1 /*
2 * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "code/debugInfoRec.hpp"
28 #include "code/icBuffer.hpp"
29 #include "code/vtableStubs.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "oops/compiledICHolder.hpp"
32 #include "prims/jvmtiRedefineClassesTrace.hpp"
33 #include "runtime/sharedRuntime.hpp"
34 #include "runtime/vframeArray.hpp"
35 #include "vmreg_sparc.inline.hpp"
36 #ifdef COMPILER1
37 #include "c1/c1_Runtime1.hpp"
38 #endif
39 #ifdef COMPILER2
40 #include "opto/runtime.hpp"
41 #endif
42 #ifdef SHARK
43 #include "compiler/compileBroker.hpp"
44 #include "shark/sharkCompiler.hpp"
45 #endif
46
47 #define __ masm->
48
49
50 class RegisterSaver {
51
52 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
53 // The Oregs are problematic. In the 32bit build the compiler can
54 // have O registers live with 64 bit quantities. A window save will
55 // cut the heads off of the registers. We have to do a very extensive
56 // stack dance to save and restore these properly.
57
58 // Note that the Oregs problem only exists if we block at either a polling
59 // page exception a compiled code safepoint that was not originally a call
60 // or deoptimize following one of these kinds of safepoints.
61
62 // Lots of registers to save. For all builds, a window save will preserve
63 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
64 // builds a window-save will preserve the %o registers. In the LION build
65 // we need to save the 64-bit %o registers which requires we save them
66 // before the window-save (as then they become %i registers and get their
67 // heads chopped off on interrupt). We have to save some %g registers here
68 // as well.
69 enum {
70 // This frame's save area. Includes extra space for the native call:
71 // vararg's layout space and the like. Briefly holds the caller's
72 // register save area.
73 call_args_area = frame::register_save_words_sp_offset +
74 frame::memory_parameter_word_sp_offset*wordSize,
75 // Make sure save locations are always 8 byte aligned.
76 // can't use round_to because it doesn't produce compile time constant
77 start_of_extra_save_area = ((call_args_area + 7) & ~7),
78 g1_offset = start_of_extra_save_area, // g-regs needing saving
79 g3_offset = g1_offset+8,
80 g4_offset = g3_offset+8,
81 g5_offset = g4_offset+8,
82 o0_offset = g5_offset+8,
83 o1_offset = o0_offset+8,
84 o2_offset = o1_offset+8,
85 o3_offset = o2_offset+8,
86 o4_offset = o3_offset+8,
87 o5_offset = o4_offset+8,
88 start_of_flags_save_area = o5_offset+8,
89 ccr_offset = start_of_flags_save_area,
90 fsr_offset = ccr_offset + 8,
91 d00_offset = fsr_offset+8, // Start of float save area
92 register_save_size = d00_offset+8*32
93 };
94
95
96 public:
97
Oexception_offset()98 static int Oexception_offset() { return o0_offset; };
G3_offset()99 static int G3_offset() { return g3_offset; };
G5_offset()100 static int G5_offset() { return g5_offset; };
101 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
102 static void restore_live_registers(MacroAssembler* masm);
103
104 // During deoptimization only the result register need to be restored
105 // all the other values have already been extracted.
106
107 static void restore_result_registers(MacroAssembler* masm);
108 };
109
save_live_registers(MacroAssembler * masm,int additional_frame_words,int * total_frame_words)110 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
111 // Record volatile registers as callee-save values in an OopMap so their save locations will be
112 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
113 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
114 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
115 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
116 int i;
117 // Always make the frame size 16 byte aligned.
118 int frame_size = round_to(additional_frame_words + register_save_size, 16);
119 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
120 int frame_size_in_slots = frame_size / sizeof(jint);
121 // CodeBlob frame size is in words.
122 *total_frame_words = frame_size / wordSize;
123 // OopMap* map = new OopMap(*total_frame_words, 0);
124 OopMap* map = new OopMap(frame_size_in_slots, 0);
125
126 #if !defined(_LP64)
127
128 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
129 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
130 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
131 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
132 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
133 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
134 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
135 #endif /* _LP64 */
136
137 __ save(SP, -frame_size, SP);
138
139 #ifndef _LP64
140 // Reload the 64 bit Oregs. Although they are now Iregs we load them
141 // to Oregs here to avoid interrupts cutting off their heads
142
143 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
144 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
145 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
149
150 __ stx(O0, SP, o0_offset+STACK_BIAS);
151 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
152
153 __ stx(O1, SP, o1_offset+STACK_BIAS);
154
155 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
156
157 __ stx(O2, SP, o2_offset+STACK_BIAS);
158 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
159
160 __ stx(O3, SP, o3_offset+STACK_BIAS);
161 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
162
163 __ stx(O4, SP, o4_offset+STACK_BIAS);
164 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
165
166 __ stx(O5, SP, o5_offset+STACK_BIAS);
167 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
168 #endif /* _LP64 */
169
170
171 #ifdef _LP64
172 int debug_offset = 0;
173 #else
174 int debug_offset = 4;
175 #endif
176 // Save the G's
177 __ stx(G1, SP, g1_offset+STACK_BIAS);
178 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
179
180 __ stx(G3, SP, g3_offset+STACK_BIAS);
181 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
182
183 __ stx(G4, SP, g4_offset+STACK_BIAS);
184 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
185
186 __ stx(G5, SP, g5_offset+STACK_BIAS);
187 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
188
189 // This is really a waste but we'll keep things as they were for now
190 if (true) {
191 #ifndef _LP64
192 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
193 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
194 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
195 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
196 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
197 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
198 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
199 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
200 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
201 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
202 #endif /* _LP64 */
203 }
204
205
206 // Save the flags
207 __ rdccr( G5 );
208 __ stx(G5, SP, ccr_offset+STACK_BIAS);
209 __ stxfsr(SP, fsr_offset+STACK_BIAS);
210
211 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)
212 int offset = d00_offset;
213 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
214 FloatRegister f = as_FloatRegister(i);
215 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
216 // Record as callee saved both halves of double registers (2 float registers).
217 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
218 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
219 offset += sizeof(double);
220 }
221
222 // And we're done.
223
224 return map;
225 }
226
227
228 // Pop the current frame and restore all the registers that we
229 // saved.
restore_live_registers(MacroAssembler * masm)230 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
231
232 // Restore all the FP registers
233 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
234 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
235 }
236
237 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
238 __ wrccr (G1) ;
239
240 // Restore the G's
241 // Note that G2 (AKA GThread) must be saved and restored separately.
242 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
243
244 __ ldx(SP, g1_offset+STACK_BIAS, G1);
245 __ ldx(SP, g3_offset+STACK_BIAS, G3);
246 __ ldx(SP, g4_offset+STACK_BIAS, G4);
247 __ ldx(SP, g5_offset+STACK_BIAS, G5);
248
249
250 #if !defined(_LP64)
251 // Restore the 64-bit O's.
252 __ ldx(SP, o0_offset+STACK_BIAS, O0);
253 __ ldx(SP, o1_offset+STACK_BIAS, O1);
254 __ ldx(SP, o2_offset+STACK_BIAS, O2);
255 __ ldx(SP, o3_offset+STACK_BIAS, O3);
256 __ ldx(SP, o4_offset+STACK_BIAS, O4);
257 __ ldx(SP, o5_offset+STACK_BIAS, O5);
258
259 // And temporarily place them in TLS
260
261 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
262 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
263 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
264 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
265 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
266 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
267 #endif /* _LP64 */
268
269 // Restore flags
270
271 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
272
273 __ restore();
274
275 #if !defined(_LP64)
276 // Now reload the 64bit Oregs after we've restore the window.
277 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
278 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
279 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
283 #endif /* _LP64 */
284
285 }
286
287 // Pop the current frame and restore the registers that might be holding
288 // a result.
restore_result_registers(MacroAssembler * masm)289 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
290
291 #if !defined(_LP64)
292 // 32bit build returns longs in G1
293 __ ldx(SP, g1_offset+STACK_BIAS, G1);
294
295 // Retrieve the 64-bit O's.
296 __ ldx(SP, o0_offset+STACK_BIAS, O0);
297 __ ldx(SP, o1_offset+STACK_BIAS, O1);
298 // and save to TLS
299 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
300 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
301 #endif /* _LP64 */
302
303 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
304
305 __ restore();
306
307 #if !defined(_LP64)
308 // Now reload the 64bit Oregs after we've restore the window.
309 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
310 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
311 #endif /* _LP64 */
312
313 }
314
315 // Is vector's size (in bytes) bigger than a size saved by default?
316 // 8 bytes FP registers are saved by default on SPARC.
is_wide_vector(int size)317 bool SharedRuntime::is_wide_vector(int size) {
318 // Note, MaxVectorSize == 8 on SPARC.
319 assert(size <= 8, err_msg_res("%d bytes vectors are not supported", size));
320 return size > 8;
321 }
322
323 // The java_calling_convention describes stack locations as ideal slots on
324 // a frame with no abi restrictions. Since we must observe abi restrictions
325 // (like the placement of the register window) the slots must be biased by
326 // the following value.
reg2offset(VMReg r)327 static int reg2offset(VMReg r) {
328 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
329 }
330
reg64_to_VMRegPair(Register r)331 static VMRegPair reg64_to_VMRegPair(Register r) {
332 VMRegPair ret;
333 if (wordSize == 8) {
334 ret.set2(r->as_VMReg());
335 } else {
336 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
337 }
338 return ret;
339 }
340
341 // ---------------------------------------------------------------------------
342 // Read the array of BasicTypes from a signature, and compute where the
343 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
344 // quantities. Values less than VMRegImpl::stack0 are registers, those above
345 // refer to 4-byte stack slots. All stack slots are based off of the window
346 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
347 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
348 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
349 // integer registers. Values 64-95 are the (32-bit only) float registers.
350 // Each 32-bit quantity is given its own number, so the integer registers
351 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
352 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
353
354 // Register results are passed in O0-O5, for outgoing call arguments. To
355 // convert to incoming arguments, convert all O's to I's. The regs array
356 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
357 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
358 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
359 // passed (used as a placeholder for the other half of longs and doubles in
360 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
361 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
362 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
363 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
364 // same VMRegPair.
365
366 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
367 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
368 // units regardless of build.
369
370
371 // ---------------------------------------------------------------------------
372 // The compiled Java calling convention. The Java convention always passes
373 // 64-bit values in adjacent aligned locations (either registers or stack),
374 // floats in float registers and doubles in aligned float pairs. There is
375 // no backing varargs store for values in registers.
376 // In the 32-bit build, longs are passed on the stack (cannot be
377 // passed in I's, because longs in I's get their heads chopped off at
378 // interrupt).
java_calling_convention(const BasicType * sig_bt,VMRegPair * regs,int total_args_passed,int is_outgoing)379 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
380 VMRegPair *regs,
381 int total_args_passed,
382 int is_outgoing) {
383 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
384
385 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
386 const int flt_reg_max = 8;
387
388 int int_reg = 0;
389 int flt_reg = 0;
390 int slot = 0;
391
392 for (int i = 0; i < total_args_passed; i++) {
393 switch (sig_bt[i]) {
394 case T_INT:
395 case T_SHORT:
396 case T_CHAR:
397 case T_BYTE:
398 case T_BOOLEAN:
399 #ifndef _LP64
400 case T_OBJECT:
401 case T_ARRAY:
402 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
403 #endif // _LP64
404 if (int_reg < int_reg_max) {
405 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
406 regs[i].set1(r->as_VMReg());
407 } else {
408 regs[i].set1(VMRegImpl::stack2reg(slot++));
409 }
410 break;
411
412 #ifdef _LP64
413 case T_LONG:
414 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
415 // fall-through
416 case T_OBJECT:
417 case T_ARRAY:
418 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
419 if (int_reg < int_reg_max) {
420 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
421 regs[i].set2(r->as_VMReg());
422 } else {
423 slot = round_to(slot, 2); // align
424 regs[i].set2(VMRegImpl::stack2reg(slot));
425 slot += 2;
426 }
427 break;
428 #else
429 case T_LONG:
430 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
431 // On 32-bit SPARC put longs always on the stack to keep the pressure off
432 // integer argument registers. They should be used for oops.
433 slot = round_to(slot, 2); // align
434 regs[i].set2(VMRegImpl::stack2reg(slot));
435 slot += 2;
436 #endif
437 break;
438
439 case T_FLOAT:
440 if (flt_reg < flt_reg_max) {
441 FloatRegister r = as_FloatRegister(flt_reg++);
442 regs[i].set1(r->as_VMReg());
443 } else {
444 regs[i].set1(VMRegImpl::stack2reg(slot++));
445 }
446 break;
447
448 case T_DOUBLE:
449 assert(sig_bt[i+1] == T_VOID, "expecting half");
450 if (round_to(flt_reg, 2) + 1 < flt_reg_max) {
451 flt_reg = round_to(flt_reg, 2); // align
452 FloatRegister r = as_FloatRegister(flt_reg);
453 regs[i].set2(r->as_VMReg());
454 flt_reg += 2;
455 } else {
456 slot = round_to(slot, 2); // align
457 regs[i].set2(VMRegImpl::stack2reg(slot));
458 slot += 2;
459 }
460 break;
461
462 case T_VOID:
463 regs[i].set_bad(); // Halves of longs & doubles
464 break;
465
466 default:
467 fatal(err_msg_res("unknown basic type %d", sig_bt[i]));
468 break;
469 }
470 }
471
472 // retun the amount of stack space these arguments will need.
473 return slot;
474 }
475
476 // Helper class mostly to avoid passing masm everywhere, and handle
477 // store displacement overflow logic.
478 class AdapterGenerator {
479 MacroAssembler *masm;
480 Register Rdisp;
set_Rdisp(Register r)481 void set_Rdisp(Register r) { Rdisp = r; }
482
483 void patch_callers_callsite();
484
485 // base+st_off points to top of argument
arg_offset(const int st_off)486 int arg_offset(const int st_off) { return st_off; }
next_arg_offset(const int st_off)487 int next_arg_offset(const int st_off) {
488 return st_off - Interpreter::stackElementSize;
489 }
490
491 // Argument slot values may be loaded first into a register because
492 // they might not fit into displacement.
493 RegisterOrConstant arg_slot(const int st_off);
494 RegisterOrConstant next_arg_slot(const int st_off);
495
496 // Stores long into offset pointed to by base
497 void store_c2i_long(Register r, Register base,
498 const int st_off, bool is_stack);
499 void store_c2i_object(Register r, Register base,
500 const int st_off);
501 void store_c2i_int(Register r, Register base,
502 const int st_off);
503 void store_c2i_double(VMReg r_2,
504 VMReg r_1, Register base, const int st_off);
505 void store_c2i_float(FloatRegister f, Register base,
506 const int st_off);
507
508 public:
509 void gen_c2i_adapter(int total_args_passed,
510 // VMReg max_arg,
511 int comp_args_on_stack, // VMRegStackSlots
512 const BasicType *sig_bt,
513 const VMRegPair *regs,
514 Label& skip_fixup);
515 void gen_i2c_adapter(int total_args_passed,
516 // VMReg max_arg,
517 int comp_args_on_stack, // VMRegStackSlots
518 const BasicType *sig_bt,
519 const VMRegPair *regs);
520
AdapterGenerator(MacroAssembler * _masm)521 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
522 };
523
524
525 // Patch the callers callsite with entry to compiled code if it exists.
patch_callers_callsite()526 void AdapterGenerator::patch_callers_callsite() {
527 Label L;
528 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch);
529 __ br_null(G3_scratch, false, Assembler::pt, L);
530 __ delayed()->nop();
531 // Call into the VM to patch the caller, then jump to compiled callee
532 __ save_frame(4); // Args in compiled layout; do not blow them
533
534 // Must save all the live Gregs the list is:
535 // G1: 1st Long arg (32bit build)
536 // G2: global allocated to TLS
537 // G3: used in inline cache check (scratch)
538 // G4: 2nd Long arg (32bit build);
539 // G5: used in inline cache check (Method*)
540
541 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
542
543 #ifdef _LP64
544 // mov(s,d)
545 __ mov(G1, L1);
546 __ mov(G4, L4);
547 __ mov(G5_method, L5);
548 __ mov(G5_method, O0); // VM needs target method
549 __ mov(I7, O1); // VM needs caller's callsite
550 // Must be a leaf call...
551 // can be very far once the blob has been relocated
552 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
553 __ relocate(relocInfo::runtime_call_type);
554 __ jumpl_to(dest, O7, O7);
555 __ delayed()->mov(G2_thread, L7_thread_cache);
556 __ mov(L7_thread_cache, G2_thread);
557 __ mov(L1, G1);
558 __ mov(L4, G4);
559 __ mov(L5, G5_method);
560 #else
561 __ stx(G1, FP, -8 + STACK_BIAS);
562 __ stx(G4, FP, -16 + STACK_BIAS);
563 __ mov(G5_method, L5);
564 __ mov(G5_method, O0); // VM needs target method
565 __ mov(I7, O1); // VM needs caller's callsite
566 // Must be a leaf call...
567 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
568 __ delayed()->mov(G2_thread, L7_thread_cache);
569 __ mov(L7_thread_cache, G2_thread);
570 __ ldx(FP, -8 + STACK_BIAS, G1);
571 __ ldx(FP, -16 + STACK_BIAS, G4);
572 __ mov(L5, G5_method);
573 #endif /* _LP64 */
574
575 __ restore(); // Restore args
576 __ bind(L);
577 }
578
579
arg_slot(const int st_off)580 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) {
581 RegisterOrConstant roc(arg_offset(st_off));
582 return __ ensure_simm13_or_reg(roc, Rdisp);
583 }
584
next_arg_slot(const int st_off)585 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) {
586 RegisterOrConstant roc(next_arg_offset(st_off));
587 return __ ensure_simm13_or_reg(roc, Rdisp);
588 }
589
590
591 // Stores long into offset pointed to by base
store_c2i_long(Register r,Register base,const int st_off,bool is_stack)592 void AdapterGenerator::store_c2i_long(Register r, Register base,
593 const int st_off, bool is_stack) {
594 #ifdef _LP64
595 // In V9, longs are given 2 64-bit slots in the interpreter, but the
596 // data is passed in only 1 slot.
597 __ stx(r, base, next_arg_slot(st_off));
598 #else
599 #ifdef COMPILER2
600 // Misaligned store of 64-bit data
601 __ stw(r, base, arg_slot(st_off)); // lo bits
602 __ srlx(r, 32, r);
603 __ stw(r, base, next_arg_slot(st_off)); // hi bits
604 #else
605 if (is_stack) {
606 // Misaligned store of 64-bit data
607 __ stw(r, base, arg_slot(st_off)); // lo bits
608 __ srlx(r, 32, r);
609 __ stw(r, base, next_arg_slot(st_off)); // hi bits
610 } else {
611 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
612 __ stw(r , base, next_arg_slot(st_off)); // hi bits
613 }
614 #endif // COMPILER2
615 #endif // _LP64
616 }
617
store_c2i_object(Register r,Register base,const int st_off)618 void AdapterGenerator::store_c2i_object(Register r, Register base,
619 const int st_off) {
620 __ st_ptr (r, base, arg_slot(st_off));
621 }
622
store_c2i_int(Register r,Register base,const int st_off)623 void AdapterGenerator::store_c2i_int(Register r, Register base,
624 const int st_off) {
625 __ st (r, base, arg_slot(st_off));
626 }
627
628 // Stores into offset pointed to by base
store_c2i_double(VMReg r_2,VMReg r_1,Register base,const int st_off)629 void AdapterGenerator::store_c2i_double(VMReg r_2,
630 VMReg r_1, Register base, const int st_off) {
631 #ifdef _LP64
632 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
633 // data is passed in only 1 slot.
634 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
635 #else
636 // Need to marshal 64-bit value from misaligned Lesp loads
637 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
638 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
639 #endif
640 }
641
store_c2i_float(FloatRegister f,Register base,const int st_off)642 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
643 const int st_off) {
644 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
645 }
646
gen_c2i_adapter(int total_args_passed,int comp_args_on_stack,const BasicType * sig_bt,const VMRegPair * regs,Label & L_skip_fixup)647 void AdapterGenerator::gen_c2i_adapter(
648 int total_args_passed,
649 // VMReg max_arg,
650 int comp_args_on_stack, // VMRegStackSlots
651 const BasicType *sig_bt,
652 const VMRegPair *regs,
653 Label& L_skip_fixup) {
654
655 // Before we get into the guts of the C2I adapter, see if we should be here
656 // at all. We've come from compiled code and are attempting to jump to the
657 // interpreter, which means the caller made a static call to get here
658 // (vcalls always get a compiled target if there is one). Check for a
659 // compiled target. If there is one, we need to patch the caller's call.
660 // However we will run interpreted if we come thru here. The next pass
661 // thru the call site will run compiled. If we ran compiled here then
662 // we can (theorectically) do endless i2c->c2i->i2c transitions during
663 // deopt/uncommon trap cycles. If we always go interpreted here then
664 // we can have at most one and don't need to play any tricks to keep
665 // from endlessly growing the stack.
666 //
667 // Actually if we detected that we had an i2c->c2i transition here we
668 // ought to be able to reset the world back to the state of the interpreted
669 // call and not bother building another interpreter arg area. We don't
670 // do that at this point.
671
672 patch_callers_callsite();
673
674 __ bind(L_skip_fixup);
675
676 // Since all args are passed on the stack, total_args_passed*wordSize is the
677 // space we need. Add in varargs area needed by the interpreter. Round up
678 // to stack alignment.
679 const int arg_size = total_args_passed * Interpreter::stackElementSize;
680 const int varargs_area =
681 (frame::varargs_offset - frame::register_save_words)*wordSize;
682 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
683
684 const int bias = STACK_BIAS;
685 const int interp_arg_offset = frame::varargs_offset*wordSize +
686 (total_args_passed-1)*Interpreter::stackElementSize;
687
688 const Register base = SP;
689
690 // Make some extra space on the stack.
691 __ sub(SP, __ ensure_simm13_or_reg(extraspace, G3_scratch), SP);
692 set_Rdisp(G3_scratch);
693
694 // Write the args into the outgoing interpreter space.
695 for (int i = 0; i < total_args_passed; i++) {
696 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
697 VMReg r_1 = regs[i].first();
698 VMReg r_2 = regs[i].second();
699 if (!r_1->is_valid()) {
700 assert(!r_2->is_valid(), "");
701 continue;
702 }
703 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
704 RegisterOrConstant ld_off = reg2offset(r_1) + extraspace + bias;
705 ld_off = __ ensure_simm13_or_reg(ld_off, Rdisp);
706 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
707 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
708 else __ ldx(base, ld_off, G1_scratch);
709 }
710
711 if (r_1->is_Register()) {
712 Register r = r_1->as_Register()->after_restore();
713 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
714 store_c2i_object(r, base, st_off);
715 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
716 store_c2i_long(r, base, st_off, r_2->is_stack());
717 } else {
718 store_c2i_int(r, base, st_off);
719 }
720 } else {
721 assert(r_1->is_FloatRegister(), "");
722 if (sig_bt[i] == T_FLOAT) {
723 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
724 } else {
725 assert(sig_bt[i] == T_DOUBLE, "wrong type");
726 store_c2i_double(r_2, r_1, base, st_off);
727 }
728 }
729 }
730
731 // Load the interpreter entry point.
732 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch);
733
734 // Pass O5_savedSP as an argument to the interpreter.
735 // The interpreter will restore SP to this value before returning.
736 __ add(SP, __ ensure_simm13_or_reg(extraspace, G1), O5_savedSP);
737
738 __ mov((frame::varargs_offset)*wordSize -
739 1*Interpreter::stackElementSize+bias+BytesPerWord, G1);
740 // Jump to the interpreter just as if interpreter was doing it.
741 __ jmpl(G3_scratch, 0, G0);
742 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
743 // (really L0) is in use by the compiled frame as a generic temp. However,
744 // the interpreter does not know where its args are without some kind of
745 // arg pointer being passed in. Pass it in Gargs.
746 __ delayed()->add(SP, G1, Gargs);
747 }
748
range_check(MacroAssembler * masm,Register pc_reg,Register temp_reg,Register temp2_reg,address code_start,address code_end,Label & L_ok)749 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, Register temp2_reg,
750 address code_start, address code_end,
751 Label& L_ok) {
752 Label L_fail;
753 __ set(ExternalAddress(code_start), temp_reg);
754 __ set(pointer_delta(code_end, code_start, 1), temp2_reg);
755 __ cmp(pc_reg, temp_reg);
756 __ brx(Assembler::lessEqualUnsigned, false, Assembler::pn, L_fail);
757 __ delayed()->add(temp_reg, temp2_reg, temp_reg);
758 __ cmp(pc_reg, temp_reg);
759 __ cmp_and_brx_short(pc_reg, temp_reg, Assembler::lessUnsigned, Assembler::pt, L_ok);
760 __ bind(L_fail);
761 }
762
gen_i2c_adapter(int total_args_passed,int comp_args_on_stack,const BasicType * sig_bt,const VMRegPair * regs)763 void AdapterGenerator::gen_i2c_adapter(
764 int total_args_passed,
765 // VMReg max_arg,
766 int comp_args_on_stack, // VMRegStackSlots
767 const BasicType *sig_bt,
768 const VMRegPair *regs) {
769
770 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
771 // layout. Lesp was saved by the calling I-frame and will be restored on
772 // return. Meanwhile, outgoing arg space is all owned by the callee
773 // C-frame, so we can mangle it at will. After adjusting the frame size,
774 // hoist register arguments and repack other args according to the compiled
775 // code convention. Finally, end in a jump to the compiled code. The entry
776 // point address is the start of the buffer.
777
778 // We will only enter here from an interpreted frame and never from after
779 // passing thru a c2i. Azul allowed this but we do not. If we lose the
780 // race and use a c2i we will remain interpreted for the race loser(s).
781 // This removes all sorts of headaches on the x86 side and also eliminates
782 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
783
784 // More detail:
785 // Adapters can be frameless because they do not require the caller
786 // to perform additional cleanup work, such as correcting the stack pointer.
787 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
788 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
789 // even if a callee has modified the stack pointer.
790 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
791 // routinely repairs its caller's stack pointer (from sender_sp, which is set
792 // up via the senderSP register).
793 // In other words, if *either* the caller or callee is interpreted, we can
794 // get the stack pointer repaired after a call.
795 // This is why c2i and i2c adapters cannot be indefinitely composed.
796 // In particular, if a c2i adapter were to somehow call an i2c adapter,
797 // both caller and callee would be compiled methods, and neither would
798 // clean up the stack pointer changes performed by the two adapters.
799 // If this happens, control eventually transfers back to the compiled
800 // caller, but with an uncorrected stack, causing delayed havoc.
801
802 if (VerifyAdapterCalls &&
803 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) {
804 // So, let's test for cascading c2i/i2c adapters right now.
805 // assert(Interpreter::contains($return_addr) ||
806 // StubRoutines::contains($return_addr),
807 // "i2c adapter must return to an interpreter frame");
808 __ block_comment("verify_i2c { ");
809 Label L_ok;
810 if (Interpreter::code() != NULL)
811 range_check(masm, O7, O0, O1,
812 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
813 L_ok);
814 if (StubRoutines::code1() != NULL)
815 range_check(masm, O7, O0, O1,
816 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
817 L_ok);
818 if (StubRoutines::code2() != NULL)
819 range_check(masm, O7, O0, O1,
820 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
821 L_ok);
822 const char* msg = "i2c adapter must return to an interpreter frame";
823 __ block_comment(msg);
824 __ stop(msg);
825 __ bind(L_ok);
826 __ block_comment("} verify_i2ce ");
827 }
828
829 // As you can see from the list of inputs & outputs there are not a lot
830 // of temp registers to work with: mostly G1, G3 & G4.
831
832 // Inputs:
833 // G2_thread - TLS
834 // G5_method - Method oop
835 // G4 (Gargs) - Pointer to interpreter's args
836 // O0..O4 - free for scratch
837 // O5_savedSP - Caller's saved SP, to be restored if needed
838 // O6 - Current SP!
839 // O7 - Valid return address
840 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
841
842 // Outputs:
843 // G2_thread - TLS
844 // O0-O5 - Outgoing args in compiled layout
845 // O6 - Adjusted or restored SP
846 // O7 - Valid return address
847 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
848 // F0-F7 - more outgoing args
849
850
851 // Gargs is the incoming argument base, and also an outgoing argument.
852 __ sub(Gargs, BytesPerWord, Gargs);
853
854 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
855 // WITH O7 HOLDING A VALID RETURN PC
856 //
857 // | |
858 // : java stack :
859 // | |
860 // +--------------+ <--- start of outgoing args
861 // | receiver | |
862 // : rest of args : |---size is java-arg-words
863 // | | |
864 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
865 // | | |
866 // : unused : |---Space for max Java stack, plus stack alignment
867 // | | |
868 // +--------------+ <--- SP + 16*wordsize
869 // | |
870 // : window :
871 // | |
872 // +--------------+ <--- SP
873
874 // WE REPACK THE STACK. We use the common calling convention layout as
875 // discovered by calling SharedRuntime::calling_convention. We assume it
876 // causes an arbitrary shuffle of memory, which may require some register
877 // temps to do the shuffle. We hope for (and optimize for) the case where
878 // temps are not needed. We may have to resize the stack slightly, in case
879 // we need alignment padding (32-bit interpreter can pass longs & doubles
880 // misaligned, but the compilers expect them aligned).
881 //
882 // | |
883 // : java stack :
884 // | |
885 // +--------------+ <--- start of outgoing args
886 // | pad, align | |
887 // +--------------+ |
888 // | ints, longs, | |
889 // | floats, | |---Outgoing stack args.
890 // : doubles : | First few args in registers.
891 // | | |
892 // +--------------+ <--- SP' + 16*wordsize
893 // | |
894 // : window :
895 // | |
896 // +--------------+ <--- SP'
897
898 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
899 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
900 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
901
902 // Cut-out for having no stack args. Since up to 6 args are passed
903 // in registers, we will commonly have no stack args.
904 if (comp_args_on_stack > 0) {
905 // Convert VMReg stack slots to words.
906 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
907 // Round up to miminum stack alignment, in wordSize
908 comp_words_on_stack = round_to(comp_words_on_stack, 2);
909 // Now compute the distance from Lesp to SP. This calculation does not
910 // include the space for total_args_passed because Lesp has not yet popped
911 // the arguments.
912 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
913 }
914
915 // Now generate the shuffle code. Pick up all register args and move the
916 // rest through G1_scratch.
917 for (int i = 0; i < total_args_passed; i++) {
918 if (sig_bt[i] == T_VOID) {
919 // Longs and doubles are passed in native word order, but misaligned
920 // in the 32-bit build.
921 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
922 continue;
923 }
924
925 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
926 // 32-bit build and aligned in the 64-bit build. Look for the obvious
927 // ldx/lddf optimizations.
928
929 // Load in argument order going down.
930 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
931 set_Rdisp(G1_scratch);
932
933 VMReg r_1 = regs[i].first();
934 VMReg r_2 = regs[i].second();
935 if (!r_1->is_valid()) {
936 assert(!r_2->is_valid(), "");
937 continue;
938 }
939 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
940 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
941 if (r_2->is_valid()) r_2 = r_1->next();
942 }
943 if (r_1->is_Register()) { // Register argument
944 Register r = r_1->as_Register()->after_restore();
945 if (!r_2->is_valid()) {
946 __ ld(Gargs, arg_slot(ld_off), r);
947 } else {
948 #ifdef _LP64
949 // In V9, longs are given 2 64-bit slots in the interpreter, but the
950 // data is passed in only 1 slot.
951 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ?
952 next_arg_slot(ld_off) : arg_slot(ld_off);
953 __ ldx(Gargs, slot, r);
954 #else
955 fatal("longs should be on stack");
956 #endif
957 }
958 } else {
959 assert(r_1->is_FloatRegister(), "");
960 if (!r_2->is_valid()) {
961 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
962 } else {
963 #ifdef _LP64
964 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
965 // data is passed in only 1 slot. This code also handles longs that
966 // are passed on the stack, but need a stack-to-stack move through a
967 // spare float register.
968 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
969 next_arg_slot(ld_off) : arg_slot(ld_off);
970 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
971 #else
972 // Need to marshal 64-bit value from misaligned Lesp loads
973 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
974 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
975 #endif
976 }
977 }
978 // Was the argument really intended to be on the stack, but was loaded
979 // into F8/F9?
980 if (regs[i].first()->is_stack()) {
981 assert(r_1->as_FloatRegister() == F8, "fix this code");
982 // Convert stack slot to an SP offset
983 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
984 // Store down the shuffled stack word. Target address _is_ aligned.
985 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp);
986 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
987 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);
988 }
989 }
990
991 // Jump to the compiled code just as if compiled code was doing it.
992 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3);
993
994 // 6243940 We might end up in handle_wrong_method if
995 // the callee is deoptimized as we race thru here. If that
996 // happens we don't want to take a safepoint because the
997 // caller frame will look interpreted and arguments are now
998 // "compiled" so it is much better to make this transition
999 // invisible to the stack walking code. Unfortunately if
1000 // we try and find the callee by normal means a safepoint
1001 // is possible. So we stash the desired callee in the thread
1002 // and the vm will find there should this case occur.
1003 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
1004 __ st_ptr(G5_method, callee_target_addr);
1005 __ jmpl(G3, 0, G0);
1006 __ delayed()->nop();
1007 }
1008
1009 // ---------------------------------------------------------------
generate_i2c2i_adapters(MacroAssembler * masm,int total_args_passed,int comp_args_on_stack,const BasicType * sig_bt,const VMRegPair * regs,AdapterFingerPrint * fingerprint)1010 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
1011 int total_args_passed,
1012 // VMReg max_arg,
1013 int comp_args_on_stack, // VMRegStackSlots
1014 const BasicType *sig_bt,
1015 const VMRegPair *regs,
1016 AdapterFingerPrint* fingerprint) {
1017 address i2c_entry = __ pc();
1018
1019 AdapterGenerator agen(masm);
1020
1021 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
1022
1023
1024 // -------------------------------------------------------------------------
1025 // Generate a C2I adapter. On entry we know G5 holds the Method*. The
1026 // args start out packed in the compiled layout. They need to be unpacked
1027 // into the interpreter layout. This will almost always require some stack
1028 // space. We grow the current (compiled) stack, then repack the args. We
1029 // finally end in a jump to the generic interpreter entry point. On exit
1030 // from the interpreter, the interpreter will restore our SP (lest the
1031 // compiled code, which relys solely on SP and not FP, get sick).
1032
1033 address c2i_unverified_entry = __ pc();
1034 Label L_skip_fixup;
1035 {
1036 Register R_temp = G1; // another scratch register
1037
1038 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1039
1040 __ verify_oop(O0);
1041 __ load_klass(O0, G3_scratch);
1042
1043 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp);
1044 __ cmp(G3_scratch, R_temp);
1045
1046 Label ok, ok2;
1047 __ brx(Assembler::equal, false, Assembler::pt, ok);
1048 __ delayed()->ld_ptr(G5_method, CompiledICHolder::holder_metadata_offset(), G5_method);
1049 __ jump_to(ic_miss, G3_scratch);
1050 __ delayed()->nop();
1051
1052 __ bind(ok);
1053 // Method might have been compiled since the call site was patched to
1054 // interpreted if that is the case treat it as a miss so we can get
1055 // the call site corrected.
1056 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch);
1057 __ bind(ok2);
1058 __ br_null(G3_scratch, false, Assembler::pt, L_skip_fixup);
1059 __ delayed()->nop();
1060 __ jump_to(ic_miss, G3_scratch);
1061 __ delayed()->nop();
1062
1063 }
1064
1065 address c2i_entry = __ pc();
1066
1067 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, L_skip_fixup);
1068
1069 __ flush();
1070 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
1071
1072 }
1073
1074 // Helper function for native calling conventions
int_stk_helper(int i)1075 static VMReg int_stk_helper( int i ) {
1076 // Bias any stack based VMReg we get by ignoring the window area
1077 // but not the register parameter save area.
1078 //
1079 // This is strange for the following reasons. We'd normally expect
1080 // the calling convention to return an VMReg for a stack slot
1081 // completely ignoring any abi reserved area. C2 thinks of that
1082 // abi area as only out_preserve_stack_slots. This does not include
1083 // the area allocated by the C abi to store down integer arguments
1084 // because the java calling convention does not use it. So
1085 // since c2 assumes that there are only out_preserve_stack_slots
1086 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
1087 // location the c calling convention must add in this bias amount
1088 // to make up for the fact that the out_preserve_stack_slots is
1089 // insufficient for C calls. What a mess. I sure hope those 6
1090 // stack words were worth it on every java call!
1091
1092 // Another way of cleaning this up would be for out_preserve_stack_slots
1093 // to take a parameter to say whether it was C or java calling conventions.
1094 // Then things might look a little better (but not much).
1095
1096 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
1097 if( mem_parm_offset < 0 ) {
1098 return as_oRegister(i)->as_VMReg();
1099 } else {
1100 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
1101 // Now return a biased offset that will be correct when out_preserve_slots is added back in
1102 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
1103 }
1104 }
1105
1106
c_calling_convention(const BasicType * sig_bt,VMRegPair * regs,VMRegPair * regs2,int total_args_passed)1107 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1108 VMRegPair *regs,
1109 VMRegPair *regs2,
1110 int total_args_passed) {
1111 assert(regs2 == NULL, "not needed on sparc");
1112
1113 // Return the number of VMReg stack_slots needed for the args.
1114 // This value does not include an abi space (like register window
1115 // save area).
1116
1117 // The native convention is V8 if !LP64
1118 // The LP64 convention is the V9 convention which is slightly more sane.
1119
1120 // We return the amount of VMReg stack slots we need to reserve for all
1121 // the arguments NOT counting out_preserve_stack_slots. Since we always
1122 // have space for storing at least 6 registers to memory we start with that.
1123 // See int_stk_helper for a further discussion.
1124 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
1125
1126 #ifdef _LP64
1127 // V9 convention: All things "as-if" on double-wide stack slots.
1128 // Hoist any int/ptr/long's in the first 6 to int regs.
1129 // Hoist any flt/dbl's in the first 16 dbl regs.
1130 int j = 0; // Count of actual args, not HALVES
1131 VMRegPair param_array_reg; // location of the argument in the parameter array
1132 for (int i = 0; i < total_args_passed; i++, j++) {
1133 param_array_reg.set_bad();
1134 switch (sig_bt[i]) {
1135 case T_BOOLEAN:
1136 case T_BYTE:
1137 case T_CHAR:
1138 case T_INT:
1139 case T_SHORT:
1140 regs[i].set1(int_stk_helper(j));
1141 break;
1142 case T_LONG:
1143 assert(sig_bt[i+1] == T_VOID, "expecting half");
1144 case T_ADDRESS: // raw pointers, like current thread, for VM calls
1145 case T_ARRAY:
1146 case T_OBJECT:
1147 case T_METADATA:
1148 regs[i].set2(int_stk_helper(j));
1149 break;
1150 case T_FLOAT:
1151 // Per SPARC Compliance Definition 2.4.1, page 3P-12 available here
1152 // http://www.sparc.org/wp-content/uploads/2014/01/SCD.2.4.1.pdf.gz
1153 //
1154 // "When a callee prototype exists, and does not indicate variable arguments,
1155 // floating-point values assigned to locations %sp+BIAS+128 through %sp+BIAS+248
1156 // will be promoted to floating-point registers"
1157 //
1158 // By "promoted" it means that the argument is located in two places, an unused
1159 // spill slot in the "parameter array" (starts at %sp+BIAS+128), and a live
1160 // float register. In most cases, there are 6 or fewer arguments of any type,
1161 // and the standard parameter array slots (%sp+BIAS+128 to %sp+BIAS+176 exclusive)
1162 // serve as shadow slots. Per the spec floating point registers %d6 to %d16
1163 // require slots beyond that (up to %sp+BIAS+248).
1164 //
1165 {
1166 // V9ism: floats go in ODD registers and stack slots
1167 int float_index = 1 + (j << 1);
1168 param_array_reg.set1(VMRegImpl::stack2reg(float_index));
1169 if (j < 16) {
1170 regs[i].set1(as_FloatRegister(float_index)->as_VMReg());
1171 } else {
1172 regs[i] = param_array_reg;
1173 }
1174 }
1175 break;
1176 case T_DOUBLE:
1177 {
1178 assert(sig_bt[i + 1] == T_VOID, "expecting half");
1179 // V9ism: doubles go in EVEN/ODD regs and stack slots
1180 int double_index = (j << 1);
1181 param_array_reg.set2(VMRegImpl::stack2reg(double_index));
1182 if (j < 16) {
1183 regs[i].set2(as_FloatRegister(double_index)->as_VMReg());
1184 } else {
1185 // V9ism: doubles go in EVEN/ODD stack slots
1186 regs[i] = param_array_reg;
1187 }
1188 }
1189 break;
1190 case T_VOID:
1191 regs[i].set_bad();
1192 j--;
1193 break; // Do not count HALVES
1194 default:
1195 ShouldNotReachHere();
1196 }
1197 // Keep track of the deepest parameter array slot.
1198 if (!param_array_reg.first()->is_valid()) {
1199 param_array_reg = regs[i];
1200 }
1201 if (param_array_reg.first()->is_stack()) {
1202 int off = param_array_reg.first()->reg2stack();
1203 if (off > max_stack_slots) max_stack_slots = off;
1204 }
1205 if (param_array_reg.second()->is_stack()) {
1206 int off = param_array_reg.second()->reg2stack();
1207 if (off > max_stack_slots) max_stack_slots = off;
1208 }
1209 }
1210
1211 #else // _LP64
1212 // V8 convention: first 6 things in O-regs, rest on stack.
1213 // Alignment is willy-nilly.
1214 for (int i = 0; i < total_args_passed; i++) {
1215 switch (sig_bt[i]) {
1216 case T_ADDRESS: // raw pointers, like current thread, for VM calls
1217 case T_ARRAY:
1218 case T_BOOLEAN:
1219 case T_BYTE:
1220 case T_CHAR:
1221 case T_FLOAT:
1222 case T_INT:
1223 case T_OBJECT:
1224 case T_METADATA:
1225 case T_SHORT:
1226 regs[i].set1(int_stk_helper(i));
1227 break;
1228 case T_DOUBLE:
1229 case T_LONG:
1230 assert(sig_bt[i + 1] == T_VOID, "expecting half");
1231 regs[i].set_pair(int_stk_helper(i + 1), int_stk_helper(i));
1232 break;
1233 case T_VOID: regs[i].set_bad(); break;
1234 default:
1235 ShouldNotReachHere();
1236 }
1237 if (regs[i].first()->is_stack()) {
1238 int off = regs[i].first()->reg2stack();
1239 if (off > max_stack_slots) max_stack_slots = off;
1240 }
1241 if (regs[i].second()->is_stack()) {
1242 int off = regs[i].second()->reg2stack();
1243 if (off > max_stack_slots) max_stack_slots = off;
1244 }
1245 }
1246 #endif // _LP64
1247
1248 return round_to(max_stack_slots + 1, 2);
1249
1250 }
1251
1252
1253 // ---------------------------------------------------------------------------
save_native_result(MacroAssembler * masm,BasicType ret_type,int frame_slots)1254 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1255 switch (ret_type) {
1256 case T_FLOAT:
1257 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
1258 break;
1259 case T_DOUBLE:
1260 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
1261 break;
1262 }
1263 }
1264
restore_native_result(MacroAssembler * masm,BasicType ret_type,int frame_slots)1265 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1266 switch (ret_type) {
1267 case T_FLOAT:
1268 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
1269 break;
1270 case T_DOUBLE:
1271 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
1272 break;
1273 }
1274 }
1275
1276 // Check and forward and pending exception. Thread is stored in
1277 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
1278 // is no exception handler. We merely pop this frame off and throw the
1279 // exception in the caller's frame.
check_forward_pending_exception(MacroAssembler * masm,Register Rex_oop)1280 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
1281 Label L;
1282 __ br_null(Rex_oop, false, Assembler::pt, L);
1283 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
1284 // Since this is a native call, we *know* the proper exception handler
1285 // without calling into the VM: it's the empty function. Just pop this
1286 // frame and then jump to forward_exception_entry; O7 will contain the
1287 // native caller's return PC.
1288 AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
1289 __ jump_to(exception_entry, G3_scratch);
1290 __ delayed()->restore(); // Pop this frame off.
1291 __ bind(L);
1292 }
1293
1294 // A simple move of integer like type
simple_move32(MacroAssembler * masm,VMRegPair src,VMRegPair dst)1295 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1296 if (src.first()->is_stack()) {
1297 if (dst.first()->is_stack()) {
1298 // stack to stack
1299 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1300 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1301 } else {
1302 // stack to reg
1303 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1304 }
1305 } else if (dst.first()->is_stack()) {
1306 // reg to stack
1307 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1308 } else {
1309 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1310 }
1311 }
1312
1313 // On 64 bit we will store integer like items to the stack as
1314 // 64 bits items (sparc abi) even though java would only store
1315 // 32bits for a parameter. On 32bit it will simply be 32 bits
1316 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
move32_64(MacroAssembler * masm,VMRegPair src,VMRegPair dst)1317 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1318 if (src.first()->is_stack()) {
1319 if (dst.first()->is_stack()) {
1320 // stack to stack
1321 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1322 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1323 } else {
1324 // stack to reg
1325 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1326 }
1327 } else if (dst.first()->is_stack()) {
1328 // reg to stack
1329 // Some compilers (gcc) expect a clean 32 bit value on function entry
1330 __ signx(src.first()->as_Register(), L5);
1331 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1332 } else {
1333 // Some compilers (gcc) expect a clean 32 bit value on function entry
1334 __ signx(src.first()->as_Register(), dst.first()->as_Register());
1335 }
1336 }
1337
1338
move_ptr(MacroAssembler * masm,VMRegPair src,VMRegPair dst)1339 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1340 if (src.first()->is_stack()) {
1341 if (dst.first()->is_stack()) {
1342 // stack to stack
1343 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1344 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1345 } else {
1346 // stack to reg
1347 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1348 }
1349 } else if (dst.first()->is_stack()) {
1350 // reg to stack
1351 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1352 } else {
1353 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1354 }
1355 }
1356
1357
1358 // An oop arg. Must pass a handle not the oop itself
object_move(MacroAssembler * masm,OopMap * map,int oop_handle_offset,int framesize_in_slots,VMRegPair src,VMRegPair dst,bool is_receiver,int * receiver_offset)1359 static void object_move(MacroAssembler* masm,
1360 OopMap* map,
1361 int oop_handle_offset,
1362 int framesize_in_slots,
1363 VMRegPair src,
1364 VMRegPair dst,
1365 bool is_receiver,
1366 int* receiver_offset) {
1367
1368 // must pass a handle. First figure out the location we use as a handle
1369
1370 if (src.first()->is_stack()) {
1371 // Oop is already on the stack
1372 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
1373 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
1374 __ ld_ptr(rHandle, 0, L4);
1375 #ifdef _LP64
1376 __ movr( Assembler::rc_z, L4, G0, rHandle );
1377 #else
1378 __ tst( L4 );
1379 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1380 #endif
1381 if (dst.first()->is_stack()) {
1382 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1383 }
1384 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1385 if (is_receiver) {
1386 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1387 }
1388 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1389 } else {
1390 // Oop is in an input register pass we must flush it to the stack
1391 const Register rOop = src.first()->as_Register();
1392 const Register rHandle = L5;
1393 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
1394 int offset = oop_slot * VMRegImpl::stack_slot_size;
1395 __ st_ptr(rOop, SP, offset + STACK_BIAS);
1396 if (is_receiver) {
1397 *receiver_offset = offset;
1398 }
1399 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1400 __ add(SP, offset + STACK_BIAS, rHandle);
1401 #ifdef _LP64
1402 __ movr( Assembler::rc_z, rOop, G0, rHandle );
1403 #else
1404 __ tst( rOop );
1405 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1406 #endif
1407
1408 if (dst.first()->is_stack()) {
1409 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1410 } else {
1411 __ mov(rHandle, dst.first()->as_Register());
1412 }
1413 }
1414 }
1415
1416 // A float arg may have to do float reg int reg conversion
float_move(MacroAssembler * masm,VMRegPair src,VMRegPair dst)1417 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1418 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1419
1420 if (src.first()->is_stack()) {
1421 if (dst.first()->is_stack()) {
1422 // stack to stack the easiest of the bunch
1423 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1424 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1425 } else {
1426 // stack to reg
1427 if (dst.first()->is_Register()) {
1428 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1429 } else {
1430 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1431 }
1432 }
1433 } else if (dst.first()->is_stack()) {
1434 // reg to stack
1435 if (src.first()->is_Register()) {
1436 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1437 } else {
1438 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1439 }
1440 } else {
1441 // reg to reg
1442 if (src.first()->is_Register()) {
1443 if (dst.first()->is_Register()) {
1444 // gpr -> gpr
1445 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1446 } else {
1447 // gpr -> fpr
1448 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
1449 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
1450 }
1451 } else if (dst.first()->is_Register()) {
1452 // fpr -> gpr
1453 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
1454 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
1455 } else {
1456 // fpr -> fpr
1457 // In theory these overlap but the ordering is such that this is likely a nop
1458 if ( src.first() != dst.first()) {
1459 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1460 }
1461 }
1462 }
1463 }
1464
split_long_move(MacroAssembler * masm,VMRegPair src,VMRegPair dst)1465 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1466 VMRegPair src_lo(src.first());
1467 VMRegPair src_hi(src.second());
1468 VMRegPair dst_lo(dst.first());
1469 VMRegPair dst_hi(dst.second());
1470 simple_move32(masm, src_lo, dst_lo);
1471 simple_move32(masm, src_hi, dst_hi);
1472 }
1473
1474 // A long move
long_move(MacroAssembler * masm,VMRegPair src,VMRegPair dst)1475 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1476
1477 // Do the simple ones here else do two int moves
1478 if (src.is_single_phys_reg() ) {
1479 if (dst.is_single_phys_reg()) {
1480 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1481 } else {
1482 // split src into two separate registers
1483 // Remember hi means hi address or lsw on sparc
1484 // Move msw to lsw
1485 if (dst.second()->is_reg()) {
1486 // MSW -> MSW
1487 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
1488 // Now LSW -> LSW
1489 // this will only move lo -> lo and ignore hi
1490 VMRegPair split(dst.second());
1491 simple_move32(masm, src, split);
1492 } else {
1493 VMRegPair split(src.first(), L4->as_VMReg());
1494 // MSW -> MSW (lo ie. first word)
1495 __ srax(src.first()->as_Register(), 32, L4);
1496 split_long_move(masm, split, dst);
1497 }
1498 }
1499 } else if (dst.is_single_phys_reg()) {
1500 if (src.is_adjacent_aligned_on_stack(2)) {
1501 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1502 } else {
1503 // dst is a single reg.
1504 // Remember lo is low address not msb for stack slots
1505 // and lo is the "real" register for registers
1506 // src is
1507
1508 VMRegPair split;
1509
1510 if (src.first()->is_reg()) {
1511 // src.lo (msw) is a reg, src.hi is stk/reg
1512 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
1513 split.set_pair(dst.first(), src.first());
1514 } else {
1515 // msw is stack move to L5
1516 // lsw is stack move to dst.lo (real reg)
1517 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
1518 split.set_pair(dst.first(), L5->as_VMReg());
1519 }
1520
1521 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
1522 // msw -> src.lo/L5, lsw -> dst.lo
1523 split_long_move(masm, src, split);
1524
1525 // So dst now has the low order correct position the
1526 // msw half
1527 __ sllx(split.first()->as_Register(), 32, L5);
1528
1529 const Register d = dst.first()->as_Register();
1530 __ or3(L5, d, d);
1531 }
1532 } else {
1533 // For LP64 we can probably do better.
1534 split_long_move(masm, src, dst);
1535 }
1536 }
1537
1538 // A double move
double_move(MacroAssembler * masm,VMRegPair src,VMRegPair dst)1539 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1540
1541 // The painful thing here is that like long_move a VMRegPair might be
1542 // 1: a single physical register
1543 // 2: two physical registers (v8)
1544 // 3: a physical reg [lo] and a stack slot [hi] (v8)
1545 // 4: two stack slots
1546
1547 // Since src is always a java calling convention we know that the src pair
1548 // is always either all registers or all stack (and aligned?)
1549
1550 // in a register [lo] and a stack slot [hi]
1551 if (src.first()->is_stack()) {
1552 if (dst.first()->is_stack()) {
1553 // stack to stack the easiest of the bunch
1554 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
1555 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1556 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1557 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1558 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1559 } else {
1560 // stack to reg
1561 if (dst.second()->is_stack()) {
1562 // stack -> reg, stack -> stack
1563 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1564 if (dst.first()->is_Register()) {
1565 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1566 } else {
1567 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1568 }
1569 // This was missing. (very rare case)
1570 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1571 } else {
1572 // stack -> reg
1573 // Eventually optimize for alignment QQQ
1574 if (dst.first()->is_Register()) {
1575 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1576 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
1577 } else {
1578 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1579 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
1580 }
1581 }
1582 }
1583 } else if (dst.first()->is_stack()) {
1584 // reg to stack
1585 if (src.first()->is_Register()) {
1586 // Eventually optimize for alignment QQQ
1587 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1588 if (src.second()->is_stack()) {
1589 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1590 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1591 } else {
1592 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
1593 }
1594 } else {
1595 // fpr to stack
1596 if (src.second()->is_stack()) {
1597 ShouldNotReachHere();
1598 } else {
1599 // Is the stack aligned?
1600 if (reg2offset(dst.first()) & 0x7) {
1601 // No do as pairs
1602 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1603 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
1604 } else {
1605 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1606 }
1607 }
1608 }
1609 } else {
1610 // reg to reg
1611 if (src.first()->is_Register()) {
1612 if (dst.first()->is_Register()) {
1613 // gpr -> gpr
1614 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1615 __ mov(src.second()->as_Register(), dst.second()->as_Register());
1616 } else {
1617 // gpr -> fpr
1618 // ought to be able to do a single store
1619 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
1620 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
1621 // ought to be able to do a single load
1622 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
1623 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
1624 }
1625 } else if (dst.first()->is_Register()) {
1626 // fpr -> gpr
1627 // ought to be able to do a single store
1628 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
1629 // ought to be able to do a single load
1630 // REMEMBER first() is low address not LSB
1631 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
1632 if (dst.second()->is_Register()) {
1633 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
1634 } else {
1635 __ ld(FP, -4 + STACK_BIAS, L4);
1636 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1637 }
1638 } else {
1639 // fpr -> fpr
1640 // In theory these overlap but the ordering is such that this is likely a nop
1641 if ( src.first() != dst.first()) {
1642 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1643 }
1644 }
1645 }
1646 }
1647
1648 // Creates an inner frame if one hasn't already been created, and
1649 // saves a copy of the thread in L7_thread_cache
create_inner_frame(MacroAssembler * masm,bool * already_created)1650 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
1651 if (!*already_created) {
1652 __ save_frame(0);
1653 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
1654 // Don't use save_thread because it smashes G2 and we merely want to save a
1655 // copy
1656 __ mov(G2_thread, L7_thread_cache);
1657 *already_created = true;
1658 }
1659 }
1660
1661
save_or_restore_arguments(MacroAssembler * masm,const int stack_slots,const int total_in_args,const int arg_save_area,OopMap * map,VMRegPair * in_regs,BasicType * in_sig_bt)1662 static void save_or_restore_arguments(MacroAssembler* masm,
1663 const int stack_slots,
1664 const int total_in_args,
1665 const int arg_save_area,
1666 OopMap* map,
1667 VMRegPair* in_regs,
1668 BasicType* in_sig_bt) {
1669 // if map is non-NULL then the code should store the values,
1670 // otherwise it should load them.
1671 if (map != NULL) {
1672 // Fill in the map
1673 for (int i = 0; i < total_in_args; i++) {
1674 if (in_sig_bt[i] == T_ARRAY) {
1675 if (in_regs[i].first()->is_stack()) {
1676 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1677 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
1678 } else if (in_regs[i].first()->is_Register()) {
1679 map->set_oop(in_regs[i].first());
1680 } else {
1681 ShouldNotReachHere();
1682 }
1683 }
1684 }
1685 }
1686
1687 // Save or restore double word values
1688 int handle_index = 0;
1689 for (int i = 0; i < total_in_args; i++) {
1690 int slot = handle_index + arg_save_area;
1691 int offset = slot * VMRegImpl::stack_slot_size;
1692 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) {
1693 const Register reg = in_regs[i].first()->as_Register();
1694 if (reg->is_global()) {
1695 handle_index += 2;
1696 assert(handle_index <= stack_slots, "overflow");
1697 if (map != NULL) {
1698 __ stx(reg, SP, offset + STACK_BIAS);
1699 } else {
1700 __ ldx(SP, offset + STACK_BIAS, reg);
1701 }
1702 }
1703 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) {
1704 handle_index += 2;
1705 assert(handle_index <= stack_slots, "overflow");
1706 if (map != NULL) {
1707 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS);
1708 } else {
1709 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister());
1710 }
1711 }
1712 }
1713 // Save floats
1714 for (int i = 0; i < total_in_args; i++) {
1715 int slot = handle_index + arg_save_area;
1716 int offset = slot * VMRegImpl::stack_slot_size;
1717 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) {
1718 handle_index++;
1719 assert(handle_index <= stack_slots, "overflow");
1720 if (map != NULL) {
1721 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS);
1722 } else {
1723 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister());
1724 }
1725 }
1726 }
1727
1728 }
1729
1730
1731 // Check GC_locker::needs_gc and enter the runtime if it's true. This
1732 // keeps a new JNI critical region from starting until a GC has been
1733 // forced. Save down any oops in registers and describe them in an
1734 // OopMap.
check_needs_gc_for_critical_native(MacroAssembler * masm,const int stack_slots,const int total_in_args,const int arg_save_area,OopMapSet * oop_maps,VMRegPair * in_regs,BasicType * in_sig_bt)1735 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
1736 const int stack_slots,
1737 const int total_in_args,
1738 const int arg_save_area,
1739 OopMapSet* oop_maps,
1740 VMRegPair* in_regs,
1741 BasicType* in_sig_bt) {
1742 __ block_comment("check GC_locker::needs_gc");
1743 Label cont;
1744 AddressLiteral sync_state(GC_locker::needs_gc_address());
1745 __ load_bool_contents(sync_state, G3_scratch);
1746 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont);
1747 __ delayed()->nop();
1748
1749 // Save down any values that are live in registers and call into the
1750 // runtime to halt for a GC
1751 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1752 save_or_restore_arguments(masm, stack_slots, total_in_args,
1753 arg_save_area, map, in_regs, in_sig_bt);
1754
1755 __ mov(G2_thread, L7_thread_cache);
1756
1757 __ set_last_Java_frame(SP, noreg);
1758
1759 __ block_comment("block_for_jni_critical");
1760 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type);
1761 __ delayed()->mov(L7_thread_cache, O0);
1762 oop_maps->add_gc_map( __ offset(), map);
1763
1764 __ restore_thread(L7_thread_cache); // restore G2_thread
1765 __ reset_last_Java_frame();
1766
1767 // Reload all the register arguments
1768 save_or_restore_arguments(masm, stack_slots, total_in_args,
1769 arg_save_area, NULL, in_regs, in_sig_bt);
1770
1771 __ bind(cont);
1772 #ifdef ASSERT
1773 if (StressCriticalJNINatives) {
1774 // Stress register saving
1775 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1776 save_or_restore_arguments(masm, stack_slots, total_in_args,
1777 arg_save_area, map, in_regs, in_sig_bt);
1778 // Destroy argument registers
1779 for (int i = 0; i < total_in_args; i++) {
1780 if (in_regs[i].first()->is_Register()) {
1781 const Register reg = in_regs[i].first()->as_Register();
1782 if (reg->is_global()) {
1783 __ mov(G0, reg);
1784 }
1785 } else if (in_regs[i].first()->is_FloatRegister()) {
1786 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister());
1787 }
1788 }
1789
1790 save_or_restore_arguments(masm, stack_slots, total_in_args,
1791 arg_save_area, NULL, in_regs, in_sig_bt);
1792 }
1793 #endif
1794 }
1795
1796 // Unpack an array argument into a pointer to the body and the length
1797 // if the array is non-null, otherwise pass 0 for both.
unpack_array_argument(MacroAssembler * masm,VMRegPair reg,BasicType in_elem_type,VMRegPair body_arg,VMRegPair length_arg)1798 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
1799 // Pass the length, ptr pair
1800 Label is_null, done;
1801 if (reg.first()->is_stack()) {
1802 VMRegPair tmp = reg64_to_VMRegPair(L2);
1803 // Load the arg up from the stack
1804 move_ptr(masm, reg, tmp);
1805 reg = tmp;
1806 }
1807 __ cmp(reg.first()->as_Register(), G0);
1808 __ brx(Assembler::equal, false, Assembler::pt, is_null);
1809 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4);
1810 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg);
1811 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4);
1812 move32_64(masm, reg64_to_VMRegPair(L4), length_arg);
1813 __ ba_short(done);
1814 __ bind(is_null);
1815 // Pass zeros
1816 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg);
1817 move32_64(masm, reg64_to_VMRegPair(G0), length_arg);
1818 __ bind(done);
1819 }
1820
verify_oop_args(MacroAssembler * masm,methodHandle method,const BasicType * sig_bt,const VMRegPair * regs)1821 static void verify_oop_args(MacroAssembler* masm,
1822 methodHandle method,
1823 const BasicType* sig_bt,
1824 const VMRegPair* regs) {
1825 Register temp_reg = G5_method; // not part of any compiled calling seq
1826 if (VerifyOops) {
1827 for (int i = 0; i < method->size_of_parameters(); i++) {
1828 if (sig_bt[i] == T_OBJECT ||
1829 sig_bt[i] == T_ARRAY) {
1830 VMReg r = regs[i].first();
1831 assert(r->is_valid(), "bad oop arg");
1832 if (r->is_stack()) {
1833 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
1834 ld_off = __ ensure_simm13_or_reg(ld_off, temp_reg);
1835 __ ld_ptr(SP, ld_off, temp_reg);
1836 __ verify_oop(temp_reg);
1837 } else {
1838 __ verify_oop(r->as_Register());
1839 }
1840 }
1841 }
1842 }
1843 }
1844
gen_special_dispatch(MacroAssembler * masm,methodHandle method,const BasicType * sig_bt,const VMRegPair * regs)1845 static void gen_special_dispatch(MacroAssembler* masm,
1846 methodHandle method,
1847 const BasicType* sig_bt,
1848 const VMRegPair* regs) {
1849 verify_oop_args(masm, method, sig_bt, regs);
1850 vmIntrinsics::ID iid = method->intrinsic_id();
1851
1852 // Now write the args into the outgoing interpreter space
1853 bool has_receiver = false;
1854 Register receiver_reg = noreg;
1855 int member_arg_pos = -1;
1856 Register member_reg = noreg;
1857 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
1858 if (ref_kind != 0) {
1859 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
1860 member_reg = G5_method; // known to be free at this point
1861 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
1862 } else if (iid == vmIntrinsics::_invokeBasic) {
1863 has_receiver = true;
1864 } else {
1865 fatal(err_msg_res("unexpected intrinsic id %d", iid));
1866 }
1867
1868 if (member_reg != noreg) {
1869 // Load the member_arg into register, if necessary.
1870 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
1871 VMReg r = regs[member_arg_pos].first();
1872 if (r->is_stack()) {
1873 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
1874 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg);
1875 __ ld_ptr(SP, ld_off, member_reg);
1876 } else {
1877 // no data motion is needed
1878 member_reg = r->as_Register();
1879 }
1880 }
1881
1882 if (has_receiver) {
1883 // Make sure the receiver is loaded into a register.
1884 assert(method->size_of_parameters() > 0, "oob");
1885 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
1886 VMReg r = regs[0].first();
1887 assert(r->is_valid(), "bad receiver arg");
1888 if (r->is_stack()) {
1889 // Porting note: This assumes that compiled calling conventions always
1890 // pass the receiver oop in a register. If this is not true on some
1891 // platform, pick a temp and load the receiver from stack.
1892 fatal("receiver always in a register");
1893 receiver_reg = G3_scratch; // known to be free at this point
1894 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
1895 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg);
1896 __ ld_ptr(SP, ld_off, receiver_reg);
1897 } else {
1898 // no data motion is needed
1899 receiver_reg = r->as_Register();
1900 }
1901 }
1902
1903 // Figure out which address we are really jumping to:
1904 MethodHandles::generate_method_handle_dispatch(masm, iid,
1905 receiver_reg, member_reg, /*for_compiler_entry:*/ true);
1906 }
1907
1908 // ---------------------------------------------------------------------------
1909 // Generate a native wrapper for a given method. The method takes arguments
1910 // in the Java compiled code convention, marshals them to the native
1911 // convention (handlizes oops, etc), transitions to native, makes the call,
1912 // returns to java state (possibly blocking), unhandlizes any result and
1913 // returns.
1914 //
1915 // Critical native functions are a shorthand for the use of
1916 // GetPrimtiveArrayCritical and disallow the use of any other JNI
1917 // functions. The wrapper is expected to unpack the arguments before
1918 // passing them to the callee and perform checks before and after the
1919 // native call to ensure that they GC_locker
1920 // lock_critical/unlock_critical semantics are followed. Some other
1921 // parts of JNI setup are skipped like the tear down of the JNI handle
1922 // block and the check for pending exceptions it's impossible for them
1923 // to be thrown.
1924 //
1925 // They are roughly structured like this:
1926 // if (GC_locker::needs_gc())
1927 // SharedRuntime::block_for_jni_critical();
1928 // tranistion to thread_in_native
1929 // unpack arrray arguments and call native entry point
1930 // check for safepoint in progress
1931 // check if any thread suspend flags are set
1932 // call into JVM and possible unlock the JNI critical
1933 // if a GC was suppressed while in the critical native.
1934 // transition back to thread_in_Java
1935 // return to caller
1936 //
generate_native_wrapper(MacroAssembler * masm,methodHandle method,int compile_id,BasicType * in_sig_bt,VMRegPair * in_regs,BasicType ret_type)1937 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1938 methodHandle method,
1939 int compile_id,
1940 BasicType* in_sig_bt,
1941 VMRegPair* in_regs,
1942 BasicType ret_type) {
1943 if (method->is_method_handle_intrinsic()) {
1944 vmIntrinsics::ID iid = method->intrinsic_id();
1945 intptr_t start = (intptr_t)__ pc();
1946 int vep_offset = ((intptr_t)__ pc()) - start;
1947 gen_special_dispatch(masm,
1948 method,
1949 in_sig_bt,
1950 in_regs);
1951 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
1952 __ flush();
1953 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
1954 return nmethod::new_native_nmethod(method,
1955 compile_id,
1956 masm->code(),
1957 vep_offset,
1958 frame_complete,
1959 stack_slots / VMRegImpl::slots_per_word,
1960 in_ByteSize(-1),
1961 in_ByteSize(-1),
1962 (OopMapSet*)NULL);
1963 }
1964 bool is_critical_native = true;
1965 address native_func = method->critical_native_function();
1966 if (native_func == NULL) {
1967 native_func = method->native_function();
1968 is_critical_native = false;
1969 }
1970 assert(native_func != NULL, "must have function");
1971
1972 // Native nmethod wrappers never take possesion of the oop arguments.
1973 // So the caller will gc the arguments. The only thing we need an
1974 // oopMap for is if the call is static
1975 //
1976 // An OopMap for lock (and class if static), and one for the VM call itself
1977 OopMapSet *oop_maps = new OopMapSet();
1978 intptr_t start = (intptr_t)__ pc();
1979
1980 // First thing make an ic check to see if we should even be here
1981 {
1982 Label L;
1983 const Register temp_reg = G3_scratch;
1984 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1985 __ verify_oop(O0);
1986 __ load_klass(O0, temp_reg);
1987 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
1988
1989 __ jump_to(ic_miss, temp_reg);
1990 __ delayed()->nop();
1991 __ align(CodeEntryAlignment);
1992 __ bind(L);
1993 }
1994
1995 int vep_offset = ((intptr_t)__ pc()) - start;
1996
1997 #ifdef COMPILER1
1998 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
1999 // Object.hashCode can pull the hashCode from the header word
2000 // instead of doing a full VM transition once it's been computed.
2001 // Since hashCode is usually polymorphic at call sites we can't do
2002 // this optimization at the call site without a lot of work.
2003 Label slowCase;
2004 Register receiver = O0;
2005 Register result = O0;
2006 Register header = G3_scratch;
2007 Register hash = G3_scratch; // overwrite header value with hash value
2008 Register mask = G1; // to get hash field from header
2009
2010 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
2011 // We depend on hash_mask being at most 32 bits and avoid the use of
2012 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
2013 // vm: see markOop.hpp.
2014 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
2015 __ sethi(markOopDesc::hash_mask, mask);
2016 __ btst(markOopDesc::unlocked_value, header);
2017 __ br(Assembler::zero, false, Assembler::pn, slowCase);
2018 if (UseBiasedLocking) {
2019 // Check if biased and fall through to runtime if so
2020 __ delayed()->nop();
2021 __ btst(markOopDesc::biased_lock_bit_in_place, header);
2022 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
2023 }
2024 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
2025
2026 // Check for a valid (non-zero) hash code and get its value.
2027 #ifdef _LP64
2028 __ srlx(header, markOopDesc::hash_shift, hash);
2029 #else
2030 __ srl(header, markOopDesc::hash_shift, hash);
2031 #endif
2032 __ andcc(hash, mask, hash);
2033 __ br(Assembler::equal, false, Assembler::pn, slowCase);
2034 __ delayed()->nop();
2035
2036 // leaf return.
2037 __ retl();
2038 __ delayed()->mov(hash, result);
2039 __ bind(slowCase);
2040 }
2041 #endif // COMPILER1
2042
2043
2044 // We have received a description of where all the java arg are located
2045 // on entry to the wrapper. We need to convert these args to where
2046 // the jni function will expect them. To figure out where they go
2047 // we convert the java signature to a C signature by inserting
2048 // the hidden arguments as arg[0] and possibly arg[1] (static method)
2049
2050 const int total_in_args = method->size_of_parameters();
2051 int total_c_args = total_in_args;
2052 int total_save_slots = 6 * VMRegImpl::slots_per_word;
2053 if (!is_critical_native) {
2054 total_c_args += 1;
2055 if (method->is_static()) {
2056 total_c_args++;
2057 }
2058 } else {
2059 for (int i = 0; i < total_in_args; i++) {
2060 if (in_sig_bt[i] == T_ARRAY) {
2061 // These have to be saved and restored across the safepoint
2062 total_c_args++;
2063 }
2064 }
2065 }
2066
2067 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
2068 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
2069 BasicType* in_elem_bt = NULL;
2070
2071 int argc = 0;
2072 if (!is_critical_native) {
2073 out_sig_bt[argc++] = T_ADDRESS;
2074 if (method->is_static()) {
2075 out_sig_bt[argc++] = T_OBJECT;
2076 }
2077
2078 for (int i = 0; i < total_in_args ; i++ ) {
2079 out_sig_bt[argc++] = in_sig_bt[i];
2080 }
2081 } else {
2082 Thread* THREAD = Thread::current();
2083 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
2084 SignatureStream ss(method->signature());
2085 for (int i = 0; i < total_in_args ; i++ ) {
2086 if (in_sig_bt[i] == T_ARRAY) {
2087 // Arrays are passed as int, elem* pair
2088 out_sig_bt[argc++] = T_INT;
2089 out_sig_bt[argc++] = T_ADDRESS;
2090 Symbol* atype = ss.as_symbol(CHECK_NULL);
2091 const char* at = atype->as_C_string();
2092 if (strlen(at) == 2) {
2093 assert(at[0] == '[', "must be");
2094 switch (at[1]) {
2095 case 'B': in_elem_bt[i] = T_BYTE; break;
2096 case 'C': in_elem_bt[i] = T_CHAR; break;
2097 case 'D': in_elem_bt[i] = T_DOUBLE; break;
2098 case 'F': in_elem_bt[i] = T_FLOAT; break;
2099 case 'I': in_elem_bt[i] = T_INT; break;
2100 case 'J': in_elem_bt[i] = T_LONG; break;
2101 case 'S': in_elem_bt[i] = T_SHORT; break;
2102 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
2103 default: ShouldNotReachHere();
2104 }
2105 }
2106 } else {
2107 out_sig_bt[argc++] = in_sig_bt[i];
2108 in_elem_bt[i] = T_VOID;
2109 }
2110 if (in_sig_bt[i] != T_VOID) {
2111 assert(in_sig_bt[i] == ss.type(), "must match");
2112 ss.next();
2113 }
2114 }
2115 }
2116
2117 // Now figure out where the args must be stored and how much stack space
2118 // they require (neglecting out_preserve_stack_slots but space for storing
2119 // the 1st six register arguments). It's weird see int_stk_helper.
2120 //
2121 int out_arg_slots;
2122 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
2123
2124 if (is_critical_native) {
2125 // Critical natives may have to call out so they need a save area
2126 // for register arguments.
2127 int double_slots = 0;
2128 int single_slots = 0;
2129 for ( int i = 0; i < total_in_args; i++) {
2130 if (in_regs[i].first()->is_Register()) {
2131 const Register reg = in_regs[i].first()->as_Register();
2132 switch (in_sig_bt[i]) {
2133 case T_ARRAY:
2134 case T_BOOLEAN:
2135 case T_BYTE:
2136 case T_SHORT:
2137 case T_CHAR:
2138 case T_INT: assert(reg->is_in(), "don't need to save these"); break;
2139 case T_LONG: if (reg->is_global()) double_slots++; break;
2140 default: ShouldNotReachHere();
2141 }
2142 } else if (in_regs[i].first()->is_FloatRegister()) {
2143 switch (in_sig_bt[i]) {
2144 case T_FLOAT: single_slots++; break;
2145 case T_DOUBLE: double_slots++; break;
2146 default: ShouldNotReachHere();
2147 }
2148 }
2149 }
2150 total_save_slots = double_slots * 2 + single_slots;
2151 }
2152
2153 // Compute framesize for the wrapper. We need to handlize all oops in
2154 // registers. We must create space for them here that is disjoint from
2155 // the windowed save area because we have no control over when we might
2156 // flush the window again and overwrite values that gc has since modified.
2157 // (The live window race)
2158 //
2159 // We always just allocate 6 word for storing down these object. This allow
2160 // us to simply record the base and use the Ireg number to decide which
2161 // slot to use. (Note that the reg number is the inbound number not the
2162 // outbound number).
2163 // We must shuffle args to match the native convention, and include var-args space.
2164
2165 // Calculate the total number of stack slots we will need.
2166
2167 // First count the abi requirement plus all of the outgoing args
2168 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2169
2170 // Now the space for the inbound oop handle area
2171
2172 int oop_handle_offset = round_to(stack_slots, 2);
2173 stack_slots += total_save_slots;
2174
2175 // Now any space we need for handlizing a klass if static method
2176
2177 int klass_slot_offset = 0;
2178 int klass_offset = -1;
2179 int lock_slot_offset = 0;
2180 bool is_static = false;
2181
2182 if (method->is_static()) {
2183 klass_slot_offset = stack_slots;
2184 stack_slots += VMRegImpl::slots_per_word;
2185 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
2186 is_static = true;
2187 }
2188
2189 // Plus a lock if needed
2190
2191 if (method->is_synchronized()) {
2192 lock_slot_offset = stack_slots;
2193 stack_slots += VMRegImpl::slots_per_word;
2194 }
2195
2196 // Now a place to save return value or as a temporary for any gpr -> fpr moves
2197 stack_slots += 2;
2198
2199 // Ok The space we have allocated will look like:
2200 //
2201 //
2202 // FP-> | |
2203 // |---------------------|
2204 // | 2 slots for moves |
2205 // |---------------------|
2206 // | lock box (if sync) |
2207 // |---------------------| <- lock_slot_offset
2208 // | klass (if static) |
2209 // |---------------------| <- klass_slot_offset
2210 // | oopHandle area |
2211 // |---------------------| <- oop_handle_offset
2212 // | outbound memory |
2213 // | based arguments |
2214 // | |
2215 // |---------------------|
2216 // | vararg area |
2217 // |---------------------|
2218 // | |
2219 // SP-> | out_preserved_slots |
2220 //
2221 //
2222
2223
2224 // Now compute actual number of stack words we need rounding to make
2225 // stack properly aligned.
2226 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
2227
2228 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2229
2230 // Generate stack overflow check before creating frame
2231 __ generate_stack_overflow_check(stack_size);
2232
2233 // Generate a new frame for the wrapper.
2234 __ save(SP, -stack_size, SP);
2235
2236 int frame_complete = ((intptr_t)__ pc()) - start;
2237
2238 __ verify_thread();
2239
2240 if (is_critical_native) {
2241 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args,
2242 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
2243 }
2244
2245 //
2246 // We immediately shuffle the arguments so that any vm call we have to
2247 // make from here on out (sync slow path, jvmti, etc.) we will have
2248 // captured the oops from our caller and have a valid oopMap for
2249 // them.
2250
2251 // -----------------
2252 // The Grand Shuffle
2253 //
2254 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
2255 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
2256 // the class mirror instead of a receiver. This pretty much guarantees that
2257 // register layout will not match. We ignore these extra arguments during
2258 // the shuffle. The shuffle is described by the two calling convention
2259 // vectors we have in our possession. We simply walk the java vector to
2260 // get the source locations and the c vector to get the destinations.
2261 // Because we have a new window and the argument registers are completely
2262 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
2263 // here.
2264
2265 // This is a trick. We double the stack slots so we can claim
2266 // the oops in the caller's frame. Since we are sure to have
2267 // more args than the caller doubling is enough to make
2268 // sure we can capture all the incoming oop args from the
2269 // caller.
2270 //
2271 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
2272 // Record sp-based slot for receiver on stack for non-static methods
2273 int receiver_offset = -1;
2274
2275 // We move the arguments backward because the floating point registers
2276 // destination will always be to a register with a greater or equal register
2277 // number or the stack.
2278
2279 #ifdef ASSERT
2280 bool reg_destroyed[RegisterImpl::number_of_registers];
2281 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2282 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2283 reg_destroyed[r] = false;
2284 }
2285 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2286 freg_destroyed[f] = false;
2287 }
2288
2289 #endif /* ASSERT */
2290
2291 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) {
2292
2293 #ifdef ASSERT
2294 if (in_regs[i].first()->is_Register()) {
2295 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
2296 } else if (in_regs[i].first()->is_FloatRegister()) {
2297 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
2298 }
2299 if (out_regs[c_arg].first()->is_Register()) {
2300 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2301 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
2302 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
2303 }
2304 #endif /* ASSERT */
2305
2306 switch (in_sig_bt[i]) {
2307 case T_ARRAY:
2308 if (is_critical_native) {
2309 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]);
2310 c_arg--;
2311 break;
2312 }
2313 case T_OBJECT:
2314 assert(!is_critical_native, "no oop arguments");
2315 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2316 ((i == 0) && (!is_static)),
2317 &receiver_offset);
2318 break;
2319 case T_VOID:
2320 break;
2321
2322 case T_FLOAT:
2323 float_move(masm, in_regs[i], out_regs[c_arg]);
2324 break;
2325
2326 case T_DOUBLE:
2327 assert( i + 1 < total_in_args &&
2328 in_sig_bt[i + 1] == T_VOID &&
2329 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2330 double_move(masm, in_regs[i], out_regs[c_arg]);
2331 break;
2332
2333 case T_LONG :
2334 long_move(masm, in_regs[i], out_regs[c_arg]);
2335 break;
2336
2337 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2338
2339 default:
2340 move32_64(masm, in_regs[i], out_regs[c_arg]);
2341 }
2342 }
2343
2344 // Pre-load a static method's oop into O1. Used both by locking code and
2345 // the normal JNI call code.
2346 if (method->is_static() && !is_critical_native) {
2347 __ set_oop_constant(JNIHandles::make_local(method->method_holder()->java_mirror()), O1);
2348
2349 // Now handlize the static class mirror in O1. It's known not-null.
2350 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
2351 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2352 __ add(SP, klass_offset + STACK_BIAS, O1);
2353 }
2354
2355
2356 const Register L6_handle = L6;
2357
2358 if (method->is_synchronized()) {
2359 assert(!is_critical_native, "unhandled");
2360 __ mov(O1, L6_handle);
2361 }
2362
2363 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
2364 // except O6/O7. So if we must call out we must push a new frame. We immediately
2365 // push a new frame and flush the windows.
2366 #ifdef _LP64
2367 intptr_t thepc = (intptr_t) __ pc();
2368 {
2369 address here = __ pc();
2370 // Call the next instruction
2371 __ call(here + 8, relocInfo::none);
2372 __ delayed()->nop();
2373 }
2374 #else
2375 intptr_t thepc = __ load_pc_address(O7, 0);
2376 #endif /* _LP64 */
2377
2378 // We use the same pc/oopMap repeatedly when we call out
2379 oop_maps->add_gc_map(thepc - start, map);
2380
2381 // O7 now has the pc loaded that we will use when we finally call to native.
2382
2383 // Save thread in L7; it crosses a bunch of VM calls below
2384 // Don't use save_thread because it smashes G2 and we merely
2385 // want to save a copy
2386 __ mov(G2_thread, L7_thread_cache);
2387
2388
2389 // If we create an inner frame once is plenty
2390 // when we create it we must also save G2_thread
2391 bool inner_frame_created = false;
2392
2393 // dtrace method entry support
2394 {
2395 SkipIfEqual skip_if(
2396 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2397 // create inner frame
2398 __ save_frame(0);
2399 __ mov(G2_thread, L7_thread_cache);
2400 __ set_metadata_constant(method(), O1);
2401 __ call_VM_leaf(L7_thread_cache,
2402 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2403 G2_thread, O1);
2404 __ restore();
2405 }
2406
2407 // RedefineClasses() tracing support for obsolete method entry
2408 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
2409 // create inner frame
2410 __ save_frame(0);
2411 __ mov(G2_thread, L7_thread_cache);
2412 __ set_metadata_constant(method(), O1);
2413 __ call_VM_leaf(L7_thread_cache,
2414 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2415 G2_thread, O1);
2416 __ restore();
2417 }
2418
2419 // We are in the jni frame unless saved_frame is true in which case
2420 // we are in one frame deeper (the "inner" frame). If we are in the
2421 // "inner" frames the args are in the Iregs and if the jni frame then
2422 // they are in the Oregs.
2423 // If we ever need to go to the VM (for locking, jvmti) then
2424 // we will always be in the "inner" frame.
2425
2426 // Lock a synchronized method
2427 int lock_offset = -1; // Set if locked
2428 if (method->is_synchronized()) {
2429 Register Roop = O1;
2430 const Register L3_box = L3;
2431
2432 create_inner_frame(masm, &inner_frame_created);
2433
2434 __ ld_ptr(I1, 0, O1);
2435 Label done;
2436
2437 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
2438 __ add(FP, lock_offset+STACK_BIAS, L3_box);
2439 #ifdef ASSERT
2440 if (UseBiasedLocking) {
2441 // making the box point to itself will make it clear it went unused
2442 // but also be obviously invalid
2443 __ st_ptr(L3_box, L3_box, 0);
2444 }
2445 #endif // ASSERT
2446 //
2447 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
2448 //
2449 __ compiler_lock_object(Roop, L1, L3_box, L2);
2450 __ br(Assembler::equal, false, Assembler::pt, done);
2451 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
2452
2453
2454 // None of the above fast optimizations worked so we have to get into the
2455 // slow case of monitor enter. Inline a special case of call_VM that
2456 // disallows any pending_exception.
2457 __ mov(Roop, O0); // Need oop in O0
2458 __ mov(L3_box, O1);
2459
2460 // Record last_Java_sp, in case the VM code releases the JVM lock.
2461
2462 __ set_last_Java_frame(FP, I7);
2463
2464 // do the call
2465 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
2466 __ delayed()->mov(L7_thread_cache, O2);
2467
2468 __ restore_thread(L7_thread_cache); // restore G2_thread
2469 __ reset_last_Java_frame();
2470
2471 #ifdef ASSERT
2472 { Label L;
2473 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2474 __ br_null_short(O0, Assembler::pt, L);
2475 __ stop("no pending exception allowed on exit from IR::monitorenter");
2476 __ bind(L);
2477 }
2478 #endif
2479 __ bind(done);
2480 }
2481
2482
2483 // Finally just about ready to make the JNI call
2484
2485 __ flushw();
2486 if (inner_frame_created) {
2487 __ restore();
2488 } else {
2489 // Store only what we need from this frame
2490 // QQQ I think that non-v9 (like we care) we don't need these saves
2491 // either as the flush traps and the current window goes too.
2492 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2493 #ifdef STACKGHOST
2494 __ set(sg_cookie(), G3_scratch);
2495 __ xor3(G3_scratch, I7, G3_scratch);
2496 __ st_ptr(G3_scratch, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2497 #else
2498 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2499 #endif
2500 }
2501
2502 // get JNIEnv* which is first argument to native
2503 if (!is_critical_native) {
2504 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
2505 }
2506
2507 // Use that pc we placed in O7 a while back as the current frame anchor
2508 __ set_last_Java_frame(SP, O7);
2509
2510 // We flushed the windows ages ago now mark them as flushed before transitioning.
2511 __ set(JavaFrameAnchor::flushed, G3_scratch);
2512 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
2513
2514 // Transition from _thread_in_Java to _thread_in_native.
2515 __ set(_thread_in_native, G3_scratch);
2516
2517 #ifdef _LP64
2518 AddressLiteral dest(native_func);
2519 __ relocate(relocInfo::runtime_call_type);
2520 __ jumpl_to(dest, O7, O7);
2521 #else
2522 __ call(native_func, relocInfo::runtime_call_type);
2523 #endif
2524 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2525
2526 __ restore_thread(L7_thread_cache); // restore G2_thread
2527
2528 // Unpack native results. For int-types, we do any needed sign-extension
2529 // and move things into I0. The return value there will survive any VM
2530 // calls for blocking or unlocking. An FP or OOP result (handle) is done
2531 // specially in the slow-path code.
2532 switch (ret_type) {
2533 case T_VOID: break; // Nothing to do!
2534 case T_FLOAT: break; // Got it where we want it (unless slow-path)
2535 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
2536 // In 64 bits build result is in O0, in O0, O1 in 32bit build
2537 case T_LONG:
2538 #ifndef _LP64
2539 __ mov(O1, I1);
2540 #endif
2541 // Fall thru
2542 case T_OBJECT: // Really a handle
2543 case T_ARRAY:
2544 case T_INT:
2545 __ mov(O0, I0);
2546 break;
2547 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
2548 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
2549 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
2550 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
2551 break; // Cannot de-handlize until after reclaiming jvm_lock
2552 default:
2553 ShouldNotReachHere();
2554 }
2555
2556 Label after_transition;
2557 // must we block?
2558
2559 // Block, if necessary, before resuming in _thread_in_Java state.
2560 // In order for GC to work, don't clear the last_Java_sp until after blocking.
2561 { Label no_block;
2562 AddressLiteral sync_state(SafepointSynchronize::address_of_state());
2563
2564 // Switch thread to "native transition" state before reading the synchronization state.
2565 // This additional state is necessary because reading and testing the synchronization
2566 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2567 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2568 // VM thread changes sync state to synchronizing and suspends threads for GC.
2569 // Thread A is resumed to finish this native method, but doesn't block here since it
2570 // didn't see any synchronization is progress, and escapes.
2571 __ set(_thread_in_native_trans, G3_scratch);
2572 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2573 if(os::is_MP()) {
2574 if (UseMembar) {
2575 // Force this write out before the read below
2576 __ membar(Assembler::StoreLoad);
2577 } else {
2578 // Write serialization page so VM thread can do a pseudo remote membar.
2579 // We use the current thread pointer to calculate a thread specific
2580 // offset to write to within the page. This minimizes bus traffic
2581 // due to cache line collision.
2582 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
2583 }
2584 }
2585 __ load_contents(sync_state, G3_scratch);
2586 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
2587
2588 Label L;
2589 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
2590 __ br(Assembler::notEqual, false, Assembler::pn, L);
2591 __ delayed()->ld(suspend_state, G3_scratch);
2592 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block);
2593 __ bind(L);
2594
2595 // Block. Save any potential method result value before the operation and
2596 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
2597 // lets us share the oopMap we used when we went native rather the create
2598 // a distinct one for this pc
2599 //
2600 save_native_result(masm, ret_type, stack_slots);
2601 if (!is_critical_native) {
2602 __ call_VM_leaf(L7_thread_cache,
2603 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
2604 G2_thread);
2605 } else {
2606 __ call_VM_leaf(L7_thread_cache,
2607 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition),
2608 G2_thread);
2609 }
2610
2611 // Restore any method result value
2612 restore_native_result(masm, ret_type, stack_slots);
2613
2614 if (is_critical_native) {
2615 // The call above performed the transition to thread_in_Java so
2616 // skip the transition logic below.
2617 __ ba(after_transition);
2618 __ delayed()->nop();
2619 }
2620
2621 __ bind(no_block);
2622 }
2623
2624 // thread state is thread_in_native_trans. Any safepoint blocking has already
2625 // happened so we can now change state to _thread_in_Java.
2626 __ set(_thread_in_Java, G3_scratch);
2627 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2628 __ bind(after_transition);
2629
2630 Label no_reguard;
2631 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
2632 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard);
2633
2634 save_native_result(masm, ret_type, stack_slots);
2635 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
2636 __ delayed()->nop();
2637
2638 __ restore_thread(L7_thread_cache); // restore G2_thread
2639 restore_native_result(masm, ret_type, stack_slots);
2640
2641 __ bind(no_reguard);
2642
2643 // Handle possible exception (will unlock if necessary)
2644
2645 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
2646
2647 // Unlock
2648 if (method->is_synchronized()) {
2649 Label done;
2650 Register I2_ex_oop = I2;
2651 const Register L3_box = L3;
2652 // Get locked oop from the handle we passed to jni
2653 __ ld_ptr(L6_handle, 0, L4);
2654 __ add(SP, lock_offset+STACK_BIAS, L3_box);
2655 // Must save pending exception around the slow-path VM call. Since it's a
2656 // leaf call, the pending exception (if any) can be kept in a register.
2657 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
2658 // Now unlock
2659 // (Roop, Rmark, Rbox, Rscratch)
2660 __ compiler_unlock_object(L4, L1, L3_box, L2);
2661 __ br(Assembler::equal, false, Assembler::pt, done);
2662 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
2663
2664 // save and restore any potential method result value around the unlocking
2665 // operation. Will save in I0 (or stack for FP returns).
2666 save_native_result(masm, ret_type, stack_slots);
2667
2668 // Must clear pending-exception before re-entering the VM. Since this is
2669 // a leaf call, pending-exception-oop can be safely kept in a register.
2670 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
2671
2672 // slow case of monitor enter. Inline a special case of call_VM that
2673 // disallows any pending_exception.
2674 __ mov(L3_box, O1);
2675
2676 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
2677 __ delayed()->mov(L4, O0); // Need oop in O0
2678
2679 __ restore_thread(L7_thread_cache); // restore G2_thread
2680
2681 #ifdef ASSERT
2682 { Label L;
2683 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2684 __ br_null_short(O0, Assembler::pt, L);
2685 __ stop("no pending exception allowed on exit from IR::monitorexit");
2686 __ bind(L);
2687 }
2688 #endif
2689 restore_native_result(masm, ret_type, stack_slots);
2690 // check_forward_pending_exception jump to forward_exception if any pending
2691 // exception is set. The forward_exception routine expects to see the
2692 // exception in pending_exception and not in a register. Kind of clumsy,
2693 // since all folks who branch to forward_exception must have tested
2694 // pending_exception first and hence have it in a register already.
2695 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
2696 __ bind(done);
2697 }
2698
2699 // Tell dtrace about this method exit
2700 {
2701 SkipIfEqual skip_if(
2702 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2703 save_native_result(masm, ret_type, stack_slots);
2704 __ set_metadata_constant(method(), O1);
2705 __ call_VM_leaf(L7_thread_cache,
2706 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2707 G2_thread, O1);
2708 restore_native_result(masm, ret_type, stack_slots);
2709 }
2710
2711 // Clear "last Java frame" SP and PC.
2712 __ verify_thread(); // G2_thread must be correct
2713 __ reset_last_Java_frame();
2714
2715 // Unbox oop result, e.g. JNIHandles::resolve value in I0.
2716 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2717 Label done, not_weak;
2718 __ br_null(I0, false, Assembler::pn, done); // Use NULL as-is.
2719 __ delayed()->andcc(I0, JNIHandles::weak_tag_mask, G0); // Test for jweak
2720 __ brx(Assembler::zero, true, Assembler::pt, not_weak);
2721 __ delayed()->ld_ptr(I0, 0, I0); // Maybe resolve (untagged) jobject.
2722 // Resolve jweak.
2723 __ ld_ptr(I0, -JNIHandles::weak_tag_value, I0);
2724 #if INCLUDE_ALL_GCS
2725 if (UseG1GC) {
2726 // Copy to O0 because macro doesn't allow pre_val in input reg.
2727 __ mov(I0, O0);
2728 __ g1_write_barrier_pre(noreg /* obj */,
2729 noreg /* index */,
2730 0 /* offset */,
2731 O0 /* pre_val */,
2732 G3_scratch /* tmp */,
2733 true /* preserve_o_regs */);
2734 }
2735 #endif // INCLUDE_ALL_GCS
2736 __ bind(not_weak);
2737 __ verify_oop(I0);
2738 __ bind(done);
2739 }
2740
2741 if (!is_critical_native) {
2742 // reset handle block
2743 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
2744 __ st(G0, L5, JNIHandleBlock::top_offset_in_bytes());
2745
2746 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
2747 check_forward_pending_exception(masm, G3_scratch);
2748 }
2749
2750
2751 // Return
2752
2753 #ifndef _LP64
2754 if (ret_type == T_LONG) {
2755
2756 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
2757 __ sllx(I0, 32, G1); // Shift bits into high G1
2758 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
2759 __ or3 (I1, G1, G1); // OR 64 bits into G1
2760 }
2761 #endif
2762
2763 __ ret();
2764 __ delayed()->restore();
2765
2766 __ flush();
2767
2768 nmethod *nm = nmethod::new_native_nmethod(method,
2769 compile_id,
2770 masm->code(),
2771 vep_offset,
2772 frame_complete,
2773 stack_slots / VMRegImpl::slots_per_word,
2774 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2775 in_ByteSize(lock_offset),
2776 oop_maps);
2777
2778 if (is_critical_native) {
2779 nm->set_lazy_critical_native(true);
2780 }
2781 return nm;
2782
2783 }
2784
2785 #ifdef HAVE_DTRACE_H
2786 // ---------------------------------------------------------------------------
2787 // Generate a dtrace nmethod for a given signature. The method takes arguments
2788 // in the Java compiled code convention, marshals them to the native
2789 // abi and then leaves nops at the position you would expect to call a native
2790 // function. When the probe is enabled the nops are replaced with a trap
2791 // instruction that dtrace inserts and the trace will cause a notification
2792 // to dtrace.
2793 //
2794 // The probes are only able to take primitive types and java/lang/String as
2795 // arguments. No other java types are allowed. Strings are converted to utf8
2796 // strings so that from dtrace point of view java strings are converted to C
2797 // strings. There is an arbitrary fixed limit on the total space that a method
2798 // can use for converting the strings. (256 chars per string in the signature).
2799 // So any java string larger then this is truncated.
2800
2801 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
2802 static bool offsets_initialized = false;
2803
generate_dtrace_nmethod(MacroAssembler * masm,methodHandle method)2804 nmethod *SharedRuntime::generate_dtrace_nmethod(
2805 MacroAssembler *masm, methodHandle method) {
2806
2807
2808 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2809 // be single threaded in this method.
2810 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2811
2812 // Fill in the signature array, for the calling-convention call.
2813 int total_args_passed = method->size_of_parameters();
2814
2815 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2816 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2817
2818 // The signature we are going to use for the trap that dtrace will see
2819 // java/lang/String is converted. We drop "this" and any other object
2820 // is converted to NULL. (A one-slot java/lang/Long object reference
2821 // is converted to a two-slot long, which is why we double the allocation).
2822 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2823 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2824
2825 int i=0;
2826 int total_strings = 0;
2827 int first_arg_to_pass = 0;
2828 int total_c_args = 0;
2829
2830 // Skip the receiver as dtrace doesn't want to see it
2831 if( !method->is_static() ) {
2832 in_sig_bt[i++] = T_OBJECT;
2833 first_arg_to_pass = 1;
2834 }
2835
2836 SignatureStream ss(method->signature());
2837 for ( ; !ss.at_return_type(); ss.next()) {
2838 BasicType bt = ss.type();
2839 in_sig_bt[i++] = bt; // Collect remaining bits of signature
2840 out_sig_bt[total_c_args++] = bt;
2841 if( bt == T_OBJECT) {
2842 Symbol* s = ss.as_symbol_or_null();
2843 if (s == vmSymbols::java_lang_String()) {
2844 total_strings++;
2845 out_sig_bt[total_c_args-1] = T_ADDRESS;
2846 } else if (s == vmSymbols::java_lang_Boolean() ||
2847 s == vmSymbols::java_lang_Byte()) {
2848 out_sig_bt[total_c_args-1] = T_BYTE;
2849 } else if (s == vmSymbols::java_lang_Character() ||
2850 s == vmSymbols::java_lang_Short()) {
2851 out_sig_bt[total_c_args-1] = T_SHORT;
2852 } else if (s == vmSymbols::java_lang_Integer() ||
2853 s == vmSymbols::java_lang_Float()) {
2854 out_sig_bt[total_c_args-1] = T_INT;
2855 } else if (s == vmSymbols::java_lang_Long() ||
2856 s == vmSymbols::java_lang_Double()) {
2857 out_sig_bt[total_c_args-1] = T_LONG;
2858 out_sig_bt[total_c_args++] = T_VOID;
2859 }
2860 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2861 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2862 // We convert double to long
2863 out_sig_bt[total_c_args-1] = T_LONG;
2864 out_sig_bt[total_c_args++] = T_VOID;
2865 } else if ( bt == T_FLOAT) {
2866 // We convert float to int
2867 out_sig_bt[total_c_args-1] = T_INT;
2868 }
2869 }
2870
2871 assert(i==total_args_passed, "validly parsed signature");
2872
2873 // Now get the compiled-Java layout as input arguments
2874 int comp_args_on_stack;
2875 comp_args_on_stack = SharedRuntime::java_calling_convention(
2876 in_sig_bt, in_regs, total_args_passed, false);
2877
2878 // We have received a description of where all the java arg are located
2879 // on entry to the wrapper. We need to convert these args to where
2880 // the a native (non-jni) function would expect them. To figure out
2881 // where they go we convert the java signature to a C signature and remove
2882 // T_VOID for any long/double we might have received.
2883
2884
2885 // Now figure out where the args must be stored and how much stack space
2886 // they require (neglecting out_preserve_stack_slots but space for storing
2887 // the 1st six register arguments). It's weird see int_stk_helper.
2888 //
2889 int out_arg_slots;
2890 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
2891
2892 // Calculate the total number of stack slots we will need.
2893
2894 // First count the abi requirement plus all of the outgoing args
2895 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2896
2897 // Plus a temp for possible converion of float/double/long register args
2898
2899 int conversion_temp = stack_slots;
2900 stack_slots += 2;
2901
2902
2903 // Now space for the string(s) we must convert
2904
2905 int string_locs = stack_slots;
2906 stack_slots += total_strings *
2907 (max_dtrace_string_size / VMRegImpl::stack_slot_size);
2908
2909 // Ok The space we have allocated will look like:
2910 //
2911 //
2912 // FP-> | |
2913 // |---------------------|
2914 // | string[n] |
2915 // |---------------------| <- string_locs[n]
2916 // | string[n-1] |
2917 // |---------------------| <- string_locs[n-1]
2918 // | ... |
2919 // | ... |
2920 // |---------------------| <- string_locs[1]
2921 // | string[0] |
2922 // |---------------------| <- string_locs[0]
2923 // | temp |
2924 // |---------------------| <- conversion_temp
2925 // | outbound memory |
2926 // | based arguments |
2927 // | |
2928 // |---------------------|
2929 // | |
2930 // SP-> | out_preserved_slots |
2931 //
2932 //
2933
2934 // Now compute actual number of stack words we need rounding to make
2935 // stack properly aligned.
2936 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2937
2938 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2939
2940 intptr_t start = (intptr_t)__ pc();
2941
2942 // First thing make an ic check to see if we should even be here
2943
2944 {
2945 Label L;
2946 const Register temp_reg = G3_scratch;
2947 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
2948 __ verify_oop(O0);
2949 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
2950 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
2951
2952 __ jump_to(ic_miss, temp_reg);
2953 __ delayed()->nop();
2954 __ align(CodeEntryAlignment);
2955 __ bind(L);
2956 }
2957
2958 int vep_offset = ((intptr_t)__ pc()) - start;
2959
2960
2961 // The instruction at the verified entry point must be 5 bytes or longer
2962 // because it can be patched on the fly by make_non_entrant. The stack bang
2963 // instruction fits that requirement.
2964
2965 // Generate stack overflow check before creating frame
2966 __ generate_stack_overflow_check(stack_size);
2967
2968 assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
2969 "valid size for make_non_entrant");
2970
2971 // Generate a new frame for the wrapper.
2972 __ save(SP, -stack_size, SP);
2973
2974 // Frame is now completed as far a size and linkage.
2975
2976 int frame_complete = ((intptr_t)__ pc()) - start;
2977
2978 #ifdef ASSERT
2979 bool reg_destroyed[RegisterImpl::number_of_registers];
2980 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2981 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2982 reg_destroyed[r] = false;
2983 }
2984 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2985 freg_destroyed[f] = false;
2986 }
2987
2988 #endif /* ASSERT */
2989
2990 VMRegPair zero;
2991 const Register g0 = G0; // without this we get a compiler warning (why??)
2992 zero.set2(g0->as_VMReg());
2993
2994 int c_arg, j_arg;
2995
2996 Register conversion_off = noreg;
2997
2998 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2999 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
3000
3001 VMRegPair src = in_regs[j_arg];
3002 VMRegPair dst = out_regs[c_arg];
3003
3004 #ifdef ASSERT
3005 if (src.first()->is_Register()) {
3006 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
3007 } else if (src.first()->is_FloatRegister()) {
3008 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
3009 FloatRegisterImpl::S)], "ack!");
3010 }
3011 if (dst.first()->is_Register()) {
3012 reg_destroyed[dst.first()->as_Register()->encoding()] = true;
3013 } else if (dst.first()->is_FloatRegister()) {
3014 freg_destroyed[dst.first()->as_FloatRegister()->encoding(
3015 FloatRegisterImpl::S)] = true;
3016 }
3017 #endif /* ASSERT */
3018
3019 switch (in_sig_bt[j_arg]) {
3020 case T_ARRAY:
3021 case T_OBJECT:
3022 {
3023 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
3024 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
3025 // need to unbox a one-slot value
3026 Register in_reg = L0;
3027 Register tmp = L2;
3028 if ( src.first()->is_reg() ) {
3029 in_reg = src.first()->as_Register();
3030 } else {
3031 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
3032 "must be");
3033 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
3034 }
3035 // If the final destination is an acceptable register
3036 if ( dst.first()->is_reg() ) {
3037 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
3038 tmp = dst.first()->as_Register();
3039 }
3040 }
3041
3042 Label skipUnbox;
3043 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
3044 __ mov(G0, tmp->successor());
3045 }
3046 __ br_null(in_reg, true, Assembler::pn, skipUnbox);
3047 __ delayed()->mov(G0, tmp);
3048
3049 BasicType bt = out_sig_bt[c_arg];
3050 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
3051 switch (bt) {
3052 case T_BYTE:
3053 __ ldub(in_reg, box_offset, tmp); break;
3054 case T_SHORT:
3055 __ lduh(in_reg, box_offset, tmp); break;
3056 case T_INT:
3057 __ ld(in_reg, box_offset, tmp); break;
3058 case T_LONG:
3059 __ ld_long(in_reg, box_offset, tmp); break;
3060 default: ShouldNotReachHere();
3061 }
3062
3063 __ bind(skipUnbox);
3064 // If tmp wasn't final destination copy to final destination
3065 if (tmp == L2) {
3066 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
3067 if (out_sig_bt[c_arg] == T_LONG) {
3068 long_move(masm, tmp_as_VM, dst);
3069 } else {
3070 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
3071 }
3072 }
3073 if (out_sig_bt[c_arg] == T_LONG) {
3074 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
3075 ++c_arg; // move over the T_VOID to keep the loop indices in sync
3076 }
3077 } else if (out_sig_bt[c_arg] == T_ADDRESS) {
3078 Register s =
3079 src.first()->is_reg() ? src.first()->as_Register() : L2;
3080 Register d =
3081 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
3082
3083 // We store the oop now so that the conversion pass can reach
3084 // while in the inner frame. This will be the only store if
3085 // the oop is NULL.
3086 if (s != L2) {
3087 // src is register
3088 if (d != L2) {
3089 // dst is register
3090 __ mov(s, d);
3091 } else {
3092 assert(Assembler::is_simm13(reg2offset(dst.first()) +
3093 STACK_BIAS), "must be");
3094 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
3095 }
3096 } else {
3097 // src not a register
3098 assert(Assembler::is_simm13(reg2offset(src.first()) +
3099 STACK_BIAS), "must be");
3100 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
3101 if (d == L2) {
3102 assert(Assembler::is_simm13(reg2offset(dst.first()) +
3103 STACK_BIAS), "must be");
3104 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
3105 }
3106 }
3107 } else if (out_sig_bt[c_arg] != T_VOID) {
3108 // Convert the arg to NULL
3109 if (dst.first()->is_reg()) {
3110 __ mov(G0, dst.first()->as_Register());
3111 } else {
3112 assert(Assembler::is_simm13(reg2offset(dst.first()) +
3113 STACK_BIAS), "must be");
3114 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
3115 }
3116 }
3117 }
3118 break;
3119 case T_VOID:
3120 break;
3121
3122 case T_FLOAT:
3123 if (src.first()->is_stack()) {
3124 // Stack to stack/reg is simple
3125 move32_64(masm, src, dst);
3126 } else {
3127 if (dst.first()->is_reg()) {
3128 // freg -> reg
3129 int off =
3130 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
3131 Register d = dst.first()->as_Register();
3132 if (Assembler::is_simm13(off)) {
3133 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
3134 SP, off);
3135 __ ld(SP, off, d);
3136 } else {
3137 if (conversion_off == noreg) {
3138 __ set(off, L6);
3139 conversion_off = L6;
3140 }
3141 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
3142 SP, conversion_off);
3143 __ ld(SP, conversion_off , d);
3144 }
3145 } else {
3146 // freg -> mem
3147 int off = STACK_BIAS + reg2offset(dst.first());
3148 if (Assembler::is_simm13(off)) {
3149 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
3150 SP, off);
3151 } else {
3152 if (conversion_off == noreg) {
3153 __ set(off, L6);
3154 conversion_off = L6;
3155 }
3156 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
3157 SP, conversion_off);
3158 }
3159 }
3160 }
3161 break;
3162
3163 case T_DOUBLE:
3164 assert( j_arg + 1 < total_args_passed &&
3165 in_sig_bt[j_arg + 1] == T_VOID &&
3166 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
3167 if (src.first()->is_stack()) {
3168 // Stack to stack/reg is simple
3169 long_move(masm, src, dst);
3170 } else {
3171 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
3172
3173 // Destination could be an odd reg on 32bit in which case
3174 // we can't load direct to the destination.
3175
3176 if (!d->is_even() && wordSize == 4) {
3177 d = L2;
3178 }
3179 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
3180 if (Assembler::is_simm13(off)) {
3181 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
3182 SP, off);
3183 __ ld_long(SP, off, d);
3184 } else {
3185 if (conversion_off == noreg) {
3186 __ set(off, L6);
3187 conversion_off = L6;
3188 }
3189 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
3190 SP, conversion_off);
3191 __ ld_long(SP, conversion_off, d);
3192 }
3193 if (d == L2) {
3194 long_move(masm, reg64_to_VMRegPair(L2), dst);
3195 }
3196 }
3197 break;
3198
3199 case T_LONG :
3200 // 32bit can't do a split move of something like g1 -> O0, O1
3201 // so use a memory temp
3202 if (src.is_single_phys_reg() && wordSize == 4) {
3203 Register tmp = L2;
3204 if (dst.first()->is_reg() &&
3205 (wordSize == 8 || dst.first()->as_Register()->is_even())) {
3206 tmp = dst.first()->as_Register();
3207 }
3208
3209 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
3210 if (Assembler::is_simm13(off)) {
3211 __ stx(src.first()->as_Register(), SP, off);
3212 __ ld_long(SP, off, tmp);
3213 } else {
3214 if (conversion_off == noreg) {
3215 __ set(off, L6);
3216 conversion_off = L6;
3217 }
3218 __ stx(src.first()->as_Register(), SP, conversion_off);
3219 __ ld_long(SP, conversion_off, tmp);
3220 }
3221
3222 if (tmp == L2) {
3223 long_move(masm, reg64_to_VMRegPair(L2), dst);
3224 }
3225 } else {
3226 long_move(masm, src, dst);
3227 }
3228 break;
3229
3230 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
3231
3232 default:
3233 move32_64(masm, src, dst);
3234 }
3235 }
3236
3237
3238 // If we have any strings we must store any register based arg to the stack
3239 // This includes any still live xmm registers too.
3240
3241 if (total_strings > 0 ) {
3242
3243 // protect all the arg registers
3244 __ save_frame(0);
3245 __ mov(G2_thread, L7_thread_cache);
3246 const Register L2_string_off = L2;
3247
3248 // Get first string offset
3249 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
3250
3251 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
3252 if (out_sig_bt[c_arg] == T_ADDRESS) {
3253
3254 VMRegPair dst = out_regs[c_arg];
3255 const Register d = dst.first()->is_reg() ?
3256 dst.first()->as_Register()->after_save() : noreg;
3257
3258 // It's a string the oop and it was already copied to the out arg
3259 // position
3260 if (d != noreg) {
3261 __ mov(d, O0);
3262 } else {
3263 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
3264 "must be");
3265 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0);
3266 }
3267 Label skip;
3268
3269 __ br_null(O0, false, Assembler::pn, skip);
3270 __ delayed()->add(FP, L2_string_off, O1);
3271
3272 if (d != noreg) {
3273 __ mov(O1, d);
3274 } else {
3275 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
3276 "must be");
3277 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS);
3278 }
3279
3280 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
3281 relocInfo::runtime_call_type);
3282 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
3283
3284 __ bind(skip);
3285
3286 }
3287
3288 }
3289 __ mov(L7_thread_cache, G2_thread);
3290 __ restore();
3291
3292 }
3293
3294
3295 // Ok now we are done. Need to place the nop that dtrace wants in order to
3296 // patch in the trap
3297
3298 int patch_offset = ((intptr_t)__ pc()) - start;
3299
3300 __ nop();
3301
3302
3303 // Return
3304
3305 __ ret();
3306 __ delayed()->restore();
3307
3308 __ flush();
3309
3310 nmethod *nm = nmethod::new_dtrace_nmethod(
3311 method, masm->code(), vep_offset, patch_offset, frame_complete,
3312 stack_slots / VMRegImpl::slots_per_word);
3313 return nm;
3314
3315 }
3316
3317 #endif // HAVE_DTRACE_H
3318
3319 // this function returns the adjust size (in number of words) to a c2i adapter
3320 // activation for use during deoptimization
last_frame_adjust(int callee_parameters,int callee_locals)3321 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
3322 assert(callee_locals >= callee_parameters,
3323 "test and remove; got more parms than locals");
3324 if (callee_locals < callee_parameters)
3325 return 0; // No adjustment for negative locals
3326 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
3327 return round_to(diff, WordsPerLong);
3328 }
3329
3330 // "Top of Stack" slots that may be unused by the calling convention but must
3331 // otherwise be preserved.
3332 // On Intel these are not necessary and the value can be zero.
3333 // On Sparc this describes the words reserved for storing a register window
3334 // when an interrupt occurs.
out_preserve_stack_slots()3335 uint SharedRuntime::out_preserve_stack_slots() {
3336 return frame::register_save_words * VMRegImpl::slots_per_word;
3337 }
3338
gen_new_frame(MacroAssembler * masm,bool deopt)3339 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
3340 //
3341 // Common out the new frame generation for deopt and uncommon trap
3342 //
3343 Register G3pcs = G3_scratch; // Array of new pcs (input)
3344 Register Oreturn0 = O0;
3345 Register Oreturn1 = O1;
3346 Register O2UnrollBlock = O2;
3347 Register O3array = O3; // Array of frame sizes (input)
3348 Register O4array_size = O4; // number of frames (input)
3349 Register O7frame_size = O7; // number of frames (input)
3350
3351 __ ld_ptr(O3array, 0, O7frame_size);
3352 __ sub(G0, O7frame_size, O7frame_size);
3353 __ save(SP, O7frame_size, SP);
3354 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc
3355
3356 #ifdef ASSERT
3357 // make sure that the frames are aligned properly
3358 #ifndef _LP64
3359 __ btst(wordSize*2-1, SP);
3360 __ breakpoint_trap(Assembler::notZero, Assembler::ptr_cc);
3361 #endif
3362 #endif
3363
3364 // Deopt needs to pass some extra live values from frame to frame
3365
3366 if (deopt) {
3367 __ mov(Oreturn0->after_save(), Oreturn0);
3368 __ mov(Oreturn1->after_save(), Oreturn1);
3369 }
3370
3371 __ mov(O4array_size->after_save(), O4array_size);
3372 __ sub(O4array_size, 1, O4array_size);
3373 __ mov(O3array->after_save(), O3array);
3374 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
3375 __ add(G3pcs, wordSize, G3pcs); // point to next pc value
3376
3377 #ifdef ASSERT
3378 // trash registers to show a clear pattern in backtraces
3379 __ set(0xDEAD0000, I0);
3380 __ add(I0, 2, I1);
3381 __ add(I0, 4, I2);
3382 __ add(I0, 6, I3);
3383 __ add(I0, 8, I4);
3384 // Don't touch I5 could have valuable savedSP
3385 __ set(0xDEADBEEF, L0);
3386 __ mov(L0, L1);
3387 __ mov(L0, L2);
3388 __ mov(L0, L3);
3389 __ mov(L0, L4);
3390 __ mov(L0, L5);
3391
3392 // trash the return value as there is nothing to return yet
3393 __ set(0xDEAD0001, O7);
3394 #endif
3395
3396 __ mov(SP, O5_savedSP);
3397 }
3398
3399
make_new_frames(MacroAssembler * masm,bool deopt)3400 static void make_new_frames(MacroAssembler* masm, bool deopt) {
3401 //
3402 // loop through the UnrollBlock info and create new frames
3403 //
3404 Register G3pcs = G3_scratch;
3405 Register Oreturn0 = O0;
3406 Register Oreturn1 = O1;
3407 Register O2UnrollBlock = O2;
3408 Register O3array = O3;
3409 Register O4array_size = O4;
3410 Label loop;
3411
3412 #ifdef ASSERT
3413 // Compilers generate code that bang the stack by as much as the
3414 // interpreter would need. So this stack banging should never
3415 // trigger a fault. Verify that it does not on non product builds.
3416 if (UseStackBanging) {
3417 // Get total frame size for interpreted frames
3418 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
3419 __ bang_stack_size(O4, O3, G3_scratch);
3420 }
3421 #endif
3422
3423 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
3424 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
3425 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
3426
3427 // Adjust old interpreter frame to make space for new frame's extra java locals
3428 //
3429 // We capture the original sp for the transition frame only because it is needed in
3430 // order to properly calculate interpreter_sp_adjustment. Even though in real life
3431 // every interpreter frame captures a savedSP it is only needed at the transition
3432 // (fortunately). If we had to have it correct everywhere then we would need to
3433 // be told the sp_adjustment for each frame we create. If the frame size array
3434 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
3435 // for each frame we create and keep up the illusion every where.
3436 //
3437
3438 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
3439 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
3440 __ sub(SP, O7, SP);
3441
3442 #ifdef ASSERT
3443 // make sure that there is at least one entry in the array
3444 __ tst(O4array_size);
3445 __ breakpoint_trap(Assembler::zero, Assembler::icc);
3446 #endif
3447
3448 // Now push the new interpreter frames
3449 __ bind(loop);
3450
3451 // allocate a new frame, filling the registers
3452
3453 gen_new_frame(masm, deopt); // allocate an interpreter frame
3454
3455 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop);
3456 __ delayed()->add(O3array, wordSize, O3array);
3457 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc
3458
3459 }
3460
3461 //------------------------------generate_deopt_blob----------------------------
3462 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3463 // instead.
generate_deopt_blob()3464 void SharedRuntime::generate_deopt_blob() {
3465 // allocate space for the code
3466 ResourceMark rm;
3467 // setup code generation tools
3468 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code
3469 #ifdef ASSERT
3470 if (UseStackBanging) {
3471 pad += StackShadowPages*16 + 32;
3472 }
3473 #endif
3474 #ifdef _LP64
3475 CodeBuffer buffer("deopt_blob", 2100+pad, 512);
3476 #else
3477 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread)
3478 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread)
3479 CodeBuffer buffer("deopt_blob", 1600+pad, 512);
3480 #endif /* _LP64 */
3481 MacroAssembler* masm = new MacroAssembler(&buffer);
3482 FloatRegister Freturn0 = F0;
3483 Register Greturn1 = G1;
3484 Register Oreturn0 = O0;
3485 Register Oreturn1 = O1;
3486 Register O2UnrollBlock = O2;
3487 Register L0deopt_mode = L0;
3488 Register G4deopt_mode = G4_scratch;
3489 int frame_size_words;
3490 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS);
3491 #if !defined(_LP64) && defined(COMPILER2)
3492 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
3493 #endif
3494 Label cont;
3495
3496 OopMapSet *oop_maps = new OopMapSet();
3497
3498 //
3499 // This is the entry point for code which is returning to a de-optimized
3500 // frame.
3501 // The steps taken by this frame are as follows:
3502 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1)
3503 // and all potentially live registers (at a pollpoint many registers can be live).
3504 //
3505 // - call the C routine: Deoptimization::fetch_unroll_info (this function
3506 // returns information about the number and size of interpreter frames
3507 // which are equivalent to the frame which is being deoptimized)
3508 // - deallocate the unpack frame, restoring only results values. Other
3509 // volatile registers will now be captured in the vframeArray as needed.
3510 // - deallocate the deoptimization frame
3511 // - in a loop using the information returned in the previous step
3512 // push new interpreter frames (take care to propagate the return
3513 // values through each new frame pushed)
3514 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0)
3515 // - call the C routine: Deoptimization::unpack_frames (this function
3516 // lays out values on the interpreter frame which was just created)
3517 // - deallocate the dummy unpack_frame
3518 // - ensure that all the return values are correctly set and then do
3519 // a return to the interpreter entry point
3520 //
3521 // Refer to the following methods for more information:
3522 // - Deoptimization::fetch_unroll_info
3523 // - Deoptimization::unpack_frames
3524
3525 OopMap* map = NULL;
3526
3527 int start = __ offset();
3528
3529 // restore G2, the trampoline destroyed it
3530 __ get_thread();
3531
3532 // On entry we have been called by the deoptimized nmethod with a call that
3533 // replaced the original call (or safepoint polling location) so the deoptimizing
3534 // pc is now in O7. Return values are still in the expected places
3535
3536 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3537 __ ba(cont);
3538 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode);
3539
3540 int exception_offset = __ offset() - start;
3541
3542 // restore G2, the trampoline destroyed it
3543 __ get_thread();
3544
3545 // On entry we have been jumped to by the exception handler (or exception_blob
3546 // for server). O0 contains the exception oop and O7 contains the original
3547 // exception pc. So if we push a frame here it will look to the
3548 // stack walking code (fetch_unroll_info) just like a normal call so
3549 // state will be extracted normally.
3550
3551 // save exception oop in JavaThread and fall through into the
3552 // exception_in_tls case since they are handled in same way except
3553 // for where the pending exception is kept.
3554 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
3555
3556 //
3557 // Vanilla deoptimization with an exception pending in exception_oop
3558 //
3559 int exception_in_tls_offset = __ offset() - start;
3560
3561 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
3562 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3563
3564 // Restore G2_thread
3565 __ get_thread();
3566
3567 #ifdef ASSERT
3568 {
3569 // verify that there is really an exception oop in exception_oop
3570 Label has_exception;
3571 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception);
3572 __ br_notnull_short(Oexception, Assembler::pt, has_exception);
3573 __ stop("no exception in thread");
3574 __ bind(has_exception);
3575
3576 // verify that there is no pending exception
3577 Label no_pending_exception;
3578 Address exception_addr(G2_thread, Thread::pending_exception_offset());
3579 __ ld_ptr(exception_addr, Oexception);
3580 __ br_null_short(Oexception, Assembler::pt, no_pending_exception);
3581 __ stop("must not have pending exception here");
3582 __ bind(no_pending_exception);
3583 }
3584 #endif
3585
3586 __ ba(cont);
3587 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);;
3588
3589 //
3590 // Reexecute entry, similar to c2 uncommon trap
3591 //
3592 int reexecute_offset = __ offset() - start;
3593
3594 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
3595 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3596
3597 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode);
3598
3599 __ bind(cont);
3600
3601 __ set_last_Java_frame(SP, noreg);
3602
3603 // do the call by hand so we can get the oopmap
3604
3605 __ mov(G2_thread, L7_thread_cache);
3606 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type);
3607 __ delayed()->mov(G2_thread, O0);
3608
3609 // Set an oopmap for the call site this describes all our saved volatile registers
3610
3611 oop_maps->add_gc_map( __ offset()-start, map);
3612
3613 __ mov(L7_thread_cache, G2_thread);
3614
3615 __ reset_last_Java_frame();
3616
3617 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers
3618 // so this move will survive
3619
3620 __ mov(L0deopt_mode, G4deopt_mode);
3621
3622 __ mov(O0, O2UnrollBlock->after_save());
3623
3624 RegisterSaver::restore_result_registers(masm);
3625
3626 Label noException;
3627 __ cmp_and_br_short(G4deopt_mode, Deoptimization::Unpack_exception, Assembler::notEqual, Assembler::pt, noException);
3628
3629 // Move the pending exception from exception_oop to Oexception so
3630 // the pending exception will be picked up the interpreter.
3631 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
3632 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
3633 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
3634 __ bind(noException);
3635
3636 // deallocate the deoptimization frame taking care to preserve the return values
3637 __ mov(Oreturn0, Oreturn0->after_save());
3638 __ mov(Oreturn1, Oreturn1->after_save());
3639 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3640 __ restore();
3641
3642 // Allocate new interpreter frame(s) and possible c2i adapter frame
3643
3644 make_new_frames(masm, true);
3645
3646 // push a dummy "unpack_frame" taking care of float return values and
3647 // call Deoptimization::unpack_frames to have the unpacker layout
3648 // information in the interpreter frames just created and then return
3649 // to the interpreter entry point
3650 __ save(SP, -frame_size_words*wordSize, SP);
3651 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr);
3652 #if !defined(_LP64)
3653 #if defined(COMPILER2)
3654 // 32-bit 1-register longs return longs in G1
3655 __ stx(Greturn1, saved_Greturn1_addr);
3656 #endif
3657 __ set_last_Java_frame(SP, noreg);
3658 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode);
3659 #else
3660 // LP64 uses g4 in set_last_Java_frame
3661 __ mov(G4deopt_mode, O1);
3662 __ set_last_Java_frame(SP, G0);
3663 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1);
3664 #endif
3665 __ reset_last_Java_frame();
3666 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
3667
3668 #if !defined(_LP64) && defined(COMPILER2)
3669 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
3670 // I0/I1 if the return value is long.
3671 Label not_long;
3672 __ cmp_and_br_short(O0,T_LONG, Assembler::notEqual, Assembler::pt, not_long);
3673 __ ldd(saved_Greturn1_addr,I0);
3674 __ bind(not_long);
3675 #endif
3676 __ ret();
3677 __ delayed()->restore();
3678
3679 masm->flush();
3680 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words);
3681 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3682 }
3683
3684 #ifdef COMPILER2
3685
3686 //------------------------------generate_uncommon_trap_blob--------------------
3687 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3688 // instead.
generate_uncommon_trap_blob()3689 void SharedRuntime::generate_uncommon_trap_blob() {
3690 // allocate space for the code
3691 ResourceMark rm;
3692 // setup code generation tools
3693 int pad = VerifyThread ? 512 : 0;
3694 #ifdef ASSERT
3695 if (UseStackBanging) {
3696 pad += StackShadowPages*16 + 32;
3697 }
3698 #endif
3699 #ifdef _LP64
3700 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
3701 #else
3702 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
3703 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
3704 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
3705 #endif
3706 MacroAssembler* masm = new MacroAssembler(&buffer);
3707 Register O2UnrollBlock = O2;
3708 Register O2klass_index = O2;
3709
3710 //
3711 // This is the entry point for all traps the compiler takes when it thinks
3712 // it cannot handle further execution of compilation code. The frame is
3713 // deoptimized in these cases and converted into interpreter frames for
3714 // execution
3715 // The steps taken by this frame are as follows:
3716 // - push a fake "unpack_frame"
3717 // - call the C routine Deoptimization::uncommon_trap (this function
3718 // packs the current compiled frame into vframe arrays and returns
3719 // information about the number and size of interpreter frames which
3720 // are equivalent to the frame which is being deoptimized)
3721 // - deallocate the "unpack_frame"
3722 // - deallocate the deoptimization frame
3723 // - in a loop using the information returned in the previous step
3724 // push interpreter frames;
3725 // - create a dummy "unpack_frame"
3726 // - call the C routine: Deoptimization::unpack_frames (this function
3727 // lays out values on the interpreter frame which was just created)
3728 // - deallocate the dummy unpack_frame
3729 // - return to the interpreter entry point
3730 //
3731 // Refer to the following methods for more information:
3732 // - Deoptimization::uncommon_trap
3733 // - Deoptimization::unpack_frame
3734
3735 // the unloaded class index is in O0 (first parameter to this blob)
3736
3737 // push a dummy "unpack_frame"
3738 // and call Deoptimization::uncommon_trap to pack the compiled frame into
3739 // vframe array and return the UnrollBlock information
3740 __ save_frame(0);
3741 __ set_last_Java_frame(SP, noreg);
3742 __ mov(I0, O2klass_index);
3743 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index);
3744 __ reset_last_Java_frame();
3745 __ mov(O0, O2UnrollBlock->after_save());
3746 __ restore();
3747
3748 // deallocate the deoptimized frame taking care to preserve the return values
3749 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3750 __ restore();
3751
3752 // Allocate new interpreter frame(s) and possible c2i adapter frame
3753
3754 make_new_frames(masm, false);
3755
3756 // push a dummy "unpack_frame" taking care of float return values and
3757 // call Deoptimization::unpack_frames to have the unpacker layout
3758 // information in the interpreter frames just created and then return
3759 // to the interpreter entry point
3760 __ save_frame(0);
3761 __ set_last_Java_frame(SP, noreg);
3762 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case
3763 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3);
3764 __ reset_last_Java_frame();
3765 __ ret();
3766 __ delayed()->restore();
3767
3768 masm->flush();
3769 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize);
3770 }
3771
3772 #endif // COMPILER2
3773
3774 //------------------------------generate_handler_blob-------------------
3775 //
3776 // Generate a special Compile2Runtime blob that saves all registers, and sets
3777 // up an OopMap.
3778 //
3779 // This blob is jumped to (via a breakpoint and the signal handler) from a
3780 // safepoint in compiled code. On entry to this blob, O7 contains the
3781 // address in the original nmethod at which we should resume normal execution.
3782 // Thus, this blob looks like a subroutine which must preserve lots of
3783 // registers and return normally. Note that O7 is never register-allocated,
3784 // so it is guaranteed to be free here.
3785 //
3786
3787 // The hardest part of what this blob must do is to save the 64-bit %o
3788 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and
3789 // an interrupt will chop off their heads. Making space in the caller's frame
3790 // first will let us save the 64-bit %o's before save'ing, but we cannot hand
3791 // the adjusted FP off to the GC stack-crawler: this will modify the caller's
3792 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save
3793 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP).
3794 // Tricky, tricky, tricky...
3795
generate_handler_blob(address call_ptr,int poll_type)3796 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) {
3797 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3798
3799 // allocate space for the code
3800 ResourceMark rm;
3801 // setup code generation tools
3802 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3803 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3804 // even larger with TraceJumps
3805 int pad = TraceJumps ? 512 : 0;
3806 CodeBuffer buffer("handler_blob", 1600 + pad, 512);
3807 MacroAssembler* masm = new MacroAssembler(&buffer);
3808 int frame_size_words;
3809 OopMapSet *oop_maps = new OopMapSet();
3810 OopMap* map = NULL;
3811
3812 int start = __ offset();
3813
3814 bool cause_return = (poll_type == POLL_AT_RETURN);
3815 // If this causes a return before the processing, then do a "restore"
3816 if (cause_return) {
3817 __ restore();
3818 } else {
3819 // Make it look like we were called via the poll
3820 // so that frame constructor always sees a valid return address
3821 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7);
3822 __ sub(O7, frame::pc_return_offset, O7);
3823 }
3824
3825 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3826
3827 // setup last_Java_sp (blows G4)
3828 __ set_last_Java_frame(SP, noreg);
3829
3830 // call into the runtime to handle illegal instructions exception
3831 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3832 __ mov(G2_thread, O0);
3833 __ save_thread(L7_thread_cache);
3834 __ call(call_ptr);
3835 __ delayed()->nop();
3836
3837 // Set an oopmap for the call site.
3838 // We need this not only for callee-saved registers, but also for volatile
3839 // registers that the compiler might be keeping live across a safepoint.
3840
3841 oop_maps->add_gc_map( __ offset() - start, map);
3842
3843 __ restore_thread(L7_thread_cache);
3844 // clear last_Java_sp
3845 __ reset_last_Java_frame();
3846
3847 // Check for exceptions
3848 Label pending;
3849
3850 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3851 __ br_notnull_short(O1, Assembler::pn, pending);
3852
3853 RegisterSaver::restore_live_registers(masm);
3854
3855 // We are back the the original state on entry and ready to go.
3856
3857 __ retl();
3858 __ delayed()->nop();
3859
3860 // Pending exception after the safepoint
3861
3862 __ bind(pending);
3863
3864 RegisterSaver::restore_live_registers(masm);
3865
3866 // We are back the the original state on entry.
3867
3868 // Tail-call forward_exception_entry, with the issuing PC in O7,
3869 // so it looks like the original nmethod called forward_exception_entry.
3870 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3871 __ JMP(O0, 0);
3872 __ delayed()->nop();
3873
3874 // -------------
3875 // make sure all code is generated
3876 masm->flush();
3877
3878 // return exception blob
3879 return SafepointBlob::create(&buffer, oop_maps, frame_size_words);
3880 }
3881
3882 //
3883 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3884 //
3885 // Generate a stub that calls into vm to find out the proper destination
3886 // of a java call. All the argument registers are live at this point
3887 // but since this is generic code we don't know what they are and the caller
3888 // must do any gc of the args.
3889 //
generate_resolve_blob(address destination,const char * name)3890 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
3891 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3892
3893 // allocate space for the code
3894 ResourceMark rm;
3895 // setup code generation tools
3896 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3897 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3898 // even larger with TraceJumps
3899 int pad = TraceJumps ? 512 : 0;
3900 CodeBuffer buffer(name, 1600 + pad, 512);
3901 MacroAssembler* masm = new MacroAssembler(&buffer);
3902 int frame_size_words;
3903 OopMapSet *oop_maps = new OopMapSet();
3904 OopMap* map = NULL;
3905
3906 int start = __ offset();
3907
3908 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3909
3910 int frame_complete = __ offset();
3911
3912 // setup last_Java_sp (blows G4)
3913 __ set_last_Java_frame(SP, noreg);
3914
3915 // call into the runtime to handle illegal instructions exception
3916 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3917 __ mov(G2_thread, O0);
3918 __ save_thread(L7_thread_cache);
3919 __ call(destination, relocInfo::runtime_call_type);
3920 __ delayed()->nop();
3921
3922 // O0 contains the address we are going to jump to assuming no exception got installed
3923
3924 // Set an oopmap for the call site.
3925 // We need this not only for callee-saved registers, but also for volatile
3926 // registers that the compiler might be keeping live across a safepoint.
3927
3928 oop_maps->add_gc_map( __ offset() - start, map);
3929
3930 __ restore_thread(L7_thread_cache);
3931 // clear last_Java_sp
3932 __ reset_last_Java_frame();
3933
3934 // Check for exceptions
3935 Label pending;
3936
3937 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3938 __ br_notnull_short(O1, Assembler::pn, pending);
3939
3940 // get the returned Method*
3941
3942 __ get_vm_result_2(G5_method);
3943 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS);
3944
3945 // O0 is where we want to jump, overwrite G3 which is saved and scratch
3946
3947 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS);
3948
3949 RegisterSaver::restore_live_registers(masm);
3950
3951 // We are back the the original state on entry and ready to go.
3952
3953 __ JMP(G3, 0);
3954 __ delayed()->nop();
3955
3956 // Pending exception after the safepoint
3957
3958 __ bind(pending);
3959
3960 RegisterSaver::restore_live_registers(masm);
3961
3962 // We are back the the original state on entry.
3963
3964 // Tail-call forward_exception_entry, with the issuing PC in O7,
3965 // so it looks like the original nmethod called forward_exception_entry.
3966 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3967 __ JMP(O0, 0);
3968 __ delayed()->nop();
3969
3970 // -------------
3971 // make sure all code is generated
3972 masm->flush();
3973
3974 // return the blob
3975 // frame_size_words or bytes??
3976 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
3977 }
3978