1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2
5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4
8
9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6
12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8
15
16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10
19
20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target teams distribute simd private(t_var, vec, s_arr, var)
57 for (int i = 0; i < 2; ++i) {
58 vec[i] = t_var;
59 s_arr[i] = var;
60 }
61 return T();
62 }
63
64 S<float> test;
65 int t_var = 333;
66 int vec[] = {1, 2};
67 S<float> s_arr[] = {1, 2};
68 S<float> var(3);
69
main()70 int main() {
71 static int sivar;
72 #ifdef LAMBDA
73 [&]() {
74 #pragma omp target teams distribute simd private(g, g1, sivar)
75 for (int i = 0; i < 2; ++i) {
76
77 // Skip global, bound tid and loop vars
78 g = 1;
79 g1 = 1;
80 sivar = 2;
81 [&]() {
82 g = 2;
83 g1 = 2;
84 sivar = 4;
85
86 }();
87 }
88 }();
89 return 0;
90 #else
91 #pragma omp target teams distribute simd private(t_var, vec, s_arr, var, sivar)
92 for (int i = 0; i < 2; ++i) {
93 vec[i] = t_var;
94 s_arr[i] = var;
95 sivar += i;
96 }
97 return tmain<int>();
98 #endif
99 }
100
101
102
103 // Skip global, bound tid and loop vars
104
105 // private(s_arr)
106
107 // private(var)
108
109
110
111
112
113 // Skip global, bound tid and loop vars
114
115 // private(s_arr)
116
117
118 // private(var)
119
120
121 #endif
122 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
123 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
124 // CHECK1-NEXT: entry:
125 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
126 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
127 // CHECK1-NEXT: ret void
128 //
129 //
130 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
131 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
132 // CHECK1-NEXT: entry:
133 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
134 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
135 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
136 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
137 // CHECK1-NEXT: ret void
138 //
139 //
140 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
141 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
142 // CHECK1-NEXT: entry:
143 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
144 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
145 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
146 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
147 // CHECK1-NEXT: ret void
148 //
149 //
150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
151 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
152 // CHECK1-NEXT: entry:
153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
154 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
155 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
156 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
157 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
158 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
159 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
160 // CHECK1-NEXT: ret void
161 //
162 //
163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
164 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
165 // CHECK1-NEXT: entry:
166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
169 // CHECK1-NEXT: ret void
170 //
171 //
172 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
173 // CHECK1-SAME: () #[[ATTR0]] {
174 // CHECK1-NEXT: entry:
175 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
176 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
177 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
178 // CHECK1-NEXT: ret void
179 //
180 //
181 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
182 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
183 // CHECK1-NEXT: entry:
184 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
185 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
186 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
187 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
188 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
189 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
190 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
191 // CHECK1-NEXT: ret void
192 //
193 //
194 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
195 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
196 // CHECK1-NEXT: entry:
197 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
198 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
199 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
200 // CHECK1: arraydestroy.body:
201 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
202 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
203 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
204 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
205 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
206 // CHECK1: arraydestroy.done1:
207 // CHECK1-NEXT: ret void
208 //
209 //
210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
211 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
212 // CHECK1-NEXT: entry:
213 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
214 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
215 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
216 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
217 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
218 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
219 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
220 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
221 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
222 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
223 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
224 // CHECK1-NEXT: ret void
225 //
226 //
227 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
228 // CHECK1-SAME: () #[[ATTR0]] {
229 // CHECK1-NEXT: entry:
230 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
231 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
232 // CHECK1-NEXT: ret void
233 //
234 //
235 // CHECK1-LABEL: define {{[^@]+}}@main
236 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
237 // CHECK1-NEXT: entry:
238 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
239 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
240 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
241 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
242 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
243 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
244 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
245 // CHECK1: omp_offload.failed:
246 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]
247 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
248 // CHECK1: omp_offload.cont:
249 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
250 // CHECK1-NEXT: ret i32 [[CALL]]
251 //
252 //
253 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
254 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
255 // CHECK1-NEXT: entry:
256 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
257 // CHECK1-NEXT: ret void
258 //
259 //
260 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
261 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
262 // CHECK1-NEXT: entry:
263 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
264 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
265 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
266 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
267 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
268 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
269 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
270 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
271 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
272 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
273 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
274 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
275 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
276 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
277 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
278 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
279 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
280 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
281 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
282 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
283 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
284 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
285 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
286 // CHECK1: arrayctor.loop:
287 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
288 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
289 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
290 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
291 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
292 // CHECK1: arrayctor.cont:
293 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
294 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
295 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
296 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
297 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
298 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
299 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
300 // CHECK1: cond.true:
301 // CHECK1-NEXT: br label [[COND_END:%.*]]
302 // CHECK1: cond.false:
303 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
304 // CHECK1-NEXT: br label [[COND_END]]
305 // CHECK1: cond.end:
306 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
307 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
308 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
309 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
310 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
311 // CHECK1: omp.inner.for.cond:
312 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
313 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5
314 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
315 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
316 // CHECK1: omp.inner.for.cond.cleanup:
317 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
318 // CHECK1: omp.inner.for.body:
319 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
320 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
321 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
322 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
323 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !5
324 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
325 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
326 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
327 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
328 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
329 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64
330 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]]
331 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8*
332 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
333 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group !5
334 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
335 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !5
336 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
337 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4, !llvm.access.group !5
338 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
339 // CHECK1: omp.body.continue:
340 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
341 // CHECK1: omp.inner.for.inc:
342 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
343 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
344 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
345 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
346 // CHECK1: omp.inner.for.end:
347 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
348 // CHECK1: omp.loop.exit:
349 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
350 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
351 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
352 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
353 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
354 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
355 // CHECK1: .omp.final.then:
356 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
357 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
358 // CHECK1: .omp.final.done:
359 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
360 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
361 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2
362 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
363 // CHECK1: arraydestroy.body:
364 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
365 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
366 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
367 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
368 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
369 // CHECK1: arraydestroy.done7:
370 // CHECK1-NEXT: ret void
371 //
372 //
373 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
374 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat {
375 // CHECK1-NEXT: entry:
376 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
377 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
378 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
379 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
380 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
381 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
382 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
383 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
384 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
385 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
386 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
387 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
388 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
389 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
390 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
391 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
392 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
393 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
394 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
395 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
396 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
397 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
398 // CHECK1: omp_offload.failed:
399 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
400 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
401 // CHECK1: omp_offload.cont:
402 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
403 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
404 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
405 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
406 // CHECK1: arraydestroy.body:
407 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
408 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
409 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
410 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
411 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
412 // CHECK1: arraydestroy.done2:
413 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
414 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
415 // CHECK1-NEXT: ret i32 [[TMP4]]
416 //
417 //
418 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
419 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
420 // CHECK1-NEXT: entry:
421 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
422 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
423 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
424 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
425 // CHECK1-NEXT: ret void
426 //
427 //
428 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
429 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
430 // CHECK1-NEXT: entry:
431 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
432 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
433 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
434 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
435 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
436 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
437 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
438 // CHECK1-NEXT: ret void
439 //
440 //
441 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
442 // CHECK1-SAME: () #[[ATTR4]] {
443 // CHECK1-NEXT: entry:
444 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
445 // CHECK1-NEXT: ret void
446 //
447 //
448 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
449 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
450 // CHECK1-NEXT: entry:
451 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
452 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
453 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
454 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
455 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
456 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
457 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
458 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
459 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
460 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
461 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
462 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
463 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
464 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
465 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
466 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
467 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
468 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
469 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
470 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
471 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
472 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
473 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
474 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
475 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
476 // CHECK1: arrayctor.loop:
477 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
478 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
479 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
480 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
481 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
482 // CHECK1: arrayctor.cont:
483 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
484 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
485 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
486 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
487 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
488 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
489 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
490 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
491 // CHECK1: cond.true:
492 // CHECK1-NEXT: br label [[COND_END:%.*]]
493 // CHECK1: cond.false:
494 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
495 // CHECK1-NEXT: br label [[COND_END]]
496 // CHECK1: cond.end:
497 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
498 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
499 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
500 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
501 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
502 // CHECK1: omp.inner.for.cond:
503 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
504 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
505 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
506 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
507 // CHECK1: omp.inner.for.cond.cleanup:
508 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
509 // CHECK1: omp.inner.for.body:
510 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
511 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
512 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
513 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
514 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11
515 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
516 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
517 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
518 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
519 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !11
520 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
521 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
522 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]]
523 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8*
524 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
525 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !11
526 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
527 // CHECK1: omp.body.continue:
528 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
529 // CHECK1: omp.inner.for.inc:
530 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
531 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
532 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
533 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
534 // CHECK1: omp.inner.for.end:
535 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
536 // CHECK1: omp.loop.exit:
537 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
538 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
539 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
540 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
541 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
542 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
543 // CHECK1: .omp.final.then:
544 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
545 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
546 // CHECK1: .omp.final.done:
547 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
548 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
549 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2
550 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
551 // CHECK1: arraydestroy.body:
552 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
553 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
554 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
555 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
556 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
557 // CHECK1: arraydestroy.done8:
558 // CHECK1-NEXT: ret void
559 //
560 //
561 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
562 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
563 // CHECK1-NEXT: entry:
564 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
565 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
566 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
567 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
568 // CHECK1-NEXT: ret void
569 //
570 //
571 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
572 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
573 // CHECK1-NEXT: entry:
574 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
575 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
576 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
577 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
578 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
579 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
580 // CHECK1-NEXT: ret void
581 //
582 //
583 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
584 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
585 // CHECK1-NEXT: entry:
586 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
587 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
588 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
589 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
590 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
591 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
592 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
593 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
594 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
595 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
596 // CHECK1-NEXT: ret void
597 //
598 //
599 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
600 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
601 // CHECK1-NEXT: entry:
602 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
603 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
604 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
605 // CHECK1-NEXT: ret void
606 //
607 //
608 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
609 // CHECK1-SAME: () #[[ATTR0]] {
610 // CHECK1-NEXT: entry:
611 // CHECK1-NEXT: call void @__cxx_global_var_init()
612 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
613 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
614 // CHECK1-NEXT: ret void
615 //
616 //
617 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
618 // CHECK1-SAME: () #[[ATTR0]] {
619 // CHECK1-NEXT: entry:
620 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
621 // CHECK1-NEXT: ret void
622 //
623 //
624 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
625 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
626 // CHECK2-NEXT: entry:
627 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
628 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
629 // CHECK2-NEXT: ret void
630 //
631 //
632 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
633 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
634 // CHECK2-NEXT: entry:
635 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
636 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
637 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
638 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
639 // CHECK2-NEXT: ret void
640 //
641 //
642 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
643 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
644 // CHECK2-NEXT: entry:
645 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
646 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
647 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
648 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
649 // CHECK2-NEXT: ret void
650 //
651 //
652 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
653 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
654 // CHECK2-NEXT: entry:
655 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
656 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
657 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
658 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
659 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
660 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
661 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4
662 // CHECK2-NEXT: ret void
663 //
664 //
665 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
666 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
667 // CHECK2-NEXT: entry:
668 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
669 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
670 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
671 // CHECK2-NEXT: ret void
672 //
673 //
674 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
675 // CHECK2-SAME: () #[[ATTR0]] {
676 // CHECK2-NEXT: entry:
677 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
678 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
679 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
680 // CHECK2-NEXT: ret void
681 //
682 //
683 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
684 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
685 // CHECK2-NEXT: entry:
686 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
687 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
688 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
689 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
690 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
691 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
692 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
693 // CHECK2-NEXT: ret void
694 //
695 //
696 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
697 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
698 // CHECK2-NEXT: entry:
699 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
700 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
701 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
702 // CHECK2: arraydestroy.body:
703 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
704 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
705 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
706 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
707 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
708 // CHECK2: arraydestroy.done1:
709 // CHECK2-NEXT: ret void
710 //
711 //
712 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
713 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
714 // CHECK2-NEXT: entry:
715 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
716 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
717 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
718 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
719 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
720 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
721 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
722 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
723 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
724 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
725 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
726 // CHECK2-NEXT: ret void
727 //
728 //
729 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
730 // CHECK2-SAME: () #[[ATTR0]] {
731 // CHECK2-NEXT: entry:
732 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
733 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
734 // CHECK2-NEXT: ret void
735 //
736 //
737 // CHECK2-LABEL: define {{[^@]+}}@main
738 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
739 // CHECK2-NEXT: entry:
740 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
741 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
742 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
743 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
744 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
745 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
746 // CHECK2-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
747 // CHECK2: omp_offload.failed:
748 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]
749 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
750 // CHECK2: omp_offload.cont:
751 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
752 // CHECK2-NEXT: ret i32 [[CALL]]
753 //
754 //
755 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
756 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
757 // CHECK2-NEXT: entry:
758 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
759 // CHECK2-NEXT: ret void
760 //
761 //
762 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
763 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
764 // CHECK2-NEXT: entry:
765 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
766 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
767 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
768 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
769 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
770 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
771 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
772 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
773 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
774 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
775 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
776 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
777 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
778 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
779 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
780 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
781 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
782 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
783 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
784 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
785 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
786 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
787 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
788 // CHECK2: arrayctor.loop:
789 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
790 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
791 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
792 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
793 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
794 // CHECK2: arrayctor.cont:
795 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
796 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
797 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
798 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
799 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
800 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
801 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
802 // CHECK2: cond.true:
803 // CHECK2-NEXT: br label [[COND_END:%.*]]
804 // CHECK2: cond.false:
805 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
806 // CHECK2-NEXT: br label [[COND_END]]
807 // CHECK2: cond.end:
808 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
809 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
810 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
811 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
812 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
813 // CHECK2: omp.inner.for.cond:
814 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
815 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5
816 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
817 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
818 // CHECK2: omp.inner.for.cond.cleanup:
819 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
820 // CHECK2: omp.inner.for.body:
821 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
822 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
823 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
824 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
825 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !5
826 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
827 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
828 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
829 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
830 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
831 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64
832 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]]
833 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8*
834 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
835 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group !5
836 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5
837 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !5
838 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
839 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4, !llvm.access.group !5
840 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
841 // CHECK2: omp.body.continue:
842 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
843 // CHECK2: omp.inner.for.inc:
844 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
845 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
846 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
847 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
848 // CHECK2: omp.inner.for.end:
849 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
850 // CHECK2: omp.loop.exit:
851 // CHECK2-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
852 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
853 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
854 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
855 // CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
856 // CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
857 // CHECK2: .omp.final.then:
858 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
859 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
860 // CHECK2: .omp.final.done:
861 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
862 // CHECK2-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
863 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2
864 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
865 // CHECK2: arraydestroy.body:
866 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
867 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
868 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
869 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
870 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
871 // CHECK2: arraydestroy.done7:
872 // CHECK2-NEXT: ret void
873 //
874 //
875 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
876 // CHECK2-SAME: () #[[ATTR7:[0-9]+]] comdat {
877 // CHECK2-NEXT: entry:
878 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
879 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
880 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
881 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
882 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
883 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
884 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
885 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
886 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
887 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4
888 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
889 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
890 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
891 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
892 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
893 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
894 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
895 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
896 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
897 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
898 // CHECK2-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
899 // CHECK2-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
900 // CHECK2: omp_offload.failed:
901 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
902 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
903 // CHECK2: omp_offload.cont:
904 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
905 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
906 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
907 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
908 // CHECK2: arraydestroy.body:
909 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
910 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
911 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
912 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
913 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
914 // CHECK2: arraydestroy.done2:
915 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
916 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
917 // CHECK2-NEXT: ret i32 [[TMP4]]
918 //
919 //
920 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
921 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
922 // CHECK2-NEXT: entry:
923 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
924 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
925 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
926 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
927 // CHECK2-NEXT: ret void
928 //
929 //
930 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
931 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
932 // CHECK2-NEXT: entry:
933 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
934 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
935 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
936 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
937 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
938 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
939 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
940 // CHECK2-NEXT: ret void
941 //
942 //
943 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
944 // CHECK2-SAME: () #[[ATTR4]] {
945 // CHECK2-NEXT: entry:
946 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
947 // CHECK2-NEXT: ret void
948 //
949 //
950 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
951 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
952 // CHECK2-NEXT: entry:
953 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
954 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
955 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
956 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
957 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
958 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
959 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
960 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
961 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
962 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
963 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
964 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
965 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
966 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
967 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
968 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
969 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
970 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
971 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
972 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
973 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
974 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
975 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
976 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
977 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
978 // CHECK2: arrayctor.loop:
979 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
980 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
981 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
982 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
983 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
984 // CHECK2: arrayctor.cont:
985 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
986 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
987 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
988 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
989 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
990 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
991 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
992 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
993 // CHECK2: cond.true:
994 // CHECK2-NEXT: br label [[COND_END:%.*]]
995 // CHECK2: cond.false:
996 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
997 // CHECK2-NEXT: br label [[COND_END]]
998 // CHECK2: cond.end:
999 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1000 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1001 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1002 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1003 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1004 // CHECK2: omp.inner.for.cond:
1005 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
1006 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
1007 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1008 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1009 // CHECK2: omp.inner.for.cond.cleanup:
1010 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1011 // CHECK2: omp.inner.for.body:
1012 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
1013 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1014 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1015 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
1016 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11
1017 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
1018 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
1019 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
1020 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
1021 // CHECK2-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !11
1022 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
1023 // CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
1024 // CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]]
1025 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8*
1026 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
1027 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !11
1028 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1029 // CHECK2: omp.body.continue:
1030 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1031 // CHECK2: omp.inner.for.inc:
1032 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
1033 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
1034 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
1035 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
1036 // CHECK2: omp.inner.for.end:
1037 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1038 // CHECK2: omp.loop.exit:
1039 // CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1040 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
1041 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
1042 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1043 // CHECK2-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1044 // CHECK2-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1045 // CHECK2: .omp.final.then:
1046 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
1047 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1048 // CHECK2: .omp.final.done:
1049 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1050 // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1051 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2
1052 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1053 // CHECK2: arraydestroy.body:
1054 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1055 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1056 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1057 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
1058 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
1059 // CHECK2: arraydestroy.done8:
1060 // CHECK2-NEXT: ret void
1061 //
1062 //
1063 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1064 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1065 // CHECK2-NEXT: entry:
1066 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1067 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1068 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1069 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1070 // CHECK2-NEXT: ret void
1071 //
1072 //
1073 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1074 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1075 // CHECK2-NEXT: entry:
1076 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1077 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1078 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1079 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1080 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1081 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1082 // CHECK2-NEXT: ret void
1083 //
1084 //
1085 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1086 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1087 // CHECK2-NEXT: entry:
1088 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1089 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1090 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1091 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1092 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1093 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1094 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1095 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1096 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1097 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1098 // CHECK2-NEXT: ret void
1099 //
1100 //
1101 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1102 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1103 // CHECK2-NEXT: entry:
1104 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1105 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1106 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1107 // CHECK2-NEXT: ret void
1108 //
1109 //
1110 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
1111 // CHECK2-SAME: () #[[ATTR0]] {
1112 // CHECK2-NEXT: entry:
1113 // CHECK2-NEXT: call void @__cxx_global_var_init()
1114 // CHECK2-NEXT: call void @__cxx_global_var_init.1()
1115 // CHECK2-NEXT: call void @__cxx_global_var_init.2()
1116 // CHECK2-NEXT: ret void
1117 //
1118 //
1119 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1120 // CHECK2-SAME: () #[[ATTR0]] {
1121 // CHECK2-NEXT: entry:
1122 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
1123 // CHECK2-NEXT: ret void
1124 //
1125 //
1126 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
1127 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1128 // CHECK3-NEXT: entry:
1129 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
1130 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1131 // CHECK3-NEXT: ret void
1132 //
1133 //
1134 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1135 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1136 // CHECK3-NEXT: entry:
1137 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1138 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1139 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1140 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1141 // CHECK3-NEXT: ret void
1142 //
1143 //
1144 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1145 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1146 // CHECK3-NEXT: entry:
1147 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1148 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1149 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1150 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1151 // CHECK3-NEXT: ret void
1152 //
1153 //
1154 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1155 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1156 // CHECK3-NEXT: entry:
1157 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1158 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1159 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1160 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1161 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1162 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1163 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
1164 // CHECK3-NEXT: ret void
1165 //
1166 //
1167 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1168 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1169 // CHECK3-NEXT: entry:
1170 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1171 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1172 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1173 // CHECK3-NEXT: ret void
1174 //
1175 //
1176 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1177 // CHECK3-SAME: () #[[ATTR0]] {
1178 // CHECK3-NEXT: entry:
1179 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
1180 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
1181 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1182 // CHECK3-NEXT: ret void
1183 //
1184 //
1185 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1186 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1187 // CHECK3-NEXT: entry:
1188 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1189 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1190 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1191 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1192 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1193 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1194 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1195 // CHECK3-NEXT: ret void
1196 //
1197 //
1198 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1199 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
1200 // CHECK3-NEXT: entry:
1201 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1202 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1203 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1204 // CHECK3: arraydestroy.body:
1205 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1206 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1207 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1208 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1209 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1210 // CHECK3: arraydestroy.done1:
1211 // CHECK3-NEXT: ret void
1212 //
1213 //
1214 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1215 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1216 // CHECK3-NEXT: entry:
1217 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1218 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1219 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1220 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1221 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1222 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1223 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1224 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1225 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1226 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1227 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
1228 // CHECK3-NEXT: ret void
1229 //
1230 //
1231 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1232 // CHECK3-SAME: () #[[ATTR0]] {
1233 // CHECK3-NEXT: entry:
1234 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
1235 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1236 // CHECK3-NEXT: ret void
1237 //
1238 //
1239 // CHECK3-LABEL: define {{[^@]+}}@main
1240 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1241 // CHECK3-NEXT: entry:
1242 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1243 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1244 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1245 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
1246 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
1247 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
1248 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1249 // CHECK3: omp_offload.failed:
1250 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]
1251 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1252 // CHECK3: omp_offload.cont:
1253 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
1254 // CHECK3-NEXT: ret i32 [[CALL]]
1255 //
1256 //
1257 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
1258 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
1259 // CHECK3-NEXT: entry:
1260 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1261 // CHECK3-NEXT: ret void
1262 //
1263 //
1264 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1265 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
1266 // CHECK3-NEXT: entry:
1267 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1268 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1269 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1270 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1271 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1272 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1273 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1274 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1275 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1276 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1277 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1278 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1279 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1280 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1281 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1282 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1283 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1284 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1285 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1286 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1287 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1288 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1289 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1290 // CHECK3: arrayctor.loop:
1291 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1292 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1293 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1294 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1295 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1296 // CHECK3: arrayctor.cont:
1297 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1298 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1299 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1300 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1301 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1302 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1303 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1304 // CHECK3: cond.true:
1305 // CHECK3-NEXT: br label [[COND_END:%.*]]
1306 // CHECK3: cond.false:
1307 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1308 // CHECK3-NEXT: br label [[COND_END]]
1309 // CHECK3: cond.end:
1310 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1311 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1312 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1313 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1314 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1315 // CHECK3: omp.inner.for.cond:
1316 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1317 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
1318 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1319 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1320 // CHECK3: omp.inner.for.cond.cleanup:
1321 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1322 // CHECK3: omp.inner.for.body:
1323 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1324 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1325 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1326 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
1327 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6
1328 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1329 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
1330 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
1331 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1332 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]]
1333 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
1334 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1335 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group !6
1336 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1337 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !6
1338 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
1339 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !6
1340 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1341 // CHECK3: omp.body.continue:
1342 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1343 // CHECK3: omp.inner.for.inc:
1344 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1345 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
1346 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1347 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1348 // CHECK3: omp.inner.for.end:
1349 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1350 // CHECK3: omp.loop.exit:
1351 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1352 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
1353 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
1354 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1355 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
1356 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1357 // CHECK3: .omp.final.then:
1358 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1359 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1360 // CHECK3: .omp.final.done:
1361 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1362 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1363 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
1364 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1365 // CHECK3: arraydestroy.body:
1366 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1367 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1368 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1369 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1370 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1371 // CHECK3: arraydestroy.done6:
1372 // CHECK3-NEXT: ret void
1373 //
1374 //
1375 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1376 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] comdat {
1377 // CHECK3-NEXT: entry:
1378 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1379 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1380 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1381 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1382 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1383 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
1384 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1385 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1386 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1387 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
1388 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1389 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1390 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1391 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
1392 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1393 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
1394 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1395 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1396 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
1397 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
1398 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
1399 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1400 // CHECK3: omp_offload.failed:
1401 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
1402 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1403 // CHECK3: omp_offload.cont:
1404 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1405 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1406 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1407 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1408 // CHECK3: arraydestroy.body:
1409 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1410 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1411 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1412 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1413 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1414 // CHECK3: arraydestroy.done2:
1415 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1416 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
1417 // CHECK3-NEXT: ret i32 [[TMP4]]
1418 //
1419 //
1420 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1421 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1422 // CHECK3-NEXT: entry:
1423 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1424 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1425 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1426 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1427 // CHECK3-NEXT: ret void
1428 //
1429 //
1430 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1431 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1432 // CHECK3-NEXT: entry:
1433 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1434 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1435 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1436 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1437 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1438 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1439 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
1440 // CHECK3-NEXT: ret void
1441 //
1442 //
1443 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1444 // CHECK3-SAME: () #[[ATTR4]] {
1445 // CHECK3-NEXT: entry:
1446 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
1447 // CHECK3-NEXT: ret void
1448 //
1449 //
1450 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1451 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
1452 // CHECK3-NEXT: entry:
1453 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1454 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1455 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1456 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1457 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1458 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1459 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1460 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1461 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1462 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1463 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1464 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1465 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1466 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
1467 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1468 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1469 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1470 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1471 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1472 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1473 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1474 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1475 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1476 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1477 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1478 // CHECK3: arrayctor.loop:
1479 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1480 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1481 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1482 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1483 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1484 // CHECK3: arrayctor.cont:
1485 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
1486 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
1487 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1488 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1489 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1490 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1491 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1492 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1493 // CHECK3: cond.true:
1494 // CHECK3-NEXT: br label [[COND_END:%.*]]
1495 // CHECK3: cond.false:
1496 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1497 // CHECK3-NEXT: br label [[COND_END]]
1498 // CHECK3: cond.end:
1499 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1500 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1501 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1502 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1503 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1504 // CHECK3: omp.inner.for.cond:
1505 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1506 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
1507 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1508 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1509 // CHECK3: omp.inner.for.cond.cleanup:
1510 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1511 // CHECK3: omp.inner.for.body:
1512 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1513 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1514 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1515 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
1516 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !12
1517 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12
1518 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
1519 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
1520 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !12
1521 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12
1522 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]]
1523 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
1524 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
1525 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !12
1526 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1527 // CHECK3: omp.body.continue:
1528 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1529 // CHECK3: omp.inner.for.inc:
1530 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1531 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
1532 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
1533 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
1534 // CHECK3: omp.inner.for.end:
1535 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1536 // CHECK3: omp.loop.exit:
1537 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1538 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
1539 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
1540 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1541 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1542 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1543 // CHECK3: .omp.final.then:
1544 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1545 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1546 // CHECK3: .omp.final.done:
1547 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1548 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1549 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
1550 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1551 // CHECK3: arraydestroy.body:
1552 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1553 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1554 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1555 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
1556 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1557 // CHECK3: arraydestroy.done7:
1558 // CHECK3-NEXT: ret void
1559 //
1560 //
1561 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1562 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1563 // CHECK3-NEXT: entry:
1564 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1565 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1566 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1567 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1568 // CHECK3-NEXT: ret void
1569 //
1570 //
1571 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1572 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1573 // CHECK3-NEXT: entry:
1574 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1575 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1576 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1577 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1578 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1579 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1580 // CHECK3-NEXT: ret void
1581 //
1582 //
1583 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1584 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1585 // CHECK3-NEXT: entry:
1586 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1587 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1588 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1589 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1590 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1591 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1592 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1593 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1594 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1595 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1596 // CHECK3-NEXT: ret void
1597 //
1598 //
1599 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1600 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1601 // CHECK3-NEXT: entry:
1602 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1603 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1604 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1605 // CHECK3-NEXT: ret void
1606 //
1607 //
1608 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
1609 // CHECK3-SAME: () #[[ATTR0]] {
1610 // CHECK3-NEXT: entry:
1611 // CHECK3-NEXT: call void @__cxx_global_var_init()
1612 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
1613 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
1614 // CHECK3-NEXT: ret void
1615 //
1616 //
1617 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1618 // CHECK3-SAME: () #[[ATTR0]] {
1619 // CHECK3-NEXT: entry:
1620 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
1621 // CHECK3-NEXT: ret void
1622 //
1623 //
1624 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init
1625 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
1626 // CHECK4-NEXT: entry:
1627 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
1628 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1629 // CHECK4-NEXT: ret void
1630 //
1631 //
1632 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1633 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1634 // CHECK4-NEXT: entry:
1635 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1636 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1637 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1638 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1639 // CHECK4-NEXT: ret void
1640 //
1641 //
1642 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1643 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1644 // CHECK4-NEXT: entry:
1645 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1646 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1647 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1648 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1649 // CHECK4-NEXT: ret void
1650 //
1651 //
1652 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1653 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1654 // CHECK4-NEXT: entry:
1655 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1656 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1657 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1658 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1659 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1660 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1661 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4
1662 // CHECK4-NEXT: ret void
1663 //
1664 //
1665 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1666 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1667 // CHECK4-NEXT: entry:
1668 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1669 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1670 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1671 // CHECK4-NEXT: ret void
1672 //
1673 //
1674 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1675 // CHECK4-SAME: () #[[ATTR0]] {
1676 // CHECK4-NEXT: entry:
1677 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
1678 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
1679 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1680 // CHECK4-NEXT: ret void
1681 //
1682 //
1683 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1684 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1685 // CHECK4-NEXT: entry:
1686 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1687 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1688 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1689 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1690 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1691 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1692 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1693 // CHECK4-NEXT: ret void
1694 //
1695 //
1696 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1697 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
1698 // CHECK4-NEXT: entry:
1699 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1700 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1701 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1702 // CHECK4: arraydestroy.body:
1703 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1704 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1705 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1706 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1707 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1708 // CHECK4: arraydestroy.done1:
1709 // CHECK4-NEXT: ret void
1710 //
1711 //
1712 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1713 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1714 // CHECK4-NEXT: entry:
1715 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1716 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1717 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1718 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1719 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1720 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1721 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1722 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1723 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1724 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1725 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
1726 // CHECK4-NEXT: ret void
1727 //
1728 //
1729 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1730 // CHECK4-SAME: () #[[ATTR0]] {
1731 // CHECK4-NEXT: entry:
1732 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
1733 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1734 // CHECK4-NEXT: ret void
1735 //
1736 //
1737 // CHECK4-LABEL: define {{[^@]+}}@main
1738 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
1739 // CHECK4-NEXT: entry:
1740 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1741 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
1742 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
1743 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
1744 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
1745 // CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
1746 // CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1747 // CHECK4: omp_offload.failed:
1748 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]
1749 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
1750 // CHECK4: omp_offload.cont:
1751 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
1752 // CHECK4-NEXT: ret i32 [[CALL]]
1753 //
1754 //
1755 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
1756 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] {
1757 // CHECK4-NEXT: entry:
1758 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1759 // CHECK4-NEXT: ret void
1760 //
1761 //
1762 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
1763 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
1764 // CHECK4-NEXT: entry:
1765 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1766 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1767 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1768 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
1769 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1770 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1771 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1772 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1773 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1774 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1775 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1776 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1777 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1778 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
1779 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1780 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1781 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1782 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1783 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1784 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1785 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1786 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1787 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1788 // CHECK4: arrayctor.loop:
1789 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1790 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1791 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1792 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1793 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1794 // CHECK4: arrayctor.cont:
1795 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1796 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1797 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1798 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1799 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1800 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1801 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1802 // CHECK4: cond.true:
1803 // CHECK4-NEXT: br label [[COND_END:%.*]]
1804 // CHECK4: cond.false:
1805 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1806 // CHECK4-NEXT: br label [[COND_END]]
1807 // CHECK4: cond.end:
1808 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1809 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1810 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1811 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1812 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1813 // CHECK4: omp.inner.for.cond:
1814 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1815 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
1816 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1817 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1818 // CHECK4: omp.inner.for.cond.cleanup:
1819 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1820 // CHECK4: omp.inner.for.body:
1821 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1822 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1823 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1824 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
1825 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6
1826 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1827 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
1828 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
1829 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1830 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]]
1831 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
1832 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1833 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group !6
1834 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
1835 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !6
1836 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
1837 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !6
1838 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1839 // CHECK4: omp.body.continue:
1840 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1841 // CHECK4: omp.inner.for.inc:
1842 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1843 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
1844 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
1845 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1846 // CHECK4: omp.inner.for.end:
1847 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1848 // CHECK4: omp.loop.exit:
1849 // CHECK4-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1850 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
1851 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
1852 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1853 // CHECK4-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
1854 // CHECK4-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1855 // CHECK4: .omp.final.then:
1856 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
1857 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
1858 // CHECK4: .omp.final.done:
1859 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1860 // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1861 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
1862 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1863 // CHECK4: arraydestroy.body:
1864 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1865 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1866 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1867 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1868 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1869 // CHECK4: arraydestroy.done6:
1870 // CHECK4-NEXT: ret void
1871 //
1872 //
1873 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1874 // CHECK4-SAME: () #[[ATTR7:[0-9]+]] comdat {
1875 // CHECK4-NEXT: entry:
1876 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1877 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1878 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1879 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1880 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1881 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
1882 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
1883 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1884 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1885 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4
1886 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1887 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1888 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1889 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
1890 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1891 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
1892 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1893 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1894 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
1895 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
1896 // CHECK4-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
1897 // CHECK4-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1898 // CHECK4: omp_offload.failed:
1899 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
1900 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
1901 // CHECK4: omp_offload.cont:
1902 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
1903 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1904 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1905 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1906 // CHECK4: arraydestroy.body:
1907 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1908 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1909 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1910 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1911 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1912 // CHECK4: arraydestroy.done2:
1913 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1914 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
1915 // CHECK4-NEXT: ret i32 [[TMP4]]
1916 //
1917 //
1918 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1919 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1920 // CHECK4-NEXT: entry:
1921 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1922 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1923 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1924 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1925 // CHECK4-NEXT: ret void
1926 //
1927 //
1928 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1929 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1930 // CHECK4-NEXT: entry:
1931 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1932 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1933 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1934 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1935 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1936 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1937 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
1938 // CHECK4-NEXT: ret void
1939 //
1940 //
1941 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1942 // CHECK4-SAME: () #[[ATTR4]] {
1943 // CHECK4-NEXT: entry:
1944 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
1945 // CHECK4-NEXT: ret void
1946 //
1947 //
1948 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
1949 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
1950 // CHECK4-NEXT: entry:
1951 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1952 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1953 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1954 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
1955 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1956 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1957 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1958 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1959 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1960 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1961 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1962 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1963 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1964 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
1965 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
1966 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1967 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1968 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1969 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1970 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1971 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1972 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1973 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1974 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1975 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1976 // CHECK4: arrayctor.loop:
1977 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1978 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1979 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1980 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1981 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1982 // CHECK4: arrayctor.cont:
1983 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
1984 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
1985 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1986 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1987 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1988 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1989 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1990 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1991 // CHECK4: cond.true:
1992 // CHECK4-NEXT: br label [[COND_END:%.*]]
1993 // CHECK4: cond.false:
1994 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1995 // CHECK4-NEXT: br label [[COND_END]]
1996 // CHECK4: cond.end:
1997 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1998 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1999 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2000 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2001 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2002 // CHECK4: omp.inner.for.cond:
2003 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
2004 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
2005 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2006 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2007 // CHECK4: omp.inner.for.cond.cleanup:
2008 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2009 // CHECK4: omp.inner.for.body:
2010 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
2011 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2012 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2013 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
2014 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !12
2015 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12
2016 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
2017 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
2018 // CHECK4-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !12
2019 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12
2020 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]]
2021 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
2022 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
2023 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !12
2024 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2025 // CHECK4: omp.body.continue:
2026 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2027 // CHECK4: omp.inner.for.inc:
2028 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
2029 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
2030 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
2031 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
2032 // CHECK4: omp.inner.for.end:
2033 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2034 // CHECK4: omp.loop.exit:
2035 // CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2036 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
2037 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
2038 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2039 // CHECK4-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
2040 // CHECK4-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2041 // CHECK4: .omp.final.then:
2042 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
2043 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
2044 // CHECK4: .omp.final.done:
2045 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2046 // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2047 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
2048 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2049 // CHECK4: arraydestroy.body:
2050 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2051 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2052 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2053 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
2054 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
2055 // CHECK4: arraydestroy.done7:
2056 // CHECK4-NEXT: ret void
2057 //
2058 //
2059 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2060 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2061 // CHECK4-NEXT: entry:
2062 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2063 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2064 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2065 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2066 // CHECK4-NEXT: ret void
2067 //
2068 //
2069 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2070 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2071 // CHECK4-NEXT: entry:
2072 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2073 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2074 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2075 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2076 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2077 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2078 // CHECK4-NEXT: ret void
2079 //
2080 //
2081 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2082 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2083 // CHECK4-NEXT: entry:
2084 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2085 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2086 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2087 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2088 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2089 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2090 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2091 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2092 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2093 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2094 // CHECK4-NEXT: ret void
2095 //
2096 //
2097 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2098 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2099 // CHECK4-NEXT: entry:
2100 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2101 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2102 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2103 // CHECK4-NEXT: ret void
2104 //
2105 //
2106 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
2107 // CHECK4-SAME: () #[[ATTR0]] {
2108 // CHECK4-NEXT: entry:
2109 // CHECK4-NEXT: call void @__cxx_global_var_init()
2110 // CHECK4-NEXT: call void @__cxx_global_var_init.1()
2111 // CHECK4-NEXT: call void @__cxx_global_var_init.2()
2112 // CHECK4-NEXT: ret void
2113 //
2114 //
2115 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2116 // CHECK4-SAME: () #[[ATTR0]] {
2117 // CHECK4-NEXT: entry:
2118 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
2119 // CHECK4-NEXT: ret void
2120 //
2121 //
2122 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
2123 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
2124 // CHECK5-NEXT: entry:
2125 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2126 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2127 // CHECK5-NEXT: ret void
2128 //
2129 //
2130 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2131 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2132 // CHECK5-NEXT: entry:
2133 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2134 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2135 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2136 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2137 // CHECK5-NEXT: ret void
2138 //
2139 //
2140 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2141 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2142 // CHECK5-NEXT: entry:
2143 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2144 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2145 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2146 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2147 // CHECK5-NEXT: ret void
2148 //
2149 //
2150 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2151 // CHECK5-SAME: () #[[ATTR0]] {
2152 // CHECK5-NEXT: entry:
2153 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
2154 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
2155 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2156 // CHECK5-NEXT: ret void
2157 //
2158 //
2159 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2160 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2161 // CHECK5-NEXT: entry:
2162 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2163 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2164 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2165 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2166 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2167 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2168 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2169 // CHECK5-NEXT: ret void
2170 //
2171 //
2172 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2173 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2174 // CHECK5-NEXT: entry:
2175 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2176 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2177 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2178 // CHECK5: arraydestroy.body:
2179 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2180 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2181 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2182 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2183 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2184 // CHECK5: arraydestroy.done1:
2185 // CHECK5-NEXT: ret void
2186 //
2187 //
2188 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2189 // CHECK5-SAME: () #[[ATTR0]] {
2190 // CHECK5-NEXT: entry:
2191 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2192 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2193 // CHECK5-NEXT: ret void
2194 //
2195 //
2196 // CHECK5-LABEL: define {{[^@]+}}@main
2197 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
2198 // CHECK5-NEXT: entry:
2199 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2200 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2201 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2202 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2203 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2204 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2205 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2206 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2207 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2208 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2209 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2210 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
2211 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2212 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2213 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2214 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
2215 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2216 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
2217 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2218 // CHECK5: arrayctor.loop:
2219 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2220 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2221 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
2222 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2223 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2224 // CHECK5: arrayctor.cont:
2225 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
2226 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2227 // CHECK5: omp.inner.for.cond:
2228 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2229 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
2230 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2231 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2232 // CHECK5: omp.inner.for.cond.cleanup:
2233 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2234 // CHECK5: omp.inner.for.body:
2235 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2236 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2237 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2238 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
2239 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2
2240 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2241 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
2242 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
2243 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
2244 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2245 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
2246 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]]
2247 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
2248 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
2249 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2
2250 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2251 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
2252 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
2253 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2
2254 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2255 // CHECK5: omp.body.continue:
2256 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2257 // CHECK5: omp.inner.for.inc:
2258 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2259 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
2260 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2261 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2262 // CHECK5: omp.inner.for.end:
2263 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
2264 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2265 // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2266 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2
2267 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2268 // CHECK5: arraydestroy.body:
2269 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2270 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2271 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2272 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
2273 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
2274 // CHECK5: arraydestroy.done6:
2275 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
2276 // CHECK5-NEXT: ret i32 [[CALL]]
2277 //
2278 //
2279 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2280 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
2281 // CHECK5-NEXT: entry:
2282 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2283 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2284 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2285 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2286 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2287 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
2288 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2289 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
2290 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2291 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2292 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2293 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2294 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2295 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2296 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2297 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
2298 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
2299 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2300 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
2301 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2302 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
2303 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
2304 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
2305 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
2306 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
2307 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
2308 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
2309 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2310 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2311 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2312 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
2313 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2314 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2315 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2316 // CHECK5: arrayctor.loop:
2317 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2318 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2319 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
2320 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2321 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2322 // CHECK5: arrayctor.cont:
2323 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
2324 // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
2325 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2326 // CHECK5: omp.inner.for.cond:
2327 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2328 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
2329 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
2330 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2331 // CHECK5: omp.inner.for.cond.cleanup:
2332 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2333 // CHECK5: omp.inner.for.body:
2334 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2335 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
2336 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2337 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
2338 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6
2339 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
2340 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
2341 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]]
2342 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
2343 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6
2344 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
2345 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64
2346 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
2347 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
2348 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
2349 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6
2350 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2351 // CHECK5: omp.body.continue:
2352 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2353 // CHECK5: omp.inner.for.inc:
2354 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2355 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1
2356 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2357 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2358 // CHECK5: omp.inner.for.end:
2359 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
2360 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2361 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2362 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
2363 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2364 // CHECK5: arraydestroy.body:
2365 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2366 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2367 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2368 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2369 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2370 // CHECK5: arraydestroy.done11:
2371 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
2372 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2373 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
2374 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
2375 // CHECK5: arraydestroy.body13:
2376 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
2377 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
2378 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
2379 // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
2380 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
2381 // CHECK5: arraydestroy.done17:
2382 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2383 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
2384 // CHECK5-NEXT: ret i32 [[TMP14]]
2385 //
2386 //
2387 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2388 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2389 // CHECK5-NEXT: entry:
2390 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2391 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2392 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2393 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2394 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2395 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2396 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4
2397 // CHECK5-NEXT: ret void
2398 //
2399 //
2400 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2401 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2402 // CHECK5-NEXT: entry:
2403 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2404 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2405 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2406 // CHECK5-NEXT: ret void
2407 //
2408 //
2409 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2410 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2411 // CHECK5-NEXT: entry:
2412 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2413 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2414 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2415 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2416 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2417 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2418 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2419 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2420 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2421 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2422 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4
2423 // CHECK5-NEXT: ret void
2424 //
2425 //
2426 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2427 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2428 // CHECK5-NEXT: entry:
2429 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2430 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2431 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2432 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2433 // CHECK5-NEXT: ret void
2434 //
2435 //
2436 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2437 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2438 // CHECK5-NEXT: entry:
2439 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2440 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2441 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2442 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2443 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2444 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2445 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
2446 // CHECK5-NEXT: ret void
2447 //
2448 //
2449 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2450 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2451 // CHECK5-NEXT: entry:
2452 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2453 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2454 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2455 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2456 // CHECK5-NEXT: ret void
2457 //
2458 //
2459 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2460 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2461 // CHECK5-NEXT: entry:
2462 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2463 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2464 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2465 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2466 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2467 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2468 // CHECK5-NEXT: ret void
2469 //
2470 //
2471 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2472 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2473 // CHECK5-NEXT: entry:
2474 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2475 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2476 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2477 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2478 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2479 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2480 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2481 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2482 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2483 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2484 // CHECK5-NEXT: ret void
2485 //
2486 //
2487 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2488 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2489 // CHECK5-NEXT: entry:
2490 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2491 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2492 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2493 // CHECK5-NEXT: ret void
2494 //
2495 //
2496 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
2497 // CHECK5-SAME: () #[[ATTR0]] {
2498 // CHECK5-NEXT: entry:
2499 // CHECK5-NEXT: call void @__cxx_global_var_init()
2500 // CHECK5-NEXT: call void @__cxx_global_var_init.1()
2501 // CHECK5-NEXT: call void @__cxx_global_var_init.2()
2502 // CHECK5-NEXT: ret void
2503 //
2504 //
2505 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init
2506 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
2507 // CHECK6-NEXT: entry:
2508 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2509 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2510 // CHECK6-NEXT: ret void
2511 //
2512 //
2513 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2514 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2515 // CHECK6-NEXT: entry:
2516 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2517 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2518 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2519 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2520 // CHECK6-NEXT: ret void
2521 //
2522 //
2523 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2524 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2525 // CHECK6-NEXT: entry:
2526 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2527 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2528 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2529 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2530 // CHECK6-NEXT: ret void
2531 //
2532 //
2533 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2534 // CHECK6-SAME: () #[[ATTR0]] {
2535 // CHECK6-NEXT: entry:
2536 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
2537 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
2538 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2539 // CHECK6-NEXT: ret void
2540 //
2541 //
2542 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2543 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2544 // CHECK6-NEXT: entry:
2545 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2546 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2547 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2548 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2549 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2550 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2551 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2552 // CHECK6-NEXT: ret void
2553 //
2554 //
2555 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2556 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2557 // CHECK6-NEXT: entry:
2558 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2559 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2560 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2561 // CHECK6: arraydestroy.body:
2562 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2563 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2564 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2565 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2566 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2567 // CHECK6: arraydestroy.done1:
2568 // CHECK6-NEXT: ret void
2569 //
2570 //
2571 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2572 // CHECK6-SAME: () #[[ATTR0]] {
2573 // CHECK6-NEXT: entry:
2574 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2575 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2576 // CHECK6-NEXT: ret void
2577 //
2578 //
2579 // CHECK6-LABEL: define {{[^@]+}}@main
2580 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] {
2581 // CHECK6-NEXT: entry:
2582 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2583 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
2584 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2585 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2586 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2587 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
2588 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2589 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2590 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2591 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2592 // CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2593 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
2594 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2595 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2596 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2597 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
2598 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2599 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
2600 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2601 // CHECK6: arrayctor.loop:
2602 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2603 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2604 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
2605 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2606 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2607 // CHECK6: arrayctor.cont:
2608 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
2609 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2610 // CHECK6: omp.inner.for.cond:
2611 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2612 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
2613 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2614 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2615 // CHECK6: omp.inner.for.cond.cleanup:
2616 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2617 // CHECK6: omp.inner.for.body:
2618 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2619 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2620 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2621 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
2622 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2
2623 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2624 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
2625 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
2626 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
2627 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2628 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
2629 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]]
2630 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
2631 // CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
2632 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2
2633 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2634 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
2635 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
2636 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2
2637 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2638 // CHECK6: omp.body.continue:
2639 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2640 // CHECK6: omp.inner.for.inc:
2641 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2642 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
2643 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2644 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2645 // CHECK6: omp.inner.for.end:
2646 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
2647 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2648 // CHECK6-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2649 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2
2650 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2651 // CHECK6: arraydestroy.body:
2652 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2653 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2654 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2655 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
2656 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
2657 // CHECK6: arraydestroy.done6:
2658 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
2659 // CHECK6-NEXT: ret i32 [[CALL]]
2660 //
2661 //
2662 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2663 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat {
2664 // CHECK6-NEXT: entry:
2665 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2666 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2667 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2668 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2669 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2670 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
2671 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
2672 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
2673 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2674 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2675 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2676 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
2677 // CHECK6-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2678 // CHECK6-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2679 // CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2680 // CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
2681 // CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
2682 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2683 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4
2684 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2685 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
2686 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
2687 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
2688 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
2689 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
2690 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
2691 // CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
2692 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2693 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2694 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2695 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
2696 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2697 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2698 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2699 // CHECK6: arrayctor.loop:
2700 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2701 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2702 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
2703 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2704 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2705 // CHECK6: arrayctor.cont:
2706 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
2707 // CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
2708 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2709 // CHECK6: omp.inner.for.cond:
2710 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2711 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
2712 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
2713 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2714 // CHECK6: omp.inner.for.cond.cleanup:
2715 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2716 // CHECK6: omp.inner.for.body:
2717 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2718 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
2719 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2720 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
2721 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6
2722 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
2723 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
2724 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]]
2725 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
2726 // CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6
2727 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
2728 // CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64
2729 // CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
2730 // CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
2731 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
2732 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6
2733 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2734 // CHECK6: omp.body.continue:
2735 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2736 // CHECK6: omp.inner.for.inc:
2737 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2738 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1
2739 // CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2740 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2741 // CHECK6: omp.inner.for.end:
2742 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
2743 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2744 // CHECK6-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2745 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
2746 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2747 // CHECK6: arraydestroy.body:
2748 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2749 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2750 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2751 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2752 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2753 // CHECK6: arraydestroy.done11:
2754 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
2755 // CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2756 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
2757 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
2758 // CHECK6: arraydestroy.body13:
2759 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
2760 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
2761 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
2762 // CHECK6-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
2763 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
2764 // CHECK6: arraydestroy.done17:
2765 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2766 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
2767 // CHECK6-NEXT: ret i32 [[TMP14]]
2768 //
2769 //
2770 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2771 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2772 // CHECK6-NEXT: entry:
2773 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2774 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2775 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2776 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2777 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2778 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2779 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4
2780 // CHECK6-NEXT: ret void
2781 //
2782 //
2783 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2784 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2785 // CHECK6-NEXT: entry:
2786 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2787 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2788 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2789 // CHECK6-NEXT: ret void
2790 //
2791 //
2792 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2793 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2794 // CHECK6-NEXT: entry:
2795 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2796 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2797 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2798 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2799 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2800 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2801 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2802 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2803 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2804 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2805 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4
2806 // CHECK6-NEXT: ret void
2807 //
2808 //
2809 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2810 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2811 // CHECK6-NEXT: entry:
2812 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2813 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2814 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2815 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2816 // CHECK6-NEXT: ret void
2817 //
2818 //
2819 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2820 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2821 // CHECK6-NEXT: entry:
2822 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2823 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2824 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2825 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2826 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2827 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2828 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
2829 // CHECK6-NEXT: ret void
2830 //
2831 //
2832 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2833 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2834 // CHECK6-NEXT: entry:
2835 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2836 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2837 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2838 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2839 // CHECK6-NEXT: ret void
2840 //
2841 //
2842 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2843 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2844 // CHECK6-NEXT: entry:
2845 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2846 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2847 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2848 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2849 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2850 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2851 // CHECK6-NEXT: ret void
2852 //
2853 //
2854 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2855 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2856 // CHECK6-NEXT: entry:
2857 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2858 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2859 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2860 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2861 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2862 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2863 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2864 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2865 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2866 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2867 // CHECK6-NEXT: ret void
2868 //
2869 //
2870 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2871 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2872 // CHECK6-NEXT: entry:
2873 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2874 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2875 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2876 // CHECK6-NEXT: ret void
2877 //
2878 //
2879 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
2880 // CHECK6-SAME: () #[[ATTR0]] {
2881 // CHECK6-NEXT: entry:
2882 // CHECK6-NEXT: call void @__cxx_global_var_init()
2883 // CHECK6-NEXT: call void @__cxx_global_var_init.1()
2884 // CHECK6-NEXT: call void @__cxx_global_var_init.2()
2885 // CHECK6-NEXT: ret void
2886 //
2887 //
2888 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
2889 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
2890 // CHECK7-NEXT: entry:
2891 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2892 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2893 // CHECK7-NEXT: ret void
2894 //
2895 //
2896 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2897 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2898 // CHECK7-NEXT: entry:
2899 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2900 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2901 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2902 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2903 // CHECK7-NEXT: ret void
2904 //
2905 //
2906 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2907 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2908 // CHECK7-NEXT: entry:
2909 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2910 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2911 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2912 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2913 // CHECK7-NEXT: ret void
2914 //
2915 //
2916 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2917 // CHECK7-SAME: () #[[ATTR0]] {
2918 // CHECK7-NEXT: entry:
2919 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
2920 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
2921 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2922 // CHECK7-NEXT: ret void
2923 //
2924 //
2925 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2926 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2927 // CHECK7-NEXT: entry:
2928 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2929 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2930 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2931 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2932 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2933 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2934 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2935 // CHECK7-NEXT: ret void
2936 //
2937 //
2938 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2939 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2940 // CHECK7-NEXT: entry:
2941 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
2942 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
2943 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2944 // CHECK7: arraydestroy.body:
2945 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2946 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2947 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2948 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2949 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2950 // CHECK7: arraydestroy.done1:
2951 // CHECK7-NEXT: ret void
2952 //
2953 //
2954 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2955 // CHECK7-SAME: () #[[ATTR0]] {
2956 // CHECK7-NEXT: entry:
2957 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2958 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2959 // CHECK7-NEXT: ret void
2960 //
2961 //
2962 // CHECK7-LABEL: define {{[^@]+}}@main
2963 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
2964 // CHECK7-NEXT: entry:
2965 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2966 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
2967 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2968 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2969 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2970 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2971 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2972 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2973 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2974 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2975 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2976 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
2977 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2978 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2979 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2980 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
2981 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2982 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2983 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2984 // CHECK7: arrayctor.loop:
2985 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2986 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2987 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
2988 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2989 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2990 // CHECK7: arrayctor.cont:
2991 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
2992 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2993 // CHECK7: omp.inner.for.cond:
2994 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
2995 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
2996 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2997 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2998 // CHECK7: omp.inner.for.cond.cleanup:
2999 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3000 // CHECK7: omp.inner.for.body:
3001 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3002 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
3003 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3004 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
3005 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3
3006 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3007 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]]
3008 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
3009 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3010 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]]
3011 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
3012 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
3013 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3
3014 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3015 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
3016 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
3017 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3
3018 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3019 // CHECK7: omp.body.continue:
3020 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3021 // CHECK7: omp.inner.for.inc:
3022 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3023 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
3024 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3025 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
3026 // CHECK7: omp.inner.for.end:
3027 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
3028 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
3029 // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3030 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2
3031 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3032 // CHECK7: arraydestroy.body:
3033 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3034 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3035 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3036 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
3037 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
3038 // CHECK7: arraydestroy.done5:
3039 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
3040 // CHECK7-NEXT: ret i32 [[CALL]]
3041 //
3042 //
3043 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3044 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
3045 // CHECK7-NEXT: entry:
3046 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3047 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3048 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3049 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3050 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3051 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
3052 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3053 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
3054 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3055 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3056 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3057 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
3058 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
3059 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
3060 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
3061 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
3062 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
3063 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3064 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
3065 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3066 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
3067 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3068 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
3069 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
3070 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
3071 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
3072 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
3073 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3074 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3075 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3076 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
3077 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3078 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3079 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3080 // CHECK7: arrayctor.loop:
3081 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3082 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3083 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
3084 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3085 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3086 // CHECK7: arrayctor.cont:
3087 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
3088 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
3089 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3090 // CHECK7: omp.inner.for.cond:
3091 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3092 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
3093 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
3094 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3095 // CHECK7: omp.inner.for.cond.cleanup:
3096 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3097 // CHECK7: omp.inner.for.body:
3098 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3099 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
3100 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3101 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
3102 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7
3103 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3104 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]]
3105 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
3106 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7
3107 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3108 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]]
3109 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
3110 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
3111 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7
3112 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3113 // CHECK7: omp.body.continue:
3114 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3115 // CHECK7: omp.inner.for.inc:
3116 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3117 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1
3118 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3119 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
3120 // CHECK7: omp.inner.for.end:
3121 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
3122 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3123 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3124 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
3125 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3126 // CHECK7: arraydestroy.body:
3127 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3128 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3129 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3130 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
3131 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
3132 // CHECK7: arraydestroy.done10:
3133 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
3134 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3135 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
3136 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]]
3137 // CHECK7: arraydestroy.body12:
3138 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
3139 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
3140 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
3141 // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
3142 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
3143 // CHECK7: arraydestroy.done16:
3144 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3145 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
3146 // CHECK7-NEXT: ret i32 [[TMP14]]
3147 //
3148 //
3149 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3150 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3151 // CHECK7-NEXT: entry:
3152 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3153 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3154 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3155 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3156 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3157 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3158 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4
3159 // CHECK7-NEXT: ret void
3160 //
3161 //
3162 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3163 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3164 // CHECK7-NEXT: entry:
3165 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3166 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3167 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3168 // CHECK7-NEXT: ret void
3169 //
3170 //
3171 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3172 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3173 // CHECK7-NEXT: entry:
3174 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3175 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3176 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3177 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3178 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3179 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3180 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3181 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3182 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3183 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3184 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4
3185 // CHECK7-NEXT: ret void
3186 //
3187 //
3188 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3189 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3190 // CHECK7-NEXT: entry:
3191 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3192 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3193 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3194 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3195 // CHECK7-NEXT: ret void
3196 //
3197 //
3198 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3199 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3200 // CHECK7-NEXT: entry:
3201 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3202 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3203 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3204 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3205 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3206 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3207 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
3208 // CHECK7-NEXT: ret void
3209 //
3210 //
3211 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3212 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3213 // CHECK7-NEXT: entry:
3214 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3215 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3216 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3217 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3218 // CHECK7-NEXT: ret void
3219 //
3220 //
3221 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3222 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3223 // CHECK7-NEXT: entry:
3224 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3225 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3226 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3227 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3228 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3229 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3230 // CHECK7-NEXT: ret void
3231 //
3232 //
3233 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3234 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3235 // CHECK7-NEXT: entry:
3236 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3237 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3238 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3239 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3240 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3241 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3242 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3243 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3244 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3245 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3246 // CHECK7-NEXT: ret void
3247 //
3248 //
3249 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3250 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3251 // CHECK7-NEXT: entry:
3252 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3253 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3254 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3255 // CHECK7-NEXT: ret void
3256 //
3257 //
3258 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
3259 // CHECK7-SAME: () #[[ATTR0]] {
3260 // CHECK7-NEXT: entry:
3261 // CHECK7-NEXT: call void @__cxx_global_var_init()
3262 // CHECK7-NEXT: call void @__cxx_global_var_init.1()
3263 // CHECK7-NEXT: call void @__cxx_global_var_init.2()
3264 // CHECK7-NEXT: ret void
3265 //
3266 //
3267 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init
3268 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
3269 // CHECK8-NEXT: entry:
3270 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3271 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3272 // CHECK8-NEXT: ret void
3273 //
3274 //
3275 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3276 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3277 // CHECK8-NEXT: entry:
3278 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3279 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3280 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3281 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3282 // CHECK8-NEXT: ret void
3283 //
3284 //
3285 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3286 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3287 // CHECK8-NEXT: entry:
3288 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3289 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3290 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3291 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3292 // CHECK8-NEXT: ret void
3293 //
3294 //
3295 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3296 // CHECK8-SAME: () #[[ATTR0]] {
3297 // CHECK8-NEXT: entry:
3298 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
3299 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
3300 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3301 // CHECK8-NEXT: ret void
3302 //
3303 //
3304 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3305 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3306 // CHECK8-NEXT: entry:
3307 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3308 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3309 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3310 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3311 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3312 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3313 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3314 // CHECK8-NEXT: ret void
3315 //
3316 //
3317 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3318 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3319 // CHECK8-NEXT: entry:
3320 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
3321 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
3322 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3323 // CHECK8: arraydestroy.body:
3324 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3325 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3326 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3327 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3328 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3329 // CHECK8: arraydestroy.done1:
3330 // CHECK8-NEXT: ret void
3331 //
3332 //
3333 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3334 // CHECK8-SAME: () #[[ATTR0]] {
3335 // CHECK8-NEXT: entry:
3336 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3337 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3338 // CHECK8-NEXT: ret void
3339 //
3340 //
3341 // CHECK8-LABEL: define {{[^@]+}}@main
3342 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] {
3343 // CHECK8-NEXT: entry:
3344 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3345 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
3346 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3347 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3348 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3349 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
3350 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3351 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3352 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
3353 // CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3354 // CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3355 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
3356 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3357 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3358 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3359 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
3360 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3361 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
3362 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3363 // CHECK8: arrayctor.loop:
3364 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3365 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3366 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
3367 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3368 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3369 // CHECK8: arrayctor.cont:
3370 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
3371 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3372 // CHECK8: omp.inner.for.cond:
3373 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3374 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
3375 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
3376 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3377 // CHECK8: omp.inner.for.cond.cleanup:
3378 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3379 // CHECK8: omp.inner.for.body:
3380 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3381 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
3382 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3383 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
3384 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3
3385 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3386 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]]
3387 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
3388 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3389 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]]
3390 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
3391 // CHECK8-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
3392 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3
3393 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3394 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
3395 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
3396 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3
3397 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3398 // CHECK8: omp.body.continue:
3399 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3400 // CHECK8: omp.inner.for.inc:
3401 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3402 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
3403 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3404 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
3405 // CHECK8: omp.inner.for.end:
3406 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4
3407 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
3408 // CHECK8-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3409 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2
3410 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3411 // CHECK8: arraydestroy.body:
3412 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3413 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3414 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3415 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
3416 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
3417 // CHECK8: arraydestroy.done5:
3418 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
3419 // CHECK8-NEXT: ret i32 [[CALL]]
3420 //
3421 //
3422 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3423 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat {
3424 // CHECK8-NEXT: entry:
3425 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3426 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3427 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3428 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3429 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3430 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
3431 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
3432 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
3433 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3434 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3435 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3436 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
3437 // CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
3438 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
3439 // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
3440 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
3441 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
3442 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3443 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4
3444 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3445 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
3446 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3447 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
3448 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
3449 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
3450 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
3451 // CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
3452 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3453 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3454 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3455 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
3456 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3457 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3458 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3459 // CHECK8: arrayctor.loop:
3460 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3461 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3462 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
3463 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3464 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3465 // CHECK8: arrayctor.cont:
3466 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
3467 // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
3468 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3469 // CHECK8: omp.inner.for.cond:
3470 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3471 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
3472 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
3473 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3474 // CHECK8: omp.inner.for.cond.cleanup:
3475 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3476 // CHECK8: omp.inner.for.body:
3477 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3478 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
3479 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3480 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
3481 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7
3482 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3483 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]]
3484 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
3485 // CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7
3486 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3487 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]]
3488 // CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
3489 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
3490 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7
3491 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3492 // CHECK8: omp.body.continue:
3493 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3494 // CHECK8: omp.inner.for.inc:
3495 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3496 // CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1
3497 // CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3498 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
3499 // CHECK8: omp.inner.for.end:
3500 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4
3501 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3502 // CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3503 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
3504 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3505 // CHECK8: arraydestroy.body:
3506 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3507 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3508 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3509 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
3510 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
3511 // CHECK8: arraydestroy.done10:
3512 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
3513 // CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3514 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
3515 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]]
3516 // CHECK8: arraydestroy.body12:
3517 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
3518 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
3519 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
3520 // CHECK8-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
3521 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
3522 // CHECK8: arraydestroy.done16:
3523 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3524 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
3525 // CHECK8-NEXT: ret i32 [[TMP14]]
3526 //
3527 //
3528 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3529 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3530 // CHECK8-NEXT: entry:
3531 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3532 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3533 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3534 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3535 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3536 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3537 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4
3538 // CHECK8-NEXT: ret void
3539 //
3540 //
3541 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3542 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3543 // CHECK8-NEXT: entry:
3544 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3545 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3546 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3547 // CHECK8-NEXT: ret void
3548 //
3549 //
3550 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3551 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3552 // CHECK8-NEXT: entry:
3553 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3554 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3555 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3556 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3557 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3558 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3559 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3560 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3561 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3562 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3563 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4
3564 // CHECK8-NEXT: ret void
3565 //
3566 //
3567 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3568 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3569 // CHECK8-NEXT: entry:
3570 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3571 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3572 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3573 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3574 // CHECK8-NEXT: ret void
3575 //
3576 //
3577 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3578 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3579 // CHECK8-NEXT: entry:
3580 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3581 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3582 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3583 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3584 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3585 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3586 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
3587 // CHECK8-NEXT: ret void
3588 //
3589 //
3590 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3591 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3592 // CHECK8-NEXT: entry:
3593 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3594 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3595 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3596 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3597 // CHECK8-NEXT: ret void
3598 //
3599 //
3600 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3601 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3602 // CHECK8-NEXT: entry:
3603 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3604 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3605 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3606 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3607 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3608 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3609 // CHECK8-NEXT: ret void
3610 //
3611 //
3612 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3613 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3614 // CHECK8-NEXT: entry:
3615 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3616 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3617 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3618 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3619 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3620 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3621 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3622 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3623 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3624 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3625 // CHECK8-NEXT: ret void
3626 //
3627 //
3628 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3629 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3630 // CHECK8-NEXT: entry:
3631 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3632 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3633 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3634 // CHECK8-NEXT: ret void
3635 //
3636 //
3637 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
3638 // CHECK8-SAME: () #[[ATTR0]] {
3639 // CHECK8-NEXT: entry:
3640 // CHECK8-NEXT: call void @__cxx_global_var_init()
3641 // CHECK8-NEXT: call void @__cxx_global_var_init.1()
3642 // CHECK8-NEXT: call void @__cxx_global_var_init.2()
3643 // CHECK8-NEXT: ret void
3644 //
3645 //
3646 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
3647 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
3648 // CHECK9-NEXT: entry:
3649 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3650 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3651 // CHECK9-NEXT: ret void
3652 //
3653 //
3654 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3655 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3656 // CHECK9-NEXT: entry:
3657 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3658 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3659 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3660 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3661 // CHECK9-NEXT: ret void
3662 //
3663 //
3664 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3665 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3666 // CHECK9-NEXT: entry:
3667 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3668 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3669 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3670 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3671 // CHECK9-NEXT: ret void
3672 //
3673 //
3674 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3675 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3676 // CHECK9-NEXT: entry:
3677 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3678 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3679 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3680 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3681 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3682 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3683 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
3684 // CHECK9-NEXT: ret void
3685 //
3686 //
3687 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3688 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3689 // CHECK9-NEXT: entry:
3690 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3691 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3692 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3693 // CHECK9-NEXT: ret void
3694 //
3695 //
3696 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3697 // CHECK9-SAME: () #[[ATTR0]] {
3698 // CHECK9-NEXT: entry:
3699 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
3700 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
3701 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3702 // CHECK9-NEXT: ret void
3703 //
3704 //
3705 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3706 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3707 // CHECK9-NEXT: entry:
3708 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3709 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3710 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3711 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3712 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3713 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3714 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3715 // CHECK9-NEXT: ret void
3716 //
3717 //
3718 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3719 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3720 // CHECK9-NEXT: entry:
3721 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
3722 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3723 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3724 // CHECK9: arraydestroy.body:
3725 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3726 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3727 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3728 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3729 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3730 // CHECK9: arraydestroy.done1:
3731 // CHECK9-NEXT: ret void
3732 //
3733 //
3734 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3735 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3736 // CHECK9-NEXT: entry:
3737 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3738 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3739 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3740 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3741 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3742 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3743 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3744 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3745 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3746 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3747 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
3748 // CHECK9-NEXT: ret void
3749 //
3750 //
3751 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3752 // CHECK9-SAME: () #[[ATTR0]] {
3753 // CHECK9-NEXT: entry:
3754 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3755 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3756 // CHECK9-NEXT: ret void
3757 //
3758 //
3759 // CHECK9-LABEL: define {{[^@]+}}@main
3760 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
3761 // CHECK9-NEXT: entry:
3762 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3763 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
3764 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
3765 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
3766 // CHECK9-NEXT: ret i32 0
3767 //
3768 //
3769 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74
3770 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] {
3771 // CHECK9-NEXT: entry:
3772 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3773 // CHECK9-NEXT: ret void
3774 //
3775 //
3776 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
3777 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] {
3778 // CHECK9-NEXT: entry:
3779 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3780 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3781 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3782 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
3783 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
3784 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3785 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3786 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3787 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3788 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
3789 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
3790 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
3791 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3792 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
3793 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
3794 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3795 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3796 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
3797 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3798 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3799 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3800 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3801 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
3802 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3803 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3804 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3805 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3806 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
3807 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3808 // CHECK9: cond.true:
3809 // CHECK9-NEXT: br label [[COND_END:%.*]]
3810 // CHECK9: cond.false:
3811 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3812 // CHECK9-NEXT: br label [[COND_END]]
3813 // CHECK9: cond.end:
3814 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3815 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3816 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3817 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
3818 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3819 // CHECK9: omp.inner.for.cond:
3820 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
3821 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
3822 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3823 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3824 // CHECK9: omp.inner.for.body:
3825 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
3826 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
3827 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3828 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
3829 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !4
3830 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4
3831 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
3832 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !4
3833 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
3834 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8, !llvm.access.group !4
3835 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
3836 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4
3837 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4
3838 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
3839 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4
3840 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4
3841 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3842 // CHECK9: omp.body.continue:
3843 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3844 // CHECK9: omp.inner.for.inc:
3845 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
3846 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
3847 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
3848 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
3849 // CHECK9: omp.inner.for.end:
3850 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3851 // CHECK9: omp.loop.exit:
3852 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
3853 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3854 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
3855 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3856 // CHECK9: .omp.final.then:
3857 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
3858 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
3859 // CHECK9: .omp.final.done:
3860 // CHECK9-NEXT: ret void
3861 //
3862 //
3863 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
3864 // CHECK9-SAME: () #[[ATTR0]] {
3865 // CHECK9-NEXT: entry:
3866 // CHECK9-NEXT: call void @__cxx_global_var_init()
3867 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
3868 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
3869 // CHECK9-NEXT: ret void
3870 //
3871 //
3872 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3873 // CHECK9-SAME: () #[[ATTR0]] {
3874 // CHECK9-NEXT: entry:
3875 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
3876 // CHECK9-NEXT: ret void
3877 //
3878 //
3879 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init
3880 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
3881 // CHECK10-NEXT: entry:
3882 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3883 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3884 // CHECK10-NEXT: ret void
3885 //
3886 //
3887 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3888 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3889 // CHECK10-NEXT: entry:
3890 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3891 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3892 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3893 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3894 // CHECK10-NEXT: ret void
3895 //
3896 //
3897 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3898 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3899 // CHECK10-NEXT: entry:
3900 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3901 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3902 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3903 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3904 // CHECK10-NEXT: ret void
3905 //
3906 //
3907 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3908 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3909 // CHECK10-NEXT: entry:
3910 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3911 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3912 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3913 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3914 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3915 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3916 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4
3917 // CHECK10-NEXT: ret void
3918 //
3919 //
3920 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3921 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3922 // CHECK10-NEXT: entry:
3923 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3924 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3925 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3926 // CHECK10-NEXT: ret void
3927 //
3928 //
3929 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3930 // CHECK10-SAME: () #[[ATTR0]] {
3931 // CHECK10-NEXT: entry:
3932 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
3933 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
3934 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3935 // CHECK10-NEXT: ret void
3936 //
3937 //
3938 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3939 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3940 // CHECK10-NEXT: entry:
3941 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3942 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3943 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3944 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3945 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3946 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3947 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3948 // CHECK10-NEXT: ret void
3949 //
3950 //
3951 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3952 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3953 // CHECK10-NEXT: entry:
3954 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
3955 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3956 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3957 // CHECK10: arraydestroy.body:
3958 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3959 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3960 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3961 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3962 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3963 // CHECK10: arraydestroy.done1:
3964 // CHECK10-NEXT: ret void
3965 //
3966 //
3967 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3968 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3969 // CHECK10-NEXT: entry:
3970 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3971 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3972 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3973 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3974 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3975 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3976 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3977 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3978 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3979 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3980 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4
3981 // CHECK10-NEXT: ret void
3982 //
3983 //
3984 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3985 // CHECK10-SAME: () #[[ATTR0]] {
3986 // CHECK10-NEXT: entry:
3987 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3988 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3989 // CHECK10-NEXT: ret void
3990 //
3991 //
3992 // CHECK10-LABEL: define {{[^@]+}}@main
3993 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] {
3994 // CHECK10-NEXT: entry:
3995 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3996 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
3997 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4
3998 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
3999 // CHECK10-NEXT: ret i32 0
4000 //
4001 //
4002 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74
4003 // CHECK10-SAME: () #[[ATTR5:[0-9]+]] {
4004 // CHECK10-NEXT: entry:
4005 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
4006 // CHECK10-NEXT: ret void
4007 //
4008 //
4009 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
4010 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] {
4011 // CHECK10-NEXT: entry:
4012 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4013 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4014 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4015 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
4016 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
4017 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4018 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4019 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4020 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4021 // CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4
4022 // CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4
4023 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
4024 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
4025 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
4026 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
4027 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4028 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4029 // CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8
4030 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4031 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4032 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4033 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4034 // CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
4035 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4036 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4037 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4038 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4039 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
4040 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4041 // CHECK10: cond.true:
4042 // CHECK10-NEXT: br label [[COND_END:%.*]]
4043 // CHECK10: cond.false:
4044 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4045 // CHECK10-NEXT: br label [[COND_END]]
4046 // CHECK10: cond.end:
4047 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4048 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4049 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4050 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4051 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4052 // CHECK10: omp.inner.for.cond:
4053 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
4054 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4
4055 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4056 // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4057 // CHECK10: omp.inner.for.body:
4058 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
4059 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4060 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4061 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
4062 // CHECK10-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !4
4063 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4
4064 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4
4065 // CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !4
4066 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
4067 // CHECK10-NEXT: store i32* [[G]], i32** [[TMP9]], align 8, !llvm.access.group !4
4068 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
4069 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4
4070 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4
4071 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
4072 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4
4073 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4
4074 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4075 // CHECK10: omp.body.continue:
4076 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4077 // CHECK10: omp.inner.for.inc:
4078 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
4079 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
4080 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
4081 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
4082 // CHECK10: omp.inner.for.end:
4083 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4084 // CHECK10: omp.loop.exit:
4085 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4086 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4087 // CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
4088 // CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4089 // CHECK10: .omp.final.then:
4090 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4
4091 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
4092 // CHECK10: .omp.final.done:
4093 // CHECK10-NEXT: ret void
4094 //
4095 //
4096 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
4097 // CHECK10-SAME: () #[[ATTR0]] {
4098 // CHECK10-NEXT: entry:
4099 // CHECK10-NEXT: call void @__cxx_global_var_init()
4100 // CHECK10-NEXT: call void @__cxx_global_var_init.1()
4101 // CHECK10-NEXT: call void @__cxx_global_var_init.2()
4102 // CHECK10-NEXT: ret void
4103 //
4104 //
4105 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4106 // CHECK10-SAME: () #[[ATTR0]] {
4107 // CHECK10-NEXT: entry:
4108 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
4109 // CHECK10-NEXT: ret void
4110 //
4111 //
4112 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
4113 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
4114 // CHECK11-NEXT: entry:
4115 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4116 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4117 // CHECK11-NEXT: ret void
4118 //
4119 //
4120 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4121 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4122 // CHECK11-NEXT: entry:
4123 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4124 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4125 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4126 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4127 // CHECK11-NEXT: ret void
4128 //
4129 //
4130 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4131 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4132 // CHECK11-NEXT: entry:
4133 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4134 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4135 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4136 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4137 // CHECK11-NEXT: ret void
4138 //
4139 //
4140 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4141 // CHECK11-SAME: () #[[ATTR0]] {
4142 // CHECK11-NEXT: entry:
4143 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4144 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4145 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4146 // CHECK11-NEXT: ret void
4147 //
4148 //
4149 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4150 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4151 // CHECK11-NEXT: entry:
4152 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4153 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4154 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4155 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4156 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4157 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4158 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4159 // CHECK11-NEXT: ret void
4160 //
4161 //
4162 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4163 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4164 // CHECK11-NEXT: entry:
4165 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4166 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4167 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4168 // CHECK11: arraydestroy.body:
4169 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4170 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4171 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4172 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4173 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4174 // CHECK11: arraydestroy.done1:
4175 // CHECK11-NEXT: ret void
4176 //
4177 //
4178 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4179 // CHECK11-SAME: () #[[ATTR0]] {
4180 // CHECK11-NEXT: entry:
4181 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4182 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4183 // CHECK11-NEXT: ret void
4184 //
4185 //
4186 // CHECK11-LABEL: define {{[^@]+}}@main
4187 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
4188 // CHECK11-NEXT: entry:
4189 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4190 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4191 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
4192 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4193 // CHECK11-NEXT: ret i32 0
4194 //
4195 //
4196 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4197 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4198 // CHECK11-NEXT: entry:
4199 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4200 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4201 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4202 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4203 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4204 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4205 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4
4206 // CHECK11-NEXT: ret void
4207 //
4208 //
4209 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4210 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4211 // CHECK11-NEXT: entry:
4212 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4213 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4214 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4215 // CHECK11-NEXT: ret void
4216 //
4217 //
4218 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4219 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4220 // CHECK11-NEXT: entry:
4221 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4222 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4223 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4224 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4225 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4226 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4227 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4228 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4229 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4230 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4231 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4
4232 // CHECK11-NEXT: ret void
4233 //
4234 //
4235 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
4236 // CHECK11-SAME: () #[[ATTR0]] {
4237 // CHECK11-NEXT: entry:
4238 // CHECK11-NEXT: call void @__cxx_global_var_init()
4239 // CHECK11-NEXT: call void @__cxx_global_var_init.1()
4240 // CHECK11-NEXT: call void @__cxx_global_var_init.2()
4241 // CHECK11-NEXT: ret void
4242 //
4243 //
4244 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init
4245 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
4246 // CHECK12-NEXT: entry:
4247 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4248 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4249 // CHECK12-NEXT: ret void
4250 //
4251 //
4252 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4253 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4254 // CHECK12-NEXT: entry:
4255 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4256 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4257 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4258 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4259 // CHECK12-NEXT: ret void
4260 //
4261 //
4262 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4263 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4264 // CHECK12-NEXT: entry:
4265 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4266 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4267 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4268 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4269 // CHECK12-NEXT: ret void
4270 //
4271 //
4272 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4273 // CHECK12-SAME: () #[[ATTR0]] {
4274 // CHECK12-NEXT: entry:
4275 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4276 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4277 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4278 // CHECK12-NEXT: ret void
4279 //
4280 //
4281 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4282 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4283 // CHECK12-NEXT: entry:
4284 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4285 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4286 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4287 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4288 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4289 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4290 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4291 // CHECK12-NEXT: ret void
4292 //
4293 //
4294 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4295 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4296 // CHECK12-NEXT: entry:
4297 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4298 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4299 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4300 // CHECK12: arraydestroy.body:
4301 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4302 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4303 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4304 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4305 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4306 // CHECK12: arraydestroy.done1:
4307 // CHECK12-NEXT: ret void
4308 //
4309 //
4310 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4311 // CHECK12-SAME: () #[[ATTR0]] {
4312 // CHECK12-NEXT: entry:
4313 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4314 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4315 // CHECK12-NEXT: ret void
4316 //
4317 //
4318 // CHECK12-LABEL: define {{[^@]+}}@main
4319 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] {
4320 // CHECK12-NEXT: entry:
4321 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4322 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4323 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4
4324 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4325 // CHECK12-NEXT: ret i32 0
4326 //
4327 //
4328 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4329 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4330 // CHECK12-NEXT: entry:
4331 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4332 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4333 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4334 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4335 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4336 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4337 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4
4338 // CHECK12-NEXT: ret void
4339 //
4340 //
4341 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4342 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4343 // CHECK12-NEXT: entry:
4344 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4345 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4346 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4347 // CHECK12-NEXT: ret void
4348 //
4349 //
4350 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4351 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4352 // CHECK12-NEXT: entry:
4353 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4354 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4355 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4356 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4357 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4358 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4359 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4360 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4361 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4362 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4363 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4
4364 // CHECK12-NEXT: ret void
4365 //
4366 //
4367 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
4368 // CHECK12-SAME: () #[[ATTR0]] {
4369 // CHECK12-NEXT: entry:
4370 // CHECK12-NEXT: call void @__cxx_global_var_init()
4371 // CHECK12-NEXT: call void @__cxx_global_var_init.1()
4372 // CHECK12-NEXT: call void @__cxx_global_var_init.2()
4373 // CHECK12-NEXT: ret void
4374 //
4375