1unit AT90PWM216; 2 3{$goto on} 4 5interface 6 7var 8 // PORTB 9 PORTB : byte absolute $00+$25; // Port B Data Register 10 DDRB : byte absolute $00+$24; // Port B Data Direction Register 11 PINB : byte absolute $00+$23; // Port B Input Pins 12 // PORTD 13 PORTD : byte absolute $00+$2B; // Port D Data Register 14 DDRD : byte absolute $00+$2A; // Port D Data Direction Register 15 PIND : byte absolute $00+$29; // Port D Input Pins 16 // BOOT_LOAD 17 SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register 18 // EUSART 19 EUDR : byte absolute $00+$CE; // EUSART I/O Data Register 20 EUCSRA : byte absolute $00+$C8; // EUSART Control and Status Register A 21 EUCSRB : byte absolute $00+$C9; // EUSART Control Register B 22 EUCSRC : byte absolute $00+$CA; // EUSART Status Register C 23 MUBRRH : byte absolute $00+$CD; // Manchester Receiver Baud Rate Register High Byte 24 MUBRRL : byte absolute $00+$CC; // Manchester Receiver Baud Rate Register Low Byte 25 // ANALOG_COMPARATOR 26 AC0CON : byte absolute $00+$AD; // Analog Comparator 0 Control Register 27 AC1CON : byte absolute $00+$AE; // Analog Comparator 1 Control Register 28 AC2CON : byte absolute $00+$AF; // Analog Comparator 2 Control Register 29 ACSR : byte absolute $00+$50; // Analog Comparator Status Register 30 // DA_CONVERTER 31 DACH : byte absolute $00+$AC; // DAC Data Register High Byte 32 DACL : byte absolute $00+$AB; // DAC Data Register Low Byte 33 DACON : byte absolute $00+$AA; // DAC Control Register 34 // CPU 35 SREG : byte absolute $00+$5F; // Status Register 36 SP : word absolute $00+$5D; // Stack Pointer 37 SPL : byte absolute $00+$5D; // Stack Pointer 38 SPH : byte absolute $00+$5D+1; // Stack Pointer 39 MCUCR : byte absolute $00+$55; // MCU Control Register 40 MCUSR : byte absolute $00+$54; // MCU Status Register 41 OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value 42 CLKPR : byte absolute $00+$61; // 43 SMCR : byte absolute $00+$53; // Sleep Mode Control Register 44 GPIOR3 : byte absolute $00+$3B; // General Purpose IO Register 3 45 GPIOR2 : byte absolute $00+$3A; // General Purpose IO Register 2 46 GPIOR1 : byte absolute $00+$39; // General Purpose IO Register 1 47 GPIOR0 : byte absolute $00+$3E; // General Purpose IO Register 0 48 PLLCSR : byte absolute $00+$49; // PLL Control And Status Register 49 PRR : byte absolute $00+$64; // Power Reduction Register 50 // PORTE 51 PORTE : byte absolute $00+$2E; // Port E Data Register 52 DDRE : byte absolute $00+$2D; // Port E Data Direction Register 53 PINE : byte absolute $00+$2C; // Port E Input Pins 54 // TIMER_COUNTER_0 55 TIMSK0 : byte absolute $00+$6E; // Timer/Counter0 Interrupt Mask Register 56 TIFR0 : byte absolute $00+$35; // Timer/Counter0 Interrupt Flag register 57 TCCR0A : byte absolute $00+$44; // Timer/Counter Control Register A 58 TCCR0B : byte absolute $00+$45; // Timer/Counter Control Register B 59 TCNT0 : byte absolute $00+$46; // Timer/Counter0 60 OCR0A : byte absolute $00+$47; // Timer/Counter0 Output Compare Register 61 OCR0B : byte absolute $00+$48; // Timer/Counter0 Output Compare Register 62 GTCCR : byte absolute $00+$43; // General Timer/Counter Control Register 63 // TIMER_COUNTER_1 64 TIMSK1 : byte absolute $00+$6F; // Timer/Counter Interrupt Mask Register 65 TIFR1 : byte absolute $00+$36; // Timer/Counter Interrupt Flag register 66 TCCR1A : byte absolute $00+$80; // Timer/Counter1 Control Register A 67 TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B 68 TCCR1C : byte absolute $00+$82; // Timer/Counter1 Control Register C 69 TCNT1 : word absolute $00+$84; // Timer/Counter1 Bytes 70 TCNT1L : byte absolute $00+$84; // Timer/Counter1 Bytes 71 TCNT1H : byte absolute $00+$84+1; // Timer/Counter1 Bytes 72 OCR1A : word absolute $00+$88; // Timer/Counter1 Output Compare Register Bytes 73 OCR1AL : byte absolute $00+$88; // Timer/Counter1 Output Compare Register Bytes 74 OCR1AH : byte absolute $00+$88+1; // Timer/Counter1 Output Compare Register Bytes 75 OCR1B : word absolute $00+$8A; // Timer/Counter1 Output Compare Register Bytes 76 OCR1BL : byte absolute $00+$8A; // Timer/Counter1 Output Compare Register Bytes 77 OCR1BH : byte absolute $00+$8A+1; // Timer/Counter1 Output Compare Register Bytes 78 ICR1 : word absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes 79 ICR1L : byte absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes 80 ICR1H : byte absolute $00+$86+1; // Timer/Counter1 Input Capture Register Bytes 81 // AD_CONVERTER 82 ADMUX : byte absolute $00+$7C; // The ADC multiplexer Selection Register 83 ADCSRA : byte absolute $00+$7A; // The ADC Control and Status register 84 ADC : word absolute $00+$78; // ADC Data Register Bytes 85 ADCL : byte absolute $00+$78; // ADC Data Register Bytes 86 ADCH : byte absolute $00+$78+1; // ADC Data Register Bytes 87 ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B 88 DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0 89 DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 0 90 AMP0CSR : byte absolute $00+$76; // 91 AMP1CSR : byte absolute $00+$77; // 92 // USART 93 UDR : byte absolute $00+$C6; // USART I/O Data Register 94 UCSRA : byte absolute $00+$C0; // USART Control and Status register A 95 UCSRB : byte absolute $00+$C1; // USART Control an Status register B 96 UCSRC : byte absolute $00+$C2; // USART Control an Status register C 97 UBRRH : byte absolute $00+$C5; // USART Baud Rate Register High Byte 98 UBRRL : byte absolute $00+$C4; // USART Baud Rate Register Low Byte 99 // SPI 100 SPCR : byte absolute $00+$4C; // SPI Control Register 101 SPSR : byte absolute $00+$4D; // SPI Status Register 102 SPDR : byte absolute $00+$4E; // SPI Data Register 103 // WATCHDOG 104 WDTCSR : byte absolute $00+$60; // Watchdog Timer Control Register 105 // EXTERNAL_INTERRUPT 106 EICRA : byte absolute $00+$69; // External Interrupt Control Register A 107 EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register 108 EIFR : byte absolute $00+$3C; // External Interrupt Flag Register 109 // EEPROM 110 EEAR : word absolute $00+$41; // EEPROM Read/Write Access Bytes 111 EEARL : byte absolute $00+$41; // EEPROM Read/Write Access Bytes 112 EEARH : byte absolute $00+$41+1; // EEPROM Read/Write Access Bytes 113 EEDR : byte absolute $00+$40; // EEPROM Data Register 114 EECR : byte absolute $00+$3F; // EEPROM Control Register 115 // PSC0 116 PICR0 : word absolute $00+$DE; // PSC 0 Input Capture Register 117 PICR0L : byte absolute $00+$DE; // PSC 0 Input Capture Register 118 PICR0H : byte absolute $00+$DE+1; // PSC 0 Input Capture Register 119 PFRC0B : byte absolute $00+$DD; // PSC 0 Input B Control 120 PFRC0A : byte absolute $00+$DC; // PSC 0 Input A Control 121 PCTL0 : byte absolute $00+$DB; // PSC 0 Control Register 122 PCNF0 : byte absolute $00+$DA; // PSC 0 Configuration Register 123 OCR0RB : word absolute $00+$D8; // Output Compare RB Register 124 OCR0RBL : byte absolute $00+$D8; // Output Compare RB Register 125 OCR0RBH : byte absolute $00+$D8+1; // Output Compare RB Register 126 OCR0SB : word absolute $00+$D6; // Output Compare SB Register 127 OCR0SBL : byte absolute $00+$D6; // Output Compare SB Register 128 OCR0SBH : byte absolute $00+$D6+1; // Output Compare SB Register 129 OCR0RA : word absolute $00+$D4; // Output Compare RA Register 130 OCR0RAL : byte absolute $00+$D4; // Output Compare RA Register 131 OCR0RAH : byte absolute $00+$D4+1; // Output Compare RA Register 132 OCR0SA : word absolute $00+$D2; // Output Compare SA Register 133 OCR0SAL : byte absolute $00+$D2; // Output Compare SA Register 134 OCR0SAH : byte absolute $00+$D2+1; // Output Compare SA Register 135 PSOC0 : byte absolute $00+$D0; // PSC0 Synchro and Output Configuration 136 PIM0 : byte absolute $00+$A1; // PSC0 Interrupt Mask Register 137 PIFR0 : byte absolute $00+$A0; // PSC0 Interrupt Flag Register 138 // PSC2 139 PICR2 : word absolute $00+$FE; // PSC 2 Input Capture Register 140 PICR2L : byte absolute $00+$FE; // PSC 2 Input Capture Register 141 PICR2H : byte absolute $00+$FE+1; // PSC 2 Input Capture Register 142 PFRC2B : byte absolute $00+$FD; // PSC 2 Input B Control 143 PFRC2A : byte absolute $00+$FC; // PSC 2 Input B Control 144 PCTL2 : byte absolute $00+$FB; // PSC 2 Control Register 145 PCNF2 : byte absolute $00+$FA; // PSC 2 Configuration Register 146 OCR2RB : word absolute $00+$F8; // Output Compare RB Register 147 OCR2RBL : byte absolute $00+$F8; // Output Compare RB Register 148 OCR2RBH : byte absolute $00+$F8+1; // Output Compare RB Register 149 OCR2SB : word absolute $00+$F6; // Output Compare SB Register 150 OCR2SBL : byte absolute $00+$F6; // Output Compare SB Register 151 OCR2SBH : byte absolute $00+$F6+1; // Output Compare SB Register 152 OCR2RA : word absolute $00+$F4; // Output Compare RA Register 153 OCR2RAL : byte absolute $00+$F4; // Output Compare RA Register 154 OCR2RAH : byte absolute $00+$F4+1; // Output Compare RA Register 155 OCR2SA : word absolute $00+$F2; // Output Compare SA Register 156 OCR2SAL : byte absolute $00+$F2; // Output Compare SA Register 157 OCR2SAH : byte absolute $00+$F2+1; // Output Compare SA Register 158 POM2 : byte absolute $00+$F1; // PSC 2 Output Matrix 159 PSOC2 : byte absolute $00+$F0; // PSC2 Synchro and Output Configuration 160 PIM2 : byte absolute $00+$A5; // PSC2 Interrupt Mask Register 161 PIFR2 : byte absolute $00+$A4; // PSC2 Interrupt Flag Register 162 163const 164 // SPMCSR 165 SPMIE = 7; // SPM Interrupt Enable 166 RWWSB = 6; // Read While Write Section Busy 167 RWWSRE = 4; // Read While Write section read enable 168 BLBSET = 3; // Boot Lock Bit Set 169 PGWRT = 2; // Page Write 170 PGERS = 1; // Page Erase 171 SPMEN = 0; // Store Program Memory Enable 172 // EUCSRA 173 UTxS = 4; // EUSART Control and Status Register A Bits 174 URxS = 0; // EUSART Control and Status Register A Bits 175 // EUCSRB 176 EUSART = 4; // EUSART Enable Bit 177 EUSBS = 3; // EUSBS Enable Bit 178 EMCH = 1; // Manchester Mode Bit 179 BODR = 0; // Order Bit 180 // EUCSRC 181 FEM = 3; // Frame Error Manchester Bit 182 F1617 = 2; // F1617 Bit 183 STP = 0; // Stop Bits 184 // MUBRRH 185 MUBRR = 0; // Manchester Receiver Baud Rate Register Bits 186 // MUBRRL 187 // AC0CON 188 AC0EN = 7; // Analog Comparator 0 Enable Bit 189 AC0IE = 6; // Analog Comparator 0 Interrupt Enable Bit 190 AC0IS = 4; // Analog Comparator 0 Interrupt Select Bit 191 AC0M = 0; // Analog Comparator 0 Multiplexer Register 192 // AC1CON 193 AC1EN = 7; // Analog Comparator 1 Enable Bit 194 AC1IE = 6; // Analog Comparator 1 Interrupt Enable Bit 195 AC1IS = 4; // Analog Comparator 1 Interrupt Select Bit 196 AC1ICE = 3; // Analog Comparator 1 Interrupt Capture Enable Bit 197 AC1M = 0; // Analog Comparator 1 Multiplexer Register 198 // AC2CON 199 AC2EN = 7; // Analog Comparator 2 Enable Bit 200 AC2IE = 6; // Analog Comparator 2 Interrupt Enable Bit 201 AC2IS = 4; // Analog Comparator 2 Interrupt Select Bit 202 AC2M = 0; // Analog Comparator 2 Multiplexer Register 203 // ACSR 204 ACCKDIV = 7; // Analog Comparator Clock Divider 205 AC2IF = 6; // Analog Comparator 2 Interrupt Flag Bit 206 AC1IF = 5; // Analog Comparator 1 Interrupt Flag Bit 207 AC0IF = 4; // Analog Comparator 0 Interrupt Flag Bit 208 AC2O = 2; // Analog Comparator 2 Output Bit 209 AC1O = 1; // Analog Comparator 1 Output Bit 210 AC0O = 0; // Analog Comparator 0 Output Bit 211 // DACH 212 // DACL 213 // DACON 214 DAATE = 7; // DAC Auto Trigger Enable Bit 215 DATS = 4; // DAC Trigger Selection Bits 216 DALA = 2; // DAC Left Adjust 217 DAEN = 0; // DAC Enable Bit 218 // SREG 219 I = 7; // Global Interrupt Enable 220 T = 6; // Bit Copy Storage 221 H = 5; // Half Carry Flag 222 S = 4; // Sign Bit 223 V = 3; // Two's Complement Overflow Flag 224 N = 2; // Negative Flag 225 Z = 1; // Zero Flag 226 C = 0; // Carry Flag 227 // MCUCR 228 SPIPS = 7; // SPI Pin Select 229 PUD = 4; // Pull-up disable 230 IVSEL = 1; // Interrupt Vector Select 231 IVCE = 0; // Interrupt Vector Change Enable 232 // MCUSR 233 WDRF = 3; // Watchdog Reset Flag 234 BORF = 2; // Brown-out Reset Flag 235 EXTRF = 1; // External Reset Flag 236 PORF = 0; // Power-on reset flag 237 // CLKPR 238 CLKPCE = 7; // 239 CLKPS = 0; // 240 // SMCR 241 SM = 1; // Sleep Mode Select bits 242 SE = 0; // Sleep Enable 243 // GPIOR3 244 GPIOR = 0; // General Purpose IO Register 3 bis 245 // GPIOR2 246 // GPIOR1 247 // GPIOR0 248 GPIOR07 = 7; // General Purpose IO Register 0 bit 7 249 GPIOR06 = 6; // General Purpose IO Register 0 bit 6 250 GPIOR05 = 5; // General Purpose IO Register 0 bit 5 251 GPIOR04 = 4; // General Purpose IO Register 0 bit 4 252 GPIOR03 = 3; // General Purpose IO Register 0 bit 3 253 GPIOR02 = 2; // General Purpose IO Register 0 bit 2 254 GPIOR01 = 1; // General Purpose IO Register 0 bit 1 255 GPIOR00 = 0; // General Purpose IO Register 0 bit 0 256 // PLLCSR 257 PLLF = 2; // PLL Factor 258 PLLE = 1; // PLL Enable 259 PLOCK = 0; // PLL Lock Detector 260 // PRR 261 PRPSC = 5; // Power Reduction PSC2 262 PRTIM1 = 4; // Power Reduction Timer/Counter1 263 PRTIM0 = 3; // Power Reduction Timer/Counter0 264 PRSPI = 2; // Power Reduction Serial Peripheral Interface 265 PRUSART0 = 1; // Power Reduction USART 266 PRADC = 0; // Power Reduction ADC 267 // TIMSK0 268 OCIE0B = 2; // Timer/Counter0 Output Compare Match B Interrupt Enable 269 OCIE0A = 1; // Timer/Counter0 Output Compare Match A Interrupt Enable 270 TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable 271 // TIFR0 272 OCF0B = 2; // Timer/Counter0 Output Compare Flag 0B 273 OCF0A = 1; // Timer/Counter0 Output Compare Flag 0A 274 TOV0 = 0; // Timer/Counter0 Overflow Flag 275 // TCCR0A 276 COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode 277 COM0B = 4; // Compare Output Mode, Fast PWm 278 WGM0 = 0; // Waveform Generation Mode 279 // TCCR0B 280 FOC0A = 7; // Force Output Compare A 281 FOC0B = 6; // Force Output Compare B 282 WGM02 = 3; // 283 CS0 = 0; // Clock Select 284 // GTCCR 285 TSM = 7; // Timer/Counter Synchronization Mode 286 ICPSEL1 = 6; // Timer1 Input Capture Selection Bit 287 PSR10 = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0 288 // TIMSK1 289 ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable 290 OCIE1B = 2; // Timer/Counter1 Output CompareB Match Interrupt Enable 291 OCIE1A = 1; // Timer/Counter1 Output CompareA Match Interrupt Enable 292 TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable 293 // TIFR1 294 ICF1 = 5; // Input Capture Flag 1 295 OCF1B = 2; // Output Compare Flag 1B 296 OCF1A = 1; // Output Compare Flag 1A 297 TOV1 = 0; // Timer/Counter1 Overflow Flag 298 // TCCR1A 299 COM1A = 6; // Compare Output Mode 1A, bits 300 COM1B = 4; // Compare Output Mode 1B, bits 301 WGM1 = 0; // Waveform Generation Mode 302 // TCCR1B 303 ICNC1 = 7; // Input Capture 1 Noise Canceler 304 ICES1 = 6; // Input Capture 1 Edge Select 305 CS1 = 0; // Prescaler source of Timer/Counter 1 306 // TCCR1C 307 FOC1A = 7; // 308 FOC1B = 6; // 309 // GTCCR 310 PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0 311 // ADMUX 312 REFS = 6; // Reference Selection Bits 313 ADLAR = 5; // Left Adjust Result 314 MUX = 0; // Analog Channel and Gain Selection Bits 315 // ADCSRA 316 ADEN = 7; // ADC Enable 317 ADSC = 6; // ADC Start Conversion 318 ADATE = 5; // ADC Auto Trigger Enable 319 ADIF = 4; // ADC Interrupt Flag 320 ADIE = 3; // ADC Interrupt Enable 321 ADPS = 0; // ADC Prescaler Select Bits 322 // DIDR1 323 ACMP0D = 5; // 324 AMP0PD = 4; // 325 AMP0ND = 3; // 326 ADC10D = 2; // 327 ADC9D = 1; // 328 ADC8D = 0; // 329 // AMP0CSR 330 AMP0EN = 7; // 331 AMP0IS = 6; // 332 AMP0G = 4; // 333 AMP0TS = 0; // 334 // AMP1CSR 335 AMP1EN = 7; // 336 AMP1IS = 6; // 337 AMP1G = 4; // 338 AMP1TS = 0; // 339 // UCSRA 340 RXC = 7; // USART Receive Complete 341 TXC = 6; // USART Transmitt Complete 342 UDRE = 5; // USART Data Register Empty 343 FE = 4; // Framing Error 344 DOR = 3; // Data Overrun 345 UPE = 2; // USART Parity Error 346 U2X = 1; // Double USART Transmission Bit 347 MPCM = 0; // Multi-processor Communication Mode 348 // UCSRB 349 RXCIE = 7; // RX Complete Interrupt Enable 350 TXCIE = 6; // TX Complete Interrupt Enable 351 UDRIE = 5; // USART Data Register Empty Interrupt Enable 352 RXEN = 4; // Receiver Enable 353 TXEN = 3; // Transmitter Enable 354 UCSZ2 = 2; // Character Size 355 RXB8 = 1; // Receive Data Bit 8 356 TXB8 = 0; // Transmit Data Bit 8 357 // UCSRC 358 UMSEL0 = 6; // USART Mode Select 359 UPM = 4; // Parity Mode Bits 360 USBS = 3; // Stop Bit Select 361 UCSZ = 1; // Character Size Bits 362 UCPOL = 0; // Clock Polarity 363 // UBRRH 364 UBRR = 0; // USART Baud Rate Register Bits 365 // UBRRL 366 // SPCR 367 SPIE = 7; // SPI Interrupt Enable 368 SPE = 6; // SPI Enable 369 DORD = 5; // Data Order 370 MSTR = 4; // Master/Slave Select 371 CPOL = 3; // Clock polarity 372 CPHA = 2; // Clock Phase 373 SPR = 0; // SPI Clock Rate Selects 374 // SPSR 375 SPIF = 7; // SPI Interrupt Flag 376 WCOL = 6; // Write Collision Flag 377 SPI2X = 0; // Double SPI Speed Bit 378 // WDTCSR 379 WDIF = 7; // Watchdog Timeout Interrupt Flag 380 WDIE = 6; // Watchdog Timeout Interrupt Enable 381 WDP = 0; // Watchdog Timer Prescaler Bits 382 WDCE = 4; // Watchdog Change Enable 383 WDE = 3; // Watch Dog Enable 384 // EICRA 385 ISC2 = 4; // External Interrupt Sense Control Bit 386 ISC1 = 2; // External Interrupt Sense Control Bit 387 ISC0 = 0; // External Interrupt Sense Control Bit 388 // EIMSK 389 INT = 0; // External Interrupt Request 2 Enable 390 // EIFR 391 INTF = 0; // External Interrupt Flags 392 // EECR 393 EERIE = 3; // EEPROM Ready Interrupt Enable 394 EEMWE = 2; // EEPROM Master Write Enable 395 EEWE = 1; // EEPROM Write Enable 396 EERE = 0; // EEPROM Read Enable 397 // PFRC0B 398 PCAE0B = 7; // PSC 0 Capture Enable Input Part B 399 PISEL0B = 6; // PSC 0 Input Select for Part B 400 PELEV0B = 5; // PSC 0 Edge Level Selector on Input Part B 401 PFLTE0B = 4; // PSC 0 Filter Enable on Input Part B 402 PRFM0B = 0; // PSC 0 Retrigger and Fault Mode for Part B 403 // PFRC0A 404 PCAE0A = 7; // PSC 0 Capture Enable Input Part A 405 PISEL0A = 6; // PSC 0 Input Select for Part A 406 PELEV0A = 5; // PSC 0 Edge Level Selector on Input Part A 407 PFLTE0A = 4; // PSC 0 Filter Enable on Input Part A 408 PRFM0A = 0; // PSC 0 Retrigger and Fault Mode for Part A 409 // PCTL0 410 PPRE0 = 6; // PSC 0 Prescaler Selects 411 PBFM0 = 5; // PSC 0 Balance Flank Width Modulation 412 PAOC0B = 4; // PSC 0 Asynchronous Output Control B 413 PAOC0A = 3; // PSC 0 Asynchronous Output Control A 414 PARUN0 = 2; // PSC0 Auto Run 415 PCCYC0 = 1; // PSC0 Complete Cycle 416 PRUN0 = 0; // PSC 0 Run 417 // PCNF0 418 PFIFTY0 = 7; // PSC 0 Fifty 419 PALOCK0 = 6; // PSC 0 Autolock 420 PLOCK0 = 5; // PSC 0 Lock 421 PMODE0 = 3; // PSC 0 Mode 422 POP0 = 2; // PSC 0 Output Polarity 423 PCLKSEL0 = 1; // PSC 0 Input Clock Select 424 // PSOC0 425 PSYNC0 = 4; // Synchronization Out for ADC Selection 426 POEN0B = 2; // PSCOUT01 Output Enable 427 POEN0A = 0; // PSCOUT00 Output Enable 428 // PIM0 429 PSEIE0 = 5; // PSC 0 Synchro Error Interrupt Enable 430 PEVE0B = 4; // External Event B Interrupt Enable 431 PEVE0A = 3; // External Event A Interrupt Enable 432 PEOPE0 = 0; // End of Cycle Interrupt Enable 433 // PIFR0 434 POAC0B = 7; // PSC 0 Output A Activity 435 POAC0A = 6; // PSC 0 Output A Activity 436 PSEI0 = 5; // PSC 0 Synchro Error Interrupt 437 PEV0B = 4; // External Event B Interrupt 438 PEV0A = 3; // External Event A Interrupt 439 PRN0 = 1; // Ramp Number 440 PEOP0 = 0; // End of PSC0 Interrupt 441 // PFRC2B 442 PCAE2B = 7; // PSC 2 Capture Enable Input Part B 443 PISEL2B = 6; // PSC 2 Input Select for Part B 444 PELEV2B = 5; // PSC 2 Edge Level Selector on Input Part B 445 PFLTE2B = 4; // PSC 2 Filter Enable on Input Part B 446 PRFM2B = 0; // PSC 2 Retrigger and Fault Mode for Part B 447 // PFRC2A 448 PCAE2A = 7; // PSC 2 Capture Enable Input Part A 449 PISEL2A = 6; // PSC 2 Input Select for Part A 450 PELEV2A = 5; // PSC 2 Edge Level Selector on Input Part A 451 PFLTE2A = 4; // PSC 2 Filter Enable on Input Part A 452 PRFM2A = 0; // PSC 2 Retrigger and Fault Mode for Part A 453 // PCTL2 454 PPRE2 = 6; // PSC 2 Prescaler Selects 455 PBFM2 = 5; // Balance Flank Width Modulation 456 PAOC2B = 4; // PSC 2 Asynchronous Output Control B 457 PAOC2A = 3; // PSC 2 Asynchronous Output Control A 458 PARUN2 = 2; // PSC2 Auto Run 459 PCCYC2 = 1; // PSC2 Complete Cycle 460 PRUN2 = 0; // PSC 2 Run 461 // PCNF2 462 PFIFTY2 = 7; // PSC 2 Fifty 463 PALOCK2 = 6; // PSC 2 Autolock 464 PLOCK2 = 5; // PSC 2 Lock 465 PMODE2 = 3; // PSC 2 Mode 466 POP2 = 2; // PSC 2 Output Polarity 467 PCLKSEL2 = 1; // PSC 2 Input Clock Select 468 POME2 = 0; // PSC 2 Output Matrix Enable 469 // POM2 470 POMV2B = 4; // Output Matrix Output B Ramps 471 POMV2A = 0; // Output Matrix Output A Ramps 472 // PSOC2 473 POS2 = 6; // PSC 2 Output 23 Select 474 PSYNC2_ = 4; // Synchronization Out for ADC Selection 475 POEN2D = 3; // PSCOUT23 Output Enable 476 POEN2B = 2; // PSCOUT21 Output Enable 477 POEN2C = 1; // PSCOUT22 Output Enable 478 POEN2A = 0; // PSCOUT20 Output Enable 479 // PIM2 480 PSEIE2 = 5; // PSC 2 Synchro Error Interrupt Enable 481 PEVE2B = 4; // External Event B Interrupt Enable 482 PEVE2A = 3; // External Event A Interrupt Enable 483 PEOPE2 = 0; // End of Cycle Interrupt Enable 484 // PIFR2 485 POAC2B = 7; // PSC 2 Output A Activity 486 POAC2A = 6; // PSC 2 Output A Activity 487 PSEI2 = 5; // PSC 2 Synchro Error Interrupt 488 PEV2B = 4; // External Event B Interrupt 489 PEV2A = 3; // External Event A Interrupt 490 PRN2 = 1; // Ramp Number 491 PEOP2 = 0; // End of PSC2 Interrupt 492 493implementation 494 495{$i avrcommon.inc} 496 497procedure PSC2_CAPT_ISR; external name 'PSC2_CAPT_ISR'; // Interrupt 1 PSC2 Capture Event 498procedure PSC2_EC_ISR; external name 'PSC2_EC_ISR'; // Interrupt 2 PSC2 End Cycle 499procedure PSC1_CAPT_ISR; external name 'PSC1_CAPT_ISR'; // Interrupt 3 PSC1 Capture Event 500procedure PSC1_EC_ISR; external name 'PSC1_EC_ISR'; // Interrupt 4 PSC1 End Cycle 501procedure PSC0_CAPT_ISR; external name 'PSC0_CAPT_ISR'; // Interrupt 5 PSC0 Capture Event 502procedure PSC0_EC_ISR; external name 'PSC0_EC_ISR'; // Interrupt 6 PSC0 End Cycle 503procedure ANALOG_COMP_0_ISR; external name 'ANALOG_COMP_0_ISR'; // Interrupt 7 Analog Comparator 0 504procedure ANALOG_COMP_1_ISR; external name 'ANALOG_COMP_1_ISR'; // Interrupt 8 Analog Comparator 1 505procedure ANALOG_COMP_2_ISR; external name 'ANALOG_COMP_2_ISR'; // Interrupt 9 Analog Comparator 2 506procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 10 External Interrupt Request 0 507procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event 508procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 12 Timer/Counter1 Compare Match A 509procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 13 Timer/Counter Compare Match B 510procedure RESERVED15_ISR; external name 'RESERVED15_ISR'; // Interrupt 14 511procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer/Counter1 Overflow 512procedure TIMER0_COMP_A_ISR; external name 'TIMER0_COMP_A_ISR'; // Interrupt 16 Timer/Counter0 Compare Match A 513procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 17 Timer/Counter0 Overflow 514procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 18 ADC Conversion Complete 515procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 19 External Interrupt Request 1 516procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 20 SPI Serial Transfer Complete 517procedure USART__RX_ISR; external name 'USART__RX_ISR'; // Interrupt 21 USART, Rx Complete 518procedure USART__UDRE_ISR; external name 'USART__UDRE_ISR'; // Interrupt 22 USART Data Register Empty 519procedure USART__TX_ISR; external name 'USART__TX_ISR'; // Interrupt 23 USART, Tx Complete 520procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 24 External Interrupt Request 2 521procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 25 Watchdog Timeout Interrupt 522procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 26 EEPROM Ready 523procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 27 Timer Counter 0 Compare Match B 524procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 28 External Interrupt Request 3 525procedure RESERVED30_ISR; external name 'RESERVED30_ISR'; // Interrupt 29 526procedure RESERVED31_ISR; external name 'RESERVED31_ISR'; // Interrupt 30 527procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 31 Store Program Memory Read 528 529procedure _FPC_start; assembler; nostackframe; 530label 531 _start; 532 asm 533 .init 534 .globl _start 535 536 jmp _start 537 jmp PSC2_CAPT_ISR 538 jmp PSC2_EC_ISR 539 jmp PSC1_CAPT_ISR 540 jmp PSC1_EC_ISR 541 jmp PSC0_CAPT_ISR 542 jmp PSC0_EC_ISR 543 jmp ANALOG_COMP_0_ISR 544 jmp ANALOG_COMP_1_ISR 545 jmp ANALOG_COMP_2_ISR 546 jmp INT0_ISR 547 jmp TIMER1_CAPT_ISR 548 jmp TIMER1_COMPA_ISR 549 jmp TIMER1_COMPB_ISR 550 jmp RESERVED15_ISR 551 jmp TIMER1_OVF_ISR 552 jmp TIMER0_COMP_A_ISR 553 jmp TIMER0_OVF_ISR 554 jmp ADC_ISR 555 jmp INT1_ISR 556 jmp SPI__STC_ISR 557 jmp USART__RX_ISR 558 jmp USART__UDRE_ISR 559 jmp USART__TX_ISR 560 jmp INT2_ISR 561 jmp WDT_ISR 562 jmp EE_READY_ISR 563 jmp TIMER0_COMPB_ISR 564 jmp INT3_ISR 565 jmp RESERVED30_ISR 566 jmp RESERVED31_ISR 567 jmp SPM_READY_ISR 568 569 {$i start.inc} 570 571 .weak PSC2_CAPT_ISR 572 .weak PSC2_EC_ISR 573 .weak PSC1_CAPT_ISR 574 .weak PSC1_EC_ISR 575 .weak PSC0_CAPT_ISR 576 .weak PSC0_EC_ISR 577 .weak ANALOG_COMP_0_ISR 578 .weak ANALOG_COMP_1_ISR 579 .weak ANALOG_COMP_2_ISR 580 .weak INT0_ISR 581 .weak TIMER1_CAPT_ISR 582 .weak TIMER1_COMPA_ISR 583 .weak TIMER1_COMPB_ISR 584 .weak RESERVED15_ISR 585 .weak TIMER1_OVF_ISR 586 .weak TIMER0_COMP_A_ISR 587 .weak TIMER0_OVF_ISR 588 .weak ADC_ISR 589 .weak INT1_ISR 590 .weak SPI__STC_ISR 591 .weak USART__RX_ISR 592 .weak USART__UDRE_ISR 593 .weak USART__TX_ISR 594 .weak INT2_ISR 595 .weak WDT_ISR 596 .weak EE_READY_ISR 597 .weak TIMER0_COMPB_ISR 598 .weak INT3_ISR 599 .weak RESERVED30_ISR 600 .weak RESERVED31_ISR 601 .weak SPM_READY_ISR 602 603 .set PSC2_CAPT_ISR, Default_IRQ_handler 604 .set PSC2_EC_ISR, Default_IRQ_handler 605 .set PSC1_CAPT_ISR, Default_IRQ_handler 606 .set PSC1_EC_ISR, Default_IRQ_handler 607 .set PSC0_CAPT_ISR, Default_IRQ_handler 608 .set PSC0_EC_ISR, Default_IRQ_handler 609 .set ANALOG_COMP_0_ISR, Default_IRQ_handler 610 .set ANALOG_COMP_1_ISR, Default_IRQ_handler 611 .set ANALOG_COMP_2_ISR, Default_IRQ_handler 612 .set INT0_ISR, Default_IRQ_handler 613 .set TIMER1_CAPT_ISR, Default_IRQ_handler 614 .set TIMER1_COMPA_ISR, Default_IRQ_handler 615 .set TIMER1_COMPB_ISR, Default_IRQ_handler 616 .set RESERVED15_ISR, Default_IRQ_handler 617 .set TIMER1_OVF_ISR, Default_IRQ_handler 618 .set TIMER0_COMP_A_ISR, Default_IRQ_handler 619 .set TIMER0_OVF_ISR, Default_IRQ_handler 620 .set ADC_ISR, Default_IRQ_handler 621 .set INT1_ISR, Default_IRQ_handler 622 .set SPI__STC_ISR, Default_IRQ_handler 623 .set USART__RX_ISR, Default_IRQ_handler 624 .set USART__UDRE_ISR, Default_IRQ_handler 625 .set USART__TX_ISR, Default_IRQ_handler 626 .set INT2_ISR, Default_IRQ_handler 627 .set WDT_ISR, Default_IRQ_handler 628 .set EE_READY_ISR, Default_IRQ_handler 629 .set TIMER0_COMPB_ISR, Default_IRQ_handler 630 .set INT3_ISR, Default_IRQ_handler 631 .set RESERVED30_ISR, Default_IRQ_handler 632 .set RESERVED31_ISR, Default_IRQ_handler 633 .set SPM_READY_ISR, Default_IRQ_handler 634 end; 635 636end. 637