1unit ATmega162; 2 3{$goto on} 4 5interface 6 7var 8 // TIMER_COUNTER_1 9 TIMSK : byte absolute $00+$59; // Timer/Counter Interrupt Mask Register 10 TIFR : byte absolute $00+$58; // Timer/Counter Interrupt Flag register 11 TCCR1A : byte absolute $00+$4F; // Timer/Counter1 Control Register A 12 TCCR1B : byte absolute $00+$4E; // Timer/Counter1 Control Register B 13 TCNT1 : word absolute $00+$4C; // Timer/Counter1 Bytes 14 TCNT1L : byte absolute $00+$4C; // Timer/Counter1 Bytes 15 TCNT1H : byte absolute $00+$4C+1; // Timer/Counter1 Bytes 16 OCR1A : word absolute $00+$4A; // Timer/Counter1 Output Compare Register A Bytes 17 OCR1AL : byte absolute $00+$4A; // Timer/Counter1 Output Compare Register A Bytes 18 OCR1AH : byte absolute $00+$4A+1; // Timer/Counter1 Output Compare Register A Bytes 19 OCR1B : word absolute $00+$48; // Timer/Counter1 Output Compare Register B Bytes 20 OCR1BL : byte absolute $00+$48; // Timer/Counter1 Output Compare Register B Bytes 21 OCR1BH : byte absolute $00+$48+1; // Timer/Counter1 Output Compare Register B Bytes 22 ICR1 : word absolute $00+$44; // Timer/Counter1 Input Capture Register Bytes 23 ICR1L : byte absolute $00+$44; // Timer/Counter1 Input Capture Register Bytes 24 ICR1H : byte absolute $00+$44+1; // Timer/Counter1 Input Capture Register Bytes 25 // TIMER_COUNTER_2 26 TCCR2 : byte absolute $00+$47; // Timer/Counter Control Register 27 TCNT2 : byte absolute $00+$43; // Timer/Counter Register 28 OCR2 : byte absolute $00+$42; // Output Compare Register 29 ASSR : byte absolute $00+$46; // Asynchronous Status Register 30 // TIMER_COUNTER_3 31 ETIMSK : byte absolute $00+$7D; // Extended Timer/Counter Interrupt Mask Register 32 ETIFR : byte absolute $00+$7C; // Extended Timer/Counter Interrupt Flag register 33 TCCR3A : byte absolute $00+$8B; // Timer/Counter3 Control Register A 34 TCCR3B : byte absolute $00+$8A; // Timer/Counter3 Control Register B 35 TCNT3 : word absolute $00+$88; // Timer/Counter3 Bytes 36 TCNT3L : byte absolute $00+$88; // Timer/Counter3 Bytes 37 TCNT3H : byte absolute $00+$88+1; // Timer/Counter3 Bytes 38 OCR3A : word absolute $00+$86; // Timer/Counter3 Output Compare Register A Bytes 39 OCR3AL : byte absolute $00+$86; // Timer/Counter3 Output Compare Register A Bytes 40 OCR3AH : byte absolute $00+$86+1; // Timer/Counter3 Output Compare Register A Bytes 41 OCR3B : word absolute $00+$84; // Timer/Counte3 Output Compare Register B Bytes 42 OCR3BL : byte absolute $00+$84; // Timer/Counte3 Output Compare Register B Bytes 43 OCR3BH : byte absolute $00+$84+1; // Timer/Counte3 Output Compare Register B Bytes 44 ICR3 : word absolute $00+$80; // Timer/Counter3 Input Capture Register Bytes 45 ICR3L : byte absolute $00+$80; // Timer/Counter3 Input Capture Register Bytes 46 ICR3H : byte absolute $00+$80+1; // Timer/Counter3 Input Capture Register Bytes 47 // ANALOG_COMPARATOR 48 ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register 49 // USART0 50 UDR0 : byte absolute $00+$2C; // USART I/O Data Register 51 UCSR0A : byte absolute $00+$2B; // USART Control and Status Register A 52 UCSR0B : byte absolute $00+$2A; // USART Control and Status Register B 53 UCSR0C : byte absolute $00+$40; // USART Control and Status Register C 54 UBRR0H : byte absolute $00+$40; // USART Baud Rate Register Hight Byte 55 UBRR0L : byte absolute $00+$29; // USART Baud Rate Register Low Byte 56 // USART1 57 UDR : byte absolute $00+$23; // USART I/O Data Register 58 UCSR1A : byte absolute $00+$22; // USART Control and Status Register A 59 UCSR1B : byte absolute $00+$21; // USART Control and Status Register B 60 UCSR1C : byte absolute $00+$5C; // USART Control and Status Register C 61 UBRR1H : byte absolute $00+$5C; // USART Baud Rate Register Highg Byte 62 UBRR1L : byte absolute $00+$20; // USART Baud Rate Register Low Byte 63 // SPI 64 SPCR : byte absolute $00+$2D; // SPI Control Register 65 SPSR : byte absolute $00+$2E; // SPI Status Register 66 SPDR : byte absolute $00+$2F; // SPI Data Register 67 // CPU 68 SREG : byte absolute $00+$5F; // Status Register 69 SP : word absolute $00+$5D; // Stack Pointer 70 SPL : byte absolute $00+$5D; // Stack Pointer 71 SPH : byte absolute $00+$5D+1; // Stack Pointer 72 MCUCR : byte absolute $00+$55; // MCU Control Register 73 MCUCSR : byte absolute $00+$54; // MCU Control And Status Register 74 EMCUCR : byte absolute $00+$56; // Extended MCU Control Register 75 OSCCAL : byte absolute $00+$24; // Oscillator Calibration Value 76 CLKPR : byte absolute $00+$61; // Clock prescale register 77 SFIOR : byte absolute $00+$50; // Special Function IO Register 78 // JTAG 79 OCDR : byte absolute $00+$24; // On-Chip Debug Related Register in I/O Memory 80 // BOOT_LOAD 81 SPMCR : byte absolute $00+$57; // Store Program Memory Control Register 82 // EEPROM 83 EEAR : word absolute $00+$3E; // EEPROM Address Register Bytes 84 EEARL : byte absolute $00+$3E; // EEPROM Address Register Bytes 85 EEARH : byte absolute $00+$3E+1; // EEPROM Address Register Bytes 86 EEDR : byte absolute $00+$3D; // EEPROM Data Register 87 EECR : byte absolute $00+$3C; // EEPROM Control Register 88 // PORTA 89 PORTA : byte absolute $00+$3B; // Port A Data Register 90 DDRA : byte absolute $00+$3A; // Port A Data Direction Register 91 PINA : byte absolute $00+$39; // Port A Input Pins 92 // PORTB 93 PORTB : byte absolute $00+$38; // Port B Data Register 94 DDRB : byte absolute $00+$37; // Port B Data Direction Register 95 PINB : byte absolute $00+$36; // Port B Input Pins 96 // PORTC 97 PORTC : byte absolute $00+$35; // Port C Data Register 98 DDRC : byte absolute $00+$34; // Port C Data Direction Register 99 PINC : byte absolute $00+$33; // Port C Input Pins 100 // PORTD 101 PORTD : byte absolute $00+$32; // Port D Data Register 102 DDRD : byte absolute $00+$31; // Port D Data Direction Register 103 PIND : byte absolute $00+$30; // Port D Input Pins 104 // TIMER_COUNTER_0 105 TCCR0 : byte absolute $00+$53; // Timer/Counter 0 Control Register 106 TCNT0 : byte absolute $00+$52; // Timer/Counter 0 Register 107 OCR0 : byte absolute $00+$51; // Timer/Counter 0 Output Compare Register 108 // WATCHDOG 109 WDTCR : byte absolute $00+$41; // Watchdog Timer Control Register 110 // PORTE 111 PORTE : byte absolute $00+$27; // Data Register, Port E 112 DDRE : byte absolute $00+$26; // Data Direction Register, Port E 113 PINE : byte absolute $00+$25; // Input Pins, Port E 114 // EXTERNAL_INTERRUPT 115 GICR : byte absolute $00+$5B; // General Interrupt Control Register 116 GIFR : byte absolute $00+$5A; // General Interrupt Flag Register 117 PCMSK1 : byte absolute $00+$6C; // Pin Change Mask Register 1 118 PCMSK0 : byte absolute $00+$6B; // Pin Change Enable Mask 119 120const 121 // TIMSK 122 TOIE1 = 7; // Timer/Counter1 Overflow Interrupt Enable 123 OCIE1A = 6; // Timer/Counter1 Output CompareA Match Interrupt Enable 124 OCIE1B = 5; // Timer/Counter1 Output CompareB Match Interrupt Enable 125 TICIE1 = 3; // Timer/Counter1 Input Capture Interrupt Enable 126 // TIFR 127 TOV1 = 7; // Timer/Counter1 Overflow Flag 128 OCF1A = 6; // Output Compare Flag 1A 129 OCF1B = 5; // Output Compare Flag 1B 130 ICF1 = 3; // Input Capture Flag 1 131 // TCCR1A 132 COM1A = 6; // Compare Output Mode 1A, bits 133 COM1B = 4; // Compare Output Mode 1B, bits 134 FOC1A = 3; // Force Output Compare for Channel A 135 FOC1B = 2; // Force Output Compare for Channel B 136 WGM1 = 0; // Pulse Width Modulator Select Bits 137 // TCCR1B 138 ICNC1 = 7; // Input Capture 1 Noise Canceler 139 ICES1 = 6; // Input Capture 1 Edge Select 140 CS1 = 0; // Clock Select1 bits 141 // TCCR2 142 FOC2 = 7; // Forde Output Compare 143 WGM20 = 6; // Pulse Width Modulator Select Bit 0 144 COM2 = 4; // Compare Match Output Mode 145 WGM21 = 3; // Pulse Width Modulator Select Bit 1 146 CS2 = 0; // Clock Select 147 // TIMSK 148 OCIE2 = 4; // Timer/Counter2 Output Compare Match Interrupt Enable 149 TOIE2 = 2; // Timer/Counter2 Overflow Interrupt Enable 150 // TIFR 151 OCF2 = 4; // Output Compare Flag 2 152 TOV2 = 2; // Timer/Counter2 Overflow Flag 153 // ASSR 154 AS2 = 3; // Asynchronous Timer 2 155 TCN2UB = 2; // Timer/Counter2 Update Busy 156 OCR2UB = 1; // Output Compare Register2 Update Busy 157 TCR2UB = 0; // Timer/Counter Control Register2 Update Busy 158 // ETIMSK 159 TICIE3 = 5; // Timer/Counter3 Input Capture Interrupt Enable 160 OCIE3A = 4; // Timer/Counter3 Output CompareA Match Interrupt Enable 161 OCIE3B = 3; // Timer/Counter3 Output CompareB Match Interrupt Enable 162 TOIE3 = 2; // Timer/Counter3 Overflow Interrupt Enable 163 // ETIFR 164 ICF3 = 5; // Input Capture Flag 3 165 OCF3A = 4; // Output Compare Flag 3A 166 OCF3B = 3; // Output Compare Flag 3B 167 TOV3 = 2; // Timer/Counter3 Overflow Flag 168 // TCCR3A 169 COM3A = 6; // Compare Output Mode 3A, bits 170 COM3B = 4; // Compare Output Mode 3B, bits 171 FOC3A = 3; // Force Output Compare for Channel A 172 FOC3B = 2; // Force Output Compare for Channel B 173 WGM3 = 0; // Pulse Width Modulator Select Bits 174 // TCCR3B 175 ICNC3 = 7; // Input Capture 3 Noise Canceler 176 ICES3 = 6; // Input Capture 3 Edge Select 177 CS3 = 0; // Clock Select3 bits 178 // ACSR 179 ACD = 7; // Analog Comparator Disable 180 ACBG = 6; // Analog Comparator Bandgap Select 181 ACO = 5; // Analog Compare Output 182 ACI = 4; // Analog Comparator Interrupt Flag 183 ACIE = 3; // Analog Comparator Interrupt Enable 184 ACIC = 2; // Analog Comparator Input Capture Enable 185 ACIS = 0; // Analog Comparator Interrupt Mode Select bits 186 // UCSR0A 187 RXC0 = 7; // USART Receive Complete 188 TXC0 = 6; // USART Transmitt Complete 189 UDRE0 = 5; // USART Data Register Empty 190 FE0 = 4; // Framing Error 191 DOR0 = 3; // Data overRun 192 UPE0 = 2; // Parity Error 193 U2X0 = 1; // Double the USART transmission speed 194 MPCM0 = 0; // Multi-processor Communication Mode 195 // UCSR0B 196 RXCIE0 = 7; // RX Complete Interrupt Enable 197 TXCIE0 = 6; // TX Complete Interrupt Enable 198 UDRIE0 = 5; // USART Data register Empty Interrupt Enable 199 RXEN0 = 4; // Receiver Enable 200 TXEN0 = 3; // Transmitter Enable 201 UCSZ02 = 2; // Character Size 202 RXB80 = 1; // Receive Data Bit 8 203 TXB80 = 0; // Transmit Data Bit 8 204 // UCSR0C 205 URSEL0 = 7; // Register Select 206 UMSEL0 = 6; // USART Mode Select 207 UPM0 = 4; // Parity Mode Bits 208 USBS0 = 3; // Stop Bit Select 209 UCSZ0 = 1; // Character Size 210 UCPOL0 = 0; // Clock Polarity 211 // UCSR1A 212 RXC1 = 7; // USART Receive Complete 213 TXC1 = 6; // USART Transmitt Complete 214 UDRE1 = 5; // USART Data Register Empty 215 FE1 = 4; // Framing Error 216 DOR1 = 3; // Data overRun 217 UPE1 = 2; // Parity Error 218 U2X1 = 1; // Double the USART transmission speed 219 MPCM1 = 0; // Multi-processor Communication Mode 220 // UCSR1B 221 RXCIE1 = 7; // RX Complete Interrupt Enable 222 TXCIE1 = 6; // TX Complete Interrupt Enable 223 UDRIE1 = 5; // USART Data register Empty Interrupt Enable 224 RXEN1 = 4; // Receiver Enable 225 TXEN1 = 3; // Transmitter Enable 226 UCSZ12 = 2; // Character Size 227 RXB81 = 1; // Receive Data Bit 8 228 TXB81 = 0; // Transmit Data Bit 8 229 // UCSR1C 230 URSEL1 = 7; // Register Select 231 UMSEL1 = 6; // USART Mode Select 232 UPM1 = 4; // Parity Mode Bits 233 USBS1 = 3; // Stop Bit Select 234 UCSZ1 = 1; // Character Size 235 UCPOL1 = 0; // Clock Polarity 236 // SPCR 237 SPIE = 7; // SPI Interrupt Enable 238 SPE = 6; // SPI Enable 239 DORD = 5; // Data Order 240 MSTR = 4; // Master/Slave Select 241 CPOL = 3; // Clock polarity 242 CPHA = 2; // Clock Phase 243 SPR = 0; // SPI Clock Rate Selects 244 // SPSR 245 SPIF = 7; // SPI Interrupt Flag 246 WCOL = 6; // Write Collision Flag 247 SPI2X = 0; // Double SPI Speed Bit 248 // SREG 249 I = 7; // Global Interrupt Enable 250 T = 6; // Bit Copy Storage 251 H = 5; // Half Carry Flag 252 S = 4; // Sign Bit 253 V = 3; // Two's Complement Overflow Flag 254 N = 2; // Negative Flag 255 Z = 1; // Zero Flag 256 C = 0; // Carry Flag 257 // MCUCR 258 SRE = 7; // External SRAM Enable 259 SRW10 = 6; // External SRAM Wait State Select 260 SE = 5; // Sleep Enable 261 SM1 = 4; // Sleep Mode Select 262 ISC1 = 2; // Interrupt Sense Control 1 bits 263 ISC0 = 0; // Interrupt Sense Control 0 bits 264 // MCUCSR 265 JDT = 7; // JTAG Interface Disable 266 SM2 = 5; // Sleep Mode Select Bit 2 267 JTRF = 4; // JTAG Reset Flag 268 WDRF = 3; // Watchdog Reset Flag 269 BORF = 2; // Brown-out Reset Flag 270 EXTRF = 1; // External Reset Flag 271 PORF = 0; // Power-on reset flag 272 // EMCUCR 273 SM0 = 7; // Sleep mode Select Bit 0 274 SRL = 4; // Wait State Sector Limit Bits 275 SRW0 = 2; // Wait State Select Bit 1 for Lower Sector 276 SRW11 = 1; // Wait State Select Bit 1 for Upper Sector 277 ISC2 = 0; // Interrupt Sense Control 2 278 // CLKPR 279 CLKPCE = 7; // Clock Prescaler Change Enable 280 CLKPS = 0; // Clock Prescaler Select Bits 281 // SFIOR 282 TSM = 7; // Timer/Counter Synchronization Mode 283 XMBK = 6; // External Memory Bus Keeper Enable 284 XMM = 3; // External Memory High Mask Bits 285 PUD = 2; // Pull-up Disable 286 PSR2 = 1; // Prescaler Reset Timer/Counter2 287 PSR310 = 0; // Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0 288 // OCDR 289 // MCUCSR 290 JTD = 7; // JTAG Interface Disable 291 // SPMCR 292 SPMIE = 7; // SPM Interrupt Enable 293 RWWSB = 6; // Read While Write Section Busy 294 RWWSRE = 4; // Read While Write secion read enable 295 BLBSET = 3; // Boot Lock Bit Set 296 PGWRT = 2; // Page Write 297 PGERS = 1; // Page Erase 298 SPMEN = 0; // Store Program Memory Enable 299 // EECR 300 EERIE = 3; // EEPROM Ready Interrupt Enable 301 EEMWE = 2; // EEPROM Master Write Enable 302 EEWE = 1; // EEPROM Write Enable 303 EERE = 0; // EEPROM Read Enable 304 // TCCR0 305 FOC0 = 7; // Force Output Compare 306 WGM00 = 6; // Waveform Generation Mode 0 307 COM0 = 4; // Compare Match Output Modes 308 WGM01 = 3; // Waveform Generation Mode 1 309 CS0 = 0; // Clock Selects 310 // TIMSK 311 TOIE0 = 1; // Timer/Counter0 Overflow Interrupt Enable 312 OCIE0 = 0; // Timer/Counter0 Output Compare Match Interrupt register 313 // TIFR 314 TOV0 = 1; // Timer/Counter0 Overflow Flag 315 OCF0 = 0; // Output Compare Flag 0 316 // WDTCR 317 WDCE = 4; // Watchdog Change Enable 318 WDE = 3; // Watch Dog Enable 319 WDP = 0; // Watch Dog Timer Prescaler bits 320 // MCUCR 321 // EMCUCR 322 // GICR 323 INT = 6; // External Interrupt Request 1 Enable 324 INT2 = 5; // External Interrupt Request 2 Enable 325 PCIE = 3; // Pin Change Interrupt Enables 326 IVSEL = 1; // Interrupt Vector Select 327 IVCE = 0; // Interrupt Vector Change Enable 328 // GIFR 329 INTF = 6; // External Interrupt Flags 330 INTF2 = 5; // External Interrupt Flag 2 331 PCIF = 3; // Pin Change Interrupt Flags 332 333implementation 334 335{$i avrcommon.inc} 336 337procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0 338procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1 339procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2 340procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 4 Pin Change Interrupt Request 0 341procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 5 Pin Change Interrupt Request 1 342procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 6 Timer/Counter3 Capture Event 343procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 7 Timer/Counter3 Compare Match A 344procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 8 Timer/Counter3 Compare Match B 345procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 9 Timer/Counter3 Overflow 346procedure TIMER2_COMP_ISR; external name 'TIMER2_COMP_ISR'; // Interrupt 10 Timer/Counter2 Compare Match 347procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 11 Timer/Counter2 Overflow 348procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 12 Timer/Counter1 Capture Event 349procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 13 Timer/Counter1 Compare Match A 350procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 14 Timer/Counter Compare Match B 351procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer/Counter1 Overflow 352procedure TIMER0_COMP_ISR; external name 'TIMER0_COMP_ISR'; // Interrupt 16 Timer/Counter0 Compare Match 353procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 17 Timer/Counter0 Overflow 354procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 18 SPI Serial Transfer Complete 355procedure USART0__RXC_ISR; external name 'USART0__RXC_ISR'; // Interrupt 19 USART0, Rx Complete 356procedure USART1__RXC_ISR; external name 'USART1__RXC_ISR'; // Interrupt 20 USART1, Rx Complete 357procedure USART0__UDRE_ISR; external name 'USART0__UDRE_ISR'; // Interrupt 21 USART0 Data register Empty 358procedure USART1__UDRE_ISR; external name 'USART1__UDRE_ISR'; // Interrupt 22 USART1, Data register Empty 359procedure USART0__TXC_ISR; external name 'USART0__TXC_ISR'; // Interrupt 23 USART0, Tx Complete 360procedure USART1__TXC_ISR; external name 'USART1__TXC_ISR'; // Interrupt 24 USART1, Tx Complete 361procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 25 EEPROM Ready 362procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 26 Analog Comparator 363procedure SPM_RDY_ISR; external name 'SPM_RDY_ISR'; // Interrupt 27 Store Program Memory Read 364 365procedure _FPC_start; assembler; nostackframe; 366label 367 _start; 368 asm 369 .init 370 .globl _start 371 372 jmp _start 373 jmp INT0_ISR 374 jmp INT1_ISR 375 jmp INT2_ISR 376 jmp PCINT0_ISR 377 jmp PCINT1_ISR 378 jmp TIMER3_CAPT_ISR 379 jmp TIMER3_COMPA_ISR 380 jmp TIMER3_COMPB_ISR 381 jmp TIMER3_OVF_ISR 382 jmp TIMER2_COMP_ISR 383 jmp TIMER2_OVF_ISR 384 jmp TIMER1_CAPT_ISR 385 jmp TIMER1_COMPA_ISR 386 jmp TIMER1_COMPB_ISR 387 jmp TIMER1_OVF_ISR 388 jmp TIMER0_COMP_ISR 389 jmp TIMER0_OVF_ISR 390 jmp SPI__STC_ISR 391 jmp USART0__RXC_ISR 392 jmp USART1__RXC_ISR 393 jmp USART0__UDRE_ISR 394 jmp USART1__UDRE_ISR 395 jmp USART0__TXC_ISR 396 jmp USART1__TXC_ISR 397 jmp EE_RDY_ISR 398 jmp ANA_COMP_ISR 399 jmp SPM_RDY_ISR 400 401 {$i start.inc} 402 403 .weak INT0_ISR 404 .weak INT1_ISR 405 .weak INT2_ISR 406 .weak PCINT0_ISR 407 .weak PCINT1_ISR 408 .weak TIMER3_CAPT_ISR 409 .weak TIMER3_COMPA_ISR 410 .weak TIMER3_COMPB_ISR 411 .weak TIMER3_OVF_ISR 412 .weak TIMER2_COMP_ISR 413 .weak TIMER2_OVF_ISR 414 .weak TIMER1_CAPT_ISR 415 .weak TIMER1_COMPA_ISR 416 .weak TIMER1_COMPB_ISR 417 .weak TIMER1_OVF_ISR 418 .weak TIMER0_COMP_ISR 419 .weak TIMER0_OVF_ISR 420 .weak SPI__STC_ISR 421 .weak USART0__RXC_ISR 422 .weak USART1__RXC_ISR 423 .weak USART0__UDRE_ISR 424 .weak USART1__UDRE_ISR 425 .weak USART0__TXC_ISR 426 .weak USART1__TXC_ISR 427 .weak EE_RDY_ISR 428 .weak ANA_COMP_ISR 429 .weak SPM_RDY_ISR 430 431 .set INT0_ISR, Default_IRQ_handler 432 .set INT1_ISR, Default_IRQ_handler 433 .set INT2_ISR, Default_IRQ_handler 434 .set PCINT0_ISR, Default_IRQ_handler 435 .set PCINT1_ISR, Default_IRQ_handler 436 .set TIMER3_CAPT_ISR, Default_IRQ_handler 437 .set TIMER3_COMPA_ISR, Default_IRQ_handler 438 .set TIMER3_COMPB_ISR, Default_IRQ_handler 439 .set TIMER3_OVF_ISR, Default_IRQ_handler 440 .set TIMER2_COMP_ISR, Default_IRQ_handler 441 .set TIMER2_OVF_ISR, Default_IRQ_handler 442 .set TIMER1_CAPT_ISR, Default_IRQ_handler 443 .set TIMER1_COMPA_ISR, Default_IRQ_handler 444 .set TIMER1_COMPB_ISR, Default_IRQ_handler 445 .set TIMER1_OVF_ISR, Default_IRQ_handler 446 .set TIMER0_COMP_ISR, Default_IRQ_handler 447 .set TIMER0_OVF_ISR, Default_IRQ_handler 448 .set SPI__STC_ISR, Default_IRQ_handler 449 .set USART0__RXC_ISR, Default_IRQ_handler 450 .set USART1__RXC_ISR, Default_IRQ_handler 451 .set USART0__UDRE_ISR, Default_IRQ_handler 452 .set USART1__UDRE_ISR, Default_IRQ_handler 453 .set USART0__TXC_ISR, Default_IRQ_handler 454 .set USART1__TXC_ISR, Default_IRQ_handler 455 .set EE_RDY_ISR, Default_IRQ_handler 456 .set ANA_COMP_ISR, Default_IRQ_handler 457 .set SPM_RDY_ISR, Default_IRQ_handler 458 end; 459 460end. 461