1{
2 System register definitions and utility code for Cortex-M3
3
4 Created by Jeppe Johansen 2012 - jeppe@j-software.dk
5}
6unit cortexm3;
7
8interface
9
10{$PACKRECORDS 2}
11const
12 SCS_BASE   = $E000E000;
13 DWT_BASE   = $E0001000;
14 FP_BASE    = $E0002000;
15 ITM_BASE   = $E0000000;
16 TPIU_BASE  = $E0040000;
17 ETM_BASE   = $E0041000;
18
19type
20
21 TNVICRegisters = record
22  ISER: array[0..7] of longword;
23   reserved0: array[0..23] of longword;
24  ICER: array[0..7] of longword;
25   reserved1: array[0..23] of longword;
26  ISPR: array[0..7] of longword;
27   reserved2: array[0..23] of longword;
28  ICPR: array[0..7] of longword;
29   reserved3: array[0..23] of longword;
30  IABR: array[0..7] of longword;
31   reserved4: array[0..55] of longword;
32  IP: array[0..239] of byte;
33   reserved5: array[0..643] of longword;
34  STIR: longword;
35 end;
36
37 TSCBRegisters = record
38  CPUID,                            {!< CPU ID Base Register                                     }
39  ICSR,                             {!< Interrupt Control State Register                         }
40  VTOR,                             {!< Vector Table Offset Register                             }
41  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
42  SCR,                              {!< System Control Register                                  }
43  CCR: longword;                    {!< Configuration Control Register                           }
44  SHP: array[0..11] of byte;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)    }
45  SHCSR,                            {!< System Handler Control and State Register                }
46  CFSR,                             {!< Configurable Fault Status Register                       }
47  HFSR,                             {!< Hard Fault Status Register                               }
48  DFSR,                             {!< Debug Fault Status Register                              }
49  MMFAR,                            {!< Mem Manage Address Register                              }
50  BFAR,                             {!< Bus Fault Address Register                               }
51  AFSR: longword;                   {!< Auxiliary Fault Status Register                          }
52  PFR: array[0..1] of longword;     {!< Processor Feature Register                               }
53  DFR,                              {!< Debug Feature Register                                   }
54  ADR: longword;                    {!< Auxiliary Feature Register                               }
55  MMFR: array[0..3] of longword;    {!< Memory Model Feature Register                            }
56  ISAR: array[0..4] of longword;    {!< ISA Feature Register                                     }
57 end;
58
59 TSysTickRegisters = record
60  Ctrl,
61  Load,
62  Val,
63  Calib: longword;
64 end;
65
66 TIDRegisters = record
67  PID4_7: array[0..3] of longword;
68  PID0_3: array[0..3] of longword;
69  CID: array[0..3] of longword;
70 end;
71
72 TCoreDebugRegisters = record
73  DHCSR,
74  DCRSR,
75  DCRDR,
76  DEMCR: longword;
77 end;
78
79 TFPRegisters = record
80  Ctrl,
81  Remap: longword;
82  Comp: array[0..7] of longword;
83  res: array[0..987] of longword;
84  ID: TIDRegisters;
85 end;
86
87 TDWTEntry = record
88  Comp,
89  Mask,
90  Func,
91  res: longword;
92 end;
93
94 TDWTRegisters = record
95  Ctrl,
96  CycCnt,
97  CPICnt,
98  ExcCnt,
99  SleepCnt,
100  LSUCnt,
101  FoldCnt,
102  PCSR: longword;
103  Entries: array[0..3] of TDWTEntry;
104 end;
105
106 TITMRegisters = record
107  Stimulus: array[0..31] of longword;
108   res0: array[0..($E00-$7C-4)-1] of byte;
109  TraceEnable: longword;
110   res1: array[0..($E40-$E00-4)-1] of byte;
111  TracePrivilege: longword;
112   res2: array[0..($E80-$E40-4)-1] of byte;
113  TraceControl: longword;
114   res3: array[0..($EF8-$E80-4)-1] of byte;
115  IntegrationWrite,
116  IntegrationRead,
117  IntegrationModeCtrl: longword;
118   res4: array[0..($FB0-$F00-4)-1] of byte;
119  LockAccess,
120  LockStatus: longword;
121   res5: array[0..($FD0-$FB4-4)-1] of byte;
122  ID: TIDRegisters;
123 end;
124
125 TTPIURegisters = record
126  SupportedSyncPortSizes,
127  CurrentSyncPortSize: longword;
128   res0: array[0..($10-$04-4)-1] of byte;
129  AsyncColckPrescaler: longword;
130   res1: array[0..($F0-$10-4)-1] of byte;
131  SelectedPinProtocol: longword;
132   res2: array[0..($100-$F0-4)-1] of byte;
133  TriggerControl: array[0..2] of longword;
134   res3: array[0..($200-$108-4)-1] of byte;
135  TestPattern: array[0..2] of longword;
136   res4: array[0..($300-$208-4)-1] of byte;
137  FormatFlushStatus,
138  FormatControl,
139  FormatSyncCounter: longword;
140   res5: array[0..($EF0-$308-4)-1] of byte;
141  ITATBCTR2: longword;
142   res6: longword;
143  ITATBCTR0: longword;
144 end;
145
146var
147 // System Control
148 InterruptControlType: longword     absolute (SCS_BASE+$0004);
149 SCB: TSCBRegisters                 absolute (SCS_BASE+$0D00);
150 SysTick: TSysTickRegisters         absolute (SCS_BASE+$0010);
151 NVIC: TNVICRegisters               absolute (SCS_BASE+$0100);
152 SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000);
153 SCBID: TIDRegisters                absolute (SCS_BASE+$EFD0);
154
155 // Core Debug
156 CoreDebug: TCoreDebugRegisters     absolute (SCS_BASE+$0DF0);
157
158 // Flash Patch
159 FP: TFPRegisters                   absolute FP_BASE;
160
161 DWT: TDWTRegisters                 absolute DWT_BASE;
162
163 ITM: TITMRegisters                 absolute ITM_BASE;
164
165 TPIU: TTPIURegisters               absolute TPIU_BASE;
166
167type
168 TITM_Port = 0..31;
169
170procedure ITM_SendData(Port: TITM_Port; Data: longword); inline;
171
172implementation
173
174const
175 CoreDebug_DEMCR_TRCENA = $01000000;
176 ITM_TCR_ITMENA   = $00000001;
177
178procedure ITM_SendData(Port: TITM_Port; Data: longword);
179begin
180   if ((CoreDebug.DEMCR and CoreDebug_DEMCR_TRCENA) <> 0) and
181      ((itm.TraceControl and ITM_TCR_ITMENA) <> 0) and
182      ((ITM.TraceEnable and (1 shl Port)) <> 0) then
183   begin
184      while ITM.Stimulus[Port] = 0 do;
185      ITM.Stimulus[Port] := Data;
186   end;
187end;
188
189end.
190