1;; Scheduling description for Niagara-4
2;;   Copyright (C) 2012-2020 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3.  If not see
18;; <http://www.gnu.org/licenses/>.
19
20(define_automaton "niagara4_0")
21
22(define_cpu_unit "n4_slot0,n4_slot1,n4_slot2" "niagara4_0")
23(define_reservation "n4_single_issue" "n4_slot0 + n4_slot1 + n4_slot2")
24
25(define_cpu_unit "n4_load_store" "niagara4_0")
26
27(define_insn_reservation "n4_single" 1
28  (and (eq_attr "cpu" "niagara4")
29    (eq_attr "type" "multi,savew,flushw,iflush,trap"))
30  "n4_single_issue")
31
32(define_insn_reservation "n4_integer" 1
33  (and (eq_attr "cpu" "niagara4")
34    (eq_attr "type" "ialu,ialuX,shift,cmove,compare"))
35  "(n4_slot0 | n4_slot1)")
36
37(define_insn_reservation "n4_imul" 12
38  (and (eq_attr "cpu" "niagara4")
39    (eq_attr "type" "imul"))
40  "n4_slot1, nothing*11")
41
42(define_insn_reservation "n4_idiv" 35
43  (and (eq_attr "cpu" "niagara4")
44    (eq_attr "type" "idiv"))
45  "n4_slot1, nothing*34")
46
47(define_insn_reservation "n4_load" 5
48  (and (eq_attr "cpu" "niagara4")
49    (eq_attr "type" "load,fpload,sload"))
50  "(n4_slot0 + n4_load_store), nothing*4")
51
52(define_insn_reservation "n4_store" 1
53  (and (eq_attr "cpu" "niagara4")
54    (eq_attr "type" "store,fpstore"))
55  "(n4_slot0 | n4_slot2) + n4_load_store")
56
57(define_insn_reservation "n4_cti" 1
58  (and (eq_attr "cpu" "niagara4")
59    (eq_attr "type" "cbcond,uncond_cbcond,branch,call,sibcall,call_no_delay_slot,uncond_branch,return"))
60  "n4_slot1")
61
62(define_insn_reservation "n4_fp" 11
63  (and (eq_attr "cpu" "niagara4")
64    (eq_attr "type" "fpmove,fpcmove,fpcrmove,fp,fpcmp,fpmul"))
65  "n4_slot1, nothing*10")
66
67(define_insn_reservation "n4_array" 12
68  (and (eq_attr "cpu" "niagara4")
69    (eq_attr "type" "array,bmask,edge,edgen"))
70  "n4_slot1, nothing*11")
71
72(define_insn_reservation "n4_vis_move_1cycle" 1
73  (and (eq_attr "cpu" "niagara4")
74    (and (eq_attr "type" "vismv")
75      (eq_attr "fptype" "double")))
76  "n4_slot1")
77
78;; The latency numbers for VIS instructions in the reservations below
79;; reflect empirical results, and don't match with the documented
80;; latency numbers in the T4 Processor Supplement.  This is because
81;; the HW chaps didn't feel it necessary to document the complexity in
82;; the PRM, and just assigned a latency of 11 to all/most of the VIS
83;; instructions.
84
85(define_insn_reservation "n4_vis_move_11cycle" 11
86  (and (eq_attr "cpu" "niagara4")
87    (and (eq_attr "type" "vismv")
88      (eq_attr "fptype" "single")))
89  "n4_slot1, nothing*10")
90
91(define_insn_reservation "n4_vis_logical" 3
92  (and (eq_attr "cpu" "niagara4")
93       (ior (and (eq_attr "type" "visl,pdistn")
94                 (eq_attr "fptype" "double"))
95            (eq_attr "type" "viscmp")))
96  "n4_slot1, nothing*2")
97
98(define_insn_reservation "n4_vis_logical_11cycle" 11
99  (and (eq_attr "cpu" "niagara4")
100    (and (eq_attr "type" "visl")
101      (eq_attr "fptype" "single")))
102  "n4_slot1, nothing*10")
103
104(define_insn_reservation "n4_vis_fga" 11
105  (and (eq_attr "cpu" "niagara4")
106    (eq_attr "type" "fga,gsr"))
107  "n4_slot1, nothing*10")
108
109(define_insn_reservation "n4_vis_fgm" 11
110  (and (eq_attr "cpu" "niagara4")
111    (eq_attr "type" "fgm_pack,fgm_mul,pdist"))
112  "n4_slot1, nothing*10")
113
114(define_insn_reservation "n4_fpdivs" 24
115  (and (eq_attr "cpu" "niagara4")
116    (eq_attr "type" "fpdivs,fpsqrts"))
117  "n4_slot1, nothing*23")
118
119(define_insn_reservation "n4_fpdivd" 37
120  (and (eq_attr "cpu" "niagara4")
121    (eq_attr "type" "fpdivd,fpsqrtd"))
122  "n4_slot1, nothing*36")
123