1 /* { dg-do compile } */
2 /* { dg-options "-O2" } */
3 /* { dg-final { scan-assembler-times "addi\tr., r., %lo" 4 } } */
4 /* { dg-final { scan-assembler-times "ldhu\tr., %lo" 4 } } */
5 /* { dg-final { scan-assembler-times "ldh\tr., %lo" 8 } } */
6 /* { dg-final { scan-assembler-times "sth\tr., %lo" 4 } } */
7 
8 /* Check that various address forms involving a symbolic constant
9    with a possible constant offset and/or index register are optimized
10    to generate a %lo relocation in the load/store instructions instead
11    of a plain register indirect addressing mode.  */
12 /* Note: get* uses ldhu but ext* uses ldh since TYPE is signed.  */
13 
14 #define TYPE short
15 
16 struct ss
17 {
18   TYPE x1,x2;
19 };
20 
21 extern TYPE S1;
22 extern TYPE S2[];
23 
24 extern struct ss S3;
25 extern struct ss S4[];
26 
addr1(void)27 TYPE *addr1 (void) { return &S1; }
get1(void)28 TYPE get1 (void) { return S1; }
set1(TYPE value)29 void set1 (TYPE value) { S1 = value; }
30 
addr2(int i)31 TYPE *addr2 (int i) { return &(S2[i]); }
get2(int i)32 TYPE get2 (int i) { return S2[i]; }
set2(int i,TYPE value)33 void set2 (int i, TYPE value) { S2[i] = value; }
34 
addr3(void)35 TYPE *addr3 (void) { return &(S3.x2); }
get3(void)36 TYPE get3 (void) { return S3.x2; }
set3(TYPE value)37 void set3 (TYPE value) { S3.x2 = value; }
38 
addr4(int i)39 TYPE *addr4 (int i) { return &(S4[i].x2); }
get4(int i)40 TYPE get4 (int i) { return S4[i].x2; }
set4(int i,TYPE value)41 void set4 (int i, TYPE value) { S4[i].x2 = value; }
42 
extw1(void)43 int extw1 (void) { return (int)(S1); }
extw2(int i)44 int extw2 (int i) { return (int)(S2[i]); }
extw3(void)45 int extw3 (void) { return (int)(S3.x2); }
extw4(int i)46 int extw4 (int i) { return (int)(S4[i].x2); }
extwu1(void)47 unsigned int extwu1 (void) { return (unsigned int)(S1); }
extwu2(int i)48 unsigned int extwu2 (int i) { return (unsigned int)(S2[i]); }
extwu3(void)49 unsigned int extwu3 (void) { return (unsigned int)(S3.x2); }
extwu4(int i)50 unsigned int extwu4 (int i) { return (unsigned int)(S4[i].x2); }
51 
52