1 /* { dg-do run } */
2 /* z14 only because we need msrkc, msc, msgrkc, msgc */
3 /* { dg-options "-O3 -march=z14 -mzarch --save-temps" } */
4
5 #include <stddef.h>
6 #include <limits.h>
7
8 int __attribute__((noinline,noclone))
smul(int a,int * res)9 smul (int a, int *res)
10 {
11 return __builtin_smul_overflow(a, -1, res);
12 }
13
14 int __attribute__((noinline,noclone))
smull(long a,long * res)15 smull (long a, long *res)
16 {
17 return __builtin_smull_overflow(a, -1, res);
18 }
19
20 int __attribute__((noinline,noclone))
smulll(long long a,long long * res)21 smulll (long long a, long long *res)
22 {
23 return __builtin_smulll_overflow(a, -1, res);
24 }
25
26
27 int
main()28 main ()
29 {
30 int ret = 0;
31 int result;
32 long lresult;
33 long long llresult;
34
35 ret += !!smul (INT_MIN, &result);
36 ret += !!smull (LONG_MIN, &lresult);
37 ret += !!smulll (LLONG_MIN, &llresult);
38
39 if (ret != 3)
40 __builtin_abort ();
41
42 return 0;
43 }
44
45 /* Check that no compare or bitop instructions are emitted. */
46 /* { dg-final { scan-assembler-not "\tcr" } } */
47 /* { dg-final { scan-assembler-not "\txr" } } */
48 /* { dg-final { scan-assembler-not "\tnr" } } */
49 /* { dg-final { scan-assembler-not "\tcgr" } } */
50 /* { dg-final { scan-assembler-not "\txgr" } } */
51 /* { dg-final { scan-assembler-not "\tngr" } } */
52 /* On 31 bit the long long variants use risbgn to merge the 32 bit
53 regs into a 64 bit reg. */
54 /* { dg-final { scan-assembler-not "\trisbg" { target { lp64 } } } } */
55 /* Just one for the ret != 3 comparison. */
56 /* { dg-final { scan-assembler-times "ci" 1 } } */
57 /* { dg-final { scan-assembler-times "\tlochio\t" 3 { target { ! lp64 } } } } */
58 /* { dg-final { scan-assembler-times "\tlocghio\t" 3 { target lp64 } } } */
59