1/* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2021 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21/* Important note about Carry generation in AArch64. 22 23 Unlike some architectures, the C flag generated by a subtract 24 operation, or a simple compare operation is set to 1 if the result 25 does not overflow in an unsigned sense. That is, if there is no 26 borrow needed from a higher word. That means that overflow from 27 addition will set C, but overflow from a subtraction will clear C. 28 We use CC_Cmode to represent detection of overflow from addition as 29 CCmode is used for 'normal' compare (subtraction) operations. For 30 ADC, the representation becomes more complex still, since we cannot 31 use the normal idiom of comparing the result to one of the input 32 operands; instead we use CC_ADCmode to represent this case. */ 33CC_MODE (CCFP); 34CC_MODE (CCFPE); 35CC_MODE (CC_SWP); 36CC_MODE (CC_NZC); /* Only N, Z and C bits of condition flags are valid. 37 (Used with SVE predicate tests.) */ 38CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */ 39CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */ 40CC_MODE (CC_C); /* C represents unsigned overflow of a simple addition. */ 41CC_MODE (CC_ADC); /* Unsigned overflow from an ADC (add with carry). */ 42CC_MODE (CC_V); /* Only V bit of condition flags is valid. */ 43 44/* Half-precision floating point for __fp16. */ 45FLOAT_MODE (HF, 2, 0); 46ADJUST_FLOAT_FORMAT (HF, &ieee_half_format); 47 48/* Vector modes. */ 49 50VECTOR_BOOL_MODE (VNx16BI, 16, 2); 51VECTOR_BOOL_MODE (VNx8BI, 8, 2); 52VECTOR_BOOL_MODE (VNx4BI, 4, 2); 53VECTOR_BOOL_MODE (VNx2BI, 2, 2); 54 55ADJUST_NUNITS (VNx16BI, aarch64_sve_vg * 8); 56ADJUST_NUNITS (VNx8BI, aarch64_sve_vg * 4); 57ADJUST_NUNITS (VNx4BI, aarch64_sve_vg * 2); 58ADJUST_NUNITS (VNx2BI, aarch64_sve_vg); 59 60ADJUST_ALIGNMENT (VNx16BI, 2); 61ADJUST_ALIGNMENT (VNx8BI, 2); 62ADJUST_ALIGNMENT (VNx4BI, 2); 63ADJUST_ALIGNMENT (VNx2BI, 2); 64 65/* Bfloat16 modes. */ 66FLOAT_MODE (BF, 2, 0); 67ADJUST_FLOAT_FORMAT (BF, &arm_bfloat_half_format); 68 69VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */ 70VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI. */ 71VECTOR_MODES (FLOAT, 8); /* V2SF. */ 72VECTOR_MODES (FLOAT, 16); /* V4SF V2DF. */ 73VECTOR_MODE (FLOAT, DF, 1); /* V1DF. */ 74VECTOR_MODE (FLOAT, HF, 2); /* V2HF. */ 75 76/* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */ 77INT_MODE (OI, 32); 78 79/* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers 80 (2 d-regs = 1 q-reg = TImode). */ 81INT_MODE (CI, 48); 82INT_MODE (XI, 64); 83 84/* Define SVE modes for NVECS vectors. VB, VH, VS and VD are the prefixes 85 for 8-bit, 16-bit, 32-bit and 64-bit elements respectively. It isn't 86 strictly necessary to set the alignment here, since the default would 87 be clamped to BIGGEST_ALIGNMENT anyhow, but it seems clearer. */ 88#define SVE_MODES(NVECS, VB, VH, VS, VD) \ 89 VECTOR_MODES_WITH_PREFIX (VNx, INT, 16 * NVECS, 0); \ 90 VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 16 * NVECS, 0); \ 91 \ 92 ADJUST_NUNITS (VB##QI, aarch64_sve_vg * NVECS * 8); \ 93 ADJUST_NUNITS (VH##HI, aarch64_sve_vg * NVECS * 4); \ 94 ADJUST_NUNITS (VS##SI, aarch64_sve_vg * NVECS * 2); \ 95 ADJUST_NUNITS (VD##DI, aarch64_sve_vg * NVECS); \ 96 ADJUST_NUNITS (VH##BF, aarch64_sve_vg * NVECS * 4); \ 97 ADJUST_NUNITS (VH##HF, aarch64_sve_vg * NVECS * 4); \ 98 ADJUST_NUNITS (VS##SF, aarch64_sve_vg * NVECS * 2); \ 99 ADJUST_NUNITS (VD##DF, aarch64_sve_vg * NVECS); \ 100 \ 101 ADJUST_ALIGNMENT (VB##QI, 16); \ 102 ADJUST_ALIGNMENT (VH##HI, 16); \ 103 ADJUST_ALIGNMENT (VS##SI, 16); \ 104 ADJUST_ALIGNMENT (VD##DI, 16); \ 105 ADJUST_ALIGNMENT (VH##BF, 16); \ 106 ADJUST_ALIGNMENT (VH##HF, 16); \ 107 ADJUST_ALIGNMENT (VS##SF, 16); \ 108 ADJUST_ALIGNMENT (VD##DF, 16); 109 110/* Give SVE vectors the names normally used for 256-bit vectors. 111 The actual number depends on command-line flags. */ 112SVE_MODES (1, VNx16, VNx8, VNx4, VNx2) 113SVE_MODES (2, VNx32, VNx16, VNx8, VNx4) 114SVE_MODES (3, VNx48, VNx24, VNx12, VNx6) 115SVE_MODES (4, VNx64, VNx32, VNx16, VNx8) 116 117/* Partial SVE vectors: 118 119 VNx2QI VNx4QI VNx8QI 120 VNx2HI VNx4HI 121 VNx2SI 122 123 In memory they occupy contiguous locations, in the same way as fixed-length 124 vectors. E.g. VNx8QImode is half the size of VNx16QImode. 125 126 Passing 1 as the final argument ensures that the modes come after all 127 other modes in the GET_MODE_WIDER chain, so that we never pick them 128 in preference to a full vector mode. */ 129VECTOR_MODES_WITH_PREFIX (VNx, INT, 2, 1); 130VECTOR_MODES_WITH_PREFIX (VNx, INT, 4, 1); 131VECTOR_MODES_WITH_PREFIX (VNx, INT, 8, 1); 132VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 4, 1); 133VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 8, 1); 134 135ADJUST_NUNITS (VNx2QI, aarch64_sve_vg); 136ADJUST_NUNITS (VNx2HI, aarch64_sve_vg); 137ADJUST_NUNITS (VNx2SI, aarch64_sve_vg); 138ADJUST_NUNITS (VNx2HF, aarch64_sve_vg); 139ADJUST_NUNITS (VNx2BF, aarch64_sve_vg); 140ADJUST_NUNITS (VNx2SF, aarch64_sve_vg); 141 142ADJUST_NUNITS (VNx4QI, aarch64_sve_vg * 2); 143ADJUST_NUNITS (VNx4HI, aarch64_sve_vg * 2); 144ADJUST_NUNITS (VNx4HF, aarch64_sve_vg * 2); 145ADJUST_NUNITS (VNx4BF, aarch64_sve_vg * 2); 146 147ADJUST_NUNITS (VNx8QI, aarch64_sve_vg * 4); 148 149ADJUST_ALIGNMENT (VNx2QI, 1); 150ADJUST_ALIGNMENT (VNx4QI, 1); 151ADJUST_ALIGNMENT (VNx8QI, 1); 152 153ADJUST_ALIGNMENT (VNx2HI, 2); 154ADJUST_ALIGNMENT (VNx4HI, 2); 155ADJUST_ALIGNMENT (VNx2HF, 2); 156ADJUST_ALIGNMENT (VNx2BF, 2); 157ADJUST_ALIGNMENT (VNx4HF, 2); 158ADJUST_ALIGNMENT (VNx4BF, 2); 159 160ADJUST_ALIGNMENT (VNx2SI, 4); 161ADJUST_ALIGNMENT (VNx2SF, 4); 162 163/* Quad float: 128-bit floating mode for long doubles. */ 164FLOAT_MODE (TF, 16, ieee_quad_format); 165 166/* A 4-tuple of SVE vectors with the maximum -msve-vector-bits= setting. 167 Note that this is a limit only on the compile-time sizes of modes; 168 it is not a limit on the runtime sizes, since VL-agnostic code 169 must work with arbitary vector lengths. */ 170#define MAX_BITSIZE_MODE_ANY_MODE (2048 * 4) 171 172/* Coefficient 1 is multiplied by the number of 128-bit chunks in an 173 SVE vector (referred to as "VQ") minus one. */ 174#define NUM_POLY_INT_COEFFS 2 175