1;; Machine description for GNU compiler, VAX Version 2;; Copyright (C) 1987-2021 Free Software Foundation, Inc. 3 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20 21;;- Instruction patterns. When multiple patterns apply, 22;;- the first one in the file is chosen. 23;;- 24;;- See file "rtl.def" for documentation on define_insn, match_*, et al. 25 26;; UNSPEC_VOLATILE usage: 27 28(define_c_enum "unspecv" [ 29 VUNSPEC_BLOCKAGE ; 'blockage' insn to prevent scheduling across an 30 ; insn in the code. 31 VUNSPEC_SYNC_ISTREAM ; sequence of insns to sync the I-stream 32 VUNSPEC_PEM ; 'procedure_entry_mask' insn. 33]) 34 35(define_constants 36 [(VAX_AP_REGNUM 12) ; Register 12 contains the argument pointer 37 (VAX_FP_REGNUM 13) ; Register 13 contains the frame pointer 38 (VAX_SP_REGNUM 14) ; Register 14 contains the stack pointer 39 (VAX_PC_REGNUM 15) ; Register 15 contains the program counter 40 (VAX_PSL_REGNUM 16) ; Register 16 contains the processor status 41 ; and condition codes in particular 42 ] 43) 44 45;; Integer modes supported on VAX, with a mapping from machine mode 46;; to mnemonic suffix. DImode is always a special case. 47(define_mode_iterator VAXint [QI HI SI]) 48(define_mode_iterator VAXintQH [QI HI]) 49(define_mode_iterator VAXintQHSD [QI HI SI DI]) 50(define_mode_attr isfx [(QI "b") (HI "w") (SI "l") (DI "q")]) 51 52;; Similar for float modes supported on VAX. 53(define_mode_iterator VAXfp [SF DF]) 54(define_mode_attr fsfx [(SF "f") (DF "%#")]) 55 56;; Some output patterns want integer immediates with a prefix... 57(define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")]) 58 59(define_mode_iterator VAXcc [CC CCN CCNZ CCZ]) 60(define_mode_iterator VAXccnz [CCN CCNZ CCZ]) 61 62(define_code_iterator any_extract [sign_extract zero_extract]) 63 64;; 65(include "constraints.md") 66(include "predicates.md") 67 68;; Make instructions that set the N, N+Z, and Z condition codes respectively. 69(define_subst "subst_<mode>" 70 [(set (match_operand 0 "") 71 (match_operand 1 "")) 72 (clobber (reg:CC VAX_PSL_REGNUM))] 73 "" 74 [(set (reg:VAXccnz VAX_PSL_REGNUM) 75 (compare:VAXccnz (match_dup 1) 76 (const_int 0))) 77 (set (match_dup 0) 78 (match_dup 1))]) 79 80(define_subst "subst_f<VAXccnz:mode>" 81 [(set (match_operand:VAXfp 0 "") 82 (match_operand:VAXfp 1 "")) 83 (clobber (reg:CC VAX_PSL_REGNUM))] 84 "" 85 [(set (reg:VAXccnz VAX_PSL_REGNUM) 86 (compare:VAXccnz (match_dup 1) 87 (const_double_zero:VAXfp))) 88 (set (match_dup 0) 89 (match_dup 1))]) 90 91;; Select all from the attributes below that apply to a given insn that 92;; has a clobber on CC for the comparison elimination pass to use it in 93;; place of a subsequent comparison instruction matching the mode used 94;; by a comparison operator in branch. 95;; 96;; For example a branch doing `eq' in SImode will use `*cmpsi_ccz', so 97;; to eliminate it a `*movsi_ccz', etc. pattern will be required via the 98;; `ccz' substitution. Analogously for the other CC modes. 99;; 100;; The general `cc' mode, which sets all of the C, N, V and Z condition 101;; codes, has to be handled specially as it makes no sense for the usual 102;; comparison against zero, so no substitution has been defined for it. 103(define_subst_attr "ccn" "subst_ccn" "" "_ccn") 104(define_subst_attr "ccnz" "subst_ccnz" "" "_ccnz") 105(define_subst_attr "ccz" "subst_ccz" "" "_ccz") 106(define_subst_attr "fccn" "subst_fccn" "" "_ccn") 107(define_subst_attr "fccnz" "subst_fccnz" "" "_ccnz") 108(define_subst_attr "fccz" "subst_fccz" "" "_ccz") 109 110(define_insn "*cmp<VAXint:mode>_<VAXcc:mode>" 111 [(set (reg:VAXcc VAX_PSL_REGNUM) 112 (compare:VAXcc (match_operand:VAXint 0 "general_operand" "nrmT,nrmT") 113 (match_operand:VAXint 1 "general_operand" "I,nrmT")))] 114 "reload_completed" 115 "@ 116 tst<VAXint:isfx> %0 117 cmp<VAXint:isfx> %0,%1") 118 119;; We don't have a CMPQ instruction, but we can set the N and Z condition 120;; codes with MOVQ, and also this comparison can be folded into a preceding 121;; operation by the post-reload comparison elimination pass. 122(define_insn "*cmpdi_<VAXccnz:mode>" 123 [(set (reg:VAXccnz VAX_PSL_REGNUM) 124 (compare:VAXccnz (match_operand:DI 0 "general_operand" "r,nmT") 125 (match_operand:DI 1 "const_zero_operand" "I,I"))) 126 (clobber (match_scratch:DI 2 "=X,r"))] 127 "reload_completed" 128 "@ 129 movq %0,%0 130 movq %0,%2") 131 132(define_insn "*cmp<VAXfp:mode>_<VAXccnz:mode>" 133 [(set (reg:VAXccnz VAX_PSL_REGNUM) 134 (compare:VAXccnz (match_operand:VAXfp 0 "general_operand" "gF,gF") 135 (match_operand:VAXfp 1 "general_operand" "G,gF")))] 136 "reload_completed" 137 "@ 138 tst<VAXfp:fsfx> %0 139 cmp<VAXfp:fsfx> %0,%1") 140 141(define_insn "*bit<VAXint:mode>_<VAXccnz:mode>" 142 [(set (reg:VAXccnz VAX_PSL_REGNUM) 143 (compare:VAXccnz 144 (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT") 145 (match_operand:VAXint 1 "general_operand" "nrmT")) 146 (const_int 0)))] 147 "reload_completed" 148 "bit<VAXint:isfx> %0,%1") 149 150;; The VAX has no sCOND insns. It does have add/subtract with carry 151;; which could be used to implement the sltu and sgeu patterns. However, 152;; to do this properly requires a complete rewrite of the compare insns 153;; to keep them together with the sltu/sgeu insns until after the 154;; reload pass is complete. The previous implementation didn't do this 155;; and has been deleted. 156 157 158(define_insn_and_split "mov<mode>" 159 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 160 (match_operand:VAXfp 1 "general_operand" "G,gF"))] 161 "" 162 "#" 163 "reload_completed" 164 [(parallel 165 [(set (match_dup 0) 166 (match_dup 1)) 167 (clobber (reg:CC VAX_PSL_REGNUM))])] 168 "") 169 170(define_insn "*mov<mode><fccn><fccnz><fccz>" 171 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 172 (match_operand:VAXfp 1 "general_operand" "G,gF")) 173 (clobber (reg:CC VAX_PSL_REGNUM))] 174 "reload_completed" 175 "@ 176 clr<VAXfp:fsfx> %0 177 mov<VAXfp:fsfx> %1,%0") 178 179;; Some VAXen don't support this instruction. 180;;(define_insn_and_split "movti" 181;; [(set (match_operand:TI 0 "nonimmediate_operand" "=g") 182;; (match_operand:TI 1 "general_operand" "g"))] 183;; "" 184;; "#" 185;; "reload_completed" 186;; [(parallel 187;; [(set (match_dup 0) 188;; (match_dup 1)) 189;; (clobber (reg:CC VAX_PSL_REGNUM))])] 190;; "") 191;; 192;;(define_insn "*movti<ccn><ccnz><ccz>" 193;; [(set (match_operand:TI 0 "nonimmediate_operand" "=g") 194;; (match_operand:TI 1 "general_operand" "g")) 195;; (clobber (reg:CC VAX_PSL_REGNUM))] 196;; "reload_completed" 197;; "movo %1,%0") 198 199(define_insn_and_split "movdi" 200 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 201 (match_operand:DI 1 "general_operand" "g"))] 202 "" 203 "#" 204 "reload_completed" 205 [(parallel 206 [(set (match_dup 0) 207 (match_dup 1)) 208 (clobber (reg:CC VAX_PSL_REGNUM))])] 209 "") 210 211;; In some cases `vax_output_int_move' splits a `DImode' move into a pair 212;; of `SImode' moves, in which case the flags aren't usefully set. Have 213;; separate patterns then, for the cases where the move may and may not be 214;; split each. We use the outer condition only so in some cases we will 215;; fail to notice the move does not actually get split, but this is OK. 216(define_insn "*movdi_maybe_split" 217 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 218 (match_operand:DI 1 "general_operand" "g")) 219 (clobber (reg:CC VAX_PSL_REGNUM))] 220 "reload_completed && vax_maybe_split_dimode_move (operands)" 221 "* return vax_output_int_move (insn, operands, DImode);") 222 223(define_insn "*movdi_unsplit<ccn><ccnz><ccz>" 224 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 225 (match_operand:DI 1 "general_operand" "g")) 226 (clobber (reg:CC VAX_PSL_REGNUM))] 227 "reload_completed && !vax_maybe_split_dimode_move (operands)" 228 "* return vax_output_int_move (insn, operands, DImode);") 229 230;; The VAX move instructions have space-time tradeoffs. On a MicroVAX 231;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl 232;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles 233;; if the constant is smaller than 4 bytes, 3 cycles for a longword 234;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster 235;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt 236;; instructions take 4 cycles. inc takes 3 cycles. The machine description 237;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl 238;; instead of movl). 239 240;; Cycle counts for other models may vary (on a VAX 750 they are similar, 241;; but on a VAX 9000 most move and add instructions with one constant 242;; operand take 1 cycle). 243 244;; Loads of constants between 64 and 128 used to be done with 245;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space. 246 247(define_expand "movsi" 248 [(set (match_operand:SI 0 "nonimmediate_operand" "") 249 (match_operand:SI 1 "general_operand" ""))] 250 "" 251 " 252{ 253#ifdef NO_EXTERNAL_INDIRECT_ADDRESS 254 if (flag_pic 255 && GET_CODE (operands[1]) == CONST 256 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF 257 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0))) 258 { 259 rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0); 260 rtx const_int = XEXP (XEXP (operands[1], 0), 1); 261 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); 262 emit_move_insn (temp, symbol_ref); 263 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int)); 264 DONE; 265 } 266#endif 267}") 268 269(define_insn_and_split "movsi_2" 270 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 271 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))] 272 "" 273 "#" 274 "reload_completed" 275 [(parallel 276 [(set (match_dup 0) 277 (match_dup 1)) 278 (clobber (reg:CC VAX_PSL_REGNUM))])] 279 "") 280 281(define_insn "*movsi_2<ccn><ccnz><ccz>" 282 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 283 (match_operand:SI 1 "nonsymbolic_operand" "nrmT")) 284 (clobber (reg:CC VAX_PSL_REGNUM))] 285 "reload_completed" 286 "* return vax_output_int_move (insn, operands, SImode);") 287 288(define_insn_and_split "mov<mode>" 289 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g") 290 (match_operand:VAXintQH 1 "general_operand" "g"))] 291 "" 292 "#" 293 "reload_completed" 294 [(parallel 295 [(set (match_dup 0) 296 (match_dup 1)) 297 (clobber (reg:CC VAX_PSL_REGNUM))])] 298 "") 299 300(define_insn "*mov<mode><ccn><ccnz><ccz>" 301 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g") 302 (match_operand:VAXintQH 1 "general_operand" "g")) 303 (clobber (reg:CC VAX_PSL_REGNUM))] 304 "reload_completed" 305 "* return vax_output_int_move (insn, operands, <MODE>mode);") 306 307(define_insn_and_split "movstricthi" 308 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) 309 (match_operand:HI 1 "general_operand" "g"))] 310 "" 311 "#" 312 "reload_completed" 313 [(parallel 314 [(set (strict_low_part (match_dup 0)) 315 (match_dup 1)) 316 (clobber (reg:CC VAX_PSL_REGNUM))])] 317 "") 318 319(define_insn "*movstricthi<ccn><ccnz><ccz>" 320 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) 321 (match_operand:HI 1 "general_operand" "g")) 322 (clobber (reg:CC VAX_PSL_REGNUM))] 323 "reload_completed" 324 "* 325{ 326 if (CONST_INT_P (operands[1])) 327 { 328 int i = INTVAL (operands[1]); 329 if (i == 0) 330 return \"clrw %0\"; 331 else if ((unsigned int)i < 64) 332 return \"movw %1,%0\"; 333 else if ((unsigned int)~i < 64) 334 return \"mcomw %H1,%0\"; 335 else if ((unsigned int)i < 256) 336 return \"movzbw %1,%0\"; 337 } 338 return \"movw %1,%0\"; 339}") 340 341(define_insn_and_split "movstrictqi" 342 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r")) 343 (match_operand:QI 1 "general_operand" "g"))] 344 "" 345 "#" 346 "reload_completed" 347 [(parallel 348 [(set (strict_low_part (match_dup 0)) 349 (match_dup 1)) 350 (clobber (reg:CC VAX_PSL_REGNUM))])] 351 "") 352 353(define_insn "*movstrictqi<ccn><ccnz><ccz>" 354 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r")) 355 (match_operand:QI 1 "general_operand" "g")) 356 (clobber (reg:CC VAX_PSL_REGNUM))] 357 "reload_completed" 358 "* 359{ 360 if (CONST_INT_P (operands[1])) 361 { 362 int i = INTVAL (operands[1]); 363 if (i == 0) 364 return \"clrb %0\"; 365 else if ((unsigned int)~i < 64) 366 return \"mcomb %B1,%0\"; 367 } 368 return \"movb %1,%0\"; 369}") 370 371;; This is here to accept 4 arguments and pass the first 3 along 372;; to the movmemhi1 pattern that really does the work. 373(define_expand "cpymemhi" 374 [(set (match_operand:BLK 0 "memory_operand" "") 375 (match_operand:BLK 1 "memory_operand" "")) 376 (use (match_operand:HI 2 "general_operand" "")) 377 (match_operand 3 "" "")] 378 "" 379 " 380{ 381 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2])); 382 DONE; 383}") 384 385(define_expand "movmemhi" 386 [(set (match_operand:BLK 0 "memory_operand" "") 387 (match_operand:BLK 1 "memory_operand" "")) 388 (use (match_operand:HI 2 "general_operand" "")) 389 (match_operand 3 "" "")] 390 "" 391 " 392{ 393 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2])); 394 DONE; 395}") 396 397;; The definition of this insn does not really explain what it does, 398;; but it should suffice 399;; that anything generated as this insn will be recognized as one 400;; and that it won't successfully combine with anything. 401 402(define_insn_and_split "movmemhi1" 403 [(set (match_operand:BLK 0 "memory_operand" "=o") 404 (match_operand:BLK 1 "memory_operand" "o")) 405 (use (match_operand:HI 2 "general_operand" "g")) 406 (clobber (reg:SI 0)) 407 (clobber (reg:SI 1)) 408 (clobber (reg:SI 2)) 409 (clobber (reg:SI 3)) 410 (clobber (reg:SI 4)) 411 (clobber (reg:SI 5))] 412 "" 413 "#" 414 "reload_completed" 415 [(parallel 416 [(set (match_dup 0) 417 (match_dup 1)) 418 (use (match_dup 2)) 419 (clobber (reg:SI 0)) 420 (clobber (reg:SI 1)) 421 (clobber (reg:SI 2)) 422 (clobber (reg:SI 3)) 423 (clobber (reg:SI 4)) 424 (clobber (reg:SI 5)) 425 (clobber (reg:CC VAX_PSL_REGNUM))])] 426 "") 427 428(define_insn "*movmemhi1" 429 [(set (match_operand:BLK 0 "memory_operand" "=o") 430 (match_operand:BLK 1 "memory_operand" "o")) 431 (use (match_operand:HI 2 "general_operand" "g")) 432 (clobber (reg:SI 0)) 433 (clobber (reg:SI 1)) 434 (clobber (reg:SI 2)) 435 (clobber (reg:SI 3)) 436 (clobber (reg:SI 4)) 437 (clobber (reg:SI 5)) 438 (clobber (reg:CC VAX_PSL_REGNUM))] 439 "reload_completed" 440 "movc3 %2,%1,%0") 441 442;; Extension and truncation insns. 443 444(define_insn_and_split "truncsiqi2" 445 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 446 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))] 447 "" 448 "#" 449 "reload_completed" 450 [(parallel 451 [(set (match_dup 0) 452 (truncate:QI (match_dup 1))) 453 (clobber (reg:CC VAX_PSL_REGNUM))])] 454 "") 455 456(define_insn "*truncsiqi2<ccn><ccnz><ccz>" 457 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 458 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT"))) 459 (clobber (reg:CC VAX_PSL_REGNUM))] 460 "reload_completed" 461 "cvtlb %1,%0") 462 463(define_insn_and_split "truncsihi2" 464 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 465 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))] 466 "" 467 "#" 468 "reload_completed" 469 [(parallel 470 [(set (match_dup 0) 471 (truncate:HI (match_dup 1))) 472 (clobber (reg:CC VAX_PSL_REGNUM))])] 473 "") 474 475(define_insn "*truncsihi2<ccn><ccnz><ccz>" 476 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 477 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT"))) 478 (clobber (reg:CC VAX_PSL_REGNUM))] 479 "reload_completed" 480 "cvtlw %1,%0") 481 482(define_insn_and_split "trunchiqi2" 483 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 484 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))] 485 "" 486 "#" 487 "reload_completed" 488 [(parallel 489 [(set (match_dup 0) 490 (truncate:QI (match_dup 1))) 491 (clobber (reg:CC VAX_PSL_REGNUM))])] 492 "") 493 494(define_insn "*trunchiqi2<ccn><ccnz><ccz>" 495 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 496 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g"))) 497 (clobber (reg:CC VAX_PSL_REGNUM))] 498 "reload_completed" 499 "cvtwb %1,%0") 500 501(define_insn_and_split "extendhisi2" 502 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 503 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] 504 "" 505 "#" 506 "reload_completed" 507 [(parallel 508 [(set (match_dup 0) 509 (sign_extend:SI (match_dup 1))) 510 (clobber (reg:CC VAX_PSL_REGNUM))])] 511 "") 512 513(define_insn "*extendhisi2<ccn><ccnz><ccz>" 514 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 515 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g"))) 516 (clobber (reg:CC VAX_PSL_REGNUM))] 517 "reload_completed" 518 "cvtwl %1,%0") 519 520(define_insn_and_split "extendqihi2" 521 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 522 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] 523 "" 524 "#" 525 "reload_completed" 526 [(parallel 527 [(set (match_dup 0) 528 (sign_extend:HI (match_dup 1))) 529 (clobber (reg:CC VAX_PSL_REGNUM))])] 530 "") 531 532(define_insn "*extendqihi2<ccn><ccnz><ccz>" 533 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 534 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g"))) 535 (clobber (reg:CC VAX_PSL_REGNUM))] 536 "reload_completed" 537 "cvtbw %1,%0") 538 539(define_insn_and_split "extendqisi2" 540 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 541 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] 542 "" 543 "#" 544 "reload_completed" 545 [(parallel 546 [(set (match_dup 0) 547 (sign_extend:SI (match_dup 1))) 548 (clobber (reg:CC VAX_PSL_REGNUM))])] 549 "") 550 551(define_insn "*extendqisi2<ccn><ccnz><ccz>" 552 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 553 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g"))) 554 (clobber (reg:CC VAX_PSL_REGNUM))] 555 "reload_completed" 556 "cvtbl %1,%0") 557 558(define_insn_and_split "extendsfdf2" 559 [(set (match_operand:DF 0 "nonimmediate_operand" "=g") 560 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))] 561 "" 562 "#" 563 "reload_completed" 564 [(parallel 565 [(set (match_dup 0) 566 (float_extend:DF (match_dup 1))) 567 (clobber (reg:CC VAX_PSL_REGNUM))])] 568 "") 569 570(define_insn "*extendsfdf2<fccn><fccnz><fccz>" 571 [(set (match_operand:DF 0 "nonimmediate_operand" "=g") 572 (float_extend:DF (match_operand:SF 1 "general_operand" "gF"))) 573 (clobber (reg:CC VAX_PSL_REGNUM))] 574 "reload_completed" 575 "cvtf%# %1,%0") 576 577(define_insn_and_split "truncdfsf2" 578 [(set (match_operand:SF 0 "nonimmediate_operand" "=g") 579 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))] 580 "" 581 "#" 582 "reload_completed" 583 [(parallel 584 [(set (match_dup 0) 585 (float_truncate:SF (match_dup 1))) 586 (clobber (reg:CC VAX_PSL_REGNUM))])] 587 "") 588 589(define_insn "*truncdfsf2<fccn><fccnz><fccz>" 590 [(set (match_operand:SF 0 "nonimmediate_operand" "=g") 591 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF"))) 592 (clobber (reg:CC VAX_PSL_REGNUM))] 593 "reload_completed" 594 "cvt%#f %1,%0") 595 596(define_insn_and_split "zero_extendhisi2" 597 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 598 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] 599 "" 600 "#" 601 "reload_completed" 602 [(parallel 603 [(set (match_dup 0) 604 (zero_extend:SI (match_dup 1))) 605 (clobber (reg:CC VAX_PSL_REGNUM))])] 606 "") 607 608(define_insn "*zero_extendhisi2<ccn><ccnz><ccz>" 609 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 610 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g"))) 611 (clobber (reg:CC VAX_PSL_REGNUM))] 612 "reload_completed" 613 "movzwl %1,%0") 614 615(define_insn_and_split "zero_extendqihi2" 616 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 617 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] 618 "" 619 "#" 620 "reload_completed" 621 [(parallel 622 [(set (match_dup 0) 623 (zero_extend:HI (match_dup 1))) 624 (clobber (reg:CC VAX_PSL_REGNUM))])] 625 "") 626 627(define_insn "*zero_extendqihi2<ccn><ccnz><ccz>" 628 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 629 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g"))) 630 (clobber (reg:CC VAX_PSL_REGNUM))] 631 "reload_completed" 632 "movzbw %1,%0") 633 634(define_insn_and_split "zero_extendqisi2" 635 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 636 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] 637 "" 638 "#" 639 "reload_completed" 640 [(parallel 641 [(set (match_dup 0) 642 (zero_extend:SI (match_dup 1))) 643 (clobber (reg:CC VAX_PSL_REGNUM))])] 644 "") 645 646(define_insn "*zero_extendqisi2<ccn><ccnz><ccz>" 647 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 648 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g"))) 649 (clobber (reg:CC VAX_PSL_REGNUM))] 650 "reload_completed" 651 "movzbl %1,%0") 652 653;; Fix-to-float conversion insns. 654 655(define_insn_and_split "float<VAXint:mode><VAXfp:mode>2" 656 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g") 657 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))] 658 "" 659 "#" 660 "reload_completed" 661 [(parallel 662 [(set (match_dup 0) 663 (float:VAXfp (match_dup 1))) 664 (clobber (reg:CC VAX_PSL_REGNUM))])] 665 "") 666 667(define_insn "*float<VAXint:mode><VAXfp:mode>2<fccn><fccnz><fccz>" 668 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g") 669 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g"))) 670 (clobber (reg:CC VAX_PSL_REGNUM))] 671 "reload_completed" 672 "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0") 673 674;; Float-to-fix conversion insns. 675 676(define_insn_and_split "fix_trunc<VAXfp:mode><VAXint:mode>2" 677 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 678 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF")))] 679 "" 680 "#" 681 "reload_completed" 682 [(parallel 683 [(set (match_dup 0) 684 (fix:VAXint (match_dup 1))) 685 (clobber (reg:CC VAX_PSL_REGNUM))])] 686 "") 687 688(define_insn "*fix_trunc<VAXfp:mode><VAXint:mode>2<ccn><ccnz><ccz>" 689 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 690 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF"))) 691 (clobber (reg:CC VAX_PSL_REGNUM))] 692 "reload_completed" 693 "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0") 694 695(define_expand "fixuns_trunc<VAXfp:mode><VAXint:mode>2" 696 [(set (match_operand:VAXint 0 "nonimmediate_operand" "") 697 (fix:VAXint (match_operand:VAXfp 1 "general_operand")))] 698 "") 699 700;;- All kinds of add instructions. 701 702(define_insn_and_split "add<mode>3" 703 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 704 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF") 705 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))] 706 "" 707 "#" 708 "reload_completed" 709 [(parallel 710 [(set (match_dup 0) 711 (plus:VAXfp (match_dup 1) 712 (match_dup 2))) 713 (clobber (reg:CC VAX_PSL_REGNUM))])] 714 "") 715 716(define_insn "*add<mode>3<fccn><fccnz><fccz>" 717 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 718 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF") 719 (match_operand:VAXfp 2 "general_operand" "gF,0,gF"))) 720 (clobber (reg:CC VAX_PSL_REGNUM))] 721 "reload_completed" 722 "@ 723 add<VAXfp:fsfx>2 %2,%0 724 add<VAXfp:fsfx>2 %1,%0 725 add<VAXfp:fsfx>3 %1,%2,%0") 726 727(define_insn_and_split "add<mode>3" 728 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 729 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT") 730 (match_operand:VAXint 2 "general_operand" "nrmT")))] 731 "" 732 "#" 733 "reload_completed" 734 [(parallel 735 [(set (match_dup 0) 736 (plus:VAXint (match_dup 1) 737 (match_dup 2))) 738 (clobber (reg:CC VAX_PSL_REGNUM))])] 739 "") 740 741(define_insn "*add<mode>3<ccn><ccnz><ccz>" 742 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 743 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT") 744 (match_operand:VAXint 2 "general_operand" "nrmT"))) 745 (clobber (reg:CC VAX_PSL_REGNUM))] 746 "reload_completed" 747 "* return vax_output_int_add (insn, operands, <MODE>mode);") 748 749(define_expand "adddi3" 750 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 751 (plus:DI (match_operand:DI 1 "general_operand" "g") 752 (match_operand:DI 2 "general_operand" "g")))] 753 "!reload_in_progress" 754 "vax_expand_addsub_di_operands (operands, PLUS); DONE;") 755 756(define_insn_and_split "adcdi3" 757 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr") 758 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0") 759 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))] 760 "TARGET_QMATH" 761 "#" 762 "&& reload_completed" 763 [(parallel 764 [(set (match_dup 0) 765 (plus:DI (match_dup 1) 766 (match_dup 2))) 767 (clobber (reg:CC VAX_PSL_REGNUM))])] 768 "") 769 770(define_insn "*adcdi3<ccn>" 771 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr") 772 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0") 773 (match_operand:DI 2 "general_addsub_di_operand" "nRr"))) 774 (clobber (reg:CC VAX_PSL_REGNUM))] 775 "TARGET_QMATH && reload_completed" 776 "* return vax_output_int_add (insn, operands, DImode);") 777 778;; The add-with-carry (adwc) instruction only accepts two operands. 779(define_insn_and_split "adddi3_old" 780 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>") 781 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>") 782 (match_operand:DI 2 "general_operand" "Fsro,Fs")))] 783 "!TARGET_QMATH" 784 "#" 785 "&& reload_completed" 786 [(parallel 787 [(set (match_dup 0) 788 (plus:DI (match_dup 1) 789 (match_dup 2))) 790 (clobber (reg:CC VAX_PSL_REGNUM))])] 791 "") 792 793(define_insn "*adddi3_old<ccn>" 794 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>") 795 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>") 796 (match_operand:DI 2 "general_operand" "Fsro,Fs"))) 797 (clobber (reg:CC VAX_PSL_REGNUM))] 798 "!TARGET_QMATH && reload_completed" 799 "* return vax_output_int_add (insn, operands, DImode);") 800 801;;- All kinds of subtract instructions. 802 803(define_insn_and_split "sub<mode>3" 804 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 805 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF") 806 (match_operand:VAXfp 2 "general_operand" "gF,gF")))] 807 "" 808 "#" 809 "reload_completed" 810 [(parallel 811 [(set (match_dup 0) 812 (minus:VAXfp (match_dup 1) 813 (match_dup 2))) 814 (clobber (reg:CC VAX_PSL_REGNUM))])] 815 "") 816 817(define_insn "*sub<mode>3<fccn><fccnz><fccz>" 818 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 819 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF") 820 (match_operand:VAXfp 2 "general_operand" "gF,gF"))) 821 (clobber (reg:CC VAX_PSL_REGNUM))] 822 "reload_completed" 823 "@ 824 sub<VAXfp:fsfx>2 %2,%0 825 sub<VAXfp:fsfx>3 %2,%1,%0") 826 827(define_insn_and_split "sub<mode>3" 828 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 829 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 830 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))] 831 "" 832 "#" 833 "reload_completed" 834 [(parallel 835 [(set (match_dup 0) 836 (minus:VAXint (match_dup 1) 837 (match_dup 2))) 838 (clobber (reg:CC VAX_PSL_REGNUM))])] 839 "") 840 841(define_insn "*sub<mode>3<ccn><ccnz><ccz>" 842 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 843 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 844 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT"))) 845 (clobber (reg:CC VAX_PSL_REGNUM))] 846 "reload_completed" 847 "@ 848 sub<VAXint:isfx>2 %2,%0 849 sub<VAXint:isfx>3 %2,%1,%0") 850 851(define_insn "*sub<mode>3_cc" 852 [(set (reg:CC VAX_PSL_REGNUM) 853 (compare:CC (match_operand:VAXint 1 "general_operand" "0,nrmT") 854 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT"))) 855 (set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 856 (minus:VAXint (match_dup 1) 857 (match_dup 2)))] 858 "reload_completed" 859 "@ 860 sub<VAXint:isfx>2 %2,%0 861 sub<VAXint:isfx>3 %2,%1,%0") 862 863(define_expand "subdi3" 864 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 865 (minus:DI (match_operand:DI 1 "general_operand" "g") 866 (match_operand:DI 2 "general_operand" "g")))] 867 "!reload_in_progress" 868 "vax_expand_addsub_di_operands (operands, MINUS); DONE;") 869 870(define_insn_and_split "sbcdi3" 871 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr") 872 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I") 873 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))] 874 "TARGET_QMATH" 875 "#" 876 "&& reload_completed" 877 [(parallel 878 [(set (match_dup 0) 879 (minus:DI (match_dup 1) 880 (match_dup 2))) 881 (clobber (reg:CC VAX_PSL_REGNUM))])] 882 "") 883 884(define_insn "*sbcdi3<ccn>" 885 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr") 886 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I") 887 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr"))) 888 (clobber (reg:CC VAX_PSL_REGNUM))] 889 "TARGET_QMATH && reload_completed" 890 "* return vax_output_int_subtract (insn, operands, DImode);") 891 892;; The subtract-with-carry (sbwc) instruction only takes two operands. 893(define_insn_and_split "subdi3_old" 894 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>") 895 (minus:DI (match_operand:DI 1 "general_operand" "0,or>") 896 (match_operand:DI 2 "general_operand" "Fsor,Fs")))] 897 "!TARGET_QMATH" 898 "#" 899 "&& reload_completed" 900 [(parallel 901 [(set (match_dup 0) 902 (minus:DI (match_dup 1) 903 (match_dup 2))) 904 (clobber (reg:CC VAX_PSL_REGNUM))])] 905 "") 906 907(define_insn "*subdi3_old<ccn>" 908 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>") 909 (minus:DI (match_operand:DI 1 "general_operand" "0,or>") 910 (match_operand:DI 2 "general_operand" "Fsor,Fs"))) 911 (clobber (reg:CC VAX_PSL_REGNUM))] 912 "!TARGET_QMATH && reload_completed" 913 "* return vax_output_int_subtract (insn, operands, DImode);") 914 915;;- Multiply instructions. 916 917(define_insn_and_split "mul<mode>3" 918 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 919 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF") 920 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))] 921 "" 922 "#" 923 "reload_completed" 924 [(parallel 925 [(set (match_dup 0) 926 (mult:VAXfp (match_dup 1) 927 (match_dup 2))) 928 (clobber (reg:CC VAX_PSL_REGNUM))])] 929 "") 930 931(define_insn "*mul<mode>3<fccn><fccnz><fccz>" 932 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 933 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF") 934 (match_operand:VAXfp 2 "general_operand" "gF,0,gF"))) 935 (clobber (reg:CC VAX_PSL_REGNUM))] 936 "reload_completed" 937 "@ 938 mul<VAXfp:fsfx>2 %2,%0 939 mul<VAXfp:fsfx>2 %1,%0 940 mul<VAXfp:fsfx>3 %1,%2,%0") 941 942(define_insn_and_split "mul<mode>3" 943 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 944 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 945 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))] 946 "" 947 "#" 948 "reload_completed" 949 [(parallel 950 [(set (match_dup 0) 951 (mult:VAXint (match_dup 1) 952 (match_dup 2))) 953 (clobber (reg:CC VAX_PSL_REGNUM))])] 954 "") 955 956(define_insn "*mul<mode>3<ccn><ccnz><ccz>" 957 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 958 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 959 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT"))) 960 (clobber (reg:CC VAX_PSL_REGNUM))] 961 "reload_completed" 962 "@ 963 mul<VAXint:isfx>2 %2,%0 964 mul<VAXint:isfx>2 %1,%0 965 mul<VAXint:isfx>3 %1,%2,%0") 966 967(define_insn_and_split "mulsidi3" 968 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 969 (mult:DI 970 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 971 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))))] 972 "" 973 "#" 974 "reload_completed" 975 [(parallel 976 [(set (match_dup 0) 977 (mult:DI 978 (sign_extend:DI (match_dup 1)) 979 (sign_extend:DI (match_dup 2)))) 980 (clobber (reg:CC VAX_PSL_REGNUM))])] 981 "") 982 983(define_insn "*mulsidi3<ccn><ccnz><ccz>" 984 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 985 (mult:DI 986 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 987 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))) 988 (clobber (reg:CC VAX_PSL_REGNUM))] 989 "reload_completed" 990 "emul %1,%2,$0,%0") 991 992(define_insn_and_split "*maddsidi4" 993 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 994 (plus:DI 995 (mult:DI 996 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 997 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))) 998 (sign_extend:DI (match_operand:SI 3 "general_operand" "g"))))] 999 "" 1000 "#" 1001 "reload_completed" 1002 [(parallel 1003 [(set (match_dup 0) 1004 (plus:DI 1005 (mult:DI 1006 (sign_extend:DI (match_dup 1)) 1007 (sign_extend:DI (match_dup 2))) 1008 (sign_extend:DI (match_dup 3)))) 1009 (clobber (reg:CC VAX_PSL_REGNUM))])] 1010 "") 1011 1012(define_insn "*maddsidi4_2<ccn><ccnz><ccz>" 1013 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1014 (plus:DI 1015 (mult:DI 1016 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 1017 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))) 1018 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g")))) 1019 (clobber (reg:CC VAX_PSL_REGNUM))] 1020 "reload_completed" 1021 "emul %1,%2,%3,%0") 1022 1023;; 'F' constraint means type CONST_DOUBLE 1024(define_insn_and_split "*maddsidi4_const" 1025 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1026 (plus:DI 1027 (mult:DI 1028 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 1029 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))) 1030 (match_operand:DI 3 "immediate_operand" "F")))] 1031 "GET_CODE (operands[3]) == CONST_DOUBLE 1032 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)" 1033 "#" 1034 "&& reload_completed" 1035 [(parallel 1036 [(set (match_dup 0) 1037 (plus:DI 1038 (mult:DI 1039 (sign_extend:DI (match_dup 1)) 1040 (sign_extend:DI (match_dup 2))) 1041 (match_dup 3))) 1042 (clobber (reg:CC VAX_PSL_REGNUM))])] 1043 "") 1044 1045(define_insn "*maddsidi4_const_2<ccn><ccnz><ccz>" 1046 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1047 (plus:DI 1048 (mult:DI 1049 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 1050 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))) 1051 (match_operand:DI 3 "immediate_operand" "F"))) 1052 (clobber (reg:CC VAX_PSL_REGNUM))] 1053 "GET_CODE (operands[3]) == CONST_DOUBLE 1054 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31) 1055 && reload_completed" 1056 "* 1057{ 1058 if (CONST_DOUBLE_HIGH (operands[3])) 1059 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3])); 1060 return \"emul %1,%2,%3,%0\"; 1061}") 1062 1063;;- Divide instructions. 1064 1065(define_insn_and_split "div<mode>3" 1066 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 1067 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF") 1068 (match_operand:VAXfp 2 "general_operand" "gF,gF")))] 1069 "" 1070 "#" 1071 "reload_completed" 1072 [(parallel 1073 [(set (match_dup 0) 1074 (div:VAXfp (match_dup 1) 1075 (match_dup 2))) 1076 (clobber (reg:CC VAX_PSL_REGNUM))])] 1077 "") 1078 1079(define_insn "*div<mode>3<fccn><fccnz><fccz>" 1080 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 1081 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF") 1082 (match_operand:VAXfp 2 "general_operand" "gF,gF"))) 1083 (clobber (reg:CC VAX_PSL_REGNUM))] 1084 "reload_completed" 1085 "@ 1086 div<VAXfp:fsfx>2 %2,%0 1087 div<VAXfp:fsfx>3 %2,%1,%0") 1088 1089(define_insn_and_split "div<mode>3" 1090 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1091 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 1092 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))] 1093 "" 1094 "#" 1095 "reload_completed" 1096 [(parallel 1097 [(set (match_dup 0) 1098 (div:VAXint (match_dup 1) 1099 (match_dup 2))) 1100 (clobber (reg:CC VAX_PSL_REGNUM))])] 1101 "") 1102 1103(define_insn "*div<mode>3<ccn><ccnz><ccz>" 1104 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1105 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 1106 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT"))) 1107 (clobber (reg:CC VAX_PSL_REGNUM))] 1108 "reload_completed" 1109 "@ 1110 div<VAXint:isfx>2 %2,%0 1111 div<VAXint:isfx>3 %2,%1,%0") 1112 1113;; This is left out because it is very slow; 1114;; we are better off programming around the "lack" of this insn. 1115;;(define_insn_and_split "divmoddisi4" 1116;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1117;; (div:SI (match_operand:DI 1 "general_operand" "g") 1118;; (match_operand:SI 2 "general_operand" "g"))) 1119;; (set (match_operand:SI 3 "nonimmediate_operand" "=g") 1120;; (mod:SI (match_dup 1) 1121;; (match_dup 2)))] 1122;; "" 1123;; "#" 1124;; "reload_completed" 1125;; [(parallel 1126;; [(set (match_dup 0) 1127;; (div:SI (match_dup 1) 1128;; (match_dup 2))) 1129;; (set (match_dup 3) 1130;; (mod:SI (match_dup 1) 1131;; (match_dup 2))) 1132;; (clobber (reg:CC VAX_PSL_REGNUM))])] 1133;; "") 1134;; 1135;;(define_insn "*divmoddisi4<ccn><ccnz><ccz>" 1136;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1137;; (div:SI (match_operand:DI 1 "general_operand" "g") 1138;; (match_operand:SI 2 "general_operand" "g"))) 1139;; (set (match_operand:SI 3 "nonimmediate_operand" "=g") 1140;; (mod:SI (match_dup 1) 1141;; (match_dup 2))) 1142;; (clobber (reg:CC VAX_PSL_REGNUM))] 1143;; "reload_completed" 1144;; "ediv %2,%1,%0,%3") 1145 1146;; Bit-and on the VAX is done with a clear-bits insn. 1147(define_expand "and<mode>3" 1148 [(set (match_operand:VAXint 0 "nonimmediate_operand" "") 1149 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "")) 1150 (match_operand:VAXint 2 "general_operand" "")))] 1151 "" 1152 " 1153{ 1154 rtx op1 = operands[1]; 1155 1156 /* If there is a constant argument, complement that one. */ 1157 if (CONST_INT_P (operands[2]) && ! CONST_INT_P (op1)) 1158 { 1159 operands[1] = operands[2]; 1160 operands[2] = op1; 1161 op1 = operands[1]; 1162 } 1163 1164 if (CONST_INT_P (op1)) 1165 operands[1] = GEN_INT (~INTVAL (op1)); 1166 else 1167 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1); 1168}") 1169 1170(define_insn_and_split "*and<mode>3" 1171 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1172 (and:VAXint (not:VAXint 1173 (match_operand:VAXint 1 "general_operand" "nrmT,nrmT")) 1174 (match_operand:VAXint 2 "general_operand" "0,nrmT")))] 1175 "" 1176 "#" 1177 "reload_completed" 1178 [(parallel 1179 [(set (match_dup 0) 1180 (and:VAXint (not:VAXint 1181 (match_dup 1)) 1182 (match_dup 2))) 1183 (clobber (reg:CC VAX_PSL_REGNUM))])] 1184 "") 1185 1186(define_insn "*and<mode>3_2<ccn><ccnz><ccz>" 1187 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1188 (and:VAXint (not:VAXint 1189 (match_operand:VAXint 1 "general_operand" "nrmT,nrmT")) 1190 (match_operand:VAXint 2 "general_operand" "0,nrmT"))) 1191 (clobber (reg:CC VAX_PSL_REGNUM))] 1192 "reload_completed" 1193 "@ 1194 bic<VAXint:isfx>2 %1,%0 1195 bic<VAXint:isfx>3 %1,%2,%0") 1196 1197;; The following used to be needed because constant propagation can 1198;; create them starting from the bic insn patterns above. This is no 1199;; longer a problem. However, having these patterns allows optimization 1200;; opportunities in combine.c. 1201 1202(define_insn_and_split "*and<mode>3_const_int" 1203 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1204 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 1205 (match_operand:VAXint 2 "const_int_operand" "n,n")))] 1206 "" 1207 "#" 1208 "reload_completed" 1209 [(parallel 1210 [(set (match_dup 0) 1211 (and:VAXint (match_dup 1) 1212 (match_dup 2))) 1213 (clobber (reg:CC VAX_PSL_REGNUM))])] 1214 "") 1215 1216(define_insn "*and<mode>3_2_const_int<ccn><ccnz><ccz>" 1217 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1218 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 1219 (match_operand:VAXint 2 "const_int_operand" "n,n"))) 1220 (clobber (reg:CC VAX_PSL_REGNUM))] 1221 "reload_completed" 1222 "@ 1223 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0 1224 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0") 1225 1226;; We have no direct AND operation and consequently the RTL sequence 1227;; the "and<mode>3" pattern produces does not match the instruction 1228;; the "*bit<mode>" pattern does for the purpose of the compare 1229;; elimination pass. Try to get rid of the extra operation by hand 1230;; and where the sequence is used to set the condition codes only 1231;; convert MCOM/BIC => BIT. 1232(define_peephole2 1233 [(parallel 1234 [(set (match_operand:VAXint 0 "register_operand") 1235 (not:VAXint (match_operand:VAXint 1 "general_operand"))) 1236 (clobber (reg:CC VAX_PSL_REGNUM))]) 1237 (parallel 1238 [(set (reg:VAXccnz VAX_PSL_REGNUM) 1239 (compare:VAXccnz 1240 (and:VAXint (not:VAXint (match_dup 0)) 1241 (match_operand:VAXint 3 "general_operand")) 1242 (const_int 0))) 1243 (set (match_operand:VAXint 2 "register_operand") 1244 (and:VAXint (not:VAXint (match_dup 0)) 1245 (match_dup 3)))])] 1246 "peep2_reg_dead_p (2, operands[0]) && peep2_reg_dead_p (2, operands[2])" 1247 [(set (reg:VAXccnz VAX_PSL_REGNUM) 1248 (compare:VAXccnz 1249 (and:VAXint (match_dup 1) 1250 (match_dup 3)) 1251 (const_int 0)))] 1252 "") 1253 1254;;- Bit set instructions. 1255 1256(define_insn_and_split "ior<mode>3" 1257 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 1258 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 1259 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))] 1260 "" 1261 "#" 1262 "reload_completed" 1263 [(parallel 1264 [(set (match_dup 0) 1265 (ior:VAXint (match_dup 1) 1266 (match_dup 2))) 1267 (clobber (reg:CC VAX_PSL_REGNUM))])] 1268 "") 1269 1270(define_insn "*ior<mode>3<ccn><ccnz><ccz>" 1271 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 1272 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 1273 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT"))) 1274 (clobber (reg:CC VAX_PSL_REGNUM))] 1275 "reload_completed" 1276 "@ 1277 bis<VAXint:isfx>2 %2,%0 1278 bis<VAXint:isfx>2 %1,%0 1279 bis<VAXint:isfx>3 %2,%1,%0") 1280 1281;;- xor instructions. 1282 1283(define_insn_and_split "xor<mode>3" 1284 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 1285 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 1286 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))] 1287 "" 1288 "#" 1289 "reload_completed" 1290 [(parallel 1291 [(set (match_dup 0) 1292 (xor:VAXint (match_dup 1) 1293 (match_dup 2))) 1294 (clobber (reg:CC VAX_PSL_REGNUM))])] 1295 "") 1296 1297(define_insn "*xor<mode>3<ccn><ccnz><ccz>" 1298 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 1299 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 1300 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT"))) 1301 (clobber (reg:CC VAX_PSL_REGNUM))] 1302 "reload_completed" 1303 "@ 1304 xor<VAXint:isfx>2 %2,%0 1305 xor<VAXint:isfx>2 %1,%0 1306 xor<VAXint:isfx>3 %2,%1,%0") 1307 1308(define_insn_and_split "neg<mode>2" 1309 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g") 1310 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))] 1311 "" 1312 "#" 1313 "reload_completed" 1314 [(parallel 1315 [(set (match_dup 0) 1316 (neg:VAXfp (match_dup 1))) 1317 (clobber (reg:CC VAX_PSL_REGNUM))])] 1318 "") 1319 1320(define_insn "*neg<mode>2<fccn><fccnz><fccz>" 1321 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g") 1322 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF"))) 1323 (clobber (reg:CC VAX_PSL_REGNUM))] 1324 "reload_completed" 1325 "mneg<VAXfp:fsfx> %1,%0") 1326 1327(define_insn_and_split "neg<mode>2" 1328 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 1329 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))] 1330 "" 1331 "#" 1332 "reload_completed" 1333 [(parallel 1334 [(set (match_dup 0) 1335 (neg:VAXint (match_dup 1))) 1336 (clobber (reg:CC VAX_PSL_REGNUM))])] 1337 "") 1338 1339(define_insn "*neg<mode>2<ccn><ccnz><ccz>" 1340 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 1341 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT"))) 1342 (clobber (reg:CC VAX_PSL_REGNUM))] 1343 "reload_completed" 1344 "mneg<VAXint:isfx> %1,%0") 1345 1346(define_insn "*neg<mode>2_cc" 1347 [(set (reg:CC VAX_PSL_REGNUM) 1348 (compare:CC (const_int 0) 1349 (neg:VAXint 1350 (match_operand:VAXint 1 "general_operand" "0,nrmT")))) 1351 (set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1352 (neg:VAXint (match_dup 1)))] 1353 "reload_completed" 1354 "mneg<VAXint:isfx> %1,%0") 1355 1356(define_insn_and_split "one_cmpl<mode>2" 1357 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 1358 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))] 1359 "" 1360 "#" 1361 "reload_completed" 1362 [(parallel 1363 [(set (match_dup 0) 1364 (not:VAXint (match_dup 1))) 1365 (clobber (reg:CC VAX_PSL_REGNUM))])] 1366 "") 1367 1368(define_insn "*one_cmpl<mode>2<ccn><ccnz><ccz>" 1369 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 1370 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT"))) 1371 (clobber (reg:CC VAX_PSL_REGNUM))] 1372 "reload_completed" 1373 "mcom<VAXint:isfx> %1,%0") 1374 1375;; Arithmetic right shift on the VAX works by negating the shift count, 1376;; then emitting a right shift with the shift count negated. This means 1377;; that all actual shift counts in the RTL will be positive. This 1378;; prevents converting shifts to ZERO_EXTRACTs with negative positions, 1379;; which isn't valid. 1380(define_expand "ashrsi3" 1381 [(set (match_operand:SI 0 "general_operand" "=g") 1382 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 1383 (match_operand:QI 2 "general_operand" "g")))] 1384 "" 1385 " 1386{ 1387 if (! CONST_INT_P(operands[2])) 1388 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 1389}") 1390 1391(define_insn_and_split "*ashlnegsi3_const_int" 1392 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1393 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 1394 (match_operand:QI 2 "const_int_operand" "n")))] 1395 "" 1396 "#" 1397 "reload_completed" 1398 [(parallel 1399 [(set (match_dup 0) 1400 (ashiftrt:SI (match_dup 1) 1401 (match_dup 2))) 1402 (clobber (reg:CC VAX_PSL_REGNUM))])] 1403 "") 1404 1405(define_insn "*ashlnegsi3_const_int_2<ccn><ccnz><ccz>" 1406 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1407 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 1408 (match_operand:QI 2 "const_int_operand" "n"))) 1409 (clobber (reg:CC VAX_PSL_REGNUM))] 1410 "reload_completed" 1411 "ashl $%n2,%1,%0") 1412 1413(define_insn_and_split "*ashlnegsi3" 1414 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1415 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 1416 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 1417 "" 1418 "#" 1419 "reload_completed" 1420 [(parallel 1421 [(set (match_dup 0) 1422 (ashiftrt:SI (match_dup 1) 1423 (neg:QI (match_dup 2)))) 1424 (clobber (reg:CC VAX_PSL_REGNUM))])] 1425 "") 1426 1427(define_insn "*ashlnegsi3_2<ccn><ccnz><ccz>" 1428 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1429 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 1430 (neg:QI (match_operand:QI 2 "general_operand" "g")))) 1431 (clobber (reg:CC VAX_PSL_REGNUM))] 1432 "reload_completed" 1433 "ashl %2,%1,%0") 1434 1435(define_insn_and_split "ashlsi3" 1436 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1437 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT") 1438 (match_operand:QI 2 "general_operand" "g")))] 1439 "" 1440 "#" 1441 "reload_completed" 1442 [(parallel 1443 [(set (match_dup 0) 1444 (ashift:SI (match_dup 1) 1445 (match_dup 2))) 1446 (clobber (reg:CC VAX_PSL_REGNUM))])] 1447 "") 1448 1449(define_insn "*ashlsi3<ccn><ccnz><ccz>" 1450 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1451 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT") 1452 (match_operand:QI 2 "general_operand" "g"))) 1453 (clobber (reg:CC VAX_PSL_REGNUM))] 1454 "reload_completed" 1455 "* 1456{ 1457 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1])) 1458 return \"addl2 %0,%0\"; 1459 if (REG_P (operands[1]) && CONST_INT_P (operands[2])) 1460 { 1461 int i = INTVAL (operands[2]); 1462 if (i == 1) 1463 return \"addl3 %1,%1,%0\"; 1464 if (i == 2 && !optimize_size) 1465 { 1466 if (push_operand (operands[0], SImode)) 1467 return \"pushal 0[%1]\"; 1468 return \"moval 0[%1],%0\"; 1469 } 1470 if (i == 3 && !optimize_size) 1471 { 1472 if (push_operand (operands[0], SImode)) 1473 return \"pushaq 0[%1]\"; 1474 return \"movaq 0[%1],%0\"; 1475 } 1476 } 1477 return \"ashl %2,%1,%0\"; 1478}") 1479 1480;; Arithmetic right shift on the VAX works by negating the shift count. 1481(define_expand "ashrdi3" 1482 [(set (match_operand:DI 0 "general_operand" "=g") 1483 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g") 1484 (match_operand:QI 2 "general_operand" "g")))] 1485 "" 1486 " 1487{ 1488 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 1489}") 1490 1491(define_insn_and_split "ashldi3" 1492 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1493 (ashift:DI (match_operand:DI 1 "general_operand" "g") 1494 (match_operand:QI 2 "general_operand" "g")))] 1495 "" 1496 "#" 1497 "reload_completed" 1498 [(parallel 1499 [(set (match_dup 0) 1500 (ashift:DI (match_dup 1) 1501 (match_dup 2))) 1502 (clobber (reg:CC VAX_PSL_REGNUM))])] 1503 "") 1504 1505(define_insn "*ashldi3<ccn><ccnz><ccz>" 1506 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1507 (ashift:DI (match_operand:DI 1 "general_operand" "g") 1508 (match_operand:QI 2 "general_operand" "g"))) 1509 (clobber (reg:CC VAX_PSL_REGNUM))] 1510 "reload_completed" 1511 "ashq %2,%D1,%0") 1512 1513(define_insn_and_split "*ashlnegdi3" 1514 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1515 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g") 1516 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 1517 "" 1518 "#" 1519 "reload_completed" 1520 [(parallel 1521 [(set (match_dup 0) 1522 (ashiftrt:DI (match_dup 1) 1523 (neg:QI (match_dup 2)))) 1524 (clobber (reg:CC VAX_PSL_REGNUM))])] 1525 "") 1526 1527(define_insn "*ashlnegdi3_2<ccn><ccnz><ccz>" 1528 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1529 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g") 1530 (neg:QI (match_operand:QI 2 "general_operand" "g")))) 1531 (clobber (reg:CC VAX_PSL_REGNUM))] 1532 "reload_completed" 1533 "ashq %2,%D1,%0") 1534 1535;; We used to have expand_shift handle logical right shifts by using extzv, 1536;; but this make it very difficult to do lshrdi3. Since the VAX is the 1537;; only machine with this kludge, it's better to just do this with a 1538;; define_expand and remove that case from expand_shift. 1539 1540(define_expand "lshrsi3" 1541 [(set (match_dup 3) 1542 (minus:QI (const_int 32) 1543 (match_dup 4))) 1544 (set (match_operand:SI 0 "nonimmediate_operand" "=g") 1545 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 1546 (match_dup 3) 1547 (match_operand:SI 2 "register_operand" "g")))] 1548 "" 1549 " 1550{ 1551 operands[3] = gen_reg_rtx (QImode); 1552 operands[4] = gen_lowpart (QImode, operands[2]); 1553}") 1554 1555;; Rotate right on the VAX works by negating the shift count. 1556(define_expand "rotrsi3" 1557 [(set (match_operand:SI 0 "general_operand" "=g") 1558 (rotatert:SI (match_operand:SI 1 "general_operand" "g") 1559 (match_operand:QI 2 "general_operand" "g")))] 1560 "" 1561 " 1562{ 1563 if (! CONST_INT_P (operands[2])) 1564 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 1565}") 1566 1567(define_insn_and_split "rotlsi3" 1568 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1569 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT") 1570 (match_operand:QI 2 "general_operand" "g")))] 1571 "" 1572 "#" 1573 "reload_completed" 1574 [(parallel 1575 [(set (match_dup 0) 1576 (rotate:SI (match_dup 1) 1577 (match_dup 2))) 1578 (clobber (reg:CC VAX_PSL_REGNUM))])] 1579 "") 1580 1581(define_insn "*rotlsi3<ccn><ccnz><ccz>" 1582 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1583 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT") 1584 (match_operand:QI 2 "general_operand" "g"))) 1585 (clobber (reg:CC VAX_PSL_REGNUM))] 1586 "reload_completed" 1587 "rotl %2,%1,%0") 1588 1589(define_insn_and_split "*rotrsi3_const_int" 1590 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1591 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT") 1592 (match_operand:QI 2 "const_int_operand" "n")))] 1593 "" 1594 "#" 1595 "reload_completed" 1596 [(parallel 1597 [(set (match_dup 0) 1598 (rotatert:SI (match_dup 1) 1599 (match_dup 2))) 1600 (clobber (reg:CC VAX_PSL_REGNUM))])] 1601 "") 1602 1603(define_insn "*rotrsi3_const_int_2<ccn><ccnz><ccz>" 1604 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1605 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT") 1606 (match_operand:QI 2 "const_int_operand" "n"))) 1607 (clobber (reg:CC VAX_PSL_REGNUM))] 1608 "reload_completed" 1609 "rotl %R2,%1,%0") 1610 1611(define_insn_and_split "*rotrnegsi3" 1612 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1613 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT") 1614 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 1615 "" 1616 "#" 1617 "reload_completed" 1618 [(parallel 1619 [(set (match_dup 0) 1620 (rotatert:SI (match_dup 1) 1621 (neg:QI (match_dup 2)))) 1622 (clobber (reg:CC VAX_PSL_REGNUM))])] 1623 "") 1624 1625(define_insn "*rotrnegsi3_2<ccn><ccnz><ccz>" 1626 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1627 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT") 1628 (neg:QI (match_operand:QI 2 "general_operand" "g")))) 1629 (clobber (reg:CC VAX_PSL_REGNUM))] 1630 "reload_completed" 1631 "rotl %2,%1,%0") 1632 1633;; This insn is probably slower than a multiply and an add. 1634;;(define_insn_and_split "*amulsi4" 1635;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1636;; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g") 1637;; (match_operand:SI 2 "general_operand" "g")) 1638;; (match_operand:SI 3 "general_operand" "g")))] 1639;; "" 1640;; "#" 1641;; "reload_completed" 1642;; [(parallel 1643;; [(set (match_dup 0) 1644;; (mult:SI (plus:SI (match_dup 1) 1645;; (match_dup 2)) 1646;; (match_dup 3))) 1647;; (clobber (reg:CC VAX_PSL_REGNUM))])] 1648;; "") 1649;; 1650;;(define_insn "*amulsi4_2<ccn><ccnz><ccz>" 1651;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1652;; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g") 1653;; (match_operand:SI 2 "general_operand" "g")) 1654;; (match_operand:SI 3 "general_operand" "g"))) 1655;; (clobber (reg:CC VAX_PSL_REGNUM))] 1656;; "reload_completed" 1657;; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0") 1658 1659;; Special cases of bit-field insns which we should 1660;; recognize in preference to the general case. 1661;; These handle aligned 8-bit and 16-bit fields 1662;; that can be done with move or convert instructions. 1663 1664(define_insn_and_split "*insv_aligned" 1665 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro") 1666 (match_operand:QI 1 "const_int_operand" "n") 1667 (match_operand:SI 2 "const_int_operand" "n")) 1668 (match_operand:SI 3 "general_operand" "g"))] 1669 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 1670 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 1671 && (!MEM_P (operands[0]) 1672 || ((!flag_pic 1673 || vax_acceptable_pic_operand_p (XEXP (operands[0], 0), 1674 true, true)) 1675 && !mode_dependent_address_p (XEXP (operands[0], 0), 1676 MEM_ADDR_SPACE (operands[0])))) 1677 && (!(REG_P (operands[0]) 1678 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0])))) 1679 || INTVAL (operands[2]) == 0)" 1680 "#" 1681 "&& reload_completed" 1682 [(parallel 1683 [(set (zero_extract:SI (match_dup 0) 1684 (match_dup 1) 1685 (match_dup 2)) 1686 (match_dup 3)) 1687 (clobber (reg:CC VAX_PSL_REGNUM))])] 1688 "") 1689 1690(define_insn "*insv_aligned_2<ccn><ccnz><ccz>" 1691 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro") 1692 (match_operand:QI 1 "const_int_operand" "n") 1693 (match_operand:SI 2 "const_int_operand" "n")) 1694 (match_operand:SI 3 "general_operand" "g")) 1695 (clobber (reg:CC VAX_PSL_REGNUM))] 1696 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 1697 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 1698 && (!MEM_P (operands[0]) 1699 || ((!flag_pic 1700 || vax_acceptable_pic_operand_p (XEXP (operands[0], 0), 1701 true, true)) 1702 && !mode_dependent_address_p (XEXP (operands[0], 0), 1703 MEM_ADDR_SPACE (operands[0])))) 1704 && (!(REG_P (operands[0]) 1705 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0])))) 1706 || INTVAL (operands[2]) == 0) 1707 && reload_completed" 1708 "* 1709{ 1710 if (!REG_P (operands[0])) 1711 operands[0] 1712 = adjust_address (operands[0], 1713 INTVAL (operands[1]) == 8 ? QImode : HImode, 1714 INTVAL (operands[2]) / 8); 1715 else 1716 gcc_assert (INTVAL (operands[2]) == 0); 1717 1718 if (INTVAL (operands[1]) == 8) 1719 return \"movb %3,%0\"; 1720 return \"movw %3,%0\"; 1721}") 1722 1723(define_insn_and_split "*extzv_aligned" 1724 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g") 1725 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1726 (match_operand:QI 2 "const_int_operand" "n") 1727 (match_operand:SI 3 "const_int_operand" "n")))] 1728 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1729 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 1730 && (!MEM_P (operands[1]) 1731 || ((!flag_pic 1732 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0), 1733 true, true)) 1734 && !mode_dependent_address_p (XEXP (operands[1], 0), 1735 MEM_ADDR_SPACE (operands[1])))) 1736 && (!(REG_P (operands[1]) 1737 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))) 1738 || INTVAL (operands[3]) == 0)" 1739 "#" 1740 "&& reload_completed" 1741 [(parallel 1742 [(set (match_dup 0) 1743 (zero_extract:SI (match_dup 1) 1744 (match_dup 2) 1745 (match_dup 3))) 1746 (clobber (reg:CC VAX_PSL_REGNUM))])] 1747 "") 1748 1749(define_insn "*extzv_aligned_2<ccn><ccnz><ccz>" 1750 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g") 1751 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1752 (match_operand:QI 2 "const_int_operand" "n") 1753 (match_operand:SI 3 "const_int_operand" "n"))) 1754 (clobber (reg:CC VAX_PSL_REGNUM))] 1755 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1756 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 1757 && (!MEM_P (operands[1]) 1758 || ((!flag_pic 1759 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0), 1760 true, true)) 1761 && !mode_dependent_address_p (XEXP (operands[1], 0), 1762 MEM_ADDR_SPACE (operands[1])))) 1763 && (!(REG_P (operands[1]) 1764 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))) 1765 || INTVAL (operands[3]) == 0) 1766 && reload_completed" 1767 "* 1768{ 1769 if (!REG_P (operands[1])) 1770 operands[1] 1771 = adjust_address (operands[1], 1772 INTVAL (operands[2]) == 8 ? QImode : HImode, 1773 INTVAL (operands[3]) / 8); 1774 else 1775 gcc_assert (INTVAL (operands[3]) == 0); 1776 1777 if (INTVAL (operands[2]) == 8) 1778 return \"movzbl %1,%0\"; 1779 return \"movzwl %1,%0\"; 1780}") 1781 1782(define_insn_and_split "*extv_aligned" 1783 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1784 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1785 (match_operand:QI 2 "const_int_operand" "n") 1786 (match_operand:SI 3 "const_int_operand" "n")))] 1787 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1788 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 1789 && (!MEM_P (operands[1]) 1790 || ((!flag_pic 1791 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0), 1792 true, true)) 1793 && !mode_dependent_address_p (XEXP (operands[1], 0), 1794 MEM_ADDR_SPACE (operands[1])))) 1795 && (!(REG_P (operands[1]) 1796 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))) 1797 || INTVAL (operands[3]) == 0)" 1798 "#" 1799 "&& reload_completed" 1800 [(parallel 1801 [(set (match_dup 0) 1802 (sign_extract:SI (match_dup 1) 1803 (match_dup 2) 1804 (match_dup 3))) 1805 (clobber (reg:CC VAX_PSL_REGNUM))])] 1806 "") 1807 1808(define_insn "*extv_aligned_2<ccn><ccnz><ccz>" 1809 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1810 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1811 (match_operand:QI 2 "const_int_operand" "n") 1812 (match_operand:SI 3 "const_int_operand" "n"))) 1813 (clobber (reg:CC VAX_PSL_REGNUM))] 1814 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1815 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 1816 && (!MEM_P (operands[1]) 1817 || ((!flag_pic 1818 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0), 1819 true, true)) 1820 && !mode_dependent_address_p (XEXP (operands[1], 0), 1821 MEM_ADDR_SPACE (operands[1])))) 1822 && (!(REG_P (operands[1]) 1823 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))) 1824 || INTVAL (operands[3]) == 0) 1825 && reload_completed" 1826 "* 1827{ 1828 if (!REG_P (operands[1])) 1829 operands[1] 1830 = adjust_address (operands[1], 1831 INTVAL (operands[2]) == 8 ? QImode : HImode, 1832 INTVAL (operands[3]) / 8); 1833 else 1834 gcc_assert (INTVAL (operands[3]) == 0); 1835 1836 if (INTVAL (operands[2]) == 8) 1837 return \"cvtbl %1,%0\"; 1838 return \"cvtwl %1,%0\"; 1839}") 1840 1841;; Register and non-offsettable-memory SImode cases of bit-field insns. 1842 1843(define_insn "*cmpv_<mode>" 1844 [(set (reg:VAXcc VAX_PSL_REGNUM) 1845 (compare:VAXcc 1846 (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro") 1847 (match_operand:QI 1 "general_operand" "g") 1848 (match_operand:SI 2 "general_operand" "nrmT")) 1849 (match_operand:SI 3 "general_operand" "nrmT")))] 1850 "reload_completed" 1851 "cmpv %2,%1,%0,%3") 1852 1853(define_insn "*cmpzv_<mode>" 1854 [(set (reg:VAXcc VAX_PSL_REGNUM) 1855 (compare:VAXcc 1856 (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro") 1857 (match_operand:QI 1 "general_operand" "g") 1858 (match_operand:SI 2 "general_operand" "nrmT")) 1859 (match_operand:SI 3 "general_operand" "nrmT")))] 1860 "reload_completed" 1861 "cmpzv %2,%1,%0,%3") 1862 1863;; When the field position and size are constant and the destination 1864;; is a register, extv and extzv are much slower than a rotate followed 1865;; by a bicl or sign extension. Because we might end up choosing ext[z]v 1866;; anyway, we can't allow immediate values for the primary source operand. 1867 1868(define_insn_and_split "*extv_non_const" 1869 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1870 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1871 (match_operand:QI 2 "general_operand" "g") 1872 (match_operand:SI 3 "general_operand" "nrmT")))] 1873 "" 1874 "#" 1875 "reload_completed" 1876 [(parallel 1877 [(set (match_dup 0) 1878 (sign_extract:SI (match_dup 1) 1879 (match_dup 2) 1880 (match_dup 3))) 1881 (clobber (reg:CC VAX_PSL_REGNUM))])] 1882 "") 1883 1884(define_insn "*extv_non_const_2<ccn><ccnz><ccz>" 1885 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1886 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1887 (match_operand:QI 2 "general_operand" "g") 1888 (match_operand:SI 3 "general_operand" "nrmT"))) 1889 (clobber (reg:CC VAX_PSL_REGNUM))] 1890 "reload_completed" 1891 "* 1892{ 1893 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2]) 1894 || ! REG_P (operands[0]) 1895 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)) 1896 return \"extv %3,%2,%1,%0\"; 1897 if (INTVAL (operands[2]) == 8) 1898 return \"rotl %R3,%1,%0\;cvtbl %0,%0\"; 1899 return \"rotl %R3,%1,%0\;cvtwl %0,%0\"; 1900}") 1901 1902(define_insn_and_split "*extzv_non_const" 1903 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1904 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1905 (match_operand:QI 2 "general_operand" "g") 1906 (match_operand:SI 3 "general_operand" "nrmT")))] 1907 "" 1908 "#" 1909 "reload_completed" 1910 [(parallel 1911 [(set (match_dup 0) 1912 (zero_extract:SI (match_dup 1) 1913 (match_dup 2) 1914 (match_dup 3))) 1915 (clobber (reg:CC VAX_PSL_REGNUM))])] 1916 "") 1917 1918(define_insn "*extzv_non_const_2<ccn><ccnz><ccz>" 1919 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1920 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1921 (match_operand:QI 2 "general_operand" "g") 1922 (match_operand:SI 3 "general_operand" "nrmT"))) 1923 (clobber (reg:CC VAX_PSL_REGNUM))] 1924 "reload_completed" 1925 "* 1926{ 1927 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2]) 1928 || ! REG_P (operands[0])) 1929 return \"extzv %3,%2,%1,%0\"; 1930 if (INTVAL (operands[2]) == 8) 1931 return \"rotl %R3,%1,%0\;movzbl %0,%0\"; 1932 if (INTVAL (operands[2]) == 16) 1933 return \"rotl %R3,%1,%0\;movzwl %0,%0\"; 1934 if (INTVAL (operands[3]) & 31) 1935 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\"; 1936 if (rtx_equal_p (operands[0], operands[1])) 1937 return \"bicl2 %M2,%0\"; 1938 return \"bicl3 %M2,%1,%0\"; 1939}") 1940 1941;; Non-register cases. 1942;; nonimmediate_operand is used to make sure that mode-ambiguous cases 1943;; don't match these (and therefore match the cases above instead). 1944 1945(define_insn "*cmpv_2_<mode>" 1946 [(set (reg:VAXcc VAX_PSL_REGNUM) 1947 (compare:VAXcc 1948 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m") 1949 (match_operand:QI 1 "general_operand" "g") 1950 (match_operand:SI 2 "general_operand" "nrmT")) 1951 (match_operand:SI 3 "general_operand" "nrmT")))] 1952 "reload_completed" 1953 "cmpv %2,%1,%0,%3") 1954 1955(define_insn "*cmpzv_2_<mode>" 1956 [(set (reg:VAXcc VAX_PSL_REGNUM) 1957 (compare:VAXcc 1958 (zero_extract:SI (match_operand:QI 0 "memory_operand" "m") 1959 (match_operand:QI 1 "general_operand" "g") 1960 (match_operand:SI 2 "general_operand" "nrmT")) 1961 (match_operand:SI 3 "general_operand" "nrmT")))] 1962 "reload_completed" 1963 "cmpzv %2,%1,%0,%3") 1964 1965(define_expand "extv" 1966 [(set (match_operand:SI 0 "general_operand" "") 1967 (sign_extract:SI (match_operand:SI 1 "general_operand" "") 1968 (match_operand:QI 2 "general_operand" "") 1969 (match_operand:SI 3 "general_operand" "")))] 1970 "" 1971 "") 1972 1973(define_insn_and_split "*extv" 1974 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1975 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") 1976 (match_operand:QI 2 "general_operand" "g") 1977 (match_operand:SI 3 "general_operand" "nrmT")))] 1978 "" 1979 "#" 1980 "reload_completed" 1981 [(parallel 1982 [(set (match_dup 0) 1983 (sign_extract:SI (match_dup 1) 1984 (match_dup 2) 1985 (match_dup 3))) 1986 (clobber (reg:CC VAX_PSL_REGNUM))])] 1987 "") 1988 1989(define_insn "*extv_2<ccn><ccnz><ccz>" 1990 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1991 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") 1992 (match_operand:QI 2 "general_operand" "g") 1993 (match_operand:SI 3 "general_operand" "nrmT"))) 1994 (clobber (reg:CC VAX_PSL_REGNUM))] 1995 "reload_completed" 1996 "* 1997{ 1998 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2]) 1999 || !CONST_INT_P (operands[3]) 2000 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16) 2001 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32 2002 || side_effects_p (operands[1]) 2003 || (MEM_P (operands[1]) 2004 && mode_dependent_address_p (XEXP (operands[1], 0), 2005 MEM_ADDR_SPACE (operands[1])))) 2006 return \"extv %3,%2,%1,%0\"; 2007 if (INTVAL (operands[2]) == 8) 2008 return \"rotl %R3,%1,%0\;cvtbl %0,%0\"; 2009 return \"rotl %R3,%1,%0\;cvtwl %0,%0\"; 2010}") 2011 2012(define_expand "extzv" 2013 [(set (match_operand:SI 0 "general_operand" "") 2014 (zero_extract:SI (match_operand:SI 1 "general_operand" "") 2015 (match_operand:QI 2 "general_operand" "") 2016 (match_operand:SI 3 "general_operand" "")))] 2017 "" 2018 "") 2019 2020(define_insn_and_split "*extzv" 2021 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2022 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") 2023 (match_operand:QI 2 "general_operand" "g") 2024 (match_operand:SI 3 "general_operand" "nrmT")))] 2025 "" 2026 "#" 2027 "reload_completed" 2028 [(parallel 2029 [(set (match_dup 0) 2030 (zero_extract:SI (match_dup 1) 2031 (match_dup 2) 2032 (match_dup 3))) 2033 (clobber (reg:CC VAX_PSL_REGNUM))])] 2034 "") 2035 2036(define_insn "*extzv_2<ccn><ccnz><ccz>" 2037 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2038 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") 2039 (match_operand:QI 2 "general_operand" "g") 2040 (match_operand:SI 3 "general_operand" "nrmT"))) 2041 (clobber (reg:CC VAX_PSL_REGNUM))] 2042 "reload_completed" 2043 "* 2044{ 2045 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2]) 2046 || !CONST_INT_P (operands[3]) 2047 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32 2048 || side_effects_p (operands[1]) 2049 || (MEM_P (operands[1]) 2050 && mode_dependent_address_p (XEXP (operands[1], 0), 2051 MEM_ADDR_SPACE (operands[1])))) 2052 return \"extzv %3,%2,%1,%0\"; 2053 if (INTVAL (operands[2]) == 8) 2054 return \"rotl %R3,%1,%0\;movzbl %0,%0\"; 2055 if (INTVAL (operands[2]) == 16) 2056 return \"rotl %R3,%1,%0\;movzwl %0,%0\"; 2057 if (MEM_P (operands[1]) 2058 && GET_CODE (XEXP (operands[1], 0)) == PLUS 2059 && REG_P (XEXP (XEXP (operands[1], 0), 0)) 2060 && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1)) 2061 && CONST_INT_P (operands[2]) 2062 && CONST_INT_P (operands[3])) 2063 { 2064 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1)); 2065 HOST_WIDE_INT l = INTVAL (operands[2]); 2066 HOST_WIDE_INT v = INTVAL (operands[3]); 2067 if ((o & 3) && (o & 3) * 8 + v + l <= 32) 2068 { 2069 rtx tmp; 2070 tmp = XEXP (XEXP (operands[1], 0), 0); 2071 if (o & ~3) 2072 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3)); 2073 operands[1] = gen_rtx_MEM (QImode, tmp); 2074 operands[3] = GEN_INT (v + (o & 3) * 8); 2075 } 2076 if (optimize_size) 2077 return \"extzv %3,%2,%1,%0\"; 2078 } 2079 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\"; 2080}") 2081 2082;; Combine EXTV/CMPL and EXTZV/CMPL sequences where the output of 2083;; extraction is used for the comparison only into CMPV and CMPZV 2084;; respectively. 2085(define_peephole2 2086 [(parallel 2087 [(set (match_operand:SI 0 "register_operand") 2088 (any_extract:SI (match_operand 1 "general_operand") 2089 (match_operand:QI 2 "general_operand") 2090 (match_operand:SI 3 "general_operand"))) 2091 (clobber (reg:CC VAX_PSL_REGNUM))]) 2092 (set (reg:VAXcc VAX_PSL_REGNUM) 2093 (compare:VAXcc (match_dup 0) 2094 (match_operand:SI 4 "general_operand")))] 2095 "peep2_reg_dead_p (2, operands[0])" 2096 [(set (reg:VAXcc VAX_PSL_REGNUM) 2097 (compare:VAXcc 2098 (any_extract:SI (match_dup 1) 2099 (match_dup 2) 2100 (match_dup 3)) 2101 (match_dup 4)))] 2102 "") 2103 2104(define_expand "insv" 2105 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "") 2106 (match_operand:QI 1 "general_operand" "") 2107 (match_operand:SI 2 "general_operand" "")) 2108 (match_operand:SI 3 "general_operand" ""))] 2109 "" 2110 "") 2111 2112;; This one actually doesn't change CC. 2113(define_insn "*insv" 2114 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m") 2115 (match_operand:QI 1 "general_operand" "g") 2116 (match_operand:SI 2 "general_operand" "nrmT")) 2117 (match_operand:SI 3 "general_operand" "nrmT"))] 2118 "" 2119 "* 2120{ 2121 if (MEM_P (operands[0]) 2122 && GET_CODE (XEXP (operands[0], 0)) == PLUS 2123 && REG_P (XEXP (XEXP (operands[0], 0), 0)) 2124 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1)) 2125 && CONST_INT_P (operands[1]) 2126 && CONST_INT_P (operands[2])) 2127 { 2128 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1)); 2129 HOST_WIDE_INT v = INTVAL (operands[2]); 2130 HOST_WIDE_INT l = INTVAL (operands[1]); 2131 if ((o & 3) && (o & 3) * 8 + v + l <= 32) 2132 { 2133 rtx tmp; 2134 tmp = XEXP (XEXP (operands[0], 0), 0); 2135 if (o & ~3) 2136 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3)); 2137 operands[0] = gen_rtx_MEM (QImode, tmp); 2138 operands[2] = GEN_INT (v + (o & 3) * 8); 2139 } 2140 } 2141 return \"insv %3,%2,%1,%0\"; 2142}") 2143 2144;; This one actually doesn't change CC. 2145(define_insn "*insv_2" 2146 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro") 2147 (match_operand:QI 1 "general_operand" "g") 2148 (match_operand:SI 2 "general_operand" "nrmT")) 2149 (match_operand:SI 3 "general_operand" "nrmT"))] 2150 "" 2151 "insv %3,%2,%1,%0") 2152 2153;; Unconditional jump 2154(define_insn "jump" 2155 [(set (pc) 2156 (label_ref (match_operand 0 "" "")))] 2157 "" 2158 "jbr %l0") 2159 2160;; Conditional jumps 2161 2162(define_expand "cbranch<mode>4" 2163 [(set (pc) 2164 (if_then_else 2165 (match_operator 0 "ordered_comparison_operator" 2166 [(match_operand:VAXint 1 "general_operand" "") 2167 (match_operand:VAXint 2 "general_operand" "")]) 2168 (label_ref (match_operand 3 "" "")) 2169 (pc)))] 2170 "" 2171 "") 2172 2173(define_insn_and_split "*cbranch<VAXint:mode>4_<VAXcc:mode>" 2174 [(set (pc) 2175 (if_then_else 2176 (match_operator 0 "vax_<VAXcc:mode>_comparison_operator" 2177 [(match_operand:VAXint 1 "general_operand" "nrmT") 2178 (match_operand:VAXint 2 "general_operand" "nrmT")]) 2179 (label_ref (match_operand 3 "" "")) 2180 (pc)))] 2181 "" 2182 "#" 2183 "reload_completed" 2184 [(set (reg:VAXcc VAX_PSL_REGNUM) 2185 (compare:VAXcc (match_dup 1) (match_dup 2))) 2186 (set (pc) 2187 (if_then_else 2188 (match_op_dup 0 [(reg:VAXcc VAX_PSL_REGNUM) 2189 (const_int 0)]) 2190 (label_ref (match_operand 3 "" "")) 2191 (pc)))] 2192 "") 2193 2194(define_expand "cbranch<mode>4" 2195 [(set (pc) 2196 (if_then_else 2197 (match_operator 0 "ordered_comparison_operator" 2198 [(match_operand:VAXfp 1 "general_operand" "") 2199 (match_operand:VAXfp 2 "general_operand" "")]) 2200 (label_ref (match_operand 3 "" "")) 2201 (pc)))] 2202 "" 2203 "") 2204 2205(define_insn_and_split "*cbranch<VAXfp:mode>4_<VAXccnz:mode>" 2206 [(set (pc) 2207 (if_then_else 2208 (match_operator 0 "vax_<VAXccnz:mode>_comparison_operator" 2209 [(match_operand:VAXfp 1 "general_operand" "gF") 2210 (match_operand:VAXfp 2 "general_operand" "gF")]) 2211 (label_ref (match_operand 3 "" "")) 2212 (pc)))] 2213 "" 2214 "#" 2215 "reload_completed" 2216 [(set (reg:VAXccnz VAX_PSL_REGNUM) 2217 (compare:VAXccnz (match_dup 1) (match_dup 2))) 2218 (set (pc) 2219 (if_then_else 2220 (match_op_dup 0 [(reg:VAXccnz VAX_PSL_REGNUM) 2221 (const_int 0)]) 2222 (label_ref (match_operand 3 "" "")) 2223 (pc)))] 2224 "") 2225 2226(define_insn "*branch_<mode>" 2227 [(set (pc) 2228 (if_then_else (match_operator 0 "vax_<mode>_comparison_operator" 2229 [(reg:VAXcc VAX_PSL_REGNUM) 2230 (const_int 0)]) 2231 (label_ref (match_operand 1 "" "")) 2232 (pc)))] 2233 "reload_completed" 2234 "j%k0 %l1") 2235 2236;; Recognize reversed jumps. 2237(define_insn "*branch_<mode>_reversed" 2238 [(set (pc) 2239 (if_then_else (match_operator 0 "vax_<mode>_comparison_operator" 2240 [(reg:VAXcc VAX_PSL_REGNUM) 2241 (const_int 0)]) 2242 (pc) 2243 (label_ref (match_operand 1 "" ""))))] 2244 "reload_completed" 2245 "j%K0 %l1") ; %K0 negates condition 2246 2247;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand 2248;; of jlbs and jlbc insns are SImode in the hardware. However, if it is 2249;; memory, we use QImode in the insn. So we can't use those instructions 2250;; for mode-dependent addresses. 2251 2252(define_insn "" 2253 [(set (pc) 2254 (if_then_else 2255 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g") 2256 (const_int 1) 2257 (match_operand:SI 1 "general_operand" "I,nrmT")) 2258 (const_int 0)) 2259 (label_ref (match_operand 2 "" "")) 2260 (pc)))] 2261 "" 2262 "@ 2263 jlbs %0,%l2 2264 jbs %1,%0,%l2") 2265 2266(define_insn "" 2267 [(set (pc) 2268 (if_then_else 2269 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g") 2270 (const_int 1) 2271 (match_operand:SI 1 "general_operand" "I,nrmT")) 2272 (const_int 0)) 2273 (label_ref (match_operand 2 "" "")) 2274 (pc)))] 2275 "" 2276 "@ 2277 jlbc %0,%l2 2278 jbc %1,%0,%l2") 2279 2280(define_insn "" 2281 [(set (pc) 2282 (if_then_else 2283 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") 2284 (const_int 1) 2285 (match_operand:SI 1 "general_operand" "I,nrmT")) 2286 (const_int 0)) 2287 (label_ref (match_operand 2 "" "")) 2288 (pc)))] 2289 "" 2290 "@ 2291 jlbs %0,%l2 2292 jbs %1,%0,%l2") 2293 2294(define_insn "" 2295 [(set (pc) 2296 (if_then_else 2297 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") 2298 (const_int 1) 2299 (match_operand:SI 1 "general_operand" "I,nrmT")) 2300 (const_int 0)) 2301 (label_ref (match_operand 2 "" "")) 2302 (pc)))] 2303 "" 2304 "@ 2305 jlbc %0,%l2 2306 jbc %1,%0,%l2") 2307 2308;; Subtract-and-jump and Add-and-jump insns. 2309;; These are not used when output is for the Unix assembler 2310;; because it does not know how to modify them to reach far. 2311 2312;; Normal sob insns. 2313 2314(define_insn_and_split "*jsobgtr" 2315 [(set (pc) 2316 (if_then_else 2317 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2318 (const_int -1)) 2319 (const_int 0)) 2320 (label_ref (match_operand 1 "" "")) 2321 (pc))) 2322 (set (match_dup 0) 2323 (plus:SI (match_dup 0) 2324 (const_int -1)))] 2325 "!TARGET_UNIX_ASM" 2326 "#" 2327 "&& reload_completed" 2328 [(parallel 2329 [(set (pc) 2330 (if_then_else 2331 (gt (plus:SI (match_dup 0) 2332 (const_int -1)) 2333 (const_int 0)) 2334 (label_ref (match_dup 1)) 2335 (pc))) 2336 (set (match_dup 0) 2337 (plus:SI (match_dup 0) 2338 (const_int -1))) 2339 (clobber (reg:CC VAX_PSL_REGNUM))])] 2340 "") 2341 2342(define_insn "*jsobgtr_2" 2343 [(set (pc) 2344 (if_then_else 2345 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2346 (const_int -1)) 2347 (const_int 0)) 2348 (label_ref (match_operand 1 "" "")) 2349 (pc))) 2350 (set (match_dup 0) 2351 (plus:SI (match_dup 0) 2352 (const_int -1))) 2353 (clobber (reg:CC VAX_PSL_REGNUM))] 2354 "!TARGET_UNIX_ASM && reload_completed" 2355 "jsobgtr %0,%l1") 2356 2357(define_insn_and_split "*jsobgeq" 2358 [(set (pc) 2359 (if_then_else 2360 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2361 (const_int -1)) 2362 (const_int 0)) 2363 (label_ref (match_operand 1 "" "")) 2364 (pc))) 2365 (set (match_dup 0) 2366 (plus:SI (match_dup 0) 2367 (const_int -1)))] 2368 "!TARGET_UNIX_ASM" 2369 "#" 2370 "&& reload_completed" 2371 [(parallel 2372 [(set (pc) 2373 (if_then_else 2374 (ge (plus:SI (match_dup 0) 2375 (const_int -1)) 2376 (const_int 0)) 2377 (label_ref (match_dup 1)) 2378 (pc))) 2379 (set (match_dup 0) 2380 (plus:SI (match_dup 0) 2381 (const_int -1))) 2382 (clobber (reg:CC VAX_PSL_REGNUM))])] 2383 "") 2384 2385(define_insn "*jsobgeq_2" 2386 [(set (pc) 2387 (if_then_else 2388 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2389 (const_int -1)) 2390 (const_int 0)) 2391 (label_ref (match_operand 1 "" "")) 2392 (pc))) 2393 (set (match_dup 0) 2394 (plus:SI (match_dup 0) 2395 (const_int -1))) 2396 (clobber (reg:CC VAX_PSL_REGNUM))] 2397 "!TARGET_UNIX_ASM && reload_completed" 2398 "jsobgeq %0,%l1") 2399 2400;; Normal aob insns. Define a version for when operands[1] is a constant. 2401(define_insn_and_split "*jaoblss" 2402 [(set (pc) 2403 (if_then_else 2404 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2405 (const_int 1)) 2406 (match_operand:SI 1 "general_operand" "nrmT")) 2407 (label_ref (match_operand 2 "" "")) 2408 (pc))) 2409 (set (match_dup 0) 2410 (plus:SI (match_dup 0) 2411 (const_int 1)))] 2412 "!TARGET_UNIX_ASM" 2413 "#" 2414 "&& reload_completed" 2415 [(parallel 2416 [(set (pc) 2417 (if_then_else 2418 (lt (plus:SI (match_dup 0) 2419 (const_int 1)) 2420 (match_dup 1)) 2421 (label_ref (match_dup 2)) 2422 (pc))) 2423 (set (match_dup 0) 2424 (plus:SI (match_dup 0) 2425 (const_int 1))) 2426 (clobber (reg:CC VAX_PSL_REGNUM))])] 2427 "") 2428 2429(define_insn "*jaoblss_2" 2430 [(set (pc) 2431 (if_then_else 2432 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2433 (const_int 1)) 2434 (match_operand:SI 1 "general_operand" "nrmT")) 2435 (label_ref (match_operand 2 "" "")) 2436 (pc))) 2437 (set (match_dup 0) 2438 (plus:SI (match_dup 0) 2439 (const_int 1))) 2440 (clobber (reg:CC VAX_PSL_REGNUM))] 2441 "!TARGET_UNIX_ASM && reload_completed" 2442 "jaoblss %1,%0,%l2") 2443 2444(define_insn_and_split "*jaoblss_const" 2445 [(set (pc) 2446 (if_then_else 2447 (lt (match_operand:SI 0 "nonimmediate_operand" "+g") 2448 (match_operand:SI 1 "general_operand" "nrmT")) 2449 (label_ref (match_operand 2 "" "")) 2450 (pc))) 2451 (set (match_dup 0) 2452 (plus:SI (match_dup 0) 2453 (const_int 1)))] 2454 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])" 2455 "#" 2456 "&& reload_completed" 2457 [(parallel 2458 [(set (pc) 2459 (if_then_else 2460 (lt (match_dup 0) 2461 (match_dup 1)) 2462 (label_ref (match_dup 2)) 2463 (pc))) 2464 (set (match_dup 0) 2465 (plus:SI (match_dup 0) 2466 (const_int 1))) 2467 (clobber (reg:CC VAX_PSL_REGNUM))])] 2468 "") 2469 2470(define_insn "*jaoblss_const_2" 2471 [(set (pc) 2472 (if_then_else 2473 (lt (match_operand:SI 0 "nonimmediate_operand" "+g") 2474 (match_operand:SI 1 "general_operand" "nrmT")) 2475 (label_ref (match_operand 2 "" "")) 2476 (pc))) 2477 (set (match_dup 0) 2478 (plus:SI (match_dup 0) 2479 (const_int 1))) 2480 (clobber (reg:CC VAX_PSL_REGNUM))] 2481 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1]) && reload_completed" 2482 "jaoblss %P1,%0,%l2") 2483 2484(define_insn_and_split "*jaobleq" 2485 [(set (pc) 2486 (if_then_else 2487 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2488 (const_int 1)) 2489 (match_operand:SI 1 "general_operand" "nrmT")) 2490 (label_ref (match_operand 2 "" "")) 2491 (pc))) 2492 (set (match_dup 0) 2493 (plus:SI (match_dup 0) 2494 (const_int 1)))] 2495 "!TARGET_UNIX_ASM" 2496 "#" 2497 "&& reload_completed" 2498 [(parallel 2499 [(set (pc) 2500 (if_then_else 2501 (le (plus:SI (match_dup 0) 2502 (const_int 1)) 2503 (match_dup 1)) 2504 (label_ref (match_dup 2)) 2505 (pc))) 2506 (set (match_dup 0) 2507 (plus:SI (match_dup 0) 2508 (const_int 1))) 2509 (clobber (reg:CC VAX_PSL_REGNUM))])] 2510 "") 2511 2512(define_insn "*jaobleq_2" 2513 [(set (pc) 2514 (if_then_else 2515 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2516 (const_int 1)) 2517 (match_operand:SI 1 "general_operand" "nrmT")) 2518 (label_ref (match_operand 2 "" "")) 2519 (pc))) 2520 (set (match_dup 0) 2521 (plus:SI (match_dup 0) 2522 (const_int 1))) 2523 (clobber (reg:CC VAX_PSL_REGNUM))] 2524 "!TARGET_UNIX_ASM && reload_completed" 2525 "jaobleq %1,%0,%l2") 2526 2527(define_insn_and_split "*jaobleq_const" 2528 [(set (pc) 2529 (if_then_else 2530 (le (match_operand:SI 0 "nonimmediate_operand" "+g") 2531 (match_operand:SI 1 "general_operand" "nrmT")) 2532 (label_ref (match_operand 2 "" "")) 2533 (pc))) 2534 (set (match_dup 0) 2535 (plus:SI (match_dup 0) 2536 (const_int 1)))] 2537 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])" 2538 "#" 2539 "&& reload_completed" 2540 [(parallel 2541 [(set (pc) 2542 (if_then_else 2543 (le (match_dup 0) 2544 (match_dup 1)) 2545 (label_ref (match_dup 2)) 2546 (pc))) 2547 (set (match_dup 0) 2548 (plus:SI (match_dup 0) 2549 (const_int 1))) 2550 (clobber (reg:CC VAX_PSL_REGNUM))])] 2551 "") 2552 2553(define_insn "*jaobleq_const_2" 2554 [(set (pc) 2555 (if_then_else 2556 (le (match_operand:SI 0 "nonimmediate_operand" "+g") 2557 (match_operand:SI 1 "general_operand" "nrmT")) 2558 (label_ref (match_operand 2 "" "")) 2559 (pc))) 2560 (set (match_dup 0) 2561 (plus:SI (match_dup 0) 2562 (const_int 1))) 2563 (clobber (reg:CC VAX_PSL_REGNUM))] 2564 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1]) && reload_completed" 2565 "jaobleq %P1,%0,%l2") 2566 2567;; Something like a sob insn, but compares against -1. 2568;; This finds `while (foo--)' which was changed to `while (--foo != -1)'. 2569 2570(define_insn_and_split "*jsobneq_minus_one" 2571 [(set (pc) 2572 (if_then_else 2573 (ne (match_operand:SI 0 "nonimmediate_operand" "+g") 2574 (const_int 0)) 2575 (label_ref (match_operand 1 "" "")) 2576 (pc))) 2577 (set (match_dup 0) 2578 (plus:SI (match_dup 0) 2579 (const_int -1)))] 2580 "" 2581 "#" 2582 "reload_completed" 2583 [(parallel 2584 [(set (pc) 2585 (if_then_else 2586 (ne (match_dup 0) 2587 (const_int 0)) 2588 (label_ref (match_dup 1)) 2589 (pc))) 2590 (set (match_dup 0) 2591 (plus:SI (match_dup 0) 2592 (const_int -1))) 2593 (clobber (reg:CC VAX_PSL_REGNUM))])] 2594 "") 2595 2596(define_insn "*jsobneq_minus_one_2" 2597 [(set (pc) 2598 (if_then_else 2599 (ne (match_operand:SI 0 "nonimmediate_operand" "+g") 2600 (const_int 0)) 2601 (label_ref (match_operand 1 "" "")) 2602 (pc))) 2603 (set (match_dup 0) 2604 (plus:SI (match_dup 0) 2605 (const_int -1))) 2606 (clobber (reg:CC VAX_PSL_REGNUM))] 2607 "reload_completed" 2608 "decl %0\;jgequ %l1") 2609 2610(define_expand "call_pop" 2611 [(parallel [(call (match_operand:QI 0 "memory_operand" "") 2612 (match_operand:SI 1 "const_int_operand" "")) 2613 (set (reg:SI VAX_SP_REGNUM) 2614 (plus:SI (reg:SI VAX_SP_REGNUM) 2615 (match_operand:SI 3 "immediate_operand" "")))])] 2616 "" 2617{ 2618 gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0); 2619 2620 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size 2621 during EH unwinding. We must include the argument count pushed by 2622 the calls instruction. */ 2623 operands[1] = GEN_INT (INTVAL (operands[3]) + 4); 2624}) 2625 2626(define_insn "*call_pop" 2627 [(call (match_operand:QI 0 "memory_operand" "m") 2628 (match_operand:SI 1 "const_int_operand" "n")) 2629 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM) 2630 (match_operand:SI 2 "immediate_operand" "i")))] 2631 "" 2632{ 2633 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4); 2634 return "calls %1,%0"; 2635}) 2636 2637(define_expand "call_value_pop" 2638 [(parallel [(set (match_operand 0 "" "") 2639 (call (match_operand:QI 1 "memory_operand" "") 2640 (match_operand:SI 2 "const_int_operand" ""))) 2641 (set (reg:SI VAX_SP_REGNUM) 2642 (plus:SI (reg:SI VAX_SP_REGNUM) 2643 (match_operand:SI 4 "immediate_operand" "")))])] 2644 "" 2645{ 2646 gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0); 2647 2648 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size 2649 during EH unwinding. We must include the argument count pushed by 2650 the calls instruction. */ 2651 operands[2] = GEN_INT (INTVAL (operands[4]) + 4); 2652}) 2653 2654(define_insn "*call_value_pop" 2655 [(set (match_operand 0 "" "") 2656 (call (match_operand:QI 1 "memory_operand" "m") 2657 (match_operand:SI 2 "const_int_operand" "n"))) 2658 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM) 2659 (match_operand:SI 3 "immediate_operand" "i")))] 2660 "" 2661 "* 2662{ 2663 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4); 2664 return \"calls %2,%1\"; 2665}") 2666 2667(define_expand "call" 2668 [(call (match_operand:QI 0 "memory_operand" "") 2669 (match_operand:SI 1 "const_int_operand" ""))] 2670 "" 2671 " 2672{ 2673 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size 2674 during EH unwinding. We must include the argument count pushed by 2675 the calls instruction. */ 2676 operands[1] = GEN_INT (INTVAL (operands[1]) + 4); 2677}") 2678 2679(define_insn "*call" 2680 [(call (match_operand:QI 0 "memory_operand" "m") 2681 (match_operand:SI 1 "const_int_operand" ""))] 2682 "" 2683 "calls $0,%0") 2684 2685(define_expand "call_value" 2686 [(set (match_operand 0 "" "") 2687 (call (match_operand:QI 1 "memory_operand" "") 2688 (match_operand:SI 2 "const_int_operand" "")))] 2689 "" 2690 " 2691{ 2692 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size 2693 during EH unwinding. We must include the argument count pushed by 2694 the calls instruction. */ 2695 operands[2] = GEN_INT (INTVAL (operands[2]) + 4); 2696}") 2697 2698(define_insn "*call_value" 2699 [(set (match_operand 0 "" "") 2700 (call (match_operand:QI 1 "memory_operand" "m") 2701 (match_operand:SI 2 "const_int_operand" "")))] 2702 "" 2703 "calls $0,%1") 2704 2705;; Call subroutine returning any type. 2706 2707(define_expand "untyped_call" 2708 [(parallel [(call (match_operand 0 "" "") 2709 (const_int 0)) 2710 (match_operand 1 "" "") 2711 (match_operand 2 "" "")])] 2712 "" 2713 " 2714{ 2715 int i; 2716 2717 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx)); 2718 2719 for (i = 0; i < XVECLEN (operands[2], 0); i++) 2720 { 2721 rtx set = XVECEXP (operands[2], 0, i); 2722 emit_move_insn (SET_DEST (set), SET_SRC (set)); 2723 } 2724 2725 /* The optimizer does not know that the call sets the function value 2726 registers we stored in the result block. We avoid problems by 2727 claiming that all hard registers are used and clobbered at this 2728 point. */ 2729 emit_insn (gen_blockage ()); 2730 2731 DONE; 2732}") 2733 2734;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 2735;; all of memory. This blocks insns from being moved across this point. 2736 2737(define_insn "blockage" 2738 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)] 2739 "" 2740 "") 2741 2742(define_insn "procedure_entry_mask" 2743 [(unspec_volatile [(match_operand 0 "const_int_operand")] VUNSPEC_PEM)] 2744 "" 2745 ".word %x0") 2746 2747(define_insn "return" 2748 [(return)] 2749 "" 2750 "ret") 2751 2752(define_expand "prologue" 2753 [(const_int 0)] 2754 "" 2755{ 2756 vax_expand_prologue (); 2757 DONE; 2758}) 2759 2760(define_expand "epilogue" 2761 [(return)] 2762 "" 2763 " 2764{ 2765 emit_jump_insn (gen_return ()); 2766 DONE; 2767}") 2768 2769(define_insn "nop" 2770 [(const_int 0)] 2771 "" 2772 "nop") 2773 2774;; This had a wider constraint once, and it had trouble. 2775;; If you are tempted to try `g', please don't--it's not worth 2776;; the risk we will reopen the same bug. 2777(define_insn "indirect_jump" 2778 [(set (pc) (match_operand:SI 0 "register_operand" "r"))] 2779 "" 2780 "jmp (%0)") 2781 2782;; This is here to accept 5 arguments (as passed by expand_end_case) 2783;; and pass the first 4 along to the casesi1 pattern that really does 2784;; the actual casesi work. We emit a jump here to the default label 2785;; _before_ the casesi so that we can be sure that the casesi never 2786;; drops through. 2787;; This is suboptimal perhaps, but so is much of the rest of this 2788;; machine description. For what it's worth, HPPA uses the same trick. 2789;; 2790;; operand 0 is index 2791;; operand 1 is the minimum bound (a const_int) 2792;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int) 2793;; operand 3 is CODE_LABEL for the table; 2794;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default). 2795;; 2796;; We emit: 2797;; i = index - minimum_bound 2798;; if (i > (maximum_bound - minimum_bound + 1) goto default; 2799;; casesi (i, 0, table); 2800;; 2801(define_expand "casesi" 2802 [(match_operand:SI 0 "general_operand" "") 2803 (match_operand:SI 1 "general_operand" "") 2804 (match_operand:SI 2 "general_operand" "") 2805 (match_operand 3 "" "") 2806 (match_operand 4 "" "")] 2807 "" 2808{ 2809 rtx test; 2810 2811 /* i = index - minimum_bound; 2812 But only if the lower bound is not already zero. */ 2813 if (operands[1] != const0_rtx) 2814 { 2815 rtx index = gen_reg_rtx (SImode); 2816 emit_insn (gen_addsi3 (index, 2817 operands[0], 2818 gen_int_mode (-INTVAL (operands[1]), SImode))); 2819 operands[0] = index; 2820 } 2821 2822 /* if (i > (maximum_bound - minimum_bound + 1)) goto default; */ 2823 test = gen_rtx_fmt_ee (GTU, VOIDmode, operands[0], operands[2]); 2824 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4])); 2825 2826 /* casesi (i, 0, table); */ 2827 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3])); 2828 DONE; 2829}) 2830 2831;; This insn is a bit of a lier. It actually falls through if no case 2832;; matches. But, we prevent that from ever happening by emitting a jump 2833;; before this, see the define_expand above. 2834(define_insn_and_split "casesi1" 2835 [(match_operand:SI 1 "const_int_operand" "n") 2836 (set (pc) 2837 (plus:SI (sign_extend:SI 2838 (mem:HI (plus:SI 2839 (mult:SI 2840 (match_operand:SI 0 "general_operand" "nrmT") 2841 (const_int 2)) 2842 (pc)))) 2843 (label_ref:SI (match_operand 2 "" ""))))] 2844 "" 2845 "#" 2846 "reload_completed" 2847 [(parallel 2848 [(match_dup 1) 2849 (set (pc) 2850 (plus:SI (sign_extend:SI 2851 (mem:HI (plus:SI 2852 (mult:SI 2853 (match_dup 0) 2854 (const_int 2)) 2855 (pc)))) 2856 (label_ref:SI (match_dup 2)))) 2857 (clobber (reg:CC VAX_PSL_REGNUM))])] 2858 "") 2859 2860(define_insn "*casesi1" 2861 [(match_operand:SI 1 "const_int_operand" "n") 2862 (set (pc) 2863 (plus:SI (sign_extend:SI 2864 (mem:HI (plus:SI 2865 (mult:SI 2866 (match_operand:SI 0 "general_operand" "nrmT") 2867 (const_int 2)) 2868 (pc)))) 2869 (label_ref:SI (match_operand 2 "" "")))) 2870 (clobber (reg:CC VAX_PSL_REGNUM))] 2871 "reload_completed" 2872 "casel %0,$0,%1") 2873 2874(define_insn_and_split "*pushsym" 2875 [(set (match_operand:SI 0 "push_operand" "=g") 2876 (match_operand:SI 1 "pic_symbolic_operand" "A"))] 2877 "" 2878 "#" 2879 "reload_completed" 2880 [(parallel 2881 [(set (match_dup 0) 2882 (match_dup 1)) 2883 (clobber (reg:CC VAX_PSL_REGNUM))])] 2884 "") 2885 2886(define_insn "*pushsym_2<ccn><ccnz><ccz>" 2887 [(set (match_operand:SI 0 "push_operand" "=g") 2888 (match_operand:SI 1 "pic_symbolic_operand" "A")) 2889 (clobber (reg:CC VAX_PSL_REGNUM))] 2890 "reload_completed" 2891 "pushab %a1") 2892 2893(define_insn_and_split "*movsym" 2894 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2895 (match_operand:SI 1 "pic_symbolic_operand" "A"))] 2896 "" 2897 "#" 2898 "reload_completed" 2899 [(parallel 2900 [(set (match_dup 0) 2901 (match_dup 1)) 2902 (clobber (reg:CC VAX_PSL_REGNUM))])] 2903 "") 2904 2905(define_insn "*movsym_2<ccn><ccnz><ccz>" 2906 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2907 (match_operand:SI 1 "pic_symbolic_operand" "A")) 2908 (clobber (reg:CC VAX_PSL_REGNUM))] 2909 "reload_completed" 2910 "movab %a1,%0") 2911 2912(define_insn_and_split "*pushsymreg" 2913 [(set (match_operand:SI 0 "push_operand" "=g") 2914 (plus:SI (match_operand:SI 1 "register_operand" "%r") 2915 (match_operand:SI 2 "pic_symbolic_operand" "A")))] 2916 "flag_pic" 2917 "#" 2918 "&& reload_completed" 2919 [(parallel 2920 [(set (match_dup 0) 2921 (plus:SI (match_dup 1) 2922 (match_dup 2))) 2923 (clobber (reg:CC VAX_PSL_REGNUM))])] 2924 "") 2925 2926(define_insn "*pushsymreg_2<ccn><ccnz><ccz>" 2927 [(set (match_operand:SI 0 "push_operand" "=g") 2928 (plus:SI (match_operand:SI 1 "register_operand" "%r") 2929 (match_operand:SI 2 "pic_symbolic_operand" "A"))) 2930 (clobber (reg:CC VAX_PSL_REGNUM))] 2931 "flag_pic && reload_completed" 2932 "pushab %a2[%1]") 2933 2934(define_insn_and_split "*movsymreg" 2935 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2936 (plus:SI (match_operand:SI 1 "register_operand" "%r") 2937 (match_operand:SI 2 "pic_symbolic_operand" "A")))] 2938 "flag_pic" 2939 "#" 2940 "&& reload_completed" 2941 [(parallel 2942 [(set (match_dup 0) 2943 (plus:SI (match_dup 1) 2944 (match_dup 2))) 2945 (clobber (reg:CC VAX_PSL_REGNUM))])] 2946 "") 2947 2948(define_insn "*movsymreg_2<ccn><ccnz><ccz>" 2949 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2950 (plus:SI (match_operand:SI 1 "register_operand" "%r") 2951 (match_operand:SI 2 "pic_symbolic_operand" "A"))) 2952 (clobber (reg:CC VAX_PSL_REGNUM))] 2953 "flag_pic && reload_completed" 2954 "movab %a2[%1],%0") 2955 2956;;- load or push effective address 2957;; These come after the move and add/sub patterns 2958;; because we don't want pushl $1 turned into pushad 1. 2959;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3. 2960 2961;; It does not work to use constraints to distinguish pushes from moves, 2962;; because < matches any autodecrement, not just a push. 2963 2964(define_insn_and_split "pushaddr<mode>" 2965 [(set (match_operand:SI 0 "push_operand" "=g") 2966 (match_operand:VAXintQHSD 1 "address_operand" "p"))] 2967 "" 2968 "#" 2969 "reload_completed" 2970 [(parallel 2971 [(set (match_dup 0) 2972 (match_dup 1)) 2973 (clobber (reg:CC VAX_PSL_REGNUM))])] 2974 "") 2975 2976(define_insn "*pushaddr<mode><ccn><ccnz><ccz>" 2977 [(set (match_operand:SI 0 "push_operand" "=g") 2978 (match_operand:VAXintQHSD 1 "address_operand" "p")) 2979 (clobber (reg:CC VAX_PSL_REGNUM))] 2980 "reload_completed" 2981 "pusha<VAXintQHSD:isfx> %a1") 2982 2983(define_insn_and_split "movaddr<mode>" 2984 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2985 (match_operand:VAXintQHSD 1 "address_operand" "p"))] 2986 "" 2987 "#" 2988 "reload_completed" 2989 [(parallel 2990 [(set (match_dup 0) 2991 (match_dup 1)) 2992 (clobber (reg:CC VAX_PSL_REGNUM))])] 2993 "") 2994 2995(define_insn "*movaddr<mode><ccn><ccnz><ccz>" 2996 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2997 (match_operand:VAXintQHSD 1 "address_operand" "p")) 2998 (clobber (reg:CC VAX_PSL_REGNUM))] 2999 "reload_completed" 3000 "mova<VAXintQHSD:isfx> %a1,%0") 3001 3002(define_insn_and_split "pushaddr<mode>" 3003 [(set (match_operand:SI 0 "push_operand" "=g") 3004 (match_operand:VAXfp 1 "address_operand" "p"))] 3005 "" 3006 "#" 3007 "reload_completed" 3008 [(parallel 3009 [(set (match_dup 0) 3010 (match_dup 1)) 3011 (clobber (reg:CC VAX_PSL_REGNUM))])] 3012 "") 3013 3014(define_insn "*pushaddr<mode><ccn><ccnz><ccz>" 3015 [(set (match_operand:SI 0 "push_operand" "=g") 3016 (match_operand:VAXfp 1 "address_operand" "p")) 3017 (clobber (reg:CC VAX_PSL_REGNUM))] 3018 "reload_completed" 3019 "pusha<VAXfp:fsfx> %a1") 3020 3021(define_insn_and_split "movaddr<mode>" 3022 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 3023 (match_operand:VAXfp 1 "address_operand" "p"))] 3024 "" 3025 "#" 3026 "reload_completed" 3027 [(parallel 3028 [(set (match_dup 0) 3029 (match_dup 1)) 3030 (clobber (reg:CC VAX_PSL_REGNUM))])] 3031 "") 3032 3033(define_insn "*movaddr<mode>" 3034 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 3035 (match_operand:VAXfp 1 "address_operand" "p")) 3036 (clobber (reg:CC VAX_PSL_REGNUM))] 3037 "reload_completed" 3038 "mova<VAXfp:fsfx> %a1,%0") 3039 3040;; These used to be peepholes, but it is more straightforward to do them 3041;; as single insns. However, we must force the output to be a register 3042;; if it is not an offsettable address so that we know that we can assign 3043;; to it twice. 3044 3045;; If we had a good way of evaluating the relative costs, these could be 3046;; machine-independent. 3047 3048;; Optimize extzv ...,z; andl2 ...,z 3049;; or ashl ...,z; andl2 ...,z 3050;; with other operands constant. This is what the combiner converts the 3051;; above sequences to before attempting to recognize the new insn. 3052 3053(define_insn_and_split "*andashlnegsi4" 3054 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 3055 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 3056 (match_operand:QI 2 "const_int_operand" "n")) 3057 (match_operand:SI 3 "const_int_operand" "n")))] 3058 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0" 3059 "#" 3060 "&& reload_completed" 3061 [(parallel 3062 [(set (match_dup 0) 3063 (and:SI (ashiftrt:SI (match_dup 1) 3064 (match_dup 2)) 3065 (match_dup 3))) 3066 (clobber (reg:CC VAX_PSL_REGNUM))])] 3067 "") 3068 3069(define_insn "*andashlnegsi4_2<ccn><ccnz><ccz>" 3070 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 3071 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 3072 (match_operand:QI 2 "const_int_operand" "n")) 3073 (match_operand:SI 3 "const_int_operand" "n"))) 3074 (clobber (reg:CC VAX_PSL_REGNUM))] 3075 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0 3076 && reload_completed" 3077 "* 3078{ 3079 unsigned long mask1 = INTVAL (operands[3]); 3080 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1; 3081 3082 if ((mask1 & mask2) != mask1) 3083 operands[3] = GEN_INT (mask1 & mask2); 3084 3085 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\"; 3086}") 3087 3088;; left-shift and mask 3089;; The only case where `ashl' is better is if the mask only turns off 3090;; bits that the ashl would anyways, in which case it should have been 3091;; optimized away. 3092 3093(define_insn_and_split "*andashlsi4" 3094 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 3095 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT") 3096 (match_operand:QI 2 "const_int_operand" "n")) 3097 (match_operand:SI 3 "const_int_operand" "n")))] 3098 "" 3099 "#" 3100 "reload_completed" 3101 [(parallel 3102 [(set (match_dup 0) 3103 (and:SI (ashift:SI (match_dup 1) 3104 (match_dup 2)) 3105 (match_dup 3))) 3106 (clobber (reg:CC VAX_PSL_REGNUM))])] 3107 "") 3108 3109(define_insn "*andashlsi4_2<ccn><ccnz><ccz>" 3110 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 3111 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT") 3112 (match_operand:QI 2 "const_int_operand" "n")) 3113 (match_operand:SI 3 "const_int_operand" "n"))) 3114 (clobber (reg:CC VAX_PSL_REGNUM))] 3115 "reload_completed" 3116 "* 3117{ 3118 operands[3] 3119 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1)); 3120 return \"rotl %2,%1,%0\;bicl2 %N3,%0\"; 3121}") 3122 3123;; Instruction sequence to sync the VAX instruction stream. 3124(define_insn "sync_istream" 3125 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)] 3126 "" 3127 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei") 3128 3129(define_expand "nonlocal_goto" 3130 [(use (match_operand 0 "general_operand" "")) 3131 (use (match_operand 1 "general_operand" "")) 3132 (use (match_operand 2 "general_operand" "")) 3133 (use (match_operand 3 "general_operand" ""))] 3134 "" 3135{ 3136 rtx lab = operands[1]; 3137 rtx stack = operands[2]; 3138 rtx fp = operands[3]; 3139 3140 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode))); 3141 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx)); 3142 3143 emit_move_insn (hard_frame_pointer_rtx, fp); 3144 emit_stack_restore (SAVE_NONLOCAL, stack); 3145 3146 emit_use (hard_frame_pointer_rtx); 3147 emit_use (stack_pointer_rtx); 3148 3149 /* We'll convert this to direct jump via a peephole optimization. */ 3150 emit_indirect_jump (copy_to_reg (lab)); 3151 emit_barrier (); 3152 DONE; 3153}) 3154 3155(include "builtins.md") 3156