1;; Instruction Classification for ARM for GNU compiler. 2 3;; Copyright (C) 1991-2021 Free Software Foundation, Inc. 4;; Contributed by ARM Ltd. 5 6;; This file is part of GCC. 7 8;; GCC is free software; you can redistribute it and/or modify it 9;; under the terms of the GNU General Public License as published 10;; by the Free Software Foundation; either version 3, or (at your 11;; option) any later version. 12 13;; GCC is distributed in the hope that it will be useful, but WITHOUT 14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16;; License for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21 22; The insn need to autodetect for specific type attribute 23(define_attr "autodetect_type" 24 "none, 25 alu_shift_lsl_op2, 26 alu_shift_lsr_op2, 27 alu_shift_asr_op2, 28 alu_shift_mul_op3, 29 alu_shift_operator1, 30 alu_shift_operator2, 31 alu_shift_operator3, 32 alu_shift_operator4" 33 (const_string "none")) 34 35; TYPE attribute is used to classify instructions for use in scheduling. 36; 37; Instruction classification: 38; 39; adc_imm add/subtract with carry and with an immediate operand. 40; adc_reg add/subtract with carry and no immediate operand. 41; adcs_imm as adc_imm, setting condition flags. 42; adcs_reg as adc_reg, setting condition flags. 43; adr calculate address. 44; alu_ext From ARMv8-A: any arithmetic instruction that has a 45; sign/zero-extended. 46; AArch64 Only. 47; source operand 48; alu_imm any arithmetic instruction that doesn't have a shifted 49; operand and has an immediate operand. This 50; excludes MOV, MVN and RSB(S) immediate. 51; alu_sreg any arithmetic instruction that doesn't have a shifted 52; or an immediate operand. This excludes 53; MOV and MVN but includes MOVT. This also excludes 54; DSP-kind instructions. This is also the default. 55; alu_shift_imm_lsl_1to4 56; any arithmetic instruction that has a source operand 57; shifted left by a constant in range 1 to 4. This 58; excludes simple shifts. 59; alu_shift_imm_other 60; as alu_shift_imm_lsl_1to4, with the shift type is LSR or 61; ASR, or the shift amount is greater than or equal 5. 62; alu_shift_reg as alu_shift_imm_*, with the shift amount specified in a 63; register. 64; alu_dsp_reg any DSP-kind instruction like QSUB8. 65; alus_ext From ARMv8-A: as alu_ext, setting condition flags. 66; AArch64 Only. 67; alus_imm as alu_imm, setting condition flags. 68; alus_sreg as alu_sreg, setting condition flags. 69; alus_shift_imm as alu_shift_imm_*, setting condition flags. 70; alus_shift_reg as alu_shift_reg, setting condition flags. 71; bfm bitfield move operation. 72; bfx bitfield extract operation. 73; block blockage insn, this blocks all functional units. 74; branch branch. 75; call subroutine call. 76; clz count leading zeros (CLZ). 77; csel From ARMv8-A: conditional select. 78; extend extend instruction (SXTB, SXTH, UXTB, UXTH). 79; f_cvt conversion between float representations. 80; f_cvtf2i conversion between float and integral types. 81; f_cvti2f conversion between integral and float types. 82; f_flag transfer of co-processor flags to the CPSR. 83; f_load[d,s] double/single load from memory. Used for VFP unit. 84; f_mcr transfer arm to vfp reg. 85; f_mcrr transfer two arm regs to vfp reg. 86; f_minmax[d,s] double/single floating point minimum/maximum. 87; f_mrc transfer vfp to arm reg. 88; f_mrrc transfer vfp to two arm regs. 89; f_rint[d,s] double/single floating point rount to integral. 90; f_store[d,s] double/single store to memory. Used for VFP unit. 91; fadd[d,s] double/single floating-point scalar addition. 92; fccmp[d,s] From ARMv8-A: floating-point conditional compare. 93; fcmp[d,s] double/single floating-point compare. 94; fconst[d,s] double/single load immediate. 95; fcsel From ARMv8-A: Floating-point conditional select. 96; fdiv[d,s] double/single precision floating point division. 97; ffarith[d,s] double/single floating point abs/neg/cpy. 98; ffma[d,s] double/single floating point fused multiply-accumulate. 99; float floating point arithmetic operation. 100; fmac[d,s] double/single floating point multiply-accumulate. 101; fmov floating point to floating point register move. 102; fmul[d,s] double/single floating point multiply. 103; fsqrt[d,s] double/single precision floating point square root. 104; load_acq load-acquire. 105; load_byte load 1 byte from memory. 106; load_4 load 4 bytes from memory. 107; load_8 load 8 bytes from memory. 108; load_12 load 12 bytes from memory. 109; load_16 load 16 bytes from memory. 110; logic_imm any logical instruction that doesn't have a shifted 111; operand and has an immediate operand. 112; logic_reg any logical instruction that doesn't have a shifted 113; operand or an immediate operand. 114; logic_shift_imm any logical instruction that has a source operand 115; shifted by a constant. This excludes simple shifts. 116; logic_shift_reg as logic_shift_imm, with the shift amount specified in a 117; register. 118; logics_imm as logic_imm, setting condition flags. 119; logics_reg as logic_reg, setting condition flags. 120; logics_shift_imm as logic_shift_imm, setting condition flags. 121; logics_shift_reg as logic_shift_reg, setting condition flags. 122; mla integer multiply accumulate. 123; mlas integer multiply accumulate, flag setting. 124; mov_imm simple MOV instruction that moves an immediate to 125; register. This includes MOVW, but not MOVT. 126; mov_reg simple MOV instruction that moves a register to another 127; register. This includes MOVW, but not MOVT. 128; mov_shift simple MOV instruction, shifted operand by a constant. 129; mov_shift_reg simple MOV instruction, shifted operand by a register. 130; mrs system/special/co-processor register move. 131; mul integer multiply. 132; muls integer multiply, flag setting. 133; multiple more than one instruction, candidate for future 134; splitting, or better modeling. 135; mvn_imm inverting move instruction, immediate. 136; mvn_reg inverting move instruction, register. 137; mvn_shift inverting move instruction, shifted operand by a constant. 138; mvn_shift_reg inverting move instruction, shifted operand by a register. 139; no_insn an insn which does not represent an instruction in the 140; final output, thus having no impact on scheduling. 141; rbit reverse bits. 142; rev reverse bytes. 143; rotate_imm rotate by immediate. 144; sdiv signed division. 145; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an 146; immediate. 147; shift_reg simple shift by a register. 148; smlad signed multiply accumulate dual. 149; smladx signed multiply accumulate dual reverse. 150; smlal signed multiply accumulate long. 151; smlald signed multiply accumulate long dual. 152; smlals signed multiply accumulate long, flag setting. 153; smlalxy signed multiply accumulate, 16x16-bit, 64-bit accumulate. 154; smlawx signed multiply accumulate, 32x16-bit, 32-bit accumulate. 155; smlawy signed multiply accumulate wide, 32x16-bit, 156; 32-bit accumulate. 157; smlaxy signed multiply accumulate, 16x16-bit, 32-bit accumulate. 158; smlsd signed multiply subtract dual. 159; smlsdx signed multiply subtract dual reverse. 160; smlsld signed multiply subtract long dual. 161; smmla signed most significant word multiply accumulate. 162; smmul signed most significant word multiply. 163; smmulr signed most significant word multiply, rounded. 164; smuad signed dual multiply add. 165; smuadx signed dual multiply add reverse. 166; smull signed multiply long. 167; smulls signed multiply long, flag setting. 168; smulwy signed multiply wide, 32x16-bit, 32-bit accumulate. 169; smulxy signed multiply, 16x16-bit, 32-bit accumulate. 170; smusd signed dual multiply subtract. 171; smusdx signed dual multiply subtract reverse. 172; store_rel store-release. 173; store_4 store 4 bytes to memory. 174; store_8 store 8 bytes to memory. 175; store_12 store 12 bytes to memory. 176; store_16 store 16 bytes (or more) to memory. 177; trap cause a trap in the kernel. 178; udiv unsigned division. 179; umaal unsigned multiply accumulate accumulate long. 180; umlal unsigned multiply accumulate long. 181; umlals unsigned multiply accumulate long, flag setting. 182; umull unsigned multiply long. 183; umulls unsigned multiply long, flag setting. 184; untyped insn without type information - default, and error, 185; case. 186; 187; The classification below is for instructions used by the Wireless MMX 188; Technology. Each attribute value is used to classify an instruction of the 189; same name or family. 190; 191; wmmx_tandc 192; wmmx_tbcst 193; wmmx_textrc 194; wmmx_textrm 195; wmmx_tinsr 196; wmmx_tmcr 197; wmmx_tmcrr 198; wmmx_tmia 199; wmmx_tmiaph 200; wmmx_tmiaxy 201; wmmx_tmrc 202; wmmx_tmrrc 203; wmmx_tmovmsk 204; wmmx_torc 205; wmmx_torvsc 206; wmmx_wabs 207; wmmx_wdiff 208; wmmx_wacc 209; wmmx_wadd 210; wmmx_waddbhus 211; wmmx_waddsubhx 212; wmmx_waligni 213; wmmx_walignr 214; wmmx_wand 215; wmmx_wandn 216; wmmx_wavg2 217; wmmx_wavg4 218; wmmx_wcmpeq 219; wmmx_wcmpgt 220; wmmx_wmac 221; wmmx_wmadd 222; wmmx_wmax 223; wmmx_wmerge 224; wmmx_wmiawxy 225; wmmx_wmiaxy 226; wmmx_wmin 227; wmmx_wmov 228; wmmx_wmul 229; wmmx_wmulw 230; wmmx_wldr 231; wmmx_wor 232; wmmx_wpack 233; wmmx_wqmiaxy 234; wmmx_wqmulm 235; wmmx_wqmulwm 236; wmmx_wror 237; wmmx_wsad 238; wmmx_wshufh 239; wmmx_wsll 240; wmmx_wsra 241; wmmx_wsrl 242; wmmx_wstr 243; wmmx_wsub 244; wmmx_wsubaddhx 245; wmmx_wunpckeh 246; wmmx_wunpckel 247; wmmx_wunpckih 248; wmmx_wunpckil 249; wmmx_wxor 250; 251; The classification below is for NEON instructions. 252; 253; neon_add 254; neon_add_q 255; neon_add_widen 256; neon_add_long 257; neon_qadd 258; neon_qadd_q 259; neon_add_halve 260; neon_add_halve_q 261; neon_add_halve_narrow_q 262; neon_sub 263; neon_sub_q 264; neon_sub_widen 265; neon_sub_long 266; neon_qsub 267; neon_qsub_q 268; neon_sub_halve 269; neon_sub_halve_q 270; neon_sub_halve_narrow_q 271; neon_abs 272; neon_abs_q 273; neon_neg 274; neon_neg_q 275; neon_qneg 276; neon_qneg_q 277; neon_qabs 278; neon_qabs_q 279; neon_abd 280; neon_abd_q 281; neon_abd_long 282; neon_minmax 283; neon_minmax_q 284; neon_compare 285; neon_compare_q 286; neon_compare_zero 287; neon_compare_zero_q 288; neon_arith_acc 289; neon_arith_acc_q 290; neon_reduc_add 291; neon_reduc_add_q 292; neon_reduc_add_long 293; neon_reduc_add_acc 294; neon_reduc_add_acc_q 295; neon_reduc_minmax 296; neon_reduc_minmax_q 297; neon_logic 298; neon_logic_q 299; neon_tst 300; neon_tst_q 301; neon_shift_imm 302; neon_shift_imm_q 303; neon_shift_imm_narrow_q 304; neon_shift_imm_long 305; neon_shift_reg 306; neon_shift_reg_q 307; neon_shift_acc 308; neon_shift_acc_q 309; neon_sat_shift_imm 310; neon_sat_shift_imm_q 311; neon_sat_shift_imm_narrow_q 312; neon_sat_shift_reg 313; neon_sat_shift_reg_q 314; neon_ins 315; neon_ins_q 316; neon_move 317; neon_move_q 318; neon_move_narrow_q 319; neon_permute 320; neon_permute_q 321; neon_zip 322; neon_zip_q 323; neon_tbl1 324; neon_tbl1_q 325; neon_tbl2 326; neon_tbl2_q 327; neon_tbl3 328; neon_tbl3_q 329; neon_tbl4 330; neon_tbl4_q 331; neon_bsl 332; neon_bsl_q 333; neon_cls 334; neon_cls_q 335; neon_cnt 336; neon_cnt_q 337; neon_dot 338; neon_dot_q 339; neon_ext 340; neon_ext_q 341; neon_rbit 342; neon_rbit_q 343; neon_rev 344; neon_rev_q 345; neon_mul_b 346; neon_mul_b_q 347; neon_mul_h 348; neon_mul_h_q 349; neon_mul_s 350; neon_mul_s_q 351; neon_mul_b_long 352; neon_mul_h_long 353; neon_mul_s_long 354; neon_mul_d_long 355; neon_mul_h_scalar 356; neon_mul_h_scalar_q 357; neon_mul_s_scalar 358; neon_mul_s_scalar_q 359; neon_mul_h_scalar_long 360; neon_mul_s_scalar_long 361; neon_sat_mul_b 362; neon_sat_mul_b_q 363; neon_sat_mul_h 364; neon_sat_mul_h_q 365; neon_sat_mul_s 366; neon_sat_mul_s_q 367; neon_sat_mul_b_long 368; neon_sat_mul_h_long 369; neon_sat_mul_s_long 370; neon_sat_mul_h_scalar 371; neon_sat_mul_h_scalar_q 372; neon_sat_mul_s_scalar 373; neon_sat_mul_s_scalar_q 374; neon_sat_mul_h_scalar_long 375; neon_sat_mul_s_scalar_long 376; neon_mla_b 377; neon_mla_b_q 378; neon_mla_h 379; neon_mla_h_q 380; neon_mla_s 381; neon_mla_s_q 382; neon_mla_b_long 383; neon_mla_h_long 384; neon_mla_s_long 385; neon_mla_h_scalar 386; neon_mla_h_scalar_q 387; neon_mla_s_scalar 388; neon_mla_s_scalar_q 389; neon_mla_h_scalar_long 390; neon_mla_s_scalar_long 391; neon_sat_mla_b_long 392; neon_sat_mla_h_long 393; neon_sat_mla_s_long 394; neon_sat_mla_h_scalar_long 395; neon_sat_mla_s_scalar_long 396; neon_to_gp 397; neon_to_gp_q 398; neon_from_gp 399; neon_from_gp_q 400; neon_ldr 401; neon_ldp 402; neon_ldp_q 403; neon_load1_1reg 404; neon_load1_1reg_q 405; neon_load1_2reg 406; neon_load1_2reg_q 407; neon_load1_3reg 408; neon_load1_3reg_q 409; neon_load1_4reg 410; neon_load1_4reg_q 411; neon_load1_all_lanes 412; neon_load1_all_lanes_q 413; neon_load1_one_lane 414; neon_load1_one_lane_q 415; neon_load2_2reg 416; neon_load2_2reg_q 417; neon_load2_4reg 418; neon_load2_4reg_q 419; neon_load2_all_lanes 420; neon_load2_all_lanes_q 421; neon_load2_one_lane 422; neon_load2_one_lane_q 423; neon_load3_3reg 424; neon_load3_3reg_q 425; neon_load3_all_lanes 426; neon_load3_all_lanes_q 427; neon_load3_one_lane 428; neon_load3_one_lane_q 429; neon_load4_4reg 430; neon_load4_4reg_q 431; neon_load4_all_lanes 432; neon_load4_all_lanes_q 433; neon_load4_one_lane 434; neon_load4_one_lane_q 435; neon_str 436; neon_stp 437; neon_stp_q 438; neon_store1_1reg 439; neon_store1_1reg_q 440; neon_store1_2reg 441; neon_store1_2reg_q 442; neon_store1_3reg 443; neon_store1_3reg_q 444; neon_store1_4reg 445; neon_store1_4reg_q 446; neon_store1_one_lane 447; neon_store1_one_lane_q 448; neon_store2_2reg 449; neon_store2_2reg_q 450; neon_store2_4reg 451; neon_store2_4reg_q 452; neon_store2_one_lane 453; neon_store2_one_lane_q 454; neon_store3_3reg 455; neon_store3_3reg_q 456; neon_store3_one_lane 457; neon_store3_one_lane_q 458; neon_store4_4reg 459; neon_store4_4reg_q 460; neon_store4_one_lane 461; neon_store4_one_lane_q 462; neon_fp_abs_s 463; neon_fp_abs_s_q 464; neon_fp_abs_d 465; neon_fp_abs_d_q 466; neon_fp_neg_s 467; neon_fp_neg_s_q 468; neon_fp_neg_d 469; neon_fp_neg_d_q 470; neon_fp_abd_s 471; neon_fp_abd_s_q 472; neon_fp_abd_d 473; neon_fp_abd_d_q 474; neon_fp_addsub_s 475; neon_fp_addsub_s_q 476; neon_fp_addsub_d 477; neon_fp_addsub_d_q 478; neon_fp_compare_s 479; neon_fp_compare_s_q 480; neon_fp_compare_d 481; neon_fp_compare_d_q 482; neon_fp_minmax_s 483; neon_fp_minmax_s_q 484; neon_fp_minmax_d 485; neon_fp_minmax_d_q 486; neon_fp_reduc_add_s 487; neon_fp_reduc_add_s_q 488; neon_fp_reduc_add_d 489; neon_fp_reduc_add_d_q 490; neon_fp_reduc_minmax_s 491; neon_fp_reduc_minmax_s_q 492; neon_fp_reduc_minmax_d 493; neon_fp_reduc_minmax_d_q 494; neon_fp_cvt_narrow_s_q 495; neon_fp_cvt_narrow_d_q 496; neon_fp_cvt_widen_h 497; neon_fp_cvt_widen_s 498; neon_fp_to_int_s 499; neon_fp_to_int_s_q 500; neon_fp_to_int_d 501; neon_fp_to_int_d_q 502; neon_int_to_fp_s 503; neon_int_to_fp_s_q 504; neon_int_to_fp_d 505; neon_int_to_fp_d_q 506; neon_fp_round_s 507; neon_fp_round_s_q 508; neon_fp_round_d 509; neon_fp_round_d_q 510; neon_fp_recpe_s 511; neon_fp_recpe_s_q 512; neon_fp_recpe_d 513; neon_fp_recpe_d_q 514; neon_fp_recps_s 515; neon_fp_recps_s_q 516; neon_fp_recps_d 517; neon_fp_recps_d_q 518; neon_fp_recpx_s 519; neon_fp_recpx_s_q 520; neon_fp_recpx_d 521; neon_fp_recpx_d_q 522; neon_fp_rsqrte_s 523; neon_fp_rsqrte_s_q 524; neon_fp_rsqrte_d 525; neon_fp_rsqrte_d_q 526; neon_fp_rsqrts_s 527; neon_fp_rsqrts_s_q 528; neon_fp_rsqrts_d 529; neon_fp_rsqrts_d_q 530; neon_fp_mul_s 531; neon_fp_mul_s_q 532; neon_fp_mul_s_scalar 533; neon_fp_mul_s_scalar_q 534; neon_fp_mul_d 535; neon_fp_mul_d_q 536; neon_fp_mul_d_scalar_q 537; neon_fp_mla_s 538; neon_fp_mla_s_q 539; neon_fp_mla_s_scalar 540; neon_fp_mla_s_scalar_q 541; neon_fp_mla_d 542; neon_fp_mla_d_q 543; neon_fp_mla_d_scalar_q 544; neon_fp_sqrt_s 545; neon_fp_sqrt_s_q 546; neon_fp_sqrt_d 547; neon_fp_sqrt_d_q 548; neon_fp_div_s 549; neon_fp_div_s_q 550; neon_fp_div_d 551; neon_fp_div_d_q 552; 553; The classification below is for Crypto instructions. 554; 555; crypto_aese 556; crypto_aesmc 557; crypto_sha1_xor 558; crypto_sha1_fast 559; crypto_sha1_slow 560; crypto_sha256_fast 561; crypto_sha256_slow 562; crypto_pmull 563; 564; The classification below is for coprocessor instructions 565; 566; coproc 567; 568; The classification below is for TME instructions 569; 570; tme 571; The classification below is for M-profile Vector Extension instructions 572; 573; mve_move 574; mve_store 575; mve_load 576 577(define_attr "type" 578 "adc_imm,\ 579 adc_reg,\ 580 adcs_imm,\ 581 adcs_reg,\ 582 adr,\ 583 alu_ext,\ 584 alu_imm,\ 585 alu_sreg,\ 586 alu_shift_imm_lsl_1to4,\ 587 alu_shift_imm_other,\ 588 alu_shift_reg,\ 589 alu_dsp_reg,\ 590 alus_ext,\ 591 alus_imm,\ 592 alus_sreg,\ 593 alus_shift_imm,\ 594 alus_shift_reg,\ 595 bfm,\ 596 bfx,\ 597 block,\ 598 branch,\ 599 call,\ 600 clz,\ 601 no_insn,\ 602 csel,\ 603 crc,\ 604 extend,\ 605 f_cvt,\ 606 f_cvtf2i,\ 607 f_cvti2f,\ 608 f_flag,\ 609 f_loadd,\ 610 f_loads,\ 611 f_mcr,\ 612 f_mcrr,\ 613 f_minmaxd,\ 614 f_minmaxs,\ 615 f_mrc,\ 616 f_mrrc,\ 617 f_rintd,\ 618 f_rints,\ 619 f_stored,\ 620 f_stores,\ 621 faddd,\ 622 fadds,\ 623 fccmpd,\ 624 fccmps,\ 625 fcmpd,\ 626 fcmps,\ 627 fconstd,\ 628 fconsts,\ 629 fcsel,\ 630 fdivd,\ 631 fdivs,\ 632 ffarithd,\ 633 ffariths,\ 634 ffmad,\ 635 ffmas,\ 636 float,\ 637 fmacd,\ 638 fmacs,\ 639 fmov,\ 640 fmuld,\ 641 fmuls,\ 642 fsqrts,\ 643 fsqrtd,\ 644 load_acq,\ 645 load_byte,\ 646 load_4,\ 647 load_8,\ 648 load_12,\ 649 load_16,\ 650 logic_imm,\ 651 logic_reg,\ 652 logic_shift_imm,\ 653 logic_shift_reg,\ 654 logics_imm,\ 655 logics_reg,\ 656 logics_shift_imm,\ 657 logics_shift_reg,\ 658 mla,\ 659 mlas,\ 660 mov_imm,\ 661 mov_reg,\ 662 mov_shift,\ 663 mov_shift_reg,\ 664 mrs,\ 665 mul,\ 666 muls,\ 667 multiple,\ 668 mvn_imm,\ 669 mvn_reg,\ 670 mvn_shift,\ 671 mvn_shift_reg,\ 672 nop,\ 673 rbit,\ 674 rev,\ 675 rotate_imm,\ 676 sdiv,\ 677 shift_imm,\ 678 shift_reg,\ 679 smlad,\ 680 smladx,\ 681 smlal,\ 682 smlald,\ 683 smlals,\ 684 smlalxy,\ 685 smlawx,\ 686 smlawy,\ 687 smlaxy,\ 688 smlsd,\ 689 smlsdx,\ 690 smlsld,\ 691 smmla,\ 692 smmul,\ 693 smmulr,\ 694 smuad,\ 695 smuadx,\ 696 smull,\ 697 smulls,\ 698 smulwy,\ 699 smulxy,\ 700 smusd,\ 701 smusdx,\ 702 store_rel,\ 703 store_4,\ 704 store_8,\ 705 store_12,\ 706 store_16,\ 707 trap,\ 708 udiv,\ 709 umaal,\ 710 umlal,\ 711 umlals,\ 712 umull,\ 713 umulls,\ 714 untyped,\ 715 wmmx_tandc,\ 716 wmmx_tbcst,\ 717 wmmx_textrc,\ 718 wmmx_textrm,\ 719 wmmx_tinsr,\ 720 wmmx_tmcr,\ 721 wmmx_tmcrr,\ 722 wmmx_tmia,\ 723 wmmx_tmiaph,\ 724 wmmx_tmiaxy,\ 725 wmmx_tmrc,\ 726 wmmx_tmrrc,\ 727 wmmx_tmovmsk,\ 728 wmmx_torc,\ 729 wmmx_torvsc,\ 730 wmmx_wabs,\ 731 wmmx_wabsdiff,\ 732 wmmx_wacc,\ 733 wmmx_wadd,\ 734 wmmx_waddbhus,\ 735 wmmx_waddsubhx,\ 736 wmmx_waligni,\ 737 wmmx_walignr,\ 738 wmmx_wand,\ 739 wmmx_wandn,\ 740 wmmx_wavg2,\ 741 wmmx_wavg4,\ 742 wmmx_wcmpeq,\ 743 wmmx_wcmpgt,\ 744 wmmx_wmac,\ 745 wmmx_wmadd,\ 746 wmmx_wmax,\ 747 wmmx_wmerge,\ 748 wmmx_wmiawxy,\ 749 wmmx_wmiaxy,\ 750 wmmx_wmin,\ 751 wmmx_wmov,\ 752 wmmx_wmul,\ 753 wmmx_wmulw,\ 754 wmmx_wldr,\ 755 wmmx_wor,\ 756 wmmx_wpack,\ 757 wmmx_wqmiaxy,\ 758 wmmx_wqmulm,\ 759 wmmx_wqmulwm,\ 760 wmmx_wror,\ 761 wmmx_wsad,\ 762 wmmx_wshufh,\ 763 wmmx_wsll,\ 764 wmmx_wsra,\ 765 wmmx_wsrl,\ 766 wmmx_wstr,\ 767 wmmx_wsub,\ 768 wmmx_wsubaddhx,\ 769 wmmx_wunpckeh,\ 770 wmmx_wunpckel,\ 771 wmmx_wunpckih,\ 772 wmmx_wunpckil,\ 773 wmmx_wxor,\ 774\ 775 neon_add,\ 776 neon_add_q,\ 777 neon_add_widen,\ 778 neon_add_long,\ 779 neon_qadd,\ 780 neon_qadd_q,\ 781 neon_add_halve,\ 782 neon_add_halve_q,\ 783 neon_add_halve_narrow_q,\ 784\ 785 neon_sub,\ 786 neon_sub_q,\ 787 neon_sub_widen,\ 788 neon_sub_long,\ 789 neon_qsub,\ 790 neon_qsub_q,\ 791 neon_sub_halve,\ 792 neon_sub_halve_q,\ 793 neon_sub_halve_narrow_q,\ 794\ 795 neon_fcadd,\ 796 neon_fcmla,\ 797\ 798 neon_abs,\ 799 neon_abs_q,\ 800 neon_dot,\ 801 neon_dot_q,\ 802 neon_neg,\ 803 neon_neg_q,\ 804 neon_qneg,\ 805 neon_qneg_q,\ 806 neon_qabs,\ 807 neon_qabs_q,\ 808 neon_abd,\ 809 neon_abd_q,\ 810 neon_abd_long,\ 811\ 812 neon_minmax,\ 813 neon_minmax_q,\ 814 neon_compare,\ 815 neon_compare_q,\ 816 neon_compare_zero,\ 817 neon_compare_zero_q,\ 818\ 819 neon_arith_acc,\ 820 neon_arith_acc_q,\ 821 neon_reduc_add,\ 822 neon_reduc_add_q,\ 823 neon_reduc_add_long,\ 824 neon_reduc_add_acc,\ 825 neon_reduc_add_acc_q,\ 826 neon_reduc_minmax,\ 827 neon_reduc_minmax_q,\ 828 neon_logic,\ 829 neon_logic_q,\ 830 neon_tst,\ 831 neon_tst_q,\ 832\ 833 neon_shift_imm,\ 834 neon_shift_imm_q,\ 835 neon_shift_imm_narrow_q,\ 836 neon_shift_imm_long,\ 837 neon_shift_reg,\ 838 neon_shift_reg_q,\ 839 neon_shift_acc,\ 840 neon_shift_acc_q,\ 841 neon_sat_shift_imm,\ 842 neon_sat_shift_imm_q,\ 843 neon_sat_shift_imm_narrow_q,\ 844 neon_sat_shift_reg,\ 845 neon_sat_shift_reg_q,\ 846\ 847 neon_ins,\ 848 neon_ins_q,\ 849 neon_move,\ 850 neon_move_q,\ 851 neon_move_narrow_q,\ 852 neon_permute,\ 853 neon_permute_q,\ 854 neon_zip,\ 855 neon_zip_q,\ 856 neon_tbl1,\ 857 neon_tbl1_q,\ 858 neon_tbl2,\ 859 neon_tbl2_q,\ 860 neon_tbl3,\ 861 neon_tbl3_q,\ 862 neon_tbl4,\ 863 neon_tbl4_q,\ 864\ 865 neon_bsl,\ 866 neon_bsl_q,\ 867 neon_cls,\ 868 neon_cls_q,\ 869 neon_cnt,\ 870 neon_cnt_q,\ 871 neon_dup,\ 872 neon_dup_q,\ 873 neon_ext,\ 874 neon_ext_q,\ 875 neon_rbit,\ 876 neon_rbit_q,\ 877 neon_rev,\ 878 neon_rev_q,\ 879\ 880 neon_mul_b,\ 881 neon_mul_b_q,\ 882 neon_mul_h,\ 883 neon_mul_h_q,\ 884 neon_mul_s,\ 885 neon_mul_s_q,\ 886 neon_mul_b_long,\ 887 neon_mul_h_long,\ 888 neon_mul_s_long,\ 889 neon_mul_d_long,\ 890 neon_mul_h_scalar,\ 891 neon_mul_h_scalar_q,\ 892 neon_mul_s_scalar,\ 893 neon_mul_s_scalar_q,\ 894 neon_mul_h_scalar_long,\ 895 neon_mul_s_scalar_long,\ 896\ 897 neon_sat_mul_b,\ 898 neon_sat_mul_b_q,\ 899 neon_sat_mul_h,\ 900 neon_sat_mul_h_q,\ 901 neon_sat_mul_s,\ 902 neon_sat_mul_s_q,\ 903 neon_sat_mul_b_long,\ 904 neon_sat_mul_h_long,\ 905 neon_sat_mul_s_long,\ 906 neon_sat_mul_h_scalar,\ 907 neon_sat_mul_h_scalar_q,\ 908 neon_sat_mul_s_scalar,\ 909 neon_sat_mul_s_scalar_q,\ 910 neon_sat_mul_h_scalar_long,\ 911 neon_sat_mul_s_scalar_long,\ 912\ 913 neon_mla_b,\ 914 neon_mla_b_q,\ 915 neon_mla_h,\ 916 neon_mla_h_q,\ 917 neon_mla_s,\ 918 neon_mla_s_q,\ 919 neon_mla_b_long,\ 920 neon_mla_h_long,\ 921 neon_mla_s_long,\ 922 neon_mla_h_scalar,\ 923 neon_mla_h_scalar_q,\ 924 neon_mla_s_scalar,\ 925 neon_mla_s_scalar_q,\ 926 neon_mla_h_scalar_long,\ 927 neon_mla_s_scalar_long,\ 928\ 929 neon_sat_mla_b_long,\ 930 neon_sat_mla_h_long,\ 931 neon_sat_mla_s_long,\ 932 neon_sat_mla_h_scalar_long,\ 933 neon_sat_mla_s_scalar_long,\ 934\ 935 neon_to_gp,\ 936 neon_to_gp_q,\ 937 neon_from_gp,\ 938 neon_from_gp_q,\ 939\ 940 neon_ldr,\ 941 neon_ldp,\ 942 neon_ldp_q,\ 943 neon_load1_1reg,\ 944 neon_load1_1reg_q,\ 945 neon_load1_2reg,\ 946 neon_load1_2reg_q,\ 947 neon_load1_3reg,\ 948 neon_load1_3reg_q,\ 949 neon_load1_4reg,\ 950 neon_load1_4reg_q,\ 951 neon_load1_all_lanes,\ 952 neon_load1_all_lanes_q,\ 953 neon_load1_one_lane,\ 954 neon_load1_one_lane_q,\ 955\ 956 neon_load2_2reg,\ 957 neon_load2_2reg_q,\ 958 neon_load2_4reg,\ 959 neon_load2_4reg_q,\ 960 neon_load2_all_lanes,\ 961 neon_load2_all_lanes_q,\ 962 neon_load2_one_lane,\ 963 neon_load2_one_lane_q,\ 964\ 965 neon_load3_3reg,\ 966 neon_load3_3reg_q,\ 967 neon_load3_all_lanes,\ 968 neon_load3_all_lanes_q,\ 969 neon_load3_one_lane,\ 970 neon_load3_one_lane_q,\ 971\ 972 neon_load4_4reg,\ 973 neon_load4_4reg_q,\ 974 neon_load4_all_lanes,\ 975 neon_load4_all_lanes_q,\ 976 neon_load4_one_lane,\ 977 neon_load4_one_lane_q,\ 978\ 979 neon_str,\ 980 neon_stp,\ 981 neon_stp_q,\ 982 neon_store1_1reg,\ 983 neon_store1_1reg_q,\ 984 neon_store1_2reg,\ 985 neon_store1_2reg_q,\ 986 neon_store1_3reg,\ 987 neon_store1_3reg_q,\ 988 neon_store1_4reg,\ 989 neon_store1_4reg_q,\ 990 neon_store1_one_lane,\ 991 neon_store1_one_lane_q,\ 992\ 993 neon_store2_2reg,\ 994 neon_store2_2reg_q,\ 995 neon_store2_4reg,\ 996 neon_store2_4reg_q,\ 997 neon_store2_one_lane,\ 998 neon_store2_one_lane_q,\ 999\ 1000 neon_store3_3reg,\ 1001 neon_store3_3reg_q,\ 1002 neon_store3_one_lane,\ 1003 neon_store3_one_lane_q,\ 1004\ 1005 neon_store4_4reg,\ 1006 neon_store4_4reg_q,\ 1007 neon_store4_one_lane,\ 1008 neon_store4_one_lane_q,\ 1009\ 1010 neon_fp_abs_s,\ 1011 neon_fp_abs_s_q,\ 1012 neon_fp_abs_d,\ 1013 neon_fp_abs_d_q,\ 1014 neon_fp_neg_s,\ 1015 neon_fp_neg_s_q,\ 1016 neon_fp_neg_d,\ 1017 neon_fp_neg_d_q,\ 1018\ 1019 neon_fp_abd_s,\ 1020 neon_fp_abd_s_q,\ 1021 neon_fp_abd_d,\ 1022 neon_fp_abd_d_q,\ 1023 neon_fp_addsub_s,\ 1024 neon_fp_addsub_s_q,\ 1025 neon_fp_addsub_d,\ 1026 neon_fp_addsub_d_q,\ 1027 neon_fp_compare_s,\ 1028 neon_fp_compare_s_q,\ 1029 neon_fp_compare_d,\ 1030 neon_fp_compare_d_q,\ 1031 neon_fp_minmax_s,\ 1032 neon_fp_minmax_s_q,\ 1033 neon_fp_minmax_d,\ 1034 neon_fp_minmax_d_q,\ 1035\ 1036 neon_fp_reduc_add_s,\ 1037 neon_fp_reduc_add_s_q,\ 1038 neon_fp_reduc_add_d,\ 1039 neon_fp_reduc_add_d_q,\ 1040 neon_fp_reduc_minmax_s,\ 1041 neon_fp_reduc_minmax_s_q,\ 1042 neon_fp_reduc_minmax_d,\ 1043 neon_fp_reduc_minmax_d_q,\ 1044\ 1045 neon_fp_cvt_narrow_s_q,\ 1046 neon_fp_cvt_narrow_d_q,\ 1047 neon_fp_cvt_widen_h,\ 1048 neon_fp_cvt_widen_s,\ 1049\ 1050 neon_fp_to_int_s,\ 1051 neon_fp_to_int_s_q,\ 1052 neon_fp_to_int_d,\ 1053 neon_fp_to_int_d_q,\ 1054 neon_int_to_fp_s,\ 1055 neon_int_to_fp_s_q,\ 1056 neon_int_to_fp_d,\ 1057 neon_int_to_fp_d_q,\ 1058 neon_fp_round_s,\ 1059 neon_fp_round_s_q,\ 1060 neon_fp_round_d,\ 1061 neon_fp_round_d_q,\ 1062\ 1063 neon_fp_recpe_s,\ 1064 neon_fp_recpe_s_q,\ 1065 neon_fp_recpe_d,\ 1066 neon_fp_recpe_d_q,\ 1067 neon_fp_recps_s,\ 1068 neon_fp_recps_s_q,\ 1069 neon_fp_recps_d,\ 1070 neon_fp_recps_d_q,\ 1071 neon_fp_recpx_s,\ 1072 neon_fp_recpx_s_q,\ 1073 neon_fp_recpx_d,\ 1074 neon_fp_recpx_d_q,\ 1075\ 1076 neon_fp_rsqrte_s,\ 1077 neon_fp_rsqrte_s_q,\ 1078 neon_fp_rsqrte_d,\ 1079 neon_fp_rsqrte_d_q,\ 1080 neon_fp_rsqrts_s,\ 1081 neon_fp_rsqrts_s_q,\ 1082 neon_fp_rsqrts_d,\ 1083 neon_fp_rsqrts_d_q,\ 1084\ 1085 neon_fp_mul_s,\ 1086 neon_fp_mul_s_q,\ 1087 neon_fp_mul_s_scalar,\ 1088 neon_fp_mul_s_scalar_q,\ 1089 neon_fp_mul_d,\ 1090 neon_fp_mul_d_q,\ 1091 neon_fp_mul_d_scalar_q,\ 1092\ 1093 neon_fp_mla_s,\ 1094 neon_fp_mla_s_q,\ 1095 neon_fp_mla_s_scalar,\ 1096 neon_fp_mla_s_scalar_q,\ 1097 neon_fp_mla_d,\ 1098 neon_fp_mla_d_q,\ 1099 neon_fp_mla_d_scalar_q,\ 1100\ 1101 neon_fp_sqrt_s,\ 1102 neon_fp_sqrt_s_q,\ 1103 neon_fp_sqrt_d,\ 1104 neon_fp_sqrt_d_q,\ 1105 neon_fp_div_s,\ 1106 neon_fp_div_s_q,\ 1107 neon_fp_div_d,\ 1108 neon_fp_div_d_q,\ 1109\ 1110 crypto_aese,\ 1111 crypto_aesmc,\ 1112 crypto_sha1_xor,\ 1113 crypto_sha1_fast,\ 1114 crypto_sha1_slow,\ 1115 crypto_sha256_fast,\ 1116 crypto_sha256_slow,\ 1117 crypto_pmull,\ 1118 crypto_sha512,\ 1119 crypto_sha3,\ 1120 crypto_sm3,\ 1121 crypto_sm4,\ 1122 coproc,\ 1123 tme,\ 1124 memtag,\ 1125 mve_move,\ 1126 mve_store,\ 1127 mve_load" 1128 (cond [(eq_attr "autodetect_type" "alu_shift_lsr_op2,alu_shift_asr_op2") 1129 (const_string "alu_shift_imm_other") 1130 (eq_attr "autodetect_type" "alu_shift_lsl_op2") 1131 (if_then_else (match_operand 2 "const_1_to_4_operand") 1132 (const_string "alu_shift_imm_lsl_1to4") 1133 (const_string "alu_shift_imm_other")) 1134 (eq_attr "autodetect_type" "alu_shift_mul_op3") 1135 (if_then_else (match_operand 3 "const_2_4_8_16_operand") 1136 (const_string "alu_shift_imm_lsl_1to4") 1137 (const_string "alu_shift_imm_other")) 1138 (eq_attr "autodetect_type" "alu_shift_operator1") 1139 (if_then_else (match_operand 1 "alu_shift_reg_p") 1140 (const_string "alu_shift_reg") 1141 (if_then_else (match_operand 1 "alu_shift_operator_lsl_1_to_4") 1142 (const_string "alu_shift_imm_lsl_1to4") 1143 (const_string "alu_shift_imm_other"))) 1144 (eq_attr "autodetect_type" "alu_shift_operator2") 1145 (if_then_else (match_operand 2 "alu_shift_reg_p") 1146 (const_string "alu_shift_reg") 1147 (if_then_else (match_operand 2 "alu_shift_operator_lsl_1_to_4") 1148 (const_string "alu_shift_imm_lsl_1to4") 1149 (const_string "alu_shift_imm_other"))) 1150 (eq_attr "autodetect_type" "alu_shift_operator3") 1151 (if_then_else (match_operand 3 "alu_shift_reg_p") 1152 (const_string "alu_shift_reg") 1153 (if_then_else (match_operand 3 "alu_shift_operator_lsl_1_to_4") 1154 (const_string "alu_shift_imm_lsl_1to4") 1155 (const_string "alu_shift_imm_other"))) 1156 (eq_attr "autodetect_type" "alu_shift_operator4") 1157 (if_then_else (match_operand 4 "alu_shift_reg_p") 1158 (const_string "alu_shift_reg") 1159 (if_then_else (match_operand 4 "alu_shift_operator_lsl_1_to_4") 1160 (const_string "alu_shift_imm_lsl_1to4") 1161 (const_string "alu_shift_imm_other"))) 1162 ] 1163 (const_string "untyped"))) 1164 1165 1166; Is this an (integer side) multiply with a 32-bit (or smaller) result? 1167(define_attr "mul32" "no,yes" 1168 (if_then_else 1169 (eq_attr "type" 1170 "smulxy,smlaxy,smulwy,smlawx,mul,muls,mla,mlas,smlawy,smuad,smuadx,\ 1171 smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,smlald,smlsld") 1172 (const_string "yes") 1173 (const_string "no"))) 1174 1175; Is this an (integer side) widening multiply with a 64-bit result? 1176(define_attr "widen_mul64" "no,yes" 1177 (if_then_else 1178 (eq_attr "type" 1179 "smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals") 1180 (const_string "yes") 1181 (const_string "no"))) 1182 1183; YES if the "type" attribute assigned to the insn denotes an 1184; Advanced SIMD instruction, NO otherwise. 1185(define_attr "is_neon_type" "yes,no" 1186 (if_then_else (eq_attr "type" 1187 "neon_add, neon_add_q, neon_add_widen, neon_add_long,\ 1188 neon_qadd, neon_qadd_q, neon_add_halve, neon_add_halve_q,\ 1189 neon_add_halve_narrow_q,\ 1190 neon_sub, neon_sub_q, neon_sub_widen, neon_sub_long, neon_qsub,\ 1191 neon_qsub_q, neon_sub_halve, neon_sub_halve_q,\ 1192 neon_sub_halve_narrow_q,\ 1193 neon_abs, neon_abs_q, neon_dot, neon_dot_q, neon_neg, neon_neg_q,\ 1194 neon_qneg, neon_qneg_q, neon_qabs, neon_qabs_q, neon_abd, neon_abd_q,\ 1195 neon_abd_long, neon_minmax, neon_minmax_q, neon_compare,\ 1196 neon_compare_q, neon_compare_zero, neon_compare_zero_q,\ 1197 neon_arith_acc, neon_arith_acc_q, neon_reduc_add,\ 1198 neon_reduc_add_q, neon_reduc_add_long, neon_reduc_add_acc,\ 1199 neon_reduc_add_acc_q, neon_reduc_minmax, neon_reduc_minmax_q,\ 1200 neon_logic, neon_logic_q, neon_tst, neon_tst_q,\ 1201 neon_shift_imm, neon_shift_imm_q, neon_shift_imm_narrow_q,\ 1202 neon_shift_imm_long, neon_shift_reg, neon_shift_reg_q,\ 1203 neon_shift_acc, neon_shift_acc_q, neon_sat_shift_imm,\ 1204 neon_sat_shift_imm_q, neon_sat_shift_imm_narrow_q,\ 1205 neon_sat_shift_reg, neon_sat_shift_reg_q,\ 1206 neon_ins, neon_ins_q, neon_move, neon_move_q, neon_move_narrow_q,\ 1207 neon_permute, neon_permute_q, neon_zip, neon_zip_q, neon_tbl1,\ 1208 neon_tbl1_q, neon_tbl2, neon_tbl2_q, neon_tbl3, neon_tbl3_q,\ 1209 neon_tbl4, neon_tbl4_q, neon_bsl, neon_bsl_q, neon_cls,\ 1210 neon_cls_q, neon_cnt, neon_cnt_q, neon_dup, neon_dup_q,\ 1211 neon_ext, neon_ext_q, neon_rbit, neon_rbit_q,\ 1212 neon_rev, neon_rev_q, neon_mul_b, neon_mul_b_q, neon_mul_h,\ 1213 neon_mul_h_q, neon_mul_s, neon_mul_s_q, neon_mul_b_long,\ 1214 neon_mul_h_long, neon_mul_s_long, neon_mul_d_long, neon_mul_h_scalar,\ 1215 neon_mul_h_scalar_q, neon_mul_s_scalar, neon_mul_s_scalar_q,\ 1216 neon_mul_h_scalar_long, neon_mul_s_scalar_long, neon_sat_mul_b,\ 1217 neon_sat_mul_b_q, neon_sat_mul_h, neon_sat_mul_h_q,\ 1218 neon_sat_mul_s, neon_sat_mul_s_q, neon_sat_mul_b_long,\ 1219 neon_sat_mul_h_long, neon_sat_mul_s_long, neon_sat_mul_h_scalar,\ 1220 neon_sat_mul_h_scalar_q, neon_sat_mul_s_scalar,\ 1221 neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\ 1222 neon_sat_mul_s_scalar_long, neon_mla_b, neon_mla_b_q, neon_mla_h,\ 1223 neon_mla_h_q, neon_mla_s, neon_mla_s_q, neon_mla_b_long,\ 1224 neon_mla_h_long, neon_mla_s_long, neon_mla_h_scalar,\ 1225 neon_mla_h_scalar_q, neon_mla_s_scalar, neon_mla_s_scalar_q,\ 1226 neon_mla_h_scalar_long, neon_mla_s_scalar_long,\ 1227 neon_sat_mla_b_long, neon_sat_mla_h_long,\ 1228 neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\ 1229 neon_sat_mla_s_scalar_long,\ 1230 neon_to_gp, neon_to_gp_q, neon_from_gp, neon_from_gp_q,\ 1231 neon_ldr, neon_ldp, neon_ldp_q,\ 1232 neon_load1_1reg, neon_load1_1reg_q, neon_load1_2reg,\ 1233 neon_load1_2reg_q, neon_load1_3reg, neon_load1_3reg_q,\ 1234 neon_load1_4reg, neon_load1_4reg_q, neon_load1_all_lanes,\ 1235 neon_load1_all_lanes_q, neon_load1_one_lane, neon_load1_one_lane_q,\ 1236 neon_load2_2reg, neon_load2_2reg_q, neon_load2_4reg,\ 1237 neon_load2_4reg_q, neon_load2_all_lanes, neon_load2_all_lanes_q,\ 1238 neon_load2_one_lane, neon_load2_one_lane_q,\ 1239 neon_load3_3reg, neon_load3_3reg_q, neon_load3_all_lanes,\ 1240 neon_load3_all_lanes_q, neon_load3_one_lane, neon_load3_one_lane_q,\ 1241 neon_load4_4reg, neon_load4_4reg_q, neon_load4_all_lanes,\ 1242 neon_load4_all_lanes_q, neon_load4_one_lane, neon_load4_one_lane_q,\ 1243 neon_str, neon_stp, neon_stp_q,\ 1244 neon_store1_1reg, neon_store1_1reg_q, neon_store1_2reg,\ 1245 neon_store1_2reg_q, neon_store1_3reg, neon_store1_3reg_q,\ 1246 neon_store1_4reg, neon_store1_4reg_q, neon_store1_one_lane,\ 1247 neon_store1_one_lane_q, neon_store2_2reg, neon_store2_2reg_q,\ 1248 neon_store2_4reg, neon_store2_4reg_q, neon_store2_one_lane,\ 1249 neon_store2_one_lane_q, neon_store3_3reg, neon_store3_3reg_q,\ 1250 neon_store3_one_lane, neon_store3_one_lane_q, neon_store4_4reg,\ 1251 neon_store4_4reg_q, neon_store4_one_lane, neon_store4_one_lane_q,\ 1252 neon_fp_abd_s, neon_fp_abd_s_q, neon_fp_abd_d, neon_fp_abd_d_q,\ 1253 neon_fp_abs_s, neon_fp_abs_s_q, neon_fp_abs_d, neon_fp_abs_d_q,\ 1254 neon_fp_addsub_s, neon_fp_addsub_s_q, neon_fp_addsub_d,\ 1255 neon_fp_addsub_d_q, neon_fp_compare_s, neon_fp_compare_s_q,\ 1256 neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\ 1257 neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\ 1258 neon_fp_neg_s, neon_fp_neg_s_q, neon_fp_neg_d, neon_fp_neg_d_q,\ 1259 neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\ 1260 neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s, 1261 neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\ 1262 neon_fp_reduc_minmax_d_q,\ 1263 neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\ 1264 neon_fp_cvt_widen_h, neon_fp_cvt_widen_s, neon_fp_to_int_s,\ 1265 neon_fp_to_int_s_q, neon_int_to_fp_s, neon_int_to_fp_s_q,\ 1266 neon_fp_to_int_d, neon_fp_to_int_d_q,\ 1267 neon_int_to_fp_d, neon_int_to_fp_d_q,\ 1268 neon_fp_round_s, neon_fp_round_s_q, neon_fp_recpe_s,\ 1269 neon_fp_recpe_s_q,\ 1270 neon_fp_recpe_d, neon_fp_recpe_d_q, neon_fp_recps_s,\ 1271 neon_fp_recps_s_q, neon_fp_recps_d, neon_fp_recps_d_q,\ 1272 neon_fp_recpx_s, neon_fp_recpx_s_q, neon_fp_recpx_d,\ 1273 neon_fp_recpx_d_q, neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\ 1274 neon_fp_rsqrte_d, neon_fp_rsqrte_d_q, neon_fp_rsqrts_s,\ 1275 neon_fp_rsqrts_s_q, neon_fp_rsqrts_d, neon_fp_rsqrts_d_q,\ 1276 neon_fp_mul_s, neon_fp_mul_s_q, neon_fp_mul_s_scalar,\ 1277 neon_fp_mul_s_scalar_q, neon_fp_mul_d, neon_fp_mul_d_q,\ 1278 neon_fp_mul_d_scalar_q, neon_fp_mla_s, neon_fp_mla_s_q,\ 1279 neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q, neon_fp_mla_d,\ 1280 neon_fp_mla_d_q, neon_fp_mla_d_scalar_q, neon_fp_sqrt_s,\ 1281 neon_fp_sqrt_s_q, neon_fp_sqrt_d, neon_fp_sqrt_d_q,\ 1282 neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q, crypto_aese,\ 1283 crypto_aesmc, crypto_sha1_xor, crypto_sha1_fast, crypto_sha1_slow,\ 1284 crypto_sha256_fast, crypto_sha256_slow") 1285 (const_string "yes") 1286 (const_string "no"))) 1287 1288;; YES if the "type" attribute assigned to the insn denotes an MVE instruction, 1289;; No otherwise. 1290(define_attr "is_mve_type" "yes,no" 1291 (if_then_else (eq_attr "type" 1292 "mve_move, mve_load, mve_store, mrs") 1293 (const_string "yes") 1294 (const_string "no"))) 1295 1296(define_insn_reservation "no_reservation" 0 1297 (eq_attr "type" "no_insn") 1298 "nothing") 1299