1;; Constraint definitions for RS6000 2;; Copyright (C) 2006-2013 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Available constraint letters: "e", "k", "q", "u", "A", "B", "C", "D" 21 22;; Register constraints 23 24(define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]" 25 "@internal") 26 27(define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]" 28 "@internal") 29 30(define_register_constraint "b" "BASE_REGS" 31 "@internal") 32 33(define_register_constraint "h" "SPECIAL_REGS" 34 "@internal") 35 36(define_register_constraint "c" "CTR_REGS" 37 "@internal") 38 39(define_register_constraint "l" "LINK_REGS" 40 "@internal") 41 42(define_register_constraint "v" "ALTIVEC_REGS" 43 "@internal") 44 45(define_register_constraint "x" "CR0_REGS" 46 "@internal") 47 48(define_register_constraint "y" "CR_REGS" 49 "@internal") 50 51(define_register_constraint "z" "CA_REGS" 52 "@internal") 53 54;; Use w as a prefix to add VSX modes 55;; any VSX register 56(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 57 "Any VSX register if the -mvsx option was used or NO_REGS.") 58 59(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]" 60 "VSX vector register to hold vector double data or NO_REGS.") 61 62(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" 63 "VSX vector register to hold vector float data or NO_REGS.") 64 65(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" 66 "If -mmfpgpr was used, a floating point register or NO_REGS.") 67 68(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]" 69 "Floating point register if direct moves are available, or NO_REGS.") 70 71;; At present, DImode is not allowed in the Altivec registers. If in the 72;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS. 73(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" 74 "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") 75 76(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]" 77 "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.") 78 79(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]" 80 "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.") 81 82(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" 83 "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") 84 85(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]" 86 "VSX register if direct move instructions are enabled, or NO_REGS.") 87 88;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use 89;; direct move directly, and movsf can't to move between the register sets. 90;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode 91(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).") 92 93(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]" 94 "General purpose register if 64-bit instructions are enabled or NO_REGS.") 95 96(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]" 97 "VSX vector register to hold scalar double values or NO_REGS.") 98 99(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]" 100 "VSX vector register to hold 128 bit integer or NO_REGS.") 101 102(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]" 103 "Altivec register to use for float/32-bit int loads/stores or NO_REGS.") 104 105(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]" 106 "Altivec register to use for double loads/stores or NO_REGS.") 107 108(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]" 109 "FP or VSX register to perform float operations under -mvsx or NO_REGS.") 110 111(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]" 112 "Floating point register if the STFIWX instruction is enabled or NO_REGS.") 113 114(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]" 115 "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.") 116 117(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" 118 "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") 119 120;; Lq/stq validates the address for load/store quad 121(define_memory_constraint "wQ" 122 "Memory operand suitable for the load/store quad instructions" 123 (match_operand 0 "quad_memory_operand")) 124 125;; Altivec style load/store that ignores the bottom bits of the address 126(define_memory_constraint "wZ" 127 "Indexed or indirect memory operand, ignoring the bottom 4 bits" 128 (match_operand 0 "altivec_indexed_or_indirect_operand")) 129 130;; Integer constraints 131 132(define_constraint "I" 133 "A signed 16-bit constant" 134 (and (match_code "const_int") 135 (match_test "(unsigned HOST_WIDE_INT) (ival + 0x8000) < 0x10000"))) 136 137(define_constraint "J" 138 "high-order 16 bits nonzero" 139 (and (match_code "const_int") 140 (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0"))) 141 142(define_constraint "K" 143 "low-order 16 bits nonzero" 144 (and (match_code "const_int") 145 (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0"))) 146 147(define_constraint "L" 148 "signed 16-bit constant shifted left 16 bits" 149 (and (match_code "const_int") 150 (match_test "((ival & 0xffff) == 0 151 && (ival >> 31 == -1 || ival >> 31 == 0))"))) 152 153(define_constraint "M" 154 "constant greater than 31" 155 (and (match_code "const_int") 156 (match_test "ival > 31"))) 157 158(define_constraint "N" 159 "positive constant that is an exact power of two" 160 (and (match_code "const_int") 161 (match_test "ival > 0 && exact_log2 (ival) >= 0"))) 162 163(define_constraint "O" 164 "constant zero" 165 (and (match_code "const_int") 166 (match_test "ival == 0"))) 167 168(define_constraint "P" 169 "constant whose negation is signed 16-bit constant" 170 (and (match_code "const_int") 171 (match_test "(unsigned HOST_WIDE_INT) ((- ival) + 0x8000) < 0x10000"))) 172 173;; Floating-point constraints 174 175(define_constraint "G" 176 "Constant that can be copied into GPR with two insns for DF/DI 177 and one for SF." 178 (and (match_code "const_double") 179 (match_test "num_insns_constant (op, mode) 180 == (mode == SFmode ? 1 : 2)"))) 181 182(define_constraint "H" 183 "DF/DI constant that takes three insns." 184 (and (match_code "const_double") 185 (match_test "num_insns_constant (op, mode) == 3"))) 186 187;; Memory constraints 188 189(define_memory_constraint "es" 190 "A ``stable'' memory operand; that is, one which does not include any 191automodification of the base register. Unlike @samp{m}, this constraint 192can be used in @code{asm} statements that might access the operand 193several times, or that might not access it at all." 194 (and (match_code "mem") 195 (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC"))) 196 197(define_memory_constraint "Q" 198 "Memory operand that is an offset from a register (it is usually better 199to use @samp{m} or @samp{es} in @code{asm} statements)" 200 (and (match_code "mem") 201 (match_test "GET_CODE (XEXP (op, 0)) == REG"))) 202 203(define_memory_constraint "Y" 204 "memory operand for 8 byte and 16 byte gpr load/store" 205 (and (match_code "mem") 206 (match_operand 0 "mem_operand_gpr"))) 207 208(define_memory_constraint "Z" 209 "Memory operand that is an indexed or indirect from a register (it is 210usually better to use @samp{m} or @samp{es} in @code{asm} statements)" 211 (match_operand 0 "indexed_or_indirect_operand")) 212 213;; Address constraints 214 215(define_address_constraint "a" 216 "Indexed or indirect address operand" 217 (match_operand 0 "indexed_or_indirect_address")) 218 219(define_constraint "R" 220 "AIX TOC entry" 221 (match_test "legitimate_constant_pool_address_p (op, QImode, false)")) 222 223;; General constraints 224 225(define_constraint "S" 226 "Constant that can be placed into a 64-bit mask operand" 227 (match_operand 0 "mask64_operand")) 228 229(define_constraint "T" 230 "Constant that can be placed into a 32-bit mask operand" 231 (match_operand 0 "mask_operand")) 232 233(define_constraint "U" 234 "V.4 small data reference" 235 (and (match_test "DEFAULT_ABI == ABI_V4") 236 (match_operand 0 "small_data_operand"))) 237 238(define_constraint "t" 239 "AND masks that can be performed by two rldic{l,r} insns 240 (but excluding those that could match other constraints of anddi3)" 241 (and (and (and (match_operand 0 "mask64_2_operand") 242 (match_test "(fixed_regs[CR0_REGNO] 243 || !logical_operand (op, DImode))")) 244 (not (match_operand 0 "mask_operand"))) 245 (not (match_operand 0 "mask64_operand")))) 246 247(define_constraint "W" 248 "vector constant that does not require memory" 249 (match_operand 0 "easy_vector_constant")) 250 251(define_constraint "j" 252 "Zero vector constant" 253 (match_test "op == const0_rtx || op == CONST0_RTX (GET_MODE (op))")) 254