1;; Constraint definitions for Renesas / SuperH SH. 2;; Copyright (C) 2007-2016 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Overview of uppercase letter constraints: 21;; Axx: atomic memory operand constraints 22;; Ara: Same as Sra but disallows r15 23;; Add: Same as Sdd but disallows r15 24;; Bxx: miscellaneous constraints 25;; Bsc: SCRATCH - for the scratch register in movsi_ie in the 26;; fldi0 / fldi0 cases 27;; Cxx: Constants other than only CONST_INT 28;; Ccl: call site label 29;; Css: signed 16-bit constant, literal or symbolic 30;; Csu: unsigned 16-bit constant, literal or symbolic 31;; Csy: label or symbol 32;; Cpg: non-explicit constants that can be directly loaded into a general 33;; purpose register in PIC code. Like 's' except we don't allow 34;; PIC_ADDR_P 35;; IJKLMNOP: CONT_INT constants 36;; Ixx: signed xx bit 37;; J16: 0xffffffff00000000 | 0x00000000ffffffff 38;; Jmb: 0x000000FF 39;; Jmw: 0x0000FFFF 40;; Jhb: 0x80000000 41;; Kxx: unsigned xx bit 42;; M: 1 43;; N: 0 44;; P27: 1 | 2 | 8 | 16 45;; Pso: 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 46;; Psz: ~1 | ~2 | ~4 | ~8 | ~16 | ~32 | ~64 | ~128 47;; G: Floating point 0 48;; H: Floating point 1 49;; Q: pc relative load operand 50;; Rxx: reserved for exotic register classes. 51;; Sxx: extra memory constraints 52;; Sua: unaligned memory address 53;; Sbv: QImode address without displacement 54;; Sbw: QImode address with 12 bit displacement 55;; Snd: address without displacement 56;; Sdd: address with displacement 57;; Sra: simple register address 58;; W: vector 59;; Z: zero in any mode 60;; 61;; unused CONST_INT constraint letters: LO 62;; unused "extra" constraint letters: D T U Y 63 64;; Register constraints 65(define_register_constraint "a" "ALL_REGS" 66 "@internal") 67 68(define_register_constraint "b" "TARGET_REGS" 69 "Branch target registers.") 70 71(define_register_constraint "c" "FPSCR_REGS" 72 "Floating-point status register.") 73 74(define_register_constraint "d" "DF_REGS" 75 "Double precision floating-point register.") 76 77(define_register_constraint "e" "TARGET_FMOVD ? NO_REGS : FP_REGS" 78 "Floating-point register.") 79 80(define_register_constraint "f" "FP_REGS" 81 "Floating-point register.") 82 83(define_register_constraint "k" "SIBCALL_REGS" 84 "@internal") 85 86(define_register_constraint "l" "PR_REGS" 87 "PR register.") 88 89(define_register_constraint "t" "T_REGS" 90 "T register.") 91 92(define_register_constraint "u" "NON_SP_REGS" 93 "Non-stack-pointer register.") 94 95(define_register_constraint "w" "FP0_REGS" 96 "Floating-point register 0.") 97 98(define_register_constraint "x" "MAC_REGS" 99 "MACH and MACL registers.") 100 101(define_register_constraint "y" "FPUL_REGS" 102 "FPUL register.") 103 104(define_register_constraint "z" "R0_REGS" 105 "R0 register.") 106 107;; Integer constraints 108(define_constraint "I06" 109 "A signed 6-bit constant, as used in SHmedia beqi, bnei and xori." 110 (and (match_code "const_int") 111 (match_test "ival >= -32 && ival <= 31"))) 112 113(define_constraint "I08" 114 "A signed 8-bit constant, as used in add, sub, etc." 115 (and (match_code "const_int") 116 (match_test "ival >= -128 && ival <= 127"))) 117 118(define_constraint "I10" 119 "A signed 10-bit constant, as used in SHmedia andi, ori." 120 (and (match_code "const_int") 121 (match_test "ival >= -512 && ival <= 511"))) 122 123(define_constraint "I16" 124 "A signed 16-bit constant, as used in SHmedia movi." 125 (and (match_code "const_int") 126 (match_test "ival >= -32768 && ival <= 32767"))) 127 128(define_constraint "I20" 129 "A signed 20-bit constant, as used in SH2A movi20." 130 (and (match_code "const_int") 131 (match_test "ival >= -524288 && ival <= 524287") 132 (match_test "TARGET_SH2A"))) 133 134(define_constraint "I28" 135 "A signed 28-bit constant, as used in SH2A movi20s." 136 (and (match_code "const_int") 137 (match_test "ival >= -134217728 && ival <= 134217727") 138 (match_test "(ival & 255) == 0") 139 (match_test "TARGET_SH2A"))) 140 141(define_constraint "J16" 142 "0xffffffff00000000 or 0x00000000ffffffff." 143 (and (match_code "const_int") 144 (match_test "CONST_OK_FOR_J16 (ival)"))) 145 146(define_constraint "Jmb" 147 "Low byte mask constant 0x000000FF" 148 (and (match_code "const_int") 149 (match_test "ival == 0xFF"))) 150 151(define_constraint "Jmw" 152 "Low word mask constant 0x0000FFFF" 153 (and (match_code "const_int") 154 (match_test "ival == 0xFFFF"))) 155 156(define_constraint "Jhb" 157 "Highest bit constant" 158 (and (match_code "const_int") 159 (match_test "(ival & 0xFFFFFFFF) == 0x80000000"))) 160 161(define_constraint "K03" 162 "An unsigned 3-bit constant, as used in SH2A bclr, bset, etc." 163 (and (match_code "const_int") 164 (match_test "ival >= 0 && ival <= 7"))) 165 166(define_constraint "K04" 167 "An unsigned 4-bit constant, as used in mov.b displacement addressing." 168 (and (match_code "const_int") 169 (match_test "ival >= 0 && ival <= 15"))) 170 171(define_constraint "K05" 172 "An unsigned 5-bit constant, as used in mov.w displacement addressing." 173 (and (match_code "const_int") 174 (match_test "ival >= 0 && ival <= 31"))) 175 176(define_constraint "K08" 177 "An unsigned 8-bit constant, as used in and, or, etc." 178 (and (match_code "const_int") 179 (match_test "ival >= 0 && ival <= 255"))) 180 181(define_constraint "K12" 182 "An unsigned 12-bit constant, as used in SH2A 12-bit mov.b displacement 183 addressing." 184 (and (match_code "const_int") 185 (match_test "ival >= 0 && ival <= 4095"))) 186 187(define_constraint "K13" 188 "An unsigned 13-bit constant, as used in SH2A 12-bit mov.w displacement 189 addressing." 190 (and (match_code "const_int") 191 (match_test "ival >= 0 && ival <= 8191"))) 192 193(define_constraint "K16" 194 "An unsigned 16-bit constant, as used in SHmedia shori." 195 (and (match_code "const_int") 196 (match_test "ival >= 0 && ival <= 65535"))) 197 198(define_constraint "P27" 199 "A constant for shift operand 1,2,8 or 16." 200 (and (match_code "const_int") 201 (match_test "ival == 1 || ival == 2 || ival == 8 || ival == 16"))) 202 203(define_constraint "M" 204 "Integer constant 1." 205 (and (match_code "const_int") 206 (match_test "ival == 1"))) 207 208(define_constraint "N" 209 "Integer constant 0." 210 (and (match_code "const_int") 211 (match_test "ival == 0"))) 212 213;; Floating-point constraints 214(define_constraint "G" 215 "Double constant 0." 216 (and (match_code "const_double") 217 (match_test "fp_zero_operand (op)"))) 218 219(define_constraint "H" 220 "Double constant 1." 221 (and (match_code "const_double") 222 (match_test "fp_one_operand (op)"))) 223 224;; Extra constraints 225(define_constraint "Q" 226 "A pc relative load operand." 227 (and (match_code "mem") 228 (match_test "GET_MODE (op) != QImode") 229 (match_test "IS_PC_RELATIVE_LOAD_ADDR_P (XEXP (op, 0))"))) 230 231(define_constraint "Bsc" 232 "Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber 233 operand is not SCRATCH (i.e. REG) then R0 is probably being used, 234 hence mova is being used, hence do not select this pattern." 235 (match_code "scratch")) 236 237(define_constraint "Ccl" 238 "A call site label, for bsrf." 239 (and (match_code "unspec") 240 (match_test "XINT (op, 1) == UNSPEC_CALLER"))) 241 242(define_constraint "Css" 243 "A signed 16-bit constant, literal or symbolic." 244 (and (match_code "const") 245 (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC") 246 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_EXTRACT_S16"))) 247 248(define_constraint "Csu" 249 "An unsigned 16-bit constant, literal or symbolic." 250 (and (match_code "const") 251 (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC") 252 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_EXTRACT_U16"))) 253 254(define_constraint "Csy" 255 "A label or a symbol." 256 (ior (match_test "NON_PIC_REFERENCE_P (op)") 257 (match_test "PIC_ADDR_P (op)"))) 258 259(define_constraint "Z" 260 "A zero in any shape or form." 261 (match_test "op == CONST0_RTX (GET_MODE (op))")) 262 263(define_constraint "W" 264 "Any vector constant we can handle." 265 (and (match_code "const_vector") 266 (ior (match_test "sh_rep_vec (op, VOIDmode)") 267 (match_test "HOST_BITS_PER_WIDE_INT >= 64 268 ? sh_const_vec (op, VOIDmode) 269 : sh_1el_vec (op, VOIDmode)")))) 270 271(define_constraint "Cpg" 272 "A non-explicit constant that can be loaded directly into a general 273 purpose register. This is like 's' except we don't allow 274 PIC_ADDR_P." 275 (match_test "IS_NON_EXPLICIT_CONSTANT_P (op)")) 276 277(define_constraint "Pso" 278 "Integer constant with a single bit set in its lower 8-bit." 279 (and (match_code "const_int") 280 (ior (match_test "ival == 1") 281 (match_test "ival == 2") 282 (match_test "ival == 4") 283 (match_test "ival == 8") 284 (match_test "ival == 16") 285 (match_test "ival == 32") 286 (match_test "ival == 64") 287 (match_test "ival == 128")))) 288 289(define_constraint "Psz" 290 "Integer constant with a single zero bit in the lower 8-bit." 291 (and (match_code "const_int") 292 (ior (match_test "~ival == 1") 293 (match_test "~ival == 2") 294 (match_test "~ival == 4") 295 (match_test "~ival == 8") 296 (match_test "~ival == 16") 297 (match_test "~ival == 32") 298 (match_test "~ival == 64") 299 (match_test "~ival == 128")))) 300 301(define_memory_constraint "Sua" 302 "@internal" 303 (and (match_test "memory_operand (op, GET_MODE (op))") 304 (match_test "GET_CODE (XEXP (op, 0)) != PLUS"))) 305 306(define_memory_constraint "Sdd" 307 "A memory reference that uses displacement addressing." 308 (and (match_code "mem") 309 (match_code "plus" "0") 310 (match_code "reg" "00") 311 (match_code "const_int" "01"))) 312 313(define_memory_constraint "Snd" 314 "A memory reference that excludes displacement addressing." 315 (and (match_code "mem") 316 (match_test "! satisfies_constraint_Sdd (op)"))) 317 318(define_memory_constraint "Sid" 319 "A memory reference that uses index addressing." 320 (and (match_code "mem") 321 (match_code "plus" "0") 322 (match_code "reg" "00") 323 (match_code "reg" "01"))) 324 325(define_memory_constraint "Ssd" 326 "A memory reference that excludes index and displacement addressing." 327 (and (match_code "mem") 328 (match_test "! satisfies_constraint_Sid (op)") 329 (match_test "! satisfies_constraint_Sdd (op)"))) 330 331(define_memory_constraint "Sbv" 332 "A memory reference, as used in SH2A bclr.b, bset.b, etc." 333 (and (match_test "MEM_P (op) && GET_MODE (op) == QImode") 334 (match_test "REG_P (XEXP (op, 0))"))) 335 336(define_memory_constraint "Sbw" 337 "A memory reference, as used in SH2A bclr.b, bset.b, etc." 338 (and (match_test "satisfies_constraint_Sdd (op)") 339 (match_test "GET_MODE (op) == QImode") 340 (match_test "satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))"))) 341 342(define_memory_constraint "Sra" 343 "A memory reference that uses simple register addressing." 344 (and (match_code "mem") 345 (match_code "reg" "0"))) 346 347(define_memory_constraint "Ara" 348 "A memory reference that uses simple register addressing suitable for 349 gusa atomic operations." 350 (and (match_code "mem") 351 (match_code "reg" "0") 352 (match_test "REGNO (XEXP (op, 0)) != SP_REG"))) 353 354(define_memory_constraint "Add" 355 "A memory reference that uses displacement addressing suitable for 356 gusa atomic operations." 357 (and (match_code "mem") 358 (match_test "GET_MODE (op) == SImode") 359 (match_code "plus" "0") 360 (match_code "reg" "00") 361 (match_code "const_int" "01") 362 (match_test "REGNO (XEXP (XEXP (op, 0), 0)) != SP_REG"))) 363