1;; Machine description for AArch64 architecture.
2;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21(define_register_constraint "k" "STACK_REG"
22  "@internal The stack register.")
23
24(define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
25  "@internal Registers suitable for an indirect tail call")
26
27(define_register_constraint "w" "FP_REGS"
28  "Floating point and SIMD vector registers.")
29
30(define_register_constraint "Upa" "PR_REGS"
31  "SVE predicate registers p0 - p15.")
32
33(define_register_constraint "Upl" "PR_LO_REGS"
34  "SVE predicate registers p0 - p7.")
35
36(define_register_constraint "x" "FP_LO_REGS"
37  "Floating point and SIMD vector registers V0 - V15.")
38
39(define_constraint "I"
40 "A constant that can be used with an ADD operation."
41 (and (match_code "const_int")
42      (match_test "aarch64_uimm12_shift (ival)")))
43
44(define_constraint "Uaa"
45  "@internal A constant that matches two uses of add instructions."
46  (and (match_code "const_int")
47       (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
48
49(define_constraint "Uav"
50  "@internal
51   A constraint that matches a VG-based constant that can be added by
52   a single ADDVL or ADDPL."
53 (match_operand 0 "aarch64_sve_addvl_addpl_immediate"))
54
55(define_constraint "Uat"
56  "@internal
57   A constraint that matches a VG-based constant that can be added by
58   using multiple instructions, with one temporary register."
59 (match_operand 0 "aarch64_split_add_offset_immediate"))
60
61(define_constraint "J"
62 "A constant that can be used with a SUB operation (once negated)."
63 (and (match_code "const_int")
64      (match_test "aarch64_uimm12_shift (-ival)")))
65
66;; We can't use the mode of a CONST_INT to determine the context in
67;; which it is being used, so we must have a separate constraint for
68;; each context.
69
70(define_constraint "K"
71 "A constant that can be used with a 32-bit logical operation."
72 (and (match_code "const_int")
73      (match_test "aarch64_bitmask_imm (ival, SImode)")))
74
75(define_constraint "L"
76 "A constant that can be used with a 64-bit logical operation."
77 (and (match_code "const_int")
78      (match_test "aarch64_bitmask_imm (ival, DImode)")))
79
80(define_constraint "M"
81 "A constant that can be used with a 32-bit MOV immediate operation."
82 (and (match_code "const_int")
83      (match_test "aarch64_move_imm (ival, SImode)")))
84
85(define_constraint "N"
86 "A constant that can be used with a 64-bit MOV immediate operation."
87 (and (match_code "const_int")
88      (match_test "aarch64_move_imm (ival, DImode)")))
89
90(define_constraint "Uti"
91 "A constant that can be used with a 128-bit MOV immediate operation."
92 (and (ior (match_code "const_int")
93	   (match_code "const_wide_int"))
94      (match_test "aarch64_mov128_immediate (op)")))
95
96(define_constraint "UsO"
97 "A constant that can be used with a 32-bit and operation."
98 (and (match_code "const_int")
99      (match_test "aarch64_and_bitmask_imm (ival, SImode)")))
100
101(define_constraint "UsP"
102 "A constant that can be used with a 64-bit and operation."
103 (and (match_code "const_int")
104      (match_test "aarch64_and_bitmask_imm (ival, DImode)")))
105
106(define_constraint "S"
107  "A constraint that matches an absolute symbolic address."
108  (and (match_code "const,symbol_ref,label_ref")
109       (match_test "aarch64_symbolic_address_p (op)")))
110
111(define_constraint "Y"
112  "Floating point constant zero."
113  (and (match_code "const_double")
114       (match_test "aarch64_float_const_zero_rtx_p (op)")))
115
116(define_constraint "Z"
117  "Integer constant zero."
118  (match_test "op == const0_rtx"))
119
120(define_constraint "Ush"
121  "A constraint that matches an absolute symbolic address high part."
122  (and (match_code "high")
123       (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
124
125(define_constraint "Usa"
126  "@internal
127   A constraint that matches an absolute symbolic address that can be
128   loaded by a single ADR."
129  (and (match_code "const,symbol_ref,label_ref")
130       (match_test "aarch64_symbolic_address_p (op)")
131       (match_test "aarch64_mov_operand_p (op, GET_MODE (op))")))
132
133(define_constraint "Uss"
134  "@internal
135  A constraint that matches an immediate shift constant in SImode."
136  (and (match_code "const_int")
137       (match_test "(unsigned HOST_WIDE_INT) ival < 32")))
138
139(define_constraint "Usn"
140 "A constant that can be used with a CCMN operation (once negated)."
141 (and (match_code "const_int")
142      (match_test "IN_RANGE (ival, -31, 0)")))
143
144(define_constraint "Usd"
145  "@internal
146  A constraint that matches an immediate shift constant in DImode."
147  (and (match_code "const_int")
148       (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
149
150(define_constraint "Usf"
151  "@internal Usf is a symbol reference under the context where plt stub allowed."
152  (and (match_code "symbol_ref")
153       (match_test "!(aarch64_is_noplt_call_p (op)
154		      || aarch64_is_long_call_p (op))")))
155
156(define_constraint "Usg"
157  "@internal
158  A constraint that matches an immediate right shift constant in SImode
159  suitable for a SISD instruction."
160  (and (match_code "const_int")
161       (match_test "IN_RANGE (ival, 1, 31)")))
162
163(define_constraint "Usj"
164  "@internal
165  A constraint that matches an immediate right shift constant in DImode
166  suitable for a SISD instruction."
167  (and (match_code "const_int")
168       (match_test "IN_RANGE (ival, 1, 63)")))
169
170(define_constraint "UsM"
171  "@internal
172  A constraint that matches the immediate constant -1."
173  (match_test "op == constm1_rtx"))
174
175(define_constraint "Usv"
176  "@internal
177   A constraint that matches a VG-based constant that can be loaded by
178   a single CNT[BHWD]."
179 (match_operand 0 "aarch64_sve_cnt_immediate"))
180
181(define_constraint "Usi"
182  "@internal
183 A constraint that matches an immediate operand valid for
184 the SVE INDEX instruction."
185 (match_operand 0 "aarch64_sve_index_immediate"))
186
187(define_constraint "Ui1"
188  "@internal
189  A constraint that matches the immediate constant +1."
190  (match_test "op == const1_rtx"))
191
192(define_constraint "Ui2"
193  "@internal
194  A constraint that matches the integers 0...3."
195  (and (match_code "const_int")
196       (match_test "(unsigned HOST_WIDE_INT) ival <= 3")))
197
198(define_constraint "Ui3"
199  "@internal
200  A constraint that matches the integers 0...4."
201  (and (match_code "const_int")
202       (match_test "(unsigned HOST_WIDE_INT) ival <= 4")))
203
204(define_constraint "Ui7"
205  "@internal
206  A constraint that matches the integers 0...7."
207  (and (match_code "const_int")
208       (match_test "(unsigned HOST_WIDE_INT) ival <= 7")))
209
210(define_constraint "Up3"
211  "@internal
212  A constraint that matches the integers 2^(0...4)."
213  (and (match_code "const_int")
214       (match_test "(unsigned) exact_log2 (ival) <= 4")))
215
216(define_constraint "Uph"
217  "@internal
218  A constraint that matches HImode integers zero extendable to
219  SImode plus_operand."
220  (and (match_code "const_int")
221       (match_test "aarch64_plushi_immediate (op, VOIDmode)")))
222
223(define_memory_constraint "Q"
224 "A memory address which uses a single base register with no offset."
225 (and (match_code "mem")
226      (match_test "REG_P (XEXP (op, 0))")))
227
228(define_memory_constraint "Umq"
229  "@internal
230   A memory address which uses a base register with an offset small enough for
231   a load/store pair operation in DI mode."
232   (and (match_code "mem")
233	(match_test "aarch64_legitimate_address_p (DImode, XEXP (op, 0), false,
234						   ADDR_QUERY_LDP_STP)")))
235
236(define_memory_constraint "Ump"
237  "@internal
238  A memory address suitable for a load/store pair operation."
239  (and (match_code "mem")
240       (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
241						  true, ADDR_QUERY_LDP_STP)")))
242
243;; Used for storing two 64-bit values in an AdvSIMD register using an STP
244;; as a 128-bit vec_concat.
245(define_memory_constraint "Uml"
246  "@internal
247  A memory address suitable for a load/store pair operation."
248  (and (match_code "mem")
249       (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 1,
250						  ADDR_QUERY_LDP_STP)")))
251
252(define_memory_constraint "Utr"
253  "@internal
254   An address valid for SVE LDR and STR instructions (as distinct from
255   LD[1234] and ST[1234] patterns)."
256  (and (match_code "mem")
257       (match_test "aarch64_sve_ldr_operand_p (op)")))
258
259(define_memory_constraint "Utv"
260  "@internal
261   An address valid for loading/storing opaque structure
262   types wider than TImode."
263  (and (match_code "mem")
264       (match_test "aarch64_simd_mem_operand_p (op)")))
265
266(define_memory_constraint "Utq"
267  "@internal
268   An address valid for loading or storing a 128-bit AdvSIMD register"
269  (and (match_code "mem")
270       (match_test "aarch64_legitimate_address_p (V2DImode,
271						  XEXP (op, 0), 1)")))
272
273(define_memory_constraint "Uty"
274  "@internal
275   An address valid for SVE LD1Rs."
276  (and (match_code "mem")
277       (match_test "aarch64_sve_ld1r_operand_p (op)")))
278
279(define_memory_constraint "Utx"
280  "@internal
281   An address valid for SVE structure mov patterns (as distinct from
282   LD[234] and ST[234] patterns)."
283  (match_operand 0 "aarch64_sve_struct_memory_operand"))
284
285(define_constraint "Ufc"
286  "A floating point constant which can be used with an\
287   FMOV immediate operation."
288  (and (match_code "const_double")
289       (match_test "aarch64_float_const_representable_p (op)")))
290
291(define_constraint "Uvi"
292  "A floating point constant which can be used with a\
293   MOVI immediate operation."
294  (and (match_code "const_double")
295       (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))")))
296
297(define_constraint "Do"
298  "@internal
299   A constraint that matches vector of immediates for orr."
300 (and (match_code "const_vector")
301      (match_test "aarch64_simd_valid_immediate (op, NULL,
302						 AARCH64_CHECK_ORR)")))
303
304(define_constraint "Db"
305  "@internal
306   A constraint that matches vector of immediates for bic."
307 (and (match_code "const_vector")
308      (match_test "aarch64_simd_valid_immediate (op, NULL,
309						 AARCH64_CHECK_BIC)")))
310
311(define_constraint "Dn"
312  "@internal
313 A constraint that matches vector of immediates."
314 (and (match_code "const,const_vector")
315      (match_test "aarch64_simd_valid_immediate (op, NULL)")))
316
317(define_constraint "Dh"
318  "@internal
319 A constraint that matches an immediate operand valid for\
320 AdvSIMD scalar move in HImode."
321 (and (match_code "const_int")
322      (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
323						 HImode)")))
324
325(define_constraint "Dq"
326  "@internal
327 A constraint that matches an immediate operand valid for\
328 AdvSIMD scalar move in QImode."
329 (and (match_code "const_int")
330      (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
331						 QImode)")))
332
333(define_constraint "Dl"
334  "@internal
335 A constraint that matches vector of immediates for left shifts."
336 (and (match_code "const,const_vector")
337      (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
338						 true)")))
339
340(define_constraint "Dr"
341  "@internal
342 A constraint that matches vector of immediates for right shifts."
343 (and (match_code "const,const_vector")
344      (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
345						 false)")))
346(define_constraint "Dz"
347  "@internal
348 A constraint that matches a vector of immediate zero."
349 (and (match_code "const,const_vector")
350      (match_test "op == CONST0_RTX (GET_MODE (op))")))
351
352(define_constraint "Dm"
353  "@internal
354 A constraint that matches a vector of immediate minus one."
355 (and (match_code "const,const_vector")
356      (match_test "op == CONST1_RTX (GET_MODE (op))")))
357
358(define_constraint "Dd"
359  "@internal
360 A constraint that matches an integer immediate operand valid\
361 for AdvSIMD scalar operations in DImode."
362 (and (match_code "const_int")
363      (match_test "aarch64_can_const_movi_rtx_p (op, DImode)")))
364
365(define_constraint "Ds"
366  "@internal
367 A constraint that matches an integer immediate operand valid\
368 for AdvSIMD scalar operations in SImode."
369 (and (match_code "const_int")
370      (match_test "aarch64_can_const_movi_rtx_p (op, SImode)")))
371
372(define_address_constraint "Dp"
373  "@internal
374 An address valid for a prefetch instruction."
375 (match_test "aarch64_address_valid_for_prefetch_p (op, true)"))
376
377(define_constraint "vsa"
378  "@internal
379   A constraint that matches an immediate operand valid for SVE
380   arithmetic instructions."
381 (match_operand 0 "aarch64_sve_arith_immediate"))
382
383(define_constraint "vsc"
384  "@internal
385   A constraint that matches a signed immediate operand valid for SVE
386   CMP instructions."
387 (match_operand 0 "aarch64_sve_cmp_vsc_immediate"))
388
389(define_constraint "vsd"
390  "@internal
391   A constraint that matches an unsigned immediate operand valid for SVE
392   CMP instructions."
393 (match_operand 0 "aarch64_sve_cmp_vsd_immediate"))
394
395(define_constraint "vsi"
396  "@internal
397   A constraint that matches a vector count operand valid for SVE INC and
398   DEC instructions."
399 (match_operand 0 "aarch64_sve_inc_dec_immediate"))
400
401(define_constraint "vsn"
402  "@internal
403   A constraint that matches an immediate operand whose negative
404   is valid for SVE SUB instructions."
405 (match_operand 0 "aarch64_sve_sub_arith_immediate"))
406
407(define_constraint "vsl"
408  "@internal
409   A constraint that matches an immediate operand valid for SVE logical
410   operations."
411 (match_operand 0 "aarch64_sve_logical_immediate"))
412
413(define_constraint "vsm"
414  "@internal
415   A constraint that matches an immediate operand valid for SVE MUL
416   operations."
417 (match_operand 0 "aarch64_sve_mul_immediate"))
418
419(define_constraint "vsA"
420  "@internal
421   A constraint that matches an immediate operand valid for SVE FADD
422   and FSUB operations."
423 (match_operand 0 "aarch64_sve_float_arith_immediate"))
424
425(define_constraint "vsM"
426  "@internal
427   A constraint that matches an imediate operand valid for SVE FMUL
428   operations."
429 (match_operand 0 "aarch64_sve_float_mul_immediate"))
430
431(define_constraint "vsN"
432  "@internal
433   A constraint that matches the negative of vsA"
434 (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate"))
435