1;; Marvell ARM Processor Pipeline Description
2;; Copyright (C) 2010-2019 Free Software Foundation, Inc.
3;; Contributed by Marvell.
4
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; Pipeline description for the Marvell PJ4, aka "Flareon".
22(define_automaton "pj4")
23
24;; Issue resources
25(define_cpu_unit    "pj4_is1,pj4_is2"        "pj4")
26(define_reservation "pj4_is"             "(pj4_is1|pj4_is2)")
27(define_reservation "pj4_isb"            "(pj4_is1+pj4_is2)")
28
29;; Functional units
30(define_cpu_unit "pj4_alu1,pj4_alu2,pj4_mul,pj4_div" "pj4")
31
32;; Completion ports
33(define_cpu_unit "pj4_w1,pj4_w2"             "pj4")
34
35;; Complete/Retire control
36(define_cpu_unit    "pj4_c1,pj4_c2"          "pj4")
37(define_reservation "pj4_cp"             "(pj4_c1|pj4_c2)")
38(define_reservation "pj4_cpb"            "(pj4_c1+pj4_c2)")
39
40;; Integer arithmetic instructions
41
42(define_insn_reservation "pj4_alu_e1" 1
43  (and (eq_attr "tune" "marvell_pj4")
44       (eq_attr "type" "mov_imm,mov_reg,mvn_imm,mvn_reg")
45       (not (eq_attr "conds" "set")))
46                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
47
48(define_insn_reservation "pj4_alu_e1_conds" 4
49  (and (eq_attr "tune" "marvell_pj4")
50       (eq_attr "type" "mov_imm,mov_reg,mvn_imm,mvn_reg")
51       (eq_attr "conds" "set"))
52                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
53
54(define_insn_reservation "pj4_alu" 1
55  (and (eq_attr "tune" "marvell_pj4")
56       (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\
57                        logic_imm,logics_imm,logic_reg,logics_reg,\
58                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
59                        adr,bfm,rev,alu_dsp_reg,\
60                        shift_imm,shift_reg")
61       (not (eq_attr "conds" "set")))
62                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
63
64(define_insn_reservation "pj4_alu_conds" 4
65  (and (eq_attr "tune" "marvell_pj4")
66       (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\
67                        logic_imm,logics_imm,logic_reg,logics_reg,\
68                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
69                        adr,bfm,rev,alu_dsp_reg,\
70                        shift_imm,shift_reg")
71       (eq_attr "conds" "set"))
72                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
73
74(define_insn_reservation "pj4_shift" 1
75  (and (eq_attr "tune" "marvell_pj4")
76       (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
77                        alus_shift_imm,logics_shift_imm,\
78                        alu_shift_reg,logic_shift_reg,\
79                        alus_shift_reg,logics_shift_reg,\
80                        extend,\
81                        mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
82       (not (eq_attr "conds" "set"))
83       (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
84
85(define_insn_reservation "pj4_shift_conds" 4
86  (and (eq_attr "tune" "marvell_pj4")
87       (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
88                        alus_shift_imm,logics_shift_imm,\
89                        alu_shift_reg,logic_shift_reg,\
90                        alus_shift_reg,logics_shift_reg,\
91                        extend,\
92                        mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
93       (eq_attr "conds" "set")
94       (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
95
96(define_insn_reservation "pj4_alu_shift" 1
97  (and (eq_attr "tune" "marvell_pj4")
98       (not (eq_attr "conds" "set"))
99       (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
100                        alus_shift_imm,logics_shift_imm,\
101                        alu_shift_reg,logic_shift_reg,\
102                        alus_shift_reg,logics_shift_reg,\
103                        extend,\
104                        mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
105                               "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
106
107(define_insn_reservation "pj4_alu_shift_conds" 4
108  (and (eq_attr "tune" "marvell_pj4")
109       (eq_attr "conds" "set")
110       (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
111                        alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
112                        extend,\
113                        mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
114                               "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
115
116(define_bypass 2 "pj4_alu_shift,pj4_shift"
117                 "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
118
119(define_insn_reservation "pj4_ir_mul" 3
120  (and (eq_attr "tune" "marvell_pj4")
121       (ior (eq_attr "mul32" "yes")
122	    (eq_attr "widen_mul64" "yes")))
123		     "pj4_is,pj4_mul,nothing*2,pj4_cp")
124
125(define_insn_reservation "pj4_ir_div" 20
126  (and (eq_attr "tune" "marvell_pj4")
127       (eq_attr "type" "udiv,sdiv")) "pj4_is,pj4_div*19,pj4_cp")
128
129;; Branches and calls.
130
131(define_insn_reservation "pj4_branches" 0
132  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "branch")) "pj4_is")
133
134(define_insn_reservation "pj4_calls" 32
135  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "call")) "pj4_is")
136
137;; Load/store instructions
138
139(define_insn_reservation "pj4_ldr"  3
140  (and (eq_attr "tune" "marvell_pj4")
141       (eq_attr "type" "load_byte,load_4"))
142                       "pj4_is,pj4_alu1,nothing*2,pj4_cp")
143
144(define_insn_reservation "pj4_ldrd" 3
145  (and (eq_attr "tune" "marvell_pj4")
146       (eq_attr "type" "load_8"))
147                       "pj4_is,pj4_alu1,nothing*2,pj4_cpb")
148
149(define_insn_reservation "pj4_str"  1
150  (and (eq_attr "tune" "marvell_pj4")
151       (eq_attr "type" "store_4"))
152                       "pj4_is,pj4_alu1,nothing*2,pj4_cp")
153
154(define_insn_reservation "pj4_strd" 1
155  (and (eq_attr "tune" "marvell_pj4")
156       (eq_attr "type" "store_8"))
157                       "pj4_is,pj4_alu1,nothing*2,pj4_cpb")
158
159(define_insn_reservation "pj4_ldm" 4
160  (and (eq_attr "tune" "marvell_pj4")
161       (eq_attr "type" "load_12,load_16")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
162
163(define_insn_reservation "pj4_stm" 2
164  (and (eq_attr "tune" "marvell_pj4")
165       (eq_attr "type" "store_12,store_16")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
166
167;; Loads forward at WR-stage to ALU pipes
168(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu")
169(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu_shift" "arm_no_early_alu_shift_dep")
170
171(define_bypass 4 "pj4_ldr,pj4_ldrd" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
172(define_bypass 5 "pj4_ldm" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
173
174;; Loads to stores can back-to-back forward
175(define_bypass 1 "pj4_ldr,pj4_ldrd" "pj4_str,pj4_strd" "arm_no_early_store_addr_dep")
176
177;; PJ4 VFP floating point unit
178(define_automaton "pj4_vfp")
179
180(define_cpu_unit "vissue" "pj4_vfp")
181(define_cpu_unit "vadd"   "pj4_vfp")
182(define_cpu_unit "vmul"   "pj4_vfp")
183(define_cpu_unit "vdiv"   "pj4_vfp")
184(define_cpu_unit "vfast"  "pj4_vfp")
185
186(define_insn_reservation "pj4_vfp_add"  5
187  (and (eq_attr "tune" "marvell_pj4")
188       (eq_attr "type" "fadds,faddd")) "pj4_is,nothing*2,vissue,vadd,nothing*3")
189
190(define_insn_reservation "pj4_vfp_mul"  6
191  (and (eq_attr "tune" "marvell_pj4")
192       (eq_attr "type" "fmuls,fmuld")) "pj4_is,nothing*2,vissue,vmul,nothing*4")
193
194(define_insn_reservation "pj4_vfp_divs" 20
195  (and (eq_attr "tune" "marvell_pj4")
196       (eq_attr "type" "fdivs, fsqrts"))       "pj4_is,nothing*2,vissue,vdiv*18,nothing")
197
198(define_insn_reservation "pj4_vfp_divd" 34
199  (and (eq_attr "tune" "marvell_pj4")
200       (eq_attr "type" "fdivd, fsqrtd"))       "pj4_is,nothing*2,vissue,vdiv*32,nothing")
201
202(define_insn_reservation "pj4_vfp_mac"  9
203  (and (eq_attr "tune" "marvell_pj4")
204       (eq_attr "type" "fmacs,fmacd"))
205                       "pj4_is,nothing*2,vissue,vmul,nothing*3,vadd,nothing*3")
206
207(define_bypass 5 "pj4_vfp_mac" "pj4_vfp_mac" "arm_no_early_mul_dep")
208
209(define_insn_reservation "pj4_vfp_cpy"  4
210  (and (eq_attr "tune" "marvell_pj4")
211       (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,\
212                        fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f"))
213"pj4_is,nothing*2,vissue,vfast,nothing*2")
214
215;; Enlarge latency, and wish that more nondependent insns are
216;; scheduled immediately after VFP load.
217(define_insn_reservation "pj4_vfp_load" 4
218  (and (eq_attr "tune" "marvell_pj4")
219       (eq_attr "type" "f_loads,f_loadd"))    "pj4_isb,pj4_alu1,nothing,vissue,pj4_cp")
220
221(define_insn_reservation "pj4_vfp_store" 1
222  (and (eq_attr "tune" "marvell_pj4")
223       (eq_attr "type" "f_stores,f_stored"))  "pj4_isb,pj4_alu1,nothing,vissue,pj4_cp")
224
225(define_insn_reservation "pj4_vfp_to_core" 7
226  (and (eq_attr "tune" "marvell_pj4")
227       (eq_attr "type" "f_mrc,f_mrrc,f_flag")) "pj4_isb,nothing,nothing,vissue,vfast,nothing*2")
228
229(define_insn_reservation "pj4_core_to_vfp" 2
230  (and (eq_attr "tune" "marvell_pj4")
231       (eq_attr "type" "f_mcr,f_mcrr")) "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp")
232
233