1 /* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987-2019 Free Software Foundation, Inc. 3 Contributed by Michael Tiemann (tiemann@cygnus.com). 4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 5 at Cygnus Support. 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GCC is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #include "config/vxworks-dummy.h" 24 25 /* Note that some other tm.h files include this one and then override 26 whatever definitions are necessary. */ 27 28 #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros () 29 30 /* Target CPU versions for D. */ 31 #define TARGET_D_CPU_VERSIONS sparc_d_target_versions 32 33 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ 34 /* #define SPARC_BI_ARCH */ 35 36 /* Macro used later in this file to determine default architecture. */ 37 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 38 39 /* TARGET_ARCH{32,64} are the main macros to decide which of the two 40 architectures to compile for. We allow targets to choose compile time or 41 runtime selection. */ 42 #ifdef IN_LIBGCC2 43 #if defined(__sparcv9) || defined(__arch64__) 44 #define TARGET_ARCH32 0 45 #else 46 #define TARGET_ARCH32 1 47 #endif /* sparc64 */ 48 #else 49 #ifdef SPARC_BI_ARCH 50 #define TARGET_ARCH32 (!TARGET_64BIT) 51 #else 52 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) 53 #endif /* SPARC_BI_ARCH */ 54 #endif /* IN_LIBGCC2 */ 55 #define TARGET_ARCH64 (!TARGET_ARCH32) 56 57 /* Code model selection in 64-bit environment. 58 59 The machine mode used for addresses is 32-bit wide: 60 61 TARGET_CM_32: 32-bit address space. 62 It is the code model used when generating 32-bit code. 63 64 The machine mode used for addresses is 64-bit wide: 65 66 TARGET_CM_MEDLOW: 32-bit address space. 67 The executable must be in the low 32 bits of memory. 68 This avoids generating %uhi and %ulo terms. Programs 69 can be statically or dynamically linked. 70 71 TARGET_CM_MEDMID: 44-bit address space. 72 The executable must be in the low 44 bits of memory, 73 and the %[hml]44 terms are used. The text and data 74 segments have a maximum size of 2GB (31-bit span). 75 The maximum offset from any instruction to the label 76 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 77 78 TARGET_CM_MEDANY: 64-bit address space. 79 The text and data segments have a maximum size of 2GB 80 (31-bit span) and may be located anywhere in memory. 81 The maximum offset from any instruction to the label 82 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 83 84 TARGET_CM_EMBMEDANY: 64-bit address space. 85 The text and data segments have a maximum size of 2GB 86 (31-bit span) and may be located anywhere in memory. 87 The global register %g4 contains the start address of 88 the data segment. Programs are statically linked and 89 PIC is not supported. 90 91 Different code models are not supported in 32-bit environment. */ 92 93 #define TARGET_CM_MEDLOW (sparc_code_model == CM_MEDLOW) 94 #define TARGET_CM_MEDMID (sparc_code_model == CM_MEDMID) 95 #define TARGET_CM_MEDANY (sparc_code_model == CM_MEDANY) 96 #define TARGET_CM_EMBMEDANY (sparc_code_model == CM_EMBMEDANY) 97 98 /* Default code model to be overridden in 64-bit environment. */ 99 #define SPARC_DEFAULT_CMODEL CM_32 100 101 /* Do not use the .note.GNU-stack convention by default. */ 102 #define NEED_INDICATE_EXEC_STACK 0 103 104 /* This is call-clobbered in the normal ABI, but is reserved in the 105 home grown (aka upward compatible) embedded ABI. */ 106 #define EMBMEDANY_BASE_REG "%g4" 107 108 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 109 and specified by the user via --with-cpu=foo. 110 This specifies the cpu implementation, not the architecture size. */ 111 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 112 capable cpu's. */ 113 #define TARGET_CPU_sparc 0 114 #define TARGET_CPU_v7 0 /* alias */ 115 #define TARGET_CPU_cypress 0 /* alias */ 116 #define TARGET_CPU_v8 1 /* generic v8 implementation */ 117 #define TARGET_CPU_supersparc 2 118 #define TARGET_CPU_hypersparc 3 119 #define TARGET_CPU_leon 4 120 #define TARGET_CPU_leon3 5 121 #define TARGET_CPU_leon3v7 6 122 #define TARGET_CPU_sparclite 7 123 #define TARGET_CPU_f930 7 /* alias */ 124 #define TARGET_CPU_f934 7 /* alias */ 125 #define TARGET_CPU_sparclite86x 8 126 #define TARGET_CPU_sparclet 9 127 #define TARGET_CPU_tsc701 9 /* alias */ 128 #define TARGET_CPU_v9 10 /* generic v9 implementation */ 129 #define TARGET_CPU_sparcv9 10 /* alias */ 130 #define TARGET_CPU_sparc64 10 /* alias */ 131 #define TARGET_CPU_ultrasparc 11 132 #define TARGET_CPU_ultrasparc3 12 133 #define TARGET_CPU_niagara 13 134 #define TARGET_CPU_niagara2 14 135 #define TARGET_CPU_niagara3 15 136 #define TARGET_CPU_niagara4 16 137 #define TARGET_CPU_niagara7 19 138 #define TARGET_CPU_m8 20 139 140 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 141 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 142 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ 143 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ 144 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ 145 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ 146 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 \ 147 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 \ 148 || TARGET_CPU_DEFAULT == TARGET_CPU_m8 149 150 #define CPP_CPU32_DEFAULT_SPEC "" 151 #define ASM_CPU32_DEFAULT_SPEC "" 152 153 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 154 /* ??? What does Sun's CC pass? */ 155 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 156 /* ??? It's not clear how other assemblers will handle this, so by default 157 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 158 is handled in sol2.h. */ 159 #define ASM_CPU64_DEFAULT_SPEC "-Av9" 160 #endif 161 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 162 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 163 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" 164 #endif 165 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 166 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 167 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 168 #endif 169 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara 170 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 171 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 172 #endif 173 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 174 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 175 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 176 #endif 177 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 178 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 179 #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG 180 #endif 181 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 182 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 183 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG 184 #endif 185 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 186 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 187 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG 188 #endif 189 #if TARGET_CPU_DEFAULT == TARGET_CPU_m8 190 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 191 #define ASM_CPU64_DEFAULT_SPEC AS_M8_FLAG 192 #endif 193 194 #else 195 196 #define CPP_CPU64_DEFAULT_SPEC "" 197 #define ASM_CPU64_DEFAULT_SPEC "" 198 199 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 200 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 201 #define CPP_CPU32_DEFAULT_SPEC "" 202 #define ASM_CPU32_DEFAULT_SPEC "" 203 #endif 204 205 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 206 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 207 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 208 #endif 209 210 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 211 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 212 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 213 #endif 214 215 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 216 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 217 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 218 #endif 219 220 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 221 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 222 #define ASM_CPU32_DEFAULT_SPEC "" 223 #endif 224 225 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 226 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 227 #define ASM_CPU32_DEFAULT_SPEC "" 228 #endif 229 230 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \ 231 || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 232 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__" 233 #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG 234 #endif 235 236 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 237 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__" 238 #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG 239 #endif 240 241 #endif 242 243 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 244 #error Unrecognized value in TARGET_CPU_DEFAULT. 245 #endif 246 247 #ifdef SPARC_BI_ARCH 248 249 #define CPP_CPU_DEFAULT_SPEC \ 250 (DEFAULT_ARCH32_P ? "\ 251 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 252 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 253 " : "\ 254 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 255 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 256 ") 257 #define ASM_CPU_DEFAULT_SPEC \ 258 (DEFAULT_ARCH32_P ? "\ 259 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 260 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 261 " : "\ 262 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 263 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 264 ") 265 266 #else /* !SPARC_BI_ARCH */ 267 268 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 269 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 270 271 #endif /* !SPARC_BI_ARCH */ 272 273 /* Define macros to distinguish architectures. */ 274 275 /* Common CPP definitions used by CPP_SPEC amongst the various targets 276 for handling -mcpu=xxx switches. */ 277 #define CPP_CPU_SPEC "\ 278 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 279 %{mcpu=sparclite:-D__sparclite__} \ 280 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 281 %{mcpu=sparclite86x:-D__sparclite86x__} \ 282 %{mcpu=v8:-D__sparc_v8__} \ 283 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 284 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 285 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ 286 %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ 287 %{mcpu=leon3v7:-D__leon__} \ 288 %{mcpu=v9:-D__sparc_v9__} \ 289 %{mcpu=ultrasparc:-D__sparc_v9__} \ 290 %{mcpu=ultrasparc3:-D__sparc_v9__} \ 291 %{mcpu=niagara:-D__sparc_v9__} \ 292 %{mcpu=niagara2:-D__sparc_v9__} \ 293 %{mcpu=niagara3:-D__sparc_v9__} \ 294 %{mcpu=niagara4:-D__sparc_v9__} \ 295 %{mcpu=niagara7:-D__sparc_v9__} \ 296 %{mcpu=m8:-D__sparc_v9__} \ 297 %{!mcpu*:%(cpp_cpu_default)} \ 298 " 299 #define CPP_ARCH32_SPEC "" 300 #define CPP_ARCH64_SPEC "-D__arch64__" 301 302 #define CPP_ARCH_DEFAULT_SPEC \ 303 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 304 305 #define CPP_ARCH_SPEC "\ 306 %{m32:%(cpp_arch32)} \ 307 %{m64:%(cpp_arch64)} \ 308 %{!m32:%{!m64:%(cpp_arch_default)}} \ 309 " 310 311 /* Macros to distinguish the endianness, window model and FP support. */ 312 #define CPP_OTHER_SPEC "\ 313 %{mflat:-D_FLAT} \ 314 %{msoft-float:-D_SOFT_FLOAT} \ 315 " 316 317 /* Macros to distinguish the particular subtarget. */ 318 #define CPP_SUBTARGET_SPEC "" 319 320 #define CPP_SPEC \ 321 "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)" 322 323 /* This used to translate -dalign to -malign, but that is no good 324 because it can't turn off the usual meaning of making debugging dumps. */ 325 326 #define CC1_SPEC "" 327 328 /* Override in target specific files. */ 329 #define ASM_CPU_SPEC "\ 330 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 331 %{mcpu=sparclite:-Asparclite} \ 332 %{mcpu=sparclite86x:-Asparclite} \ 333 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 334 %{mcpu=v8:-Av8} \ 335 %{mcpu=supersparc:-Av8} \ 336 %{mcpu=hypersparc:-Av8} \ 337 %{mcpu=leon:" AS_LEON_FLAG "} \ 338 %{mcpu=leon3:" AS_LEON_FLAG "} \ 339 %{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ 340 %{mv8plus:-Av8plus} \ 341 %{mcpu=v9:-Av9} \ 342 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 343 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 344 %{mcpu=niagara:%{!mv8plus:-Av9b}} \ 345 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ 346 %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ 347 %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \ 348 %{mcpu=niagara7:%{!mv8plus:" AS_NIAGARA7_FLAG "}} \ 349 %{mcpu=m8:%{!mv8plus:" AS_M8_FLAG "}} \ 350 %{!mcpu*:%(asm_cpu_default)} \ 351 " 352 353 /* Word size selection, among other things. 354 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 355 356 #define ASM_ARCH32_SPEC "-32" 357 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 358 #define ASM_ARCH_DEFAULT_SPEC \ 359 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 360 361 #define ASM_ARCH_SPEC "\ 362 %{m32:%(asm_arch32)} \ 363 %{m64:%(asm_arch64)} \ 364 %{!m32:%{!m64:%(asm_arch_default)}} \ 365 " 366 367 #ifdef HAVE_AS_RELAX_OPTION 368 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 369 #else 370 #define ASM_RELAX_SPEC "" 371 #endif 372 373 /* Special flags to the Sun-4 assembler when using pipe for input. */ 374 375 #define ASM_SPEC "\ 376 %{!pg:%{!p:%{" FPIE_OR_FPIC_SPEC ":-k}}} %{keep-local-as-symbols:-L} \ 377 %(asm_cpu) %(asm_relax)" 378 379 /* This macro defines names of additional specifications to put in the specs 380 that can be used in various specifications like CC1_SPEC. Its definition 381 is an initializer with a subgrouping for each command option. 382 383 Each subgrouping contains a string constant, that defines the 384 specification name, and a string constant that used by the GCC driver 385 program. 386 387 Do not define this macro if it does not need to do anything. */ 388 389 #define EXTRA_SPECS \ 390 { "cpp_cpu", CPP_CPU_SPEC }, \ 391 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 392 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 393 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 394 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 395 { "cpp_arch", CPP_ARCH_SPEC }, \ 396 { "cpp_other", CPP_OTHER_SPEC }, \ 397 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 398 { "asm_cpu", ASM_CPU_SPEC }, \ 399 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 400 { "asm_arch32", ASM_ARCH32_SPEC }, \ 401 { "asm_arch64", ASM_ARCH64_SPEC }, \ 402 { "asm_relax", ASM_RELAX_SPEC }, \ 403 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 404 { "asm_arch", ASM_ARCH_SPEC }, \ 405 SUBTARGET_EXTRA_SPECS 406 407 #define SUBTARGET_EXTRA_SPECS 408 409 /* Because libgcc can generate references back to libc (via .umul etc.) we have 410 to list libc again after the second libgcc. */ 411 #define LINK_GCC_C_SEQUENCE_SPEC "%G %{!nolibc:%L} %G %{!nolibc:%L}" 412 413 414 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 415 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 416 417 /* ??? This should be 32 bits for v9 but what can we do? */ 418 #define WCHAR_TYPE "short unsigned int" 419 #define WCHAR_TYPE_SIZE 16 420 421 /* Mask of all CPU selection flags. */ 422 #define MASK_ISA \ 423 (MASK_SPARCLITE + MASK_SPARCLET + MASK_LEON + MASK_LEON3 \ 424 + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 425 426 /* Mask of all CPU feature flags. */ 427 #define MASK_FEATURES \ 428 (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \ 429 + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \ 430 + MASK_POPC + MASK_SUBXC) 431 432 /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ 433 #define TARGET_HARD_MUL \ 434 (TARGET_SPARCLITE || TARGET_SPARCLET \ 435 || TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) 436 437 /* TARGET_HARD_MUL32: Use 32-bit hardware multiply instructions with %y 438 to get high 32 bits. False in 64-bit or V8+ because multiply stores 439 a 64-bit result in a register. */ 440 #define TARGET_HARD_MUL32 \ 441 (TARGET_HARD_MUL && TARGET_ARCH32 && !TARGET_V8PLUS) 442 443 /* MASK_APP_REGS must always be the default because that's what 444 FIXED_REGISTERS is set to and -ffixed- is processed before 445 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process 446 -mno-app-regs). */ 447 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 448 449 /* Recast the cpu class to be the cpu attribute. 450 Every file includes us, but not every file includes insn-attr.h. */ 451 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 452 453 /* Support for a compile-time default CPU, et cetera. The rules are: 454 --with-cpu is ignored if -mcpu is specified. 455 --with-tune is ignored if -mtune is specified. 456 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu 457 are specified. */ 458 #define OPTION_DEFAULT_SPECS \ 459 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 460 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 461 {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } 462 463 /* target machine storage layout */ 464 465 /* Define this if most significant bit is lowest numbered 466 in instructions that operate on numbered bit-fields. */ 467 #define BITS_BIG_ENDIAN 1 468 469 /* Define this if most significant byte of a word is the lowest numbered. */ 470 #define BYTES_BIG_ENDIAN 1 471 472 /* Define this if most significant word of a multiword number is the lowest 473 numbered. */ 474 #define WORDS_BIG_ENDIAN 1 475 476 #define MAX_BITS_PER_WORD 64 477 478 /* Width of a word, in units (bytes). */ 479 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 480 #ifdef IN_LIBGCC2 481 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 482 #else 483 #define MIN_UNITS_PER_WORD 4 484 #endif 485 486 /* Now define the sizes of the C data types. */ 487 #define SHORT_TYPE_SIZE 16 488 #define INT_TYPE_SIZE 32 489 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 490 #define LONG_LONG_TYPE_SIZE 64 491 #define FLOAT_TYPE_SIZE 32 492 #define DOUBLE_TYPE_SIZE 64 493 494 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the 495 SPARC ABI says that it is 128-bit wide. */ 496 /* #define LONG_DOUBLE_TYPE_SIZE 128 */ 497 498 /* The widest floating-point format really supported by the hardware. */ 499 #define WIDEST_HARDWARE_FP_SIZE 64 500 501 /* Width in bits of a pointer. This is the size of ptr_mode. */ 502 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 503 504 /* This is the machine mode used for addresses. */ 505 #define Pmode (TARGET_ARCH64 ? DImode : SImode) 506 507 /* If we have to extend pointers (only when TARGET_ARCH64 and not 508 TARGET_PTR64), we want to do it unsigned. This macro does nothing 509 if ptr_mode and Pmode are the same. */ 510 #define POINTERS_EXTEND_UNSIGNED 1 511 512 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 513 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 514 515 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 516 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because 517 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ 518 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 519 520 /* Temporary hack until the FIXME above is fixed. */ 521 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) 522 523 /* ALIGN FRAMES on double word boundaries */ 524 #define SPARC_STACK_ALIGN(LOC) ROUND_UP ((LOC), UNITS_PER_WORD * 2) 525 526 /* Allocation boundary (in *bits*) for the code of a function. */ 527 #define FUNCTION_BOUNDARY 32 528 529 /* Alignment of field after `int : 0' in a structure. */ 530 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 531 532 /* Every structure's size must be a multiple of this. */ 533 #define STRUCTURE_SIZE_BOUNDARY 8 534 535 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 536 #define PCC_BITFIELD_TYPE_MATTERS 1 537 538 /* No data type wants to be aligned rounder than this. */ 539 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 540 541 /* The best alignment to use in cases where we have a choice. */ 542 #define FASTEST_ALIGNMENT 64 543 544 /* Define this macro as an expression for the alignment of a structure 545 (given by STRUCT as a tree node) if the alignment computed in the 546 usual way is COMPUTED and the alignment explicitly specified was 547 SPECIFIED. 548 549 The default is to use SPECIFIED if it is larger; otherwise, use 550 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 551 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 552 (TARGET_FASTER_STRUCTS ? \ 553 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 554 || TREE_CODE (STRUCT) == UNION_TYPE \ 555 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 556 && TYPE_FIELDS (STRUCT) != 0 \ 557 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 558 : MAX ((COMPUTED), (SPECIFIED))) \ 559 : MAX ((COMPUTED), (SPECIFIED))) 560 561 /* An integer expression for the size in bits of the largest integer machine 562 mode that should actually be used. We allow pairs of registers. */ 563 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode) 564 565 /* We need 2 words, so we can save the stack pointer and the return register 566 of the function containing a non-local goto target. */ 567 #define STACK_SAVEAREA_MODE(LEVEL) \ 568 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode) 569 570 /* Make arrays of chars word-aligned for the same reasons. */ 571 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 572 (TREE_CODE (TYPE) == ARRAY_TYPE \ 573 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 574 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 575 576 /* Make local arrays of chars word-aligned for the same reasons. */ 577 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) 578 579 /* Set this nonzero if move instructions will actually fail to work 580 when given unaligned data. */ 581 #define STRICT_ALIGNMENT 1 582 583 /* Things that must be doubleword aligned cannot go in the text section, 584 because the linker fails to align the text section enough! 585 Put them in the data section. This macro is only used in this file. */ 586 #define MAX_TEXT_ALIGN 32 587 588 /* Standard register usage. */ 589 590 /* Number of actual hardware registers. 591 The hardware registers are assigned numbers for the compiler 592 from 0 to just below FIRST_PSEUDO_REGISTER. 593 All registers that the compiler knows about must be given numbers, 594 even those that are not normally considered general registers. 595 596 SPARC has 32 integer registers and 32 floating point registers. 597 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not 598 accessible. We still account for them to simplify register computations 599 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 600 32+32+32+4 == 100. 601 Register 100 is used as the integer condition code register. 602 Register 101 is used as the soft frame pointer register. 603 Register 102 is used as the general status register by VIS instructions. */ 604 605 #define FIRST_PSEUDO_REGISTER 103 606 607 #define SPARC_FIRST_INT_REG 0 608 #define SPARC_LAST_INT_REG 31 609 #define SPARC_FIRST_FP_REG 32 610 /* Additional V9 fp regs. */ 611 #define SPARC_FIRST_V9_FP_REG 64 612 #define SPARC_LAST_V9_FP_REG 95 613 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 614 #define SPARC_FIRST_V9_FCC_REG 96 615 #define SPARC_LAST_V9_FCC_REG 99 616 /* V8 fcc reg. */ 617 #define SPARC_FCC_REG 96 618 /* Integer CC reg. We don't distinguish %icc from %xcc. */ 619 #define SPARC_ICC_REG 100 620 #define SPARC_GSR_REG 102 621 622 /* Nonzero if REGNO is an fp reg. */ 623 #define SPARC_FP_REG_P(REGNO) \ 624 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 625 626 /* Nonzero if REGNO is an int reg. */ 627 #define SPARC_INT_REG_P(REGNO) \ 628 (((unsigned) (REGNO)) <= SPARC_LAST_INT_REG) 629 630 /* Argument passing regs. */ 631 #define SPARC_OUTGOING_INT_ARG_FIRST 8 632 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) 633 #define SPARC_FP_ARG_FIRST 32 634 635 /* 1 for registers that have pervasive standard uses 636 and are not available for the register allocator. 637 638 On non-v9 systems: 639 g1 is free to use as temporary. 640 g2-g4 are reserved for applications. Gcc normally uses them as 641 temporaries, but this can be disabled via the -mno-app-regs option. 642 g5 through g7 are reserved for the operating system. 643 644 On v9 systems: 645 g1,g5 are free to use as temporaries, and are free to use between calls 646 if the call is to an external function via the PLT. 647 g4 is free to use as a temporary in the non-embedded case. 648 g4 is reserved in the embedded case. 649 g2-g3 are reserved for applications. Gcc normally uses them as 650 temporaries, but this can be disabled via the -mno-app-regs option. 651 g6-g7 are reserved for the operating system (or application in 652 embedded case). 653 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 654 currently be a fixed register until this pattern is rewritten. 655 Register 1 is also used when restoring call-preserved registers in large 656 stack frames. 657 658 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 659 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 660 */ 661 662 #define FIXED_REGISTERS \ 663 {1, 0, 2, 2, 2, 2, 1, 1, \ 664 0, 0, 0, 0, 0, 0, 1, 0, \ 665 0, 0, 0, 0, 0, 0, 0, 0, \ 666 0, 0, 0, 0, 0, 0, 0, 1, \ 667 \ 668 0, 0, 0, 0, 0, 0, 0, 0, \ 669 0, 0, 0, 0, 0, 0, 0, 0, \ 670 0, 0, 0, 0, 0, 0, 0, 0, \ 671 0, 0, 0, 0, 0, 0, 0, 0, \ 672 \ 673 0, 0, 0, 0, 0, 0, 0, 0, \ 674 0, 0, 0, 0, 0, 0, 0, 0, \ 675 0, 0, 0, 0, 0, 0, 0, 0, \ 676 0, 0, 0, 0, 0, 0, 0, 0, \ 677 \ 678 0, 0, 0, 0, 1, 1, 1} 679 680 /* 1 for registers not available across function calls. 681 These must include the FIXED_REGISTERS and also any 682 registers that can be used without being saved. 683 The latter must include the registers where values are returned 684 and the register where structure-value addresses are passed. 685 Aside from that, you can include as many other registers as you like. */ 686 687 #define CALL_USED_REGISTERS \ 688 {1, 1, 1, 1, 1, 1, 1, 1, \ 689 1, 1, 1, 1, 1, 1, 1, 1, \ 690 0, 0, 0, 0, 0, 0, 0, 0, \ 691 0, 0, 0, 0, 0, 0, 0, 1, \ 692 \ 693 1, 1, 1, 1, 1, 1, 1, 1, \ 694 1, 1, 1, 1, 1, 1, 1, 1, \ 695 1, 1, 1, 1, 1, 1, 1, 1, \ 696 1, 1, 1, 1, 1, 1, 1, 1, \ 697 \ 698 1, 1, 1, 1, 1, 1, 1, 1, \ 699 1, 1, 1, 1, 1, 1, 1, 1, \ 700 1, 1, 1, 1, 1, 1, 1, 1, \ 701 1, 1, 1, 1, 1, 1, 1, 1, \ 702 \ 703 1, 1, 1, 1, 1, 1, 1} 704 705 /* 1 for registers not available across function calls. 706 Unlike the above, this need not include the FIXED_REGISTERS, but any 707 registers that can be used without being saved. 708 The latter must include the registers where values are returned 709 and the register where structure-value addresses are passed. 710 Aside from that, you can include as many other registers as you like. */ 711 712 #define CALL_REALLY_USED_REGISTERS \ 713 {1, 1, 1, 1, 1, 1, 1, 1, \ 714 1, 1, 1, 1, 1, 1, 1, 1, \ 715 0, 0, 0, 0, 0, 0, 0, 0, \ 716 0, 0, 0, 0, 0, 0, 0, 0, \ 717 \ 718 1, 1, 1, 1, 1, 1, 1, 1, \ 719 1, 1, 1, 1, 1, 1, 1, 1, \ 720 1, 1, 1, 1, 1, 1, 1, 1, \ 721 1, 1, 1, 1, 1, 1, 1, 1, \ 722 \ 723 1, 1, 1, 1, 1, 1, 1, 1, \ 724 1, 1, 1, 1, 1, 1, 1, 1, \ 725 1, 1, 1, 1, 1, 1, 1, 1, \ 726 1, 1, 1, 1, 1, 1, 1, 1, \ 727 \ 728 1, 1, 1, 1, 1, 1, 1} 729 730 /* Due to the ARCH64 discrepancy above we must override this next 731 macro too. */ 732 #define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE) 733 734 /* Value is 1 if it is OK to rename a hard register FROM to another hard 735 register TO. We cannot rename %g1 as it may be used before the save 736 register window instruction in the prologue. */ 737 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) 738 739 /* Select a register mode required for caller save of hard regno REGNO. 740 Contrary to what is documented, the default is not the smallest suitable 741 mode but the largest suitable mode for the given (REGNO, NREGS) pair and 742 it quickly creates paradoxical subregs that can be problematic. */ 743 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 744 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, false) : (MODE)) 745 746 /* Specify the registers used for certain standard purposes. 747 The values of these macros are register numbers. */ 748 749 /* Register to use for pushing function arguments. */ 750 #define STACK_POINTER_REGNUM 14 751 752 /* The stack bias (amount by which the hardware register is offset by). */ 753 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 754 755 /* Actual top-of-stack address is 92/176 greater than the contents of the 756 stack pointer register for !v9/v9. That is: 757 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 758 address, and 6*4 bytes for the 6 register parameters. 759 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 760 parameter regs. */ 761 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 762 763 /* Base register for access to local variables of the function. */ 764 #define HARD_FRAME_POINTER_REGNUM 30 765 766 /* The soft frame pointer does not have the stack bias applied. */ 767 #define FRAME_POINTER_REGNUM 101 768 769 #define INIT_EXPANDERS \ 770 do { \ 771 if (crtl->emit.regno_pointer_align) \ 772 { \ 773 /* The biased stack pointer is only aligned on BITS_PER_UNIT. */\ 774 if (SPARC_STACK_BIAS) \ 775 { \ 776 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) \ 777 = BITS_PER_UNIT; \ 778 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) \ 779 = BITS_PER_UNIT; \ 780 } \ 781 \ 782 /* In 32-bit mode, not everything is double-word aligned. */ \ 783 if (TARGET_ARCH32) \ 784 { \ 785 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) \ 786 = BITS_PER_WORD; \ 787 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) \ 788 = BITS_PER_WORD; \ 789 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) \ 790 = BITS_PER_WORD; \ 791 } \ 792 } \ 793 } while (0) 794 795 /* Base register for access to arguments of the function. */ 796 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 797 798 /* Register in which static-chain is passed to a function. This must 799 not be a register used by the prologue. */ 800 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 801 802 /* Register which holds the global offset table, if any. */ 803 #define GLOBAL_OFFSET_TABLE_REGNUM 23 804 805 /* Register which holds offset table for position-independent data references. 806 The original SPARC ABI imposes no requirement on the choice of the register 807 so we use a pseudo-register to make sure it is properly saved and restored 808 around calls to setjmp. Now the ABI of VxWorks RTP makes it live on entry 809 to PLT entries so we use the canonical GOT register in this case. */ 810 #define PIC_OFFSET_TABLE_REGNUM \ 811 (TARGET_VXWORKS_RTP && flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 812 813 /* Pick a default value we can notice from override_options: 814 !v9: Default is on. 815 v9: Default is off. 816 Originally it was -1, but later on the container of options changed to 817 unsigned byte, so we decided to pick 127 as default value, which does 818 reflect an undefined default value in case of 0/1. */ 819 #define DEFAULT_PCC_STRUCT_RETURN 127 820 821 /* Functions which return large structures get the address 822 to place the wanted value at offset 64 from the frame. 823 Must reserve 64 bytes for the in and local registers. 824 v9: Functions which return large structures get the address to place the 825 wanted value from an invisible first argument. */ 826 #define STRUCT_VALUE_OFFSET 64 827 828 /* Define the classes of registers for register constraints in the 829 machine description. Also define ranges of constants. 830 831 One of the classes must always be named ALL_REGS and include all hard regs. 832 If there is more than one class, another class must be named NO_REGS 833 and contain no registers. 834 835 The name GENERAL_REGS must be the name of a class (or an alias for 836 another name such as ALL_REGS). This is the class of registers 837 that is allowed by "g" or "r" in a register constraint. 838 Also, registers outside this class are allocated only when 839 instructions express preferences for them. 840 841 The classes must be numbered in nondecreasing order; that is, 842 a larger-numbered class must never be contained completely 843 in a smaller-numbered class. 844 845 For any two classes, it is very desirable that there be another 846 class that represents their union. */ 847 848 /* The SPARC has various kinds of registers: general, floating point, 849 and condition codes [well, it has others as well, but none that we 850 care directly about]. 851 852 For v9 we must distinguish between the upper and lower floating point 853 registers because the upper ones can't hold SFmode values. 854 TARGET_HARD_REGNO_MODE_OK won't help here because reload assumes that 855 register(s) satisfying a group need for a class will also satisfy a 856 single need for that class. EXTRA_FP_REGS is a bit of a misnomer as 857 it covers all 64 fp regs. 858 859 It is important that one class contains all the general and all the standard 860 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 861 because reg_class_record() will bias the selection in favor of fp regs, 862 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 863 because FP_REGS > GENERAL_REGS. 864 865 It is also important that one class contain all the general and all 866 the fp regs. Otherwise when spilling a DFmode reg, it may be from 867 EXTRA_FP_REGS but find_reloads() may use class 868 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die 869 because the compiler thinks it doesn't have a spill reg when in 870 fact it does. 871 872 v9 also has 4 floating point condition code registers. Since we don't 873 have a class that is the union of FPCC_REGS with either of the others, 874 it is important that it appear first. Otherwise the compiler will die 875 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 876 constraints. */ 877 878 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 879 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 880 ALL_REGS, LIM_REG_CLASSES }; 881 882 #define N_REG_CLASSES (int) LIM_REG_CLASSES 883 884 /* Give names of register classes as strings for dump file. */ 885 886 #define REG_CLASS_NAMES \ 887 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 888 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 889 "ALL_REGS" } 890 891 /* Define which registers fit in which classes. 892 This is an initializer for a vector of HARD_REG_SET 893 of length N_REG_CLASSES. */ 894 895 #define REG_CLASS_CONTENTS \ 896 {{0, 0, 0, 0}, /* NO_REGS */ \ 897 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 898 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 899 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 900 {0, -1, 0, 0}, /* FP_REGS */ \ 901 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 902 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 903 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 904 {-1, -1, -1, 0x7f}} /* ALL_REGS */ 905 906 /* The same information, inverted: 907 Return the class number of the smallest class containing 908 reg number REGNO. This could be a conditional expression 909 or could index an array. */ 910 911 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 912 913 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 914 915 /* This is the order in which to allocate registers normally. 916 917 We put %f0-%f7 last among the float registers, so as to make it more 918 likely that a pseudo-register which dies in the float return register 919 area will get allocated to the float return register, thus saving a move 920 instruction at the end of the function. 921 922 Similarly for integer return value registers. 923 924 We know in this case that we will not end up with a leaf function. 925 926 The register allocator is given the global and out registers first 927 because these registers are call clobbered and thus less useful to 928 global register allocation. 929 930 Next we list the local and in registers. They are not call clobbered 931 and thus very useful for global register allocation. We list the input 932 registers before the locals so that it is more likely the incoming 933 arguments received in those registers can just stay there and not be 934 reloaded. */ 935 936 #define REG_ALLOC_ORDER \ 937 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 938 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 939 15, /* %o7 */ \ 940 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 941 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 942 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 943 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 944 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 945 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 946 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 947 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 948 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 949 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 950 96, 97, 98, 99, /* %fcc0-3 */ \ 951 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */ 952 953 /* This is the order in which to allocate registers for 954 leaf functions. If all registers can fit in the global and 955 output registers, then we have the possibility of having a leaf 956 function. 957 958 The macro actually mentioned the input registers first, 959 because they get renumbered into the output registers once 960 we know really do have a leaf function. 961 962 To be more precise, this register allocation order is used 963 when %o7 is found to not be clobbered right before register 964 allocation. Normally, the reason %o7 would be clobbered is 965 due to a call which could not be transformed into a sibling 966 call. 967 968 As a consequence, it is possible to use the leaf register 969 allocation order and not end up with a leaf function. We will 970 not get suboptimal register allocation in that case because by 971 definition of being potentially leaf, there were no function 972 calls. Therefore, allocation order within the local register 973 window is not critical like it is when we do have function calls. */ 974 975 #define REG_LEAF_ALLOC_ORDER \ 976 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 977 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 978 15, /* %o7 */ \ 979 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 980 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 981 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 982 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 983 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 984 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 985 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 986 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 987 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 988 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 989 96, 97, 98, 99, /* %fcc0-3 */ \ 990 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */ 991 992 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () 993 994 extern char sparc_leaf_regs[]; 995 #define LEAF_REGISTERS sparc_leaf_regs 996 997 extern char leaf_reg_remap[]; 998 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 999 1000 /* The class value for index registers, and the one for base regs. */ 1001 #define INDEX_REG_CLASS GENERAL_REGS 1002 #define BASE_REG_CLASS GENERAL_REGS 1003 1004 /* Local macro to handle the two v9 classes of FP regs. */ 1005 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1006 1007 /* Predicate for 2-bit and 5-bit unsigned constants. */ 1008 #define SPARC_IMM2_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x3) == 0) 1009 #define SPARC_IMM5_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x1F) == 0) 1010 1011 /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */ 1012 #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20) 1013 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 1014 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 1015 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 1016 1017 /* 10- and 11-bit immediates are only used for a few specific insns. 1018 SMALL_INT is used throughout the port so we continue to use it. */ 1019 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 1020 1021 /* Predicate for constants that can be loaded with a sethi instruction. 1022 This is the general, 64-bit aware, bitwise version that ensures that 1023 only constants whose representation fits in the mask 1024 1025 0x00000000fffffc00 1026 1027 are accepted. It will reject, for example, negative SImode constants 1028 on 64-bit hosts, so correct handling is to mask the value beforehand 1029 according to the mode of the instruction. */ 1030 #define SPARC_SETHI_P(X) \ 1031 (((unsigned HOST_WIDE_INT) (X) \ 1032 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1033 1034 /* Version of the above predicate for SImode constants and below. */ 1035 #define SPARC_SETHI32_P(X) \ 1036 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1037 1038 /* Return the maximum number of consecutive registers 1039 needed to represent mode MODE in a register of class CLASS. */ 1040 /* On SPARC, this is the size of MODE in words. */ 1041 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1042 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1043 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1044 1045 /* Stack layout; function entry, exit and calling. */ 1046 1047 /* Define this if pushing a word on the stack 1048 makes the stack pointer a smaller address. */ 1049 #define STACK_GROWS_DOWNWARD 1 1050 1051 /* Define this to nonzero if the nominal address of the stack frame 1052 is at the high-address end of the local variables; 1053 that is, each additional local variable allocated 1054 goes at a more negative offset in the frame. */ 1055 #define FRAME_GROWS_DOWNWARD 1 1056 1057 /* Offset of first parameter from the argument pointer register value. 1058 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1059 even if this function isn't going to use it. 1060 v9: This is 128 for the ins and locals. */ 1061 #define FIRST_PARM_OFFSET(FNDECL) \ 1062 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1063 1064 /* Offset from the argument pointer register value to the CFA. 1065 This is different from FIRST_PARM_OFFSET because the register window 1066 comes between the CFA and the arguments. */ 1067 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1068 1069 /* When a parameter is passed in a register, stack space is still 1070 allocated for it. 1071 !v9: All 6 possible integer registers have backing store allocated. 1072 v9: Only space for the arguments passed is allocated. */ 1073 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1074 meaning to the backend. Further, we need to be able to detect if a 1075 varargs/unprototyped function is called, as they may want to spill more 1076 registers than we've provided space. Ugly, ugly. So for now we retain 1077 all 6 slots even for v9. */ 1078 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1079 1080 /* Definitions for register elimination. */ 1081 1082 #define ELIMINABLE_REGS \ 1083 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1084 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1085 1086 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1087 do \ 1088 { \ 1089 (OFFSET) = sparc_initial_elimination_offset ((TO)); \ 1090 } \ 1091 while (0) 1092 1093 /* Keep the stack pointer constant throughout the function. 1094 This is both an optimization and a necessity: longjmp 1095 doesn't behave itself when the stack pointer moves within 1096 the function! */ 1097 #define ACCUMULATE_OUTGOING_ARGS 1 1098 1099 /* Define this macro if the target machine has "register windows". This 1100 C expression returns the register number as seen by the called function 1101 corresponding to register number OUT as seen by the calling function. 1102 Return OUT if register number OUT is not an outbound register. */ 1103 1104 #define INCOMING_REGNO(OUT) \ 1105 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1106 1107 /* Define this macro if the target machine has "register windows". This 1108 C expression returns the register number as seen by the calling function 1109 corresponding to register number IN as seen by the called function. 1110 Return IN if register number IN is not an inbound register. */ 1111 1112 #define OUTGOING_REGNO(IN) \ 1113 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1114 1115 /* Define this macro if the target machine has register windows. This 1116 C expression returns true if the register is call-saved but is in the 1117 register window. */ 1118 1119 #define LOCAL_REGNO(REGNO) \ 1120 (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31) 1121 1122 /* Define the size of space to allocate for the return value of an 1123 untyped_call. */ 1124 1125 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) 1126 1127 /* 1 if N is a possible register number for function argument passing. 1128 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1129 1130 #define FUNCTION_ARG_REGNO_P(N) \ 1131 (((N) >= 8 && (N) <= 13) \ 1132 || (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63)) 1133 1134 /* Define a data type for recording info about an argument list 1135 during the scan of that argument list. This data type should 1136 hold all necessary information about the function itself 1137 and about the args processed so far, enough to enable macros 1138 such as FUNCTION_ARG to determine where the next arg should go. 1139 1140 On SPARC (!v9), this is a single integer, which is a number of words 1141 of arguments scanned so far (including the invisible argument, 1142 if any, which holds the structure-value-address). 1143 Thus 7 or more means all following args should go on the stack. 1144 1145 For v9, we also need to know whether a prototype is present. */ 1146 1147 struct sparc_args { 1148 int words; /* number of words passed so far */ 1149 int prototype_p; /* nonzero if a prototype is present */ 1150 int libcall_p; /* nonzero if a library call */ 1151 }; 1152 #define CUMULATIVE_ARGS struct sparc_args 1153 1154 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1155 for a call to a function whose data type is FNTYPE. 1156 For a library call, FNTYPE is 0. */ 1157 1158 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1159 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); 1160 1161 1162 /* Generate the special assembly code needed to tell the assembler whatever 1163 it might need to know about the return value of a function. 1164 1165 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1166 information to the assembler relating to peephole optimization (done in 1167 the assembler). */ 1168 1169 #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1170 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1171 1172 /* Output the special assembly code needed to tell the assembler some 1173 register is used as global register variable. 1174 1175 SPARC 64bit psABI declares registers %g2 and %g3 as application 1176 registers and %g6 and %g7 as OS registers. Any object using them 1177 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1178 and how they are used (scratch or some global variable). 1179 Linker will then refuse to link together objects which use those 1180 registers incompatibly. 1181 1182 Unless the registers are used for scratch, two different global 1183 registers cannot be declared to the same name, so in the unlikely 1184 case of a global register variable occupying more than one register 1185 we prefix the second and following registers with .gnu.part1. etc. */ 1186 1187 extern GTY(()) char sparc_hard_reg_printed[8]; 1188 1189 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1190 do { \ 1191 if (TARGET_ARCH64) \ 1192 { \ 1193 int end = end_hard_regno (DECL_MODE (decl), REGNO); \ 1194 int reg; \ 1195 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1196 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1197 { \ 1198 if (reg == (REGNO)) \ 1199 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1200 else \ 1201 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1202 reg, reg - (REGNO), (NAME)); \ 1203 sparc_hard_reg_printed[reg] = 1; \ 1204 } \ 1205 } \ 1206 } while (0) 1207 1208 /* Emit rtl for profiling. */ 1209 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1210 1211 /* All the work done in PROFILE_HOOK, but still required. */ 1212 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1213 1214 /* Set the name of the mcount function for the system. */ 1215 #define MCOUNT_FUNCTION "*mcount" 1216 1217 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1218 the stack pointer does not matter. The value is tested only in 1219 functions that have frame pointers. */ 1220 #define EXIT_IGNORE_STACK 1 1221 1222 /* Length in units of the trampoline for entering a nested function. */ 1223 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1224 1225 /* Alignment required for trampolines, in bits. */ 1226 #define TRAMPOLINE_ALIGNMENT 128 1227 1228 /* Generate RTL to flush the register windows so as to make arbitrary frames 1229 available. */ 1230 #define SETUP_FRAME_ADDRESSES() \ 1231 do { \ 1232 if (!TARGET_FLAT) \ 1233 emit_insn (gen_flush_register_windows ());\ 1234 } while (0) 1235 1236 /* Given an rtx for the address of a frame, 1237 return an rtx for the address of the word in the frame 1238 that holds the dynamic chain--the previous frame's address. */ 1239 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1240 plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1241 1242 /* Given an rtx for the frame pointer, 1243 return an rtx for the address of the frame. */ 1244 #define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS) 1245 1246 /* The return address isn't on the stack, it is in a register, so we can't 1247 access it from the current frame pointer. We can access it from the 1248 previous frame pointer though by reading a value from the register window 1249 save area. */ 1250 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1 1251 1252 /* This is the offset of the return address to the true next instruction to be 1253 executed for the current function. */ 1254 #define RETURN_ADDR_OFFSET \ 1255 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) 1256 1257 /* The current return address is in %i7. The return address of anything 1258 farther back is in the register window save area at [%fp+60]. */ 1259 /* ??? This ignores the fact that the actual return address is +8 for normal 1260 returns, and +12 for structure returns. */ 1261 #define RETURN_ADDR_REGNUM 31 1262 #define RETURN_ADDR_RTX(count, frame) \ 1263 ((count == -1) \ 1264 ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \ 1265 : gen_rtx_MEM (Pmode, \ 1266 memory_address (Pmode, plus_constant (Pmode, frame, \ 1267 15 * UNITS_PER_WORD \ 1268 + SPARC_STACK_BIAS)))) 1269 1270 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 1271 +12, but always using +8 is close enough for frame unwind purposes. 1272 Actually, just using %o7 is close enough for unwinding, but %o7+8 1273 is something you can return to. */ 1274 #define INCOMING_RETURN_ADDR_REGNUM 15 1275 #define INCOMING_RETURN_ADDR_RTX \ 1276 plus_constant (word_mode, \ 1277 gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8) 1278 #define DWARF_FRAME_RETURN_COLUMN \ 1279 DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM) 1280 1281 /* The offset from the incoming value of %sp to the top of the stack frame 1282 for the current function. On sparc64, we have to account for the stack 1283 bias if present. */ 1284 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 1285 1286 /* Describe how we implement __builtin_eh_return. */ 1287 #define EH_RETURN_REGNUM 1 1288 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 1289 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) 1290 1291 /* Define registers used by the epilogue and return instruction. */ 1292 #define EPILOGUE_USES(REGNO) \ 1293 ((REGNO) == RETURN_ADDR_REGNUM \ 1294 || (TARGET_FLAT \ 1295 && epilogue_completed \ 1296 && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \ 1297 || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM)) 1298 1299 /* Select a format to encode pointers in exception handling data. CODE 1300 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1301 true if the symbol may be affected by dynamic relocations. 1302 1303 If assembler and linker properly support .uaword %r_disp32(foo), 1304 then use PC relative 32-bit relocations instead of absolute relocs 1305 for shared libraries. On sparc64, use pc relative 32-bit relocs even 1306 for binaries, to save memory. 1307 1308 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 1309 symbol %r_disp32() is against was not local, but .hidden. In that 1310 case, we have to use DW_EH_PE_absptr for pic personality. */ 1311 #ifdef HAVE_AS_SPARC_UA_PCREL 1312 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 1313 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1314 (flag_pic \ 1315 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 1316 : ((TARGET_ARCH64 && ! GLOBAL) \ 1317 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1318 : DW_EH_PE_absptr)) 1319 #else 1320 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1321 (flag_pic \ 1322 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 1323 : ((TARGET_ARCH64 && ! GLOBAL) \ 1324 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1325 : DW_EH_PE_absptr)) 1326 #endif 1327 1328 /* Emit a PC-relative relocation. */ 1329 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1330 do { \ 1331 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1332 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 1333 assemble_name (FILE, LABEL); \ 1334 fputc (')', FILE); \ 1335 } while (0) 1336 #endif 1337 1338 /* Addressing modes, and classification of registers for them. */ 1339 1340 /* Macros to check register numbers against specific register classes. */ 1341 1342 /* These assume that REGNO is a hard or pseudo reg number. 1343 They give nonzero only if REGNO is a hard reg of the suitable class 1344 or a pseudo reg currently allocated to a suitable hard reg. 1345 Since they use reg_renumber, they are safe only once reg_renumber 1346 has been allocated, which happens in reginfo.c during register 1347 allocation. */ 1348 1349 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1350 (SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \ 1351 || (REGNO) == FRAME_POINTER_REGNUM \ 1352 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 1353 1354 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 1355 1356 #define REGNO_OK_FOR_FP_P(REGNO) \ 1357 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 1358 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 1359 1360 #define REGNO_OK_FOR_CCFP_P(REGNO) \ 1361 (TARGET_V9 \ 1362 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 1363 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 1364 1365 /* Maximum number of registers that can appear in a valid memory address. */ 1366 1367 #define MAX_REGS_PER_ADDRESS 2 1368 1369 /* Recognize any constant value that is a valid address. 1370 When PIC, we do not accept an address that would require a scratch reg 1371 to load into a register. */ 1372 1373 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1374 1375 /* Define this, so that when PIC, reload won't try to reload invalid 1376 addresses which require two reload registers. */ 1377 1378 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1379 1380 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 1381 1382 #ifdef HAVE_AS_OFFSETABLE_LO10 1383 #define USE_AS_OFFSETABLE_LO10 1 1384 #else 1385 #define USE_AS_OFFSETABLE_LO10 0 1386 #endif 1387 1388 /* Try a machine-dependent way of reloading an illegitimate address 1389 operand. If we find one, push the reload and jump to WIN. This 1390 macro is used in only one place: `find_reloads_address' in reload.c. */ 1391 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1392 do { \ 1393 int win; \ 1394 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1395 (int)(TYPE), (IND_LEVELS), &win); \ 1396 if (win) \ 1397 goto WIN; \ 1398 } while (0) 1399 1400 /* Specify the machine mode that this machine uses 1401 for the index in the tablejump instruction. */ 1402 /* If we ever implement any of the full models (such as CM_FULLANY), 1403 this has to be DImode in that case */ 1404 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1405 #define CASE_VECTOR_MODE \ 1406 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 1407 #else 1408 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 1409 we have to sign extend which slows things down. */ 1410 #define CASE_VECTOR_MODE \ 1411 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 1412 #endif 1413 1414 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1415 #define DEFAULT_SIGNED_CHAR 1 1416 1417 /* Max number of bytes we can move from memory to memory 1418 in one reasonably fast instruction. */ 1419 #define MOVE_MAX 8 1420 1421 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1422 move-instruction pairs, we will do a movmem or libcall instead. */ 1423 1424 #define MOVE_RATIO(speed) ((speed) ? 8 : 3) 1425 1426 /* Define if operations between registers always perform the operation 1427 on the full register even if a narrower mode is specified. */ 1428 #define WORD_REGISTER_OPERATIONS 1 1429 1430 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1431 will either zero-extend or sign-extend. The value of this macro should 1432 be the code that says which one of the two operations is implicitly 1433 done, UNKNOWN if none. */ 1434 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1435 1436 /* Nonzero if access to memory by bytes is slow and undesirable. 1437 For RISC chips, it means that access to memory by bytes is no 1438 better than access by words when possible, so grab a whole word 1439 and maybe make use of that. */ 1440 #define SLOW_BYTE_ACCESS 1 1441 1442 /* Define this to be nonzero if shift instructions ignore all but the low-order 1443 few bits. */ 1444 #define SHIFT_COUNT_TRUNCATED 1 1445 1446 /* For SImode, we make sure the top 32-bits of the register are clear and 1447 then we subtract 32 from the lzd instruction result. */ 1448 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1449 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) 1450 1451 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1452 return the mode to be used for the comparison. For floating-point, 1453 CCFP[E]mode is used. CCNZmode should be used when the first operand 1454 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 1455 processing is needed. */ 1456 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 1457 1458 /* Return nonzero if MODE implies a floating point inequality can be 1459 reversed. For SPARC this is always true because we have a full 1460 compliment of ordered and unordered comparisons, but until generic 1461 code knows how to reverse it correctly we keep the old definition. */ 1462 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 1463 1464 /* A function address in a call instruction for indexing purposes. */ 1465 #define FUNCTION_MODE Pmode 1466 1467 /* Define this if addresses of constant functions 1468 shouldn't be put through pseudo regs where they can be cse'd. 1469 Desirable on machines where ordinary constants are expensive 1470 but a CALL with constant address is cheap. */ 1471 #define NO_FUNCTION_CSE 1 1472 1473 /* The _Q_* comparison libcalls return booleans. */ 1474 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 1475 1476 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such 1477 that the inputs are fully consumed before the output memory is clobbered. */ 1478 1479 #define TARGET_BUGGY_QP_LIB 0 1480 1481 /* Assume by default that we do not have the Solaris-specific conversion 1482 routines nor 64-bit integer multiply and divide routines. */ 1483 1484 #define SUN_CONVERSION_LIBFUNCS 0 1485 #define DITF_CONVERSION_LIBFUNCS 0 1486 #define SUN_INTEGER_MULTIPLY_64 0 1487 1488 /* A C expression for the cost of a branch instruction. A value of 1 1489 is the default; other values are interpreted relative to that. */ 1490 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ 1491 (sparc_branch_cost (SPEED_P, PREDICTABLE_P)) 1492 1493 /* Control the assembler format that we output. */ 1494 1495 /* A C string constant describing how to begin a comment in the target 1496 assembler language. The compiler assumes that the comment will end at 1497 the end of the line. */ 1498 1499 #define ASM_COMMENT_START "!" 1500 1501 /* Output to assembler file text saying following lines 1502 may contain character constants, extra white space, comments, etc. */ 1503 1504 #define ASM_APP_ON "" 1505 1506 /* Output to assembler file text saying following lines 1507 no longer contain unusual constructs. */ 1508 1509 #define ASM_APP_OFF "" 1510 1511 /* How to refer to registers in assembler output. 1512 This sequence is indexed by compiler's hard-register-number (see above). */ 1513 1514 #define REGISTER_NAMES \ 1515 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 1516 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 1517 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 1518 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 1519 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 1520 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 1521 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 1522 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 1523 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 1524 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 1525 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 1526 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 1527 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" } 1528 1529 /* Define additional names for use in asm clobbers and asm declarations. */ 1530 1531 #define ADDITIONAL_REGISTER_NAMES \ 1532 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 1533 1534 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 1535 can run past this up to a continuation point. Once we used 1500, but 1536 a single entry in C++ can run more than 500 bytes, due to the length of 1537 mangled symbol names. dbxout.c should really be fixed to do 1538 continuations when they are actually needed instead of trying to 1539 guess... */ 1540 #define DBX_CONTIN_LENGTH 1000 1541 1542 /* This is how to output a command to make the user-level label named NAME 1543 defined for reference from other files. */ 1544 1545 /* Globalizing directive for a label. */ 1546 #define GLOBAL_ASM_OP "\t.global " 1547 1548 /* The prefix to add to user-visible assembler symbols. */ 1549 1550 #define USER_LABEL_PREFIX "_" 1551 1552 /* This is how to store into the string LABEL 1553 the symbol_ref name of an internal numbered label where 1554 PREFIX is the class of label and NUM is the number within the class. 1555 This is suitable for output with `assemble_name'. */ 1556 1557 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1558 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 1559 1560 /* This is how we hook in and defer the case-vector until the end of 1561 the function. */ 1562 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 1563 sparc_defer_case_vector ((LAB),(VEC), 0) 1564 1565 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 1566 sparc_defer_case_vector ((LAB),(VEC), 1) 1567 1568 /* This is how to output an element of a case-vector that is absolute. */ 1569 1570 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1571 do { \ 1572 char label[30]; \ 1573 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1574 if (CASE_VECTOR_MODE == SImode) \ 1575 fprintf (FILE, "\t.word\t"); \ 1576 else \ 1577 fprintf (FILE, "\t.xword\t"); \ 1578 assemble_name (FILE, label); \ 1579 fputc ('\n', FILE); \ 1580 } while (0) 1581 1582 /* This is how to output an element of a case-vector that is relative. 1583 (SPARC uses such vectors only when generating PIC.) */ 1584 1585 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1586 do { \ 1587 char label[30]; \ 1588 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 1589 if (CASE_VECTOR_MODE == SImode) \ 1590 fprintf (FILE, "\t.word\t"); \ 1591 else \ 1592 fprintf (FILE, "\t.xword\t"); \ 1593 assemble_name (FILE, label); \ 1594 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 1595 fputc ('-', FILE); \ 1596 assemble_name (FILE, label); \ 1597 fputc ('\n', FILE); \ 1598 } while (0) 1599 1600 /* This is what to output before and after case-vector (both 1601 relative and absolute). If .subsection -1 works, we put case-vectors 1602 at the beginning of the current section. */ 1603 1604 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1605 1606 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 1607 fprintf(FILE, "\t.subsection\t-1\n") 1608 1609 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 1610 fprintf(FILE, "\t.previous\n") 1611 1612 #endif 1613 1614 /* This is how to output an assembler line 1615 that says to advance the location counter 1616 to a multiple of 2**LOG bytes. */ 1617 1618 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1619 if ((LOG) != 0) \ 1620 fprintf (FILE, "\t.align %d\n", (1 << (LOG))) 1621 1622 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1623 fprintf (FILE, "\t.skip " HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 1624 1625 /* This says how to output an assembler line 1626 to define a global common symbol. */ 1627 1628 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1629 ( fputs ("\t.common ", (FILE)), \ 1630 assemble_name ((FILE), (NAME)), \ 1631 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) 1632 1633 /* This says how to output an assembler line to define a local common 1634 symbol. */ 1635 1636 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 1637 ( fputs ("\t.reserve ", (FILE)), \ 1638 assemble_name ((FILE), (NAME)), \ 1639 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ 1640 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 1641 1642 /* A C statement (sans semicolon) to output to the stdio stream 1643 FILE the assembler definition of uninitialized global DECL named 1644 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 1645 Try to use asm_output_aligned_bss to implement this macro. */ 1646 1647 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1648 do { \ 1649 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 1650 } while (0) 1651 1652 /* Output #ident as a .ident. */ 1653 1654 #undef TARGET_ASM_OUTPUT_IDENT 1655 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive 1656 1657 /* Prettify the assembly. */ 1658 1659 extern int sparc_indent_opcode; 1660 1661 #define ASM_OUTPUT_OPCODE(FILE, PTR) \ 1662 do { \ 1663 if (sparc_indent_opcode) \ 1664 { \ 1665 putc (' ', FILE); \ 1666 sparc_indent_opcode = 0; \ 1667 } \ 1668 } while (0) 1669 1670 /* TLS support defaulting to original Sun flavor. GNU extensions 1671 must be activated in separate configuration files. */ 1672 #ifdef HAVE_AS_TLS 1673 #define TARGET_TLS 1 1674 #else 1675 #define TARGET_TLS 0 1676 #endif 1677 1678 #define TARGET_SUN_TLS TARGET_TLS 1679 #define TARGET_GNU_TLS 0 1680 1681 #ifdef HAVE_AS_FMAF_HPC_VIS3 1682 #define AS_NIAGARA3_FLAG "d" 1683 #else 1684 #define AS_NIAGARA3_FLAG "b" 1685 #endif 1686 1687 #ifdef HAVE_AS_SPARC4 1688 #define AS_NIAGARA4_FLAG "-xarch=sparc4" 1689 #else 1690 #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG 1691 #endif 1692 1693 #ifdef HAVE_AS_SPARC5_VIS4 1694 #define AS_NIAGARA7_FLAG "-xarch=sparc5" 1695 #else 1696 #define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG 1697 #endif 1698 1699 #ifdef HAVE_AS_SPARC6 1700 #define AS_M8_FLAG "-xarch=sparc6" 1701 #else 1702 #define AS_M8_FLAG AS_NIAGARA7_FLAG 1703 #endif 1704 1705 #ifdef HAVE_AS_LEON 1706 #define AS_LEON_FLAG "-Aleon" 1707 #define AS_LEONV7_FLAG "-Aleon" 1708 #else 1709 #define AS_LEON_FLAG "-Av8" 1710 #define AS_LEONV7_FLAG "-Av7" 1711 #endif 1712 1713 /* We use gcc _mcount for profiling. */ 1714 #define NO_PROFILE_COUNTERS 0 1715 1716 /* Debug support */ 1717 #define MASK_DEBUG_OPTIONS 0x01 /* debug option handling */ 1718 #define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS 1719 1720 #define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS) 1721 1722 /* By default, use the weakest memory model for the cpu. */ 1723 #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL 1724 #define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT 1725 #endif 1726 1727 /* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1. */ 1728 #define SPARC_LOW_FE_EXCEPT_VALUES 0 1729 1730 #define TARGET_SUPPORTS_WIDE_INT 1 1731