1 /* Opcode table for the H8/300
2    Copyright (C) 1991-2016 Free Software Foundation, Inc.
3    Written by Steve Chamberlain <sac@cygnus.com>.
4 
5    This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
6 
7    This program is free software; you can redistribute it and/or modify
8    it under the terms of the GNU General Public License as published by
9    the Free Software Foundation; either version 3 of the License, or
10    (at your option) any later version.
11 
12    This program is distributed in the hope that it will be useful,
13    but WITHOUT ANY WARRANTY; without even the implied warranty of
14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15    GNU General Public License for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with this program; if not, write to the Free Software
19    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
20    02110-1301, USA.  */
21 
22 /* Instructions are stored as a sequence of nibbles.
23    If the nibble has value 15 or less than the representation is complete.
24    Otherwise, we record what it contains with several flags.  */
25 
26 typedef int op_type;
27 
28 enum h8_flags
29 {
30   L_2  =	0x10,
31   L_3  =	0x20,
32   /* 3 bit constant, zero not accepted.  */
33   L_3NZ =	0x30,
34   L_4  =	0x40,
35   L_5  =	0x50,
36   L_8  =	0x60,
37   L_8U =	0x70,
38   L_16 =	0x80,
39   L_16U =	0x90,
40   L_24 =	0xA0,
41   L_32 =	0xB0,
42   L_P  =	0xC0,
43 
44   /* Mask to isolate the L_x size bits.  */
45   SIZE =	0xF0,
46 
47   REG =		0x0100,
48   ABS =		0x0200,
49   MEMIND =	0x0300,
50   IMM =		0x0400,
51   DISP =	0x0500,
52   IND =		0x0600,
53   POSTINC =	0x0700,
54   POSTDEC =	0x0800,
55   PREINC =	0x0900,
56   PREDEC =	0x0A00,
57   PCREL =	0x0B00,
58   KBIT =	0x0C00,
59   DBIT =	0x0D00,
60   CONST_2 =     0x0E00,
61   CONST_4 =     0x0F00,
62   CONST_8 =     0x1000,
63   CONST_16 =    0x1100,
64   INDEXB =      0x1200,
65   INDEXW =      0x1300,
66   INDEXL =      0x1400,
67   PCIDXB =      0x1500,
68   PCIDXW =      0x1600,
69   PCIDXL =      0x1700,
70   VECIND =      0x1800,
71   LOWREG =      0x1900,
72   DATA   =      0x2000,
73 
74   /* Synonyms.  */
75   INC =		POSTINC,
76   DEC =		PREDEC,
77   /* Control Registers.  */
78   CCR =		0x4000,
79   EXR =		0x4100,
80   MACH = 	0x4200,
81   MACL = 	0x4300,
82   RESERV1 = 	0x4400,
83   RESERV2 = 	0x4500,
84   VBR = 	0x4600,
85   SBR = 	0x4700,
86   MACREG =	0x4800,
87   CCR_EXR = 	0x4900,
88   VBR_SBR = 	0x4A00,
89   CC_EX_VB_SB =	0x4B00,
90   RESERV3 =	0x4C00,
91   RESERV4 = 	0x4D00,
92   RESERV5 = 	0x4E00,
93   RESERV6 = 	0x4F00,
94 
95   /* Mask to isolate the addressing mode bits (REG .. PREDEC).  */
96   MODE =	0x7F00,
97 
98   CTRL = 	0x4000,
99 
100   NO_SYMBOLS =  0x8000,
101   SRC =		0x10000,
102   DST =		0x20000,
103   OP3 =		0x40000,
104   MEMRELAX = 	0x80000,		/* Move insn which may relax.  */
105 
106   DISPREG =	0x100000,
107   IGNORE =	0x200000,
108   ABSJMP =	0x400000,
109 
110   B00 =         0x800000, 		/* Bit 0 must be low.   */
111   B01 =         0x1000000, 		/* Bit 0 must be high.  */
112   B10 = 	0x2000000, 		/* Bit 1 must be low.   */
113   B11 = 	0x4000000, 		/* Bit 1 must be high.  */
114   B20 = 	0x8000000, 		/* Bit 2 must be low.   */
115   B21 = 	0x10000000, 		/* Bit 2 must be high.  */
116   B30 =		0x20000000, 		/* Bit 3 must be low.   */
117   B31 =		0x40000000,		/* Bit 3 must be high.  */
118   E =  		0x80000000,		/* End of nibble sequence.  */
119 
120   /* Immediates smaller than 8 bits are always unsigned.  */
121   IMM3 =	IMM | L_3,
122   IMM4 =	IMM | L_4,
123   IMM5 =	IMM | L_5,
124   IMM3NZ =	IMM | L_3NZ,
125   IMM2 =	IMM | L_2,
126 
127   IMM8 =	IMM | SRC | L_8,
128   IMM8U =	IMM | SRC | L_8U,
129   IMM16 =	IMM | SRC | L_16,
130   IMM16U =	IMM | SRC | L_16U,
131   IMM32 =	IMM | SRC | L_32,
132 
133   IMM3NZ_NS =   IMM3NZ | NO_SYMBOLS,
134   IMM4_NS =	IMM4 | NO_SYMBOLS,
135   IMM8U_NS =	IMM8U | NO_SYMBOLS,
136   IMM16U_NS =   IMM16U | NO_SYMBOLS,
137 
138   RD8  =	DST | L_8  | REG,
139   RD16 =	DST | L_16 | REG,
140   RD32 =	DST | L_32 | REG,
141   R3_8  =       OP3 | L_8  | REG,
142   R3_16 =       OP3 | L_16 | REG,
143   R3_32 =       OP3 | L_32 | REG,
144   RS8  =	SRC | L_8  | REG,
145   RS16 =	SRC | L_16 | REG,
146   RS32 =	SRC | L_32 | REG,
147 
148   RSP =		SRC | L_P | REG,
149   RDP =		DST | L_P | REG,
150 
151   PCREL8 =	PCREL | L_8,
152   PCREL16 =	PCREL | L_16,
153 
154   OP3PCREL8 =	OP3 | PCREL | L_8,
155   OP3PCREL16 =	OP3 | PCREL | L_16,
156 
157   INDEXB16  =	INDEXB | L_16,
158   INDEXW16  =	INDEXW | L_16,
159   INDEXL16  =	INDEXL | L_16,
160   INDEXB16D =	INDEXB | L_16 | DST,
161   INDEXW16D =	INDEXW | L_16 | DST,
162   INDEXL16D =	INDEXL | L_16 | DST,
163 
164   INDEXB32  =	INDEXB | L_32,
165   INDEXW32  =	INDEXW | L_32,
166   INDEXL32  =	INDEXL | L_32,
167   INDEXB32D =	INDEXB | L_32 | DST,
168   INDEXW32D =	INDEXW | L_32 | DST,
169   INDEXL32D =	INDEXL | L_32 | DST,
170 
171   DISP2SRC =	DISP | L_2  | SRC,
172   DISP16SRC =	DISP | L_16 | SRC,
173   DISP32SRC =	DISP | L_32 | SRC,
174 
175   DISP2DST =	DISP | L_2  | DST,
176   DISP16DST =	DISP | L_16 | DST,
177   DISP32DST =	DISP | L_32 | DST,
178 
179   DSTDISPREG =  DST | DISPREG,
180   SRCDISPREG =  SRC | DISPREG,
181 
182   ABS8SRC  = 	SRC | ABS | L_8,
183   ABS16SRC = 	SRC | ABS | L_16U,
184   ABS24SRC = 	SRC | ABS | L_24,
185   ABS32SRC = 	SRC | ABS | L_32,
186 
187   ABS8DST  =	DST | ABS | L_8,
188   ABS16DST = 	DST | ABS | L_16U,
189   ABS24DST = 	DST | ABS | L_24,
190   ABS32DST = 	DST | ABS | L_32,
191 
192   ABS8OP3  =	OP3 | ABS | L_8,
193   ABS16OP3 = 	OP3 | ABS | L_16U,
194   ABS24OP3 = 	OP3 | ABS | L_24,
195   ABS32OP3 = 	OP3 | ABS | L_32,
196 
197   RDDEC =	DST | DEC,
198   RSINC =	SRC | INC,
199   RDINC =	DST | INC,
200 
201   RSPOSTINC =	SRC | POSTINC,
202   RDPOSTINC =	DST | POSTINC,
203   RSPREINC =	SRC | PREINC,
204   RDPREINC =	DST | PREINC,
205   RSPOSTDEC =	SRC | POSTDEC,
206   RDPOSTDEC =	DST | POSTDEC,
207   RSPREDEC =	SRC | PREDEC,
208   RDPREDEC =	DST | PREDEC,
209 
210   RSIND =	SRC | IND,
211   RDIND =	DST | IND,
212   R3_IND = 	OP3 | IND,
213 
214 #define MS32	(SRC | L_32 | MACREG)
215 #define MD32	(DST | L_32 | MACREG)
216 
217 #if 1
218   OR8  =	RS8,		/* ??? OR as in One Register.  */
219   OR16 =	RS16,
220   OR32 =	RS32,
221 #else
222   OR8  =	RD8,
223   OR16 =	RD16,
224   OR32 =	RD32
225 #endif
226 };
227 
228 enum ctrlreg
229 {
230   C_CCR  = 0,
231   C_EXR  = 1,
232   C_MACH = 2,
233   C_MACL = 3,
234   C_VBR  = 6,
235   C_SBR  = 7
236 };
237 
238 enum {MAX_CODE_NIBBLES = 33};
239 
240 struct code
241 {
242   op_type nib[MAX_CODE_NIBBLES];
243 };
244 
245 struct arg
246 {
247   op_type nib[3];
248 };
249 
250 /* Availability of instructions on processor models.  */
251 enum h8_model
252 {
253   AV_H8,
254   AV_H8H,
255   AV_H8S,
256   AV_H8SX
257 };
258 
259 struct h8_opcode
260 {
261   int how;
262   enum h8_model available;
263   int time;
264   const char *name;
265   struct arg args;
266   struct code data;
267 };
268 
269 #ifdef DEFINE_TABLE
270 
271 #define DATA2   DATA, DATA
272 #define DATA3   DATA, DATA, DATA
273 #define DATA5   DATA, DATA, DATA, DATA, DATA
274 #define DATA7   DATA, DATA, DATA, DATA, DATA, DATA, DATA
275 
276 #define IMM8LIST	IMM8,   DATA
277 #define IMM16LIST	IMM16,  DATA3
278 #define IMM16ULIST	IMM16U, DATA3
279 #define IMM24LIST	IMM24,  DATA5
280 #define IMM32LIST	IMM32,  DATA7
281 
282 #define DISP16LIST DISP | L_16, DATA3
283 #define DISP24LIST DISP | L_24, DATA5
284 #define DISP32LIST DISP | L_32, DATA7
285 
286 #define ABS8LIST   ABS  | L_8,   DATA
287 #define ABS16LIST  ABS  | L_16U, DATA3
288 #define ABS24LIST  ABS  | L_24,  DATA5
289 #define ABS32LIST  ABS  | L_32,  DATA7
290 
291 #define DSTABS8LIST  DST | ABS | L_8,   DATA
292 #define DSTABS16LIST DST | ABS | L_16U, DATA3
293 #define DSTABS24LIST DST | ABS | L_24,  DATA5
294 #define DSTABS32LIST DST | ABS | L_32,  DATA7
295 
296 #define OP3ABS8LIST  OP3 | ABS | L_8,  DATA
297 #define OP3ABS16LIST OP3 | ABS | L_16, DATA3
298 #define OP3ABS24LIST OP3 | ABS | L_24, DATA5
299 #define OP3ABS32LIST OP3 | ABS | L_32, DATA7
300 
301 #define DSTDISP16LIST DST | DISP | L_16, DATA3
302 #define DSTDISP24LIST DST | DISP | L_24, DATA5
303 #define DSTDISP32LIST DST | DISP | L_32, DATA7
304 
305 #define A16LIST   L_16,  DATA3
306 #define A24LIST   L_24,  DATA5
307 #define A32LIST   L_32,  DATA7
308 
309 /* Extended Operand Prefixes:  */
310 
311 #define PREFIX_010	0x0, 0x1, 0x0
312 #define PREFIX_015	0x0, 0x1, 0x5
313 #define PREFIX_017	0x0, 0x1, 0x7
314 
315 #define PREFIX_0100	0x0, 0x1, 0x0, 0x0
316 #define PREFIX_010_D2	0x0, 0x1, 0x0, B30 | B21 | DISP2SRC
317 #define PREFIX_0101	0x0, 0x1, 0x0, 0x1
318 #define PREFIX_0102	0x0, 0x1, 0x0, 0x2
319 #define PREFIX_0103	0x0, 0x1, 0x0, 0x3
320 #define PREFIX_0104	0x0, 0x1, 0x0, 0x4
321 #define PREFIX_0105	0x0, 0x1, 0x0, 0x5
322 #define PREFIX_0106	0x0, 0x1, 0x0, 0x6
323 #define PREFIX_0107	0x0, 0x1, 0x0, 0x7
324 #define PREFIX_0108	0x0, 0x1, 0x0, 0x8
325 #define PREFIX_0109	0x0, 0x1, 0x0, 0x9
326 #define PREFIX_010A	0x0, 0x1, 0x0, 0xa
327 #define PREFIX_010D	0x0, 0x1, 0x0, 0xd
328 #define PREFIX_010E	0x0, 0x1, 0x0, 0xe
329 
330 #define PREFIX_0150	0x0, 0x1, 0x5, 0x0
331 #define PREFIX_015_D2	0x0, 0x1, 0x5, B30 | B21 | DISP2SRC
332 #define PREFIX_0151	0x0, 0x1, 0x5, 0x1
333 #define PREFIX_0152	0x0, 0x1, 0x5, 0x2
334 #define PREFIX_0153	0x0, 0x1, 0x5, 0x3
335 #define PREFIX_0154	0x0, 0x1, 0x5, 0x4
336 #define PREFIX_0155	0x0, 0x1, 0x5, 0x5
337 #define PREFIX_0156	0x0, 0x1, 0x5, 0x6
338 #define PREFIX_0157	0x0, 0x1, 0x5, 0x7
339 #define PREFIX_0158	0x0, 0x1, 0x5, 0x8
340 #define PREFIX_0159	0x0, 0x1, 0x5, 0x9
341 #define PREFIX_015A	0x0, 0x1, 0x5, 0xa
342 #define PREFIX_015D	0x0, 0x1, 0x5, 0xd
343 #define PREFIX_015E	0x0, 0x1, 0x5, 0xe
344 #define PREFIX_015F	0x0, 0x1, 0x5, 0xf
345 
346 #define PREFIX_0170	0x0, 0x1, 0x7, 0x0
347 #define PREFIX_017_D2S	0x0, 0x1, 0x7, B30 | B21 | DISP2SRC
348 #define PREFIX_017_D2D	0x0, 0x1, 0x7, B30 | B21 | DISP2DST
349 #define PREFIX_0171	0x0, 0x1, 0x7, 0x1
350 #define PREFIX_0172	0x0, 0x1, 0x7, 0x2
351 #define PREFIX_0173	0x0, 0x1, 0x7, 0x3
352 #define PREFIX_0174	0x0, 0x1, 0x7, 0x4
353 #define PREFIX_0175	0x0, 0x1, 0x7, 0x5
354 #define PREFIX_0176	0x0, 0x1, 0x7, 0x6
355 #define PREFIX_0177	0x0, 0x1, 0x7, 0x7
356 #define PREFIX_0178	0x0, 0x1, 0x7, 0x8
357 #define PREFIX_0179	0x0, 0x1, 0x7, 0x9
358 #define PREFIX_017A	0x0, 0x1, 0x7, 0xa
359 #define PREFIX_017D	0x0, 0x1, 0x7, 0xd
360 #define PREFIX_017E	0x0, 0x1, 0x7, 0xe
361 #define PREFIX_017F	0x0, 0x1, 0x7, 0xf
362 
363 #define PREFIX_6A15	0x6, 0xa, 0x1, 0x5
364 #define PREFIX_6A35	0x6, 0xa, 0x3, 0x5
365 #define PREFIX_6B15	0x6, 0xb, 0x1, 0x5
366 #define PREFIX_6B35	0x6, 0xb, 0x3, 0x5
367 
368 #define PREFIX_78R4	0x7, 0x8, B31 | DISPREG, 0x4
369 #define PREFIX_78R5	0x7, 0x8, B31 | DISPREG, 0x5
370 #define PREFIX_78R6	0x7, 0x8, B31 | DISPREG, 0x6
371 #define PREFIX_78R7	0x7, 0x8, B31 | DISPREG, 0x7
372 
373 #define PREFIX_78R4W	0x7, 0x8, B30 | DISPREG, 0x4
374 #define PREFIX_78R5W	0x7, 0x8, B30 | DISPREG, 0x5
375 #define PREFIX_78R6W	0x7, 0x8, B30 | DISPREG, 0x6
376 #define PREFIX_78R7W	0x7, 0x8, B30 | DISPREG, 0x7
377 
378 #define PREFIX_78R4WD	0x7, 0x8, B30 | DSTDISPREG, 0x4
379 #define PREFIX_78R5WD	0x7, 0x8, B30 | DSTDISPREG, 0x5
380 #define PREFIX_78R6WD	0x7, 0x8, B30 | DSTDISPREG, 0x6
381 #define PREFIX_78R7WD	0x7, 0x8, B30 | DSTDISPREG, 0x7
382 
383 #define PREFIX_7974	0x7, 0x9, 0x7, 0x4
384 #define PREFIX_7A74	0x7, 0xa, 0x7, 0x4
385 #define PREFIX_7A7C	0x7, 0xa, 0x7, 0xc
386 
387 
388 /* Source standard fragment:  */
389 #define FROM_IND	 0, RSIND
390 #define FROM_POSTINC	 8, RSPOSTINC
391 #define FROM_POSTDEC	10, RSPOSTDEC
392 #define FROM_PREINC	 9, RSPREINC
393 #define FROM_PREDEC	11, RSPREDEC
394 #define FROM_DISP2	B30 | B20 | DISP2SRC, DISPREG
395 #define FROM_DISP16	12, B30 | DISPREG
396 #define FROM_DISP32	12, B31 | DISPREG
397 #define FROM_DISP16B	13, B30 | DISPREG
398 #define FROM_DISP16W	14, B30 | DISPREG
399 #define FROM_DISP16L	15, B30 | DISPREG
400 #define FROM_DISP32B	13, B31 | DISPREG
401 #define FROM_DISP32W	14, B31 | DISPREG
402 #define FROM_DISP32L	15, B31 | DISPREG
403 #define FROM_ABS16	 4, B30 | IGNORE
404 #define FROM_ABS32	 4, B31 | IGNORE
405 
406 /* Destination standard fragment:  */
407 #define TO_IND		 0, RDIND
408 #define TO_IND_MOV	 0, RDIND | B30
409 #define TO_POSTINC	 8, RDPOSTINC
410 #define TO_POSTINC_MOV	 8, RDPOSTINC | B30
411 #define TO_POSTDEC	10, RDPOSTDEC
412 #define TO_POSTDEC_MOV	10, RDPOSTDEC | B30
413 #define TO_PREINC	 9, RDPREINC
414 #define TO_PREINC_MOV	 9, RDPREINC  | B30
415 #define TO_PREDEC	11, RDPREDEC
416 #define TO_PREDEC_MOV	11, RDPREDEC  | B30
417 #define TO_DISP2	B30 | B20 | DISP2DST, DSTDISPREG
418 #define TO_DISP2_MOV	B30 | B20 | DISP2DST, DSTDISPREG | B30
419 #define TO_DISP16	12, B30 | DSTDISPREG
420 #define TO_DISP32	12, B31 | DSTDISPREG
421 #define TO_DISP16B	13, B30 | DSTDISPREG
422 #define TO_DISP16W	14, B30 | DSTDISPREG
423 #define TO_DISP16L	15, B30 | DSTDISPREG
424 #define TO_DISP32B	13, B31 | DSTDISPREG
425 #define TO_DISP32W	14, B31 | DSTDISPREG
426 #define TO_DISP32L	15, B31 | DSTDISPREG
427 #define TO_ABS16	 4, B30 | IGNORE
428 #define TO_ABS32	 4, B31 | IGNORE
429 
430 /* Source fragment for three-word instruction:  */
431 #define TFROM_IND	6,  9, B30 | RSIND, 12
432 #define TFROM_DISP2	6,  9, B30 | DISPREG, 12
433 #define TFROM_ABS16	6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST
434 #define TFROM_ABS32	6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST
435 #define TFROM_POSTINC	6, 13, B30 | RSPOSTINC, 12
436 #define TFROM_PREINC	6, 13, B30 | RSPREINC, 12
437 #define TFROM_POSTDEC	6, 13, B30 | RSPOSTDEC, 12
438 #define TFROM_PREDEC	6, 13, B30 | RSPREDEC, 12
439 #define TFROM_DISP16	6, 15, B30 | DISPREG, 12, DISP16LIST
440 #define TFROM_DISP32	6, 11, 2, 12, DISP32LIST
441 #define TFROM_DISP16B	6, 15, B30 | DISPREG, 12, DISP16LIST
442 #define TFROM_DISP16W	6, 15, B30 | DISPREG, 12, DISP16LIST
443 #define TFROM_DISP16L	6, 15, B30 | DISPREG, 12, DISP16LIST
444 #define TFROM_DISP32B	6, 11, 2, 12, DISP32LIST
445 #define TFROM_DISP32W	6, 11, 2, 12, DISP32LIST
446 #define TFROM_DISP32L	6, 11, 2, 12, DISP32LIST
447 #define TFROM_ABS16W	6, 11, 1, 12, ABS16LIST
448 #define TFROM_ABS32W	6, 11, 3, 12, ABS32LIST
449 
450 /* Source fragment for three-word instruction:  */
451 #define TFROM_IND_B	6,  8, B30 | RSIND, 12
452 #define TFROM_ABS16_B	6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST
453 #define TFROM_ABS32_B	6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST
454 
455 #define TFROM_DISP2_B	6,  8, B30 | DISPREG, 12
456 #define TFROM_POSTINC_B	6, 12, B30 | RSPOSTINC, 12
457 #define TFROM_PREINC_B	6, 12, B30 | RSPREINC, 12
458 #define TFROM_POSTDEC_B	6, 12, B30 | RSPOSTDEC, 12
459 #define TFROM_PREDEC_B	6, 12, B30 | RSPREDEC, 12
460 #define TFROM_DISP16_B	6, 14, B30 | DISPREG, 12, DISP16LIST
461 #define TFROM_DISP32_B	6, 10, 2, 12, DISP32LIST
462 #define TFROM_DISP16B_B	6, 14, B30 | DISPREG, 12, DISP16LIST
463 #define TFROM_DISP16W_B	6, 14, B30 | DISPREG, 12, DISP16LIST
464 #define TFROM_DISP16L_B	6, 14, B30 | DISPREG, 12, DISP16LIST
465 #define TFROM_DISP32B_B	6, 10, 2, 12, DISP32LIST
466 #define TFROM_DISP32W_B	6, 10, 2, 12, DISP32LIST
467 #define TFROM_DISP32L_B	6, 10, 2, 12, DISP32LIST
468 
469 #define TFROM_ABS16W_B	6, 10, 1, 12, ABS16LIST
470 #define TFROM_ABS32W_B	6, 10, 3, 12, ABS32LIST
471 
472 /* Extended Operand Class Expanders:  */
473 
474 #define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \
475   {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, SRC_INFIX, TO_IND_MOV,     E}}}, \
476   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \
477   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \
478   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, SRC_INFIX, TO_PREINC_MOV,  E}}}, \
479   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, SRC_INFIX, TO_PREDEC_MOV,  E}}}, \
480   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, SRC_INFIX, TO_DISP2_MOV,   E}}}, \
481   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP16,  DSTDISP16LIST, E}}}, \
482   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP32,  DSTDISP32LIST, E}}}, \
483   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \
484   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \
485   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \
486   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \
487   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \
488   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \
489   {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS16,   DSTABS16LIST,  E}}}, \
490   {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS32,   DSTABS32LIST,  E}}}
491 
492 #define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \
493   {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, SRC_INFIX, TO_IND_MOV,     SRC_SUFFIX, E}}}, \
494   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \
495   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \
496   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, SRC_INFIX, TO_PREINC_MOV,  SRC_SUFFIX, E}}}, \
497   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, SRC_INFIX, TO_PREDEC_MOV,  SRC_SUFFIX, E}}}, \
498   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, SRC_INFIX, TO_DISP2_MOV,   SRC_SUFFIX, E}}}, \
499   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP16,  SRC_SUFFIX, DSTDISP16LIST, E}}}, \
500   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP32,  SRC_SUFFIX, DSTDISP32LIST, E}}}, \
501   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16B, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
502   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16W, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
503   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16L, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
504   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32B, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
505   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32W, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
506   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32L, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
507   {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS16,   SRC_SUFFIX, DSTABS16LIST,  E}}}, \
508   {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS32,   SRC_SUFFIX, DSTABS32LIST,  E}}}
509 
510 #define MOVFROM_IMM8(CODE, PREFIX, NAME, SRC) \
511   {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX,  0, RDIND,     IMM8LIST, E}}}, \
512   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX,  8, RDPOSTINC, IMM8LIST, E}}}, \
513   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, 10, RDPOSTDEC, IMM8LIST, E}}}, \
514   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX,  9, RDPREINC,  IMM8LIST, E}}}, \
515   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, 11, RDPREDEC,  IMM8LIST, E}}}, \
516   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, B30 | B20 | DISP2DST, DSTDISPREG, IMM8LIST, E}}}, \
517   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, 12, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
518   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, 12, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
519   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, 13, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
520   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, 14, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
521   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, 15, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
522   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, 13, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
523   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, 14, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
524   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, 15, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
525   {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX,  4, B30 | IGNORE,     IMM8LIST, DSTABS16LIST,  E}}}, \
526   {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX,  4, B31 | IGNORE,     IMM8LIST, DSTABS32LIST,  E}}}
527 
528 #define MOVFROM_IMM(CODE, PREFIX, NAME, SRC, LIST) \
529   {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, LIST,  0, RDIND,     DATA2, E}}}, \
530   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, LIST,  8, RDPOSTINC, DATA2, E}}}, \
531   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, LIST, 10, RDPOSTDEC, DATA2, E}}}, \
532   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, LIST,  9, RDPREINC,  DATA2, E}}}, \
533   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, LIST, 11, RDPREDEC,  DATA2, E}}}, \
534   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, LIST, B30 | B20 | DISP2DST, DSTDISPREG, DATA2, E}}}, \
535   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, LIST, 12, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
536   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, LIST, 12, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
537   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, LIST, 13, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
538   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, LIST, 14, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
539   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, LIST, 15, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
540   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, LIST, 13, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
541   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, LIST, 14, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
542   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, LIST, 15, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
543   {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX, LIST,  4, B30 | IGNORE,     DATA2, DSTABS16LIST,  E}}}, \
544   {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX, LIST,  4, B31 | IGNORE,     DATA2, DSTABS32LIST,  E}}}
545 
546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
547   {CODE, AV_H8,   4, NAME, {{SRC, RDIND,     E}}, {{                              6, OP1, B31 | RDIND,      SRC,                E}}}, \
548   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 3,                    6, OP3, B31 | RDPOSTINC,  SRC,                E}}}, \
549   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 1,                    6, OP3, B31 | RDPOSTDEC,  SRC,                E}}}, \
550   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, 2,                    6, OP3, B31 | RDPREINC,   SRC,                E}}}, \
551   {CODE, AV_H8,   6, NAME, {{SRC, RDPREDEC,  E}}, {{                              6, OP3, B31 | RDPREDEC,   SRC,                E}}}, \
552   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC,                E}}}, \
553   {CODE, AV_H8,   6, NAME, {{SRC, DISP16DST, E}}, {{                              6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
554   {CODE, AV_H8,   6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0,    6, OP2, 10,               SRC, MEMRELAX | DSTDISP32LIST, E}}}, \
555   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1,                    6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
556   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2,                    6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
557   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3,                    6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
558   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1,    6, OP2, 10,               SRC, DSTDISP32LIST, E}}}, \
559   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2,    6, OP2, 10,               SRC, DSTDISP32LIST, E}}}, \
560   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3,    6, OP2, 10,               SRC, DSTDISP32LIST, E}}}, \
561   {CODE, AV_H8,   4, NAME, {{SRC, ABS16DST,  E}}, {{                              6, OP2, 8,                SRC, RELAX16  | DSTABS16LIST, E}}}, \
562   {CODE, AV_H8,   6, NAME, {{SRC, ABS32DST,  E}}, {{                              6, OP2, 10,               SRC, MEMRELAX | DSTABS32LIST, E}}}
563 
564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
565   {CODE, AV_H8,   4, NAME, {{RSIND,     DST, E}}, {{                              6, OP1, B30 | RSIND,     DST,             E}}}, \
566   {CODE, AV_H8,   6, NAME, {{RSPOSTINC, DST, E}}, {{                              6, OP3, B30 | RSPOSTINC, DST,             E}}}, \
567   {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, 2,                    6, OP3, B30 | RSPOSTDEC, DST,             E}}}, \
568   {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  DST, E}}, {{PREFIX, 1,                    6, OP3, B30 | RSPREINC,  DST,             E}}}, \
569   {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  DST, E}}, {{PREFIX, 3,                    6, OP3, B30 | RSPREDEC,  DST,             E}}}, \
570   {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG,   DST,             E}}}, \
571   {CODE, AV_H8,   6, NAME, {{DISP16SRC, DST, E}}, {{                              6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
572   {CODE, AV_H8,   6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0,       6, OP2, 2,               DST, MEMRELAX | DISP32LIST, E}}}, \
573   {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  DST, E}}, {{PREFIX, 1,                    6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
574   {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  DST, E}}, {{PREFIX, 2,                    6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
575   {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  DST, E}}, {{PREFIX, 3,                    6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
576   {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  DST, E}}, {{7, 8, B30 | DISPREG, 1,       6, OP2, 2,               DST, DISP32LIST, E}}}, \
577   {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  DST, E}}, {{7, 8, B30 | DISPREG, 2,       6, OP2, 2,               DST, DISP32LIST, E}}}, \
578   {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  DST, E}}, {{7, 8, B30 | DISPREG, 3,       6, OP2, 2,               DST, DISP32LIST, E}}}, \
579   {CODE, AV_H8,   4, NAME, {{ABS16SRC,  DST, E}}, {{                              6, OP2, 0,               DST, RELAX16  | ABS16LIST, E}}}, \
580   {CODE, AV_H8,   6, NAME, {{ABS32SRC,  DST, E}}, {{                              6, OP2, 2,               DST, MEMRELAX | ABS32LIST, E}}}
581 
582 /* Expansion macros for two-word (plus data) instructions.  */
583 
584 /* Expansion from one source to "standard" destinations.  */
585 #define EXPAND2_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, NIB1, NIB2) \
586   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, NIB1, NIB2, E}}}, \
587   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, NIB1, NIB2, E}}}, \
588   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, TO_PREINC,  NIB1, NIB2, E}}}, \
589   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, TO_PREDEC,  NIB1, NIB2, E}}}, \
590   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, TO_DISP2,   NIB1, NIB2, E}}}, \
591   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16,  NIB1, NIB2, DSTDISP16LIST, E}}}, \
592   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32,  NIB1, NIB2, DSTDISP32LIST, E}}}, \
593   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \
594   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \
595   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \
596   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \
597   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \
598   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}}
599 
600 /* Expansion from one destination to "standard" sources.  */
601 #define EXPAND2_STD_DST(CODE, WEIGHT, NAME, DST, PREFIX, NIB1, NIB2) \
602   {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, DST, E}}, {{PREFIX, FROM_POSTINC, NIB1, NIB2, E}}}, \
603   {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, FROM_POSTDEC, NIB1, NIB2, E}}}, \
604   {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  DST, E}}, {{PREFIX, FROM_PREINC,  NIB1, NIB2, E}}}, \
605   {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  DST, E}}, {{PREFIX, FROM_PREDEC,  NIB1, NIB2, E}}}, \
606   {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  DST, E}}, {{PREFIX, FROM_DISP2,   NIB1, NIB2, E}}}, \
607   {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, DST, E}}, {{PREFIX, FROM_DISP16,  NIB1, NIB2, DISP16LIST, E}}}, \
608   {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, DST, E}}, {{PREFIX, FROM_DISP32,  NIB1, NIB2, DISP32LIST, E}}}, \
609   {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  DST, E}}, {{PREFIX, FROM_DISP16B, NIB1, NIB2, DISP16LIST, E}}}, \
610   {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  DST, E}}, {{PREFIX, FROM_DISP16W, NIB1, NIB2, DISP16LIST, E}}}, \
611   {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  DST, E}}, {{PREFIX, FROM_DISP16L, NIB1, NIB2, DISP16LIST, E}}}, \
612   {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  DST, E}}, {{PREFIX, FROM_DISP32B, NIB1, NIB2, DISP32LIST, E}}}, \
613   {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  DST, E}}, {{PREFIX, FROM_DISP32W, NIB1, NIB2, DISP32LIST, E}}}, \
614   {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  DST, E}}, {{PREFIX, FROM_DISP32L, NIB1, NIB2, DISP32LIST, E}}}
615 
616 /* Expansion from immediate source to "standard" destinations.  */
617 #define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
618   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
619   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
620   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, TO_PREINC,  OPCODE, IGN, IMMLIST, E}}}, \
621   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, TO_PREDEC,  OPCODE, IGN, IMMLIST, E}}}, \
622   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, TO_DISP2,   OPCODE, IGN, IMMLIST, E}}}, \
623   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16,  OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
624   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32,  OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
625   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
626   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
627   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
628   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
629   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
630   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}
631 
632 /* Expansion from abs/disp source to "standard" destinations.  */
633 #define EXPAND2_STD_ABSDISP(CODE, WEIGHT, NAME, SRC, PREFIX, DSTLIST, NIB1, NIB2) \
634   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, DSTLIST, TO_POSTINC, NIB1, NIB2, E}}}, \
635   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, DSTLIST, TO_POSTDEC, NIB1, NIB2, E}}}, \
636   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, DSTLIST, TO_PREINC,  NIB1, NIB2, E}}}, \
637   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, DSTLIST, TO_PREDEC,  NIB1, NIB2, E}}}, \
638   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, DSTLIST, TO_DISP2,   NIB1, NIB2, E}}}, \
639   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, DSTLIST, TO_DISP16,  NIB1, NIB2, DSTDISP16LIST, E}}}, \
640   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, DSTLIST, TO_DISP32,  NIB1, NIB2, DSTDISP32LIST, E}}}, \
641   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, DSTLIST, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \
642   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, DSTLIST, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \
643   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, DSTLIST, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \
644   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, DSTLIST, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \
645   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, DSTLIST, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \
646   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, DSTLIST, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}}
647 
648 /* Expansion from ind source to "standard" destinations.  */
649 #define EXPAND2_STD_IND(CODE, WEIGHT, NAME, OPCODE, BIT) \
650   {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTINC, OPCODE, IGNORE, E}}}, \
651   {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTDEC, OPCODE, IGNORE, E}}}, \
652   {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREINC,  E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREINC,  OPCODE, IGNORE, E}}}, \
653   {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREDEC,  E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREDEC,  OPCODE, IGNORE, E}}}, \
654   {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP2DST,  E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP2,   OPCODE, IGNORE, E}}}, \
655   {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP16DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16,  OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
656   {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP32DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32,  OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
657   {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16B, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
658   {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16W, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
659   {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16L, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
660   {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32B, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
661   {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32W, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
662   {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32L, OPCODE, IGNORE, DSTDISP32LIST, E}}}
663 
664 /* Expansion macros for three word (plus data) instructions.  */
665 
666 #define EXPAND3_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE)  \
667   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX,  8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \
668   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \
669   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, INFIX,  9, RDPREINC,  OPCODE, B30 | IGNORE, E}}}, \
670   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, INFIX, 11, RDPREDEC,  OPCODE, B30 | IGNORE, E}}}, \
671   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \
672   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
673   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
674   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
675   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
676   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
677   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
678   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
679   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}
680 
681 #define EXPAND3_L_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE)  \
682   {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}}, {{PREFIX, INFIX,  0, RDIND,     OPCODE, B30 | IGNORE, E}}}, \
683   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX,  8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \
684   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \
685   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, INFIX,  9, RDPREINC,  OPCODE, B30 | IGNORE, E}}}, \
686   {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, INFIX, 11, RDPREDEC,  OPCODE, B30 | IGNORE, E}}}, \
687   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \
688   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
689   {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
690   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
691   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
692   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
693   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
694   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
695   {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
696   {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}}, {{PREFIX, INFIX,  4, B30 | IGNORE,     OPCODE, B30 | IGNORE, DSTABS16LIST,  E}}}, \
697   {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}}, {{PREFIX, INFIX,  4, B31 | IGNORE,     OPCODE, B30 | IGNORE, DSTABS32LIST,  E}}}
698 
699 
700 #define EXPAND_STD_MATRIX_L(CODE, NAME, OPCODE) \
701   EXPAND3_L_SRC (CODE, 6, NAME, RSIND,     PREFIX_0104,   TFROM_IND,     OPCODE), \
702   EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTINC, PREFIX_0104,   TFROM_POSTINC, OPCODE), \
703   EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTDEC, PREFIX_0106,   TFROM_POSTDEC, OPCODE), \
704   EXPAND3_L_SRC (CODE, 6, NAME, RSPREINC,  PREFIX_0105,   TFROM_PREINC,  OPCODE), \
705   EXPAND3_L_SRC (CODE, 6, NAME, RSPREDEC,  PREFIX_0107,   TFROM_PREDEC,  OPCODE), \
706   EXPAND3_L_SRC (CODE, 6, NAME, DISP2SRC,  PREFIX_010_D2, TFROM_DISP2,   OPCODE), \
707   EXPAND3_L_SRC (CODE, 6, NAME, DISP16SRC, PREFIX_0104,   TFROM_DISP16,  OPCODE), \
708   EXPAND3_L_SRC (CODE, 6, NAME, DISP32SRC, PREFIX_78R4,   TFROM_DISP32,  OPCODE), \
709   EXPAND3_L_SRC (CODE, 6, NAME, INDEXB16,  PREFIX_0105,   TFROM_DISP16B, OPCODE), \
710   EXPAND3_L_SRC (CODE, 6, NAME, INDEXW16,  PREFIX_0106,   TFROM_DISP16W, OPCODE), \
711   EXPAND3_L_SRC (CODE, 6, NAME, INDEXL16,  PREFIX_0107,   TFROM_DISP16L, OPCODE), \
712   EXPAND3_L_SRC (CODE, 6, NAME, INDEXB32,  PREFIX_78R5,   TFROM_DISP32B, OPCODE), \
713   EXPAND3_L_SRC (CODE, 6, NAME, INDEXW32,  PREFIX_78R6,   TFROM_DISP32W, OPCODE), \
714   EXPAND3_L_SRC (CODE, 6, NAME, INDEXL32,  PREFIX_78R7,   TFROM_DISP32L, OPCODE), \
715   EXPAND3_L_SRC (CODE, 6, NAME, ABS16SRC,  PREFIX_0104,   TFROM_ABS16,   OPCODE), \
716   EXPAND3_L_SRC (CODE, 6, NAME, ABS32SRC,  PREFIX_0104,   TFROM_ABS32,   OPCODE)
717 
718 
719 #define EXPAND_STD_MATRIX_W(CODE, NAME, OPCODE) \
720   EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0154,   TFROM_POSTINC, OPCODE), \
721   EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0156,   TFROM_POSTDEC, OPCODE), \
722   EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC,  PREFIX_0155,   TFROM_PREINC,  OPCODE), \
723   EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC,  PREFIX_0157,   TFROM_PREDEC,  OPCODE), \
724   EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC,  PREFIX_015_D2, TFROM_DISP2,   OPCODE), \
725   EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0154,   TFROM_DISP16,  OPCODE), \
726   EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W,  TFROM_DISP32,  OPCODE), \
727   EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16,  PREFIX_0155,   TFROM_DISP16B, OPCODE), \
728   EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16,  PREFIX_0156,   TFROM_DISP16W, OPCODE), \
729   EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16,  PREFIX_0157,   TFROM_DISP16L, OPCODE), \
730   EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32,  PREFIX_78R5W,  TFROM_DISP32B, OPCODE), \
731   EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32,  PREFIX_78R6W,  TFROM_DISP32W, OPCODE), \
732   EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32,  PREFIX_78R7W,  TFROM_DISP32L, OPCODE)
733 
734 #define EXPAND_STD_MATRIX_B(CODE, NAME, OPCODE) \
735   EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0174,    TFROM_POSTINC_B, OPCODE), \
736   EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0176,    TFROM_POSTDEC_B, OPCODE), \
737   EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC,  PREFIX_0175,    TFROM_PREINC_B,  OPCODE), \
738   EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC,  PREFIX_0177,    TFROM_PREDEC_B,  OPCODE), \
739   EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC,  PREFIX_017_D2S, TFROM_DISP2_B,   OPCODE), \
740   EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0174,    TFROM_DISP16_B,  OPCODE), \
741   EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W,   TFROM_DISP32_B,  OPCODE), \
742   EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16,  PREFIX_0175,    TFROM_DISP16B_B, OPCODE), \
743   EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16,  PREFIX_0176,    TFROM_DISP16W_B, OPCODE), \
744   EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16,  PREFIX_0177,    TFROM_DISP16L_B, OPCODE), \
745   EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32,  PREFIX_78R5W,   TFROM_DISP32B_B, OPCODE), \
746   EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32,  PREFIX_78R6W,   TFROM_DISP32W_B, OPCODE), \
747   EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32,  PREFIX_78R7W,   TFROM_DISP32L_B, OPCODE)
748 
749 
750 /* Use the expansion macros to fill out the opcode table.  */
751 
752 #define EXPAND_FROM_REG8(CODE, NAME, OP1, OP2, OP3) \
753   {CODE, AV_H8SX, 0, NAME, {{RS8, RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,             OP1, OP2, RS8, IGNORE, E}}}, \
754   EXPAND2_STD_SRC (CODE, 2, NAME, RS8, PREFIX_0179, OP3, RS8), \
755   {CODE, AV_H8SX, 0, NAME, {{RS8, ABS8DST,   E}}, {{0x7, 0xf, DSTABS8LIST,                     OP1, OP2, RS8, IGNORE, E}}}, \
756   {CODE, AV_H8SX, 0, NAME, {{RS8, ABS16DST,  E}}, {{0x6, 0xa, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS8, IGNORE, E}}}, \
757   {CODE, AV_H8SX, 0, NAME, {{RS8, ABS32DST,  E}}, {{0x6, 0xa, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS8, IGNORE, E}}}
758 
759 #define EXPAND_TO_REG8(CODE, NAME, OP1, OP2, OP3) \
760   {CODE, AV_H8SX, 0, NAME, {{RSIND, RD8,     E}}, {{0x7, 0xc, B30 | RSIND, IGNORE,          OP1, OP2, IGNORE, RD8, E}}}, \
761   EXPAND2_STD_DST (CODE, 2, NAME, RD8, PREFIX_017A, OP3, RD8), \
762   {CODE, AV_H8SX, 0, NAME, {{ABS8SRC,  RD8,  E}}, {{0x7, 0xe, ABS8LIST,                     OP1, OP2, IGNORE, RD8, E}}}, \
763   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD8,  E}}, {{0x6, 0xa, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD8, E}}}, \
764   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD8,  E}}, {{0x6, 0xa, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD8, E}}}
765 
766 #define EXPAND_FROM_IND8(CODE, NAME, OPCODE) \
767   {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND,    E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_IND,   OPCODE, IGNORE, E}}}, \
768   EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B30), \
769   {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
770   {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
771 
772 #define EXPAND_FROM_ABS16_B(CODE, NAME, OPCODE) \
773   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND,    E}}, {{PREFIX_6A15, ABS16LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
774   EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6A15, ABS16LIST, OPCODE, IGNORE), \
775   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
776   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
777 
778 #define EXPAND_FROM_ABS32_B(CODE, NAME, OPCODE) \
779   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND,    E}}, {{PREFIX_6A35, ABS32LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
780   EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6A35, ABS32LIST, OPCODE, IGNORE), \
781   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
782   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
783 
784 #define EXPAND_FROM_IMM16_W(CODE, NAME, OPCODE) \
785   {CODE, AV_H8SX, 0, NAME, {{IMM16, RDIND,    E}}, {{PREFIX_015E, TO_IND, OPCODE, IGNORE, IMM16LIST, E}}}, \
786   EXPAND2_STD_IMM (CODE, 2, NAME, IMM16, PREFIX_015E, OPCODE, IGNORE, IMM16LIST), \
787   {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS16DST, E}}, {{PREFIX_015E, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, IMM16LIST, E}}}, \
788   {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS32DST, E}}, {{PREFIX_015E, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, IMM16LIST, E}}}
789 
790 #define EXPAND_FROM_REG16(CODE, NAME, OP1, OP2, OP3) \
791   {CODE, AV_H8,   2, NAME, {{RS16, RDIND,    E}}, {{0x7, 0xd, B31 | RDIND, IGNORE,             OP1, OP2, RS16, IGNORE, E}}}, \
792   EXPAND2_STD_SRC (CODE, 2, NAME, RS16, PREFIX_0159, OP3, RS16), \
793   {CODE, AV_H8SX, 0, NAME, {{RS16, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS16, IGNORE, E}}}, \
794   {CODE, AV_H8SX, 0, NAME, {{RS16, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS16, IGNORE, E}}}
795 
796 #define EXPAND_TO_REG16(CODE, NAME, OP1, OP2, OP3) \
797   {CODE, AV_H8SX, 0, NAME, {{RSIND, RD16,    E}}, {{0x7, 0xc, B31 | RSIND, IGNORE,          OP1, OP2, IGNORE, RD16, E}}}, \
798   EXPAND2_STD_DST (CODE, 2, NAME, RD16, PREFIX_015A, OP3, RD16), \
799   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD16, E}}, {{0x6, 0xb, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD16, E}}}, \
800   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD16, E}}, {{0x6, 0xb, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD16, E}}}
801 
802 #define EXPAND_FROM_IND16(CODE, NAME, OPCODE) \
803   {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND,    E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \
804   EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B31), \
805   {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
806   {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
807 
808 #define EXPAND_FROM_ABS16_W(CODE, NAME, OPCODE) \
809   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND,    E}}, {{PREFIX_6B15, ABS16LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
810   EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6B15, ABS16LIST, OPCODE, IGNORE), \
811   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
812   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
813 
814 #define EXPAND_FROM_ABS32_W(CODE, NAME, OPCODE) \
815   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND,    E}}, {{PREFIX_6B35, ABS32LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
816   EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6B35, ABS32LIST, OPCODE, IGNORE), \
817   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
818   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
819 
820 #define EXPAND_FROM_IMM16_L(CODE, NAME, OPCODE) \
821   {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RDIND,    E}}, {{PREFIX_010E, TO_IND, OPCODE, B30 | IGNORE, IMM16ULIST, E}}}, \
822   EXPAND2_STD_IMM (CODE, 2, NAME, IMM16U_NS, PREFIX_010E, OPCODE, B30 | IGNORE, IMM16ULIST), \
823   {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B30 | IGNORE, DSTABS16LIST, IMM16ULIST, E}}}, \
824   {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B30 | IGNORE, DSTABS32LIST, IMM16ULIST, E}}}
825 
826 #define EXPAND_FROM_IMM32_L(CODE, NAME, OPCODE) \
827   {CODE, AV_H8SX, 0, NAME, {{IMM32, RDIND,    E}}, {{PREFIX_010E, TO_IND, OPCODE, B31 | IGNORE, IMM32LIST, E}}}, \
828   EXPAND2_STD_IMM (CODE, 2, NAME, IMM32, PREFIX_010E, OPCODE, B31 | IGNORE, IMM32LIST), \
829   {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B31 | IGNORE, DSTABS16LIST, IMM32LIST, E}}}, \
830   {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B31 | IGNORE, DSTABS32LIST, IMM32LIST, E}}}
831 
832 #define EXPAND_FROM_REG32(CODE, NAME, OPCODE) \
833   {CODE, AV_H8SX, 0, NAME, {{RS32, RDIND,    E}}, {{PREFIX_0109, TO_IND,   OPCODE, B30 | RS32, E}}}, \
834   EXPAND2_STD_SRC (CODE, 2, NAME, RS32, PREFIX_0109, OPCODE, B30 | RS32), \
835   {CODE, AV_H8SX, 0, NAME, {{RS32, ABS16DST, E}}, {{PREFIX_0109, TO_ABS16, OPCODE, B30 | RS32, DSTABS16LIST, E}}}, \
836   {CODE, AV_H8SX, 0, NAME, {{RS32, ABS32DST, E}}, {{PREFIX_0109, TO_ABS32, OPCODE, B30 | RS32, DSTABS32LIST, E}}}
837 
838 #define EXPAND_TO_REG32(CODE, NAME, OPCODE) \
839   {CODE, AV_H8SX, 0, NAME, {{RSIND, RD32,    E}}, {{PREFIX_010A, FROM_IND,   OPCODE, B30 | RD32, E}}}, \
840   EXPAND2_STD_DST (CODE, 2, NAME, RD32, PREFIX_010A, OPCODE, B30 | RD32), \
841   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS16, OPCODE, B30 | RD32, ABS16LIST, E}}}, \
842   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS32, OPCODE, B30 | RD32, ABS32LIST, E}}}
843 
844 
845 #define EXPAND_TWOOP_B(CODE, NAME, OP1, OP2, OP3, OP4, BIT) \
846   {CODE, AV_H8SX, 0, NAME, {{IMM8, RDIND,     E}}, {{0x7, 0xd,                 B30 | RDIND,            IGNORE,                      OP1, BIT | IGNORE, IMM8LIST, E}}}, \
847   {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTINC, E}}, {{PREFIX_0174,    0x6, 0xc, B30 | RDPOSTINC,  B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
848   {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176,    0x6, 0xc, B30 | RDPOSTDEC,  B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
849   {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREINC,  E}}, {{PREFIX_0175,    0x6, 0xc, B30 | RDPREINC,   B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
850   {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREDEC,  E}}, {{PREFIX_0177,    0x6, 0xc, B30 | RDPREDEC,   B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
851   {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP2DST,  E}}, {{PREFIX_017_D2D, 0x6, 0x8, B30 | DSTDISPREG, B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
852   {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP16DST, E}}, {{PREFIX_0174,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
853   {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP32DST, E}}, {{PREFIX_78R4WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
854   {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB16D, E}}, {{PREFIX_0175,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
855   {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW16D, E}}, {{PREFIX_0176,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
856   {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL16D, E}}, {{PREFIX_0177,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
857   {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB32D, E}}, {{PREFIX_78R5WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
858   {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW32D, E}}, {{PREFIX_78R6WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
859   {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL32D, E}}, {{PREFIX_78R7WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
860   {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS8DST,   E}}, {{0x7, 0xf,                                                       DSTABS8LIST,   OP1, BIT | IGNORE, IMM8LIST, E}}}, \
861   {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS16DST,  E}}, {{0x6, 0xa, 0x1,                              B31 | B20 | IGNORE, DSTABS16LIST,  OP1, BIT | IGNORE, IMM8LIST, E}}}, \
862   {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS32DST,  E}}, {{0x6, 0xa, 0x3,                              B31 | B20 | IGNORE, DSTABS32LIST,  OP1, BIT | IGNORE, IMM8LIST, E}}}, \
863   {CODE, AV_H8,   2, NAME, {{RS8,  RD8,       E}}, {{OP2, OP3, RS8, RD8, E}}}, \
864   EXPAND_FROM_REG8      (CODE, NAME, OP2, OP3, OP4), \
865   EXPAND_TO_REG8        (CODE, NAME, OP2, OP3, OP4), \
866   EXPAND_FROM_IND8      (CODE, NAME, OP4), \
867   EXPAND_STD_MATRIX_B   (CODE, NAME, OP4), \
868   EXPAND_FROM_ABS16_B   (CODE, NAME, OP4), \
869   EXPAND_FROM_ABS32_B   (CODE, NAME, OP4)
870 
871 #define EXPAND_TWOOP_W(CODE, NAME, OP1, OP2, OP3) \
872   {CODE, AV_H8H,  6, NAME, {{IMM16, RD16, E}}, {{0x7, 0x9, OP3, RD16, IMM16LIST, E}}}, \
873   EXPAND_FROM_IMM16_W   (CODE, NAME, OP3), \
874   EXPAND_FROM_REG16     (CODE, NAME, OP1, OP2, OP3), \
875   EXPAND_TO_REG16       (CODE, NAME, OP1, OP2, OP3), \
876   EXPAND_FROM_IND16     (CODE, NAME, OP3), \
877   EXPAND_STD_MATRIX_W   (CODE, NAME, OP3), \
878   EXPAND_FROM_ABS16_W   (CODE, NAME, OP3), \
879   EXPAND_FROM_ABS32_W   (CODE, NAME, OP3)
880 
881 #define EXPAND_TWOOP_L(CODE, NAME, OP1)  \
882   {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, OP1, B31 | RD32, IMM16ULIST, E}}}, \
883   {CODE, AV_H8H,  6, NAME, {{IMM32,     RD32, E}}, {{0x7, 0xa, OP1, B30 | RD32, IMM32LIST,  E}}}, \
884   EXPAND_FROM_IMM16_L   (CODE, NAME, OP1), \
885   EXPAND_FROM_IMM32_L   (CODE, NAME, OP1), \
886   EXPAND_FROM_REG32     (CODE, NAME, OP1), \
887   EXPAND_TO_REG32       (CODE, NAME, OP1), \
888   EXPAND_STD_MATRIX_L   (CODE, NAME, OP1)
889 
890 
891 /* Old expanders:  */
892 
893 #define BITOP(code, imm, name, op00, op01, op10,  op11, op20, op21, op30, op4) \
894   {code, AV_H8,  2, name, {{imm, RD8,      E}}, {{op00, op01, imm,  RD8,   E}}}, \
895   {code, AV_H8,  6, name, {{imm, RDIND,    E}}, {{op10, op11, B30 | RDIND, 0,  op00, op01, imm, 0, E}}}, \
896   {code, AV_H8,  6, name, {{imm, ABS8DST,  E}}, {{op20, op21, DSTABS8LIST,     op00, op01, imm, 0, E}}}, \
897   {code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6,  0xa,  0x1,  op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \
898   {code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6,  0xa,  0x3,  op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}}
899 
900 #define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
901   {code, AV_H8SX, 0, name, {{imm, RDIND,    E}}, {{op10, op11, B30 | RDIND, 0,  op00, op01, imm, op4, E}}}, \
902   {code, AV_H8SX, 0, name, {{imm, ABS8DST,  E}}, {{op20, op21, DSTABS8LIST,     op00, op01, imm, op4, E}}}, \
903   {code, AV_H8SX, 0, name, {{imm, ABS16DST, E}}, {{0x6,  0xa,  0x1,  op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \
904   {code, AV_H8SX, 0, name, {{imm, ABS32DST, E}}, {{0x6,  0xa,  0x3,  op30, DST | ABS32LIST, op00, op01, imm, op4, E}}}
905 
906 #define EBITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
907   BITOP(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \
908   BITOP(code, RS8, name, op00,   op01, op10, op11, op20, op21, op30, op4)
909 
910 #define EBITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
911   BITOP_B(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \
912   BITOP_B(code, RS8, name, op00,   op01, op10, op11, op20, op21, op30, op4)
913 
914 #define WTWOP(code, name, op1, op2) \
915   {code, AV_H8, 2, name, {{RS16, RD16, E}}, {{op1, op2, RS16, RD16, E}}}
916 
917 #define BRANCH(code, name, op) \
918   {code, AV_H8H, 6, name, {{PCREL16, E}}, {{0x5, 0x8, op, 0x0, PCREL16, DATA3 | B00, E}}}, \
919   {code, AV_H8,  4, name, {{PCREL8,  E}}, {{0x4, op,           PCREL8,  DATA  | B00, E}}}
920 
921 
922 #define UNOP(code, name, op1, op2) \
923   {code, AV_H8, 2, name, {{OR8, E}}, {{op1, op2, 0, OR8, E}}}
924 
925 #define EXPAND_UNOP_STD_B(CODE, NAME, PREFIX, OP1, OP2, OP3) \
926   {CODE, AV_H8,   2, NAME, {{OR8,       E}}, {{                                                                  OP1, OP2, OP3, OR8,    E}}}, \
927   {CODE, AV_H8SX, 0, NAME, {{RSIND,     E}}, {{           7, 13, B30 | RSIND,             IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
928   {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RSPOSTINC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
929   {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RSPOSTDEC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
930   {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  E}}, {{PREFIX, 5, 6, 12, B30 | RSPREINC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
931   {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  E}}, {{PREFIX, 7, 6, 12, B30 | RSPREDEC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
932   {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6,  8, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
933   {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
934   {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
935   {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  E}}, {{PREFIX, 5, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
936   {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  E}}, {{PREFIX, 6, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
937   {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  E}}, {{PREFIX, 7, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
938   {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  E}}, {{7, 8, B30 | DISPREG, 5,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
939   {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  E}}, {{7, 8, B30 | DISPREG, 6,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
940   {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  E}}, {{7, 8, B30 | DISPREG, 7,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
941   {CODE, AV_H8SX, 0, NAME, {{ABS8SRC,   E}}, {{                           7, 15,                   ABS8LIST,     OP1, OP2, OP3, IGNORE, E}}}, \
942   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC,  E}}, {{                           6, 10, 1, B31 | IGNORE,  ABS16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
943   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC,  E}}, {{                           6, 10, 3, B31 | IGNORE,  ABS32LIST,    OP1, OP2, OP3, IGNORE, E}}}
944 
945 #define EXPAND_UNOP_STD_W(CODE, NAME, PREFIX, OP1, OP2, OP3) \
946   {CODE, AV_H8H,  2, NAME, {{OR16,      E}}, {{                                                                  OP1, OP2, OP3, OR16,   E}}}, \
947   {CODE, AV_H8SX, 0, NAME, {{RSIND,     E}}, {{           7, 13, B31 | RSIND,             IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
948   {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
949   {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
950   {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
951   {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
952   {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6,  9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
953   {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
954   {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
955   {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
956   {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
957   {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
958   {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  E}}, {{7, 8, B30 | DISPREG, 5,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
959   {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  E}}, {{7, 8, B30 | DISPREG, 6,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
960   {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  E}}, {{7, 8, B30 | DISPREG, 7,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
961   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC,  E}}, {{                           6, 11, 1, B31 | IGNORE,  ABS16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
962   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC,  E}}, {{                           6, 11, 3, B31 | IGNORE,  ABS32LIST,    OP1, OP2, OP3, IGNORE, E}}}
963 
964 #define EXPAND_UNOP_STD_L(CODE, NAME, PREFIX, OP1, OP2, OP3) \
965   {CODE, AV_H8H,  2, NAME, {{OR32,      E}}, {{                                                                  OP1, OP2, OP3, B30 | OR32,   E}}}, \
966   {CODE, AV_H8SX, 0, NAME, {{RSIND,     E}}, {{PREFIX, 4, 6,  9, B30 | RSIND,       B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
967   {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC,   B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
968   {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC,   B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
969   {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC,    B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
970   {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC,    B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
971   {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6,  9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
972   {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
973   {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B31 | DISPREG, 4,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
974   {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
975   {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
976   {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
977   {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  E}}, {{7, 8, B31 | DISPREG, 5,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
978   {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  E}}, {{7, 8, B31 | DISPREG, 6,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
979   {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  E}}, {{7, 8, B31 | DISPREG, 7,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
980   {CODE, AV_H8SX, 0, NAME, {{ABS16SRC,  E}}, {{PREFIX, 4,                 6, 11, 0, B31 | IGNORE,  ABS16LIST,    OP1, OP2, OP3, B30 | IGNORE, E}}}, \
981   {CODE, AV_H8SX, 0, NAME, {{ABS32SRC,  E}}, {{PREFIX, 4,                 6, 11, 2, B31 | IGNORE,  ABS32LIST,    OP1, OP2, OP3, B30 | IGNORE, E}}}
982 
983 #define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \
984   {CODE, AV_H8,   2, NAME, {{CONST, RD8,       E}}, {{                                                                     OP1, OP2, OP3, RD8,    E}}}, \
985   {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND,     E}}, {{           7, 13, B30 | RDIND,             IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
986   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RDPOSTINC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
987   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RDPOSTDEC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
988   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC,  E}}, {{PREFIX, 5, 6, 12, B30 | RDPREINC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
989   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC,  E}}, {{PREFIX, 7, 6, 12, B30 | RDPREDEC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
990   {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST,  E}}, {{PREFIX, B30 | B21 | DISP2DST, 6,  8, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
991   {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
992   {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
993   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
994   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
995   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
996   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
997   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
998   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
999   {CODE, AV_H8SX, 0, NAME, {{CONST, ABS8DST,   E}}, {{                           7, 15,                  DSTABS8LIST,      OP1, OP2, OP3, IGNORE, E}}}, \
1000   {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST,  E}}, {{                           6, 10, 1, B31 | IGNORE, DSTABS16LIST,     OP1, OP2, OP3, IGNORE, E}}}, \
1001   {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST,  E}}, {{                           6, 10, 3, B31 | IGNORE, DSTABS32LIST,     OP1, OP2, OP3, IGNORE, E}}}
1002 
1003 #define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \
1004   {CODE, AV_H8,   2, NAME, {{CONST, RD16,      E}}, {{                                                                     OP1, OP2, OP3, RD16,   E}}}, \
1005   {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND,     E}}, {{           7, 13, B31 | RDIND,             IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
1006   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
1007   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
1008   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
1009   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
1010   {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST,  E}}, {{PREFIX, B30 | B21 | DISP2DST, 6,  9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
1011   {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
1012   {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
1013   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
1014   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
1015   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
1016   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
1017   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
1018   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
1019   {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST,  E}}, {{                           6, 11, 1, B31 | IGNORE, DSTABS16LIST,     OP1, OP2, OP3, IGNORE, E}}}, \
1020   {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST,  E}}, {{                           6, 11, 3, B31 | IGNORE, DSTABS32LIST,     OP1, OP2, OP3, IGNORE, E}}}
1021 
1022 #define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \
1023   {CODE, AV_H8,   2, NAME, {{CONST, RD32,      E}}, {{                                                                     OP1, OP2, OP3, BIT | RD32,   E}}}, \
1024   {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND,     E}}, {{PREFIX, 4, 6,  9, B30 | RDIND,       B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1025   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC,   B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1026   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC,   B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1027   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC,    B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1028   {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC,    B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1029   {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST,  E}}, {{PREFIX, B30 | B21 | DISP2DST, 6,  9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1030   {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1031   {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B31 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1032   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1033   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1034   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1035   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B31 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1036   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B31 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1037   {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B31 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1038   {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST,  E}}, {{PREFIX, 4,                 6, 11, 0, B31 | IGNORE, DSTABS16LIST,     OP1, OP2, OP3, BIT | IGNORE, E}}}, \
1039   {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST,  E}}, {{PREFIX, 4,                 6, 11, 2, B31 | IGNORE, DSTABS32LIST,     OP1, OP2, OP3, BIT | IGNORE, E}}}
1040 
1041 #define PREFIXLDC 0x0, 0x1, 0x4, B30 | CCR_EXR | DST
1042 #define PREFIXSTC 0x0, 0x1, 0x4, B30 | CCR_EXR | SRC
1043 
1044 #define O(op, size)  (op * 4 + size)
1045 #define OP_SIZE(HOW) (HOW % 4)
1046 #define OP_KIND(HOW) (HOW / 4)
1047 
1048 enum h8_asm_codes
1049 {
1050   O_RECOMPILE =	 0,
1051   O_ADD,
1052   O_ADDX,
1053   O_AND,
1054   O_BAND,
1055   O_BRA,
1056   O_BRAB,
1057   O_BRAW,
1058   O_BRAL,
1059   O_BRAS,
1060   O_BRABC,
1061   O_BRABS,
1062   O_BSRBC,
1063   O_BSRBS,
1064   O_BRN,
1065   O_BHI,
1066   O_BLS,
1067   O_BCC,
1068   O_BCS,
1069   O_BNE,
1070   O_BVC,
1071   O_BVS,
1072   O_BPL,
1073   O_BMI,
1074   O_BGE,
1075   O_BLT,
1076   O_BGT,
1077   O_BLE,
1078   O_ANDC,
1079   O_BEQ,
1080   O_BCLR,
1081   O_BCLREQ,
1082   O_BCLRNE,
1083   O_BSETEQ,
1084   O_BSETNE,
1085   O_BFLD,
1086   O_BFST,
1087   O_BIAND,
1088   O_BILD,
1089   O_BIOR,
1090   O_BIXOR,
1091   O_BIST,
1092   O_BISTZ,
1093   O_BLD,
1094   O_BNOT,
1095   O_BOR,
1096   O_BSET,
1097   O_BSR,
1098   O_BXOR,
1099   O_CMP,
1100   O_DAA,
1101   O_DAS,
1102   O_DEC,
1103   O_DIVU,
1104   O_DIVS,
1105   O_DIVXU,
1106   O_DIVXS,
1107   O_INC,
1108   O_LDC,
1109   O_MOV,
1110   O_MOVAB,
1111   O_MOVAW,
1112   O_MOVAL,
1113   O_MOVMD,
1114   O_MOVSD,
1115   O_OR,
1116   O_ROTL,
1117   O_ROTR,
1118   O_ROTXL,
1119   O_ROTXR,
1120   O_BPT,
1121   O_SHAL,
1122   O_SHAR,
1123   O_SHLL,
1124   O_SHLR,
1125   O_SUB,
1126   O_SUBS,
1127   O_TRAPA,
1128   O_XOR,
1129   O_XORC,
1130   O_BST,
1131   O_BSTZ,
1132   O_BTST,
1133   O_EEPMOV,
1134   O_EXTS,
1135   O_EXTU,
1136   O_JMP,
1137   O_JSR,
1138   O_MULU,
1139   O_MULUU,
1140   O_MULS,
1141   O_MULSU,
1142   O_MULXU,
1143   O_MULXS,
1144   O_NOP,
1145   O_NOT,
1146   O_ORC,
1147   O_RTE,
1148   O_RTEL,
1149   O_STC,
1150   O_SUBX,
1151   O_NEG,
1152   O_RTS,
1153   O_RTSL,
1154   O_SLEEP,
1155   O_ILL,
1156   O_ADDS,
1157   O_SYSCALL,
1158   O_TAS,
1159   O_CLRMAC,
1160   O_LDMAC,
1161   O_MAC,
1162   O_LDM,
1163   O_STM,
1164   O_STMAC,
1165   O_LAST,
1166   /* Change made for System Call processing.  */
1167   O_SYS_CREAT,
1168   O_SYS_OPEN,
1169   O_SYS_READ,
1170   O_SYS_WRITE,
1171   O_SYS_LSEEK,
1172   O_SYS_CLOSE,
1173   O_SYS_STAT,
1174   O_SYS_FSTAT,
1175 /* Space reserved for future file I/O system calls.  */
1176  O_SYS_CMDLINE
1177   /* End of System Call specific Changes.  */
1178 };
1179 
1180 enum h8_size
1181 {
1182   SB =	 0,
1183   SW =	 1,
1184   SL =	 2,
1185   SN =	 3
1186 };
1187 
1188 
1189 /* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences.
1190    Methinks the zeroes aren't necessary.  Once confirmed, nuke 'em.  */
1191 
1192 struct h8_opcode h8_opcodes[] =
1193 {
1194   {O (O_ADD, SB), AV_H8,   2, "add.b", {{IMM8,      RD8,      E}}, {{0x8, RD8, IMM8LIST, E}}},
1195   EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0),
1196 
1197   {O (O_ADD, SW), AV_H8,   6, "add.w", {{RS16,      RD16,     E}}, {{0x0, 0x9, RS16,         RD16,   E}}},
1198   {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RD16,     E}}, {{0x0, 0xa, B30 | IMM3NZ, RD16,   E}}},
1199   {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RDIND,    E}}, {{0x7, 0xd,      B31 | RDIND,  IGNORE,       0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}},
1200   {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}},
1201   {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}},
1202   EXPAND_TWOOP_W (O (O_ADD, SW), "add.w", 0x0, 0x9, 0x1),
1203 
1204   {O (O_ADD, SL), AV_H8H,  6, "add.l", {{RS32,      RD32,     E}}, {{0x0, 0xa, B31 | RS32,   B30 | RD32, E}}},
1205   {O (O_ADD, SL), AV_H8SX, 0, "add.l", {{IMM3NZ_NS, RD32,     E}}, {{0x0, 0xa, B31 | IMM3NZ, B31 | RD32, E}}},
1206   EXPAND_TWOOP_L (O (O_ADD, SL), "add.l", 0x1),
1207 
1208   {O (O_ADDS, SL), AV_H8,  2, "adds",  {{KBIT,  RDP,  E}}, {{0x0, 0xB,KBIT, RDP, E}}},
1209 
1210   {O (O_ADDX, SB), AV_H8,   2, "addx",   {{IMM8,      RD8,       E}}, {{0x9, RD8, IMM8LIST, E}}},
1211   {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8,      RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                        0x9, IGNORE, IMM8LIST, E}}},
1212   {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8,      RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x9, IGNORE, IMM8LIST, E}}},
1213   {O (O_ADDX, SB), AV_H8,   2, "addx",   {{RS8,       RD8,       E}}, {{0x0, 0xe, RS8,  RD8,    E}}},
1214   {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8,       RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                              0x0, 0xe, RS8, IGNORE, E}}},
1215   {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8,       RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31       | IGNORE, 0x0, 0xe, RS8, IGNORE, E}}},
1216   {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND,     RD8,       E}}, {{0x7, 0xc, B30 | RSIND, IGNORE,                              0x0, 0xe, IGNORE, RD8, E}}},
1217   {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RD8,       E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x0, 0xe, IGNORE, RD8, E}}},
1218   {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND,     RDIND,     E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND,     0xd, 0x0, RDIND,     0x1, IGNORE, E}}},
1219   {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
1220 
1221   {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16,     RD16,      E}}, {{PREFIX_0151,                         0x7, 0x9, 0x1, RD16,   IMM16LIST, E}}},
1222   {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16,     RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}},
1223   {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16,     RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}},
1224   {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16,      RD16,      E}}, {{PREFIX_0151, 0x0, 0x9, RS16,  RD16,    E}}},
1225   {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16,      RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}},
1226   {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16,      RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}},
1227   {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND,     RD16,      E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}},
1228   {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RD16,      E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}},
1229   {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND,     RDIND,     E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x1, IGNORE, E}}},
1230   {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
1231 
1232   {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32,     RD32,      E}}, {{PREFIX_0101, 0x7, 0xa, 0x1,  RD32, IMM32LIST, E}}},
1233   {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}},
1234   {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32,     RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}},
1235   {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32,      RD32,      E}}, {{PREFIX_0101, 0x0, 0xa, B31 | RS32,  B30 | RD32,    E}}},
1236   {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32,      RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}},
1237   {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32,      RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}},
1238   {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND,     RD32,      E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}},
1239   {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RD32,      E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}},
1240   {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x1, IGNORE, E}}},
1241   {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
1242 
1243   {O (O_AND, SB), AV_H8,   2, "and.b", {{IMM8, RD8,  E}}, {{0xe, RD8, IMM8LIST, E}}},
1244   EXPAND_TWOOP_B (O (O_AND, SB), "and.b", 0xe, 0x1, 0x6, 0x6, 0),
1245 
1246   {O (O_AND, SW), AV_H8,   2, "and.w", {{RS16, RD16, E}}, {{0x6, 0x6, RS16, RD16,   E}}},
1247   EXPAND_TWOOP_W (O (O_AND, SW), "and.w", 0x6, 0x6, 0x6),
1248 
1249   {O (O_AND, SL), AV_H8H,  2, "and.l", {{RS32,  RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x6, B30 | RS32, B30 | RD32, E}}},
1250   EXPAND_TWOOP_L (O (O_AND, SL), "and.l", 0x6),
1251 
1252   {O (O_ANDC, SB), AV_H8,  2, "andc", {{IMM8,  CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}},
1253   {O (O_ANDC, SB), AV_H8S, 2, "andc", {{IMM8,  EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x6, IMM8LIST, E}}},
1254 
1255   BRANCH (O (O_BRA, SB), "bra", 0x0),
1256 
1257   {O (O_BRAB, SB), AV_H8SX, 0, "bra", {{LOWREG | L_8,  E}}, {{0x5, 0x9, LOWREG | L_8  | B30, 0x5, E}}},
1258   {O (O_BRAW, SW), AV_H8SX, 0, "bra", {{LOWREG | L_16, E}}, {{0x5, 0x9, LOWREG | L_16 | B30, 0x6, E}}},
1259   {O (O_BRAL, SL), AV_H8SX, 0, "bra", {{RS32, E}}, {{0x5, 0x9, RS32 | B30, 0x7, E}}},
1260 
1261   {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND,    OP3PCREL8}},  {{0x7, 0xC, B30 | RDIND, 0x0,            0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
1262   {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST,  OP3PCREL8}},  {{0x7, 0xE, DSTABS8LIST,                 0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
1263   {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL8}},  {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST,      0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
1264   {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL8}},  {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST,      0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
1265   {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND,    OP3PCREL8}},  {{0x7, 0xC, B30 | RDIND, 0x0,            0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
1266   {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST,  OP3PCREL8}},  {{0x7, 0xE, DSTABS8LIST,                 0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
1267   {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL8}},  {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST,      0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
1268   {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL8}},  {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST,      0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
1269   {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1270   {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1271   {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1272   {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1273   {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1274   {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1275   {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1276   {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1277 
1278   {O (O_BRAS,  SB), AV_H8SX, 0, "bra/s",  {{PCREL8, E}}, {{0x4, 0x0, PCREL8, DATA | B01, E}}},
1279 
1280   {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1281   {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1282   {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1283   {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1284   {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1285   {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1286   {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1287   {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
1288 
1289   BRANCH (O (O_BRA, SB), "bt",  0x0),
1290   BRANCH (O (O_BRN, SB), "brn", 0x1),
1291   BRANCH (O (O_BRN, SB), "bf",  0x1),
1292   BRANCH (O (O_BHI, SB), "bhi", 0x2),
1293   BRANCH (O (O_BLS, SB), "bls", 0x3),
1294   BRANCH (O (O_BCC, SB), "bcc", 0x4),
1295   BRANCH (O (O_BCC, SB), "bhs", 0x4),
1296   BRANCH (O (O_BCS, SB), "bcs", 0x5),
1297   BRANCH (O (O_BCS, SB), "blo", 0x5),
1298   BRANCH (O (O_BNE, SB), "bne", 0x6),
1299   BRANCH (O (O_BEQ, SB), "beq", 0x7),
1300   BRANCH (O (O_BVC, SB), "bvc", 0x8),
1301   BRANCH (O (O_BVS, SB), "bvs", 0x9),
1302   BRANCH (O (O_BPL, SB), "bpl", 0xA),
1303   BRANCH (O (O_BMI, SB), "bmi", 0xB),
1304   BRANCH (O (O_BGE, SB), "bge", 0xC),
1305   BRANCH (O (O_BLT, SB), "blt", 0xD),
1306   BRANCH (O (O_BGT, SB), "bgt", 0xE),
1307   BRANCH (O (O_BLE, SB), "ble", 0xF),
1308 
1309   EBITOP (O (O_BCLR,  SB), IMM3 | B30, "bclr",  0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
1310   BITOP  (O (O_BAND,  SB), IMM3 | B30, "band",  0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
1311   BITOP  (O (O_BIAND, SB), IMM3 | B31, "biand", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
1312   BITOP  (O (O_BILD,  SB), IMM3 | B31, "bild",  0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
1313   BITOP  (O (O_BIOR,  SB), IMM3 | B31, "bior",  0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
1314   BITOP  (O (O_BIST,  SB), IMM3 | B31, "bist",  0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
1315   BITOP  (O (O_BIXOR, SB), IMM3 | B31, "bixor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
1316   BITOP  (O (O_BLD,   SB), IMM3 | B30, "bld",   0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
1317   EBITOP (O (O_BNOT,  SB), IMM3 | B30, "bnot",  0x6, 0x1, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
1318   BITOP  (O (O_BOR,   SB), IMM3 | B30, "bor",   0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
1319   EBITOP (O (O_BSET,  SB), IMM3 | B30, "bset",  0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
1320   BITOP  (O (O_BST,   SB), IMM3 | B30, "bst",   0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
1321   EBITOP (O (O_BTST,  SB), IMM3 | B30, "btst",  0x6, 0x3, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
1322   BITOP  (O (O_BXOR,  SB), IMM3 | B30, "bxor",  0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
1323 
1324   EBITOP_B (O (O_BCLREQ,  SB), IMM3 | B30, "bclr/eq",  0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
1325   EBITOP_B (O (O_BCLRNE,  SB), IMM3 | B30, "bclr/ne",  0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6),
1326   EBITOP_B (O (O_BSETEQ,  SB), IMM3 | B30, "bset/eq",  0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
1327   EBITOP_B (O (O_BSETNE,  SB), IMM3 | B30, "bset/ne",  0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6),
1328   BITOP_B  (O (O_BISTZ,   SB), IMM3 | B31, "bistz",    0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
1329   BITOP_B  (O (O_BSTZ,    SB), IMM3 | B30, "bstz",     0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
1330 
1331   {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, RDIND,    R3_8}},  {{0x7, 0xC,           B30 | RDIND, 0x0, 0xF, R3_8, IMM8LIST, E}}},
1332   {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS8DST,  R3_8}},  {{0x7, 0xE,           DSTABS8LIST,      0xF, R3_8, IMM8LIST, E}}},
1333   {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS16DST, R3_8}},  {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST,     0xF, R3_8, IMM8LIST, E}}},
1334   {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS32DST, R3_8}},  {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST,     0xF, R3_8, IMM8LIST, E}}},
1335 
1336   /* Because the assembler treats SRC, DST and OP3 as ordinals,
1337      I must designate the second argument, an immediate value, as DST.
1338      May God have mercy on my soul.  */
1339   {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, R3_IND}},   {{0x7, 0xD,           B30 | R3_IND, 0x0, 0xF, RS8, DST | IMM8LIST, E}}},
1340   {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS8OP3}},  {{0x7, 0xF,           OP3ABS8LIST,       0xF, RS8, DST | IMM8LIST, E}}},
1341   {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS16OP3}}, {{0x6, 0xA, 0x1, 0x8, OP3ABS16LIST,      0xF, RS8, DST | IMM8LIST, E}}},
1342   {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS32OP3}}, {{0x6, 0xA, 0x3, 0x8, OP3ABS32LIST,      0xF, RS8, DST | IMM8LIST, E}}},
1343 
1344   {O (O_BSR, SB), AV_H8,   6, "bsr", {{PCREL8,  E}}, {{0x5, 0x5,           PCREL8,  DATA,  E}}},
1345   {O (O_BSR, SB), AV_H8,   6, "bsr", {{PCREL16, E}}, {{0x5, 0xC, 0x0, 0x0, PCREL16, DATA3, E}}},
1346   {O (O_BSR, SB), AV_H8SX, 0, "bsr", {{LOWREG | L_8,    E}}, {{0x5, 0xd, B30 | LOWREG | L_8,  0x5, E}}},
1347   {O (O_BSR, SW), AV_H8SX, 0, "bsr", {{LOWREG | L_16,   E}}, {{0x5, 0xd, B30 | LOWREG | L_16, 0x6, E}}},
1348   {O (O_BSR, SL), AV_H8SX, 0, "bsr", {{OR32,   E}}, {{0x5, 0xd, B30 | OR32, 0x7, E}}},
1349 
1350   {O (O_CMP, SB), AV_H8,   2, "cmp.b", {{IMM8, RD8, E}}, {{0xa, RD8, IMM8LIST, E}}},
1351   EXPAND_TWOOP_B (O (O_CMP, SB), "cmp.b", 0xa, 0x1, 0xc, 0x2, B00),
1352 
1353   {O (O_CMP, SW), AV_H8,   2, "cmp.w", {{RS16,      RD16,     E}}, {{0x1, 0xd, RS16,         RD16,   E}}},
1354   {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RD16,     E}}, {{0x1, 0xf, B30 | IMM3NZ, RD16,   E}}},
1355   {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RDIND,    E}}, {{0x7, 0xd,      B31 | RDIND,  IGNORE,       0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}},
1356   {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}},
1357   {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}},
1358   EXPAND_TWOOP_W (O (O_CMP, SW), "cmp.w", 0x1, 0xd, 0x2),
1359 
1360   {O (O_CMP, SL), AV_H8H,  6, "cmp.l", {{RS32,      RD32,     E}}, {{0x1, 0xf, B31 | RS32,   B30 | RD32, E}}},
1361   {O (O_CMP, SL), AV_H8SX, 0, "cmp.l", {{IMM3NZ_NS, RD32,     E}}, {{0x1, 0xf, B31 | IMM3NZ, B31 | RD32, E}}},
1362   EXPAND_TWOOP_L (O (O_CMP, SL), "cmp.l", 0x2),
1363 
1364   UNOP (O (O_DAA, SB), "daa",   0x0, 0xF),
1365   UNOP (O (O_DAS, SB), "das",   0x1, 0xF),
1366   UNOP (O (O_DEC, SB), "dec.b", 0x1, 0xA),
1367 
1368   {O (O_DEC, SW), AV_H8H, 2, "dec.w", {{DBIT, RD16, E}}, {{0x1, 0xB, 0x5 | DBIT, RD16,       E}}},
1369   {O (O_DEC, SL), AV_H8H, 2, "dec.l", {{DBIT, RD32, E}}, {{0x1, 0xB, 0x7 | DBIT, RD32 | B30, E}}},
1370 
1371   {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x1, IMM4, RD16, E}}},
1372   {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x1, RS16, RD16, E}}},
1373   {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x3, IMM4,       B30 | RD32, E}}},
1374   {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}},
1375 
1376   {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x1, IMM4, RD16, E}}},
1377   {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x1, RS16, RD16, E}}},
1378   {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x3, IMM4,       B30 | RD32, E}}},
1379   {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}},
1380 
1381   {O (O_DIVXS, SB), AV_H8SX, 0,  "divxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x1, IMM4, RD16, E}}},
1382   {O (O_DIVXS, SB), AV_H8H,  13, "divxs.b", {{RS8,  RD16, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x1, RS8,  RD16, E}}},
1383   {O (O_DIVXS, SW), AV_H8SX, 0,  "divxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x3, IMM4, B30 | RD32, E}}},
1384   {O (O_DIVXS, SW), AV_H8H,  21, "divxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x3, RS16, B30 | RD32, E}}},
1385 
1386   {O (O_DIVXU, SB), AV_H8SX, 0,  "divxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x1, IMM4, RD16, E}}},
1387   {O (O_DIVXU, SB), AV_H8,   13, "divxu.b", {{RS8,  RD16, E}}, {{0x5, 0x1,                     RS8,  RD16, E}}},
1388   {O (O_DIVXU, SW), AV_H8SX, 0,  "divxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x3, IMM4, B30 | RD32, E}}},
1389   {O (O_DIVXU, SW), AV_H8H,  21, "divxu.w", {{RS16, RD32, E}}, {{0x5, 0x3,                     RS16, B30 | RD32, E}}},
1390 
1391   {O (O_EEPMOV, SB), AV_H8,  4, "eepmov.b", {{E}}, {{0x7, 0xB, 0x5, 0xC, 0x5, 0x9, 0x8, 0xF, E}}},
1392   {O (O_EEPMOV, SW), AV_H8H, 4, "eepmov.w", {{E}}, {{0x7, 0xB, 0xD, 0x4, 0x5, 0x9, 0x8, 0xF, E}}},
1393 
1394   EXPAND_UNOP_STD_W      (O (O_EXTS, SW), "exts.w",          PREFIX_015, 0x1, 0x7, 0xd),
1395   EXPAND_UNOP_STD_L      (O (O_EXTS, SL), "exts.l",          PREFIX_010, 0x1, 0x7, 0xf),
1396   EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0),
1397   EXPAND_UNOP_STD_W      (O (O_EXTU, SW), "extu.w",          PREFIX_015, 0x1, 0x7, 0x5),
1398   EXPAND_UNOP_STD_L      (O (O_EXTU, SL), "extu.l",          PREFIX_010, 0x1, 0x7, 0x7),
1399   EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0),
1400 
1401   UNOP (O (O_INC, SB), "inc", 0x0, 0xA),
1402 
1403   {O (O_INC, SW), AV_H8H,  2, "inc.w", {{DBIT, RD16, E}},    {{0x0, 0xB, 0x5 | DBIT, RD16,       E}}},
1404   {O (O_INC, SL), AV_H8H,  2, "inc.l", {{DBIT, RD32, E}},    {{0x0, 0xB, 0x7 | DBIT, RD32 | B30, E}}},
1405 
1406   {O (O_JMP, SN), AV_H8,   4, "jmp", {{RSIND, E}},         {{0x5, 0x9, B30 | RSIND, 0x0, E}}},
1407   {O (O_JMP, SN), AV_H8,   6, "jmp", {{ABSJMP | L_24, E}}, {{0x5, 0xA, SRC | ABSJMP | L_24, DATA5, E}}},
1408 
1409   {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{ABSJMP | L_32, E}}, {{0x5, 0x9, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
1410 
1411   {O (O_JMP, SN), AV_H8,   8, "jmp", {{MEMIND, E}}, {{0x5, 0xB, SRC | MEMIND, DATA, E}}},
1412   {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{VECIND, E}}, {{0x5, 0x9, B31 | SRC | VECIND, DATA, E}}},
1413 
1414   {O (O_JSR, SN), AV_H8,   6, "jsr", {{RSIND, E}},         {{0x5, 0xD, B30 | RSIND, 0x0, E}}},
1415   {O (O_JSR, SN), AV_H8,   8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E}}},
1416 
1417   {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
1418 
1419   {O (O_JSR, SN), AV_H8,   8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}},
1420   {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
1421 
1422   {O (O_LDC, SB), AV_H8,   2, "ldc", {{IMM8,       CCR     | DST, E}}, {{                           0x0, 0x7, IMM8LIST, E}}},
1423   {O (O_LDC, SB), AV_H8S,  2, "ldc", {{IMM8,       EXR     | DST, E}}, {{0x0, 0x1, 0x4,  EXR | DST, 0x0, 0x7, IMM8LIST, E}}},
1424   {O (O_LDC, SB), AV_H8,   2, "ldc", {{RS8,        CCR     | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, RS8, E}}},
1425   {O (O_LDC, SB), AV_H8S,  2, "ldc", {{RS8,        EXR     | DST, E}}, {{0x0, 0x3, B30 | EXR | DST, RS8, E}}},
1426   {O (O_LDC, SW), AV_H8H,  2, "ldc", {{RSIND,      CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND,     IGNORE, E}}},
1427   {O (O_LDC, SW), AV_H8S,  2, "ldc", {{RSIND,      EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND,     IGNORE, E}}},
1428   {O (O_LDC, SW), AV_H8H,  2, "ldc", {{RSPOSTINC,  CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}},
1429   {O (O_LDC, SW), AV_H8S,  2, "ldc", {{RSPOSTINC,  EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}},
1430   {O (O_LDC, SW), AV_H8H,  2, "ldc", {{DISP16SRC,  CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG,                     IGNORE, SRC | DISP16LIST, E}}},
1431   {O (O_LDC, SW), AV_H8S,  2, "ldc", {{DISP16SRC,  EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG,                     IGNORE, SRC | DISP16LIST, E}}},
1432   {O (O_LDC, SW), AV_H8H,  2, "ldc", {{DISP32SRC,  CCR     | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}},
1433   {O (O_LDC, SW), AV_H8S,  2, "ldc", {{DISP32SRC,  EXR     | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}},
1434   {O (O_LDC, SW), AV_H8H,  2, "ldc", {{ABS16SRC,   CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}},
1435   {O (O_LDC, SW), AV_H8S,  2, "ldc", {{ABS16SRC,   EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}},
1436   {O (O_LDC, SW), AV_H8H,  2, "ldc", {{ABS32SRC,   CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}},
1437   {O (O_LDC, SW), AV_H8S,  2, "ldc", {{ABS32SRC,   EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}},
1438 
1439   {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}},
1440 
1441 
1442   {O (O_MOV, SB), AV_H8,   2, "mov.b", {{IMM8, RD8,      E}}, {{0xF, RD8,            IMM8LIST,     E}}},
1443   {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xa, 0xd, IMM4, DSTABS16LIST, E}}},
1444   {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xa, 0xf, IMM4, DSTABS32LIST, E}}},
1445   MOVFROM_IMM8 (O (O_MOV, SB), PREFIX_017D, "mov.b", IMM8),
1446 
1447   {O (O_MOV, SB), AV_H8,   2,    "mov.b", {{RS8, RD8,     E}}, {{0x0, 0xC, RS8, RD8,    E}}},
1448   MOVFROM_REG_BW (O (O_MOV, SB), "mov.b", RS8, PREFIX_017, 8, 10, 12, 14, MEMRELAX),
1449   {O (O_MOV, SB), AV_H8,   4,    "mov.b", {{RS8, ABS8DST, E}}, {{0x3, RS8, DSTABS8LIST, E}}},
1450   MOVTO_REG_BW (O (O_MOV, SB),   "mov.b", RD8, PREFIX_017, 8, 10, 12, 14, MEMRELAX),
1451   {O (O_MOV, SB), AV_H8,   4,    "mov.b", {{ABS8SRC, RD8, E}}, {{0x2, RD8, ABS8LIST,    E}}},
1452 
1453   MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSIND,     FROM_IND),
1454   MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTINC, FROM_POSTINC),
1455   MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTDEC, FROM_POSTDEC),
1456   MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREINC,  FROM_PREINC),
1457   MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREDEC,  FROM_PREDEC),
1458   MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP2SRC,  FROM_DISP2),
1459   MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP16SRC, FROM_DISP16,  DISP16LIST),
1460   MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP32SRC, FROM_DISP32,  DISP32LIST),
1461   MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB16,  FROM_DISP16B, DISP16LIST),
1462   MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW16,  FROM_DISP16W, DISP16LIST),
1463   MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL16,  FROM_DISP16L, DISP16LIST),
1464   MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB32,  FROM_DISP32B, DISP32LIST),
1465   MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW32,  FROM_DISP32W, DISP32LIST),
1466   MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL32,  FROM_DISP32L, DISP32LIST),
1467   MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS16SRC,  FROM_ABS16,   ABS16LIST),
1468   MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS32SRC,  FROM_ABS32,   ABS32LIST),
1469 
1470   {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xf, B30 | IMM3NZ, RD16,   E}}},
1471   {O (O_MOV, SW), AV_H8,   4, "mov.w", {{IMM16,     RD16, E}}, {{0x7, 0x9, 0x0, RD16, IMM16LIST, E}}},
1472   {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS,  ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}},
1473   {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS,  ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}},
1474 
1475   MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D,   "mov.w", IMM8U_NS),
1476   MOVFROM_IMM  (O (O_MOV, SW), PREFIX_7974,   "mov.w", IMM16, IMM16LIST),
1477 
1478   {O (O_MOV, SW), AV_H8,   2, "mov.w", {{RS16, RD16,      E}}, {{0x0, 0xD, RS16, RD16, E}}},
1479   MOVFROM_REG_BW (O (O_MOV, SW), "mov.w", RS16, PREFIX_015, 9, 11, 13, 15, 0),
1480   MOVTO_REG_BW   (O (O_MOV, SW), "mov.w", RD16, PREFIX_015, 9, 11, 13, 15, 0),
1481 
1482   MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSIND,     FROM_IND),
1483   MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTINC, FROM_POSTINC),
1484   MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTDEC, FROM_POSTDEC),
1485   MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREINC,  FROM_PREINC),
1486   MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREDEC,  FROM_PREDEC),
1487   MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP2SRC,  FROM_DISP2),
1488   MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP16SRC, FROM_DISP16,  DISP16LIST),
1489   MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP32SRC, FROM_DISP32,  DISP32LIST),
1490   MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB16,  FROM_DISP16B, DISP16LIST),
1491   MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW16,  FROM_DISP16W, DISP16LIST),
1492   MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL16,  FROM_DISP16L, DISP16LIST),
1493   MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB32,  FROM_DISP32B, DISP32LIST),
1494   MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW32,  FROM_DISP32W, DISP32LIST),
1495   MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL32,  FROM_DISP32L, DISP32LIST),
1496   MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS16SRC,  FROM_ABS16,   ABS16LIST),
1497   MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS32SRC,  FROM_ABS32,   ABS32LIST),
1498 
1499   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}},
1500 
1501   MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS),
1502   MOVFROM_IMM  (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST),
1503 
1504   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}},
1505   {O (O_MOV, SL), AV_H8H,  4, "mov.l", {{IMM32,     RD32, E}}, {{0x7, 0xa, 0x0, B30 | RD32, IMM32LIST,  E}}},
1506 
1507   MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A74, "mov.l", IMM32, IMM32LIST),
1508 
1509   {O (O_MOV, SL), AV_H8H,  2, "mov.l", {{RS32, RD32,      E}}, {{0x0, 0xf, B31 | RS32, B30 | RD32, E}}},
1510 
1511   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, RDIND,     E}}, {{PREFIX_0100,                       0x6, 0x9, B31 | RDIND, B30 | RS32, E}}},
1512   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTINC, E}}, {{PREFIX_0103,                       0x6, 0xd, B31 | RDPOSTINC,   RS32, E}}},
1513   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0101,                       0x6, 0xd, B31 | RDPOSTDEC,   RS32, E}}},
1514   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPREINC,  E}}, {{PREFIX_0102,                       0x6, 0xd, B31 | RDPREINC,    RS32, E}}},
1515   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, RDPREDEC,  E}}, {{PREFIX_0100,                       0x6, 0xd, B31 | RDPREDEC,    RS32, E}}},
1516   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST,  E}}, {{PREFIX_010,  B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG,  RS32, E}}},
1517   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}},
1518   {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}},
1519   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100,                       0x7, 0x8, B31 | DSTDISPREG, 0x0,   0x6, 0xb, 0xa,               RS32, MEMRELAX | DSTDISP32LIST, E}}},
1520   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100,                       0x7, 0x8, DSTDISPREG, 0x0,   0x6, 0xb, 0xa,               RS32, MEMRELAX | DSTDISP32LIST, E}}},
1521   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}},
1522   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}},
1523   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}},
1524   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x1,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}},
1525   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x2,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}},
1526   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x3,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}},
1527   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, ABS16DST,  E}}, {{PREFIX_0100,                       0x6, 0xb, 0x8,            RS32, DSTABS16LIST,            E}}},
1528   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, ABS32DST,  E}}, {{PREFIX_0100,                       0x6, 0xb, 0xa,            RS32, MEMRELAX | DSTABS32LIST, E}}},
1529 
1530   {O (O_MOV, SL), AV_H8H,  4, "mov.l", {{RSIND,     RD32, E}}, {{PREFIX_0100,                       0x6, 0x9, B30 | RSIND,     RD32, E}}},
1531   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RSPOSTINC, RD32, E}}, {{PREFIX_0100,                       0x6, 0xd, B30 | RSPOSTINC, RD32, E}}},
1532   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0102,                       0x6, 0xd, B30 | RSPOSTDEC, RD32, E}}},
1533   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREINC,  RD32, E}}, {{PREFIX_0101,                       0x6, 0xd, B30 | RSPREINC,  RD32, E}}},
1534   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC,  RD32, E}}, {{PREFIX_0103,                       0x6, 0xd, B30 | RSPREDEC,  RD32, E}}},
1535   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC,  RD32, E}}, {{PREFIX_010,  B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG,   RD32, E}}},
1536   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}},
1537   {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}},
1538   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100,                       0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2,             RD32, MEMRELAX | SRC | DISP32LIST, E}}},
1539   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16,  RD32, E}}, {{PREFIX_0101,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}},
1540   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16,  RD32, E}}, {{PREFIX_0102,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}},
1541   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16,  RD32, E}}, {{PREFIX_0103,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}},
1542   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB32,  RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x1,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}},
1543   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW32,  RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x2,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}},
1544   {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL32,  RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x3,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}},
1545   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{ABS16SRC,  RD32, E}}, {{PREFIX_0100,                       0x6, 0xb, 0x0,             RD32, SRC | ABS16LIST,  E}}},
1546   {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{ABS32SRC,  RD32, E}}, {{PREFIX_0100,                       0x6, 0xb, 0x2,             RD32, SRC | MEMRELAX | ABS32LIST, E}}},
1547 
1548   MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSIND,     FROM_IND),
1549   MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTINC, FROM_POSTINC),
1550   MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTDEC, FROM_POSTDEC),
1551   MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREINC,  FROM_PREINC),
1552   MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREDEC,  FROM_PREDEC),
1553   MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP2SRC,  FROM_DISP2),
1554   MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP16SRC, FROM_DISP16,  DISP16LIST),
1555   MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP32SRC, FROM_DISP32,  DISP32LIST),
1556   MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB16,  FROM_DISP16B, DISP16LIST),
1557   MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW16,  FROM_DISP16W, DISP16LIST),
1558   MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL16,  FROM_DISP16L, DISP16LIST),
1559   MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB32,  FROM_DISP32B, DISP32LIST),
1560   MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW32,  FROM_DISP32W, DISP32LIST),
1561   MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL32,  FROM_DISP32L, DISP32LIST),
1562   MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS16SRC,  FROM_ABS16,   ABS16LIST),
1563   MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC,  FROM_ABS32,   ABS32LIST),
1564 
1565 #define DO_MOVA1(TYPE, OP0, OP1) \
1566   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
1567   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
1568   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
1569   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
1570   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
1571   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
1572 \
1573   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
1574   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
1575   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
1576   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
1577   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
1578   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}
1579 
1580 #define DO_MOVA2(TYPE, OP0, OP1, OP2) \
1581   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
1582   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
1583   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
1584   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
1585   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
1586   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
1587 \
1588   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
1589   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
1590   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
1591   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
1592   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
1593   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}
1594 
1595   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
1596   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
1597   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
1598   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
1599   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
1600   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
1601 
1602   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
1603   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
1604   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
1605   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
1606   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
1607   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
1608 
1609   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0x8, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
1610   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
1611   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xA, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
1612   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
1613   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xC, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
1614   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
1615 
1616   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0x8, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
1617   {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
1618   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xA, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
1619   {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
1620   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xC, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
1621   {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
1622 
1623   DO_MOVA1 (RDIND,     0x0, B30 | RDIND),
1624   DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC),
1625   DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC),
1626   DO_MOVA1 (RDPREINC,  0x9, B30 | RDPREINC),
1627   DO_MOVA1 (RDPREDEC,  0xB, B30 | RDPREDEC),
1628   DO_MOVA1 (DISP2DST,  B30 | B20 | DISP2DST,  B30 | DSTDISPREG),
1629   DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
1630   DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
1631   DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
1632   DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
1633   DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
1634   DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
1635   DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
1636   DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
1637   DO_MOVA2 (ABS16DST,  0x4, 0x0,              MEMRELAX | DSTABS16LIST),
1638   DO_MOVA2 (ABS32DST,  0x4, 0x8,              MEMRELAX | DSTABS32LIST),
1639 
1640   {O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}},
1641   {O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}},
1642 
1643   {O (O_MOVMD, SB), AV_H8SX, 0, "movmd.b", {{E}},         {{0x7, 0xb, 0x9, 0x4, E}}},
1644   {O (O_MOVMD, SW), AV_H8SX, 0, "movmd.w", {{E}},         {{0x7, 0xb, 0xa, 0x4, E}}},
1645   {O (O_MOVMD, SL), AV_H8SX, 0, "movmd.l", {{E}},         {{0x7, 0xb, 0xb, 0x4, E}}},
1646   {O (O_MOVSD, SB), AV_H8SX, 0, "movsd.b", {{PCREL16, E}}, {{0x7, 0xb, 0x8, 0x4, PCREL16, DATA3, E}}},
1647 
1648   {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x0, IMM4, RD16, E}}},
1649   {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x0, RS16, RD16, E}}},
1650   {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
1651   {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
1652 
1653   {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x0, IMM4, RD16, E}}},
1654   {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x0, RS16, RD16, E}}},
1655   {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
1656   {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
1657 
1658   {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x7, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
1659   {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x3, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
1660   {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xf, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
1661   {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xb, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
1662 
1663   {O (O_MULXS, SB), AV_H8SX, 0,  "mulxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x0, IMM4, RD16,       E}}},
1664   {O (O_MULXS, SB), AV_H8H,  20, "mulxs.b", {{RS8,  RD16, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x0, RS8,  RD16,       E}}},
1665   {O (O_MULXS, SW), AV_H8SX, 0,  "mulxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x2, IMM4, B30 | RD32, E}}},
1666   {O (O_MULXS, SW), AV_H8H,  20, "mulxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x2, RS16, B30 | RD32, E}}},
1667 
1668   {O (O_MULXU, SB), AV_H8SX, 0,  "mulxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x0, IMM4, RD16, E}}},
1669   {O (O_MULXU, SB), AV_H8,   14, "mulxu.b", {{RS8,  RD16, E}}, {{0x5, 0x0,                     RS8,  RD16, E}}},
1670   {O (O_MULXU, SW), AV_H8SX, 0,  "mulxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x2, IMM4, B30 | RD32, E}}},
1671   {O (O_MULXU, SW), AV_H8H,  14, "mulxu.w", {{RS16, RD32, E}}, {{0x5, 0x2,                     RS16, B30 | RD32, E}}},
1672 
1673   EXPAND_UNOP_STD_B (O (O_NEG,  SB), "neg.b", PREFIX_017, 0x1, 0x7, 0x8),
1674   EXPAND_UNOP_STD_W (O (O_NEG,  SW), "neg.w", PREFIX_015, 0x1, 0x7, 0x9),
1675   EXPAND_UNOP_STD_L (O (O_NEG,  SL), "neg.l", PREFIX_010, 0x1, 0x7, 0xb),
1676 
1677   {O (O_NOP, SN), AV_H8,  2, "nop",   {{E}},  {{0x0, 0x0, 0x0, 0x0, E}}},
1678 
1679   EXPAND_UNOP_STD_B (O (O_NOT,  SB), "not.b", PREFIX_017, 0x1, 0x7, 0x0),
1680   EXPAND_UNOP_STD_W (O (O_NOT,  SW), "not.w", PREFIX_015, 0x1, 0x7, 0x1),
1681   EXPAND_UNOP_STD_L (O (O_NOT,  SL), "not.l", PREFIX_010, 0x1, 0x7, 0x3),
1682 
1683   {O (O_OR,  SB), AV_H8,  2, "or.b",  {{IMM8, RD8,  E}}, {{0xc, RD8, IMM8LIST, E}}},
1684   EXPAND_TWOOP_B (O (O_OR, SB), "or.b", 0xc, 0x1, 0x4, 0x4, 0),
1685 
1686   {O (O_OR,  SW), AV_H8,  2, "or.w",  {{RS16, RD16, E}}, {{0x6, 0x4, RS16, RD16, E}}},
1687   EXPAND_TWOOP_W (O (O_OR, SW), "or.w", 0x6, 0x4, 0x4),
1688 
1689   {O (O_OR,  SL), AV_H8H, 2, "or.l",  {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x4, B30 | RS32, B30 | RD32, E}}},
1690   EXPAND_TWOOP_L (O (O_OR, SL), "or.l", 0x4),
1691 
1692   {O (O_ORC, SB), AV_H8,  2, "orc", {{IMM8, CCR | DST, E}}, {{0x0, 0x4, IMM8LIST, E}}},
1693   {O (O_ORC, SB), AV_H8S, 2, "orc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x4, IMM8LIST, E}}},
1694 
1695   {O (O_MOV, SW), AV_H8,  6, "pop.w",  {{OR16, E}}, {{0x6, 0xD, 0x7, OR16, E}}},
1696   {O (O_MOV, SL), AV_H8H, 6, "pop.l",  {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0x7, OR32 | B30, E}}},
1697   {O (O_MOV, SW), AV_H8,  6, "push.w", {{OR16, E}}, {{0x6, 0xD, 0xF, OR16, E}}},
1698   {O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 | B30, E}}},
1699 
1700   EXPAND_UNOP_STD_B      (O (O_ROTL,  SB), "rotl.b",           PREFIX_017, 0x1, 0x2, 0x8),
1701   EXPAND_UNOP_EXTENDED_B (O (O_ROTL,  SB), "rotl.b",  CONST_2, PREFIX_017, 0x1, 0x2, 0xc),
1702   EXPAND_UNOP_STD_W      (O (O_ROTL,  SW), "rotl.w",           PREFIX_015, 0x1, 0x2, 0x9),
1703   EXPAND_UNOP_EXTENDED_W (O (O_ROTL,  SW), "rotl.w",  CONST_2, PREFIX_015, 0x1, 0x2, 0xd),
1704   EXPAND_UNOP_STD_L      (O (O_ROTL,  SL), "rotl.l",           PREFIX_010, 0x1, 0x2, 0xb),
1705   EXPAND_UNOP_EXTENDED_L (O (O_ROTL,  SL), "rotl.l",  CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30),
1706   EXPAND_UNOP_STD_B      (O (O_ROTR,  SB), "rotr.b",           PREFIX_017, 0x1, 0x3, 0x8),
1707   EXPAND_UNOP_EXTENDED_B (O (O_ROTR,  SB), "rotr.b",  CONST_2, PREFIX_017, 0x1, 0x3, 0xc),
1708   EXPAND_UNOP_STD_W      (O (O_ROTR,  SW), "rotr.w",           PREFIX_015, 0x1, 0x3, 0x9),
1709   EXPAND_UNOP_EXTENDED_W (O (O_ROTR,  SW), "rotr.w",  CONST_2, PREFIX_015, 0x1, 0x3, 0xd),
1710   EXPAND_UNOP_STD_L      (O (O_ROTR,  SL), "rotr.l",           PREFIX_010, 0x1, 0x3, 0xb),
1711   EXPAND_UNOP_EXTENDED_L (O (O_ROTR,  SL), "rotr.l",  CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30),
1712   EXPAND_UNOP_STD_B      (O (O_ROTXL, SB), "rotxl.b",          PREFIX_017, 0x1, 0x2, 0x0),
1713   EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4),
1714   EXPAND_UNOP_STD_W      (O (O_ROTXL, SW), "rotxl.w",          PREFIX_015, 0x1, 0x2, 0x1),
1715   EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5),
1716   EXPAND_UNOP_STD_L      (O (O_ROTXL, SL), "rotxl.l",          PREFIX_010, 0x1, 0x2, 0x3),
1717   EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30),
1718   EXPAND_UNOP_STD_B      (O (O_ROTXR, SB), "rotxr.b",          PREFIX_017, 0x1, 0x3, 0x0),
1719   EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4),
1720   EXPAND_UNOP_STD_W      (O (O_ROTXR, SW), "rotxr.w",          PREFIX_015, 0x1, 0x3, 0x1),
1721   EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5),
1722   EXPAND_UNOP_STD_L      (O (O_ROTXR, SL), "rotxr.l",          PREFIX_010, 0x1, 0x3, 0x3),
1723   EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30),
1724 
1725 
1726   {O (O_BPT,  SN), AV_H8,  10, "bpt",   {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}},
1727   {O (O_RTE,  SN), AV_H8,  10, "rte",   {{E}}, {{0x5, 0x6, 0x7, 0x0, E}}},
1728   {O (O_RTS,  SN), AV_H8,   8, "rts",   {{E}}, {{0x5, 0x4, 0x7, 0x0, E}}},
1729   {O (O_RTEL, SN), AV_H8SX, 0, "rte/l", {{RS32, RD32, E}}, {{0x5, 0x6, RS32 | B30, RD32 | B30, E}}},
1730   {O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 | B30, RD32 | B30, E}}},
1731 
1732   EXPAND_UNOP_STD_B      (O (O_SHAL, SB), "shal.b",          PREFIX_017, 0x1, 0x0, 0x8),
1733   EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc),
1734   EXPAND_UNOP_STD_W      (O (O_SHAL, SW), "shal.w",          PREFIX_015, 0x1, 0x0, 0x9),
1735   EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd),
1736   EXPAND_UNOP_STD_L      (O (O_SHAL, SL), "shal.l",          PREFIX_010, 0x1, 0x0, 0xb),
1737   EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30),
1738   EXPAND_UNOP_STD_B      (O (O_SHAR, SB), "shar.b",          PREFIX_017, 0x1, 0x1, 0x8),
1739   EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc),
1740   EXPAND_UNOP_STD_W      (O (O_SHAR, SW), "shar.w",          PREFIX_015, 0x1, 0x1, 0x9),
1741   EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd),
1742   EXPAND_UNOP_STD_L      (O (O_SHAR, SL), "shar.l",          PREFIX_010, 0x1, 0x1, 0xb),
1743   EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30),
1744 
1745   EXPAND_UNOP_STD_B      (O (O_SHLL, SB), "shll.b",          PREFIX_017, 0x1, 0x0, 0x0),
1746 
1747   {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8,  RD8,  E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x0, 0x0, RD8,  E}}},
1748 
1749   EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4),
1750   EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa),
1751   {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8,  E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8,  E}}},
1752 
1753   EXPAND_UNOP_STD_W      (O (O_SHLL, SW), "shll.w",          PREFIX_015, 0x1, 0x0, 0x1),
1754 
1755   {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8,  RD16, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x0, 0x1, RD16, E}}},
1756 
1757   EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5),
1758   EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2),
1759   EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6),
1760   {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}},
1761 
1762   EXPAND_UNOP_STD_L      (O (O_SHLL, SL), "shll.l",           PREFIX_010, 0x1, 0x0, 0x3),
1763 
1764   {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8,  RD32, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x0, 0x3, B30 | RD32, E}}},
1765 
1766   EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2,  PREFIX_010, 0x1, 0x0, 0x7, B30),
1767   EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4,  PREFIX_010, 0x1, 0x0, 0x3, B31),
1768   EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8,  PREFIX_010, 0x1, 0x0, 0x7, B31),
1769   EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31),
1770   {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}},
1771 
1772   EXPAND_UNOP_STD_B      (O (O_SHLR, SB), "shlr.b",          PREFIX_017, 0x1, 0x1, 0x0),
1773 
1774   {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8,  RD8,  E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x1, 0x0, RD8,  E}}},
1775 
1776   EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4),
1777   EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa),
1778   {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8,  E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8,  E}}},
1779 
1780   EXPAND_UNOP_STD_W      (O (O_SHLR, SW), "shlr.w",          PREFIX_015, 0x1, 0x1, 0x1),
1781 
1782   {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8,  RD16, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x1, 0x1, RD16, E}}},
1783 
1784   EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5),
1785   EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2),
1786   EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6),
1787   {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}},
1788 
1789   EXPAND_UNOP_STD_L      (O (O_SHLR, SL), "shlr.l",           PREFIX_010, 0x1, 0x1, 0x3),
1790 
1791   {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8,  RD32, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x1, 0x3, B30 | RD32, E}}},
1792 
1793   EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2,  PREFIX_010, 0x1, 0x1, 0x7, B30),
1794   EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4,  PREFIX_010, 0x1, 0x1, 0x3, B31),
1795   EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8,  PREFIX_010, 0x1, 0x1, 0x7, B31),
1796   EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31),
1797   {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x3, B30 | RD32, E}}},
1798 
1799   {O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}},
1800 
1801   {O (O_STC, SB), AV_H8,   2, "stc", {{CCR | SRC, RD8,            E}}, {{0x0, 0x2, B30 | CCR | SRC,           RD8,    E}}},
1802   {O (O_STC, SB), AV_H8S,  2, "stc", {{EXR | SRC, RD8,            E}}, {{0x0, 0x2, B30 | EXR | SRC,           RD8,    E}}},
1803   {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, RDIND,          E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND,    IGNORE, E}}},
1804   {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, RDIND,          E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND,    IGNORE, E}}},
1805   {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, RDPREDEC,       E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}},
1806   {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, RDPREDEC,       E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}},
1807   {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, DISP16DST,      E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG,                   IGNORE, DSTDISP16LIST, E}}},
1808   {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, DISP16DST,      E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG,                   IGNORE, DSTDISP16LIST, E}}},
1809   {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, DISP32DST,      E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}},
1810   {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, DISP32DST,      E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}},
1811   {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, ABS16DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}},
1812   {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, ABS16DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}},
1813   {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, ABS32DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}},
1814   {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, ABS32DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}},
1815   {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}},
1816 
1817 
1818   EXPAND_TWOOP_B (O (O_SUB, SB), "sub.b", 0xa, 0x1, 0x8, 0x3, B01),
1819 
1820   {O (O_SUB, SW), AV_H8,   2, "sub.w", {{RS16,      RD16,     E}}, {{0x1, 0x9, RS16,         RD16,   E}}},
1821   {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RD16,     E}}, {{0x1, 0xa, B30 | IMM3NZ, RD16,   E}}},
1822   {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RDIND,    E}}, {{0x7, 0xd,      B31 | RDIND,  IGNORE,       0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}},
1823   {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}},
1824   {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}},
1825   EXPAND_TWOOP_W (O (O_SUB, SW), "sub.w", 0x1, 0x9, 0x3),
1826 
1827   {O (O_SUB, SL), AV_H8H,  6, "sub.l", {{RS32,      RD32,     E}}, {{0x1, 0xa, B31 | RS32,   B30 | RD32, E}}},
1828   {O (O_SUB, SL), AV_H8SX, 0, "sub.l", {{IMM3NZ_NS, RD32,     E}}, {{0x1, 0xa, B31 | IMM3NZ, B31 | RD32, E}}},
1829   EXPAND_TWOOP_L (O (O_SUB, SL), "sub.l", 0x3),
1830 
1831   {O (O_SUBS, SL), AV_H8, 2, "subs", {{KBIT, RDP, E}}, {{0x1, 0xB,KBIT, RDP, E}}},
1832 
1833   {O (O_SUBX, SB), AV_H8,   2, "subx",   {{IMM8,      RD8,       E}}, {{0xb, RD8, IMM8LIST, E}}},
1834   {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8,      RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                        0xb, IGNORE, IMM8LIST, E}}},
1835   {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8,      RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0xb, IGNORE, IMM8LIST, E}}},
1836   {O (O_SUBX, SB), AV_H8,   2, "subx",   {{RS8,       RD8,       E}}, {{0x1, 0xe, RS8,  RD8,    E}}},
1837   {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8,       RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                              0x1, 0xe, RS8, IGNORE, E}}},
1838   {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8,       RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31       | IGNORE, 0x1, 0xe, RS8, IGNORE, E}}},
1839   {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND,     RD8,       E}}, {{0x7, 0xc, B30 | RSIND, IGNORE,                              0x1, 0xe, IGNORE, RD8, E}}},
1840   {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RD8,       E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x1, 0xe, IGNORE, RD8, E}}},
1841   {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND,     RDIND,     E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND,     0xd, 0x0, RDIND,     0x3, IGNORE, E}}},
1842   {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
1843 
1844   {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16,     RD16,      E}}, {{PREFIX_0151,                         0x7, 0x9, 0x3, RD16,   IMM16LIST, E}}},
1845   {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16,     RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}},
1846   {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16,     RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}},
1847   {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16,      RD16,      E}}, {{PREFIX_0151, 0x1, 0x9, RS16,  RD16,    E}}},
1848   {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16,      RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}},
1849   {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16,      RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}},
1850   {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND,     RD16,      E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}},
1851   {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RD16,      E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}},
1852   {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND,     RDIND,     E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x3, IGNORE, E}}},
1853   {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
1854 
1855   {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32,     RD32,      E}}, {{PREFIX_0101, 0x7, 0xa, 0x3,  RD32, IMM32LIST, E}}},
1856   {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}},
1857   {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32,     RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}},
1858   {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32,      RD32,      E}}, {{PREFIX_0101, 0x1, 0xa, B31 | RS32,  B30 | RD32,    E}}},
1859   {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32,      RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}},
1860   {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32,      RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}},
1861   {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND,     RD32,      E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}},
1862   {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RD32,      E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}},
1863   {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x3, IGNORE, E}}},
1864   {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
1865 
1866   {O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2,  E}}, {{0x5, 0x7, IMM2, IGNORE, E}}},
1867   {O (O_TAS,   SB), AV_H8H, 2, "tas",   {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 | RSIND, 0xc, E}}},
1868 
1869   {O (O_XOR,   SB), AV_H8,  2, "xor.b", {{IMM8, RD8,  E}}, {{0xd, RD8, IMM8LIST, E}}},
1870   EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0),
1871 
1872   {O (O_XOR,   SW), AV_H8,  2, "xor.w", {{RS16, RD16, E}}, {{0x6, 0x5, RS16, RD16, E}}},
1873   EXPAND_TWOOP_W (O (O_XOR, SW), "xor.w", 0x6, 0x5, 0x5),
1874 
1875   {O (O_XOR,   SL), AV_H8H, 2, "xor.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x5, B30 | RS32, B30 | RD32, E}}},
1876   EXPAND_TWOOP_L (O (O_XOR, SL), "xor.l", 0x5),
1877 
1878   {O (O_XORC, SB), AV_H8,  2, "xorc", {{IMM8, CCR | DST, E}}, {{0x0, 0x5, IMM8LIST, E}}},
1879   {O (O_XORC, SB), AV_H8S, 2, "xorc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x5, IMM8LIST, E}}},
1880 
1881   {O (O_CLRMAC, SN), AV_H8S, 2, "clrmac", {{E}}, {{0x0, 0x1, 0xa, 0x0, E}}},
1882   {O (O_MAC,    SW), AV_H8S, 2, "mac",    {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 | RSPOSTINC, B30 | RDPOSTINC, E}}},
1883   {O (O_LDMAC,  SL), AV_H8S, 2, "ldmac",  {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}},
1884   {O (O_STMAC,  SL), AV_H8S, 2, "stmac",  {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}},
1885   {O (O_LDM,    SL), AV_H8H, 6, "ldm.l",  {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 | RD32, E}}},
1886   {O (O_STM,    SL), AV_H8H, 6, "stm.l",  {{RS32, RDPREDEC,  E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 | RS32, E}}},
1887   {0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}}
1888 };
1889 #else
1890 extern const struct h8_opcode h8_opcodes[];
1891 #endif
1892 
1893