1// Copyright 2015 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5// This file encapsulates some of the odd characteristics of the
6// 64-bit PowerPC (PPC64) instruction set, to minimize its interaction
7// with the core of the assembler.
8
9package arch
10
11import (
12	"cmd/internal/obj"
13	"cmd/internal/obj/ppc64"
14)
15
16func jumpPPC64(word string) bool {
17	switch word {
18	case "BC", "BCL", "BEQ", "BGE", "BGT", "BL", "BLE", "BLT", "BNE", "BR", "BVC", "BVS", "CALL", "JMP":
19		return true
20	}
21	return false
22}
23
24// IsPPC64RLD reports whether the op (as defined by an ppc64.A* constant) is
25// one of the RLD-like instructions that require special handling.
26// The FMADD-like instructions behave similarly.
27func IsPPC64RLD(op obj.As) bool {
28	switch op {
29	case ppc64.ARLDC, ppc64.ARLDCCC, ppc64.ARLDCL, ppc64.ARLDCLCC,
30		ppc64.ARLDCR, ppc64.ARLDCRCC, ppc64.ARLDMI, ppc64.ARLDMICC,
31		ppc64.ARLWMI, ppc64.ARLWMICC, ppc64.ARLWNM, ppc64.ARLWNMCC:
32		return true
33	case ppc64.AFMADD, ppc64.AFMADDCC, ppc64.AFMADDS, ppc64.AFMADDSCC,
34		ppc64.AFMSUB, ppc64.AFMSUBCC, ppc64.AFMSUBS, ppc64.AFMSUBSCC,
35		ppc64.AFNMADD, ppc64.AFNMADDCC, ppc64.AFNMADDS, ppc64.AFNMADDSCC,
36		ppc64.AFNMSUB, ppc64.AFNMSUBCC, ppc64.AFNMSUBS, ppc64.AFNMSUBSCC:
37		return true
38	}
39	return false
40}
41
42func IsPPC64ISEL(op obj.As) bool {
43	return op == ppc64.AISEL
44}
45
46// IsPPC64CMP reports whether the op (as defined by an ppc64.A* constant) is
47// one of the CMP instructions that require special handling.
48func IsPPC64CMP(op obj.As) bool {
49	switch op {
50	case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPU:
51		return true
52	}
53	return false
54}
55
56// IsPPC64NEG reports whether the op (as defined by an ppc64.A* constant) is
57// one of the NEG-like instructions that require special handling.
58func IsPPC64NEG(op obj.As) bool {
59	switch op {
60	case ppc64.AADDMECC, ppc64.AADDMEVCC, ppc64.AADDMEV, ppc64.AADDME,
61		ppc64.AADDZECC, ppc64.AADDZEVCC, ppc64.AADDZEV, ppc64.AADDZE,
62		ppc64.ACNTLZDCC, ppc64.ACNTLZD, ppc64.ACNTLZWCC, ppc64.ACNTLZW,
63		ppc64.AEXTSBCC, ppc64.AEXTSB, ppc64.AEXTSHCC, ppc64.AEXTSH,
64		ppc64.AEXTSWCC, ppc64.AEXTSW, ppc64.ANEGCC, ppc64.ANEGVCC,
65		ppc64.ANEGV, ppc64.ANEG, ppc64.ASLBMFEE, ppc64.ASLBMFEV,
66		ppc64.ASLBMTE, ppc64.ASUBMECC, ppc64.ASUBMEVCC, ppc64.ASUBMEV,
67		ppc64.ASUBME, ppc64.ASUBZECC, ppc64.ASUBZEVCC, ppc64.ASUBZEV,
68		ppc64.ASUBZE:
69		return true
70	}
71	return false
72}
73
74func ppc64RegisterNumber(name string, n int16) (int16, bool) {
75	switch name {
76	case "CR":
77		if 0 <= n && n <= 7 {
78			return ppc64.REG_CR0 + n, true
79		}
80	case "VS":
81		if 0 <= n && n <= 63 {
82			return ppc64.REG_VS0 + n, true
83		}
84	case "V":
85		if 0 <= n && n <= 31 {
86			return ppc64.REG_V0 + n, true
87		}
88	case "F":
89		if 0 <= n && n <= 31 {
90			return ppc64.REG_F0 + n, true
91		}
92	case "R":
93		if 0 <= n && n <= 31 {
94			return ppc64.REG_R0 + n, true
95		}
96	case "SPR":
97		if 0 <= n && n <= 1024 {
98			return ppc64.REG_SPR0 + n, true
99		}
100	}
101	return 0, false
102}
103