1// Based on cmd/internal/obj/ppc64/asm9.go. 2// 3// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5// Portions Copyright © 1997-1999 Vita Nuova Limited 6// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7// Portions Copyright © 2004,2006 Bruce Ellis 8// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10// Portions Copyright © 2009 The Go Authors. All rights reserved. 11// 12// Permission is hereby granted, free of charge, to any person obtaining a copy 13// of this software and associated documentation files (the "Software"), to deal 14// in the Software without restriction, including without limitation the rights 15// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16// copies of the Software, and to permit persons to whom the Software is 17// furnished to do so, subject to the following conditions: 18// 19// The above copyright notice and this permission notice shall be included in 20// all copies or substantial portions of the Software. 21// 22// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28// THE SOFTWARE. 29 30package s390x 31 32import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "fmt" 36 "log" 37 "math" 38 "sort" 39) 40 41// ctxtz holds state while assembling a single function. 42// Each function gets a fresh ctxtz. 43// This allows for multiple functions to be safely concurrently assembled. 44type ctxtz struct { 45 ctxt *obj.Link 46 newprog obj.ProgAlloc 47 cursym *obj.LSym 48 autosize int32 49 instoffset int64 50 pc int64 51} 52 53// instruction layout. 54const ( 55 funcAlign = 16 56) 57 58type Optab struct { 59 as obj.As // opcode 60 i uint8 // handler index 61 a1 uint8 // From 62 a2 uint8 // Reg 63 a3 uint8 // RestArgs[0] 64 a4 uint8 // RestArgs[1] 65 a5 uint8 // RestArgs[2] 66 a6 uint8 // To 67} 68 69var optab = []Optab{ 70 // zero-length instructions 71 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE}, 72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE}, 73 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON}, 74 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR}, 75 {i: 0, as: obj.ANOP}, 76 {i: 0, as: obj.ANOP, a1: C_SAUTO}, 77 78 // move register 79 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG}, 80 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG}, 81 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG}, 82 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG}, 83 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG}, 84 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG}, 85 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG}, 86 87 // load constant 88 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG}, 89 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG}, 90 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG}, 91 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG}, 92 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG}, 93 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG}, 94 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG}, 95 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG}, 96 97 // store constant 98 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO}, 99 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO}, 100 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO}, 101 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO}, 102 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO}, 103 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO}, 104 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO}, 105 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO}, 106 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO}, 107 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO}, 108 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG}, 109 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG}, 110 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG}, 111 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG}, 112 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG}, 113 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG}, 114 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG}, 115 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG}, 116 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG}, 117 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG}, 118 119 // store 120 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO}, 121 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO}, 122 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO}, 123 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO}, 124 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO}, 125 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO}, 126 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO}, 127 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG}, 128 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG}, 129 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG}, 130 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG}, 131 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG}, 132 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG}, 133 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG}, 134 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR}, 135 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR}, 136 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR}, 137 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR}, 138 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR}, 139 140 // load 141 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG}, 142 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG}, 143 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG}, 144 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG}, 145 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG}, 146 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG}, 147 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG}, 148 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG}, 149 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG}, 150 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG}, 151 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG}, 152 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG}, 153 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG}, 154 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG}, 155 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG}, 156 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG}, 157 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG}, 158 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG}, 159 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG}, 160 161 // interlocked load and op 162 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG}, 163 164 // integer arithmetic 165 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG}, 166 {i: 2, as: AADD, a1: C_REG, a6: C_REG}, 167 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG}, 168 {i: 22, as: AADD, a1: C_LCON, a6: C_REG}, 169 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG}, 170 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG}, 171 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG}, 172 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG}, 173 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG}, 174 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG}, 175 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG}, 176 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG}, 177 {i: 62, as: AMLGR, a1: C_REG, a6: C_REG}, 178 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG}, 179 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG}, 180 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG}, 181 {i: 10, as: ASUB, a1: C_REG, a6: C_REG}, 182 {i: 47, as: ANEG, a1: C_REG, a6: C_REG}, 183 {i: 47, as: ANEG, a6: C_REG}, 184 185 // integer logical 186 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG}, 187 {i: 6, as: AAND, a1: C_REG, a6: C_REG}, 188 {i: 23, as: AAND, a1: C_LCON, a6: C_REG}, 189 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG}, 190 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG}, 191 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG}, 192 {i: 6, as: AANDW, a1: C_REG, a6: C_REG}, 193 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG}, 194 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG}, 195 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG}, 196 {i: 7, as: ASLD, a1: C_REG, a6: C_REG}, 197 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG}, 198 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG}, 199 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG}, 200 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG}, 201 202 // compare and swap 203 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG}, 204 205 // floating point 206 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG}, 207 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG}, 208 {i: 33, as: AFABS, a6: C_FREG}, 209 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG}, 210 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG}, 211 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG}, 212 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG}, 213 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG}, 214 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO}, 215 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG}, 216 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR}, 217 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG}, 218 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG}, 219 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG}, 220 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG}, 221 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG}, 222 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG}, 223 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG}, 224 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG}, 225 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON}, 226 227 // load symbol address (plus offset) 228 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG}, 229 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG}, 230 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG}, 231 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG}, 232 233 // system call 234 {i: 5, as: ASYSCALL}, 235 {i: 77, as: ASYSCALL, a1: C_SCON}, 236 237 // branch 238 {i: 16, as: ABEQ, a6: C_SBRA}, 239 {i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA}, 240 {i: 11, as: ABR, a6: C_LBRA}, 241 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA}, 242 {i: 18, as: ABR, a6: C_REG}, 243 {i: 18, as: ABR, a1: C_REG, a6: C_REG}, 244 {i: 15, as: ABR, a6: C_ZOREG}, 245 {i: 15, as: ABC, a6: C_ZOREG}, 246 247 // compare and branch 248 {i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA}, 249 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, 250 {i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA}, 251 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA}, 252 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA}, 253 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA}, 254 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA}, 255 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA}, 256 {i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA}, 257 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA}, 258 259 // branch on count 260 {i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA}, 261 {i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA}, 262 263 // move on condition 264 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG}, 265 266 // load on condition 267 {i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG}, 268 269 // find leftmost one 270 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG}, 271 272 // population count 273 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG}, 274 275 // compare 276 {i: 70, as: ACMP, a1: C_REG, a6: C_REG}, 277 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON}, 278 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG}, 279 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON}, 280 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG}, 281 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG}, 282 283 // test under mask 284 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON}, 285 286 // insert program mask 287 {i: 92, as: AIPM, a1: C_REG}, 288 289 // set program mask 290 {i: 76, as: ASPM, a1: C_REG}, 291 292 // 32-bit access registers 293 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG}, 294 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG}, 295 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG}, 296 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG}, 297 298 // macros 299 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG}, 300 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO}, 301 302 // load/store multiple 303 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG}, 304 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO}, 305 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG}, 306 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG}, 307 308 // bytes 309 {i: 40, as: ABYTE, a1: C_SCON}, 310 {i: 40, as: AWORD, a1: C_LCON}, 311 {i: 31, as: ADWORD, a1: C_LCON}, 312 {i: 31, as: ADWORD, a1: C_DCON}, 313 314 // fast synchronization 315 {i: 80, as: ASYNC}, 316 317 // store clock 318 {i: 88, as: ASTCK, a6: C_SAUTO}, 319 {i: 88, as: ASTCK, a6: C_SOREG}, 320 321 // storage and storage 322 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG}, 323 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO}, 324 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO}, 325 326 // address 327 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG}, 328 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG}, 329 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG}, 330 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG}, 331 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG}, 332 333 // undefined (deliberate illegal instruction) 334 {i: 78, as: obj.AUNDEF}, 335 336 // 2 byte no-operation 337 {i: 66, as: ANOPH}, 338 339 // vector instructions 340 341 // VRX store 342 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG}, 343 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO}, 344 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, 345 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, 346 347 // VRX load 348 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG}, 349 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG}, 350 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, 351 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, 352 353 // VRV scatter 354 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG}, 355 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO}, 356 357 // VRV gather 358 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG}, 359 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG}, 360 361 // VRS element shift/rotate and load gr to/from vr element 362 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG}, 363 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG}, 364 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG}, 365 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG}, 366 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG}, 367 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG}, 368 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG}, 369 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG}, 370 371 // VRS store multiple 372 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG}, 373 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO}, 374 375 // VRS load multiple 376 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG}, 377 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG}, 378 379 // VRS store with length 380 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG}, 381 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO}, 382 383 // VRS load with length 384 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG}, 385 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG}, 386 387 // VRI-a 388 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG}, 389 {i: 109, as: AVZERO, a6: C_VREG}, 390 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG}, 391 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG}, 392 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG}, 393 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, 394 395 // VRI-b generate mask 396 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG}, 397 398 // VRI-c replicate 399 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG}, 400 401 // VRI-d element rotate and insert under mask and 402 // shift left double by byte 403 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 404 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 405 406 // VRI-d fp test data class immediate 407 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG}, 408 409 // VRR-a load reg 410 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG}, 411 412 // VRR-a compare 413 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG}, 414 415 // VRR-b 416 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 417 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 418 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 419 420 // VRR-c 421 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 422 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG}, 423 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG}, 424 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 425 426 // VRR-c shifts 427 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG}, 428 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG}, 429 430 // VRR-d 431 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 432 433 // VRR-e 434 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG}, 435 436 // VRR-f 437 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG}, 438} 439 440var oprange [ALAST & obj.AMask][]Optab 441 442var xcmp [C_NCLASS][C_NCLASS]bool 443 444func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 445 p := cursym.Func.Text 446 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 447 return 448 } 449 450 if oprange[AORW&obj.AMask] == nil { 451 ctxt.Diag("s390x ops not initialized, call s390x.buildop first") 452 } 453 454 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 455 456 buffer := make([]byte, 0) 457 changed := true 458 loop := 0 459 for changed { 460 if loop > 100 { 461 c.ctxt.Diag("stuck in spanz loop") 462 break 463 } 464 changed = false 465 buffer = buffer[:0] 466 c.cursym.R = make([]obj.Reloc, 0) 467 for p := c.cursym.Func.Text; p != nil; p = p.Link { 468 pc := int64(len(buffer)) 469 if pc != p.Pc { 470 changed = true 471 } 472 p.Pc = pc 473 c.pc = p.Pc 474 c.asmout(p, &buffer) 475 if pc == int64(len(buffer)) { 476 switch p.As { 477 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 478 // ok 479 default: 480 c.ctxt.Diag("zero-width instruction\n%v", p) 481 } 482 } 483 } 484 loop++ 485 } 486 487 c.cursym.Size = int64(len(buffer)) 488 if c.cursym.Size%funcAlign != 0 { 489 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign) 490 } 491 c.cursym.Grow(c.cursym.Size) 492 copy(c.cursym.P, buffer) 493 494 // Mark nonpreemptible instruction sequences. 495 // We use REGTMP as a scratch register during call injection, 496 // so instruction sequences that use REGTMP are unsafe to 497 // preempt asynchronously. 498 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func.Text, c.newprog, c.isUnsafePoint) 499} 500 501// Return whether p is an unsafe point. 502func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool { 503 if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP { 504 return true 505 } 506 for _, a := range p.RestArgs { 507 if a.Reg == REGTMP { 508 return true 509 } 510 } 511 return p.Mark&USETMP != 0 512} 513 514func isint32(v int64) bool { 515 return int64(int32(v)) == v 516} 517 518func isuint32(v uint64) bool { 519 return uint64(uint32(v)) == v 520} 521 522func (c *ctxtz) aclass(a *obj.Addr) int { 523 switch a.Type { 524 case obj.TYPE_NONE: 525 return C_NONE 526 527 case obj.TYPE_REG: 528 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 529 return C_REG 530 } 531 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 532 return C_FREG 533 } 534 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 535 return C_AREG 536 } 537 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 538 return C_VREG 539 } 540 return C_GOK 541 542 case obj.TYPE_MEM: 543 switch a.Name { 544 case obj.NAME_EXTERN, 545 obj.NAME_STATIC: 546 if a.Sym == nil { 547 // must have a symbol 548 break 549 } 550 c.instoffset = a.Offset 551 if a.Sym.Type == objabi.STLSBSS { 552 if c.ctxt.Flag_shared { 553 return C_TLS_IE // initial exec model 554 } 555 return C_TLS_LE // local exec model 556 } 557 return C_ADDR 558 559 case obj.NAME_GOTREF: 560 return C_GOTADDR 561 562 case obj.NAME_AUTO: 563 if a.Reg == REGSP { 564 // unset base register for better printing, since 565 // a.Offset is still relative to pseudo-SP. 566 a.Reg = obj.REG_NONE 567 } 568 c.instoffset = int64(c.autosize) + a.Offset 569 if c.instoffset >= -BIG && c.instoffset < BIG { 570 return C_SAUTO 571 } 572 return C_LAUTO 573 574 case obj.NAME_PARAM: 575 if a.Reg == REGSP { 576 // unset base register for better printing, since 577 // a.Offset is still relative to pseudo-FP. 578 a.Reg = obj.REG_NONE 579 } 580 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 581 if c.instoffset >= -BIG && c.instoffset < BIG { 582 return C_SAUTO 583 } 584 return C_LAUTO 585 586 case obj.NAME_NONE: 587 c.instoffset = a.Offset 588 if c.instoffset == 0 { 589 return C_ZOREG 590 } 591 if c.instoffset >= -BIG && c.instoffset < BIG { 592 return C_SOREG 593 } 594 return C_LOREG 595 } 596 597 return C_GOK 598 599 case obj.TYPE_TEXTSIZE: 600 return C_TEXTSIZE 601 602 case obj.TYPE_FCONST: 603 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 604 return C_ZCON 605 } 606 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val) 607 608 case obj.TYPE_CONST, 609 obj.TYPE_ADDR: 610 switch a.Name { 611 case obj.NAME_NONE: 612 c.instoffset = a.Offset 613 if a.Reg != 0 { 614 if -BIG <= c.instoffset && c.instoffset <= BIG { 615 return C_SACON 616 } 617 if isint32(c.instoffset) { 618 return C_LACON 619 } 620 return C_DACON 621 } 622 623 case obj.NAME_EXTERN, 624 obj.NAME_STATIC: 625 s := a.Sym 626 if s == nil { 627 return C_GOK 628 } 629 c.instoffset = a.Offset 630 631 return C_SYMADDR 632 633 case obj.NAME_AUTO: 634 if a.Reg == REGSP { 635 // unset base register for better printing, since 636 // a.Offset is still relative to pseudo-SP. 637 a.Reg = obj.REG_NONE 638 } 639 c.instoffset = int64(c.autosize) + a.Offset 640 if c.instoffset >= -BIG && c.instoffset < BIG { 641 return C_SACON 642 } 643 return C_LACON 644 645 case obj.NAME_PARAM: 646 if a.Reg == REGSP { 647 // unset base register for better printing, since 648 // a.Offset is still relative to pseudo-FP. 649 a.Reg = obj.REG_NONE 650 } 651 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 652 if c.instoffset >= -BIG && c.instoffset < BIG { 653 return C_SACON 654 } 655 return C_LACON 656 657 default: 658 return C_GOK 659 } 660 661 if c.instoffset == 0 { 662 return C_ZCON 663 } 664 if c.instoffset >= 0 { 665 if c.instoffset <= 0x7fff { 666 return C_SCON 667 } 668 if c.instoffset <= 0xffff { 669 return C_ANDCON 670 } 671 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 672 return C_UCON 673 } 674 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 675 return C_LCON 676 } 677 return C_DCON 678 } 679 680 if c.instoffset >= -0x8000 { 681 return C_ADDCON 682 } 683 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 684 return C_UCON 685 } 686 if isint32(c.instoffset) { 687 return C_LCON 688 } 689 return C_DCON 690 691 case obj.TYPE_BRANCH: 692 return C_SBRA 693 } 694 695 return C_GOK 696} 697 698func (c *ctxtz) oplook(p *obj.Prog) *Optab { 699 // Return cached optab entry if available. 700 if p.Optab != 0 { 701 return &optab[p.Optab-1] 702 } 703 if len(p.RestArgs) > 3 { 704 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs)) 705 return nil 706 } 707 708 // Initialize classes for all arguments. 709 p.From.Class = int8(c.aclass(&p.From) + 1) 710 p.To.Class = int8(c.aclass(&p.To) + 1) 711 for i := range p.RestArgs { 712 p.RestArgs[i].Class = int8(c.aclass(&p.RestArgs[i]) + 1) 713 } 714 715 // Mirrors the argument list in Optab. 716 args := [...]int8{ 717 p.From.Class - 1, 718 C_NONE, // p.Reg 719 C_NONE, // p.RestArgs[0] 720 C_NONE, // p.RestArgs[1] 721 C_NONE, // p.RestArgs[2] 722 p.To.Class - 1, 723 } 724 // Fill in argument class for p.Reg. 725 switch { 726 case REG_R0 <= p.Reg && p.Reg <= REG_R15: 727 args[1] = C_REG 728 case REG_V0 <= p.Reg && p.Reg <= REG_V31: 729 args[1] = C_VREG 730 case REG_F0 <= p.Reg && p.Reg <= REG_F15: 731 args[1] = C_FREG 732 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15: 733 args[1] = C_AREG 734 } 735 // Fill in argument classes for p.RestArgs. 736 for i, a := range p.RestArgs { 737 args[2+i] = a.Class - 1 738 } 739 740 // Lookup op in optab. 741 ops := oprange[p.As&obj.AMask] 742 cmp := [len(args)]*[C_NCLASS]bool{} 743 for i := range cmp { 744 cmp[i] = &xcmp[args[i]] 745 } 746 for i := range ops { 747 op := &ops[i] 748 if cmp[0][op.a1] && cmp[1][op.a2] && 749 cmp[2][op.a3] && cmp[3][op.a4] && 750 cmp[4][op.a5] && cmp[5][op.a6] { 751 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 752 return op 753 } 754 } 755 756 // Cannot find a case; abort. 757 s := "" 758 for _, a := range args { 759 s += fmt.Sprintf(" %v", DRconv(int(a))) 760 } 761 c.ctxt.Diag("illegal combination %v%v\n", p.As, s) 762 c.ctxt.Diag("prog: %v\n", p) 763 return nil 764} 765 766func cmp(a int, b int) bool { 767 if a == b { 768 return true 769 } 770 switch a { 771 case C_DCON: 772 if b == C_LCON { 773 return true 774 } 775 fallthrough 776 case C_LCON: 777 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 778 return true 779 } 780 781 case C_ADDCON: 782 if b == C_ZCON || b == C_SCON { 783 return true 784 } 785 786 case C_ANDCON: 787 if b == C_ZCON || b == C_SCON { 788 return true 789 } 790 791 case C_UCON: 792 if b == C_ZCON || b == C_SCON { 793 return true 794 } 795 796 case C_SCON: 797 if b == C_ZCON { 798 return true 799 } 800 801 case C_LACON: 802 if b == C_SACON { 803 return true 804 } 805 806 case C_LBRA: 807 if b == C_SBRA { 808 return true 809 } 810 811 case C_LAUTO: 812 if b == C_SAUTO { 813 return true 814 } 815 816 case C_LOREG: 817 if b == C_ZOREG || b == C_SOREG { 818 return true 819 } 820 821 case C_SOREG: 822 if b == C_ZOREG { 823 return true 824 } 825 826 case C_ANY: 827 return true 828 } 829 830 return false 831} 832 833type ocmp []Optab 834 835func (x ocmp) Len() int { 836 return len(x) 837} 838 839func (x ocmp) Swap(i, j int) { 840 x[i], x[j] = x[j], x[i] 841} 842 843func (x ocmp) Less(i, j int) bool { 844 p1 := &x[i] 845 p2 := &x[j] 846 n := int(p1.as) - int(p2.as) 847 if n != 0 { 848 return n < 0 849 } 850 n = int(p1.a1) - int(p2.a1) 851 if n != 0 { 852 return n < 0 853 } 854 n = int(p1.a2) - int(p2.a2) 855 if n != 0 { 856 return n < 0 857 } 858 n = int(p1.a3) - int(p2.a3) 859 if n != 0 { 860 return n < 0 861 } 862 n = int(p1.a4) - int(p2.a4) 863 if n != 0 { 864 return n < 0 865 } 866 return false 867} 868func opset(a, b obj.As) { 869 oprange[a&obj.AMask] = oprange[b&obj.AMask] 870} 871 872func buildop(ctxt *obj.Link) { 873 if oprange[AORW&obj.AMask] != nil { 874 // Already initialized; stop now. 875 // This happens in the cmd/asm tests, 876 // each of which re-initializes the arch. 877 return 878 } 879 880 for i := 0; i < C_NCLASS; i++ { 881 for n := 0; n < C_NCLASS; n++ { 882 if cmp(n, i) { 883 xcmp[i][n] = true 884 } 885 } 886 } 887 sort.Sort(ocmp(optab)) 888 for i := 0; i < len(optab); i++ { 889 r := optab[i].as 890 start := i 891 for ; i+1 < len(optab); i++ { 892 if optab[i+1].as != r { 893 break 894 } 895 } 896 oprange[r&obj.AMask] = optab[start : i+1] 897 898 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 899 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 900 switch r { 901 case AADD: 902 opset(AADDC, r) 903 opset(AADDW, r) 904 opset(AMULLD, r) 905 opset(AMULLW, r) 906 case ADIVW: 907 opset(AADDE, r) 908 opset(ADIVD, r) 909 opset(ADIVDU, r) 910 opset(ADIVWU, r) 911 opset(AMODD, r) 912 opset(AMODDU, r) 913 opset(AMODW, r) 914 opset(AMODWU, r) 915 case AMULHD: 916 opset(AMULHDU, r) 917 case AMOVBZ: 918 opset(AMOVH, r) 919 opset(AMOVHZ, r) 920 case ALA: 921 opset(ALAY, r) 922 case AMVC: 923 opset(ACLC, r) 924 opset(AXC, r) 925 opset(AOC, r) 926 opset(ANC, r) 927 case ASTCK: 928 opset(ASTCKC, r) 929 opset(ASTCKE, r) 930 opset(ASTCKF, r) 931 case ALAAG: 932 opset(ALAA, r) 933 opset(ALAAL, r) 934 opset(ALAALG, r) 935 opset(ALAN, r) 936 opset(ALANG, r) 937 opset(ALAX, r) 938 opset(ALAXG, r) 939 opset(ALAO, r) 940 opset(ALAOG, r) 941 case ASTMG: 942 opset(ASTMY, r) 943 case ALMG: 944 opset(ALMY, r) 945 case ABEQ: 946 opset(ABGE, r) 947 opset(ABGT, r) 948 opset(ABLE, r) 949 opset(ABLT, r) 950 opset(ABNE, r) 951 opset(ABVC, r) 952 opset(ABVS, r) 953 opset(ABLEU, r) 954 opset(ABLTU, r) 955 case ABR: 956 opset(ABL, r) 957 case ABC: 958 opset(ABCL, r) 959 case AFABS: 960 opset(AFNABS, r) 961 opset(ALPDFR, r) 962 opset(ALNDFR, r) 963 opset(AFNEG, r) 964 opset(AFNEGS, r) 965 opset(ALEDBR, r) 966 opset(ALDEBR, r) 967 opset(AFSQRT, r) 968 opset(AFSQRTS, r) 969 case AFADD: 970 opset(AFADDS, r) 971 opset(AFDIV, r) 972 opset(AFDIVS, r) 973 opset(AFSUB, r) 974 opset(AFSUBS, r) 975 case AFMADD: 976 opset(AFMADDS, r) 977 opset(AFMSUB, r) 978 opset(AFMSUBS, r) 979 case AFMUL: 980 opset(AFMULS, r) 981 case AFCMPO: 982 opset(AFCMPU, r) 983 opset(ACEBR, r) 984 case AAND: 985 opset(AOR, r) 986 opset(AXOR, r) 987 case AANDW: 988 opset(AORW, r) 989 opset(AXORW, r) 990 case ASLD: 991 opset(ASRD, r) 992 opset(ASLW, r) 993 opset(ASRW, r) 994 opset(ASRAD, r) 995 opset(ASRAW, r) 996 opset(ARLL, r) 997 opset(ARLLG, r) 998 case ARNSBG: 999 opset(ARXSBG, r) 1000 opset(AROSBG, r) 1001 opset(ARNSBGT, r) 1002 opset(ARXSBGT, r) 1003 opset(AROSBGT, r) 1004 opset(ARISBG, r) 1005 opset(ARISBGN, r) 1006 opset(ARISBGZ, r) 1007 opset(ARISBGNZ, r) 1008 opset(ARISBHG, r) 1009 opset(ARISBLG, r) 1010 opset(ARISBHGZ, r) 1011 opset(ARISBLGZ, r) 1012 case ACSG: 1013 opset(ACS, r) 1014 case ASUB: 1015 opset(ASUBC, r) 1016 opset(ASUBE, r) 1017 opset(ASUBW, r) 1018 case ANEG: 1019 opset(ANEGW, r) 1020 case AFMOVD: 1021 opset(AFMOVS, r) 1022 case AMOVDBR: 1023 opset(AMOVWBR, r) 1024 case ACMP: 1025 opset(ACMPW, r) 1026 case ACMPU: 1027 opset(ACMPWU, r) 1028 case ATMHH: 1029 opset(ATMHL, r) 1030 opset(ATMLH, r) 1031 opset(ATMLL, r) 1032 case ACEFBRA: 1033 opset(ACDFBRA, r) 1034 opset(ACEGBRA, r) 1035 opset(ACDGBRA, r) 1036 opset(ACELFBR, r) 1037 opset(ACDLFBR, r) 1038 opset(ACELGBR, r) 1039 opset(ACDLGBR, r) 1040 case ACFEBRA: 1041 opset(ACFDBRA, r) 1042 opset(ACGEBRA, r) 1043 opset(ACGDBRA, r) 1044 opset(ACLFEBR, r) 1045 opset(ACLFDBR, r) 1046 opset(ACLGEBR, r) 1047 opset(ACLGDBR, r) 1048 case AFIEBR: 1049 opset(AFIDBR, r) 1050 case ACMPBEQ: 1051 opset(ACMPBGE, r) 1052 opset(ACMPBGT, r) 1053 opset(ACMPBLE, r) 1054 opset(ACMPBLT, r) 1055 opset(ACMPBNE, r) 1056 case ACMPUBEQ: 1057 opset(ACMPUBGE, r) 1058 opset(ACMPUBGT, r) 1059 opset(ACMPUBLE, r) 1060 opset(ACMPUBLT, r) 1061 opset(ACMPUBNE, r) 1062 case ACGRJ: 1063 opset(ACRJ, r) 1064 case ACLGRJ: 1065 opset(ACLRJ, r) 1066 case ACGIJ: 1067 opset(ACIJ, r) 1068 case ACLGIJ: 1069 opset(ACLIJ, r) 1070 case AMOVDEQ: 1071 opset(AMOVDGE, r) 1072 opset(AMOVDGT, r) 1073 opset(AMOVDLE, r) 1074 opset(AMOVDLT, r) 1075 opset(AMOVDNE, r) 1076 case ALOCGR: 1077 opset(ALOCR, r) 1078 case ALTDBR: 1079 opset(ALTEBR, r) 1080 case ATCDB: 1081 opset(ATCEB, r) 1082 case AVL: 1083 opset(AVLLEZB, r) 1084 opset(AVLLEZH, r) 1085 opset(AVLLEZF, r) 1086 opset(AVLLEZG, r) 1087 opset(AVLREPB, r) 1088 opset(AVLREPH, r) 1089 opset(AVLREPF, r) 1090 opset(AVLREPG, r) 1091 case AVLEG: 1092 opset(AVLBB, r) 1093 opset(AVLEB, r) 1094 opset(AVLEH, r) 1095 opset(AVLEF, r) 1096 opset(AVLEG, r) 1097 opset(AVLREP, r) 1098 case AVSTEG: 1099 opset(AVSTEB, r) 1100 opset(AVSTEH, r) 1101 opset(AVSTEF, r) 1102 case AVSCEG: 1103 opset(AVSCEF, r) 1104 case AVGEG: 1105 opset(AVGEF, r) 1106 case AVESLG: 1107 opset(AVESLB, r) 1108 opset(AVESLH, r) 1109 opset(AVESLF, r) 1110 opset(AVERLLB, r) 1111 opset(AVERLLH, r) 1112 opset(AVERLLF, r) 1113 opset(AVERLLG, r) 1114 opset(AVESRAB, r) 1115 opset(AVESRAH, r) 1116 opset(AVESRAF, r) 1117 opset(AVESRAG, r) 1118 opset(AVESRLB, r) 1119 opset(AVESRLH, r) 1120 opset(AVESRLF, r) 1121 opset(AVESRLG, r) 1122 case AVLGVG: 1123 opset(AVLGVB, r) 1124 opset(AVLGVH, r) 1125 opset(AVLGVF, r) 1126 case AVLVGG: 1127 opset(AVLVGB, r) 1128 opset(AVLVGH, r) 1129 opset(AVLVGF, r) 1130 case AVZERO: 1131 opset(AVONE, r) 1132 case AVREPIG: 1133 opset(AVREPIB, r) 1134 opset(AVREPIH, r) 1135 opset(AVREPIF, r) 1136 case AVLEIG: 1137 opset(AVLEIB, r) 1138 opset(AVLEIH, r) 1139 opset(AVLEIF, r) 1140 case AVGMG: 1141 opset(AVGMB, r) 1142 opset(AVGMH, r) 1143 opset(AVGMF, r) 1144 case AVREPG: 1145 opset(AVREPB, r) 1146 opset(AVREPH, r) 1147 opset(AVREPF, r) 1148 case AVERIMG: 1149 opset(AVERIMB, r) 1150 opset(AVERIMH, r) 1151 opset(AVERIMF, r) 1152 case AVFTCIDB: 1153 opset(AWFTCIDB, r) 1154 case AVLR: 1155 opset(AVUPHB, r) 1156 opset(AVUPHH, r) 1157 opset(AVUPHF, r) 1158 opset(AVUPLHB, r) 1159 opset(AVUPLHH, r) 1160 opset(AVUPLHF, r) 1161 opset(AVUPLB, r) 1162 opset(AVUPLHW, r) 1163 opset(AVUPLF, r) 1164 opset(AVUPLLB, r) 1165 opset(AVUPLLH, r) 1166 opset(AVUPLLF, r) 1167 opset(AVCLZB, r) 1168 opset(AVCLZH, r) 1169 opset(AVCLZF, r) 1170 opset(AVCLZG, r) 1171 opset(AVCTZB, r) 1172 opset(AVCTZH, r) 1173 opset(AVCTZF, r) 1174 opset(AVCTZG, r) 1175 opset(AVLDEB, r) 1176 opset(AWLDEB, r) 1177 opset(AVFLCDB, r) 1178 opset(AWFLCDB, r) 1179 opset(AVFLNDB, r) 1180 opset(AWFLNDB, r) 1181 opset(AVFLPDB, r) 1182 opset(AWFLPDB, r) 1183 opset(AVFSQDB, r) 1184 opset(AWFSQDB, r) 1185 opset(AVISTRB, r) 1186 opset(AVISTRH, r) 1187 opset(AVISTRF, r) 1188 opset(AVISTRBS, r) 1189 opset(AVISTRHS, r) 1190 opset(AVISTRFS, r) 1191 opset(AVLCB, r) 1192 opset(AVLCH, r) 1193 opset(AVLCF, r) 1194 opset(AVLCG, r) 1195 opset(AVLPB, r) 1196 opset(AVLPH, r) 1197 opset(AVLPF, r) 1198 opset(AVLPG, r) 1199 opset(AVPOPCT, r) 1200 opset(AVSEGB, r) 1201 opset(AVSEGH, r) 1202 opset(AVSEGF, r) 1203 case AVECG: 1204 opset(AVECB, r) 1205 opset(AVECH, r) 1206 opset(AVECF, r) 1207 opset(AVECLB, r) 1208 opset(AVECLH, r) 1209 opset(AVECLF, r) 1210 opset(AVECLG, r) 1211 opset(AWFCDB, r) 1212 opset(AWFKDB, r) 1213 case AVCEQG: 1214 opset(AVCEQB, r) 1215 opset(AVCEQH, r) 1216 opset(AVCEQF, r) 1217 opset(AVCEQBS, r) 1218 opset(AVCEQHS, r) 1219 opset(AVCEQFS, r) 1220 opset(AVCEQGS, r) 1221 opset(AVCHB, r) 1222 opset(AVCHH, r) 1223 opset(AVCHF, r) 1224 opset(AVCHG, r) 1225 opset(AVCHBS, r) 1226 opset(AVCHHS, r) 1227 opset(AVCHFS, r) 1228 opset(AVCHGS, r) 1229 opset(AVCHLB, r) 1230 opset(AVCHLH, r) 1231 opset(AVCHLF, r) 1232 opset(AVCHLG, r) 1233 opset(AVCHLBS, r) 1234 opset(AVCHLHS, r) 1235 opset(AVCHLFS, r) 1236 opset(AVCHLGS, r) 1237 case AVFAEF: 1238 opset(AVFAEB, r) 1239 opset(AVFAEH, r) 1240 opset(AVFAEBS, r) 1241 opset(AVFAEHS, r) 1242 opset(AVFAEFS, r) 1243 opset(AVFAEZB, r) 1244 opset(AVFAEZH, r) 1245 opset(AVFAEZF, r) 1246 opset(AVFAEZBS, r) 1247 opset(AVFAEZHS, r) 1248 opset(AVFAEZFS, r) 1249 opset(AVFEEB, r) 1250 opset(AVFEEH, r) 1251 opset(AVFEEF, r) 1252 opset(AVFEEBS, r) 1253 opset(AVFEEHS, r) 1254 opset(AVFEEFS, r) 1255 opset(AVFEEZB, r) 1256 opset(AVFEEZH, r) 1257 opset(AVFEEZF, r) 1258 opset(AVFEEZBS, r) 1259 opset(AVFEEZHS, r) 1260 opset(AVFEEZFS, r) 1261 opset(AVFENEB, r) 1262 opset(AVFENEH, r) 1263 opset(AVFENEF, r) 1264 opset(AVFENEBS, r) 1265 opset(AVFENEHS, r) 1266 opset(AVFENEFS, r) 1267 opset(AVFENEZB, r) 1268 opset(AVFENEZH, r) 1269 opset(AVFENEZF, r) 1270 opset(AVFENEZBS, r) 1271 opset(AVFENEZHS, r) 1272 opset(AVFENEZFS, r) 1273 case AVPKSG: 1274 opset(AVPKSH, r) 1275 opset(AVPKSF, r) 1276 opset(AVPKSHS, r) 1277 opset(AVPKSFS, r) 1278 opset(AVPKSGS, r) 1279 opset(AVPKLSH, r) 1280 opset(AVPKLSF, r) 1281 opset(AVPKLSG, r) 1282 opset(AVPKLSHS, r) 1283 opset(AVPKLSFS, r) 1284 opset(AVPKLSGS, r) 1285 case AVAQ: 1286 opset(AVAB, r) 1287 opset(AVAH, r) 1288 opset(AVAF, r) 1289 opset(AVAG, r) 1290 opset(AVACCB, r) 1291 opset(AVACCH, r) 1292 opset(AVACCF, r) 1293 opset(AVACCG, r) 1294 opset(AVACCQ, r) 1295 opset(AVN, r) 1296 opset(AVNC, r) 1297 opset(AVAVGB, r) 1298 opset(AVAVGH, r) 1299 opset(AVAVGF, r) 1300 opset(AVAVGG, r) 1301 opset(AVAVGLB, r) 1302 opset(AVAVGLH, r) 1303 opset(AVAVGLF, r) 1304 opset(AVAVGLG, r) 1305 opset(AVCKSM, r) 1306 opset(AVX, r) 1307 opset(AVFADB, r) 1308 opset(AWFADB, r) 1309 opset(AVFCEDB, r) 1310 opset(AVFCEDBS, r) 1311 opset(AWFCEDB, r) 1312 opset(AWFCEDBS, r) 1313 opset(AVFCHDB, r) 1314 opset(AVFCHDBS, r) 1315 opset(AWFCHDB, r) 1316 opset(AWFCHDBS, r) 1317 opset(AVFCHEDB, r) 1318 opset(AVFCHEDBS, r) 1319 opset(AWFCHEDB, r) 1320 opset(AWFCHEDBS, r) 1321 opset(AVFMDB, r) 1322 opset(AWFMDB, r) 1323 opset(AVGFMB, r) 1324 opset(AVGFMH, r) 1325 opset(AVGFMF, r) 1326 opset(AVGFMG, r) 1327 opset(AVMXB, r) 1328 opset(AVMXH, r) 1329 opset(AVMXF, r) 1330 opset(AVMXG, r) 1331 opset(AVMXLB, r) 1332 opset(AVMXLH, r) 1333 opset(AVMXLF, r) 1334 opset(AVMXLG, r) 1335 opset(AVMNB, r) 1336 opset(AVMNH, r) 1337 opset(AVMNF, r) 1338 opset(AVMNG, r) 1339 opset(AVMNLB, r) 1340 opset(AVMNLH, r) 1341 opset(AVMNLF, r) 1342 opset(AVMNLG, r) 1343 opset(AVMRHB, r) 1344 opset(AVMRHH, r) 1345 opset(AVMRHF, r) 1346 opset(AVMRHG, r) 1347 opset(AVMRLB, r) 1348 opset(AVMRLH, r) 1349 opset(AVMRLF, r) 1350 opset(AVMRLG, r) 1351 opset(AVMEB, r) 1352 opset(AVMEH, r) 1353 opset(AVMEF, r) 1354 opset(AVMLEB, r) 1355 opset(AVMLEH, r) 1356 opset(AVMLEF, r) 1357 opset(AVMOB, r) 1358 opset(AVMOH, r) 1359 opset(AVMOF, r) 1360 opset(AVMLOB, r) 1361 opset(AVMLOH, r) 1362 opset(AVMLOF, r) 1363 opset(AVMHB, r) 1364 opset(AVMHH, r) 1365 opset(AVMHF, r) 1366 opset(AVMLHB, r) 1367 opset(AVMLHH, r) 1368 opset(AVMLHF, r) 1369 opset(AVMLH, r) 1370 opset(AVMLHW, r) 1371 opset(AVMLF, r) 1372 opset(AVNO, r) 1373 opset(AVO, r) 1374 opset(AVPKH, r) 1375 opset(AVPKF, r) 1376 opset(AVPKG, r) 1377 opset(AVSUMGH, r) 1378 opset(AVSUMGF, r) 1379 opset(AVSUMQF, r) 1380 opset(AVSUMQG, r) 1381 opset(AVSUMB, r) 1382 opset(AVSUMH, r) 1383 case AVERLLVG: 1384 opset(AVERLLVB, r) 1385 opset(AVERLLVH, r) 1386 opset(AVERLLVF, r) 1387 opset(AVESLVB, r) 1388 opset(AVESLVH, r) 1389 opset(AVESLVF, r) 1390 opset(AVESLVG, r) 1391 opset(AVESRAVB, r) 1392 opset(AVESRAVH, r) 1393 opset(AVESRAVF, r) 1394 opset(AVESRAVG, r) 1395 opset(AVESRLVB, r) 1396 opset(AVESRLVH, r) 1397 opset(AVESRLVF, r) 1398 opset(AVESRLVG, r) 1399 opset(AVFDDB, r) 1400 opset(AWFDDB, r) 1401 opset(AVFSDB, r) 1402 opset(AWFSDB, r) 1403 opset(AVSL, r) 1404 opset(AVSLB, r) 1405 opset(AVSRA, r) 1406 opset(AVSRAB, r) 1407 opset(AVSRL, r) 1408 opset(AVSRLB, r) 1409 opset(AVSB, r) 1410 opset(AVSH, r) 1411 opset(AVSF, r) 1412 opset(AVSG, r) 1413 opset(AVSQ, r) 1414 opset(AVSCBIB, r) 1415 opset(AVSCBIH, r) 1416 opset(AVSCBIF, r) 1417 opset(AVSCBIG, r) 1418 opset(AVSCBIQ, r) 1419 case AVACQ: 1420 opset(AVACCCQ, r) 1421 opset(AVGFMAB, r) 1422 opset(AVGFMAH, r) 1423 opset(AVGFMAF, r) 1424 opset(AVGFMAG, r) 1425 opset(AVMALB, r) 1426 opset(AVMALHW, r) 1427 opset(AVMALF, r) 1428 opset(AVMAHB, r) 1429 opset(AVMAHH, r) 1430 opset(AVMAHF, r) 1431 opset(AVMALHB, r) 1432 opset(AVMALHH, r) 1433 opset(AVMALHF, r) 1434 opset(AVMAEB, r) 1435 opset(AVMAEH, r) 1436 opset(AVMAEF, r) 1437 opset(AVMALEB, r) 1438 opset(AVMALEH, r) 1439 opset(AVMALEF, r) 1440 opset(AVMAOB, r) 1441 opset(AVMAOH, r) 1442 opset(AVMAOF, r) 1443 opset(AVMALOB, r) 1444 opset(AVMALOH, r) 1445 opset(AVMALOF, r) 1446 opset(AVSTRCB, r) 1447 opset(AVSTRCH, r) 1448 opset(AVSTRCF, r) 1449 opset(AVSTRCBS, r) 1450 opset(AVSTRCHS, r) 1451 opset(AVSTRCFS, r) 1452 opset(AVSTRCZB, r) 1453 opset(AVSTRCZH, r) 1454 opset(AVSTRCZF, r) 1455 opset(AVSTRCZBS, r) 1456 opset(AVSTRCZHS, r) 1457 opset(AVSTRCZFS, r) 1458 opset(AVSBCBIQ, r) 1459 opset(AVSBIQ, r) 1460 opset(AVMSLG, r) 1461 opset(AVMSLEG, r) 1462 opset(AVMSLOG, r) 1463 opset(AVMSLEOG, r) 1464 case AVSEL: 1465 opset(AVFMADB, r) 1466 opset(AWFMADB, r) 1467 opset(AVFMSDB, r) 1468 opset(AWFMSDB, r) 1469 opset(AVPERM, r) 1470 } 1471 } 1472} 1473 1474const ( 1475 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1476 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1477 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1478 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1479 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1480 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1481 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1482 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1483 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1484 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1485 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1486 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1487 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1488 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1489 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1490 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1491 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1492 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1493 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1494 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1495 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1496 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1497 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1498 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1499 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1500 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1501 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1502 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1503 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1504 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1505 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1506 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1507 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1508 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1509 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1510 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1511 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1512 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1513 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1514 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1515 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1516 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1517 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1518 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1519 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1520 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1521 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1522 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1523 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1524 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1525 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1526 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1527 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1528 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1529 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1530 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1531 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1532 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1533 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1534 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1535 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1536 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1537 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1538 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1539 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1540 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1541 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1542 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1543 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1544 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1545 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1546 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1547 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1548 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1549 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1550 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1551 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1552 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1553 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1554 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1555 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1556 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1557 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1558 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1559 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1560 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1561 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1562 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1563 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1564 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1565 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1566 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1567 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1568 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1569 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1570 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1571 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1572 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1573 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1574 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1575 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1576 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1577 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1578 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1579 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1580 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1581 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1582 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1583 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1584 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1585 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1586 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1587 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1588 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1589 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1590 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1591 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1592 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1593 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1594 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1595 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1596 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1597 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1598 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1599 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1600 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1601 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1602 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1603 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1604 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1605 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1606 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1607 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1608 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1609 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1610 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1611 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1612 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1613 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1614 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1615 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1616 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1617 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1618 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1619 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1620 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1621 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1622 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1623 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1624 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1625 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1626 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1627 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1628 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1629 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1630 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1631 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1632 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1633 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1634 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1635 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1636 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1637 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1638 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1639 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1640 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1641 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1642 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1643 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1644 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1645 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1646 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1647 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1648 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1649 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1650 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1651 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1652 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1653 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1654 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1655 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1656 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1657 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1658 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1659 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1660 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1661 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1662 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1663 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1664 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1665 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1666 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1667 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1668 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1669 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1670 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1671 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1672 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1673 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1674 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1675 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1676 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1677 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1678 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1679 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1680 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1681 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1682 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1683 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1684 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1685 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1686 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1687 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1688 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1689 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1690 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1691 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1692 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1693 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1694 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1695 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1696 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1697 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1698 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1699 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1700 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1701 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1702 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1703 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1704 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1705 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1706 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1707 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1708 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1709 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1710 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1711 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1712 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1713 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1714 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1715 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1716 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1717 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1718 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1719 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1720 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1721 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1722 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1723 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1724 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1725 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1726 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1727 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1728 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1729 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1730 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1731 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1732 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1733 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1734 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1735 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1736 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1737 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1738 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1739 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1740 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1741 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1742 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1743 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1744 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1745 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1746 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1747 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1748 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1749 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1750 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1751 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1752 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1753 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1754 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1755 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1756 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1757 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1758 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1759 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1760 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1761 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1762 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1763 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1764 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1765 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1766 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1767 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1768 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1769 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1770 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1771 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1772 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1773 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1774 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1775 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1776 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1777 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1778 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1779 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1780 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1781 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1782 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1783 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1784 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1785 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1786 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1787 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1788 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1789 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1790 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1791 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1792 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1793 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1794 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1795 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1796 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1797 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1798 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1799 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1800 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1801 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1802 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1803 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1804 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1805 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1806 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1807 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1808 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1809 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1810 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1811 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1812 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1813 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1814 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1815 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1816 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1817 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1818 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1819 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1820 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1821 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1822 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1823 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1824 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1825 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1826 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1827 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1828 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1829 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1830 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1831 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1832 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1833 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1834 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1835 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1836 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1837 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1838 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1839 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1840 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1841 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1842 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1843 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1844 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1845 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1846 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1847 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1848 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1849 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1850 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1851 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1852 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1853 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1854 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1855 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1856 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1857 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1858 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1859 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1860 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1861 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1862 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1863 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1864 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1865 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1866 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1867 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1868 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1869 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1870 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1871 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1872 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1873 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1874 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1875 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1876 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1877 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1878 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1879 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1880 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1881 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1882 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1883 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1884 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1885 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1886 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1887 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1888 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1889 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1890 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1891 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1892 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1893 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1894 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1895 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1896 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1897 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1898 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1899 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1900 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1901 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1902 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1903 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1904 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1905 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1906 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1907 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1908 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1909 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1910 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1911 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1912 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1913 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1914 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1915 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1916 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1917 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1918 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1919 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1920 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1921 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1922 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1923 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1924 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1925 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1926 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1927 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1928 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1929 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1930 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1931 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1932 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1933 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1934 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1935 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1936 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1937 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1938 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1939 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1940 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1941 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1942 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1943 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1944 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1945 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1946 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1947 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1948 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1949 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1950 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1951 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1952 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1953 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1954 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1955 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1956 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1957 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1958 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1959 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1960 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1961 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1962 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1963 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1964 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1965 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1966 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1967 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1968 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1969 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1970 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1971 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1972 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1973 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1974 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1975 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1976 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1977 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1978 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1979 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1980 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1981 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1982 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1983 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1984 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1985 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1986 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1987 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1988 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1989 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1990 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1991 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1992 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1993 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1994 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1995 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1996 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1997 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1998 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1999 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 2000 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 2001 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 2002 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 2003 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 2004 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 2005 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 2006 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 2007 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 2008 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 2009 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 2010 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 2011 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 2012 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 2013 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 2014 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 2015 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 2016 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 2017 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 2018 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 2019 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 2020 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 2021 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 2022 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 2023 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 2024 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 2025 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 2026 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 2027 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 2028 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 2029 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 2030 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 2031 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 2032 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 2033 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 2034 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 2035 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 2036 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 2037 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 2038 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 2039 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 2040 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 2041 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 2042 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 2043 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 2044 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 2045 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 2046 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 2047 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 2048 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 2049 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 2050 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 2051 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 2052 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 2053 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 2054 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 2055 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 2056 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 2057 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 2058 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 2059 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 2060 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 2061 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 2062 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 2063 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 2064 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 2065 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 2066 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 2067 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 2068 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 2069 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 2070 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 2071 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 2072 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 2073 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 2074 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 2075 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 2076 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 2077 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 2078 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 2079 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 2080 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 2081 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 2082 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 2083 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2084 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 2085 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 2086 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2087 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 2088 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 2089 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 2090 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 2091 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 2092 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 2093 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 2094 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 2095 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 2096 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 2097 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 2098 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 2099 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 2100 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 2101 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 2102 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 2103 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 2104 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 2105 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 2106 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 2107 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 2108 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 2109 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 2110 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 2111 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 2112 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 2113 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 2114 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 2115 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 2116 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 2117 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 2118 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 2119 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 2120 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 2121 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 2122 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 2123 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 2124 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 2125 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 2126 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 2127 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 2128 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 2129 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 2130 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 2131 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 2132 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 2133 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 2134 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 2135 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 2136 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 2137 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2138 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2139 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2140 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2141 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2142 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2143 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2144 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2145 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2146 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2147 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2148 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2149 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2150 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2151 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2152 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2153 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2154 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2155 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2156 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2157 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2158 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2159 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2160 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2161 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2162 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2163 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2164 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2165 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2166 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2167 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2168 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2169 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2170 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2171 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2172 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2173 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2174 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2175 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2176 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2177 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2178 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2179 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2180 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2181 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2182 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2183 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2184 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2185 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2186 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2187 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2188 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2189 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2190 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2191 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2192 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2193 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2194 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2195 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2196 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2197 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2198 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2199 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2200 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2201 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2202 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2203 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2204 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2205 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2206 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2207 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2208 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2209 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2210 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2211 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2212 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2213 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2214 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2215 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2216 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2217 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2218 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2219 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2220 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2221 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2222 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2223 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2224 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2225 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2226 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2227 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2228 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2229 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2230 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2231 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2232 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2233 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2234 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2235 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2236 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2237 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2238 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2239 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2240 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2241 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2242 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2243 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2244 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2245 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2246 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2247 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2248 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2249 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2250 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2251 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2252 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2253 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2254 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2255 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2256 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2257 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2258 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2259 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2260 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2261 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2262 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2263 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2264 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2265 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2266 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2267 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2268 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2269 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2270 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2271 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2272 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2273 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2274 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2275 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2276 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2277 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2278 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2279 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2280 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2281 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2282 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2283 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2284 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2285 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2286 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2287 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2288 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2289 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2290 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2291 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2292 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2293 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2294 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2295 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2296 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2297 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2298 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2299 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2300 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2301 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2302 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2303 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2304 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2305 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2306 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2307 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2308 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2309 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2310 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2311 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2312 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2313 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2314 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2315 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2316 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2317 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2318 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2319 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2320 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2321 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2322 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2323 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2324 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2325 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2326 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2327 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2328 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2329 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2330 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2331 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2332 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2333 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2334 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2335 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2336 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2337 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2338 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2339 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2340 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2341 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2342 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2343 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2344 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2345 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2346 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2347 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2348 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2349 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2350 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2351 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2352 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2353 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2354 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2355 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2356 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2357 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2358 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2359 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2360 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2361 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2362 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2363 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2364 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2365 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2366 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2367 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2368 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2369 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2370 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2371 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2372 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2373 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2374 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2375 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2376 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2377 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2378 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2379 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2380 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2381 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2382 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2383 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2384 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2385 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2386 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2387 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2388 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2389 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2390 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2391 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2392 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2393 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2394 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2395 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2396 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2397 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2398 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2399 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2400 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2401 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2402 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2403 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2404 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2405 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2406 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2407 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2408 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2409 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2410 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2411 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2412 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2413 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2414 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2415 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2416 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2417 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2418 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2419 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2420 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2421 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2422 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2423 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2424 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2425 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2426 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2427 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2428 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2429 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2430 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2431 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2432 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2433 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2434 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2435 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2436 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2437 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2438 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2439 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2440 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2441 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2442 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2443 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2444 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2445 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2446 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2447 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2448 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2449 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2450 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2451 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2452 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2453 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2454 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2455 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2456 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2457 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2458 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2459 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2460 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2461 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2462 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2463 2464 // added in z13 2465 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2466 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2467 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2468 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2469 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2470 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2471 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2472 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2473 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2474 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2475 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2476 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2477 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2478 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2479 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2480 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2481 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2482 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2483 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2484 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2485 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2486 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2487 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2488 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2489 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2490 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2491 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2492 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2493 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2494 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2495 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2496 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2497 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2498 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2499 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2500 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2501 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2502 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2503 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2504 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2505 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2506 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2507 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2508 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2509 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2510 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2511 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2512 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2513 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2514 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2515 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2516 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2517 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2518 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2519 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2520 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2521 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2522 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2523 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2524 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2525 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2526 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2527 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2528 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2529 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2530 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2531 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2532 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2533 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2534 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2535 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2536 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2537 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2538 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2539 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2540 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2541 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2542 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2543 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2544 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2545 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2546 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2547 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2548 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2549 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2550 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2551 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2552 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2553 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2554 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2555 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2556 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2557 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2558 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2559 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2560 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2561 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2562 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2563 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2564 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2565 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2566 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2567 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2568 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2569 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2570 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2571 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2572 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2573 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2574 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2575 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2576 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2577 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2578 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2579 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2580 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2581 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2582 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2583 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2584 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2585 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2586 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2587 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2588 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2589 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2590 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2591 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2592 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2593 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2594 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2595 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2596 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2597 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2598 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2599 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2600 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2601 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2602 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2603 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2604 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2605 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2606 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2607 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2608 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2609 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2610 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2611 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2612 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2613 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2614 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2615 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2616 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2617 op_VMSL uint32 = 0xE7B8 // VRR-d VECTOR MULTIPLY SUM LOGICAL 2618) 2619 2620func oclass(a *obj.Addr) int { 2621 return int(a.Class) - 1 2622} 2623 2624// Add a relocation for the immediate in a RIL style instruction. 2625// The addend will be adjusted as required. 2626func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc { 2627 if sym == nil { 2628 c.ctxt.Diag("require symbol to apply relocation") 2629 } 2630 offset := int64(2) // relocation offset from start of instruction 2631 rel := obj.Addrel(c.cursym) 2632 rel.Off = int32(c.pc + offset) 2633 rel.Siz = 4 2634 rel.Sym = sym 2635 rel.Add = add + offset + int64(rel.Siz) 2636 rel.Type = objabi.R_PCRELDBL 2637 return rel 2638} 2639 2640func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc { 2641 if sym == nil { 2642 c.ctxt.Diag("require symbol to apply relocation") 2643 } 2644 offset += int64(2) // relocation offset from start of instruction 2645 rel := obj.Addrel(c.cursym) 2646 rel.Off = int32(c.pc + offset) 2647 rel.Siz = 4 2648 rel.Sym = sym 2649 rel.Add = add + offset + int64(rel.Siz) 2650 rel.Type = objabi.R_PCRELDBL 2651 return rel 2652} 2653 2654// Add a CALL relocation for the immediate in a RIL style instruction. 2655// The addend will be adjusted as required. 2656func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc { 2657 if sym == nil { 2658 c.ctxt.Diag("require symbol to apply relocation") 2659 } 2660 offset := int64(2) // relocation offset from start of instruction 2661 rel := obj.Addrel(c.cursym) 2662 rel.Off = int32(c.pc + offset) 2663 rel.Siz = 4 2664 rel.Sym = sym 2665 rel.Add = add + offset + int64(rel.Siz) 2666 rel.Type = objabi.R_CALL 2667 return rel 2668} 2669 2670func (c *ctxtz) branchMask(p *obj.Prog) CCMask { 2671 switch p.As { 2672 case ABRC, ALOCR, ALOCGR, 2673 ACRJ, ACGRJ, ACIJ, ACGIJ, 2674 ACLRJ, ACLGRJ, ACLIJ, ACLGIJ: 2675 return CCMask(p.From.Offset) 2676 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2677 return Equal 2678 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2679 return GreaterOrEqual 2680 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2681 return Greater 2682 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2683 return LessOrEqual 2684 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2685 return Less 2686 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2687 return NotEqual 2688 case ABLEU: // LE or unordered 2689 return NotGreater 2690 case ABLTU: // LT or unordered 2691 return LessOrUnordered 2692 case ABVC: 2693 return Never // needs extra instruction 2694 case ABVS: 2695 return Unordered 2696 } 2697 c.ctxt.Diag("unknown conditional branch %v", p.As) 2698 return Always 2699} 2700 2701func regtmp(p *obj.Prog) uint32 { 2702 p.Mark |= USETMP 2703 return REGTMP 2704} 2705 2706func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { 2707 o := c.oplook(p) 2708 2709 if o == nil { 2710 return 2711 } 2712 2713 // If REGTMP is used in generated code, we need to set USETMP on p.Mark. 2714 // So we use regtmp(p) for REGTMP. 2715 2716 switch o.i { 2717 default: 2718 c.ctxt.Diag("unknown index %d", o.i) 2719 2720 case 0: // PSEUDO OPS 2721 break 2722 2723 case 1: // mov reg reg 2724 switch p.As { 2725 default: 2726 c.ctxt.Diag("unhandled operation: %v", p.As) 2727 case AMOVD: 2728 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2729 // sign extend 2730 case AMOVW: 2731 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2732 case AMOVH: 2733 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2734 case AMOVB: 2735 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2736 // zero extend 2737 case AMOVWZ: 2738 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2739 case AMOVHZ: 2740 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2741 case AMOVBZ: 2742 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2743 // reverse bytes 2744 case AMOVDBR: 2745 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2746 case AMOVWBR: 2747 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2748 // floating point 2749 case AFMOVD, AFMOVS: 2750 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2751 } 2752 2753 case 2: // arithmetic op reg [reg] reg 2754 r := p.Reg 2755 if r == 0 { 2756 r = p.To.Reg 2757 } 2758 2759 var opcode uint32 2760 2761 switch p.As { 2762 default: 2763 c.ctxt.Diag("invalid opcode") 2764 case AADD: 2765 opcode = op_AGRK 2766 case AADDC: 2767 opcode = op_ALGRK 2768 case AADDE: 2769 opcode = op_ALCGR 2770 case AADDW: 2771 opcode = op_ARK 2772 case AMULLW: 2773 opcode = op_MSGFR 2774 case AMULLD: 2775 opcode = op_MSGR 2776 case ADIVW, AMODW: 2777 opcode = op_DSGFR 2778 case ADIVWU, AMODWU: 2779 opcode = op_DLR 2780 case ADIVD, AMODD: 2781 opcode = op_DSGR 2782 case ADIVDU, AMODDU: 2783 opcode = op_DLGR 2784 } 2785 2786 switch p.As { 2787 default: 2788 2789 case AADD, AADDC, AADDW: 2790 if p.As == AADDW && r == p.To.Reg { 2791 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2792 } else { 2793 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2794 } 2795 2796 case AADDE, AMULLW, AMULLD: 2797 if r == p.To.Reg { 2798 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2799 } else if p.From.Reg == p.To.Reg { 2800 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2801 } else { 2802 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2803 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2804 } 2805 2806 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2807 if p.As == ADIVWU || p.As == ADIVDU { 2808 zRI(op_LGHI, regtmp(p), 0, asm) 2809 } 2810 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2811 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm) 2812 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2813 2814 case AMODW, AMODWU, AMODD, AMODDU: 2815 if p.As == AMODWU || p.As == AMODDU { 2816 zRI(op_LGHI, regtmp(p), 0, asm) 2817 } 2818 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2819 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm) 2820 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm) 2821 2822 } 2823 2824 case 3: // mov $constant reg 2825 v := c.vregoff(&p.From) 2826 switch p.As { 2827 case AMOVBZ: 2828 v = int64(uint8(v)) 2829 case AMOVHZ: 2830 v = int64(uint16(v)) 2831 case AMOVWZ: 2832 v = int64(uint32(v)) 2833 case AMOVB: 2834 v = int64(int8(v)) 2835 case AMOVH: 2836 v = int64(int16(v)) 2837 case AMOVW: 2838 v = int64(int32(v)) 2839 } 2840 if int64(int16(v)) == v { 2841 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2842 } else if v&0xffff0000 == v { 2843 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2844 } else if v&0xffff00000000 == v { 2845 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2846 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2847 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2848 } else if int64(int32(v)) == v { 2849 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2850 } else if int64(uint32(v)) == v { 2851 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2852 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2853 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2854 } else { 2855 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2856 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2857 } 2858 2859 case 4: // multiply high (a*b)>>64 2860 r := p.Reg 2861 if r == 0 { 2862 r = p.To.Reg 2863 } 2864 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2865 zRRE(op_MLGR, regtmp(p), uint32(p.From.Reg), asm) 2866 switch p.As { 2867 case AMULHDU: 2868 // Unsigned: move result into correct register. 2869 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm) 2870 case AMULHD: 2871 // Signed: need to convert result. 2872 // See Hacker's Delight 8-3. 2873 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2874 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2875 zRRE(op_SGR, regtmp(p), REGTMP2, asm) 2876 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2877 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2878 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), regtmp(p), asm) 2879 } 2880 2881 case 5: // syscall 2882 zI(op_SVC, 0, asm) 2883 2884 case 6: // logical op reg [reg] reg 2885 var oprr, oprre, oprrf uint32 2886 switch p.As { 2887 case AAND: 2888 oprre = op_NGR 2889 oprrf = op_NGRK 2890 case AANDW: 2891 oprr = op_NR 2892 oprrf = op_NRK 2893 case AOR: 2894 oprre = op_OGR 2895 oprrf = op_OGRK 2896 case AORW: 2897 oprr = op_OR 2898 oprrf = op_ORK 2899 case AXOR: 2900 oprre = op_XGR 2901 oprrf = op_XGRK 2902 case AXORW: 2903 oprr = op_XR 2904 oprrf = op_XRK 2905 } 2906 if p.Reg == 0 { 2907 if oprr != 0 { 2908 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2909 } else { 2910 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2911 } 2912 } else { 2913 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2914 } 2915 2916 case 7: // shift/rotate reg [reg] reg 2917 d2 := c.vregoff(&p.From) 2918 b2 := p.From.Reg 2919 r3 := p.Reg 2920 if r3 == 0 { 2921 r3 = p.To.Reg 2922 } 2923 r1 := p.To.Reg 2924 var opcode uint32 2925 switch p.As { 2926 default: 2927 case ASLD: 2928 opcode = op_SLLG 2929 case ASRD: 2930 opcode = op_SRLG 2931 case ASLW: 2932 opcode = op_SLLK 2933 case ASRW: 2934 opcode = op_SRLK 2935 case ARLL: 2936 opcode = op_RLL 2937 case ARLLG: 2938 opcode = op_RLLG 2939 case ASRAW: 2940 opcode = op_SRAK 2941 case ASRAD: 2942 opcode = op_SRAG 2943 } 2944 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2945 2946 case 8: // find leftmost one 2947 if p.To.Reg&1 != 0 { 2948 c.ctxt.Diag("target must be an even-numbered register") 2949 } 2950 // FLOGR also writes a mask to p.To.Reg+1. 2951 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2952 2953 case 9: // population count 2954 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2955 2956 case 10: // subtract reg [reg] reg 2957 r := int(p.Reg) 2958 2959 switch p.As { 2960 default: 2961 case ASUB: 2962 if r == 0 { 2963 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2964 } else { 2965 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2966 } 2967 case ASUBC: 2968 if r == 0 { 2969 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2970 } else { 2971 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2972 } 2973 case ASUBE: 2974 if r == 0 { 2975 r = int(p.To.Reg) 2976 } 2977 if r == int(p.To.Reg) { 2978 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2979 } else if p.From.Reg == p.To.Reg { 2980 zRRE(op_LGR, regtmp(p), uint32(p.From.Reg), asm) 2981 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2982 zRRE(op_SLBGR, uint32(p.To.Reg), regtmp(p), asm) 2983 } else { 2984 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2985 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2986 } 2987 case ASUBW: 2988 if r == 0 { 2989 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2990 } else { 2991 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2992 } 2993 } 2994 2995 case 11: // br/bl 2996 v := int32(0) 2997 2998 if p.Pcond != nil { 2999 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3000 } 3001 3002 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 3003 zRI(op_BRC, 0xF, uint32(v), asm) 3004 } else { 3005 if p.As == ABL { 3006 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 3007 } else { 3008 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 3009 } 3010 if p.To.Sym != nil { 3011 c.addcallreloc(p.To.Sym, p.To.Offset) 3012 } 3013 } 3014 3015 case 12: 3016 r1 := p.To.Reg 3017 d2 := c.vregoff(&p.From) 3018 b2 := p.From.Reg 3019 if b2 == 0 { 3020 b2 = REGSP 3021 } 3022 x2 := p.From.Index 3023 if -DISP20/2 > d2 || d2 >= DISP20/2 { 3024 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3025 if x2 != 0 { 3026 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3027 } 3028 x2 = int16(regtmp(p)) 3029 d2 = 0 3030 } 3031 var opx, opxy uint32 3032 switch p.As { 3033 case AADD: 3034 opxy = op_AG 3035 case AADDC: 3036 opxy = op_ALG 3037 case AADDW: 3038 opx = op_A 3039 opxy = op_AY 3040 case AMULLW: 3041 opx = op_MS 3042 opxy = op_MSY 3043 case AMULLD: 3044 opxy = op_MSG 3045 case ASUB: 3046 opxy = op_SG 3047 case ASUBC: 3048 opxy = op_SLG 3049 case ASUBE: 3050 opxy = op_SLBG 3051 case ASUBW: 3052 opx = op_S 3053 opxy = op_SY 3054 case AAND: 3055 opxy = op_NG 3056 case AANDW: 3057 opx = op_N 3058 opxy = op_NY 3059 case AOR: 3060 opxy = op_OG 3061 case AORW: 3062 opx = op_O 3063 opxy = op_OY 3064 case AXOR: 3065 opxy = op_XG 3066 case AXORW: 3067 opx = op_X 3068 opxy = op_XY 3069 } 3070 if opx != 0 && 0 <= d2 && d2 < DISP12 { 3071 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 3072 } else { 3073 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 3074 } 3075 3076 case 13: // rotate, followed by operation 3077 r1 := p.To.Reg 3078 r2 := p.RestArgs[2].Reg 3079 i3 := uint8(p.From.Offset) // start 3080 i4 := uint8(p.RestArgs[0].Offset) // end 3081 i5 := uint8(p.RestArgs[1].Offset) // rotate amount 3082 switch p.As { 3083 case ARNSBGT, ARXSBGT, AROSBGT: 3084 i3 |= 0x80 // test-results 3085 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ: 3086 i4 |= 0x80 // zero-remaining-bits 3087 } 3088 var opcode uint32 3089 switch p.As { 3090 case ARNSBG, ARNSBGT: 3091 opcode = op_RNSBG 3092 case ARXSBG, ARXSBGT: 3093 opcode = op_RXSBG 3094 case AROSBG, AROSBGT: 3095 opcode = op_ROSBG 3096 case ARISBG, ARISBGZ: 3097 opcode = op_RISBG 3098 case ARISBGN, ARISBGNZ: 3099 opcode = op_RISBGN 3100 case ARISBHG, ARISBHGZ: 3101 opcode = op_RISBHG 3102 case ARISBLG, ARISBLGZ: 3103 opcode = op_RISBLG 3104 } 3105 zRIE(_f, uint32(opcode), uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm) 3106 3107 case 15: // br/bl (reg) 3108 r := p.To.Reg 3109 if p.As == ABCL || p.As == ABL { 3110 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 3111 } else { 3112 zRR(op_BCR, uint32(Always), uint32(r), asm) 3113 } 3114 3115 case 16: // conditional branch 3116 v := int32(0) 3117 if p.Pcond != nil { 3118 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3119 } 3120 mask := uint32(c.branchMask(p)) 3121 if p.To.Sym == nil && int32(int16(v)) == v { 3122 zRI(op_BRC, mask, uint32(v), asm) 3123 } else { 3124 zRIL(_c, op_BRCL, mask, uint32(v), asm) 3125 } 3126 if p.To.Sym != nil { 3127 c.addrilreloc(p.To.Sym, p.To.Offset) 3128 } 3129 3130 case 17: // move on condition 3131 m3 := uint32(c.branchMask(p)) 3132 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3133 3134 case 18: // br/bl reg 3135 if p.As == ABL { 3136 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 3137 } else { 3138 zRR(op_BCR, uint32(Always), uint32(p.To.Reg), asm) 3139 } 3140 3141 case 19: // mov $sym+n(SB) reg 3142 d := c.vregoff(&p.From) 3143 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 3144 if d&1 != 0 { 3145 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 3146 d -= 1 3147 } 3148 c.addrilreloc(p.From.Sym, d) 3149 3150 case 21: // subtract $constant [reg] reg 3151 v := c.vregoff(&p.From) 3152 r := p.Reg 3153 if r == 0 { 3154 r = p.To.Reg 3155 } 3156 switch p.As { 3157 case ASUB: 3158 zRIL(_a, op_LGFI, uint32(regtmp(p)), uint32(v), asm) 3159 zRRF(op_SLGRK, uint32(regtmp(p)), 0, uint32(p.To.Reg), uint32(r), asm) 3160 case ASUBC: 3161 if r != p.To.Reg { 3162 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3163 } 3164 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 3165 case ASUBW: 3166 if r != p.To.Reg { 3167 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3168 } 3169 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 3170 } 3171 3172 case 22: // add/multiply $constant [reg] reg 3173 v := c.vregoff(&p.From) 3174 r := p.Reg 3175 if r == 0 { 3176 r = p.To.Reg 3177 } 3178 var opri, opril, oprie uint32 3179 switch p.As { 3180 case AADD: 3181 opri = op_AGHI 3182 opril = op_AGFI 3183 oprie = op_AGHIK 3184 case AADDC: 3185 opril = op_ALGFI 3186 oprie = op_ALGHSIK 3187 case AADDW: 3188 opri = op_AHI 3189 opril = op_AFI 3190 oprie = op_AHIK 3191 case AMULLW: 3192 opri = op_MHI 3193 opril = op_MSFI 3194 case AMULLD: 3195 opri = op_MGHI 3196 opril = op_MSGFI 3197 } 3198 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3199 switch p.As { 3200 case AADD, AADDC, AMULLD: 3201 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3202 case AADDW, AMULLW: 3203 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3204 } 3205 r = p.To.Reg 3206 } 3207 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v { 3208 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3209 } else if oprie != 0 && int64(int16(v)) == v { 3210 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3211 } else { 3212 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3213 } 3214 3215 case 23: // 64-bit logical op $constant reg 3216 // TODO(mundaym): merge with case 24. 3217 v := c.vregoff(&p.From) 3218 switch p.As { 3219 default: 3220 c.ctxt.Diag("%v is not supported", p) 3221 case AAND: 3222 if v >= 0 { // needs zero extend 3223 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3224 zRRE(op_NGR, uint32(p.To.Reg), regtmp(p), asm) 3225 } else if int64(int16(v)) == v { 3226 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3227 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3228 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3229 } 3230 case AOR: 3231 if int64(uint32(v)) != v { // needs sign extend 3232 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3233 zRRE(op_OGR, uint32(p.To.Reg), regtmp(p), asm) 3234 } else if int64(uint16(v)) == v { 3235 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3236 } else { 3237 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3238 } 3239 case AXOR: 3240 if int64(uint32(v)) != v { // needs sign extend 3241 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3242 zRRE(op_XGR, uint32(p.To.Reg), regtmp(p), asm) 3243 } else { 3244 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3245 } 3246 } 3247 3248 case 24: // 32-bit logical op $constant reg 3249 v := c.vregoff(&p.From) 3250 switch p.As { 3251 case AANDW: 3252 if uint32(v&0xffff0000) == 0xffff0000 { 3253 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3254 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3255 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3256 } else { 3257 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3258 } 3259 case AORW: 3260 if uint32(v&0xffff0000) == 0 { 3261 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3262 } else if uint32(v&0x0000ffff) == 0 { 3263 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3264 } else { 3265 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3266 } 3267 case AXORW: 3268 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3269 } 3270 3271 case 25: // load on condition (register) 3272 m3 := uint32(c.branchMask(p)) 3273 var opcode uint32 3274 switch p.As { 3275 case ALOCR: 3276 opcode = op_LOCR 3277 case ALOCGR: 3278 opcode = op_LOCGR 3279 } 3280 zRRF(opcode, m3, 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3281 3282 case 26: // MOVD $offset(base)(index), reg 3283 v := c.regoff(&p.From) 3284 r := p.From.Reg 3285 if r == 0 { 3286 r = REGSP 3287 } 3288 i := p.From.Index 3289 if v >= 0 && v < DISP12 { 3290 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3291 } else if v >= -DISP20/2 && v < DISP20/2 { 3292 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3293 } else { 3294 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm) 3295 zRX(op_LA, uint32(p.To.Reg), uint32(r), regtmp(p), uint32(i), asm) 3296 } 3297 3298 case 31: // dword 3299 wd := uint64(c.vregoff(&p.From)) 3300 *asm = append(*asm, 3301 uint8(wd>>56), 3302 uint8(wd>>48), 3303 uint8(wd>>40), 3304 uint8(wd>>32), 3305 uint8(wd>>24), 3306 uint8(wd>>16), 3307 uint8(wd>>8), 3308 uint8(wd)) 3309 3310 case 32: // float op freg freg 3311 var opcode uint32 3312 switch p.As { 3313 default: 3314 c.ctxt.Diag("invalid opcode") 3315 case AFADD: 3316 opcode = op_ADBR 3317 case AFADDS: 3318 opcode = op_AEBR 3319 case AFDIV: 3320 opcode = op_DDBR 3321 case AFDIVS: 3322 opcode = op_DEBR 3323 case AFMUL: 3324 opcode = op_MDBR 3325 case AFMULS: 3326 opcode = op_MEEBR 3327 case AFSUB: 3328 opcode = op_SDBR 3329 case AFSUBS: 3330 opcode = op_SEBR 3331 } 3332 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3333 3334 case 33: // float op [freg] freg 3335 r := p.From.Reg 3336 if oclass(&p.From) == C_NONE { 3337 r = p.To.Reg 3338 } 3339 var opcode uint32 3340 switch p.As { 3341 default: 3342 case AFABS: 3343 opcode = op_LPDBR 3344 case AFNABS: 3345 opcode = op_LNDBR 3346 case ALPDFR: 3347 opcode = op_LPDFR 3348 case ALNDFR: 3349 opcode = op_LNDFR 3350 case AFNEG: 3351 opcode = op_LCDFR 3352 case AFNEGS: 3353 opcode = op_LCEBR 3354 case ALEDBR: 3355 opcode = op_LEDBR 3356 case ALDEBR: 3357 opcode = op_LDEBR 3358 case AFSQRT: 3359 opcode = op_SQDBR 3360 case AFSQRTS: 3361 opcode = op_SQEBR 3362 } 3363 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3364 3365 case 34: // float multiply-add freg freg freg 3366 var opcode uint32 3367 switch p.As { 3368 default: 3369 c.ctxt.Diag("invalid opcode") 3370 case AFMADD: 3371 opcode = op_MADBR 3372 case AFMADDS: 3373 opcode = op_MAEBR 3374 case AFMSUB: 3375 opcode = op_MSDBR 3376 case AFMSUBS: 3377 opcode = op_MSEBR 3378 } 3379 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3380 3381 case 35: // mov reg mem (no relocation) 3382 d2 := c.regoff(&p.To) 3383 b2 := p.To.Reg 3384 if b2 == 0 { 3385 b2 = REGSP 3386 } 3387 x2 := p.To.Index 3388 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3389 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3390 if x2 != 0 { 3391 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3392 } 3393 x2 = int16(regtmp(p)) 3394 d2 = 0 3395 } 3396 // Emits an RX instruction if an appropriate one exists and the displacement fits in 12 bits. Otherwise use an RXY instruction. 3397 if op, ok := c.zopstore12(p.As); ok && isU12(d2) { 3398 zRX(op, uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3399 } else { 3400 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3401 } 3402 3403 case 36: // mov mem reg (no relocation) 3404 d2 := c.regoff(&p.From) 3405 b2 := p.From.Reg 3406 if b2 == 0 { 3407 b2 = REGSP 3408 } 3409 x2 := p.From.Index 3410 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3411 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm) 3412 if x2 != 0 { 3413 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm) 3414 } 3415 x2 = int16(regtmp(p)) 3416 d2 = 0 3417 } 3418 // Emits an RX instruction if an appropriate one exists and the displacement fits in 12 bits. Otherwise use an RXY instruction. 3419 if op, ok := c.zopload12(p.As); ok && isU12(d2) { 3420 zRX(op, uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3421 } else { 3422 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3423 } 3424 3425 case 40: // word/byte 3426 wd := uint32(c.regoff(&p.From)) 3427 if p.As == AWORD { //WORD 3428 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3429 } else { //BYTE 3430 *asm = append(*asm, uint8(wd)) 3431 } 3432 3433 case 41: // branch on count 3434 r1 := p.From.Reg 3435 ri2 := (p.Pcond.Pc - p.Pc) >> 1 3436 if int64(int16(ri2)) != ri2 { 3437 c.ctxt.Diag("branch target too far away") 3438 } 3439 var opcode uint32 3440 switch p.As { 3441 case ABRCT: 3442 opcode = op_BRCT 3443 case ABRCTG: 3444 opcode = op_BRCTG 3445 } 3446 zRI(opcode, uint32(r1), uint32(ri2), asm) 3447 3448 case 47: // negate [reg] reg 3449 r := p.From.Reg 3450 if r == 0 { 3451 r = p.To.Reg 3452 } 3453 switch p.As { 3454 case ANEG: 3455 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3456 case ANEGW: 3457 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3458 } 3459 3460 case 48: // floating-point round to integer 3461 m3 := c.vregoff(&p.From) 3462 if 0 > m3 || m3 > 7 { 3463 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3464 } 3465 var opcode uint32 3466 switch p.As { 3467 case AFIEBR: 3468 opcode = op_FIEBR 3469 case AFIDBR: 3470 opcode = op_FIDBR 3471 } 3472 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3473 3474 case 49: // copysign 3475 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3476 3477 case 50: // load and test 3478 var opcode uint32 3479 switch p.As { 3480 case ALTEBR: 3481 opcode = op_LTEBR 3482 case ALTDBR: 3483 opcode = op_LTDBR 3484 } 3485 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3486 3487 case 51: // test data class (immediate only) 3488 var opcode uint32 3489 switch p.As { 3490 case ATCEB: 3491 opcode = op_TCEB 3492 case ATCDB: 3493 opcode = op_TCDB 3494 } 3495 d2 := c.regoff(&p.To) 3496 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm) 3497 3498 case 62: // equivalent of Mul64 in math/bits 3499 zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3500 3501 case 66: 3502 zRR(op_BCR, uint32(Never), 0, asm) 3503 3504 case 67: // fmov $0 freg 3505 var opcode uint32 3506 switch p.As { 3507 case AFMOVS: 3508 opcode = op_LZER 3509 case AFMOVD: 3510 opcode = op_LZDR 3511 } 3512 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3513 3514 case 68: // movw areg reg 3515 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3516 3517 case 69: // movw reg areg 3518 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3519 3520 case 70: // cmp reg reg 3521 if p.As == ACMPW || p.As == ACMPWU { 3522 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3523 } else { 3524 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3525 } 3526 3527 case 71: // cmp reg $constant 3528 v := c.vregoff(&p.To) 3529 switch p.As { 3530 case ACMP, ACMPW: 3531 if int64(int32(v)) != v { 3532 c.ctxt.Diag("%v overflows an int32", v) 3533 } 3534 case ACMPU, ACMPWU: 3535 if int64(uint32(v)) != v { 3536 c.ctxt.Diag("%v overflows a uint32", v) 3537 } 3538 } 3539 if p.As == ACMP && int64(int16(v)) == v { 3540 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3541 } else if p.As == ACMPW && int64(int16(v)) == v { 3542 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3543 } else { 3544 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm) 3545 } 3546 3547 case 72: // mov $constant mem 3548 v := c.regoff(&p.From) 3549 d := c.regoff(&p.To) 3550 r := p.To.Reg 3551 if p.To.Index != 0 { 3552 c.ctxt.Diag("cannot use index register") 3553 } 3554 if r == 0 { 3555 r = REGSP 3556 } 3557 var opcode uint32 3558 switch p.As { 3559 case AMOVD: 3560 opcode = op_MVGHI 3561 case AMOVW, AMOVWZ: 3562 opcode = op_MVHI 3563 case AMOVH, AMOVHZ: 3564 opcode = op_MVHHI 3565 case AMOVB, AMOVBZ: 3566 opcode = op_MVI 3567 } 3568 if d < 0 || d >= DISP12 { 3569 if r == int16(regtmp(p)) { 3570 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r) 3571 } 3572 if d >= -DISP20/2 && d < DISP20/2 { 3573 if opcode == op_MVI { 3574 opcode = op_MVIY 3575 } else { 3576 zRXY(op_LAY, uint32(regtmp(p)), 0, uint32(r), uint32(d), asm) 3577 r = int16(regtmp(p)) 3578 d = 0 3579 } 3580 } else { 3581 zRIL(_a, op_LGFI, regtmp(p), uint32(d), asm) 3582 zRX(op_LA, regtmp(p), regtmp(p), uint32(r), 0, asm) 3583 r = int16(regtmp(p)) 3584 d = 0 3585 } 3586 } 3587 switch opcode { 3588 case op_MVI: 3589 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3590 case op_MVIY: 3591 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm) 3592 default: 3593 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3594 } 3595 3596 case 74: // mov reg addr (including relocation) 3597 i2 := c.regoff(&p.To) 3598 switch p.As { 3599 case AMOVD: 3600 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3601 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3602 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3603 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3604 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3605 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3606 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3607 adj := uint32(0) // adjustment needed for odd addresses 3608 if i2&1 != 0 { 3609 i2 -= 1 3610 adj = 1 3611 } 3612 zRX(op_STC, uint32(p.From.Reg), 0, regtmp(p), adj, asm) 3613 case AFMOVD: 3614 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3615 zRX(op_STD, uint32(p.From.Reg), 0, regtmp(p), 0, asm) 3616 case AFMOVS: 3617 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3618 zRX(op_STE, uint32(p.From.Reg), 0, regtmp(p), 0, asm) 3619 } 3620 c.addrilreloc(p.To.Sym, int64(i2)) 3621 3622 case 75: // mov addr reg (including relocation) 3623 i2 := c.regoff(&p.From) 3624 switch p.As { 3625 case AMOVD: 3626 if i2&1 != 0 { 3627 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3628 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 1, asm) 3629 i2 -= 1 3630 } else { 3631 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3632 } 3633 case AMOVW: 3634 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3635 case AMOVWZ: 3636 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3637 case AMOVH: 3638 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3639 case AMOVHZ: 3640 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3641 case AMOVB, AMOVBZ: 3642 zRIL(_b, op_LARL, regtmp(p), 0, asm) 3643 adj := uint32(0) // adjustment needed for odd addresses 3644 if i2&1 != 0 { 3645 i2 -= 1 3646 adj = 1 3647 } 3648 switch p.As { 3649 case AMOVB: 3650 zRXY(op_LGB, uint32(p.To.Reg), 0, regtmp(p), adj, asm) 3651 case AMOVBZ: 3652 zRXY(op_LLGC, uint32(p.To.Reg), 0, regtmp(p), adj, asm) 3653 } 3654 case AFMOVD: 3655 zRIL(_a, op_LARL, regtmp(p), 0, asm) 3656 zRX(op_LD, uint32(p.To.Reg), 0, regtmp(p), 0, asm) 3657 case AFMOVS: 3658 zRIL(_a, op_LARL, regtmp(p), 0, asm) 3659 zRX(op_LE, uint32(p.To.Reg), 0, regtmp(p), 0, asm) 3660 } 3661 c.addrilreloc(p.From.Sym, int64(i2)) 3662 3663 case 76: // set program mask 3664 zRR(op_SPM, uint32(p.From.Reg), 0, asm) 3665 3666 case 77: // syscall $constant 3667 if p.From.Offset > 255 || p.From.Offset < 1 { 3668 c.ctxt.Diag("illegal system call; system call number out of range: %v", p) 3669 zE(op_TRAP2, asm) // trap always 3670 } else { 3671 zI(op_SVC, uint32(p.From.Offset), asm) 3672 } 3673 3674 case 78: // undef 3675 // "An instruction consisting entirely of binary 0s is guaranteed 3676 // always to be an illegal instruction." 3677 *asm = append(*asm, 0, 0, 0, 0) 3678 3679 case 79: // compare and swap reg reg reg 3680 v := c.regoff(&p.To) 3681 if v < 0 { 3682 v = 0 3683 } 3684 if p.As == ACS { 3685 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3686 } else if p.As == ACSG { 3687 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3688 } 3689 3690 case 80: // sync 3691 zRR(op_BCR, uint32(NotEqual), 0, asm) 3692 3693 case 81: // float to fixed and fixed to float moves (no conversion) 3694 switch p.As { 3695 case ALDGR: 3696 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3697 case ALGDR: 3698 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3699 } 3700 3701 case 82: // fixed to float conversion 3702 var opcode uint32 3703 switch p.As { 3704 default: 3705 log.Fatalf("unexpected opcode %v", p.As) 3706 case ACEFBRA: 3707 opcode = op_CEFBRA 3708 case ACDFBRA: 3709 opcode = op_CDFBRA 3710 case ACEGBRA: 3711 opcode = op_CEGBRA 3712 case ACDGBRA: 3713 opcode = op_CDGBRA 3714 case ACELFBR: 3715 opcode = op_CELFBR 3716 case ACDLFBR: 3717 opcode = op_CDLFBR 3718 case ACELGBR: 3719 opcode = op_CELGBR 3720 case ACDLGBR: 3721 opcode = op_CDLGBR 3722 } 3723 // set immediate operand M3 to 0 to use the default BFP rounding mode 3724 // (usually round to nearest, ties to even) 3725 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3726 // M4 is reserved and must be 0 3727 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3728 3729 case 83: // float to fixed conversion 3730 var opcode uint32 3731 switch p.As { 3732 default: 3733 log.Fatalf("unexpected opcode %v", p.As) 3734 case ACFEBRA: 3735 opcode = op_CFEBRA 3736 case ACFDBRA: 3737 opcode = op_CFDBRA 3738 case ACGEBRA: 3739 opcode = op_CGEBRA 3740 case ACGDBRA: 3741 opcode = op_CGDBRA 3742 case ACLFEBR: 3743 opcode = op_CLFEBR 3744 case ACLFDBR: 3745 opcode = op_CLFDBR 3746 case ACLGEBR: 3747 opcode = op_CLGEBR 3748 case ACLGDBR: 3749 opcode = op_CLGDBR 3750 } 3751 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3752 // M4 is reserved and must be 0 3753 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3754 3755 case 84: // storage-and-storage operations $length mem mem 3756 l := c.regoff(&p.From) 3757 if l < 1 || l > 256 { 3758 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3759 } 3760 if p.GetFrom3().Index != 0 || p.To.Index != 0 { 3761 c.ctxt.Diag("cannot use index reg") 3762 } 3763 b1 := p.To.Reg 3764 b2 := p.GetFrom3().Reg 3765 if b1 == 0 { 3766 b1 = REGSP 3767 } 3768 if b2 == 0 { 3769 b2 = REGSP 3770 } 3771 d1 := c.regoff(&p.To) 3772 d2 := c.regoff(p.GetFrom3()) 3773 if d1 < 0 || d1 >= DISP12 { 3774 if b2 == int16(regtmp(p)) { 3775 c.ctxt.Diag("regtmp(p) conflict") 3776 } 3777 if b1 != int16(regtmp(p)) { 3778 zRRE(op_LGR, regtmp(p), uint32(b1), asm) 3779 } 3780 zRIL(_a, op_AGFI, regtmp(p), uint32(d1), asm) 3781 if d1 == d2 && b1 == b2 { 3782 d2 = 0 3783 b2 = int16(regtmp(p)) 3784 } 3785 d1 = 0 3786 b1 = int16(regtmp(p)) 3787 } 3788 if d2 < 0 || d2 >= DISP12 { 3789 if b1 == REGTMP2 { 3790 c.ctxt.Diag("REGTMP2 conflict") 3791 } 3792 if b2 != REGTMP2 { 3793 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3794 } 3795 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3796 d2 = 0 3797 b2 = REGTMP2 3798 } 3799 var opcode uint32 3800 switch p.As { 3801 default: 3802 c.ctxt.Diag("unexpected opcode %v", p.As) 3803 case AMVC: 3804 opcode = op_MVC 3805 case ACLC: 3806 opcode = op_CLC 3807 // swap operand order for CLC so that it matches CMP 3808 b1, b2 = b2, b1 3809 d1, d2 = d2, d1 3810 case AXC: 3811 opcode = op_XC 3812 case AOC: 3813 opcode = op_OC 3814 case ANC: 3815 opcode = op_NC 3816 } 3817 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3818 3819 case 85: // load address relative long 3820 v := c.regoff(&p.From) 3821 if p.From.Sym == nil { 3822 if (v & 1) != 0 { 3823 c.ctxt.Diag("cannot use LARL with odd offset: %v", v) 3824 } 3825 } else { 3826 c.addrilreloc(p.From.Sym, int64(v)) 3827 v = 0 3828 } 3829 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3830 3831 case 86: // load address 3832 d := c.vregoff(&p.From) 3833 x := p.From.Index 3834 b := p.From.Reg 3835 if b == 0 { 3836 b = REGSP 3837 } 3838 switch p.As { 3839 case ALA: 3840 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3841 case ALAY: 3842 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3843 } 3844 3845 case 87: // execute relative long 3846 v := c.vregoff(&p.From) 3847 if p.From.Sym == nil { 3848 if v&1 != 0 { 3849 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3850 } 3851 } else { 3852 c.addrilreloc(p.From.Sym, v) 3853 v = 0 3854 } 3855 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3856 3857 case 88: // store clock 3858 var opcode uint32 3859 switch p.As { 3860 case ASTCK: 3861 opcode = op_STCK 3862 case ASTCKC: 3863 opcode = op_STCKC 3864 case ASTCKE: 3865 opcode = op_STCKE 3866 case ASTCKF: 3867 opcode = op_STCKF 3868 } 3869 v := c.vregoff(&p.To) 3870 r := p.To.Reg 3871 if r == 0 { 3872 r = REGSP 3873 } 3874 zS(opcode, uint32(r), uint32(v), asm) 3875 3876 case 89: // compare and branch reg reg 3877 var v int32 3878 if p.Pcond != nil { 3879 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3880 } 3881 3882 // Some instructions take a mask as the first argument. 3883 r1, r2 := p.From.Reg, p.Reg 3884 if p.From.Type == obj.TYPE_CONST { 3885 r1, r2 = p.Reg, p.RestArgs[0].Reg 3886 } 3887 m3 := uint32(c.branchMask(p)) 3888 3889 var opcode uint32 3890 switch p.As { 3891 case ACRJ: 3892 // COMPARE AND BRANCH RELATIVE (32) 3893 opcode = op_CRJ 3894 case ACGRJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3895 // COMPARE AND BRANCH RELATIVE (64) 3896 opcode = op_CGRJ 3897 case ACLRJ: 3898 // COMPARE LOGICAL AND BRANCH RELATIVE (32) 3899 opcode = op_CLRJ 3900 case ACLGRJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3901 // COMPARE LOGICAL AND BRANCH RELATIVE (64) 3902 opcode = op_CLGRJ 3903 } 3904 3905 if int32(int16(v)) != v { 3906 // The branch is too far for one instruction so crack 3907 // `CMPBEQ x, y, target` into: 3908 // 3909 // CMPBNE x, y, 2(PC) 3910 // BR target 3911 // 3912 // Note that the instruction sequence MUST NOT clobber 3913 // the condition code. 3914 m3 ^= 0xe // invert 3-bit mask 3915 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(sizeRIE+sizeRIL)/2, 0, 0, m3, 0, asm) 3916 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm) 3917 } else { 3918 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(v), 0, 0, m3, 0, asm) 3919 } 3920 3921 case 90: // compare and branch reg $constant 3922 var v int32 3923 if p.Pcond != nil { 3924 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3925 } 3926 3927 // Some instructions take a mask as the first argument. 3928 r1, i2 := p.From.Reg, p.RestArgs[0].Offset 3929 if p.From.Type == obj.TYPE_CONST { 3930 r1 = p.Reg 3931 } 3932 m3 := uint32(c.branchMask(p)) 3933 3934 var opcode uint32 3935 switch p.As { 3936 case ACIJ: 3937 opcode = op_CIJ 3938 case ACGIJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3939 opcode = op_CGIJ 3940 case ACLIJ: 3941 opcode = op_CLIJ 3942 case ACLGIJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3943 opcode = op_CLGIJ 3944 } 3945 if int32(int16(v)) != v { 3946 // The branch is too far for one instruction so crack 3947 // `CMPBEQ x, $0, target` into: 3948 // 3949 // CMPBNE x, $0, 2(PC) 3950 // BR target 3951 // 3952 // Note that the instruction sequence MUST NOT clobber 3953 // the condition code. 3954 m3 ^= 0xe // invert 3-bit mask 3955 zRIE(_c, opcode, uint32(r1), m3, uint32(sizeRIE+sizeRIL)/2, 0, 0, 0, uint32(i2), asm) 3956 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm) 3957 } else { 3958 zRIE(_c, opcode, uint32(r1), m3, uint32(v), 0, 0, 0, uint32(i2), asm) 3959 } 3960 3961 case 91: // test under mask (immediate) 3962 var opcode uint32 3963 switch p.As { 3964 case ATMHH: 3965 opcode = op_TMHH 3966 case ATMHL: 3967 opcode = op_TMHL 3968 case ATMLH: 3969 opcode = op_TMLH 3970 case ATMLL: 3971 opcode = op_TMLL 3972 } 3973 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm) 3974 3975 case 92: // insert program mask 3976 zRRE(op_IPM, uint32(p.From.Reg), 0, asm) 3977 3978 case 93: // GOT lookup 3979 v := c.vregoff(&p.To) 3980 if v != 0 { 3981 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3982 } 3983 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3984 rel := obj.Addrel(c.cursym) 3985 rel.Off = int32(c.pc + 2) 3986 rel.Siz = 4 3987 rel.Sym = p.From.Sym 3988 rel.Type = objabi.R_GOTPCREL 3989 rel.Add = 2 + int64(rel.Siz) 3990 3991 case 94: // TLS local exec model 3992 zRIL(_b, op_LARL, regtmp(p), (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3993 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 0, asm) 3994 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3995 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3996 rel := obj.Addrel(c.cursym) 3997 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI) 3998 rel.Siz = 8 3999 rel.Sym = p.From.Sym 4000 rel.Type = objabi.R_TLS_LE 4001 rel.Add = 0 4002 4003 case 95: // TLS initial exec model 4004 // Assembly | Relocation symbol | Done Here? 4005 // -------------------------------------------------------------- 4006 // ear %r11, %a0 | | 4007 // sllg %r11, %r11, 32 | | 4008 // ear %r11, %a1 | | 4009 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 4010 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 4011 // la %r10, 0(%r10, %r11) | | 4012 // -------------------------------------------------------------- 4013 4014 // R_390_TLS_IEENT 4015 zRIL(_b, op_LARL, regtmp(p), 0, asm) 4016 ieent := obj.Addrel(c.cursym) 4017 ieent.Off = int32(c.pc + 2) 4018 ieent.Siz = 4 4019 ieent.Sym = p.From.Sym 4020 ieent.Type = objabi.R_TLS_IE 4021 ieent.Add = 2 + int64(ieent.Siz) 4022 4023 // R_390_TLS_LOAD 4024 zRXY(op_LGF, uint32(p.To.Reg), regtmp(p), 0, 0, asm) 4025 // TODO(mundaym): add R_390_TLS_LOAD relocation here 4026 // not strictly required but might allow the linker to optimize 4027 4028 case 96: // clear macro 4029 length := c.vregoff(&p.From) 4030 offset := c.vregoff(&p.To) 4031 reg := p.To.Reg 4032 if reg == 0 { 4033 reg = REGSP 4034 } 4035 if length <= 0 { 4036 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 4037 } 4038 for length > 0 { 4039 if offset < 0 || offset >= DISP12 { 4040 if offset >= -DISP20/2 && offset < DISP20/2 { 4041 zRXY(op_LAY, regtmp(p), uint32(reg), 0, uint32(offset), asm) 4042 } else { 4043 if reg != int16(regtmp(p)) { 4044 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4045 } 4046 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4047 } 4048 reg = int16(regtmp(p)) 4049 offset = 0 4050 } 4051 size := length 4052 if size > 256 { 4053 size = 256 4054 } 4055 4056 switch size { 4057 case 1: 4058 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 4059 case 2: 4060 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 4061 case 4: 4062 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 4063 case 8: 4064 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 4065 default: 4066 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 4067 } 4068 4069 length -= size 4070 offset += size 4071 } 4072 4073 case 97: // store multiple 4074 rstart := p.From.Reg 4075 rend := p.Reg 4076 offset := c.regoff(&p.To) 4077 reg := p.To.Reg 4078 if reg == 0 { 4079 reg = REGSP 4080 } 4081 if offset < -DISP20/2 || offset >= DISP20/2 { 4082 if reg != int16(regtmp(p)) { 4083 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4084 } 4085 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4086 reg = int16(regtmp(p)) 4087 offset = 0 4088 } 4089 switch p.As { 4090 case ASTMY: 4091 if offset >= 0 && offset < DISP12 { 4092 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4093 } else { 4094 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4095 } 4096 case ASTMG: 4097 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4098 } 4099 4100 case 98: // load multiple 4101 rstart := p.Reg 4102 rend := p.To.Reg 4103 offset := c.regoff(&p.From) 4104 reg := p.From.Reg 4105 if reg == 0 { 4106 reg = REGSP 4107 } 4108 if offset < -DISP20/2 || offset >= DISP20/2 { 4109 if reg != int16(regtmp(p)) { 4110 zRRE(op_LGR, regtmp(p), uint32(reg), asm) 4111 } 4112 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm) 4113 reg = int16(regtmp(p)) 4114 offset = 0 4115 } 4116 switch p.As { 4117 case ALMY: 4118 if offset >= 0 && offset < DISP12 { 4119 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4120 } else { 4121 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4122 } 4123 case ALMG: 4124 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 4125 } 4126 4127 case 99: // interlocked load and op 4128 if p.To.Index != 0 { 4129 c.ctxt.Diag("cannot use indexed address") 4130 } 4131 offset := c.regoff(&p.To) 4132 if offset < -DISP20/2 || offset >= DISP20/2 { 4133 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 4134 } 4135 var opcode uint32 4136 switch p.As { 4137 case ALAA: 4138 opcode = op_LAA 4139 case ALAAG: 4140 opcode = op_LAAG 4141 case ALAAL: 4142 opcode = op_LAAL 4143 case ALAALG: 4144 opcode = op_LAALG 4145 case ALAN: 4146 opcode = op_LAN 4147 case ALANG: 4148 opcode = op_LANG 4149 case ALAX: 4150 opcode = op_LAX 4151 case ALAXG: 4152 opcode = op_LAXG 4153 case ALAO: 4154 opcode = op_LAO 4155 case ALAOG: 4156 opcode = op_LAOG 4157 } 4158 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 4159 4160 case 100: // VRX STORE 4161 op, m3, _ := vop(p.As) 4162 v1 := p.From.Reg 4163 if p.Reg != 0 { 4164 m3 = uint32(c.vregoff(&p.From)) 4165 v1 = p.Reg 4166 } 4167 b2 := p.To.Reg 4168 if b2 == 0 { 4169 b2 = REGSP 4170 } 4171 d2 := uint32(c.vregoff(&p.To)) 4172 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm) 4173 4174 case 101: // VRX LOAD 4175 op, m3, _ := vop(p.As) 4176 src := &p.From 4177 if p.GetFrom3() != nil { 4178 m3 = uint32(c.vregoff(&p.From)) 4179 src = p.GetFrom3() 4180 } 4181 b2 := src.Reg 4182 if b2 == 0 { 4183 b2 = REGSP 4184 } 4185 d2 := uint32(c.vregoff(src)) 4186 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm) 4187 4188 case 102: // VRV SCATTER 4189 op, _, _ := vop(p.As) 4190 m3 := uint32(c.vregoff(&p.From)) 4191 b2 := p.To.Reg 4192 if b2 == 0 { 4193 b2 = REGSP 4194 } 4195 d2 := uint32(c.vregoff(&p.To)) 4196 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 4197 4198 case 103: // VRV GATHER 4199 op, _, _ := vop(p.As) 4200 m3 := uint32(c.vregoff(&p.From)) 4201 b2 := p.GetFrom3().Reg 4202 if b2 == 0 { 4203 b2 = REGSP 4204 } 4205 d2 := uint32(c.vregoff(p.GetFrom3())) 4206 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm) 4207 4208 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 4209 op, m4, _ := vop(p.As) 4210 fr := p.Reg 4211 if fr == 0 { 4212 fr = p.To.Reg 4213 } 4214 bits := uint32(c.vregoff(&p.From)) 4215 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 4216 4217 case 105: // VRS STORE MULTIPLE 4218 op, _, _ := vop(p.As) 4219 offset := uint32(c.vregoff(&p.To)) 4220 reg := p.To.Reg 4221 if reg == 0 { 4222 reg = REGSP 4223 } 4224 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 4225 4226 case 106: // VRS LOAD MULTIPLE 4227 op, _, _ := vop(p.As) 4228 offset := uint32(c.vregoff(&p.From)) 4229 reg := p.From.Reg 4230 if reg == 0 { 4231 reg = REGSP 4232 } 4233 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 4234 4235 case 107: // VRS STORE WITH LENGTH 4236 op, _, _ := vop(p.As) 4237 offset := uint32(c.vregoff(&p.To)) 4238 reg := p.To.Reg 4239 if reg == 0 { 4240 reg = REGSP 4241 } 4242 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4243 4244 case 108: // VRS LOAD WITH LENGTH 4245 op, _, _ := vop(p.As) 4246 offset := uint32(c.vregoff(p.GetFrom3())) 4247 reg := p.GetFrom3().Reg 4248 if reg == 0 { 4249 reg = REGSP 4250 } 4251 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 4252 4253 case 109: // VRI-a 4254 op, m3, _ := vop(p.As) 4255 i2 := uint32(c.vregoff(&p.From)) 4256 if p.GetFrom3() != nil { 4257 m3 = uint32(c.vregoff(&p.From)) 4258 i2 = uint32(c.vregoff(p.GetFrom3())) 4259 } 4260 switch p.As { 4261 case AVZERO: 4262 i2 = 0 4263 case AVONE: 4264 i2 = 0xffff 4265 } 4266 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 4267 4268 case 110: 4269 op, m4, _ := vop(p.As) 4270 i2 := uint32(c.vregoff(&p.From)) 4271 i3 := uint32(c.vregoff(p.GetFrom3())) 4272 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 4273 4274 case 111: 4275 op, m4, _ := vop(p.As) 4276 i2 := uint32(c.vregoff(&p.From)) 4277 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 4278 4279 case 112: 4280 op, m5, _ := vop(p.As) 4281 i4 := uint32(c.vregoff(&p.From)) 4282 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm) 4283 4284 case 113: 4285 op, m4, _ := vop(p.As) 4286 m5 := singleElementMask(p.As) 4287 i3 := uint32(c.vregoff(&p.From)) 4288 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 4289 4290 case 114: // VRR-a 4291 op, m3, m5 := vop(p.As) 4292 m4 := singleElementMask(p.As) 4293 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4294 4295 case 115: // VRR-a COMPARE 4296 op, m3, m5 := vop(p.As) 4297 m4 := singleElementMask(p.As) 4298 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4299 4300 case 117: // VRR-b 4301 op, m4, m5 := vop(p.As) 4302 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4303 4304 case 118: // VRR-c 4305 op, m4, m6 := vop(p.As) 4306 m5 := singleElementMask(p.As) 4307 v3 := p.Reg 4308 if v3 == 0 { 4309 v3 = p.To.Reg 4310 } 4311 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4312 4313 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4314 op, m4, m6 := vop(p.As) 4315 m5 := singleElementMask(p.As) 4316 v2 := p.Reg 4317 if v2 == 0 { 4318 v2 = p.To.Reg 4319 } 4320 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4321 4322 case 120: // VRR-d 4323 op, m6, _ := vop(p.As) 4324 m5 := singleElementMask(p.As) 4325 v1 := uint32(p.To.Reg) 4326 v2 := uint32(p.From.Reg) 4327 v3 := uint32(p.Reg) 4328 v4 := uint32(p.GetFrom3().Reg) 4329 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4330 4331 case 121: // VRR-e 4332 op, m6, _ := vop(p.As) 4333 m5 := singleElementMask(p.As) 4334 v1 := uint32(p.To.Reg) 4335 v2 := uint32(p.From.Reg) 4336 v3 := uint32(p.Reg) 4337 v4 := uint32(p.GetFrom3().Reg) 4338 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4339 4340 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4341 op, _, _ := vop(p.As) 4342 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4343 4344 case 123: // VPDI $m4, V2, V3, V1 4345 op, _, _ := vop(p.As) 4346 m4 := c.regoff(&p.From) 4347 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm) 4348 } 4349} 4350 4351func (c *ctxtz) vregoff(a *obj.Addr) int64 { 4352 c.instoffset = 0 4353 if a != nil { 4354 c.aclass(a) 4355 } 4356 return c.instoffset 4357} 4358 4359func (c *ctxtz) regoff(a *obj.Addr) int32 { 4360 return int32(c.vregoff(a)) 4361} 4362 4363// find if the displacement is within 12 bit 4364func isU12(displacement int32) bool { 4365 return displacement >= 0 && displacement < DISP12 4366} 4367 4368// zopload12 returns the RX op with 12 bit displacement for the given load 4369func (c *ctxtz) zopload12(a obj.As) (uint32, bool) { 4370 switch a { 4371 case AFMOVD: 4372 return op_LD, true 4373 case AFMOVS: 4374 return op_LE, true 4375 } 4376 return 0, false 4377} 4378 4379// zopload returns the RXY op for the given load 4380func (c *ctxtz) zopload(a obj.As) uint32 { 4381 switch a { 4382 // fixed point load 4383 case AMOVD: 4384 return op_LG 4385 case AMOVW: 4386 return op_LGF 4387 case AMOVWZ: 4388 return op_LLGF 4389 case AMOVH: 4390 return op_LGH 4391 case AMOVHZ: 4392 return op_LLGH 4393 case AMOVB: 4394 return op_LGB 4395 case AMOVBZ: 4396 return op_LLGC 4397 4398 // floating point load 4399 case AFMOVD: 4400 return op_LDY 4401 case AFMOVS: 4402 return op_LEY 4403 4404 // byte reversed load 4405 case AMOVDBR: 4406 return op_LRVG 4407 case AMOVWBR: 4408 return op_LRV 4409 case AMOVHBR: 4410 return op_LRVH 4411 } 4412 4413 c.ctxt.Diag("unknown store opcode %v", a) 4414 return 0 4415} 4416 4417// zopstore12 returns the RX op with 12 bit displacement for the given store 4418func (c *ctxtz) zopstore12(a obj.As) (uint32, bool) { 4419 switch a { 4420 case AFMOVD: 4421 return op_STD, true 4422 case AFMOVS: 4423 return op_STE, true 4424 case AMOVW, AMOVWZ: 4425 return op_ST, true 4426 case AMOVH, AMOVHZ: 4427 return op_STH, true 4428 case AMOVB, AMOVBZ: 4429 return op_STC, true 4430 } 4431 return 0, false 4432} 4433 4434// zopstore returns the RXY op for the given store 4435func (c *ctxtz) zopstore(a obj.As) uint32 { 4436 switch a { 4437 // fixed point store 4438 case AMOVD: 4439 return op_STG 4440 case AMOVW, AMOVWZ: 4441 return op_STY 4442 case AMOVH, AMOVHZ: 4443 return op_STHY 4444 case AMOVB, AMOVBZ: 4445 return op_STCY 4446 4447 // floating point store 4448 case AFMOVD: 4449 return op_STDY 4450 case AFMOVS: 4451 return op_STEY 4452 4453 // byte reversed store 4454 case AMOVDBR: 4455 return op_STRVG 4456 case AMOVWBR: 4457 return op_STRV 4458 case AMOVHBR: 4459 return op_STRVH 4460 } 4461 4462 c.ctxt.Diag("unknown store opcode %v", a) 4463 return 0 4464} 4465 4466// zoprre returns the RRE op for the given a 4467func (c *ctxtz) zoprre(a obj.As) uint32 { 4468 switch a { 4469 case ACMP: 4470 return op_CGR 4471 case ACMPU: 4472 return op_CLGR 4473 case AFCMPO: //ordered 4474 return op_KDBR 4475 case AFCMPU: //unordered 4476 return op_CDBR 4477 case ACEBR: 4478 return op_CEBR 4479 } 4480 c.ctxt.Diag("unknown rre opcode %v", a) 4481 return 0 4482} 4483 4484// zoprr returns the RR op for the given a 4485func (c *ctxtz) zoprr(a obj.As) uint32 { 4486 switch a { 4487 case ACMPW: 4488 return op_CR 4489 case ACMPWU: 4490 return op_CLR 4491 } 4492 c.ctxt.Diag("unknown rr opcode %v", a) 4493 return 0 4494} 4495 4496// zopril returns the RIL op for the given a 4497func (c *ctxtz) zopril(a obj.As) uint32 { 4498 switch a { 4499 case ACMP: 4500 return op_CGFI 4501 case ACMPU: 4502 return op_CLGFI 4503 case ACMPW: 4504 return op_CFI 4505 case ACMPWU: 4506 return op_CLFI 4507 } 4508 c.ctxt.Diag("unknown ril opcode %v", a) 4509 return 0 4510} 4511 4512// z instructions sizes 4513const ( 4514 sizeE = 2 4515 sizeI = 2 4516 sizeIE = 4 4517 sizeMII = 6 4518 sizeRI = 4 4519 sizeRI1 = 4 4520 sizeRI2 = 4 4521 sizeRI3 = 4 4522 sizeRIE = 6 4523 sizeRIE1 = 6 4524 sizeRIE2 = 6 4525 sizeRIE3 = 6 4526 sizeRIE4 = 6 4527 sizeRIE5 = 6 4528 sizeRIE6 = 6 4529 sizeRIL = 6 4530 sizeRIL1 = 6 4531 sizeRIL2 = 6 4532 sizeRIL3 = 6 4533 sizeRIS = 6 4534 sizeRR = 2 4535 sizeRRD = 4 4536 sizeRRE = 4 4537 sizeRRF = 4 4538 sizeRRF1 = 4 4539 sizeRRF2 = 4 4540 sizeRRF3 = 4 4541 sizeRRF4 = 4 4542 sizeRRF5 = 4 4543 sizeRRR = 2 4544 sizeRRS = 6 4545 sizeRS = 4 4546 sizeRS1 = 4 4547 sizeRS2 = 4 4548 sizeRSI = 4 4549 sizeRSL = 6 4550 sizeRSY = 6 4551 sizeRSY1 = 6 4552 sizeRSY2 = 6 4553 sizeRX = 4 4554 sizeRX1 = 4 4555 sizeRX2 = 4 4556 sizeRXE = 6 4557 sizeRXF = 6 4558 sizeRXY = 6 4559 sizeRXY1 = 6 4560 sizeRXY2 = 6 4561 sizeS = 4 4562 sizeSI = 4 4563 sizeSIL = 6 4564 sizeSIY = 6 4565 sizeSMI = 6 4566 sizeSS = 6 4567 sizeSS1 = 6 4568 sizeSS2 = 6 4569 sizeSS3 = 6 4570 sizeSS4 = 6 4571 sizeSS5 = 6 4572 sizeSS6 = 6 4573 sizeSSE = 6 4574 sizeSSF = 6 4575) 4576 4577// instruction format variations 4578type form int 4579 4580const ( 4581 _a form = iota 4582 _b 4583 _c 4584 _d 4585 _e 4586 _f 4587) 4588 4589func zE(op uint32, asm *[]byte) { 4590 *asm = append(*asm, uint8(op>>8), uint8(op)) 4591} 4592 4593func zI(op, i1 uint32, asm *[]byte) { 4594 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4595} 4596 4597func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4598 *asm = append(*asm, 4599 uint8(op>>8), 4600 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4601 uint8(ri2), 4602 uint8(ri3>>16), 4603 uint8(ri3>>8), 4604 uint8(ri3)) 4605} 4606 4607func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4608 *asm = append(*asm, 4609 uint8(op>>8), 4610 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4611 uint8(i2_ri2>>8), 4612 uint8(i2_ri2)) 4613} 4614 4615// Expected argument values for the instruction formats. 4616// 4617// Format a1 a2 a3 a4 a5 a6 a7 4618// ------------------------------------ 4619// a r1, 0, i2, 0, 0, m3, 0 4620// b r1, r2, ri4, 0, 0, m3, 0 4621// c r1, m3, ri4, 0, 0, 0, i2 4622// d r1, r3, i2, 0, 0, 0, 0 4623// e r1, r3, ri2, 0, 0, 0, 0 4624// f r1, r2, 0, i3, i4, 0, i5 4625// g r1, m3, i2, 0, 0, 0, 0 4626func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4627 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4628 4629 switch f { 4630 default: 4631 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4632 case _f: 4633 *asm = append(*asm, uint8(i3), uint8(i4)) 4634 } 4635 4636 switch f { 4637 case _a, _b: 4638 *asm = append(*asm, uint8(m3)<<4) 4639 default: 4640 *asm = append(*asm, uint8(i2_i5)) 4641 } 4642 4643 *asm = append(*asm, uint8(op)) 4644} 4645 4646func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4647 if f == _a || f == _b { 4648 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4649 } 4650 *asm = append(*asm, 4651 uint8(op>>8), 4652 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4653 uint8(i2_ri2>>24), 4654 uint8(i2_ri2>>16), 4655 uint8(i2_ri2>>8), 4656 uint8(i2_ri2)) 4657} 4658 4659func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4660 *asm = append(*asm, 4661 uint8(op>>8), 4662 (uint8(r1)<<4)|uint8(m3&0x0F), 4663 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4664 uint8(d4), 4665 uint8(i2), 4666 uint8(op)) 4667} 4668 4669func zRR(op, r1, r2 uint32, asm *[]byte) { 4670 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4671} 4672 4673func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4674 *asm = append(*asm, 4675 uint8(op>>8), 4676 uint8(op), 4677 uint8(r1)<<4, 4678 (uint8(r3)<<4)|uint8(r2&0x0F)) 4679} 4680 4681func zRRE(op, r1, r2 uint32, asm *[]byte) { 4682 *asm = append(*asm, 4683 uint8(op>>8), 4684 uint8(op), 4685 0, 4686 (uint8(r1)<<4)|uint8(r2&0x0F)) 4687} 4688 4689func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4690 *asm = append(*asm, 4691 uint8(op>>8), 4692 uint8(op), 4693 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4694 (uint8(r1)<<4)|uint8(r2&0x0F)) 4695} 4696 4697func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4698 *asm = append(*asm, 4699 uint8(op>>8), 4700 (uint8(r1)<<4)|uint8(r2&0x0F), 4701 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4702 uint8(d4), 4703 uint8(m3)<<4, 4704 uint8(op)) 4705} 4706 4707func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4708 *asm = append(*asm, 4709 uint8(op>>8), 4710 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4711 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4712 uint8(d2)) 4713} 4714 4715func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4716 *asm = append(*asm, 4717 uint8(op>>8), 4718 (uint8(r1)<<4)|uint8(r3&0x0F), 4719 uint8(ri2>>8), 4720 uint8(ri2)) 4721} 4722 4723func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4724 *asm = append(*asm, 4725 uint8(op>>8), 4726 uint8(l1), 4727 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4728 uint8(d2), 4729 uint8(op)) 4730} 4731 4732func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4733 dl2 := uint16(d2) & 0x0FFF 4734 *asm = append(*asm, 4735 uint8(op>>8), 4736 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4737 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4738 uint8(dl2), 4739 uint8(d2>>12), 4740 uint8(op)) 4741} 4742 4743func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4744 *asm = append(*asm, 4745 uint8(op>>8), 4746 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4747 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4748 uint8(d2)) 4749} 4750 4751func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4752 *asm = append(*asm, 4753 uint8(op>>8), 4754 (uint8(r1)<<4)|uint8(x2&0x0F), 4755 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4756 uint8(d2), 4757 uint8(m3)<<4, 4758 uint8(op)) 4759} 4760 4761func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4762 *asm = append(*asm, 4763 uint8(op>>8), 4764 (uint8(r3)<<4)|uint8(x2&0x0F), 4765 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4766 uint8(d2), 4767 uint8(m1)<<4, 4768 uint8(op)) 4769} 4770 4771func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4772 dl2 := uint16(d2) & 0x0FFF 4773 *asm = append(*asm, 4774 uint8(op>>8), 4775 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4776 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4777 uint8(dl2), 4778 uint8(d2>>12), 4779 uint8(op)) 4780} 4781 4782func zS(op, b2, d2 uint32, asm *[]byte) { 4783 *asm = append(*asm, 4784 uint8(op>>8), 4785 uint8(op), 4786 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4787 uint8(d2)) 4788} 4789 4790func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4791 *asm = append(*asm, 4792 uint8(op>>8), 4793 uint8(i2), 4794 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4795 uint8(d1)) 4796} 4797 4798func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4799 *asm = append(*asm, 4800 uint8(op>>8), 4801 uint8(op), 4802 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4803 uint8(d1), 4804 uint8(i2>>8), 4805 uint8(i2)) 4806} 4807 4808func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4809 dl1 := uint16(d1) & 0x0FFF 4810 *asm = append(*asm, 4811 uint8(op>>8), 4812 uint8(i2), 4813 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4814 uint8(dl1), 4815 uint8(d1>>12), 4816 uint8(op)) 4817} 4818 4819func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4820 *asm = append(*asm, 4821 uint8(op>>8), 4822 uint8(m1)<<4, 4823 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4824 uint8(d3), 4825 uint8(ri2>>8), 4826 uint8(ri2)) 4827} 4828 4829// Expected argument values for the instruction formats. 4830// 4831// Format a1 a2 a3 a4 a5 a6 4832// ------------------------------- 4833// a l1, 0, b1, d1, b2, d2 4834// b l1, l2, b1, d1, b2, d2 4835// c l1, i3, b1, d1, b2, d2 4836// d r1, r3, b1, d1, b2, d2 4837// e r1, r3, b2, d2, b4, d4 4838// f 0, l2, b1, d1, b2, d2 4839func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4840 *asm = append(*asm, uint8(op>>8)) 4841 4842 switch f { 4843 case _a: 4844 *asm = append(*asm, uint8(l1_r1)) 4845 case _b, _c, _d, _e: 4846 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4847 case _f: 4848 *asm = append(*asm, uint8(l2_i3_r3)) 4849 } 4850 4851 *asm = append(*asm, 4852 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4853 uint8(d1_d2), 4854 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4855 uint8(d2_d4)) 4856} 4857 4858func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4859 *asm = append(*asm, 4860 uint8(op>>8), 4861 uint8(op), 4862 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4863 uint8(d1), 4864 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4865 uint8(d2)) 4866} 4867 4868func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4869 *asm = append(*asm, 4870 uint8(op>>8), 4871 (uint8(r3)<<4)|(uint8(op)&0x0F), 4872 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4873 uint8(d1), 4874 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4875 uint8(d2)) 4876} 4877 4878func rxb(va, vb, vc, vd uint32) uint8 { 4879 mask := uint8(0) 4880 if va >= REG_V16 && va <= REG_V31 { 4881 mask |= 0x8 4882 } 4883 if vb >= REG_V16 && vb <= REG_V31 { 4884 mask |= 0x4 4885 } 4886 if vc >= REG_V16 && vc <= REG_V31 { 4887 mask |= 0x2 4888 } 4889 if vd >= REG_V16 && vd <= REG_V31 { 4890 mask |= 0x1 4891 } 4892 return mask 4893} 4894 4895func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4896 *asm = append(*asm, 4897 uint8(op>>8), 4898 (uint8(v1)<<4)|(uint8(x2)&0xf), 4899 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4900 uint8(d2), 4901 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4902 uint8(op)) 4903} 4904 4905func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4906 *asm = append(*asm, 4907 uint8(op>>8), 4908 (uint8(v1)<<4)|(uint8(v2)&0xf), 4909 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4910 uint8(d2), 4911 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4912 uint8(op)) 4913} 4914 4915func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4916 *asm = append(*asm, 4917 uint8(op>>8), 4918 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4919 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4920 uint8(d2), 4921 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4922 uint8(op)) 4923} 4924 4925func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4926 *asm = append(*asm, 4927 uint8(op>>8), 4928 (uint8(v1)<<4)|(uint8(v2)&0xf), 4929 0, 4930 (uint8(m5)<<4)|(uint8(m4)&0xf), 4931 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4932 uint8(op)) 4933} 4934 4935func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4936 *asm = append(*asm, 4937 uint8(op>>8), 4938 (uint8(v1)<<4)|(uint8(v2)&0xf), 4939 uint8(v3)<<4, 4940 uint8(m5)<<4, 4941 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4942 uint8(op)) 4943} 4944 4945func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4946 *asm = append(*asm, 4947 uint8(op>>8), 4948 (uint8(v1)<<4)|(uint8(v2)&0xf), 4949 uint8(v3)<<4, 4950 (uint8(m6)<<4)|(uint8(m5)&0xf), 4951 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4952 uint8(op)) 4953} 4954 4955func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4956 *asm = append(*asm, 4957 uint8(op>>8), 4958 (uint8(v1)<<4)|(uint8(v2)&0xf), 4959 (uint8(v3)<<4)|(uint8(m5)&0xf), 4960 uint8(m6)<<4, 4961 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4962 uint8(op)) 4963} 4964 4965func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4966 *asm = append(*asm, 4967 uint8(op>>8), 4968 (uint8(v1)<<4)|(uint8(v2)&0xf), 4969 (uint8(v3)<<4)|(uint8(m6)&0xf), 4970 uint8(m5), 4971 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4972 uint8(op)) 4973} 4974 4975func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4976 *asm = append(*asm, 4977 uint8(op>>8), 4978 (uint8(v1)<<4)|(uint8(r2)&0xf), 4979 uint8(r3)<<4, 4980 0, 4981 rxb(v1, 0, 0, 0), 4982 uint8(op)) 4983} 4984 4985func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4986 *asm = append(*asm, 4987 uint8(op>>8), 4988 uint8(v1)<<4, 4989 uint8(i2>>8), 4990 uint8(i2), 4991 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4992 uint8(op)) 4993} 4994 4995func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4996 *asm = append(*asm, 4997 uint8(op>>8), 4998 uint8(v1)<<4, 4999 uint8(i2), 5000 uint8(i3), 5001 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 5002 uint8(op)) 5003} 5004 5005func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 5006 *asm = append(*asm, 5007 uint8(op>>8), 5008 (uint8(v1)<<4)|(uint8(v3)&0xf), 5009 uint8(i2>>8), 5010 uint8(i2), 5011 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 5012 uint8(op)) 5013} 5014 5015func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 5016 *asm = append(*asm, 5017 uint8(op>>8), 5018 (uint8(v1)<<4)|(uint8(v2)&0xf), 5019 uint8(v3)<<4, 5020 uint8(i4), 5021 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 5022 uint8(op)) 5023} 5024 5025func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 5026 *asm = append(*asm, 5027 uint8(op>>8), 5028 (uint8(v1)<<4)|(uint8(v2)&0xf), 5029 uint8(i3>>4), 5030 (uint8(i3)<<4)|(uint8(m5)&0xf), 5031 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 5032 uint8(op)) 5033} 5034