1 /* 2 * Copyright (C) 2018-2021 Intel Corporation 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 */ 7 8 #pragma once 9 #include "CL/cl.h" 10 11 /********************************** 12 * Internal only queue properties * 13 **********************************/ 14 // Intel evaluation now. Remove it after approval for public release 15 #define CL_DEVICE_DRIVER_VERSION_INTEL 0x10010 16 17 #define CL_DEVICE_DRIVER_VERSION_INTEL_NEO1 0x454E4831 // Driver version is ENH1 18 19 /********************************************* 20 * Internal only kernel exec info properties * 21 *********************************************/ 22 23 #define CL_KERNEL_EXEC_INFO_KERNEL_TYPE_INTEL 0x1000C 24 #define CL_KERNEL_EXEC_INFO_DEFAULT_TYPE_INTEL 0x1000D 25 #define CL_KERNEL_EXEC_INFO_CONCURRENT_TYPE_INTEL 0x1000E 26 27 /********************************* 28 * cl_intel_debug_info extension * 29 *********************************/ 30 #define cl_intel_debug_info 1 31 32 // New queries for clGetProgramInfo: 33 #define CL_PROGRAM_DEBUG_INFO_INTEL 0x4100 34 #define CL_PROGRAM_DEBUG_INFO_SIZES_INTEL 0x4101 35 36 // New queries for clGetKernelInfo: 37 #define CL_KERNEL_BINARY_PROGRAM_INTEL 0x407D 38 #define CL_KERNEL_BINARIES_INTEL 0x4102 39 #define CL_KERNEL_BINARY_SIZES_INTEL 0x4103 40 #define CL_KERNEL_BINARY_GPU_ADDRESS_INTEL 0x10010 41 42 /******************************************** 43 * event properties for performance counter * 44 ********************************************/ 45 /* performance counter */ 46 #define CL_PROFILING_COMMAND_PERFCOUNTERS_INTEL 0x407F 47 48 /************************** 49 * Internal only cl types * 50 **************************/ 51 52 using cl_execution_info_kernel_type_intel = cl_uint; 53 using cl_mem_alloc_flags_intel = cl_bitfield; 54 using cl_mem_properties_intel = cl_bitfield; 55 using cl_mem_flags_intel = cl_mem_flags; 56 using cl_mem_info_intel = cl_uint; 57 using cl_mem_advice_intel = cl_uint; 58 using cl_unified_shared_memory_type_intel = cl_uint; 59 using cl_unified_shared_memory_capabilities_intel = cl_bitfield; 60 61 /****************************** 62 * Internal only cl_mem_flags * 63 ******************************/ 64 65 #define CL_MEM_FLAGS_INTEL 0x10001 66 #define CL_MEM_LOCALLY_UNCACHED_RESOURCE (1 << 18) 67 #define CL_MEM_LOCALLY_UNCACHED_SURFACE_STATE_RESOURCE (1 << 25) 68 #define CL_MEM_48BIT_RESOURCE_INTEL (1 << 26) 69 70 // Used with clEnqueueVerifyMemory 71 #define CL_MEM_COMPARE_EQUAL 0u 72 #define CL_MEM_COMPARE_NOT_EQUAL 1u 73 74 #define CL_MEM_FORCE_LINEAR_STORAGE_INTEL (1 << 19) 75 #define CL_MEM_FORCE_HOST_MEMORY_INTEL (1 << 20) 76 77 #define CL_MEM_ALLOCATION_HANDLE_INTEL 0x10050 78 #define CL_MEM_USES_COMPRESSION_INTEL 0x10051 79 80 //Used with createBuffer 81 #define CL_MEM_ALLOW_UNRESTRICTED_SIZE_INTEL (1 << 23) 82 83 /****************************** 84 * UNIFIED MEMORY * 85 *******************************/ 86 87 /* cl_device_info */ 88 #define CL_DEVICE_HOST_MEM_CAPABILITIES_INTEL 0x4190 89 #define CL_DEVICE_DEVICE_MEM_CAPABILITIES_INTEL 0x4191 90 #define CL_DEVICE_SINGLE_DEVICE_SHARED_MEM_CAPABILITIES_INTEL 0x4192 91 #define CL_DEVICE_CROSS_DEVICE_SHARED_MEM_CAPABILITIES_INTEL 0x4193 92 #define CL_DEVICE_SHARED_SYSTEM_MEM_CAPABILITIES_INTEL 0x4194 93 94 /* cl_unified_shared_memory_capabilities_intel - bitfield */ 95 #define CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL (1 << 0) 96 #define CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL (1 << 1) 97 #define CL_UNIFIED_SHARED_MEMORY_CONCURRENT_ACCESS_INTEL (1 << 2) 98 #define CL_UNIFIED_SHARED_MEMORY_CONCURRENT_ATOMIC_ACCESS_INTEL (1 << 3) 99 100 /* cl_mem_properties_intel */ 101 #define CL_MEM_ALLOC_FLAGS_INTEL 0x4195 102 103 /* cl_mem_alloc_flags_intel - bitfield */ 104 #define CL_MEM_ALLOC_DEFAULT_INTEL 0 105 #define CL_MEM_ALLOC_WRITE_COMBINED_INTEL (1 << 0) 106 #define CL_MEM_ALLOC_INITIAL_PLACEMENT_DEVICE_INTEL (1 << 1) 107 #define CL_MEM_ALLOC_INITIAL_PLACEMENT_HOST_INTEL (1 << 2) 108 109 /* cl_mem_alloc_info_intel */ 110 #define CL_MEM_ALLOC_TYPE_INTEL 0x419A 111 #define CL_MEM_ALLOC_BASE_PTR_INTEL 0x419B 112 #define CL_MEM_ALLOC_SIZE_INTEL 0x419C 113 #define CL_MEM_ALLOC_DEVICE_INTEL 0x419D 114 115 /* cl_unified_shared_memory_type_intel */ 116 #define CL_MEM_TYPE_UNKNOWN_INTEL 0x4196 117 #define CL_MEM_TYPE_HOST_INTEL 0x4197 118 #define CL_MEM_TYPE_DEVICE_INTEL 0x4198 119 #define CL_MEM_TYPE_SHARED_INTEL 0x4199 120 121 /* cl_command_type */ 122 #define CL_COMMAND_MEMSET_INTEL 0x4204 123 #define CL_COMMAND_MEMFILL_INTEL 0x4204 124 #define CL_COMMAND_MEMCPY_INTEL 0x4205 125 #define CL_COMMAND_MIGRATEMEM_INTEL 0x4206 126 #define CL_COMMAND_MEMADVISE_INTEL 0x4207 127 128 /****************************** 129 * THREAD ARBITRATION POLICY * 130 *******************************/ 131 132 /* cl_device_info */ 133 #define CL_DEVICE_SUPPORTED_THREAD_ARBITRATION_POLICY_INTEL 0x4208 134 135 /* cl_kernel_exec_info */ 136 #define CL_KERNEL_EXEC_INFO_INDIRECT_HOST_ACCESS_INTEL 0x4200 137 #define CL_KERNEL_EXEC_INFO_INDIRECT_DEVICE_ACCESS_INTEL 0x4201 138 #define CL_KERNEL_EXEC_INFO_INDIRECT_SHARED_ACCESS_INTEL 0x4202 139 #define CL_KERNEL_EXEC_INFO_USM_PTRS_INTEL 0x4203 140 141 #define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_OLDEST_FIRST_INTEL 0x10022 142 #define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_ROUND_ROBIN_INTEL 0x10023 143 #define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_AFTER_DEPENDENCY_ROUND_ROBIN_INTEL 0x10024 144 #define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_INTEL 0x10025 145 #define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_STALL_BASED_ROUND_ROBIN_INTEL 0x10026 146 147 /****************************** 148 * SLICE COUNT SELECTING * 149 *******************************/ 150 151 /* cl_device_info */ 152 #define CL_DEVICE_SLICE_COUNT_INTEL 0x10020 153 154 /* cl_queue_properties */ 155 #define CL_QUEUE_SLICE_COUNT_INTEL 0x10021 156 157 /****************************** 158 * QUEUE FAMILY SELECTING * 159 *******************************/ 160 161 /* cl_device_info */ 162 #define CL_DEVICE_QUEUE_FAMILY_PROPERTIES_INTEL 0x418B 163 164 /* cl_queue_properties */ 165 #define CL_QUEUE_FAMILY_INTEL 0x418C 166 #define CL_QUEUE_INDEX_INTEL 0x418D 167 168 /* cl_command_queue_capabilities_intel */ 169 #define CL_QUEUE_DEFAULT_CAPABILITIES_INTEL 0u 170 #define CL_QUEUE_CAPABILITY_CREATE_SINGLE_QUEUE_EVENTS_INTEL (1 << 0) 171 #define CL_QUEUE_CAPABILITY_CREATE_CROSS_QUEUE_EVENTS_INTEL (1 << 1) 172 #define CL_QUEUE_CAPABILITY_SINGLE_QUEUE_EVENT_WAIT_LIST_INTEL (1 << 2) 173 #define CL_QUEUE_CAPABILITY_CROSS_QUEUE_EVENT_WAIT_LIST_INTEL (1 << 3) 174 #define CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_INTEL (1 << 8) 175 #define CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_RECT_INTEL (1 << 9) 176 #define CL_QUEUE_CAPABILITY_MAP_BUFFER_INTEL (1 << 10) 177 #define CL_QUEUE_CAPABILITY_FILL_BUFFER_INTEL (1 << 11) 178 #define CL_QUEUE_CAPABILITY_TRANSFER_IMAGE_INTEL (1 << 12) 179 #define CL_QUEUE_CAPABILITY_MAP_IMAGE_INTEL (1 << 13) 180 #define CL_QUEUE_CAPABILITY_FILL_IMAGE_INTEL (1 << 14) 181 #define CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_IMAGE_INTEL (1 << 15) 182 #define CL_QUEUE_CAPABILITY_TRANSFER_IMAGE_BUFFER_INTEL (1 << 16) 183 #define CL_QUEUE_CAPABILITY_MARKER_INTEL (1 << 24) 184 #define CL_QUEUE_CAPABILITY_BARRIER_INTEL (1 << 25) 185 #define CL_QUEUE_CAPABILITY_KERNEL_INTEL (1 << 26) 186 187 typedef cl_bitfield cl_command_queue_capabilities_intel; 188 189 #define CL_QUEUE_FAMILY_MAX_NAME_SIZE_INTEL 64 190 typedef struct _cl_queue_family_properties_intel { 191 cl_command_queue_properties properties; 192 cl_command_queue_capabilities_intel capabilities; 193 cl_uint count; 194 char name[CL_QUEUE_FAMILY_MAX_NAME_SIZE_INTEL]; 195 } cl_queue_family_properties_intel; 196 197 /****************************** 198 * DEVICE ATTRIBUTE QUERY * 199 *******************************/ 200 201 /* For GPU devices, version 1.0.0: */ 202 #define CL_DEVICE_IP_VERSION_INTEL 0x4250 203 #define CL_DEVICE_ID_INTEL 0x4251 204 #define CL_DEVICE_NUM_SLICES_INTEL 0x4252 205 #define CL_DEVICE_NUM_SUB_SLICES_PER_SLICE_INTEL 0x4253 206 #define CL_DEVICE_NUM_EUS_PER_SUB_SLICE_INTEL 0x4254 207 #define CL_DEVICE_NUM_THREADS_PER_EU_INTEL 0x4255 208 #define CL_DEVICE_FEATURE_CAPABILITIES_INTEL 0x4256 209 210 typedef cl_bitfield cl_device_feature_capabilities_intel; 211 212 /* For GPU devices, version 1.0.0: */ 213 #define CL_DEVICE_FEATURE_FLAG_DP4A_INTEL (1 << 0) 214 215 ////// RESOURCE BARRIER EXT 216 #define CL_COMMAND_RESOURCE_BARRIER 0x10010 217 218 typedef cl_uint cl_resource_barrier_type; 219 #define CL_RESOURCE_BARRIER_TYPE_ACQUIRE 0x1 // FLUSH+EVICT 220 #define CL_RESOURCE_BARRIER_TYPE_RELEASE 0x2 // FLUSH 221 #define CL_RESOURCE_BARRIER_TYPE_DISCARD 0x3 // DISCARD 222 223 typedef cl_uint cl_resource_memory_scope; 224 #define CL_MEMORY_SCOPE_DEVICE 0x0 // INCLUDES CROSS-TILE 225 #define CL_MEMORY_SCOPE_ALL_SVM_DEVICES 0x1 // CL_MEMORY_SCOPE_DEVICE + CROSS-DEVICE 226 227 #pragma pack(push, 1) 228 typedef struct _cl_resource_barrier_descriptor_intel { 229 void *svm_allocation_pointer; 230 cl_mem mem_object; 231 cl_resource_barrier_type type; 232 cl_resource_memory_scope scope; 233 } cl_resource_barrier_descriptor_intel; 234 #pragma pack(pop) 235 236 /**************************************** 237 * cl_khr_pci_bus_info extension * 238 ***************************************/ 239 #define cl_khr_pci_bus_info 1 240 241 // New queries for clGetDeviceInfo: 242 #define CL_DEVICE_PCI_BUS_INFO_KHR 0x410F 243 244 typedef struct _cl_device_pci_bus_info_khr { 245 cl_uint pci_domain; 246 cl_uint pci_bus; 247 cl_uint pci_device; 248 cl_uint pci_function; 249 } cl_device_pci_bus_info_khr; 250 251 /************************************************ 252 * cl_intel_mem_compression_hints extension * 253 *************************************************/ 254 #define CL_MEM_COMPRESSED_HINT_INTEL (1u << 21) 255 #define CL_MEM_UNCOMPRESSED_HINT_INTEL (1u << 22) 256 257 // New query for clGetDeviceInfo: 258 #define CL_MEM_COMPRESSED_INTEL 0x417D 259