1 /*
2 * Copyright 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26
27 #include "drm.h"
28
29 #if defined(__cplusplus)
30 extern "C" {
31 #endif
32
33 /**
34 * DOC: overview
35 *
36 * In the DRM subsystem, framebuffer pixel formats are described using the
37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
40 *
41 * Format Modifiers
42 * ----------------
43 *
44 * Format modifiers are used in conjunction with a fourcc code, forming a
45 * unique fourcc:modifier pair. This format:modifier pair must fully define the
46 * format and data layout of the buffer, and should be the only way to describe
47 * that particular buffer.
48 *
49 * Having multiple fourcc:modifier pairs which describe the same layout should
50 * be avoided, as such aliases run the risk of different drivers exposing
51 * different names for the same data format, forcing userspace to understand
52 * that they are aliases.
53 *
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * modifier is specific to the modifer being used. For example, some modifiers
58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.
60 *
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
63 * another modifier. For instance, it's incorrect to encode pitch alignment in
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
65 * aligned modifier. That said, modifiers can have implicit minimal
66 * requirements.
67 *
68 * For modifiers where the combination of fourcc code and modifier can alias,
69 * a canonical pair needs to be defined and used by all drivers. Preferred
70 * combinations are also encouraged where all combinations might lead to
71 * confusion and unnecessarily reduced interoperability. An example for the
72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
73 *
74 * There are two kinds of modifier users:
75 *
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
77 * don't alias, otherwise two drivers might support the same format but use
78 * different aliases, preventing them from sharing buffers in an efficient
79 * format.
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
81 * see modifiers as opaque tokens they can check for equality and intersect.
82 * These users musn't need to know to reason about the modifier value
83 * (i.e. they are not expected to extract information out of the modifier).
84 *
85 * Vendors should document their modifier usage in as much detail as
86 * possible, to ensure maximum compatibility across devices, drivers and
87 * applications.
88 *
89 * The authoritative list of format modifier codes is found in
90 * `include/uapi/drm/drm_fourcc.h`
91 */
92
93 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
94 ((__u32)(c) << 16) | ((__u32)(d) << 24))
95
96 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
97
98 /* Reserve 0 for the invalid format specifier */
99 #define DRM_FORMAT_INVALID 0
100
101 /* color index */
102 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
103
104 /* 8 bpp Red */
105 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
106
107 /* 16 bpp Red */
108 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
109
110 /* 16 bpp RG */
111 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
112 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
113
114 /* 32 bpp RG */
115 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
116 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
117
118 /* 8 bpp RGB */
119 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
120 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
121
122 /* 16 bpp RGB */
123 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
124 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
125 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
126 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
127
128 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
129 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
130 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
131 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
132
133 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
134 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
135 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
136 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
137
138 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
139 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
140 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
141 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
142
143 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
144 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
145
146 /* 24 bpp RGB */
147 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
148 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
149
150 /* 32 bpp RGB */
151 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
152 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
153 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
154 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
155
156 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
157 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
158 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
159 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
160
161 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
162 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
163 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
164 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
165
166 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
167 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
168 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
169 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
170
171 /*
172 * Floating point 64bpp RGB
173 * IEEE 754-2008 binary16 half-precision float
174 * [15:0] sign:exponent:mantissa 1:5:10
175 */
176 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
177 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
178
179 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
180 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
181
182 /*
183 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
184 * of unused padding per component:
185 */
186 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
187
188 /* packed YCbCr */
189 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
190 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
191 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
192 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
193
194 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
195 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
196 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
197 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
198
199 /*
200 * packed Y2xx indicate for each component, xx valid data occupy msb
201 * 16-xx padding occupy lsb
202 */
203 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
204 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
205 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
206
207 /*
208 * packed Y4xx indicate for each component, xx valid data occupy msb
209 * 16-xx padding occupy lsb except Y410
210 */
211 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
212 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
213 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
214
215 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
216 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
217 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
218
219 /*
220 * packed YCbCr420 2x2 tiled formats
221 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
222 */
223 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
224 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
225 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
226 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
227
228 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
229 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
230 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
231 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
232
233 /*
234 * 1-plane YUV 4:2:0
235 * In these formats, the component ordering is specified (Y, followed by U
236 * then V), but the exact Linear layout is undefined.
237 * These formats can only be used with a non-Linear modifier.
238 */
239 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
240 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
241
242 /*
243 * 2 plane RGB + A
244 * index 0 = RGB plane, same format as the corresponding non _A8 format has
245 * index 1 = A plane, [7:0] A
246 */
247 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
248 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
249 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
250 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
251 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
252 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
253 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
254 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
255
256 /*
257 * 2 plane YCbCr
258 * index 0 = Y plane, [7:0] Y
259 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
260 * or
261 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
262 */
263 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
264 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
265 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
266 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
267 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
268 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
269 /*
270 * 2 plane YCbCr
271 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
272 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
273 */
274 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
275
276 /*
277 * 2 plane YCbCr MSB aligned
278 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
279 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
280 */
281 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
282
283 /*
284 * 2 plane YCbCr MSB aligned
285 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
286 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
287 */
288 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
289
290 /*
291 * 2 plane YCbCr MSB aligned
292 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
293 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
294 */
295 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
296
297 /*
298 * 2 plane YCbCr MSB aligned
299 * index 0 = Y plane, [15:0] Y little endian
300 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
301 */
302 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
303
304 /* 3 plane non-subsampled (444) YCbCr
305 * 16 bits per component, but only 10 bits are used and 6 bits are padded
306 * index 0: Y plane, [15:0] Y:x [10:6] little endian
307 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
308 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
309 */
310 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
311
312 /* 3 plane non-subsampled (444) YCrCb
313 * 16 bits per component, but only 10 bits are used and 6 bits are padded
314 * index 0: Y plane, [15:0] Y:x [10:6] little endian
315 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
316 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
317 */
318 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
319
320 /*
321 * 3 plane YCbCr
322 * index 0: Y plane, [7:0] Y
323 * index 1: Cb plane, [7:0] Cb
324 * index 2: Cr plane, [7:0] Cr
325 * or
326 * index 1: Cr plane, [7:0] Cr
327 * index 2: Cb plane, [7:0] Cb
328 */
329 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
330 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
331 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
332 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
333 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
334 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
335 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
336 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
337 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
338 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
339
340
341 /*
342 * Format Modifiers:
343 *
344 * Format modifiers describe, typically, a re-ordering or modification
345 * of the data in a plane of an FB. This can be used to express tiled/
346 * swizzled formats, or compression, or a combination of the two.
347 *
348 * The upper 8 bits of the format modifier are a vendor-id as assigned
349 * below. The lower 56 bits are assigned as vendor sees fit.
350 */
351
352 /* Vendor Ids: */
353 #define DRM_FORMAT_MOD_VENDOR_NONE 0
354 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
355 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
356 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
357 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
358 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
359 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
360 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
361 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
362 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
363 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
364
365 /* add more to the end as needed */
366
367 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
368
369 #define fourcc_mod_code(vendor, val) \
370 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
371
372 /*
373 * Intel modifiers for new platforms should be added using the PRELIM_ prefix
374 * and the intel_prelim_fourcc_mod_code macro, while the upstreaming of the
375 * platform should happen without the prefix using the fourcc_mod_code macro.
376 */
377 #define INTEL_PRELIM_ID_FLAG (1ULL << 55)
378
379 #define intel_prelim_fourcc_mod_code(val) \
380 (fourcc_mod_code(INTEL, (val)) | INTEL_PRELIM_ID_FLAG)
381
382 /*
383 * Format Modifier tokens:
384 *
385 * When adding a new token please document the layout with a code comment,
386 * similar to the fourcc codes above. drm_fourcc.h is considered the
387 * authoritative source for all of these.
388 *
389 * Generic modifier names:
390 *
391 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
392 * for layouts which are common across multiple vendors. To preserve
393 * compatibility, in cases where a vendor-specific definition already exists and
394 * a generic name for it is desired, the common name is a purely symbolic alias
395 * and must use the same numerical value as the original definition.
396 *
397 * Note that generic names should only be used for modifiers which describe
398 * generic layouts (such as pixel re-ordering), which may have
399 * independently-developed support across multiple vendors.
400 *
401 * In future cases where a generic layout is identified before merging with a
402 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
403 * 'NONE' could be considered. This should only be for obvious, exceptional
404 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
405 * apply to a single vendor.
406 *
407 * Generic names should not be used for cases where multiple hardware vendors
408 * have implementations of the same standardised compression scheme (such as
409 * AFBC). In those cases, all implementations should use the same format
410 * modifier(s), reflecting the vendor of the standard.
411 */
412
413 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
414
415 /*
416 * Invalid Modifier
417 *
418 * This modifier can be used as a sentinel to terminate the format modifiers
419 * list, or to initialize a variable with an invalid modifier. It might also be
420 * used to report an error back to userspace for certain APIs.
421 */
422 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
423
424 /*
425 * Linear Layout
426 *
427 * Just plain linear layout. Note that this is different from no specifying any
428 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
429 * which tells the driver to also take driver-internal information into account
430 * and so might actually result in a tiled framebuffer.
431 */
432 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
433
434 /*
435 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
436 *
437 * The "none" format modifier doesn't actually mean that the modifier is
438 * implicit, instead it means that the layout is linear. Whether modifiers are
439 * used is out-of-band information carried in an API-specific way (e.g. in a
440 * flag for drm_mode_fb_cmd2).
441 */
442 #define DRM_FORMAT_MOD_NONE 0
443
444 /* Intel framebuffer modifiers */
445
446 /*
447 * Intel X-tiling layout
448 *
449 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
450 * in row-major layout. Within the tile bytes are laid out row-major, with
451 * a platform-dependent stride. On top of that the memory can apply
452 * platform-depending swizzling of some higher address bits into bit6.
453 *
454 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
455 * On earlier platforms the is highly platforms specific and not useful for
456 * cross-driver sharing. It exists since on a given platform it does uniquely
457 * identify the layout in a simple way for i915-specific userspace, which
458 * facilitated conversion of userspace to modifiers. Additionally the exact
459 * format on some really old platforms is not known.
460 */
461 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
462
463 /*
464 * Intel Y-tiling layout
465 *
466 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
467 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
468 * chunks column-major, with a platform-dependent height. On top of that the
469 * memory can apply platform-depending swizzling of some higher address bits
470 * into bit6.
471 *
472 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
473 * On earlier platforms the is highly platforms specific and not useful for
474 * cross-driver sharing. It exists since on a given platform it does uniquely
475 * identify the layout in a simple way for i915-specific userspace, which
476 * facilitated conversion of userspace to modifiers. Additionally the exact
477 * format on some really old platforms is not known.
478 */
479 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
480
481 /*
482 * Intel Yf-tiling layout
483 *
484 * This is a tiled layout using 4Kb tiles in row-major layout.
485 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
486 * are arranged in four groups (two wide, two high) with column-major layout.
487 * Each group therefore consits out of four 256 byte units, which are also laid
488 * out as 2x2 column-major.
489 * 256 byte units are made out of four 64 byte blocks of pixels, producing
490 * either a square block or a 2:1 unit.
491 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
492 * in pixel depends on the pixel depth.
493 */
494 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
495
496 /*
497 * Intel color control surface (CCS) for render compression
498 *
499 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
500 * The main surface will be plane index 0 and must be Y/Yf-tiled,
501 * the CCS will be plane index 1.
502 *
503 * Each CCS tile matches a 1024x512 pixel area of the main surface.
504 * To match certain aspects of the 3D hardware the CCS is
505 * considered to be made up of normal 128Bx32 Y tiles, Thus
506 * the CCS pitch must be specified in multiples of 128 bytes.
507 *
508 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
509 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
510 * But that fact is not relevant unless the memory is accessed
511 * directly.
512 */
513 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
514 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
515
516 /*
517 * Intel color control surfaces (CCS) for Gen-12 render compression.
518 *
519 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
520 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
521 * main surface. In other words, 4 bits in CCS map to a main surface cache
522 * line pair. The main surface pitch is required to be a multiple of four
523 * Y-tile widths.
524 */
525 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
526
527 /*
528 * Intel color control surfaces (CCS) for Gen-12 media compression
529 *
530 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
531 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
532 * main surface. In other words, 4 bits in CCS map to a main surface cache
533 * line pair. The main surface pitch is required to be a multiple of four
534 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
535 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
536 * planes 2 and 3 for the respective CCS.
537 */
538 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
539
540 /*
541 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
542 * compression.
543 *
544 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
545 * and at index 1. The clear color is stored at index 2, and the pitch should
546 * be ignored. The clear color structure is 256 bits. The first 128 bits
547 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
548 * by 32 bits. The raw clear color is consumed by the 3d engine and generates
549 * the converted clear color of size 64 bits. The first 32 bits store the Lower
550 * Converted Clear Color value and the next 32 bits store the Higher Converted
551 * Clear Color value when applicable. The Converted Clear Color values are
552 * consumed by the DE. The last 64 bits are used to store Color Discard Enable
553 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
554 * corresponds to an area of 4x1 tiles in the main surface. The main surface
555 * pitch is required to be a multiple of 4 tile widths.
556 */
557 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
558
559 /*
560 * TODO: Remove the non-PRELIM version of DG2 CCS modifiers in the 9-11 ID range
561 * Backport the upstream ADL-P CCS modifiers using the 9-11 ID range.
562 */
563
564 /*
565 * Intel F-tiling(aka Tile4) layout
566 *
567 * This is a tiled layout using 4Kb tiles in row-major layout.
568 * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
569 * (16 bytes) chunks column-major..
570 */
571 #define I915_FORMAT_MOD_F_TILED fourcc_mod_code(INTEL, 12)
572
573 /*
574 * Intel color control surfaces (CCS) for DG2 render compression.
575 *
576 * DG2 uses a new compression format for render compression. The general
577 * layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
578 * but a new hashing/compression algorithm is used, so a fresh modifier must
579 * be associated with buffers of this type. Render compression uses 128 byte
580 * compression blocks.
581 */
582 #define I915_FORMAT_MOD_F_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 9)
583 #define PRELIM_I915_FORMAT_MOD_F_TILED_DG2_RC_CCS intel_prelim_fourcc_mod_code(13)
584
585 /*
586 * Intel color control surfaces (CCS) for DG2 media compression.
587 *
588 * DG2 uses a new compression format for media compression. The general
589 * layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
590 * but a new hashing/compression algorithm is used, so a fresh modifier must
591 * be associated with buffers of this type. Media compression uses 256 byte
592 * compression blocks.
593 */
594 #define I915_FORMAT_MOD_F_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 10)
595 #define PRELIM_I915_FORMAT_MOD_F_TILED_DG2_MC_CCS intel_prelim_fourcc_mod_code(14)
596
597 /*
598 * Intel color control surfaces (CCS) for DG2 clear color render compression.
599 *
600 * DG2 uses a unified compression format for clear color render compression.
601 * The general layout is a tiled layout using 4Kb tiles i.e. Tile4 layout.
602 */
603 #define I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 11)
604 #define PRELIM_I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC intel_prelim_fourcc_mod_code(15)
605
606 /*
607 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
608 *
609 * Macroblocks are laid in a Z-shape, and each pixel data is following the
610 * standard NV12 style.
611 * As for NV12, an image is the result of two frame buffers: one for Y,
612 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
613 * Alignment requirements are (for each buffer):
614 * - multiple of 128 pixels for the width
615 * - multiple of 32 pixels for the height
616 *
617 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
618 */
619 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
620
621 /*
622 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
623 *
624 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
625 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
626 * they correspond to their 16x16 luma block.
627 */
628 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
629
630 /*
631 * Qualcomm Compressed Format
632 *
633 * Refers to a compressed variant of the base format that is compressed.
634 * Implementation may be platform and base-format specific.
635 *
636 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
637 * Pixel data pitch/stride is aligned with macrotile width.
638 * Pixel data height is aligned with macrotile height.
639 * Entire pixel data buffer is aligned with 4k(bytes).
640 */
641 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
642
643 /* Vivante framebuffer modifiers */
644
645 /*
646 * Vivante 4x4 tiling layout
647 *
648 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
649 * layout.
650 */
651 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
652
653 /*
654 * Vivante 64x64 super-tiling layout
655 *
656 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
657 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
658 * major layout.
659 *
660 * For more information: see
661 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
662 */
663 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
664
665 /*
666 * Vivante 4x4 tiling layout for dual-pipe
667 *
668 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
669 * different base address. Offsets from the base addresses are therefore halved
670 * compared to the non-split tiled layout.
671 */
672 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
673
674 /*
675 * Vivante 64x64 super-tiling layout for dual-pipe
676 *
677 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
678 * starts at a different base address. Offsets from the base addresses are
679 * therefore halved compared to the non-split super-tiled layout.
680 */
681 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
682
683 /* NVIDIA frame buffer modifiers */
684
685 /*
686 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
687 *
688 * Pixels are arranged in simple tiles of 16 x 16 bytes.
689 */
690 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
691
692 /*
693 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
694 * and Tegra GPUs starting with Tegra K1.
695 *
696 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
697 * based on the architecture generation. GOBs themselves are then arranged in
698 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
699 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
700 * a block depth or height of "4").
701 *
702 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
703 * in full detail.
704 *
705 * Macro
706 * Bits Param Description
707 * ---- ----- -----------------------------------------------------------------
708 *
709 * 3:0 h log2(height) of each block, in GOBs. Placed here for
710 * compatibility with the existing
711 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
712 *
713 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
714 * compatibility with the existing
715 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
716 *
717 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
718 * size). Must be zero.
719 *
720 * Note there is no log2(width) parameter. Some portions of the
721 * hardware support a block width of two gobs, but it is impractical
722 * to use due to lack of support elsewhere, and has no known
723 * benefits.
724 *
725 * 11:9 - Reserved (To support 2D-array textures with variable array stride
726 * in blocks, specified via log2(tile width in blocks)). Must be
727 * zero.
728 *
729 * 19:12 k Page Kind. This value directly maps to a field in the page
730 * tables of all GPUs >= NV50. It affects the exact layout of bits
731 * in memory and can be derived from the tuple
732 *
733 * (format, GPU model, compression type, samples per pixel)
734 *
735 * Where compression type is defined below. If GPU model were
736 * implied by the format modifier, format, or memory buffer, page
737 * kind would not need to be included in the modifier itself, but
738 * since the modifier should define the layout of the associated
739 * memory buffer independent from any device or other context, it
740 * must be included here.
741 *
742 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
743 * starting with Fermi GPUs. Additionally, the mapping between page
744 * kind and bit layout has changed at various points.
745 *
746 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
747 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
748 * 2 = Gob Height 8, Turing+ Page Kind mapping
749 * 3 = Reserved for future use.
750 *
751 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
752 * bit remapping step that occurs at an even lower level than the
753 * page kind and block linear swizzles. This causes the layout of
754 * surfaces mapped in those SOC's GPUs to be incompatible with the
755 * equivalent mapping on other GPUs in the same system.
756 *
757 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
758 * 1 = Desktop GPU and Tegra Xavier+ Layout
759 *
760 * 25:23 c Lossless Framebuffer Compression type.
761 *
762 * 0 = none
763 * 1 = ROP/3D, layout 1, exact compression format implied by Page
764 * Kind field
765 * 2 = ROP/3D, layout 2, exact compression format implied by Page
766 * Kind field
767 * 3 = CDE horizontal
768 * 4 = CDE vertical
769 * 5 = Reserved for future use
770 * 6 = Reserved for future use
771 * 7 = Reserved for future use
772 *
773 * 55:25 - Reserved for future use. Must be zero.
774 */
775 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
776 fourcc_mod_code(NVIDIA, (0x10 | \
777 ((h) & 0xf) | \
778 (((k) & 0xff) << 12) | \
779 (((g) & 0x3) << 20) | \
780 (((s) & 0x1) << 22) | \
781 (((c) & 0x7) << 23)))
782
783 /* To grandfather in prior block linear format modifiers to the above layout,
784 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
785 * with block-linear layouts, is remapped within drivers to the value 0xfe,
786 * which corresponds to the "generic" kind used for simple single-sample
787 * uncompressed color formats on Fermi - Volta GPUs.
788 */
789 static __inline__ __u64
drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)790 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
791 {
792 if (!(modifier & 0x10) || (modifier & (0xff << 12)))
793 return modifier;
794 else
795 return modifier | (0xfe << 12);
796 }
797
798 /*
799 * 16Bx2 Block Linear layout, used by Tegra K1 and later
800 *
801 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
802 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
803 *
804 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
805 *
806 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
807 * Valid values are:
808 *
809 * 0 == ONE_GOB
810 * 1 == TWO_GOBS
811 * 2 == FOUR_GOBS
812 * 3 == EIGHT_GOBS
813 * 4 == SIXTEEN_GOBS
814 * 5 == THIRTYTWO_GOBS
815 *
816 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
817 * in full detail.
818 */
819 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
820 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
821
822 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
823 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
824 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
825 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
826 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
827 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
828 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
829 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
830 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
831 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
832 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
833 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
834
835 /*
836 * Some Broadcom modifiers take parameters, for example the number of
837 * vertical lines in the image. Reserve the lower 32 bits for modifier
838 * type, and the next 24 bits for parameters. Top 8 bits are the
839 * vendor code.
840 */
841 #define __fourcc_mod_broadcom_param_shift 8
842 #define __fourcc_mod_broadcom_param_bits 48
843 #define fourcc_mod_broadcom_code(val, params) \
844 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
845 #define fourcc_mod_broadcom_param(m) \
846 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
847 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
848 #define fourcc_mod_broadcom_mod(m) \
849 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
850 __fourcc_mod_broadcom_param_shift))
851
852 /*
853 * Broadcom VC4 "T" format
854 *
855 * This is the primary layout that the V3D GPU can texture from (it
856 * can't do linear). The T format has:
857 *
858 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
859 * pixels at 32 bit depth.
860 *
861 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
862 * 16x16 pixels).
863 *
864 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
865 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
866 * they're (TR, BR, BL, TL), where bottom left is start of memory.
867 *
868 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
869 * tiles) or right-to-left (odd rows of 4k tiles).
870 */
871 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
872
873 /*
874 * Broadcom SAND format
875 *
876 * This is the native format that the H.264 codec block uses. For VC4
877 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
878 *
879 * The image can be considered to be split into columns, and the
880 * columns are placed consecutively into memory. The width of those
881 * columns can be either 32, 64, 128, or 256 pixels, but in practice
882 * only 128 pixel columns are used.
883 *
884 * The pitch between the start of each column is set to optimally
885 * switch between SDRAM banks. This is passed as the number of lines
886 * of column width in the modifier (we can't use the stride value due
887 * to various core checks that look at it , so you should set the
888 * stride to width*cpp).
889 *
890 * Note that the column height for this format modifier is the same
891 * for all of the planes, assuming that each column contains both Y
892 * and UV. Some SAND-using hardware stores UV in a separate tiled
893 * image from Y to reduce the column height, which is not supported
894 * with these modifiers.
895 */
896
897 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
898 fourcc_mod_broadcom_code(2, v)
899 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
900 fourcc_mod_broadcom_code(3, v)
901 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
902 fourcc_mod_broadcom_code(4, v)
903 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
904 fourcc_mod_broadcom_code(5, v)
905
906 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
907 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
908 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
909 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
910 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
911 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
912 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
913 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
914
915 /* Broadcom UIF format
916 *
917 * This is the common format for the current Broadcom multimedia
918 * blocks, including V3D 3.x and newer, newer video codecs, and
919 * displays.
920 *
921 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
922 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
923 * stored in columns, with padding between the columns to ensure that
924 * moving from one column to the next doesn't hit the same SDRAM page
925 * bank.
926 *
927 * To calculate the padding, it is assumed that each hardware block
928 * and the software driving it knows the platform's SDRAM page size,
929 * number of banks, and XOR address, and that it's identical between
930 * all blocks using the format. This tiling modifier will use XOR as
931 * necessary to reduce the padding. If a hardware block can't do XOR,
932 * the assumption is that a no-XOR tiling modifier will be created.
933 */
934 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
935
936 /*
937 * Arm Framebuffer Compression (AFBC) modifiers
938 *
939 * AFBC is a proprietary lossless image compression protocol and format.
940 * It provides fine-grained random access and minimizes the amount of data
941 * transferred between IP blocks.
942 *
943 * AFBC has several features which may be supported and/or used, which are
944 * represented using bits in the modifier. Not all combinations are valid,
945 * and different devices or use-cases may support different combinations.
946 *
947 * Further information on the use of AFBC modifiers can be found in
948 * Documentation/gpu/afbc.rst
949 */
950
951 /*
952 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
953 * modifiers) denote the category for modifiers. Currently we have only two
954 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
955 * different categories.
956 */
957 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
958 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
959
960 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
961 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
962
963 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
964 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
965
966 /*
967 * AFBC superblock size
968 *
969 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
970 * size (in pixels) must be aligned to a multiple of the superblock size.
971 * Four lowest significant bits(LSBs) are reserved for block size.
972 *
973 * Where one superblock size is specified, it applies to all planes of the
974 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
975 * the first applies to the Luma plane and the second applies to the Chroma
976 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
977 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
978 */
979 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
980 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
981 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
982 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
983 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
984
985 /*
986 * AFBC lossless colorspace transform
987 *
988 * Indicates that the buffer makes use of the AFBC lossless colorspace
989 * transform.
990 */
991 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
992
993 /*
994 * AFBC block-split
995 *
996 * Indicates that the payload of each superblock is split. The second
997 * half of the payload is positioned at a predefined offset from the start
998 * of the superblock payload.
999 */
1000 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
1001
1002 /*
1003 * AFBC sparse layout
1004 *
1005 * This flag indicates that the payload of each superblock must be stored at a
1006 * predefined position relative to the other superblocks in the same AFBC
1007 * buffer. This order is the same order used by the header buffer. In this mode
1008 * each superblock is given the same amount of space as an uncompressed
1009 * superblock of the particular format would require, rounding up to the next
1010 * multiple of 128 bytes in size.
1011 */
1012 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
1013
1014 /*
1015 * AFBC copy-block restrict
1016 *
1017 * Buffers with this flag must obey the copy-block restriction. The restriction
1018 * is such that there are no copy-blocks referring across the border of 8x8
1019 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
1020 */
1021 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
1022
1023 /*
1024 * AFBC tiled layout
1025 *
1026 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1027 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1028 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
1029 * larger bpp formats. The order between the tiles is scan line.
1030 * When the tiled layout is used, the buffer size (in pixels) must be aligned
1031 * to the tile size.
1032 */
1033 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
1034
1035 /*
1036 * AFBC solid color blocks
1037 *
1038 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1039 * can be reduced if a whole superblock is a single color.
1040 */
1041 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
1042
1043 /*
1044 * AFBC double-buffer
1045 *
1046 * Indicates that the buffer is allocated in a layout safe for front-buffer
1047 * rendering.
1048 */
1049 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
1050
1051 /*
1052 * AFBC buffer content hints
1053 *
1054 * Indicates that the buffer includes per-superblock content hints.
1055 */
1056 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
1057
1058 /* AFBC uncompressed storage mode
1059 *
1060 * Indicates that the buffer is using AFBC uncompressed storage mode.
1061 * In this mode all superblock payloads in the buffer use the uncompressed
1062 * storage mode, which is usually only used for data which cannot be compressed.
1063 * The buffer layout is the same as for AFBC buffers without USM set, this only
1064 * affects the storage mode of the individual superblocks. Note that even a
1065 * buffer without USM set may use uncompressed storage mode for some or all
1066 * superblocks, USM just guarantees it for all.
1067 */
1068 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
1069
1070 /*
1071 * Arm 16x16 Block U-Interleaved modifier
1072 *
1073 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
1074 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
1075 * in the block are reordered.
1076 */
1077 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
1078 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1079
1080 /*
1081 * Allwinner tiled modifier
1082 *
1083 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
1084 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1085 * planes.
1086 *
1087 * With this tiling, the luminance samples are disposed in tiles representing
1088 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
1089 * The pixel order in each tile is linear and the tiles are disposed linearly,
1090 * both in row-major order.
1091 */
1092 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1093
1094 /*
1095 * Amlogic Video Framebuffer Compression modifiers
1096 *
1097 * Amlogic uses a proprietary lossless image compression protocol and format
1098 * for their hardware video codec accelerators, either video decoders or
1099 * video input encoders.
1100 *
1101 * It considerably reduces memory bandwidth while writing and reading
1102 * frames in memory.
1103 *
1104 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1105 * per component YCbCr 420, single plane :
1106 * - DRM_FORMAT_YUV420_8BIT
1107 * - DRM_FORMAT_YUV420_10BIT
1108 *
1109 * The first 8 bits of the mode defines the layout, then the following 8 bits
1110 * defines the options changing the layout.
1111 *
1112 * Not all combinations are valid, and different SoCs may support different
1113 * combinations of layout and options.
1114 */
1115 #define __fourcc_mod_amlogic_layout_mask 0xf
1116 #define __fourcc_mod_amlogic_options_shift 8
1117 #define __fourcc_mod_amlogic_options_mask 0xf
1118
1119 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1120 fourcc_mod_code(AMLOGIC, \
1121 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \
1122 (((__options) & __fourcc_mod_amlogic_options_mask) \
1123 << __fourcc_mod_amlogic_options_shift))
1124
1125 /* Amlogic FBC Layouts */
1126
1127 /*
1128 * Amlogic FBC Basic Layout
1129 *
1130 * The basic layout is composed of:
1131 * - a body content organized in 64x32 superblocks with 4096 bytes per
1132 * superblock in default mode.
1133 * - a 32 bytes per 128x64 header block
1134 *
1135 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1136 */
1137 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1138
1139 /*
1140 * Amlogic FBC Scatter Memory layout
1141 *
1142 * Indicates the header contains IOMMU references to the compressed
1143 * frames content to optimize memory access and layout.
1144 *
1145 * In this mode, only the header memory address is needed, thus the
1146 * content memory organization is tied to the current producer
1147 * execution and cannot be saved/dumped neither transferrable between
1148 * Amlogic SoCs supporting this modifier.
1149 *
1150 * Due to the nature of the layout, these buffers are not expected to
1151 * be accessible by the user-space clients, but only accessible by the
1152 * hardware producers and consumers.
1153 *
1154 * The user-space clients should expect a failure while trying to mmap
1155 * the DMA-BUF handle returned by the producer.
1156 */
1157 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
1158
1159 /* Amlogic FBC Layout Options Bit Mask */
1160
1161 /*
1162 * Amlogic FBC Memory Saving mode
1163 *
1164 * Indicates the storage is packed when pixel size is multiple of word
1165 * boudaries, i.e. 8bit should be stored in this mode to save allocation
1166 * memory.
1167 *
1168 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1169 * the basic layout and 3200 bytes per 64x32 superblock combined with
1170 * the scatter layout.
1171 */
1172 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1173
1174 /*
1175 * AMD modifiers
1176 *
1177 * Memory layout:
1178 *
1179 * without DCC:
1180 * - main surface
1181 *
1182 * with DCC & without DCC_RETILE:
1183 * - main surface in plane 0
1184 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1185 *
1186 * with DCC & DCC_RETILE:
1187 * - main surface in plane 0
1188 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1189 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1190 *
1191 * For multi-plane formats the above surfaces get merged into one plane for
1192 * each format plane, based on the required alignment only.
1193 *
1194 * Bits Parameter Notes
1195 * ----- ------------------------ ---------------------------------------------
1196 *
1197 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
1198 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1199 * 13 DCC
1200 * 14 DCC_RETILE
1201 * 15 DCC_PIPE_ALIGN
1202 * 16 DCC_INDEPENDENT_64B
1203 * 17 DCC_INDEPENDENT_128B
1204 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
1205 * 20 DCC_CONSTANT_ENCODE
1206 * 23:21 PIPE_XOR_BITS Only for some chips
1207 * 26:24 BANK_XOR_BITS Only for some chips
1208 * 29:27 PACKERS Only for some chips
1209 * 32:30 RB Only for some chips
1210 * 35:33 PIPE Only for some chips
1211 * 55:36 - Reserved for future use, must be zero
1212 */
1213 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
1214
1215 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
1216
1217 /* Reserve 0 for GFX8 and older */
1218 #define AMD_FMT_MOD_TILE_VER_GFX9 1
1219 #define AMD_FMT_MOD_TILE_VER_GFX10 2
1220 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
1221
1222 /*
1223 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
1224 * version.
1225 */
1226 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9
1227
1228 /*
1229 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1230 * GFX9 as canonical version.
1231 */
1232 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1233 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
1234 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
1235 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
1236
1237 #define AMD_FMT_MOD_DCC_BLOCK_64B 0
1238 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
1239 #define AMD_FMT_MOD_DCC_BLOCK_256B 2
1240
1241 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
1242 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
1243 #define AMD_FMT_MOD_TILE_SHIFT 8
1244 #define AMD_FMT_MOD_TILE_MASK 0x1F
1245
1246 /* Whether DCC compression is enabled. */
1247 #define AMD_FMT_MOD_DCC_SHIFT 13
1248 #define AMD_FMT_MOD_DCC_MASK 0x1
1249
1250 /*
1251 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
1252 * one which is not-aligned.
1253 */
1254 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
1255 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
1256
1257 /* Only set if DCC_RETILE = false */
1258 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
1259 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
1260
1261 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
1262 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
1263 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
1264 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
1265 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
1266 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
1267
1268 /*
1269 * DCC supports embedding some clear colors directly in the DCC surface.
1270 * However, on older GPUs the rendering HW ignores the embedded clear color
1271 * and prefers the driver provided color. This necessitates doing a fastclear
1272 * eliminate operation before a process transfers control.
1273 *
1274 * If this bit is set that means the fastclear eliminate is not needed for these
1275 * embeddable colors.
1276 */
1277 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
1278 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
1279
1280 /*
1281 * The below fields are for accounting for per GPU differences. These are only
1282 * relevant for GFX9 and later and if the tile field is *_X/_T.
1283 *
1284 * PIPE_XOR_BITS = always needed
1285 * BANK_XOR_BITS = only for TILE_VER_GFX9
1286 * PACKERS = only for TILE_VER_GFX10_RBPLUS
1287 * RB = only for TILE_VER_GFX9 & DCC
1288 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
1289 */
1290 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
1291 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
1292 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
1293 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
1294 #define AMD_FMT_MOD_PACKERS_SHIFT 27
1295 #define AMD_FMT_MOD_PACKERS_MASK 0x7
1296 #define AMD_FMT_MOD_RB_SHIFT 30
1297 #define AMD_FMT_MOD_RB_MASK 0x7
1298 #define AMD_FMT_MOD_PIPE_SHIFT 33
1299 #define AMD_FMT_MOD_PIPE_MASK 0x7
1300
1301 #define AMD_FMT_MOD_SET(field, value) \
1302 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
1303 #define AMD_FMT_MOD_GET(field, value) \
1304 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
1305 #define AMD_FMT_MOD_CLEAR(field) \
1306 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
1307
1308 #if defined(__cplusplus)
1309 }
1310 #endif
1311
1312 #endif /* DRM_FOURCC_H */
1313