1 // dpgeorge: this file taken from w5500/w5500.h and adapted to W5200 2 3 //***************************************************************************** 4 // 5 //! \file w5500.h 6 //! \brief W5500 HAL Header File. 7 //! \version 1.0.0 8 //! \date 2013/10/21 9 //! \par Revision history 10 //! <2013/10/21> 1st Release 11 //! \author MidnightCow 12 //! \copyright 13 //! 14 //! Copyright (c) 2013, WIZnet Co., LTD. 15 //! All rights reserved. 16 //! 17 //! Redistribution and use in source and binary forms, with or without 18 //! modification, are permitted provided that the following conditions 19 //! are met: 20 //! 21 //! * Redistributions of source code must retain the above copyright 22 //! notice, this list of conditions and the following disclaimer. 23 //! * Redistributions in binary form must reproduce the above copyright 24 //! notice, this list of conditions and the following disclaimer in the 25 //! documentation and/or other materials provided with the distribution. 26 //! * Neither the name of the <ORGANIZATION> nor the names of its 27 //! contributors may be used to endorse or promote products derived 28 //! from this software without specific prior written permission. 29 //! 30 //! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 31 //! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 //! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 //! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 34 //! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 35 //! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 36 //! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 37 //! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 38 //! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 //! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 40 //! THE POSSIBILITY OF SUCH DAMAGE. 41 // 42 //***************************************************************************** 43 44 #ifndef _W5200_H_ 45 #define _W5200_H_ 46 47 #include <stdint.h> 48 #include "../wizchip_conf.h" 49 //#include "board.h" 50 51 #define _W5200_IO_BASE_ 0x00000000 52 53 #define WIZCHIP_CREG_ADDR(addr) (_W5200_IO_BASE_ + (addr)) 54 55 #define WIZCHIP_CH_BASE (0x4000) 56 #define WIZCHIP_CH_SIZE (0x100) 57 #define WIZCHIP_SREG_ADDR(sn, addr) (_W5200_IO_BASE_ + WIZCHIP_CH_BASE + (sn) * WIZCHIP_CH_SIZE + (addr)) 58 59 ////////////////////////////// 60 //-------------------------- defgroup --------------------------------- 61 /** 62 * @defgroup W5500 W5500 63 * 64 * @brief WHIZCHIP register defines and I/O functions of @b W5500. 65 * 66 * - @ref WIZCHIP_register : @ref Common_register_group and @ref Socket_register_group 67 * - @ref WIZCHIP_IO_Functions : @ref Basic_IO_function, @ref Common_register_access_function and @ref Socket_register_access_function 68 */ 69 70 71 /** 72 * @defgroup WIZCHIP_register WIZCHIP register 73 * @ingroup W5500 74 * 75 * @brief WHIZCHIP register defines register group of @b W5500. 76 * 77 * - @ref Common_register_group : Common register group 78 * - @ref Socket_register_group : \c SOCKET n register group 79 */ 80 81 82 /** 83 * @defgroup WIZCHIP_IO_Functions WIZCHIP I/O functions 84 * @ingroup W5500 85 * 86 * @brief This supports the basic I/O functions for @ref WIZCHIP_register. 87 * 88 * - <b> Basic I/O function </b> \n 89 * WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() \n\n 90 * 91 * - @ref Common_register_group <b>access functions</b> \n 92 * -# @b Mode \n 93 * getMR(), setMR() 94 * -# @b Interrupt \n 95 * getIR(), setIR(), getIMR(), setIMR(), getSIR(), setSIR(), getSIMR(), setSIMR(), getINTLEVEL(), setINTLEVEL() 96 * -# <b> Network Information </b> \n 97 * getSHAR(), setSHAR(), getGAR(), setGAR(), getSUBR(), setSUBR(), getSIPR(), setSIPR() 98 * -# @b Retransmission \n 99 * getRCR(), setRCR(), getRTR(), setRTR() 100 * -# @b PPPoE \n 101 * getPTIMER(), setPTIMER(), getPMAGIC(), getPMAGIC(), getPSID(), setPSID(), getPHAR(), setPHAR(), getPMRU(), setPMRU() 102 * -# <b> ICMP packet </b>\n 103 * getUIPR(), getUPORTR() 104 * -# @b etc. \n 105 * getPHYCFGR(), setPHYCFGR(), getVERSIONR() \n\n 106 * 107 * - \ref Socket_register_group <b>access functions</b> \n 108 * -# <b> SOCKET control</b> \n 109 * getSn_MR(), setSn_MR(), getSn_CR(), setSn_CR(), getSn_IMR(), setSn_IMR(), getSn_IR(), setSn_IR() 110 * -# <b> SOCKET information</b> \n 111 * getSn_SR(), getSn_DHAR(), setSn_DHAR(), getSn_PORT(), setSn_PORT(), getSn_DIPR(), setSn_DIPR(), getSn_DPORT(), setSn_DPORT() 112 * getSn_MSSR(), setSn_MSSR() 113 * -# <b> SOCKET communication </b> \n 114 * getSn_RXBUF_SIZE(), setSn_RXBUF_SIZE(), getSn_TXBUF_SIZE(), setSn_TXBUF_SIZE() \n 115 * getSn_TX_RD(), getSn_TX_WR(), setSn_TX_WR() \n 116 * getSn_RX_RD(), setSn_RX_RD(), getSn_RX_WR() \n 117 * getSn_TX_FSR(), getSn_RX_RSR(), getSn_KPALVTR(), setSn_KPALVTR() 118 * -# <b> IP header field </b> \n 119 * getSn_FRAG(), setSn_FRAG(), getSn_TOS(), setSn_TOS() \n 120 * getSn_TTL(), setSn_TTL() 121 */ 122 123 124 125 /** 126 * @defgroup Common_register_group Common register 127 * @ingroup WIZCHIP_register 128 * 129 * @brief Common register group\n 130 * It set the basic for the networking\n 131 * It set the configuration such as interrupt, network information, ICMP, etc. 132 * @details 133 * @sa MR : Mode register. 134 * @sa GAR, SUBR, SHAR, SIPR 135 * @sa INTLEVEL, IR, IMR, SIR, SIMR : Interrupt. 136 * @sa RTR, RCR : Data retransmission. 137 * @sa PTIMER, PMAGIC, PHAR, PSID, PMRU : PPPoE. 138 * @sa UIPR, UPORTR : ICMP message. 139 * @sa PHYCFGR, VERSIONR : etc. 140 */ 141 142 143 144 /** 145 * @defgroup Socket_register_group Socket register 146 * @ingroup WIZCHIP_register 147 * 148 * @brief Socket register group.\n 149 * Socket register configures and control SOCKETn which is necessary to data communication. 150 * @details 151 * @sa Sn_MR, Sn_CR, Sn_IR, Sn_IMR : SOCKETn Control 152 * @sa Sn_SR, Sn_PORT, Sn_DHAR, Sn_DIPR, Sn_DPORT : SOCKETn Information 153 * @sa Sn_MSSR, Sn_TOS, Sn_TTL, Sn_KPALVTR, Sn_FRAG : Internet protocol. 154 * @sa Sn_RXBUF_SIZE, Sn_TXBUF_SIZE, Sn_TX_FSR, Sn_TX_RD, Sn_TX_WR, Sn_RX_RSR, Sn_RX_RD, Sn_RX_WR : Data communication 155 */ 156 157 158 159 /** 160 * @defgroup Basic_IO_function Basic I/O function 161 * @ingroup WIZCHIP_IO_Functions 162 * @brief These are basic input/output functions to read values from register or write values to register. 163 */ 164 165 /** 166 * @defgroup Common_register_access_function Common register access functions 167 * @ingroup WIZCHIP_IO_Functions 168 * @brief These are functions to access <b>common registers</b>. 169 */ 170 171 /** 172 * @defgroup Socket_register_access_function Socket register access functions 173 * @ingroup WIZCHIP_IO_Functions 174 * @brief These are functions to access <b>socket registers</b>. 175 */ 176 177 //------------------------------- defgroup end -------------------------------------------- 178 //----------------------------- W5500 Common Registers IOMAP ----------------------------- 179 /** 180 * @ingroup Common_register_group 181 * @brief Mode Register address(R/W)\n 182 * @ref MR is used for S/W reset, ping block mode, PPPoE mode and etc. 183 * @details Each bit of @ref MR defined as follows. 184 * <table> 185 * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> 186 * <tr> <td>RST</td> <td>Reserved</td> <td>WOL</td> <td>PB</td> <td>PPPoE</td> <td>Reserved</td> <td>FARP</td> <td>Reserved</td> </tr> 187 * </table> 188 * - \ref MR_RST : Reset 189 * - \ref MR_WOL : Wake on LAN 190 * - \ref MR_PB : Ping block 191 * - \ref MR_PPPOE : PPPoE mode 192 * - \ref MR_FARP : Force ARP mode 193 */ 194 #define MR WIZCHIP_CREG_ADDR(0x0000) 195 196 /** 197 * @ingroup Common_register_group 198 * @brief Gateway IP Register address(R/W) 199 * @details @ref GAR configures the default gateway address. 200 */ 201 #define GAR WIZCHIP_CREG_ADDR(0x0001) 202 203 /** 204 * @ingroup Common_register_group 205 * @brief Subnet mask Register address(R/W) 206 * @details @ref SUBR configures the subnet mask address. 207 */ 208 #define SUBR WIZCHIP_CREG_ADDR(0x0005) 209 210 /** 211 * @ingroup Common_register_group 212 * @brief Source MAC Register address(R/W) 213 * @details @ref SHAR configures the source hardware address. 214 */ 215 #define SHAR WIZCHIP_CREG_ADDR(0x0009) 216 217 /** 218 * @ingroup Common_register_group 219 * @brief Source IP Register address(R/W) 220 * @details @ref SIPR configures the source IP address. 221 */ 222 #define SIPR WIZCHIP_CREG_ADDR(0x000f) 223 224 /** 225 * @ingroup Common_register_group 226 * @brief Set Interrupt low level timer register address(R/W) 227 * @details @ref INTLEVEL configures the Interrupt Assert Time. 228 */ 229 //#define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 230 231 /** 232 * @ingroup Common_register_group 233 * @brief Interrupt Register(R/W) 234 * @details @ref IR indicates the interrupt status. Each bit of @ref IR will be still until the bit will be written to by the host. 235 * If @ref IR is not equal to x00 INTn PIN is asserted to low until it is x00\n\n 236 * Each bit of @ref IR defined as follows. 237 * <table> 238 * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> 239 * <tr> <td>CONFLICT</td> <td>UNREACH</td> <td>PPPoE</td> <td>MP</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr> 240 * </table> 241 * - \ref IR_CONFLICT : IP conflict 242 * - \ref IR_UNREACH : Destination unreachable 243 * - \ref IR_PPPoE : PPPoE connection close 244 * - \ref IR_MP : Magic packet 245 */ 246 #define IR WIZCHIP_CREG_ADDR(0x0015) 247 248 /** 249 * @ingroup Common_register_group 250 * @brief Interrupt mask register(R/W) 251 * @details @ref IMR is used to mask interrupts. Each bit of @ref IMR corresponds to each bit of @ref IR. 252 * When a bit of @ref IMR is and the corresponding bit of @ref IR is an interrupt will be issued. In other words, 253 * if a bit of @ref IMR is an interrupt will not be issued even if the corresponding bit of @ref IR is \n\n 254 * Each bit of @ref IMR defined as the following. 255 * <table> 256 * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> 257 * <tr> <td>IM_IR7</td> <td>IM_IR6</td> <td>IM_IR5</td> <td>IM_IR4</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr> 258 * </table> 259 * - \ref IM_IR7 : IP Conflict Interrupt Mask 260 * - \ref IM_IR6 : Destination unreachable Interrupt Mask 261 * - \ref IM_IR5 : PPPoE Close Interrupt Mask 262 * - \ref IM_IR4 : Magic Packet Interrupt Mask 263 */ 264 #define IMR WIZCHIP_CREG_ADDR(0x0016) 265 266 /** 267 * @ingroup Common_register_group 268 * @brief Socket Interrupt Register(R/W) 269 * @details @ref SIR indicates the interrupt status of Socket.\n 270 * Each bit of @ref SIR be still until @ref Sn_IR is cleared by the host.\n 271 * If @ref Sn_IR is not equal to x00 the n-th bit of @ref SIR is and INTn PIN is asserted until @ref SIR is x00 */ 272 //#define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 273 274 /** 275 * @ingroup Common_register_group 276 * @brief Socket Interrupt Mask Register(R/W) 277 * @details Each bit of @ref SIMR corresponds to each bit of @ref SIR. 278 * When a bit of @ref SIMR is and the corresponding bit of @ref SIR is Interrupt will be issued. 279 * In other words, if a bit of @ref SIMR is an interrupt will be not issued even if the corresponding bit of @ref SIR is 280 */ 281 //#define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 282 283 /** 284 * @ingroup Common_register_group 285 * @brief Timeout register address( 1 is 100us )(R/W) 286 * @details @ref RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of @ref RTR is x07D0or 000 287 * And so the default timeout period is 200ms(100us X 2000). During the time configured by @ref RTR, W5500 waits for the peer response 288 * to the packet that is transmitted by \ref Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). 289 * If the peer does not respond within the @ref RTR time, W5500 retransmits the packet or issues timeout. 290 */ 291 #define RTR WIZCHIP_CREG_ADDR(0x0017) 292 293 /** 294 * @ingroup Common_register_group 295 * @brief Retry count register(R/W) 296 * @details @ref RCR configures the number of time of retransmission. 297 * When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (@ref Sn_IR[TIMEOUT] = . 298 */ 299 #define RCR WIZCHIP_CREG_ADDR(0x0019) 300 301 /** 302 * @ingroup Common_register_group 303 * @brief PPP LCP Request Timer register in PPPoE mode(R/W) 304 * @details @ref PTIMER configures the time for sending LCP echo request. The unit of time is 25ms. 305 */ 306 #define PTIMER WIZCHIP_CREG_ADDR(0x0028) 307 308 /** 309 * @ingroup Common_register_group 310 * @brief PPP LCP Magic number register in PPPoE mode(R/W) 311 * @details @ref PMAGIC configures the 4bytes magic number to be used in LCP negotiation. 312 */ 313 #define PMAGIC WIZCHIP_CREG_ADDR(0x0029) 314 315 /** 316 * @ingroup Common_register_group 317 * @brief PPP Destination MAC Register address(R/W) 318 * @details @ref PHAR configures the PPPoE server hardware address that is acquired during PPPoE connection process. 319 */ 320 //#define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3)) 321 322 /** 323 * @ingroup Common_register_group 324 * @brief PPP Session Identification Register(R/W) 325 * @details @ref PSID configures the PPPoE sever session ID acquired during PPPoE connection process. 326 */ 327 //#define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 328 329 /** 330 * @ingroup Common_register_group 331 * @brief PPP Maximum Segment Size(MSS) register(R/W) 332 * @details @ref PMRU configures the maximum receive unit of PPPoE. 333 */ 334 //#define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 335 336 /** 337 * @ingroup Common_register_group 338 * @brief Unreachable IP register address in UDP mode(R) 339 * @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number 340 * which socket is not open and @ref UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR indicates 341 * the destination IP address & port number respectively. 342 */ 343 //#define UIPR (_W5500_IO_BASE_ + (0x002a << 8) + (WIZCHIP_CREG_BLOCK << 3)) 344 345 /** 346 * @ingroup Common_register_group 347 * @brief Unreachable Port register address in UDP mode(R) 348 * @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number 349 * which socket is not open and @ref UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR 350 * indicates the destination IP address & port number respectively. 351 */ 352 //#define UPORTR (_W5500_IO_BASE_ + (0x002e << 8) + (WIZCHIP_CREG_BLOCK << 3)) 353 354 /** 355 * @ingroup Common_register_group 356 * @brief PHY Status Register(R/W) 357 * @details @ref PHYCFGR configures PHY operation mode and resets PHY. In addition, @ref PHYCFGR indicates the status of PHY such as duplex, Speed, Link. 358 */ 359 //#define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3)) 360 #define PHYSTATUS WIZCHIP_CREG_ADDR(0x0035) 361 362 // Reserved (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_CREG_BLOCK << 3)) 363 // Reserved (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 364 // Reserved (_W5500_IO_BASE_ + (0x0031 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 365 // Reserved (_W5500_IO_BASE_ + (0x0032 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 366 // Reserved (_W5500_IO_BASE_ + (0x0033 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 367 // Reserved (_W5500_IO_BASE_ + (0x0034 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 368 // Reserved (_W5500_IO_BASE_ + (0x0035 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 369 // Reserved (_W5500_IO_BASE_ + (0x0036 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 370 // Reserved (_W5500_IO_BASE_ + (0x0037 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 371 // Reserved (_W5500_IO_BASE_ + (0x0038 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 372 373 /** 374 * @ingroup Common_register_group 375 * @brief chip version register address(R) 376 * @details @ref VERSIONR always indicates the W5500 version as @b 0x04. 377 */ 378 //#define VERSIONR (_W5200_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3)) 379 380 381 //----------------------------- W5500 Socket Registers IOMAP ----------------------------- 382 /** 383 * @ingroup Socket_register_group 384 * @brief socket Mode register(R/W) 385 * @details @ref Sn_MR configures the option or protocol type of Socket n.\n\n 386 * Each bit of @ref Sn_MR defined as the following. 387 * <table> 388 * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> 389 * <tr> <td>MULTI/MFEN</td> <td>BCASTB</td> <td>ND/MC/MMB</td> <td>UCASTB/MIP6B</td> <td>Protocol[3]</td> <td>Protocol[2]</td> <td>Protocol[1]</td> <td>Protocol[0]</td> </tr> 390 * </table> 391 * - @ref Sn_MR_MULTI : Support UDP Multicasting 392 * - @ref Sn_MR_BCASTB : Broadcast block <b>in UDP Multicasting</b> 393 * - @ref Sn_MR_ND : No Delayed Ack(TCP) flag 394 * - @ref Sn_MR_MC : IGMP version used <b>in UDP mulitcasting</b> 395 * - @ref Sn_MR_MMB : Multicast Blocking <b>in @ref Sn_MR_MACRAW mode</b> 396 * - @ref Sn_MR_UCASTB : Unicast Block <b>in UDP Multicating</b> 397 * - @ref Sn_MR_MIP6B : IPv6 packet Blocking <b>in @ref Sn_MR_MACRAW mode</b> 398 * - <b>Protocol</b> 399 * <table> 400 * <tr> <td><b>Protocol[3]</b></td> <td><b>Protocol[2]</b></td> <td><b>Protocol[1]</b></td> <td><b>Protocol[0]</b></td> <td>@b Meaning</td> </tr> 401 * <tr> <td>0</td> <td>0</td> <td>0</td> <td>0</td> <td>Closed</td> </tr> 402 * <tr> <td>0</td> <td>0</td> <td>0</td> <td>1</td> <td>TCP</td> </tr> 403 * <tr> <td>0</td> <td>0</td> <td>1</td> <td>0</td> <td>UDP</td> </tr> 404 * <tr> <td>0</td> <td>1</td> <td>0</td> <td>0</td> <td>MACRAW</td> </tr> 405 * </table> 406 * - @ref Sn_MR_MACRAW : MAC LAYER RAW SOCK \n 407 * - @ref Sn_MR_UDP : UDP 408 * - @ref Sn_MR_TCP : TCP 409 * - @ref Sn_MR_CLOSE : Unused socket 410 * @note MACRAW mode should be only used in Socket 0. 411 */ 412 #define Sn_MR(N) WIZCHIP_SREG_ADDR(N, 0x0000) 413 414 /** 415 * @ingroup Socket_register_group 416 * @brief Socket command register(R/W) 417 * @details This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE.\n 418 * After W5500 accepts the command, the @ref Sn_CR register is automatically cleared to 0x00. 419 * Even though @ref Sn_CR is cleared to 0x00, the command is still being processed.\n 420 * To check whether the command is completed or not, please check the @ref Sn_IR or @ref Sn_SR. 421 * - @ref Sn_CR_OPEN : Initialize or open socket. 422 * - @ref Sn_CR_LISTEN : Wait connection request in TCP mode(<b>Server mode</b>) 423 * - @ref Sn_CR_CONNECT : Send connection request in TCP mode(<b>Client mode</b>) 424 * - @ref Sn_CR_DISCON : Send closing request in TCP mode. 425 * - @ref Sn_CR_CLOSE : Close socket. 426 * - @ref Sn_CR_SEND : Update TX buffer pointer and send data. 427 * - @ref Sn_CR_SEND_MAC : Send data with MAC address, so without ARP process. 428 * - @ref Sn_CR_SEND_KEEP : Send keep alive message. 429 * - @ref Sn_CR_RECV : Update RX buffer pointer and receive data. 430 */ 431 #define Sn_CR(N) WIZCHIP_SREG_ADDR(N, 0x0001) 432 433 /** 434 * @ingroup Socket_register_group 435 * @brief Socket interrupt register(R) 436 * @details @ref Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving data, timeout).\n 437 * When an interrupt occurs and the corresponding bit of @ref Sn_IMR is the corresponding bit of @ref Sn_IR becomes \n 438 * In order to clear the @ref Sn_IR bit, the host should write the bit to \n 439 * <table> 440 * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> 441 * <tr> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>SEND_OK</td> <td>TIMEOUT</td> <td>RECV</td> <td>DISCON</td> <td>CON</td> </tr> 442 * </table> 443 * - \ref Sn_IR_SENDOK : <b>SEND_OK Interrupt</b> 444 * - \ref Sn_IR_TIMEOUT : <b>TIMEOUT Interrupt</b> 445 * - \ref Sn_IR_RECV : <b>RECV Interrupt</b> 446 * - \ref Sn_IR_DISCON : <b>DISCON Interrupt</b> 447 * - \ref Sn_IR_CON : <b>CON Interrupt</b> 448 */ 449 #define Sn_IR(N) WIZCHIP_SREG_ADDR(N, 0x0002) 450 451 /** 452 * @ingroup Socket_register_group 453 * @brief Socket status register(R) 454 * @details @ref Sn_SR indicates the status of Socket n.\n 455 * The status of Socket n is changed by @ref Sn_CR or some special control packet as SYN, FIN packet in TCP. 456 * @par Normal status 457 * - @ref SOCK_CLOSED : Closed 458 * - @ref SOCK_INIT : Initiate state 459 * - @ref SOCK_LISTEN : Listen state 460 * - @ref SOCK_ESTABLISHED : Success to connect 461 * - @ref SOCK_CLOSE_WAIT : Closing state 462 * - @ref SOCK_UDP : UDP socket 463 * - @ref SOCK_MACRAW : MAC raw mode socket 464 *@par Temporary status during changing the status of Socket n. 465 * - @ref SOCK_SYNSENT : This indicates Socket n sent the connect-request packet (SYN packet) to a peer. 466 * - @ref SOCK_SYNRECV : It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer. 467 * - @ref SOCK_FIN_WAIT : Connection state 468 * - @ref SOCK_CLOSING : Closing state 469 * - @ref SOCK_TIME_WAIT : Closing state 470 * - @ref SOCK_LAST_ACK : Closing state 471 */ 472 #define Sn_SR(N) WIZCHIP_SREG_ADDR(N, 0x0003) 473 474 /** 475 * @ingroup Socket_register_group 476 * @brief source port register(R/W) 477 * @details @ref Sn_PORT configures the source port number of Socket n. 478 * It is valid when Socket n is used in TCP/UPD mode. It should be set before OPEN command is ordered. 479 */ 480 #define Sn_PORT(N) WIZCHIP_SREG_ADDR(N, 0x0004) 481 482 /** 483 * @ingroup Socket_register_group 484 * @brief Peer MAC register address(R/W) 485 * @details @ref Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or 486 * it indicates that it is acquired in ARP-process by CONNECT/SEND command. 487 */ 488 #define Sn_DHAR(N) WIZCHIP_SREG_ADDR(N, 0x0006) 489 490 /** 491 * @ingroup Socket_register_group 492 * @brief Peer IP register address(R/W) 493 * @details @ref Sn_DIPR configures or indicates the destination IP address of Socket n. It is valid when Socket n is used in TCP/UDP mode. 494 * In TCP client mode, it configures an IP address of �TCP serverbefore CONNECT command. 495 * In TCP server mode, it indicates an IP address of �TCP clientafter successfully establishing connection. 496 * In UDP mode, it configures an IP address of peer to be received the UDP packet by SEND or SEND_MAC command. 497 */ 498 #define Sn_DIPR(N) WIZCHIP_SREG_ADDR(N, 0x000c) 499 500 /** 501 * @ingroup Socket_register_group 502 * @brief Peer port register address(R/W) 503 * @details @ref Sn_DPORT configures or indicates the destination port number of Socket n. It is valid when Socket n is used in TCP/UDP mode. 504 * In �TCP clientmode, it configures the listen port number of �TCP serverbefore CONNECT command. 505 * In �TCP Servermode, it indicates the port number of TCP client after successfully establishing connection. 506 * In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command. 507 */ 508 #define Sn_DPORT(N) WIZCHIP_SREG_ADDR(N, 0x0010) 509 510 /** 511 * @ingroup Socket_register_group 512 * @brief Maximum Segment Size(Sn_MSSR0) register address(R/W) 513 * @details @ref Sn_MSSR configures or indicates the MTU(Maximum Transfer Unit) of Socket n. 514 */ 515 #define Sn_MSSR(N) WIZCHIP_SREG_ADDR(N, 0x0012) 516 517 // Reserved (_W5500_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 518 519 /** 520 * @ingroup Socket_register_group 521 * @brief IP Type of Service(TOS) Register(R/W) 522 * @details @ref Sn_TOS configures the TOS(Type Of Service field in IP Header) of Socket n. 523 * It is set before OPEN command. 524 */ 525 #define Sn_TOS(N) WIZCHIP_SREG_ADDR(N, 0x0015) 526 /** 527 * @ingroup Socket_register_group 528 * @brief IP Time to live(TTL) Register(R/W) 529 * @details @ref Sn_TTL configures the TTL(Time To Live field in IP header) of Socket n. 530 * It is set before OPEN command. 531 */ 532 #define Sn_TTL(N) WIZCHIP_SREG_ADDR(N, 0x0016) 533 // Reserved (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 534 // Reserved (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 535 // Reserved (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 536 // Reserved (_W5500_IO_BASE_ + (0x001A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 537 // Reserved (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 538 // Reserved (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 539 // Reserved (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 540 541 /** 542 * @ingroup Socket_register_group 543 * @brief Receive memory size register(R/W) 544 * @details @ref Sn_RXBUF_SIZE configures the RX buffer block size of Socket n. 545 * Socket n RX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes. 546 * If a different size is configured, the data cannot be normally received from a peer. 547 * Although Socket n RX Buffer Block size is initially configured to 2Kbytes, 548 * user can re-configure its size using @ref Sn_RXBUF_SIZE. The total sum of @ref Sn_RXBUF_SIZE can not be exceed 16Kbytes. 549 * When exceeded, the data reception error is occurred. 550 */ 551 #define Sn_RXBUF_SIZE(N) WIZCHIP_SREG_ADDR(N, 0x001e) 552 553 /** 554 * @ingroup Socket_register_group 555 * @brief Transmit memory size register(R/W) 556 * @details @ref Sn_TXBUF_SIZE configures the TX buffer block size of Socket n. Socket n TX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes. 557 * If a different size is configured, the data can�t be normally transmitted to a peer. 558 * Although Socket n TX Buffer Block size is initially configured to 2Kbytes, 559 * user can be re-configure its size using @ref Sn_TXBUF_SIZE. The total sum of @ref Sn_TXBUF_SIZE can not be exceed 16Kbytes. 560 * When exceeded, the data transmission error is occurred. 561 */ 562 #define Sn_TXBUF_SIZE(N) WIZCHIP_SREG_ADDR(N, 0x001f) 563 564 /** 565 * @ingroup Socket_register_group 566 * @brief Transmit free memory size register(R) 567 * @details @ref Sn_TX_FSR indicates the free size of Socket n TX Buffer Block. It is initialized to the configured size by @ref Sn_TXBUF_SIZE. 568 * Data bigger than @ref Sn_TX_FSR should not be saved in the Socket n TX Buffer because the bigger data overwrites the previous saved data not yet sent. 569 * Therefore, check before saving the data to the Socket n TX Buffer, and if data is equal or smaller than its checked size, 570 * transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size, 571 * transmit the data after dividing into the checked size and saving in the Socket n TX buffer. 572 */ 573 #define Sn_TX_FSR(N) WIZCHIP_SREG_ADDR(N, 0x0020) 574 575 /** 576 * @ingroup Socket_register_group 577 * @brief Transmit memory read pointer register address(R) 578 * @details @ref Sn_TX_RD is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP. 579 * After its initialization, it is auto-increased by SEND command. 580 * SEND command transmits the saved data from the current @ref Sn_TX_RD to the @ref Sn_TX_WR in the Socket n TX Buffer. 581 * After transmitting the saved data, the SEND command increases the @ref Sn_TX_RD as same as the @ref Sn_TX_WR. 582 * If its increment value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), 583 * then the carry bit is ignored and will automatically update with the lower 16bits value. 584 */ 585 #define Sn_TX_RD(N) WIZCHIP_SREG_ADDR(N, 0x0022) 586 587 /** 588 * @ingroup Socket_register_group 589 * @brief Transmit memory write pointer register address(R/W) 590 * @details @ref Sn_TX_WR is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP.\n 591 * It should be read or be updated like as follows.\n 592 * 1. Read the starting address for saving the transmitting data.\n 593 * 2. Save the transmitting data from the starting address of Socket n TX buffer.\n 594 * 3. After saving the transmitting data, update @ref Sn_TX_WR to the increased value as many as transmitting data size. 595 * If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs), 596 * then the carry bit is ignored and will automatically update with the lower 16bits value.\n 597 * 4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command 598 */ 599 #define Sn_TX_WR(N) WIZCHIP_SREG_ADDR(N, 0x0024) 600 601 /** 602 * @ingroup Socket_register_group 603 * @brief Received data size register(R) 604 * @details @ref Sn_RX_RSR indicates the data size received and saved in Socket n RX Buffer. 605 * @ref Sn_RX_RSR does not exceed the @ref Sn_RXBUF_SIZE and is calculated as the difference between 606 * �Socket n RX Write Pointer (@ref Sn_RX_WR)and �Socket n RX Read Pointer (@ref Sn_RX_RD) 607 */ 608 #define Sn_RX_RSR(N) WIZCHIP_SREG_ADDR(N, 0x0026) 609 610 /** 611 * @ingroup Socket_register_group 612 * @brief Read point of Receive memory(R/W) 613 * @details @ref Sn_RX_RD is initialized by OPEN command. Make sure to be read or updated as follows.\n 614 * 1. Read the starting save address of the received data.\n 615 * 2. Read data from the starting address of Socket n RX Buffer.\n 616 * 3. After reading the received data, Update @ref Sn_RX_RD to the increased value as many as the reading size. 617 * If the increment value exceeds the maximum value 0xFFFF, that is, is greater than 0x10000 and the carry bit occurs, 618 * update with the lower 16bits value ignored the carry bit.\n 619 * 4. Order RECV command is for notifying the updated @ref Sn_RX_RD to W5500. 620 */ 621 #define Sn_RX_RD(N) WIZCHIP_SREG_ADDR(N, 0x0028) 622 623 /** 624 * @ingroup Socket_register_group 625 * @brief Write point of Receive memory(R) 626 * @details @ref Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception. 627 * If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), 628 * then the carry bit is ignored and will automatically update with the lower 16bits value. 629 */ 630 #define Sn_RX_WR(N) WIZCHIP_SREG_ADDR(N, 0x002a) 631 632 /** 633 * @ingroup Socket_register_group 634 * @brief socket interrupt mask register(R) 635 * @details @ref Sn_IMR masks the interrupt of Socket n. 636 * Each bit corresponds to each bit of @ref Sn_IR. When a Socket n Interrupt is occurred and the corresponding bit of @ref Sn_IMR is 637 * the corresponding bit of @ref Sn_IR becomes When both the corresponding bit of @ref Sn_IMR and @ref Sn_IR are and the n-th bit of @ref IR is 638 * Host is interrupted by asserted INTn PIN to low. 639 */ 640 //#define Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 641 642 /** 643 * @ingroup Socket_register_group 644 * @brief Fragment field value in IP header register(R/W) 645 * @details @ref Sn_FRAG configures the FRAG(Fragment field in IP header). 646 */ 647 //#define Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 648 649 /** 650 * @ingroup Socket_register_group 651 * @brief Keep Alive Timer register(R/W) 652 * @details @ref Sn_KPALVTR configures the transmitting timer of �KEEP ALIVE(KA)packet of SOCKETn. It is valid only in TCP mode, 653 * and ignored in other modes. The time unit is 5s. 654 * KA packet is transmittable after @ref Sn_SR is changed to SOCK_ESTABLISHED and after the data is transmitted or received to/from a peer at least once. 655 * In case of '@ref Sn_KPALVTR > 0', W5500 automatically transmits KA packet after time-period for checking the TCP connection (Auto-keepalive-process). 656 * In case of '@ref Sn_KPALVTR = 0', Auto-keep-alive-process will not operate, 657 * and KA packet can be transmitted by SEND_KEEP command by the host (Manual-keep-alive-process). 658 * Manual-keep-alive-process is ignored in case of '@ref Sn_KPALVTR > 0'. 659 */ 660 //#define Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 661 662 //#define Sn_TSR(N) (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 663 664 665 //----------------------------- W5500 Register values ----------------------------- 666 667 /* MODE register values */ 668 /** 669 * @brief Reset 670 * @details If this bit is All internal registers will be initialized. It will be automatically cleared as after S/W reset. 671 */ 672 #define MR_RST 0x80 673 674 /** 675 * @brief Wake on LAN 676 * @details 0 : Disable WOL mode\n 677 * 1 : Enable WOL mode\n 678 * If WOL mode is enabled and the received magic packet over UDP has been normally processed, the Interrupt PIN (INTn) asserts to low. 679 * When using WOL mode, the UDP Socket should be opened with any source port number. (Refer to Socket n Mode Register (@ref Sn_MR) for opening Socket.) 680 * @note The magic packet over UDP supported by W5500 consists of 6 bytes synchronization stream (xFFFFFFFFFFFF and 681 * 16 times Target MAC address stream in UDP payload. The options such like password are ignored. You can use any UDP source port number for WOL mode. 682 */ 683 #define MR_WOL 0x20 684 685 /** 686 * @brief Ping block 687 * @details 0 : Disable Ping block\n 688 * 1 : Enable Ping block\n 689 * If the bit is it blocks the response to a ping request. 690 */ 691 #define MR_PB 0x10 692 693 /** 694 * @brief Enable PPPoE 695 * @details 0 : DisablePPPoE mode\n 696 * 1 : EnablePPPoE mode\n 697 * If you use ADSL, this bit should be 698 */ 699 #define MR_PPPOE 0x08 700 701 /** 702 * @brief Enable UDP_FORCE_ARP CHECHK 703 * @details 0 : Disable Force ARP mode\n 704 * 1 : Enable Force ARP mode\n 705 * In Force ARP mode, It forces on sending ARP Request whenever data is sent. 706 */ 707 #define MR_FARP 0x02 708 709 /* IR register values */ 710 /** 711 * @brief Check IP conflict. 712 * @details Bit is set as when own source IP address is same with the sender IP address in the received ARP request. 713 */ 714 #define IR_CONFLICT 0x80 715 716 /** 717 * @brief Get the destination unreachable message in UDP sending. 718 * @details When receiving the ICMP (Destination port unreachable) packet, this bit is set as 719 * When this bit is Destination Information such as IP address and Port number may be checked with the corresponding @ref UIPR & @ref UPORTR. 720 */ 721 #define IR_UNREACH 0x40 722 723 /** 724 * @brief Get the PPPoE close message. 725 * @details When PPPoE is disconnected during PPPoE mode, this bit is set. 726 */ 727 #define IR_PPPoE 0x20 728 729 /** 730 * @brief Get the magic packet interrupt. 731 * @details When WOL mode is enabled and receives the magic packet over UDP, this bit is set. 732 */ 733 #define IR_MP 0x10 734 735 736 /* PHYCFGR register value */ 737 #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask. 738 #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value 739 #define PHYCFGR_OPMDC_ALLA (7<<3) 740 #define PHYCFGR_OPMDC_PDOWN (6<<3) 741 #define PHYCFGR_OPMDC_NA (5<<3) 742 #define PHYCFGR_OPMDC_100FA (4<<3) 743 #define PHYCFGR_OPMDC_100F (3<<3) 744 #define PHYCFGR_OPMDC_100H (2<<3) 745 #define PHYCFGR_OPMDC_10F (1<<3) 746 #define PHYCFGR_OPMDC_10H (0<<3) 747 #define PHYCFGR_DPX_FULL (1<<2) 748 #define PHYCFGR_DPX_HALF (0<<2) 749 #define PHYCFGR_SPD_100 (1<<1) 750 #define PHYCFGR_SPD_10 (0<<1) 751 #define PHYCFGR_LNK_ON (1<<0) 752 #define PHYCFGR_LNK_OFF (0<<0) 753 754 // PHYSTATUS register 755 #define PHYSTATUS_POWERDOWN (0x08) 756 #define PHYSTATUS_LINK (0x20) 757 758 /* IMR register values */ 759 /** 760 * @brief IP Conflict Interrupt Mask. 761 * @details 0: Disable IP Conflict Interrupt\n 762 * 1: Enable IP Conflict Interrupt 763 */ 764 #define IM_IR7 0x80 765 766 /** 767 * @brief Destination unreachable Interrupt Mask. 768 * @details 0: Disable Destination unreachable Interrupt\n 769 * 1: Enable Destination unreachable Interrupt 770 */ 771 #define IM_IR6 0x40 772 773 /** 774 * @brief PPPoE Close Interrupt Mask. 775 * @details 0: Disable PPPoE Close Interrupt\n 776 * 1: Enable PPPoE Close Interrupt 777 */ 778 #define IM_IR5 0x20 779 780 /** 781 * @brief Magic Packet Interrupt Mask. 782 * @details 0: Disable Magic Packet Interrupt\n 783 * 1: Enable Magic Packet Interrupt 784 */ 785 #define IM_IR4 0x10 786 787 /* Sn_MR Default values */ 788 /** 789 * @brief Support UDP Multicasting 790 * @details 0 : disable Multicasting\n 791 * 1 : enable Multicasting\n 792 * This bit is applied only during UDP mode(P[3:0] = 010.\n 793 * To use multicasting, @ref Sn_DIPR & @ref Sn_DPORT should be respectively configured with the multicast group IP address & port number 794 * before Socket n is opened by OPEN command of @ref Sn_CR. 795 */ 796 #define Sn_MR_MULTI 0x80 797 798 /** 799 * @brief Broadcast block in UDP Multicasting. 800 * @details 0 : disable Broadcast Blocking\n 801 * 1 : enable Broadcast Blocking\n 802 * This bit blocks to receive broadcasting packet during UDP mode(P[3:0] = 010.\m 803 * In addition, This bit does when MACRAW mode(P[3:0] = 100 804 */ 805 //#define Sn_MR_BCASTB 0x40 806 807 /** 808 * @brief No Delayed Ack(TCP), Multicast flag 809 * @details 0 : Disable No Delayed ACK option\n 810 * 1 : Enable No Delayed ACK option\n 811 * This bit is applied only during TCP mode (P[3:0] = 001.\n 812 * When this bit is It sends the ACK packet without delay as soon as a Data packet is received from a peer.\n 813 * When this bit is It sends the ACK packet after waiting for the timeout time configured by @ref RTR. 814 */ 815 #define Sn_MR_ND 0x20 816 817 /** 818 * @brief Unicast Block in UDP Multicasting 819 * @details 0 : disable Unicast Blocking\n 820 * 1 : enable Unicast Blocking\n 821 * This bit blocks receiving the unicast packet during UDP mode(P[3:0] = 010 and MULTI = 822 */ 823 //#define Sn_MR_UCASTB 0x10 824 825 /** 826 * @brief MAC LAYER RAW SOCK 827 * @details This configures the protocol mode of Socket n. 828 * @note MACRAW mode should be only used in Socket 0. 829 */ 830 #define Sn_MR_MACRAW 0x04 831 832 #define Sn_MR_IPRAW 0x03 /**< IP LAYER RAW SOCK */ 833 834 /** 835 * @brief UDP 836 * @details This configures the protocol mode of Socket n. 837 */ 838 #define Sn_MR_UDP 0x02 839 840 /** 841 * @brief TCP 842 * @details This configures the protocol mode of Socket n. 843 */ 844 #define Sn_MR_TCP 0x01 845 846 /** 847 * @brief Unused socket 848 * @details This configures the protocol mode of Socket n. 849 */ 850 #define Sn_MR_CLOSE 0x00 851 852 /* Sn_MR values used with Sn_MR_MACRAW */ 853 /** 854 * @brief MAC filter enable in @ref Sn_MR_MACRAW mode 855 * @details 0 : disable MAC Filtering\n 856 * 1 : enable MAC Filtering\n 857 * This bit is applied only during MACRAW mode(P[3:0] = 100.\n 858 * When set as W5500 can only receive broadcasting packet or packet sent to itself. 859 * When this bit is W5500 can receive all packets on Ethernet. 860 * If user wants to implement Hybrid TCP/IP stack, 861 * it is recommended that this bit is set as for reducing host overhead to process the all received packets. 862 */ 863 #define Sn_MR_MFEN Sn_MR_MULTI 864 865 /** 866 * @brief Multicast Blocking in @ref Sn_MR_MACRAW mode 867 * @details 0 : using IGMP version 2\n 868 * 1 : using IGMP version 1\n 869 * This bit is applied only during UDP mode(P[3:0] = 010 and MULTI = 870 * It configures the version for IGMP messages (Join/Leave/Report). 871 */ 872 #define Sn_MR_MMB Sn_MR_ND 873 874 /** 875 * @brief IPv6 packet Blocking in @ref Sn_MR_MACRAW mode 876 * @details 0 : disable IPv6 Blocking\n 877 * 1 : enable IPv6 Blocking\n 878 * This bit is applied only during MACRAW mode (P[3:0] = 100. It blocks to receiving the IPv6 packet. 879 */ 880 #define Sn_MR_MIP6B Sn_MR_UCASTB 881 882 /* Sn_MR value used with Sn_MR_UDP & Sn_MR_MULTI */ 883 /** 884 * @brief IGMP version used in UDP mulitcasting 885 * @details 0 : disable Multicast Blocking\n 886 * 1 : enable Multicast Blocking\n 887 * This bit is applied only when MACRAW mode(P[3:0] = 100. It blocks to receive the packet with multicast MAC address. 888 */ 889 #define Sn_MR_MC Sn_MR_ND 890 891 /* Sn_MR alternate values */ 892 /** 893 * @brief For Berkeley Socket API 894 */ 895 #define SOCK_STREAM Sn_MR_TCP 896 897 /** 898 * @brief For Berkeley Socket API 899 */ 900 #define SOCK_DGRAM Sn_MR_UDP 901 902 903 /* Sn_CR values */ 904 /** 905 * @brief Initialize or open socket 906 * @details Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0). 907 * The table below shows the value of @ref Sn_SR corresponding to @ref Sn_MR.\n 908 * <table> 909 * <tr> <td>\b Sn_MR (P[3:0])</td> <td>\b Sn_SR</td> </tr> 910 * <tr> <td>Sn_MR_CLOSE (000</td> <td></td> </tr> 911 * <tr> <td>Sn_MR_TCP (001</td> <td>SOCK_INIT (0x13)</td> </tr> 912 * <tr> <td>Sn_MR_UDP (010</td> <td>SOCK_UDP (0x22)</td> </tr> 913 * <tr> <td>S0_MR_MACRAW (100</td> <td>SOCK_MACRAW (0x02)</td> </tr> 914 * </table> 915 */ 916 #define Sn_CR_OPEN 0x01 917 918 /** 919 * @brief Wait connection request in TCP mode(Server mode) 920 * @details This is valid only in TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP). 921 * In this mode, Socket n operates as a �TCP serverand waits for connection-request (SYN packet) from any �TCP client 922 * The @ref Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN. 923 * When a �TCP clientconnection request is successfully established, 924 * the @ref Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the Sn_IR(0) becomes 925 * But when a �TCP clientconnection request is failed, Sn_IR(3) becomes and the status of @ref Sn_SR changes to SOCK_CLOSED. 926 */ 927 #define Sn_CR_LISTEN 0x02 928 929 /** 930 * @brief Send connection request in TCP mode(Client mode) 931 * @details To connect, a connect-request (SYN packet) is sent to b>TCP server</b>configured by @ref Sn_DIPR & Sn_DPORT(destination address & port). 932 * If the connect-request is successful, the @ref Sn_SR is changed to @ref SOCK_ESTABLISHED and the Sn_IR(0) becomes \n\n 933 * The connect-request fails in the following three cases.\n 934 * 1. When a @b ARPTO occurs (@ref Sn_IR[3] = ) because destination hardware address is not acquired through the ARP-process.\n 935 * 2. When a @b SYN/ACK packet is not received and @b TCPTO (Sn_IR(3) = )\n 936 * 3. When a @b RST packet is received instead of a @b SYN/ACK packet. In these cases, @ref Sn_SR is changed to @ref SOCK_CLOSED. 937 * @note This is valid only in TCP mode and operates when Socket n acts as b>TCP client</b> 938 */ 939 #define Sn_CR_CONNECT 0x04 940 941 /** 942 * @brief Send closing request in TCP mode 943 * @details Regardless of b>TCP server</b>or b>TCP client</b> the DISCON command processes the disconnect-process (b>Active close</b>or b>Passive close</b>.\n 944 * @par Active close 945 * it transmits disconnect-request(FIN packet) to the connected peer\n 946 * @par Passive close 947 * When FIN packet is received from peer, a FIN packet is replied back to the peer.\n 948 * @details When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), @ref Sn_SR is changed to @ref SOCK_CLOSED.\n 949 * Otherwise, TCPTO occurs (Sn_IR(3)=)= and then @ref Sn_SR is changed to @ref SOCK_CLOSED. 950 * @note Valid only in TCP mode. 951 */ 952 #define Sn_CR_DISCON 0x08 953 954 /** 955 * @brief Close socket 956 * @details Sn_SR is changed to @ref SOCK_CLOSED. 957 */ 958 #define Sn_CR_CLOSE 0x10 959 960 /** 961 * @brief Update TX buffer pointer and send data 962 * @details SEND transmits all the data in the Socket n TX buffer.\n 963 * For more details, please refer to Socket n TX Free Size Register (@ref Sn_TX_FSR), Socket n, 964 * TX Write Pointer Register(@ref Sn_TX_WR), and Socket n TX Read Pointer Register(@ref Sn_TX_RD). 965 */ 966 #define Sn_CR_SEND 0x20 967 968 /** 969 * @brief Send data with MAC address, so without ARP process 970 * @details The basic operation is same as SEND.\n 971 * Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).\n 972 * But SEND_MAC transmits data without the automatic ARP-process.\n 973 * In this case, the destination hardware address is acquired from @ref Sn_DHAR configured by host, instead of APR-process. 974 * @note Valid only in UDP mode. 975 */ 976 #define Sn_CR_SEND_MAC 0x21 977 978 /** 979 * @brief Send keep alive message 980 * @details It checks the connection status by sending 1byte keep-alive packet.\n 981 * If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur. 982 * @note Valid only in TCP mode. 983 */ 984 #define Sn_CR_SEND_KEEP 0x22 985 986 /** 987 * @brief Update RX buffer pointer and receive data 988 * @details RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (@ref Sn_RX_RD).\n 989 * For more details, refer to Socket n RX Received Size Register (@ref Sn_RX_RSR), Socket n RX Write Pointer Register (@ref Sn_RX_WR), 990 * and Socket n RX Read Pointer Register (@ref Sn_RX_RD). 991 */ 992 #define Sn_CR_RECV 0x40 993 994 /* Sn_IR values */ 995 /** 996 * @brief SEND_OK Interrupt 997 * @details This is issued when SEND command is completed. 998 */ 999 #define Sn_IR_SENDOK 0x10 1000 1001 /** 1002 * @brief TIMEOUT Interrupt 1003 * @details This is issued when ARPTO or TCPTO occurs. 1004 */ 1005 #define Sn_IR_TIMEOUT 0x08 1006 1007 /** 1008 * @brief RECV Interrupt 1009 * @details This is issued whenever data is received from a peer. 1010 */ 1011 #define Sn_IR_RECV 0x04 1012 1013 /** 1014 * @brief DISCON Interrupt 1015 * @details This is issued when FIN or FIN/ACK packet is received from a peer. 1016 */ 1017 #define Sn_IR_DISCON 0x02 1018 1019 /** 1020 * @brief CON Interrupt 1021 * @details This is issued one time when the connection with peer is successful and then @ref Sn_SR is changed to @ref SOCK_ESTABLISHED. 1022 */ 1023 #define Sn_IR_CON 0x01 1024 1025 /* Sn_SR values */ 1026 /** 1027 * @brief Closed 1028 * @details This indicates that Socket n is released.\N 1029 * When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to @ref SOCK_CLOSED regardless of previous status. 1030 */ 1031 #define SOCK_CLOSED 0x00 1032 1033 /** 1034 * @brief Initiate state 1035 * @details This indicates Socket n is opened with TCP mode.\N 1036 * It is changed to @ref SOCK_INIT when Sn_MR(P[3:0]) = 001and OPEN command is ordered.\N 1037 * After @ref SOCK_INIT, user can use LISTEN /CONNECT command. 1038 */ 1039 #define SOCK_INIT 0x13 1040 1041 /** 1042 * @brief Listen state 1043 * @details This indicates Socket n is operating as b>TCP server</b>mode and waiting for connection-request (SYN packet) from a peer (b>TCP client</b>.\n 1044 * It will change to @ref SOCK_ESTALBLISHED when the connection-request is successfully accepted.\n 1045 * Otherwise it will change to @ref SOCK_CLOSED after TCPTO occurred (Sn_IR(TIMEOUT) = . 1046 */ 1047 #define SOCK_LISTEN 0x14 1048 1049 /** 1050 * @brief Connection state 1051 * @details This indicates Socket n sent the connect-request packet (SYN packet) to a peer.\n 1052 * It is temporarily shown when @ref Sn_SR is changed from @ref SOCK_INIT to @ref SOCK_ESTABLISHED by CONNECT command.\n 1053 * If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to @ref SOCK_ESTABLISHED.\n 1054 * Otherwise, it changes to @ref SOCK_CLOSED after TCPTO (@ref Sn_IR[TIMEOUT] = is occurred. 1055 */ 1056 #define SOCK_SYNSENT 0x15 1057 1058 /** 1059 * @brief Connection state 1060 * @details It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.\n 1061 * If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to @ref SOCK_ESTABLISHED. \n 1062 * If not, it changes to @ref SOCK_CLOSED after timeout occurs (@ref Sn_IR[TIMEOUT] = . 1063 */ 1064 #define SOCK_SYNRECV 0x16 1065 1066 /** 1067 * @brief Success to connect 1068 * @details This indicates the status of the connection of Socket n.\n 1069 * It changes to @ref SOCK_ESTABLISHED when the b>TCP SERVER</b>processed the SYN packet from the b>TCP CLIENT</b>during @ref SOCK_LISTEN, or 1070 * when the CONNECT command is successful.\n 1071 * During @ref SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command. 1072 */ 1073 #define SOCK_ESTABLISHED 0x17 1074 1075 /** 1076 * @brief Closing state 1077 * @details These indicate Socket n is closing.\n 1078 * These are shown in disconnect-process such as active-close and passive-close.\n 1079 * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED. 1080 */ 1081 #define SOCK_FIN_WAIT 0x18 1082 1083 /** 1084 * @brief Closing state 1085 * @details These indicate Socket n is closing.\n 1086 * These are shown in disconnect-process such as active-close and passive-close.\n 1087 * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED. 1088 */ 1089 #define SOCK_CLOSING 0x1A 1090 1091 /** 1092 * @brief Closing state 1093 * @details These indicate Socket n is closing.\n 1094 * These are shown in disconnect-process such as active-close and passive-close.\n 1095 * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED. 1096 */ 1097 #define SOCK_TIME_WAIT 0x1B 1098 1099 /** 1100 * @brief Closing state 1101 * @details This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.\n 1102 * This is half-closing status, and data can be transferred.\n 1103 * For full-closing, DISCON command is used. But For just-closing, CLOSE command is used. 1104 */ 1105 #define SOCK_CLOSE_WAIT 0x1C 1106 1107 /** 1108 * @brief Closing state 1109 * @details This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.\n 1110 * It changes to @ref SOCK_CLOSED when Socket n received the response successfully, or when timeout occurs (@ref Sn_IR[TIMEOUT] = . 1111 */ 1112 #define SOCK_LAST_ACK 0x1D 1113 1114 /** 1115 * @brief UDP socket 1116 * @details This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0]) = 010.\n 1117 * It changes to SOCK_UPD when Sn_MR(P[3:0]) = 010 and OPEN command is ordered.\n 1118 * Unlike TCP mode, data can be transfered without the connection-process. 1119 */ 1120 #define SOCK_UDP 0x22 1121 1122 //#define SOCK_IPRAW 0x32 /**< IP raw mode socket */ 1123 1124 /** 1125 * @brief MAC raw mode socket 1126 * @details This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = 100and is valid only in Socket 0.\n 1127 * It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100and OPEN command is ordered.\n 1128 * Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process. 1129 */ 1130 #define SOCK_MACRAW 0x42 1131 1132 //#define SOCK_PPPOE 0x5F 1133 1134 /* IP PROTOCOL */ 1135 #define IPPROTO_IP 0 //< Dummy for IP 1136 #define IPPROTO_ICMP 1 //< Control message protocol 1137 #define IPPROTO_IGMP 2 //< Internet group management protocol 1138 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated) 1139 #define IPPROTO_TCP 6 //< TCP 1140 #define IPPROTO_PUP 12 //< PUP 1141 #define IPPROTO_UDP 17 //< UDP 1142 #define IPPROTO_IDP 22 //< XNS idp 1143 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol 1144 #define IPPROTO_RAW 255 //< Raw IP packet 1145 1146 1147 /** 1148 * @brief Enter a critical section 1149 * 1150 * @details It is provided to protect your shared code which are executed without distribution. \n \n 1151 * 1152 * In non-OS environment, It can be just implemented by disabling whole interrupt.\n 1153 * In OS environment, You can replace it to critical section api supported by OS. 1154 * 1155 * \sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() 1156 * \sa WIZCHIP_CRITICAL_EXIT() 1157 */ 1158 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter() 1159 1160 /** 1161 * @brief Exit a critical section 1162 * 1163 * @details It is provided to protect your shared code which are executed without distribution. \n\n 1164 * 1165 * In non-OS environment, It can be just implemented by disabling whole interrupt. \n 1166 * In OS environment, You can replace it to critical section api supported by OS. 1167 * 1168 * @sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() 1169 * @sa WIZCHIP_CRITICAL_ENTER() 1170 */ 1171 #ifdef _exit 1172 #undef _exit 1173 #endif 1174 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit() 1175 1176 1177 1178 //////////////////////// 1179 // Basic I/O Function // 1180 //////////////////////// 1181 1182 /** 1183 * @ingroup Basic_IO_function 1184 * @brief It reads 1 byte value from a register. 1185 * @param AddrSel Register address 1186 * @return The value of register 1187 */ 1188 uint8_t WIZCHIP_READ (uint32_t AddrSel); 1189 1190 /** 1191 * @ingroup Basic_IO_function 1192 * @brief It writes 1 byte value to a register. 1193 * @param AddrSel Register address 1194 * @param wb Write data 1195 * @return void 1196 */ 1197 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb ); 1198 1199 /** 1200 * @ingroup Basic_IO_function 1201 * @brief It reads sequence data from registers. 1202 * @param AddrSel Register address 1203 * @param pBuf Pointer buffer to read data 1204 * @param len Data length 1205 */ 1206 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len); 1207 1208 /** 1209 * @ingroup Basic_IO_function 1210 * @brief It writes sequence data to registers. 1211 * @param AddrSel Register address 1212 * @param pBuf Pointer buffer to write data 1213 * @param len Data length 1214 */ 1215 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); 1216 1217 ///////////////////////////////// 1218 // Common Register I/O function // 1219 ///////////////////////////////// 1220 /** 1221 * @ingroup Common_register_access_function 1222 * @brief Set Mode Register 1223 * @param (uint8_t)mr The value to be set. 1224 * @sa getMR() 1225 */ 1226 #define setMR(mr) \ 1227 WIZCHIP_WRITE(MR,mr) 1228 1229 1230 /** 1231 * @ingroup Common_register_access_function 1232 * @brief Get Mode Register 1233 * @return uint8_t. The value of Mode register. 1234 * @sa setMR() 1235 */ 1236 #define getMR() \ 1237 WIZCHIP_READ(MR) 1238 1239 /** 1240 * @ingroup Common_register_access_function 1241 * @brief Set gateway IP address 1242 * @param (uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes. 1243 * @sa getGAR() 1244 */ 1245 #define setGAR(gar) \ 1246 WIZCHIP_WRITE_BUF(GAR,gar,4) 1247 1248 /** 1249 * @ingroup Common_register_access_function 1250 * @brief Get gateway IP address 1251 * @param (uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes. 1252 * @sa setGAR() 1253 */ 1254 #define getGAR(gar) \ 1255 WIZCHIP_READ_BUF(GAR,gar,4) 1256 1257 /** 1258 * @ingroup Common_register_access_function 1259 * @brief Set subnet mask address 1260 * @param (uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes. 1261 * @sa getSUBR() 1262 */ 1263 #define setSUBR(subr) \ 1264 WIZCHIP_WRITE_BUF(SUBR, subr,4) 1265 1266 1267 /** 1268 * @ingroup Common_register_access_function 1269 * @brief Get subnet mask address 1270 * @param (uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes. 1271 * @sa setSUBR() 1272 */ 1273 #define getSUBR(subr) \ 1274 WIZCHIP_READ_BUF(SUBR, subr, 4) 1275 1276 /** 1277 * @ingroup Common_register_access_function 1278 * @brief Set local MAC address 1279 * @param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes. 1280 * @sa getSHAR() 1281 */ 1282 #define setSHAR(shar) \ 1283 WIZCHIP_WRITE_BUF(SHAR, shar, 6) 1284 1285 /** 1286 * @ingroup Common_register_access_function 1287 * @brief Get local MAC address 1288 * @param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes. 1289 * @sa setSHAR() 1290 */ 1291 #define getSHAR(shar) \ 1292 WIZCHIP_READ_BUF(SHAR, shar, 6) 1293 1294 /** 1295 * @ingroup Common_register_access_function 1296 * @brief Set local IP address 1297 * @param (uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes. 1298 * @sa getSIPR() 1299 */ 1300 #define setSIPR(sipr) \ 1301 WIZCHIP_WRITE_BUF(SIPR, sipr, 4) 1302 1303 /** 1304 * @ingroup Common_register_access_function 1305 * @brief Get local IP address 1306 * @param (uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes. 1307 * @sa setSIPR() 1308 */ 1309 #define getSIPR(sipr) \ 1310 WIZCHIP_READ_BUF(SIPR, sipr, 4) 1311 1312 /** 1313 * @ingroup Common_register_access_function 1314 * @brief Set INTLEVEL register 1315 * @param (uint16_t)intlevel Value to set @ref INTLEVEL register. 1316 * @sa getINTLEVEL() 1317 */ 1318 // dpgeorge: not yet implemented 1319 #define setINTLEVEL(intlevel) (void)intlevel 1320 #if 0 1321 #define setINTLEVEL(intlevel) {\ 1322 WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \ 1323 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \ 1324 } 1325 #endif 1326 1327 1328 /** 1329 * @ingroup Common_register_access_function 1330 * @brief Get INTLEVEL register 1331 * @return uint16_t. Value of @ref INTLEVEL register. 1332 * @sa setINTLEVEL() 1333 */ 1334 // dpgeorge: not yet implemented 1335 #define getINTLEVEL() (0) 1336 #if 0 1337 #define getINTLEVEL() \ 1338 ((WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1))) 1339 #endif 1340 1341 /** 1342 * @ingroup Common_register_access_function 1343 * @brief Set @ref IR register 1344 * @param (uint8_t)ir Value to set @ref IR register. 1345 * @sa getIR() 1346 */ 1347 #define setIR(ir) \ 1348 WIZCHIP_WRITE(IR, (ir & 0xF0)) 1349 1350 /** 1351 * @ingroup Common_register_access_function 1352 * @brief Get @ref IR register 1353 * @return uint8_t. Value of @ref IR register. 1354 * @sa setIR() 1355 */ 1356 #define getIR() \ 1357 (WIZCHIP_READ(IR) & 0xF0) 1358 /** 1359 * @ingroup Common_register_access_function 1360 * @brief Set @ref IMR register 1361 * @param (uint8_t)imr Value to set @ref IMR register. 1362 * @sa getIMR() 1363 */ 1364 #define setIMR(imr) \ 1365 WIZCHIP_WRITE(IMR, imr) 1366 1367 /** 1368 * @ingroup Common_register_access_function 1369 * @brief Get @ref IMR register 1370 * @return uint8_t. Value of @ref IMR register. 1371 * @sa setIMR() 1372 */ 1373 #define getIMR() \ 1374 WIZCHIP_READ(IMR) 1375 1376 1377 /** 1378 * @ingroup Common_register_access_function 1379 * @brief Set @ref SIR register 1380 * @param (uint8_t)sir Value to set @ref SIR register. 1381 * @sa getSIR() 1382 */ 1383 // dpgeorge: not yet implemented 1384 #define setSIR(sir) ((void)sir) 1385 #if 0 1386 #define setSIR(sir) \ 1387 WIZCHIP_WRITE(SIR, sir) 1388 #endif 1389 1390 /** 1391 * @ingroup Common_register_access_function 1392 * @brief Get @ref SIR register 1393 * @return uint8_t. Value of @ref SIR register. 1394 * @sa setSIR() 1395 */ 1396 // dpgeorge: not yet implemented 1397 #define getSIR() (0) 1398 #if 0 1399 #define getSIR() \ 1400 WIZCHIP_READ(SIR) 1401 #endif 1402 1403 /** 1404 * @ingroup Common_register_access_function 1405 * @brief Set @ref SIMR register 1406 * @param (uint8_t)simr Value to set @ref SIMR register. 1407 * @sa getSIMR() 1408 */ 1409 // dpgeorge: not yet implemented 1410 #define setSIMR(simr) ((void)simr) 1411 #if 0 1412 #define setSIMR(simr) \ 1413 WIZCHIP_WRITE(SIMR, simr) 1414 #endif 1415 1416 /** 1417 * @ingroup Common_register_access_function 1418 * @brief Get @ref SIMR register 1419 * @return uint8_t. Value of @ref SIMR register. 1420 * @sa setSIMR() 1421 */ 1422 // dpgeorge: not yet implemented 1423 #define getSIMR() (0) 1424 #if 0 1425 #define getSIMR() \ 1426 WIZCHIP_READ(SIMR) 1427 #endif 1428 1429 /** 1430 * @ingroup Common_register_access_function 1431 * @brief Set @ref RTR register 1432 * @param (uint16_t)rtr Value to set @ref RTR register. 1433 * @sa getRTR() 1434 */ 1435 #define setRTR(rtr) {\ 1436 WIZCHIP_WRITE(RTR, (uint8_t)(rtr >> 8)); \ 1437 WIZCHIP_WRITE(RTR + 1, (uint8_t) rtr); \ 1438 } 1439 1440 /** 1441 * @ingroup Common_register_access_function 1442 * @brief Get @ref RTR register 1443 * @return uint16_t. Value of @ref RTR register. 1444 * @sa setRTR() 1445 */ 1446 #define getRTR() \ 1447 ((WIZCHIP_READ(RTR) << 8) + WIZCHIP_READ(RTR + 1)) 1448 1449 /** 1450 * @ingroup Common_register_access_function 1451 * @brief Set @ref RCR register 1452 * @param (uint8_t)rcr Value to set @ref RCR register. 1453 * @sa getRCR() 1454 */ 1455 #define setRCR(rcr) \ 1456 WIZCHIP_WRITE(RCR, rcr) 1457 1458 /** 1459 * @ingroup Common_register_access_function 1460 * @brief Get @ref RCR register 1461 * @return uint8_t. Value of @ref RCR register. 1462 * @sa setRCR() 1463 */ 1464 #define getRCR() \ 1465 WIZCHIP_READ(RCR) 1466 1467 //================================================== test done =========================================================== 1468 1469 /** 1470 * @ingroup Common_register_access_function 1471 * @brief Set @ref PTIMER register 1472 * @param (uint8_t)ptimer Value to set @ref PTIMER register. 1473 * @sa getPTIMER() 1474 */ 1475 #define setPTIMER(ptimer) \ 1476 WIZCHIP_WRITE(PTIMER, ptimer) 1477 1478 /** 1479 * @ingroup Common_register_access_function 1480 * @brief Get @ref PTIMER register 1481 * @return uint8_t. Value of @ref PTIMER register. 1482 * @sa setPTIMER() 1483 */ 1484 #define getPTIMER() \ 1485 WIZCHIP_READ(PTIMER) 1486 1487 /** 1488 * @ingroup Common_register_access_function 1489 * @brief Set @ref PMAGIC register 1490 * @param (uint8_t)pmagic Value to set @ref PMAGIC register. 1491 * @sa getPMAGIC() 1492 */ 1493 #define setPMAGIC(pmagic) \ 1494 WIZCHIP_WRITE(PMAGIC, pmagic) 1495 1496 /** 1497 * @ingroup Common_register_access_function 1498 * @brief Get @ref PMAGIC register 1499 * @return uint8_t. Value of @ref PMAGIC register. 1500 * @sa setPMAGIC() 1501 */ 1502 #define getPMAGIC() \ 1503 WIZCHIP_READ(PMAGIC) 1504 1505 /** 1506 * @ingroup Common_register_access_function 1507 * @brief Set PHAR address 1508 * @param (uint8_t*)phar Pointer variable to set PPP destination MAC register address. It should be allocated 6 bytes. 1509 * @sa getPHAR() 1510 */ 1511 #if 0 1512 #define setPHAR(phar) \ 1513 WIZCHIP_WRITE_BUF(PHAR, phar, 6) 1514 1515 /** 1516 * @ingroup Common_register_access_function 1517 * @brief Get local IP address 1518 * @param (uint8_t*)phar Pointer variable to PPP destination MAC register address. It should be allocated 6 bytes. 1519 * @sa setPHAR() 1520 */ 1521 #define getPHAR(phar) \ 1522 WIZCHIP_READ_BUF(PHAR, phar, 6) 1523 1524 /** 1525 * @ingroup Common_register_access_function 1526 * @brief Set @ref PSID register 1527 * @param (uint16_t)psid Value to set @ref PSID register. 1528 * @sa getPSID() 1529 */ 1530 #define setPSID(psid) {\ 1531 WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); \ 1532 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \ 1533 } 1534 1535 /** 1536 * @ingroup Common_register_access_function 1537 * @brief Get @ref PSID register 1538 * @return uint16_t. Value of @ref PSID register. 1539 * @sa setPSID() 1540 */ 1541 //uint16_t getPSID(void); 1542 #define getPSID() \ 1543 ((WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1))) 1544 1545 /** 1546 * @ingroup Common_register_access_function 1547 * @brief Set @ref PMRU register 1548 * @param (uint16_t)pmru Value to set @ref PMRU register. 1549 * @sa getPMRU() 1550 */ 1551 #define setPMRU(pmru) { \ 1552 WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); \ 1553 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \ 1554 } 1555 1556 /** 1557 * @ingroup Common_register_access_function 1558 * @brief Get @ref PMRU register 1559 * @return uint16_t. Value of @ref PMRU register. 1560 * @sa setPMRU() 1561 */ 1562 #define getPMRU() \ 1563 ((WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1))) 1564 1565 /** 1566 * @ingroup Common_register_access_function 1567 * @brief Get unreachable IP address 1568 * @param (uint8_t*)uipr Pointer variable to get unreachable IP address. It should be allocated 4 bytes. 1569 */ 1570 #define getUIPR(uipr) \ 1571 WIZCHIP_READ_BUF(UIPR,uipr,6) 1572 1573 /** 1574 * @ingroup Common_register_access_function 1575 * @brief Get @ref UPORTR register 1576 * @return uint16_t. Value of @ref UPORTR register. 1577 */ 1578 #define getUPORTR() \ 1579 ((WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1))) 1580 1581 /** 1582 * @ingroup Common_register_access_function 1583 * @brief Set @ref PHYCFGR register 1584 * @param (uint8_t)phycfgr Value to set @ref PHYCFGR register. 1585 * @sa getPHYCFGR() 1586 */ 1587 #define setPHYCFGR(phycfgr) \ 1588 WIZCHIP_WRITE(PHYCFGR, phycfgr) 1589 #endif 1590 1591 /** 1592 * @ingroup Common_register_access_function 1593 * @brief Get @ref PHYCFGR register 1594 * @return uint8_t. Value of @ref PHYCFGR register. 1595 * @sa setPHYCFGR() 1596 */ 1597 #define getPHYSTATUS() \ 1598 WIZCHIP_READ(PHYSTATUS) 1599 1600 /** 1601 * @ingroup Common_register_access_function 1602 * @brief Get @ref VERSIONR register 1603 * @return uint8_t. Value of @ref VERSIONR register. 1604 */ 1605 /* 1606 #define getVERSIONR() \ 1607 WIZCHIP_READ(VERSIONR) 1608 */ 1609 ///////////////////////////////////// 1610 1611 /////////////////////////////////// 1612 // Socket N register I/O function // 1613 /////////////////////////////////// 1614 /** 1615 * @ingroup Socket_register_access_function 1616 * @brief Set @ref Sn_MR register 1617 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1618 * @param (uint8_t)mr Value to set @ref Sn_MR 1619 * @sa getSn_MR() 1620 */ 1621 #define setSn_MR(sn, mr) \ 1622 WIZCHIP_WRITE(Sn_MR(sn),mr) 1623 1624 /** 1625 * @ingroup Socket_register_access_function 1626 * @brief Get @ref Sn_MR register 1627 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1628 * @return uint8_t. Value of @ref Sn_MR. 1629 * @sa setSn_MR() 1630 */ 1631 #define getSn_MR(sn) \ 1632 WIZCHIP_READ(Sn_MR(sn)) 1633 1634 /** 1635 * @ingroup Socket_register_access_function 1636 * @brief Set @ref Sn_CR register 1637 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1638 * @param (uint8_t)cr Value to set @ref Sn_CR 1639 * @sa getSn_CR() 1640 */ 1641 #define setSn_CR(sn, cr) \ 1642 WIZCHIP_WRITE(Sn_CR(sn), cr) 1643 1644 /** 1645 * @ingroup Socket_register_access_function 1646 * @brief Get @ref Sn_CR register 1647 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1648 * @return uint8_t. Value of @ref Sn_CR. 1649 * @sa setSn_CR() 1650 */ 1651 #define getSn_CR(sn) \ 1652 WIZCHIP_READ(Sn_CR(sn)) 1653 1654 /** 1655 * @ingroup Socket_register_access_function 1656 * @brief Set @ref Sn_IR register 1657 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1658 * @param (uint8_t)ir Value to set @ref Sn_IR 1659 * @sa getSn_IR() 1660 */ 1661 #define setSn_IR(sn, ir) \ 1662 WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F)) 1663 1664 /** 1665 * @ingroup Socket_register_access_function 1666 * @brief Get @ref Sn_IR register 1667 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1668 * @return uint8_t. Value of @ref Sn_IR. 1669 * @sa setSn_IR() 1670 */ 1671 #define getSn_IR(sn) \ 1672 (WIZCHIP_READ(Sn_IR(sn)) & 0x1F) 1673 1674 /** 1675 * @ingroup Socket_register_access_function 1676 * @brief Set @ref Sn_IMR register 1677 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1678 * @param (uint8_t)imr Value to set @ref Sn_IMR 1679 * @sa getSn_IMR() 1680 */ 1681 // dpgeorge: not yet implemented 1682 #define setSn_IMR(sn, imr) (void)sn; (void)imr 1683 #if 0 1684 #define setSn_IMR(sn, imr) \ 1685 WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F)) 1686 #endif 1687 1688 /** 1689 * @ingroup Socket_register_access_function 1690 * @brief Get @ref Sn_IMR register 1691 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1692 * @return uint8_t. Value of @ref Sn_IMR. 1693 * @sa setSn_IMR() 1694 */ 1695 // dpgeorge: not yet implemented 1696 #define getSn_IMR(sn) (0) 1697 #if 0 1698 #define getSn_IMR(sn) \ 1699 (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F) 1700 #endif 1701 1702 /** 1703 * @ingroup Socket_register_access_function 1704 * @brief Get @ref Sn_SR register 1705 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1706 * @return uint8_t. Value of @ref Sn_SR. 1707 */ 1708 #define getSn_SR(sn) \ 1709 WIZCHIP_READ(Sn_SR(sn)) 1710 1711 /** 1712 * @ingroup Socket_register_access_function 1713 * @brief Set @ref Sn_PORT register 1714 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1715 * @param (uint16_t)port Value to set @ref Sn_PORT. 1716 * @sa getSn_PORT() 1717 */ 1718 #define setSn_PORT(sn, port) { \ 1719 WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \ 1720 WIZCHIP_WRITE(Sn_PORT(sn) + 1, (uint8_t) port); \ 1721 } 1722 1723 /** 1724 * @ingroup Socket_register_access_function 1725 * @brief Get @ref Sn_PORT register 1726 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1727 * @return uint16_t. Value of @ref Sn_PORT. 1728 * @sa setSn_PORT() 1729 */ 1730 #define getSn_PORT(sn) \ 1731 ((WIZCHIP_READ(Sn_PORT(sn)) << 8) | WIZCHIP_READ(Sn_PORT(sn) + 1)) 1732 1733 /** 1734 * @ingroup Socket_register_access_function 1735 * @brief Set @ref Sn_DHAR register 1736 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1737 * @param (uint8_t*)dhar Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes. 1738 * @sa getSn_DHAR() 1739 */ 1740 #define setSn_DHAR(sn, dhar) \ 1741 WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6) 1742 1743 /** 1744 * @ingroup Socket_register_access_function 1745 * @brief Get @ref Sn_MR register 1746 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1747 * @param (uint8_t*)dhar Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes. 1748 * @sa setSn_DHAR() 1749 */ 1750 #define getSn_DHAR(sn, dhar) \ 1751 WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6) 1752 1753 /** 1754 * @ingroup Socket_register_access_function 1755 * @brief Set @ref Sn_DIPR register 1756 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1757 * @param (uint8_t*)dipr Pointer variable to set socket n destination IP address. It should be allocated 4 bytes. 1758 * @sa getSn_DIPR() 1759 */ 1760 #define setSn_DIPR(sn, dipr) \ 1761 WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4) 1762 1763 /** 1764 * @ingroup Socket_register_access_function 1765 * @brief Get @ref Sn_DIPR register 1766 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1767 * @param (uint8_t*)dipr Pointer variable to get socket n destination IP address. It should be allocated 4 bytes. 1768 * @sa SetSn_DIPR() 1769 */ 1770 #define getSn_DIPR(sn, dipr) \ 1771 WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4) 1772 1773 /** 1774 * @ingroup Socket_register_access_function 1775 * @brief Set @ref Sn_DPORT register 1776 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1777 * @param (uint16_t)dport Value to set @ref Sn_DPORT 1778 * @sa getSn_DPORT() 1779 */ 1780 #define setSn_DPORT(sn, dport) { \ 1781 WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \ 1782 WIZCHIP_WRITE(Sn_DPORT(sn) + 1, (uint8_t) dport); \ 1783 } 1784 1785 /** 1786 * @ingroup Socket_register_access_function 1787 * @brief Get @ref Sn_DPORT register 1788 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1789 * @return uint16_t. Value of @ref Sn_DPORT. 1790 * @sa setSn_DPORT() 1791 */ 1792 #define getSn_DPORT(sn) \ 1793 ((WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ((Sn_DPORT(sn)+1))) 1794 1795 /** 1796 * @ingroup Socket_register_access_function 1797 * @brief Set @ref Sn_MSSR register 1798 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1799 * @param (uint16_t)mss Value to set @ref Sn_MSSR 1800 * @sa setSn_MSSR() 1801 */ 1802 #define setSn_MSSR(sn, mss) { \ 1803 WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \ 1804 WIZCHIP_WRITE((Sn_MSSR(sn)+1), (uint8_t) mss); \ 1805 } 1806 1807 /** 1808 * @ingroup Socket_register_access_function 1809 * @brief Get @ref Sn_MSSR register 1810 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1811 * @return uint16_t. Value of @ref Sn_MSSR. 1812 * @sa setSn_MSSR() 1813 */ 1814 #define getSn_MSSR(sn) \ 1815 ((WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ((Sn_MSSR(sn)+1))) 1816 1817 /** 1818 * @ingroup Socket_register_access_function 1819 * @brief Set @ref Sn_TOS register 1820 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1821 * @param (uint8_t)tos Value to set @ref Sn_TOS 1822 * @sa getSn_TOS() 1823 */ 1824 #define setSn_TOS(sn, tos) \ 1825 WIZCHIP_WRITE(Sn_TOS(sn), tos) 1826 1827 /** 1828 * @ingroup Socket_register_access_function 1829 * @brief Get @ref Sn_TOS register 1830 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1831 * @return uint8_t. Value of Sn_TOS. 1832 * @sa setSn_TOS() 1833 */ 1834 #define getSn_TOS(sn) \ 1835 WIZCHIP_READ(Sn_TOS(sn)) 1836 1837 /** 1838 * @ingroup Socket_register_access_function 1839 * @brief Set @ref Sn_TTL register 1840 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1841 * @param (uint8_t)ttl Value to set @ref Sn_TTL 1842 * @sa getSn_TTL() 1843 */ 1844 #define setSn_TTL(sn, ttl) \ 1845 WIZCHIP_WRITE(Sn_TTL(sn), ttl) 1846 1847 1848 /** 1849 * @ingroup Socket_register_access_function 1850 * @brief Get @ref Sn_TTL register 1851 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1852 * @return uint8_t. Value of @ref Sn_TTL. 1853 * @sa setSn_TTL() 1854 */ 1855 #define getSn_TTL(sn) \ 1856 WIZCHIP_READ(Sn_TTL(sn)) 1857 1858 1859 /** 1860 * @ingroup Socket_register_access_function 1861 * @brief Set @ref Sn_RXBUF_SIZE register 1862 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1863 * @param (uint8_t)rxbufsize Value to set @ref Sn_RXBUF_SIZE 1864 * @sa getSn_RXBUF_SIZE() 1865 */ 1866 #define setSn_RXBUF_SIZE(sn, rxbufsize) \ 1867 WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize) 1868 1869 1870 /** 1871 * @ingroup Socket_register_access_function 1872 * @brief Get @ref Sn_RXBUF_SIZE register 1873 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1874 * @return uint8_t. Value of @ref Sn_RXBUF_SIZE. 1875 * @sa setSn_RXBUF_SIZE() 1876 */ 1877 #define getSn_RXBUF_SIZE(sn) \ 1878 WIZCHIP_READ(Sn_RXBUF_SIZE(sn)) 1879 1880 /** 1881 * @ingroup Socket_register_access_function 1882 * @brief Set @ref Sn_TXBUF_SIZE register 1883 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1884 * @param (uint8_t)txbufsize Value to set @ref Sn_TXBUF_SIZE 1885 * @sa getSn_TXBUF_SIZE() 1886 */ 1887 #define setSn_TXBUF_SIZE(sn, txbufsize) \ 1888 WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize) 1889 1890 /** 1891 * @ingroup Socket_register_access_function 1892 * @brief Get @ref Sn_TXBUF_SIZE register 1893 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1894 * @return uint8_t. Value of @ref Sn_TXBUF_SIZE. 1895 * @sa setSn_TXBUF_SIZE() 1896 */ 1897 #define getSn_TXBUF_SIZE(sn) \ 1898 WIZCHIP_READ(Sn_TXBUF_SIZE(sn)) 1899 1900 /** 1901 * @ingroup Socket_register_access_function 1902 * @brief Get @ref Sn_TX_FSR register 1903 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1904 * @return uint16_t. Value of @ref Sn_TX_FSR. 1905 */ 1906 uint16_t getSn_TX_FSR(uint8_t sn); 1907 1908 /** 1909 * @ingroup Socket_register_access_function 1910 * @brief Get @ref Sn_TX_RD register 1911 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1912 * @return uint16_t. Value of @ref Sn_TX_RD. 1913 */ 1914 #define getSn_TX_RD(sn) \ 1915 ((WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ((Sn_TX_RD(sn)+1))) 1916 1917 /** 1918 * @ingroup Socket_register_access_function 1919 * @brief Set @ref Sn_TX_WR register 1920 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1921 * @param (uint16_t)txwr Value to set @ref Sn_TX_WR 1922 * @sa GetSn_TX_WR() 1923 */ 1924 #define setSn_TX_WR(sn, txwr) { \ 1925 WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \ 1926 WIZCHIP_WRITE((Sn_TX_WR(sn)+1), (uint8_t) txwr); \ 1927 } 1928 1929 /** 1930 * @ingroup Socket_register_access_function 1931 * @brief Get @ref Sn_TX_WR register 1932 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1933 * @return uint16_t. Value of @ref Sn_TX_WR. 1934 * @sa setSn_TX_WR() 1935 */ 1936 #define getSn_TX_WR(sn) \ 1937 ((WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ((Sn_TX_WR(sn)+1))) 1938 1939 1940 /** 1941 * @ingroup Socket_register_access_function 1942 * @brief Get @ref Sn_RX_RSR register 1943 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1944 * @return uint16_t. Value of @ref Sn_RX_RSR. 1945 */ 1946 uint16_t getSn_RX_RSR(uint8_t sn); 1947 1948 1949 /** 1950 * @ingroup Socket_register_access_function 1951 * @brief Set @ref Sn_RX_RD register 1952 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1953 * @param (uint16_t)rxrd Value to set @ref Sn_RX_RD 1954 * @sa getSn_RX_RD() 1955 */ 1956 #define setSn_RX_RD(sn, rxrd) { \ 1957 WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \ 1958 WIZCHIP_WRITE((Sn_RX_RD(sn)+1), (uint8_t) rxrd); \ 1959 } 1960 1961 /** 1962 * @ingroup Socket_register_access_function 1963 * @brief Get @ref Sn_RX_RD register 1964 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1965 * @regurn uint16_t. Value of @ref Sn_RX_RD. 1966 * @sa setSn_RX_RD() 1967 */ 1968 #define getSn_RX_RD(sn) \ 1969 ((WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ((Sn_RX_RD(sn)+1))) 1970 1971 /** 1972 * @ingroup Socket_register_access_function 1973 * @brief Get @ref Sn_RX_WR register 1974 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1975 * @return uint16_t. Value of @ref Sn_RX_WR. 1976 */ 1977 #define getSn_RX_WR(sn) \ 1978 ((WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ((Sn_RX_WR(sn)+1))) 1979 1980 1981 /** 1982 * @ingroup Socket_register_access_function 1983 * @brief Set @ref Sn_FRAG register 1984 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1985 * @param (uint16_t)frag Value to set @ref Sn_FRAG 1986 * @sa getSn_FRAD() 1987 */ 1988 #if 0 // dpgeorge 1989 #define setSn_FRAG(sn, frag) { \ 1990 WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \ 1991 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \ 1992 } 1993 1994 /** 1995 * @ingroup Socket_register_access_function 1996 * @brief Get @ref Sn_FRAG register 1997 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 1998 * @return uint16_t. Value of @ref Sn_FRAG. 1999 * @sa setSn_FRAG() 2000 */ 2001 #define getSn_FRAG(sn) \ 2002 ((WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1))) 2003 2004 /** 2005 * @ingroup Socket_register_access_function 2006 * @brief Set @ref Sn_KPALVTR register 2007 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 2008 * @param (uint8_t)kpalvt Value to set @ref Sn_KPALVTR 2009 * @sa getSn_KPALVTR() 2010 */ 2011 #define setSn_KPALVTR(sn, kpalvt) \ 2012 WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt) 2013 2014 /** 2015 * @ingroup Socket_register_access_function 2016 * @brief Get @ref Sn_KPALVTR register 2017 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 2018 * @return uint8_t. Value of @ref Sn_KPALVTR. 2019 * @sa setSn_KPALVTR() 2020 */ 2021 #define getSn_KPALVTR(sn) \ 2022 WIZCHIP_READ(Sn_KPALVTR(sn)) 2023 2024 ////////////////////////////////////// 2025 #endif 2026 2027 ///////////////////////////////////// 2028 // Sn_TXBUF & Sn_RXBUF IO function // 2029 ///////////////////////////////////// 2030 /** 2031 * @brief Gets the max buffer size of socket sn passed as parameter. 2032 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 2033 * @return uint16_t. Value of Socket n RX max buffer size. 2034 */ 2035 #define getSn_RxMAX(sn) \ 2036 (getSn_RXBUF_SIZE(sn) << 10) 2037 2038 /** 2039 * @brief Gets the max buffer size of socket sn passed as parameters. 2040 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 2041 * @return uint16_t. Value of Socket n TX max buffer size. 2042 */ 2043 //uint16_t getSn_TxMAX(uint8_t sn); 2044 #define getSn_TxMAX(sn) \ 2045 (getSn_TXBUF_SIZE(sn) << 10) 2046 2047 void wiz_init(void); 2048 2049 /** 2050 * @ingroup Basic_IO_function 2051 * @brief It copies data to internal TX memory 2052 * 2053 * @details This function reads the Tx write pointer register and after that, 2054 * it copies the <i>wizdata(pointer buffer)</i> of the length of <i>len(variable)</i> bytes to internal TX memory 2055 * and updates the Tx write pointer register. 2056 * This function is being called by send() and sendto() function also. 2057 * 2058 * @note User should read upper byte first and lower byte later to get proper value. 2059 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 2060 * @param wizdata Pointer buffer to write data 2061 * @param len Data length 2062 * @sa wiz_recv_data() 2063 */ 2064 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len); 2065 2066 /** 2067 * @ingroup Basic_IO_function 2068 * @brief It copies data to your buffer from internal RX memory 2069 * 2070 * @details This function read the Rx read pointer register and after that, 2071 * it copies the received data from internal RX memory 2072 * to <i>wizdata(pointer variable)</i> of the length of <i>len(variable)</i> bytes. 2073 * This function is being called by recv() also. 2074 * 2075 * @note User should read upper byte first and lower byte later to get proper value. 2076 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 2077 * @param wizdata Pointer buffer to read data 2078 * @param len Data length 2079 * @sa wiz_send_data() 2080 */ 2081 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len); 2082 2083 /** 2084 * @ingroup Basic_IO_function 2085 * @brief It discard the received data in RX memory. 2086 * @details It discards the data of the length of <i>len(variable)</i> bytes in internal RX memory. 2087 * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. 2088 * @param len Data length 2089 */ 2090 void wiz_recv_ignore(uint8_t sn, uint16_t len); 2091 2092 #endif // _W5500_H_ 2093