1 /**
2 * \file
3 * AMD64 backend for the Mono code generator
4 *
5 * Based on mini-x86.c.
6 *
7 * Authors:
8 * Paolo Molaro (lupus@ximian.com)
9 * Dietmar Maurer (dietmar@ximian.com)
10 * Patrik Torstensson
11 * Zoltan Varga (vargaz@gmail.com)
12 * Johan Lorensson (lateralusx.github@gmail.com)
13 *
14 * (C) 2003 Ximian, Inc.
15 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
16 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
17 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
18 */
19 #include "mini.h"
20 #include <string.h>
21 #include <math.h>
22 #include <assert.h>
23 #ifdef HAVE_UNISTD_H
24 #include <unistd.h>
25 #endif
26
27 #include <mono/metadata/abi-details.h>
28 #include <mono/metadata/appdomain.h>
29 #include <mono/metadata/debug-helpers.h>
30 #include <mono/metadata/threads.h>
31 #include <mono/metadata/profiler-private.h>
32 #include <mono/metadata/mono-debug.h>
33 #include <mono/metadata/gc-internals.h>
34 #include <mono/utils/mono-math.h>
35 #include <mono/utils/mono-mmap.h>
36 #include <mono/utils/mono-memory-model.h>
37 #include <mono/utils/mono-tls.h>
38 #include <mono/utils/mono-hwcap.h>
39 #include <mono/utils/mono-threads.h>
40 #include <mono/utils/unlocked.h>
41
42 #include "trace.h"
43 #include "ir-emit.h"
44 #include "mini-amd64.h"
45 #include "cpu-amd64.h"
46 #include "debugger-agent.h"
47 #include "mini-gc.h"
48 #include "mini-runtime.h"
49 #include "aot-runtime.h"
50
51 #ifdef MONO_XEN_OPT
52 static gboolean optimize_for_xen = TRUE;
53 #else
54 #define optimize_for_xen 0
55 #endif
56
57 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
58
59 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
60
61 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
62
63 #ifdef TARGET_WIN32
64 /* Under windows, the calling convention is never stdcall */
65 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
66 #else
67 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
68 #endif
69
70 /* This mutex protects architecture specific caches */
71 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
72 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
73 static mono_mutex_t mini_arch_mutex;
74
75 /* The single step trampoline */
76 static gpointer ss_trampoline;
77
78 /* The breakpoint trampoline */
79 static gpointer bp_trampoline;
80
81 /* Offset between fp and the first argument in the callee */
82 #define ARGS_OFFSET 16
83 #define GP_SCRATCH_REG AMD64_R11
84
85 /*
86 * AMD64 register usage:
87 * - callee saved registers are used for global register allocation
88 * - %r11 is used for materializing 64 bit constants in opcodes
89 * - the rest is used for local allocation
90 */
91
92 /*
93 * Floating point comparison results:
94 * ZF PF CF
95 * A > B 0 0 0
96 * A < B 0 0 1
97 * A = B 1 0 0
98 * A > B 0 0 0
99 * UNORDERED 1 1 1
100 */
101
102 const char*
mono_arch_regname(int reg)103 mono_arch_regname (int reg)
104 {
105 switch (reg) {
106 case AMD64_RAX: return "%rax";
107 case AMD64_RBX: return "%rbx";
108 case AMD64_RCX: return "%rcx";
109 case AMD64_RDX: return "%rdx";
110 case AMD64_RSP: return "%rsp";
111 case AMD64_RBP: return "%rbp";
112 case AMD64_RDI: return "%rdi";
113 case AMD64_RSI: return "%rsi";
114 case AMD64_R8: return "%r8";
115 case AMD64_R9: return "%r9";
116 case AMD64_R10: return "%r10";
117 case AMD64_R11: return "%r11";
118 case AMD64_R12: return "%r12";
119 case AMD64_R13: return "%r13";
120 case AMD64_R14: return "%r14";
121 case AMD64_R15: return "%r15";
122 }
123 return "unknown";
124 }
125
126 static const char * packed_xmmregs [] = {
127 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
128 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
129 };
130
131 static const char * single_xmmregs [] = {
132 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
133 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
134 };
135
136 const char*
mono_arch_fregname(int reg)137 mono_arch_fregname (int reg)
138 {
139 if (reg < AMD64_XMM_NREG)
140 return single_xmmregs [reg];
141 else
142 return "unknown";
143 }
144
145 const char *
mono_arch_xregname(int reg)146 mono_arch_xregname (int reg)
147 {
148 if (reg < AMD64_XMM_NREG)
149 return packed_xmmregs [reg];
150 else
151 return "unknown";
152 }
153
154 static gboolean
debug_omit_fp(void)155 debug_omit_fp (void)
156 {
157 #if 0
158 return mono_debug_count ();
159 #else
160 return TRUE;
161 #endif
162 }
163
164 static inline gboolean
amd64_is_near_call(guint8 * code)165 amd64_is_near_call (guint8 *code)
166 {
167 /* Skip REX */
168 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
169 code += 1;
170
171 return code [0] == 0xe8;
172 }
173
174 static inline gboolean
amd64_use_imm32(gint64 val)175 amd64_use_imm32 (gint64 val)
176 {
177 if (mini_get_debug_options()->single_imm_size)
178 return FALSE;
179
180 return amd64_is_imm32 (val);
181 }
182
183 static void
amd64_patch(unsigned char * code,gpointer target)184 amd64_patch (unsigned char* code, gpointer target)
185 {
186 guint8 rex = 0;
187
188 /* Skip REX */
189 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
190 rex = code [0];
191 code += 1;
192 }
193
194 if ((code [0] & 0xf8) == 0xb8) {
195 /* amd64_set_reg_template */
196 *(guint64*)(code + 1) = (guint64)target;
197 }
198 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
199 /* mov 0(%rip), %dreg */
200 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
201 }
202 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
203 /* call *<OFFSET>(%rip) */
204 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
205 }
206 else if (code [0] == 0xe8) {
207 /* call <DISP> */
208 gint64 disp = (guint8*)target - (guint8*)code;
209 g_assert (amd64_is_imm32 (disp));
210 x86_patch (code, (unsigned char*)target);
211 }
212 else
213 x86_patch (code, (unsigned char*)target);
214 }
215
216 void
mono_amd64_patch(unsigned char * code,gpointer target)217 mono_amd64_patch (unsigned char* code, gpointer target)
218 {
219 amd64_patch (code, target);
220 }
221
222 #define DEBUG(a) if (cfg->verbose_level > 1) a
223
224 static void inline
add_general(guint32 * gr,guint32 * stack_size,ArgInfo * ainfo)225 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
226 {
227 ainfo->offset = *stack_size;
228
229 if (*gr >= PARAM_REGS) {
230 ainfo->storage = ArgOnStack;
231 ainfo->arg_size = sizeof (mgreg_t);
232 /* Since the same stack slot size is used for all arg */
233 /* types, it needs to be big enough to hold them all */
234 (*stack_size) += sizeof(mgreg_t);
235 }
236 else {
237 ainfo->storage = ArgInIReg;
238 ainfo->reg = param_regs [*gr];
239 (*gr) ++;
240 }
241 }
242
243 static void inline
add_float(guint32 * gr,guint32 * stack_size,ArgInfo * ainfo,gboolean is_double)244 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
245 {
246 ainfo->offset = *stack_size;
247
248 if (*gr >= FLOAT_PARAM_REGS) {
249 ainfo->storage = ArgOnStack;
250 ainfo->arg_size = sizeof (mgreg_t);
251 /* Since the same stack slot size is used for both float */
252 /* types, it needs to be big enough to hold them both */
253 (*stack_size) += sizeof(mgreg_t);
254 }
255 else {
256 /* A double register */
257 if (is_double)
258 ainfo->storage = ArgInDoubleSSEReg;
259 else
260 ainfo->storage = ArgInFloatSSEReg;
261 ainfo->reg = *gr;
262 (*gr) += 1;
263 }
264 }
265
266 typedef enum ArgumentClass {
267 ARG_CLASS_NO_CLASS,
268 ARG_CLASS_MEMORY,
269 ARG_CLASS_INTEGER,
270 ARG_CLASS_SSE
271 } ArgumentClass;
272
273 static ArgumentClass
merge_argument_class_from_type(MonoType * type,ArgumentClass class1)274 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
275 {
276 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
277 MonoType *ptype;
278
279 ptype = mini_get_underlying_type (type);
280 switch (ptype->type) {
281 case MONO_TYPE_I1:
282 case MONO_TYPE_U1:
283 case MONO_TYPE_I2:
284 case MONO_TYPE_U2:
285 case MONO_TYPE_I4:
286 case MONO_TYPE_U4:
287 case MONO_TYPE_I:
288 case MONO_TYPE_U:
289 case MONO_TYPE_OBJECT:
290 case MONO_TYPE_PTR:
291 case MONO_TYPE_FNPTR:
292 case MONO_TYPE_I8:
293 case MONO_TYPE_U8:
294 class2 = ARG_CLASS_INTEGER;
295 break;
296 case MONO_TYPE_R4:
297 case MONO_TYPE_R8:
298 #ifdef TARGET_WIN32
299 class2 = ARG_CLASS_INTEGER;
300 #else
301 class2 = ARG_CLASS_SSE;
302 #endif
303 break;
304
305 case MONO_TYPE_TYPEDBYREF:
306 g_assert_not_reached ();
307
308 case MONO_TYPE_GENERICINST:
309 if (!mono_type_generic_inst_is_valuetype (ptype)) {
310 class2 = ARG_CLASS_INTEGER;
311 break;
312 }
313 /* fall through */
314 case MONO_TYPE_VALUETYPE: {
315 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
316 int i;
317
318 for (i = 0; i < info->num_fields; ++i) {
319 class2 = class1;
320 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
321 }
322 break;
323 }
324 default:
325 g_assert_not_reached ();
326 }
327
328 /* Merge */
329 if (class1 == class2)
330 ;
331 else if (class1 == ARG_CLASS_NO_CLASS)
332 class1 = class2;
333 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
334 class1 = ARG_CLASS_MEMORY;
335 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
336 class1 = ARG_CLASS_INTEGER;
337 else
338 class1 = ARG_CLASS_SSE;
339
340 return class1;
341 }
342
343 typedef struct {
344 MonoType *type;
345 int size, offset;
346 } StructFieldInfo;
347
348 /*
349 * collect_field_info_nested:
350 *
351 * Collect field info from KLASS recursively into FIELDS.
352 */
353 static void
collect_field_info_nested(MonoClass * klass,GArray * fields_array,int offset,gboolean pinvoke,gboolean unicode)354 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
355 {
356 MonoMarshalType *info;
357 int i;
358
359 if (pinvoke) {
360 info = mono_marshal_load_type_info (klass);
361 g_assert(info);
362 for (i = 0; i < info->num_fields; ++i) {
363 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
364 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
365 } else {
366 guint32 align;
367 StructFieldInfo f;
368
369 f.type = info->fields [i].field->type;
370 f.size = mono_marshal_type_size (info->fields [i].field->type,
371 info->fields [i].mspec,
372 &align, TRUE, unicode);
373 f.offset = offset + info->fields [i].offset;
374 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
375 /* This can happen with .pack directives eg. 'fixed' arrays */
376 if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
377 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
378 g_array_append_val (fields_array, f);
379 while (f.size + f.offset < info->native_size) {
380 f.offset += f.size;
381 g_array_append_val (fields_array, f);
382 }
383 } else {
384 f.size = info->native_size - f.offset;
385 g_array_append_val (fields_array, f);
386 }
387 } else {
388 g_array_append_val (fields_array, f);
389 }
390 }
391 }
392 } else {
393 gpointer iter;
394 MonoClassField *field;
395
396 iter = NULL;
397 while ((field = mono_class_get_fields (klass, &iter))) {
398 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
399 continue;
400 if (MONO_TYPE_ISSTRUCT (field->type)) {
401 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
402 } else {
403 int align;
404 StructFieldInfo f;
405
406 f.type = field->type;
407 f.size = mono_type_size (field->type, &align);
408 f.offset = field->offset - sizeof (MonoObject) + offset;
409
410 g_array_append_val (fields_array, f);
411 }
412 }
413 }
414 }
415
416 #ifdef TARGET_WIN32
417
418 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
419 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
420
421 static gboolean
allocate_register_for_valuetype_win64(ArgInfo * arg_info,ArgumentClass arg_class,guint32 arg_size,AMD64_Reg_No int_regs[],int int_reg_count,AMD64_XMM_Reg_No float_regs[],int float_reg_count,guint32 * current_int_reg,guint32 * current_float_reg)422 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
423 {
424 gboolean result = FALSE;
425
426 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
427 assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
428
429 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
430 arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
431 arg_info->pair_size [0] = 0;
432 arg_info->pair_size [1] = 0;
433 arg_info->nregs = 0;
434
435 if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
436 /* Pass parameter in integer register. */
437 arg_info->pair_storage [0] = ArgInIReg;
438 arg_info->pair_regs [0] = int_regs [*current_int_reg];
439 (*current_int_reg) ++;
440 result = TRUE;
441 } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
442 /* Pass parameter in float register. */
443 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
444 arg_info->pair_regs [0] = float_regs [*current_float_reg];
445 (*current_float_reg) ++;
446 result = TRUE;
447 }
448
449 if (result == TRUE) {
450 arg_info->pair_size [0] = arg_size;
451 arg_info->nregs = 1;
452 }
453
454 return result;
455 }
456
457 static inline gboolean
allocate_parameter_register_for_valuetype_win64(ArgInfo * arg_info,ArgumentClass arg_class,guint32 arg_size,guint32 * current_int_reg,guint32 * current_float_reg)458 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
459 {
460 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
461 }
462
463 static inline gboolean
allocate_return_register_for_valuetype_win64(ArgInfo * arg_info,ArgumentClass arg_class,guint32 arg_size,guint32 * current_int_reg,guint32 * current_float_reg)464 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
465 {
466 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
467 }
468
469 static void
allocate_storage_for_valuetype_win64(ArgInfo * arg_info,MonoType * type,gboolean is_return,ArgumentClass arg_class,guint32 arg_size,guint32 * current_int_reg,guint32 * current_float_reg,guint32 * stack_size)470 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
471 guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
472 {
473 /* Windows x64 value type ABI.
474 *
475 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
476 *
477 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
478 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
479 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
480 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
481 *
482 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
483 *
484 * Integers/Float types smaller than or equal to 8 bytes
485 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
486 * Properly sized struct/unions (1,2,4,8)
487 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
488 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
489 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
490 */
491
492 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
493
494 if (!is_return) {
495
496 /* Parameter cases. */
497 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
498 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
499
500 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
501 arg_info->storage = ArgValuetypeInReg;
502 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
503 /* No more registers, fallback passing parameter on stack as value. */
504 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
505
506 /* Passing value directly on stack, so use size of value. */
507 arg_info->storage = ArgOnStack;
508 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
509 arg_info->offset = *stack_size;
510 arg_info->arg_size = arg_size;
511 *stack_size += arg_size;
512 }
513 } else {
514 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
515 arg_info->storage = ArgValuetypeAddrInIReg;
516 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
517 /* No more registers, fallback passing address to parameter on stack. */
518 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
519
520 /* Passing an address to value on stack, so use size of register as argument size. */
521 arg_info->storage = ArgValuetypeAddrOnStack;
522 arg_size = sizeof (mgreg_t);
523 arg_info->offset = *stack_size;
524 arg_info->arg_size = arg_size;
525 *stack_size += arg_size;
526 }
527 }
528 } else {
529 /* Return value cases. */
530 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
531 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
532
533 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
534 arg_info->storage = ArgValuetypeInReg;
535 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
536
537 /* Only RAX/XMM0 should be used to return valuetype. */
538 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
539 } else {
540 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
541 arg_info->storage = ArgValuetypeAddrInIReg;
542 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
543
544 /* Only RAX should be used to return valuetype address. */
545 assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
546
547 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
548 arg_info->offset = *stack_size;
549 *stack_size += arg_size;
550 }
551 }
552 }
553
554 static void
get_valuetype_size_win64(MonoClass * klass,gboolean pinvoke,ArgInfo * arg_info,MonoType * type,ArgumentClass * arg_class,guint32 * arg_size)555 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
556 {
557 *arg_size = 0;
558 *arg_class = ARG_CLASS_NO_CLASS;
559
560 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
561
562 if (pinvoke) {
563 /* Calculate argument class type and size of marshalled type. */
564 MonoMarshalType *info = mono_marshal_load_type_info (klass);
565 *arg_size = info->native_size;
566 } else {
567 /* Calculate argument class type and size of managed type. */
568 *arg_size = mono_class_value_size (klass, NULL);
569 }
570
571 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
572 *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
573
574 if (*arg_class == ARG_CLASS_MEMORY) {
575 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
576 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
577 }
578
579 /*
580 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
581 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
582 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
583 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
584 * it must be represented in call and cannot be dropped.
585 */
586 if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
587 arg_info->pass_empty_struct = TRUE;
588 *arg_size = SIZEOF_REGISTER;
589 *arg_class = ARG_CLASS_INTEGER;
590 }
591
592 assert (*arg_class != ARG_CLASS_NO_CLASS);
593 }
594
595 static void
add_valuetype_win64(MonoMethodSignature * signature,ArgInfo * arg_info,MonoType * type,gboolean is_return,guint32 * current_int_reg,guint32 * current_float_reg,guint32 * stack_size)596 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
597 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
598 {
599 guint32 arg_size = SIZEOF_REGISTER;
600 MonoClass *klass = NULL;
601 ArgumentClass arg_class;
602
603 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
604
605 klass = mono_class_from_mono_type (type);
606 get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
607
608 /* Only drop value type if its not an empty struct as input that must be represented in call */
609 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
610 arg_info->storage = ArgValuetypeInReg;
611 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
612 } else {
613 /* Alocate storage for value type. */
614 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
615 }
616 }
617
618 #endif /* TARGET_WIN32 */
619
620 static void
add_valuetype(MonoMethodSignature * sig,ArgInfo * ainfo,MonoType * type,gboolean is_return,guint32 * gr,guint32 * fr,guint32 * stack_size)621 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
622 gboolean is_return,
623 guint32 *gr, guint32 *fr, guint32 *stack_size)
624 {
625 #ifdef TARGET_WIN32
626 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
627 #else
628 guint32 size, quad, nquads, i, nfields;
629 /* Keep track of the size used in each quad so we can */
630 /* use the right size when copying args/return vars. */
631 guint32 quadsize [2] = {8, 8};
632 ArgumentClass args [2];
633 StructFieldInfo *fields = NULL;
634 GArray *fields_array;
635 MonoClass *klass;
636 gboolean pass_on_stack = FALSE;
637 int struct_size;
638
639 klass = mono_class_from_mono_type (type);
640 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
641
642 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
643 /* We pass and return vtypes of size 8 in a register */
644 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
645 pass_on_stack = TRUE;
646 }
647
648 /* If this struct can't be split up naturally into 8-byte */
649 /* chunks (registers), pass it on the stack. */
650 if (sig->pinvoke) {
651 MonoMarshalType *info = mono_marshal_load_type_info (klass);
652 g_assert (info);
653 struct_size = info->native_size;
654 } else {
655 struct_size = mono_class_value_size (klass, NULL);
656 }
657 /*
658 * Collect field information recursively to be able to
659 * handle nested structures.
660 */
661 fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
662 collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
663 fields = (StructFieldInfo*)fields_array->data;
664 nfields = fields_array->len;
665
666 for (i = 0; i < nfields; ++i) {
667 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
668 pass_on_stack = TRUE;
669 break;
670 }
671 }
672
673 if (size == 0) {
674 ainfo->storage = ArgValuetypeInReg;
675 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
676 return;
677 }
678
679 if (pass_on_stack) {
680 /* Allways pass in memory */
681 ainfo->offset = *stack_size;
682 *stack_size += ALIGN_TO (size, 8);
683 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
684 if (!is_return)
685 ainfo->arg_size = ALIGN_TO (size, 8);
686
687 g_array_free (fields_array, TRUE);
688 return;
689 }
690
691 if (size > 8)
692 nquads = 2;
693 else
694 nquads = 1;
695
696 if (!sig->pinvoke) {
697 int n = mono_class_value_size (klass, NULL);
698
699 quadsize [0] = n >= 8 ? 8 : n;
700 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
701
702 /* Always pass in 1 or 2 integer registers */
703 args [0] = ARG_CLASS_INTEGER;
704 args [1] = ARG_CLASS_INTEGER;
705 /* Only the simplest cases are supported */
706 if (is_return && nquads != 1) {
707 args [0] = ARG_CLASS_MEMORY;
708 args [1] = ARG_CLASS_MEMORY;
709 }
710 } else {
711 /*
712 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
713 * The X87 and SSEUP stuff is left out since there are no such types in
714 * the CLR.
715 */
716 if (!nfields) {
717 ainfo->storage = ArgValuetypeInReg;
718 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
719 return;
720 }
721
722 if (struct_size > 16) {
723 ainfo->offset = *stack_size;
724 *stack_size += ALIGN_TO (struct_size, 8);
725 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
726 if (!is_return)
727 ainfo->arg_size = ALIGN_TO (struct_size, 8);
728
729 g_array_free (fields_array, TRUE);
730 return;
731 }
732
733 args [0] = ARG_CLASS_NO_CLASS;
734 args [1] = ARG_CLASS_NO_CLASS;
735 for (quad = 0; quad < nquads; ++quad) {
736 ArgumentClass class1;
737
738 if (nfields == 0)
739 class1 = ARG_CLASS_MEMORY;
740 else
741 class1 = ARG_CLASS_NO_CLASS;
742 for (i = 0; i < nfields; ++i) {
743 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
744 /* Unaligned field */
745 NOT_IMPLEMENTED;
746 }
747
748 /* Skip fields in other quad */
749 if ((quad == 0) && (fields [i].offset >= 8))
750 continue;
751 if ((quad == 1) && (fields [i].offset < 8))
752 continue;
753
754 /* How far into this quad this data extends.*/
755 /* (8 is size of quad) */
756 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
757
758 class1 = merge_argument_class_from_type (fields [i].type, class1);
759 }
760 /* Empty structs have a nonzero size, causing this assert to be hit */
761 if (sig->pinvoke)
762 g_assert (class1 != ARG_CLASS_NO_CLASS);
763 args [quad] = class1;
764 }
765 }
766
767 g_array_free (fields_array, TRUE);
768
769 /* Post merger cleanup */
770 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
771 args [0] = args [1] = ARG_CLASS_MEMORY;
772
773 /* Allocate registers */
774 {
775 int orig_gr = *gr;
776 int orig_fr = *fr;
777
778 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
779 quadsize [0] ++;
780 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
781 quadsize [1] ++;
782
783 ainfo->storage = ArgValuetypeInReg;
784 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
785 g_assert (quadsize [0] <= 8);
786 g_assert (quadsize [1] <= 8);
787 ainfo->pair_size [0] = quadsize [0];
788 ainfo->pair_size [1] = quadsize [1];
789 ainfo->nregs = nquads;
790 for (quad = 0; quad < nquads; ++quad) {
791 switch (args [quad]) {
792 case ARG_CLASS_INTEGER:
793 if (*gr >= PARAM_REGS)
794 args [quad] = ARG_CLASS_MEMORY;
795 else {
796 ainfo->pair_storage [quad] = ArgInIReg;
797 if (is_return)
798 ainfo->pair_regs [quad] = return_regs [*gr];
799 else
800 ainfo->pair_regs [quad] = param_regs [*gr];
801 (*gr) ++;
802 }
803 break;
804 case ARG_CLASS_SSE:
805 if (*fr >= FLOAT_PARAM_REGS)
806 args [quad] = ARG_CLASS_MEMORY;
807 else {
808 if (quadsize[quad] <= 4)
809 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
810 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
811 ainfo->pair_regs [quad] = *fr;
812 (*fr) ++;
813 }
814 break;
815 case ARG_CLASS_MEMORY:
816 break;
817 case ARG_CLASS_NO_CLASS:
818 break;
819 default:
820 g_assert_not_reached ();
821 }
822 }
823
824 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
825 int arg_size;
826 /* Revert possible register assignments */
827 *gr = orig_gr;
828 *fr = orig_fr;
829
830 ainfo->offset = *stack_size;
831 if (sig->pinvoke)
832 arg_size = ALIGN_TO (struct_size, 8);
833 else
834 arg_size = nquads * sizeof(mgreg_t);
835 *stack_size += arg_size;
836 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
837 if (!is_return)
838 ainfo->arg_size = arg_size;
839 }
840 }
841 #endif /* !TARGET_WIN32 */
842 }
843
844 /*
845 * get_call_info:
846 *
847 * Obtain information about a call according to the calling convention.
848 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
849 * Draft Version 0.23" document for more information.
850 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
851 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
852 */
853 static CallInfo*
get_call_info(MonoMemPool * mp,MonoMethodSignature * sig)854 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
855 {
856 guint32 i, gr, fr, pstart;
857 MonoType *ret_type;
858 int n = sig->hasthis + sig->param_count;
859 guint32 stack_size = 0;
860 CallInfo *cinfo;
861 gboolean is_pinvoke = sig->pinvoke;
862
863 if (mp)
864 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
865 else
866 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
867
868 cinfo->nargs = n;
869 cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
870
871 gr = 0;
872 fr = 0;
873
874 #ifdef TARGET_WIN32
875 /* Reserve space where the callee can save the argument registers */
876 stack_size = 4 * sizeof (mgreg_t);
877 #endif
878
879 /* return value */
880 ret_type = mini_get_underlying_type (sig->ret);
881 switch (ret_type->type) {
882 case MONO_TYPE_I1:
883 case MONO_TYPE_U1:
884 case MONO_TYPE_I2:
885 case MONO_TYPE_U2:
886 case MONO_TYPE_I4:
887 case MONO_TYPE_U4:
888 case MONO_TYPE_I:
889 case MONO_TYPE_U:
890 case MONO_TYPE_PTR:
891 case MONO_TYPE_FNPTR:
892 case MONO_TYPE_OBJECT:
893 cinfo->ret.storage = ArgInIReg;
894 cinfo->ret.reg = AMD64_RAX;
895 break;
896 case MONO_TYPE_U8:
897 case MONO_TYPE_I8:
898 cinfo->ret.storage = ArgInIReg;
899 cinfo->ret.reg = AMD64_RAX;
900 break;
901 case MONO_TYPE_R4:
902 cinfo->ret.storage = ArgInFloatSSEReg;
903 cinfo->ret.reg = AMD64_XMM0;
904 break;
905 case MONO_TYPE_R8:
906 cinfo->ret.storage = ArgInDoubleSSEReg;
907 cinfo->ret.reg = AMD64_XMM0;
908 break;
909 case MONO_TYPE_GENERICINST:
910 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
911 cinfo->ret.storage = ArgInIReg;
912 cinfo->ret.reg = AMD64_RAX;
913 break;
914 }
915 if (mini_is_gsharedvt_type (ret_type)) {
916 cinfo->ret.storage = ArgGsharedvtVariableInReg;
917 break;
918 }
919 /* fall through */
920 case MONO_TYPE_VALUETYPE:
921 case MONO_TYPE_TYPEDBYREF: {
922 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
923
924 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
925 g_assert (cinfo->ret.storage != ArgInIReg);
926 break;
927 }
928 case MONO_TYPE_VAR:
929 case MONO_TYPE_MVAR:
930 g_assert (mini_is_gsharedvt_type (ret_type));
931 cinfo->ret.storage = ArgGsharedvtVariableInReg;
932 break;
933 case MONO_TYPE_VOID:
934 break;
935 default:
936 g_error ("Can't handle as return value 0x%x", ret_type->type);
937 }
938
939 pstart = 0;
940 /*
941 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
942 * the first argument, allowing 'this' to be always passed in the first arg reg.
943 * Also do this if the first argument is a reference type, since virtual calls
944 * are sometimes made using calli without sig->hasthis set, like in the delegate
945 * invoke wrappers.
946 */
947 ArgStorage ret_storage = cinfo->ret.storage;
948 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
949 if (sig->hasthis) {
950 add_general (&gr, &stack_size, cinfo->args + 0);
951 } else {
952 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
953 pstart = 1;
954 }
955 add_general (&gr, &stack_size, &cinfo->ret);
956 cinfo->ret.storage = ret_storage;
957 cinfo->vret_arg_index = 1;
958 } else {
959 /* this */
960 if (sig->hasthis)
961 add_general (&gr, &stack_size, cinfo->args + 0);
962
963 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
964 add_general (&gr, &stack_size, &cinfo->ret);
965 cinfo->ret.storage = ret_storage;
966 }
967 }
968
969 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
970 gr = PARAM_REGS;
971 fr = FLOAT_PARAM_REGS;
972
973 /* Emit the signature cookie just before the implicit arguments */
974 add_general (&gr, &stack_size, &cinfo->sig_cookie);
975 }
976
977 for (i = pstart; i < sig->param_count; ++i) {
978 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
979 MonoType *ptype;
980
981 #ifdef TARGET_WIN32
982 /* The float param registers and other param registers must be the same index on Windows x64.*/
983 if (gr > fr)
984 fr = gr;
985 else if (fr > gr)
986 gr = fr;
987 #endif
988
989 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
990 /* We allways pass the sig cookie on the stack for simplicity */
991 /*
992 * Prevent implicit arguments + the sig cookie from being passed
993 * in registers.
994 */
995 gr = PARAM_REGS;
996 fr = FLOAT_PARAM_REGS;
997
998 /* Emit the signature cookie just before the implicit arguments */
999 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1000 }
1001
1002 ptype = mini_get_underlying_type (sig->params [i]);
1003 switch (ptype->type) {
1004 case MONO_TYPE_I1:
1005 case MONO_TYPE_U1:
1006 add_general (&gr, &stack_size, ainfo);
1007 ainfo->byte_arg_size = 1;
1008 break;
1009 case MONO_TYPE_I2:
1010 case MONO_TYPE_U2:
1011 add_general (&gr, &stack_size, ainfo);
1012 ainfo->byte_arg_size = 2;
1013 break;
1014 case MONO_TYPE_I4:
1015 case MONO_TYPE_U4:
1016 add_general (&gr, &stack_size, ainfo);
1017 ainfo->byte_arg_size = 4;
1018 break;
1019 case MONO_TYPE_I:
1020 case MONO_TYPE_U:
1021 case MONO_TYPE_PTR:
1022 case MONO_TYPE_FNPTR:
1023 case MONO_TYPE_OBJECT:
1024 add_general (&gr, &stack_size, ainfo);
1025 break;
1026 case MONO_TYPE_GENERICINST:
1027 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1028 add_general (&gr, &stack_size, ainfo);
1029 break;
1030 }
1031 if (mini_is_gsharedvt_variable_type (ptype)) {
1032 /* gsharedvt arguments are passed by ref */
1033 add_general (&gr, &stack_size, ainfo);
1034 if (ainfo->storage == ArgInIReg)
1035 ainfo->storage = ArgGSharedVtInReg;
1036 else
1037 ainfo->storage = ArgGSharedVtOnStack;
1038 break;
1039 }
1040 /* fall through */
1041 case MONO_TYPE_VALUETYPE:
1042 case MONO_TYPE_TYPEDBYREF:
1043 add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1044 break;
1045 case MONO_TYPE_U8:
1046
1047 case MONO_TYPE_I8:
1048 add_general (&gr, &stack_size, ainfo);
1049 break;
1050 case MONO_TYPE_R4:
1051 add_float (&fr, &stack_size, ainfo, FALSE);
1052 break;
1053 case MONO_TYPE_R8:
1054 add_float (&fr, &stack_size, ainfo, TRUE);
1055 break;
1056 case MONO_TYPE_VAR:
1057 case MONO_TYPE_MVAR:
1058 /* gsharedvt arguments are passed by ref */
1059 g_assert (mini_is_gsharedvt_type (ptype));
1060 add_general (&gr, &stack_size, ainfo);
1061 if (ainfo->storage == ArgInIReg)
1062 ainfo->storage = ArgGSharedVtInReg;
1063 else
1064 ainfo->storage = ArgGSharedVtOnStack;
1065 break;
1066 default:
1067 g_assert_not_reached ();
1068 }
1069 }
1070
1071 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1072 gr = PARAM_REGS;
1073 fr = FLOAT_PARAM_REGS;
1074
1075 /* Emit the signature cookie just before the implicit arguments */
1076 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1077 }
1078
1079 cinfo->stack_usage = stack_size;
1080 cinfo->reg_usage = gr;
1081 cinfo->freg_usage = fr;
1082 return cinfo;
1083 }
1084
1085 /*
1086 * mono_arch_get_argument_info:
1087 * @csig: a method signature
1088 * @param_count: the number of parameters to consider
1089 * @arg_info: an array to store the result infos
1090 *
1091 * Gathers information on parameters such as size, alignment and
1092 * padding. arg_info should be large enought to hold param_count + 1 entries.
1093 *
1094 * Returns the size of the argument area on the stack.
1095 */
1096 int
mono_arch_get_argument_info(MonoMethodSignature * csig,int param_count,MonoJitArgumentInfo * arg_info)1097 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1098 {
1099 int k;
1100 CallInfo *cinfo = get_call_info (NULL, csig);
1101 guint32 args_size = cinfo->stack_usage;
1102
1103 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1104 if (csig->hasthis) {
1105 arg_info [0].offset = 0;
1106 }
1107
1108 for (k = 0; k < param_count; k++) {
1109 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1110 /* FIXME: */
1111 arg_info [k + 1].size = 0;
1112 }
1113
1114 g_free (cinfo);
1115
1116 return args_size;
1117 }
1118
1119 gboolean
mono_arch_tail_call_supported(MonoCompile * cfg,MonoMethodSignature * caller_sig,MonoMethodSignature * callee_sig)1120 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1121 {
1122 CallInfo *c1, *c2;
1123 gboolean res;
1124 MonoType *callee_ret;
1125
1126 c1 = get_call_info (NULL, caller_sig);
1127 c2 = get_call_info (NULL, callee_sig);
1128 res = c1->stack_usage >= c2->stack_usage;
1129 callee_ret = mini_get_underlying_type (callee_sig->ret);
1130 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1131 /* An address on the callee's stack is passed as the first argument */
1132 res = FALSE;
1133
1134 g_free (c1);
1135 g_free (c2);
1136
1137 return res;
1138 }
1139
1140 /*
1141 * Initialize the cpu to execute managed code.
1142 */
1143 void
mono_arch_cpu_init(void)1144 mono_arch_cpu_init (void)
1145 {
1146 #ifndef _MSC_VER
1147 guint16 fpcw;
1148
1149 /* spec compliance requires running with double precision */
1150 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1151 fpcw &= ~X86_FPCW_PRECC_MASK;
1152 fpcw |= X86_FPCW_PREC_DOUBLE;
1153 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1154 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1155 #else
1156 /* TODO: This is crashing on Win64 right now.
1157 * _control87 (_PC_53, MCW_PC);
1158 */
1159 #endif
1160 }
1161
1162 /*
1163 * Initialize architecture specific code.
1164 */
1165 void
mono_arch_init(void)1166 mono_arch_init (void)
1167 {
1168 mono_os_mutex_init_recursive (&mini_arch_mutex);
1169
1170 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1171 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1172 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1173
1174 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1175 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1176 #endif
1177
1178 if (!mono_aot_only)
1179 bp_trampoline = mini_get_breakpoint_trampoline ();
1180 }
1181
1182 /*
1183 * Cleanup architecture specific code.
1184 */
1185 void
mono_arch_cleanup(void)1186 mono_arch_cleanup (void)
1187 {
1188 mono_os_mutex_destroy (&mini_arch_mutex);
1189 }
1190
1191 /*
1192 * This function returns the optimizations supported on this cpu.
1193 */
1194 guint32
mono_arch_cpu_optimizations(guint32 * exclude_mask)1195 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1196 {
1197 guint32 opts = 0;
1198
1199 *exclude_mask = 0;
1200
1201 if (mono_hwcap_x86_has_cmov) {
1202 opts |= MONO_OPT_CMOV;
1203
1204 if (mono_hwcap_x86_has_fcmov)
1205 opts |= MONO_OPT_FCMOV;
1206 else
1207 *exclude_mask |= MONO_OPT_FCMOV;
1208 } else {
1209 *exclude_mask |= MONO_OPT_CMOV;
1210 }
1211
1212 #ifdef TARGET_WIN32
1213 /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1214 /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1215 /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1216 /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1217 /* will now have a reference to an argument that won't be fully decomposed. */
1218 *exclude_mask |= MONO_OPT_SIMD;
1219 #endif
1220
1221 return opts;
1222 }
1223
1224 /*
1225 * This function test for all SSE functions supported.
1226 *
1227 * Returns a bitmask corresponding to all supported versions.
1228 *
1229 */
1230 guint32
mono_arch_cpu_enumerate_simd_versions(void)1231 mono_arch_cpu_enumerate_simd_versions (void)
1232 {
1233 guint32 sse_opts = 0;
1234
1235 if (mono_hwcap_x86_has_sse1)
1236 sse_opts |= SIMD_VERSION_SSE1;
1237
1238 if (mono_hwcap_x86_has_sse2)
1239 sse_opts |= SIMD_VERSION_SSE2;
1240
1241 if (mono_hwcap_x86_has_sse3)
1242 sse_opts |= SIMD_VERSION_SSE3;
1243
1244 if (mono_hwcap_x86_has_ssse3)
1245 sse_opts |= SIMD_VERSION_SSSE3;
1246
1247 if (mono_hwcap_x86_has_sse41)
1248 sse_opts |= SIMD_VERSION_SSE41;
1249
1250 if (mono_hwcap_x86_has_sse42)
1251 sse_opts |= SIMD_VERSION_SSE42;
1252
1253 if (mono_hwcap_x86_has_sse4a)
1254 sse_opts |= SIMD_VERSION_SSE4a;
1255
1256 return sse_opts;
1257 }
1258
1259 #ifndef DISABLE_JIT
1260
1261 GList *
mono_arch_get_allocatable_int_vars(MonoCompile * cfg)1262 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1263 {
1264 GList *vars = NULL;
1265 int i;
1266
1267 for (i = 0; i < cfg->num_varinfo; i++) {
1268 MonoInst *ins = cfg->varinfo [i];
1269 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1270
1271 /* unused vars */
1272 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1273 continue;
1274
1275 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1276 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1277 continue;
1278
1279 if (mono_is_regsize_var (ins->inst_vtype)) {
1280 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1281 g_assert (i == vmv->idx);
1282 vars = g_list_prepend (vars, vmv);
1283 }
1284 }
1285
1286 vars = mono_varlist_sort (cfg, vars, 0);
1287
1288 return vars;
1289 }
1290
1291 /**
1292 * mono_arch_compute_omit_fp:
1293 * Determine whether the frame pointer can be eliminated.
1294 */
1295 static void
mono_arch_compute_omit_fp(MonoCompile * cfg)1296 mono_arch_compute_omit_fp (MonoCompile *cfg)
1297 {
1298 MonoMethodSignature *sig;
1299 MonoMethodHeader *header;
1300 int i, locals_size;
1301 CallInfo *cinfo;
1302
1303 if (cfg->arch.omit_fp_computed)
1304 return;
1305
1306 header = cfg->header;
1307
1308 sig = mono_method_signature (cfg->method);
1309
1310 if (!cfg->arch.cinfo)
1311 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1312 cinfo = (CallInfo *)cfg->arch.cinfo;
1313
1314 /*
1315 * FIXME: Remove some of the restrictions.
1316 */
1317 cfg->arch.omit_fp = TRUE;
1318 cfg->arch.omit_fp_computed = TRUE;
1319
1320 if (cfg->disable_omit_fp)
1321 cfg->arch.omit_fp = FALSE;
1322
1323 if (!debug_omit_fp ())
1324 cfg->arch.omit_fp = FALSE;
1325 /*
1326 if (cfg->method->save_lmf)
1327 cfg->arch.omit_fp = FALSE;
1328 */
1329 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1330 cfg->arch.omit_fp = FALSE;
1331 if (header->num_clauses)
1332 cfg->arch.omit_fp = FALSE;
1333 if (cfg->param_area)
1334 cfg->arch.omit_fp = FALSE;
1335 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1336 cfg->arch.omit_fp = FALSE;
1337 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)))
1338 cfg->arch.omit_fp = FALSE;
1339 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1340 ArgInfo *ainfo = &cinfo->args [i];
1341
1342 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1343 /*
1344 * The stack offset can only be determined when the frame
1345 * size is known.
1346 */
1347 cfg->arch.omit_fp = FALSE;
1348 }
1349 }
1350
1351 locals_size = 0;
1352 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1353 MonoInst *ins = cfg->varinfo [i];
1354 int ialign;
1355
1356 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1357 }
1358 }
1359
1360 GList *
mono_arch_get_global_int_regs(MonoCompile * cfg)1361 mono_arch_get_global_int_regs (MonoCompile *cfg)
1362 {
1363 GList *regs = NULL;
1364
1365 mono_arch_compute_omit_fp (cfg);
1366
1367 if (cfg->arch.omit_fp)
1368 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1369
1370 /* We use the callee saved registers for global allocation */
1371 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1372 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1373 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1374 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1375 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1376 #ifdef TARGET_WIN32
1377 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1378 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1379 #endif
1380
1381 return regs;
1382 }
1383
1384 GList*
mono_arch_get_global_fp_regs(MonoCompile * cfg)1385 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1386 {
1387 GList *regs = NULL;
1388 int i;
1389
1390 /* All XMM registers */
1391 for (i = 0; i < 16; ++i)
1392 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1393
1394 return regs;
1395 }
1396
1397 GList*
mono_arch_get_iregs_clobbered_by_call(MonoCallInst * call)1398 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1399 {
1400 static GList *r = NULL;
1401
1402 if (r == NULL) {
1403 GList *regs = NULL;
1404
1405 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1406 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1407 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1408 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1409 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1410 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1411
1412 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1413 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1414 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1415 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1416 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1417 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1418 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1419 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1420
1421 mono_atomic_cas_ptr ((gpointer*)&r, regs, NULL);
1422 }
1423
1424 return r;
1425 }
1426
1427 GList*
mono_arch_get_fregs_clobbered_by_call(MonoCallInst * call)1428 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1429 {
1430 int i;
1431 static GList *r = NULL;
1432
1433 if (r == NULL) {
1434 GList *regs = NULL;
1435
1436 for (i = 0; i < AMD64_XMM_NREG; ++i)
1437 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1438
1439 mono_atomic_cas_ptr ((gpointer*)&r, regs, NULL);
1440 }
1441
1442 return r;
1443 }
1444
1445 /*
1446 * mono_arch_regalloc_cost:
1447 *
1448 * Return the cost, in number of memory references, of the action of
1449 * allocating the variable VMV into a register during global register
1450 * allocation.
1451 */
1452 guint32
mono_arch_regalloc_cost(MonoCompile * cfg,MonoMethodVar * vmv)1453 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1454 {
1455 MonoInst *ins = cfg->varinfo [vmv->idx];
1456
1457 if (cfg->method->save_lmf)
1458 /* The register is already saved */
1459 /* substract 1 for the invisible store in the prolog */
1460 return (ins->opcode == OP_ARG) ? 0 : 1;
1461 else
1462 /* push+pop */
1463 return (ins->opcode == OP_ARG) ? 1 : 2;
1464 }
1465
1466 /*
1467 * mono_arch_fill_argument_info:
1468 *
1469 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1470 * of the method.
1471 */
1472 void
mono_arch_fill_argument_info(MonoCompile * cfg)1473 mono_arch_fill_argument_info (MonoCompile *cfg)
1474 {
1475 MonoType *sig_ret;
1476 MonoMethodSignature *sig;
1477 MonoInst *ins;
1478 int i;
1479 CallInfo *cinfo;
1480
1481 sig = mono_method_signature (cfg->method);
1482
1483 cinfo = (CallInfo *)cfg->arch.cinfo;
1484 sig_ret = mini_get_underlying_type (sig->ret);
1485
1486 /*
1487 * Contrary to mono_arch_allocate_vars (), the information should describe
1488 * where the arguments are at the beginning of the method, not where they can be
1489 * accessed during the execution of the method. The later makes no sense for the
1490 * global register allocator, since a variable can be in more than one location.
1491 */
1492 switch (cinfo->ret.storage) {
1493 case ArgInIReg:
1494 case ArgInFloatSSEReg:
1495 case ArgInDoubleSSEReg:
1496 cfg->ret->opcode = OP_REGVAR;
1497 cfg->ret->inst_c0 = cinfo->ret.reg;
1498 break;
1499 case ArgValuetypeInReg:
1500 cfg->ret->opcode = OP_REGOFFSET;
1501 cfg->ret->inst_basereg = -1;
1502 cfg->ret->inst_offset = -1;
1503 break;
1504 case ArgNone:
1505 break;
1506 default:
1507 g_assert_not_reached ();
1508 }
1509
1510 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1511 ArgInfo *ainfo = &cinfo->args [i];
1512
1513 ins = cfg->args [i];
1514
1515 switch (ainfo->storage) {
1516 case ArgInIReg:
1517 case ArgInFloatSSEReg:
1518 case ArgInDoubleSSEReg:
1519 ins->opcode = OP_REGVAR;
1520 ins->inst_c0 = ainfo->reg;
1521 break;
1522 case ArgOnStack:
1523 ins->opcode = OP_REGOFFSET;
1524 ins->inst_basereg = -1;
1525 ins->inst_offset = -1;
1526 break;
1527 case ArgValuetypeInReg:
1528 /* Dummy */
1529 ins->opcode = OP_NOP;
1530 break;
1531 default:
1532 g_assert_not_reached ();
1533 }
1534 }
1535 }
1536
1537 void
mono_arch_allocate_vars(MonoCompile * cfg)1538 mono_arch_allocate_vars (MonoCompile *cfg)
1539 {
1540 MonoType *sig_ret;
1541 MonoMethodSignature *sig;
1542 MonoInst *ins;
1543 int i, offset;
1544 guint32 locals_stack_size, locals_stack_align;
1545 gint32 *offsets;
1546 CallInfo *cinfo;
1547
1548 sig = mono_method_signature (cfg->method);
1549
1550 cinfo = (CallInfo *)cfg->arch.cinfo;
1551 sig_ret = mini_get_underlying_type (sig->ret);
1552
1553 mono_arch_compute_omit_fp (cfg);
1554
1555 /*
1556 * We use the ABI calling conventions for managed code as well.
1557 * Exception: valuetypes are only sometimes passed or returned in registers.
1558 */
1559
1560 /*
1561 * The stack looks like this:
1562 * <incoming arguments passed on the stack>
1563 * <return value>
1564 * <lmf/caller saved registers>
1565 * <locals>
1566 * <spill area>
1567 * <localloc area> -> grows dynamically
1568 * <params area>
1569 */
1570
1571 if (cfg->arch.omit_fp) {
1572 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1573 cfg->frame_reg = AMD64_RSP;
1574 offset = 0;
1575 } else {
1576 /* Locals are allocated backwards from %fp */
1577 cfg->frame_reg = AMD64_RBP;
1578 offset = 0;
1579 }
1580
1581 cfg->arch.saved_iregs = cfg->used_int_regs;
1582 if (cfg->method->save_lmf) {
1583 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1584 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1585 cfg->arch.saved_iregs |= iregs_to_save;
1586 }
1587
1588 if (cfg->arch.omit_fp)
1589 cfg->arch.reg_save_area_offset = offset;
1590 /* Reserve space for callee saved registers */
1591 for (i = 0; i < AMD64_NREG; ++i)
1592 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1593 offset += sizeof(mgreg_t);
1594 }
1595 if (!cfg->arch.omit_fp)
1596 cfg->arch.reg_save_area_offset = -offset;
1597
1598 if (sig_ret->type != MONO_TYPE_VOID) {
1599 switch (cinfo->ret.storage) {
1600 case ArgInIReg:
1601 case ArgInFloatSSEReg:
1602 case ArgInDoubleSSEReg:
1603 cfg->ret->opcode = OP_REGVAR;
1604 cfg->ret->inst_c0 = cinfo->ret.reg;
1605 cfg->ret->dreg = cinfo->ret.reg;
1606 break;
1607 case ArgValuetypeAddrInIReg:
1608 case ArgGsharedvtVariableInReg:
1609 /* The register is volatile */
1610 cfg->vret_addr->opcode = OP_REGOFFSET;
1611 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1612 if (cfg->arch.omit_fp) {
1613 cfg->vret_addr->inst_offset = offset;
1614 offset += 8;
1615 } else {
1616 offset += 8;
1617 cfg->vret_addr->inst_offset = -offset;
1618 }
1619 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1620 printf ("vret_addr =");
1621 mono_print_ins (cfg->vret_addr);
1622 }
1623 break;
1624 case ArgValuetypeInReg:
1625 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1626 cfg->ret->opcode = OP_REGOFFSET;
1627 cfg->ret->inst_basereg = cfg->frame_reg;
1628 if (cfg->arch.omit_fp) {
1629 cfg->ret->inst_offset = offset;
1630 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1631 } else {
1632 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1633 cfg->ret->inst_offset = - offset;
1634 }
1635 break;
1636 default:
1637 g_assert_not_reached ();
1638 }
1639 }
1640
1641 /* Allocate locals */
1642 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1643 if (locals_stack_align) {
1644 offset += (locals_stack_align - 1);
1645 offset &= ~(locals_stack_align - 1);
1646 }
1647 if (cfg->arch.omit_fp) {
1648 cfg->locals_min_stack_offset = offset;
1649 cfg->locals_max_stack_offset = offset + locals_stack_size;
1650 } else {
1651 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1652 cfg->locals_max_stack_offset = - offset;
1653 }
1654
1655 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1656 if (offsets [i] != -1) {
1657 MonoInst *ins = cfg->varinfo [i];
1658 ins->opcode = OP_REGOFFSET;
1659 ins->inst_basereg = cfg->frame_reg;
1660 if (cfg->arch.omit_fp)
1661 ins->inst_offset = (offset + offsets [i]);
1662 else
1663 ins->inst_offset = - (offset + offsets [i]);
1664 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1665 }
1666 }
1667 offset += locals_stack_size;
1668
1669 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1670 g_assert (!cfg->arch.omit_fp);
1671 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1672 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1673 }
1674
1675 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1676 ins = cfg->args [i];
1677 if (ins->opcode != OP_REGVAR) {
1678 ArgInfo *ainfo = &cinfo->args [i];
1679 gboolean inreg = TRUE;
1680
1681 /* FIXME: Allocate volatile arguments to registers */
1682 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1683 inreg = FALSE;
1684
1685 /*
1686 * Under AMD64, all registers used to pass arguments to functions
1687 * are volatile across calls.
1688 * FIXME: Optimize this.
1689 */
1690 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1691 inreg = FALSE;
1692
1693 ins->opcode = OP_REGOFFSET;
1694
1695 switch (ainfo->storage) {
1696 case ArgInIReg:
1697 case ArgInFloatSSEReg:
1698 case ArgInDoubleSSEReg:
1699 case ArgGSharedVtInReg:
1700 if (inreg) {
1701 ins->opcode = OP_REGVAR;
1702 ins->dreg = ainfo->reg;
1703 }
1704 break;
1705 case ArgOnStack:
1706 case ArgGSharedVtOnStack:
1707 g_assert (!cfg->arch.omit_fp);
1708 ins->opcode = OP_REGOFFSET;
1709 ins->inst_basereg = cfg->frame_reg;
1710 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1711 break;
1712 case ArgValuetypeInReg:
1713 break;
1714 case ArgValuetypeAddrInIReg:
1715 case ArgValuetypeAddrOnStack: {
1716 MonoInst *indir;
1717 g_assert (!cfg->arch.omit_fp);
1718 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1719 MONO_INST_NEW (cfg, indir, 0);
1720
1721 indir->opcode = OP_REGOFFSET;
1722 if (ainfo->pair_storage [0] == ArgInIReg) {
1723 indir->inst_basereg = cfg->frame_reg;
1724 offset = ALIGN_TO (offset, sizeof (gpointer));
1725 offset += (sizeof (gpointer));
1726 indir->inst_offset = - offset;
1727 }
1728 else {
1729 indir->inst_basereg = cfg->frame_reg;
1730 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1731 }
1732
1733 ins->opcode = OP_VTARG_ADDR;
1734 ins->inst_left = indir;
1735
1736 break;
1737 }
1738 default:
1739 NOT_IMPLEMENTED;
1740 }
1741
1742 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1743 ins->opcode = OP_REGOFFSET;
1744 ins->inst_basereg = cfg->frame_reg;
1745 /* These arguments are saved to the stack in the prolog */
1746 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1747 if (cfg->arch.omit_fp) {
1748 ins->inst_offset = offset;
1749 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1750 // Arguments are yet supported by the stack map creation code
1751 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1752 } else {
1753 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1754 ins->inst_offset = - offset;
1755 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1756 }
1757 }
1758 }
1759 }
1760
1761 cfg->stack_offset = offset;
1762 }
1763
1764 void
mono_arch_create_vars(MonoCompile * cfg)1765 mono_arch_create_vars (MonoCompile *cfg)
1766 {
1767 MonoMethodSignature *sig;
1768 CallInfo *cinfo;
1769 MonoType *sig_ret;
1770
1771 sig = mono_method_signature (cfg->method);
1772
1773 if (!cfg->arch.cinfo)
1774 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1775 cinfo = (CallInfo *)cfg->arch.cinfo;
1776
1777 if (cinfo->ret.storage == ArgValuetypeInReg)
1778 cfg->ret_var_is_local = TRUE;
1779
1780 sig_ret = mini_get_underlying_type (sig->ret);
1781 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1782 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1783 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1784 printf ("vret_addr = ");
1785 mono_print_ins (cfg->vret_addr);
1786 }
1787 }
1788
1789 if (cfg->gen_sdb_seq_points) {
1790 MonoInst *ins;
1791
1792 if (cfg->compile_aot) {
1793 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1794 ins->flags |= MONO_INST_VOLATILE;
1795 cfg->arch.seq_point_info_var = ins;
1796 }
1797 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1798 ins->flags |= MONO_INST_VOLATILE;
1799 cfg->arch.ss_tramp_var = ins;
1800
1801 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1802 ins->flags |= MONO_INST_VOLATILE;
1803 cfg->arch.bp_tramp_var = ins;
1804 }
1805
1806 if (cfg->method->save_lmf)
1807 cfg->create_lmf_var = TRUE;
1808
1809 if (cfg->method->save_lmf) {
1810 cfg->lmf_ir = TRUE;
1811 }
1812 }
1813
1814 static void
add_outarg_reg(MonoCompile * cfg,MonoCallInst * call,ArgStorage storage,int reg,MonoInst * tree)1815 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1816 {
1817 MonoInst *ins;
1818
1819 switch (storage) {
1820 case ArgInIReg:
1821 MONO_INST_NEW (cfg, ins, OP_MOVE);
1822 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1823 ins->sreg1 = tree->dreg;
1824 MONO_ADD_INS (cfg->cbb, ins);
1825 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1826 break;
1827 case ArgInFloatSSEReg:
1828 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1829 ins->dreg = mono_alloc_freg (cfg);
1830 ins->sreg1 = tree->dreg;
1831 MONO_ADD_INS (cfg->cbb, ins);
1832
1833 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1834 break;
1835 case ArgInDoubleSSEReg:
1836 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1837 ins->dreg = mono_alloc_freg (cfg);
1838 ins->sreg1 = tree->dreg;
1839 MONO_ADD_INS (cfg->cbb, ins);
1840
1841 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1842
1843 break;
1844 default:
1845 g_assert_not_reached ();
1846 }
1847 }
1848
1849 static int
arg_storage_to_load_membase(ArgStorage storage)1850 arg_storage_to_load_membase (ArgStorage storage)
1851 {
1852 switch (storage) {
1853 case ArgInIReg:
1854 #if defined(__mono_ilp32__)
1855 return OP_LOADI8_MEMBASE;
1856 #else
1857 return OP_LOAD_MEMBASE;
1858 #endif
1859 case ArgInDoubleSSEReg:
1860 return OP_LOADR8_MEMBASE;
1861 case ArgInFloatSSEReg:
1862 return OP_LOADR4_MEMBASE;
1863 default:
1864 g_assert_not_reached ();
1865 }
1866
1867 return -1;
1868 }
1869
1870 static void
emit_sig_cookie(MonoCompile * cfg,MonoCallInst * call,CallInfo * cinfo)1871 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1872 {
1873 MonoMethodSignature *tmp_sig;
1874 int sig_reg;
1875
1876 if (call->tail_call)
1877 NOT_IMPLEMENTED;
1878
1879 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1880
1881 /*
1882 * mono_ArgIterator_Setup assumes the signature cookie is
1883 * passed first and all the arguments which were before it are
1884 * passed on the stack after the signature. So compensate by
1885 * passing a different signature.
1886 */
1887 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1888 tmp_sig->param_count -= call->signature->sentinelpos;
1889 tmp_sig->sentinelpos = 0;
1890 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1891
1892 sig_reg = mono_alloc_ireg (cfg);
1893 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1894
1895 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1896 }
1897
1898 #ifdef ENABLE_LLVM
1899 static inline LLVMArgStorage
arg_storage_to_llvm_arg_storage(MonoCompile * cfg,ArgStorage storage)1900 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1901 {
1902 switch (storage) {
1903 case ArgInIReg:
1904 return LLVMArgInIReg;
1905 case ArgNone:
1906 return LLVMArgNone;
1907 case ArgGSharedVtInReg:
1908 case ArgGSharedVtOnStack:
1909 return LLVMArgGSharedVt;
1910 default:
1911 g_assert_not_reached ();
1912 return LLVMArgNone;
1913 }
1914 }
1915
1916 LLVMCallInfo*
mono_arch_get_llvm_call_info(MonoCompile * cfg,MonoMethodSignature * sig)1917 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1918 {
1919 int i, n;
1920 CallInfo *cinfo;
1921 ArgInfo *ainfo;
1922 int j;
1923 LLVMCallInfo *linfo;
1924 MonoType *t, *sig_ret;
1925
1926 n = sig->param_count + sig->hasthis;
1927 sig_ret = mini_get_underlying_type (sig->ret);
1928
1929 cinfo = get_call_info (cfg->mempool, sig);
1930
1931 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1932
1933 /*
1934 * LLVM always uses the native ABI while we use our own ABI, the
1935 * only difference is the handling of vtypes:
1936 * - we only pass/receive them in registers in some cases, and only
1937 * in 1 or 2 integer registers.
1938 */
1939 switch (cinfo->ret.storage) {
1940 case ArgNone:
1941 linfo->ret.storage = LLVMArgNone;
1942 break;
1943 case ArgInIReg:
1944 case ArgInFloatSSEReg:
1945 case ArgInDoubleSSEReg:
1946 linfo->ret.storage = LLVMArgNormal;
1947 break;
1948 case ArgValuetypeInReg: {
1949 ainfo = &cinfo->ret;
1950
1951 if (sig->pinvoke &&
1952 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1953 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1954 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1955 cfg->disable_llvm = TRUE;
1956 return linfo;
1957 }
1958
1959 linfo->ret.storage = LLVMArgVtypeInReg;
1960 for (j = 0; j < 2; ++j)
1961 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1962 break;
1963 }
1964 case ArgValuetypeAddrInIReg:
1965 case ArgGsharedvtVariableInReg:
1966 /* Vtype returned using a hidden argument */
1967 linfo->ret.storage = LLVMArgVtypeRetAddr;
1968 linfo->vret_arg_index = cinfo->vret_arg_index;
1969 break;
1970 default:
1971 g_assert_not_reached ();
1972 break;
1973 }
1974
1975 for (i = 0; i < n; ++i) {
1976 ainfo = cinfo->args + i;
1977
1978 if (i >= sig->hasthis)
1979 t = sig->params [i - sig->hasthis];
1980 else
1981 t = &mono_defaults.int_class->byval_arg;
1982 t = mini_type_get_underlying_type (t);
1983
1984 linfo->args [i].storage = LLVMArgNone;
1985
1986 switch (ainfo->storage) {
1987 case ArgInIReg:
1988 linfo->args [i].storage = LLVMArgNormal;
1989 break;
1990 case ArgInDoubleSSEReg:
1991 case ArgInFloatSSEReg:
1992 linfo->args [i].storage = LLVMArgNormal;
1993 break;
1994 case ArgOnStack:
1995 if (MONO_TYPE_ISSTRUCT (t))
1996 linfo->args [i].storage = LLVMArgVtypeByVal;
1997 else
1998 linfo->args [i].storage = LLVMArgNormal;
1999 break;
2000 case ArgValuetypeInReg:
2001 if (sig->pinvoke &&
2002 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2003 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2004 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2005 cfg->disable_llvm = TRUE;
2006 return linfo;
2007 }
2008
2009 linfo->args [i].storage = LLVMArgVtypeInReg;
2010 for (j = 0; j < 2; ++j)
2011 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2012 break;
2013 case ArgGSharedVtInReg:
2014 case ArgGSharedVtOnStack:
2015 linfo->args [i].storage = LLVMArgGSharedVt;
2016 break;
2017 default:
2018 cfg->exception_message = g_strdup ("ainfo->storage");
2019 cfg->disable_llvm = TRUE;
2020 break;
2021 }
2022 }
2023
2024 return linfo;
2025 }
2026 #endif
2027
2028 void
mono_arch_emit_call(MonoCompile * cfg,MonoCallInst * call)2029 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2030 {
2031 MonoInst *arg, *in;
2032 MonoMethodSignature *sig;
2033 MonoType *sig_ret;
2034 int i, n;
2035 CallInfo *cinfo;
2036 ArgInfo *ainfo;
2037
2038 sig = call->signature;
2039 n = sig->param_count + sig->hasthis;
2040
2041 cinfo = get_call_info (cfg->mempool, sig);
2042
2043 sig_ret = sig->ret;
2044
2045 if (COMPILE_LLVM (cfg)) {
2046 /* We shouldn't be called in the llvm case */
2047 cfg->disable_llvm = TRUE;
2048 return;
2049 }
2050
2051 /*
2052 * Emit all arguments which are passed on the stack to prevent register
2053 * allocation problems.
2054 */
2055 for (i = 0; i < n; ++i) {
2056 MonoType *t;
2057 ainfo = cinfo->args + i;
2058
2059 in = call->args [i];
2060
2061 if (sig->hasthis && i == 0)
2062 t = &mono_defaults.object_class->byval_arg;
2063 else
2064 t = sig->params [i - sig->hasthis];
2065
2066 t = mini_get_underlying_type (t);
2067 //XXX what about ArgGSharedVtOnStack here?
2068 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2069 if (!t->byref) {
2070 if (t->type == MONO_TYPE_R4)
2071 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2072 else if (t->type == MONO_TYPE_R8)
2073 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2074 else
2075 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2076 } else {
2077 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2078 }
2079 if (cfg->compute_gc_maps) {
2080 MonoInst *def;
2081
2082 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2083 }
2084 }
2085 }
2086
2087 /*
2088 * Emit all parameters passed in registers in non-reverse order for better readability
2089 * and to help the optimization in emit_prolog ().
2090 */
2091 for (i = 0; i < n; ++i) {
2092 ainfo = cinfo->args + i;
2093
2094 in = call->args [i];
2095
2096 if (ainfo->storage == ArgInIReg)
2097 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2098 }
2099
2100 for (i = n - 1; i >= 0; --i) {
2101 MonoType *t;
2102
2103 ainfo = cinfo->args + i;
2104
2105 in = call->args [i];
2106
2107 if (sig->hasthis && i == 0)
2108 t = &mono_defaults.object_class->byval_arg;
2109 else
2110 t = sig->params [i - sig->hasthis];
2111 t = mini_get_underlying_type (t);
2112
2113 switch (ainfo->storage) {
2114 case ArgInIReg:
2115 /* Already done */
2116 break;
2117 case ArgInFloatSSEReg:
2118 case ArgInDoubleSSEReg:
2119 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2120 break;
2121 case ArgOnStack:
2122 case ArgValuetypeInReg:
2123 case ArgValuetypeAddrInIReg:
2124 case ArgValuetypeAddrOnStack:
2125 case ArgGSharedVtInReg:
2126 case ArgGSharedVtOnStack: {
2127 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2128 /* Already emitted above */
2129 break;
2130 //FIXME what about ArgGSharedVtOnStack ?
2131 if (ainfo->storage == ArgOnStack && call->tail_call) {
2132 MonoInst *call_inst = (MonoInst*)call;
2133 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2134 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2135 break;
2136 }
2137
2138 guint32 align;
2139 guint32 size;
2140
2141 if (sig->pinvoke)
2142 size = mono_type_native_stack_size (t, &align);
2143 else {
2144 /*
2145 * Other backends use mono_type_stack_size (), but that
2146 * aligns the size to 8, which is larger than the size of
2147 * the source, leading to reads of invalid memory if the
2148 * source is at the end of address space.
2149 */
2150 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2151 }
2152
2153 if (size >= 10000) {
2154 /* Avoid asserts in emit_memcpy () */
2155 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2156 /* Continue normally */
2157 }
2158
2159 if (size > 0 || ainfo->pass_empty_struct) {
2160 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2161 arg->sreg1 = in->dreg;
2162 arg->klass = mono_class_from_mono_type (t);
2163 arg->backend.size = size;
2164 arg->inst_p0 = call;
2165 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2166 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2167
2168 MONO_ADD_INS (cfg->cbb, arg);
2169 }
2170 break;
2171 }
2172 default:
2173 g_assert_not_reached ();
2174 }
2175
2176 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2177 /* Emit the signature cookie just before the implicit arguments */
2178 emit_sig_cookie (cfg, call, cinfo);
2179 }
2180
2181 /* Handle the case where there are no implicit arguments */
2182 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2183 emit_sig_cookie (cfg, call, cinfo);
2184
2185 switch (cinfo->ret.storage) {
2186 case ArgValuetypeInReg:
2187 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2188 /*
2189 * Tell the JIT to use a more efficient calling convention: call using
2190 * OP_CALL, compute the result location after the call, and save the
2191 * result there.
2192 */
2193 call->vret_in_reg = TRUE;
2194 /*
2195 * Nullify the instruction computing the vret addr to enable
2196 * future optimizations.
2197 */
2198 if (call->vret_var)
2199 NULLIFY_INS (call->vret_var);
2200 } else {
2201 if (call->tail_call)
2202 NOT_IMPLEMENTED;
2203 /*
2204 * The valuetype is in RAX:RDX after the call, need to be copied to
2205 * the stack. Push the address here, so the call instruction can
2206 * access it.
2207 */
2208 if (!cfg->arch.vret_addr_loc) {
2209 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2210 /* Prevent it from being register allocated or optimized away */
2211 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2212 }
2213
2214 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2215 }
2216 break;
2217 case ArgValuetypeAddrInIReg:
2218 case ArgGsharedvtVariableInReg: {
2219 MonoInst *vtarg;
2220 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2221 vtarg->sreg1 = call->vret_var->dreg;
2222 vtarg->dreg = mono_alloc_preg (cfg);
2223 MONO_ADD_INS (cfg->cbb, vtarg);
2224
2225 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2226 break;
2227 }
2228 default:
2229 break;
2230 }
2231
2232 if (cfg->method->save_lmf) {
2233 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2234 MONO_ADD_INS (cfg->cbb, arg);
2235 }
2236
2237 call->stack_usage = cinfo->stack_usage;
2238 }
2239
2240 void
mono_arch_emit_outarg_vt(MonoCompile * cfg,MonoInst * ins,MonoInst * src)2241 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2242 {
2243 MonoInst *arg;
2244 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2245 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2246 int size = ins->backend.size;
2247
2248 switch (ainfo->storage) {
2249 case ArgValuetypeInReg: {
2250 MonoInst *load;
2251 int part;
2252
2253 for (part = 0; part < 2; ++part) {
2254 if (ainfo->pair_storage [part] == ArgNone)
2255 continue;
2256
2257 if (ainfo->pass_empty_struct) {
2258 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2259 NEW_ICONST (cfg, load, 0);
2260 }
2261 else {
2262 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2263 load->inst_basereg = src->dreg;
2264 load->inst_offset = part * sizeof(mgreg_t);
2265
2266 switch (ainfo->pair_storage [part]) {
2267 case ArgInIReg:
2268 load->dreg = mono_alloc_ireg (cfg);
2269 break;
2270 case ArgInDoubleSSEReg:
2271 case ArgInFloatSSEReg:
2272 load->dreg = mono_alloc_freg (cfg);
2273 break;
2274 default:
2275 g_assert_not_reached ();
2276 }
2277 }
2278
2279 MONO_ADD_INS (cfg->cbb, load);
2280
2281 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2282 }
2283 break;
2284 }
2285 case ArgValuetypeAddrInIReg:
2286 case ArgValuetypeAddrOnStack: {
2287 MonoInst *vtaddr, *load;
2288
2289 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2290
2291 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2292
2293 MONO_INST_NEW (cfg, load, OP_LDADDR);
2294 cfg->has_indirection = TRUE;
2295 load->inst_p0 = vtaddr;
2296 vtaddr->flags |= MONO_INST_INDIRECT;
2297 load->type = STACK_MP;
2298 load->klass = vtaddr->klass;
2299 load->dreg = mono_alloc_ireg (cfg);
2300 MONO_ADD_INS (cfg->cbb, load);
2301 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, SIZEOF_VOID_P);
2302
2303 if (ainfo->pair_storage [0] == ArgInIReg) {
2304 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2305 arg->dreg = mono_alloc_ireg (cfg);
2306 arg->sreg1 = load->dreg;
2307 arg->inst_imm = 0;
2308 MONO_ADD_INS (cfg->cbb, arg);
2309 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2310 } else {
2311 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2312 }
2313 break;
2314 }
2315 case ArgGSharedVtInReg:
2316 /* Pass by addr */
2317 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2318 break;
2319 case ArgGSharedVtOnStack:
2320 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2321 break;
2322 default:
2323 if (size == 8) {
2324 int dreg = mono_alloc_ireg (cfg);
2325
2326 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2327 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2328 } else if (size <= 40) {
2329 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2330 } else {
2331 // FIXME: Code growth
2332 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2333 }
2334
2335 if (cfg->compute_gc_maps) {
2336 MonoInst *def;
2337 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2338 }
2339 }
2340 }
2341
2342 void
mono_arch_emit_setret(MonoCompile * cfg,MonoMethod * method,MonoInst * val)2343 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2344 {
2345 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2346
2347 if (ret->type == MONO_TYPE_R4) {
2348 if (COMPILE_LLVM (cfg))
2349 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2350 else
2351 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2352 return;
2353 } else if (ret->type == MONO_TYPE_R8) {
2354 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2355 return;
2356 }
2357
2358 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2359 }
2360
2361 #endif /* DISABLE_JIT */
2362
2363 #define EMIT_COND_BRANCH(ins,cond,sign) \
2364 if (ins->inst_true_bb->native_offset) { \
2365 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2366 } else { \
2367 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2368 if ((cfg->opt & MONO_OPT_BRANCH) && \
2369 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2370 x86_branch8 (code, cond, 0, sign); \
2371 else \
2372 x86_branch32 (code, cond, 0, sign); \
2373 }
2374
2375 typedef struct {
2376 MonoMethodSignature *sig;
2377 CallInfo *cinfo;
2378 int nstack_args;
2379 } ArchDynCallInfo;
2380
2381 static gboolean
dyn_call_supported(MonoMethodSignature * sig,CallInfo * cinfo)2382 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2383 {
2384 int i;
2385
2386 switch (cinfo->ret.storage) {
2387 case ArgNone:
2388 case ArgInIReg:
2389 case ArgInFloatSSEReg:
2390 case ArgInDoubleSSEReg:
2391 case ArgValuetypeAddrInIReg:
2392 case ArgValuetypeInReg:
2393 break;
2394 default:
2395 return FALSE;
2396 }
2397
2398 for (i = 0; i < cinfo->nargs; ++i) {
2399 ArgInfo *ainfo = &cinfo->args [i];
2400 switch (ainfo->storage) {
2401 case ArgInIReg:
2402 case ArgInFloatSSEReg:
2403 case ArgInDoubleSSEReg:
2404 case ArgValuetypeInReg:
2405 case ArgOnStack:
2406 break;
2407 default:
2408 return FALSE;
2409 }
2410 }
2411
2412 return TRUE;
2413 }
2414
2415 /*
2416 * mono_arch_dyn_call_prepare:
2417 *
2418 * Return a pointer to an arch-specific structure which contains information
2419 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2420 * supported for SIG.
2421 * This function is equivalent to ffi_prep_cif in libffi.
2422 */
2423 MonoDynCallInfo*
mono_arch_dyn_call_prepare(MonoMethodSignature * sig)2424 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2425 {
2426 ArchDynCallInfo *info;
2427 CallInfo *cinfo;
2428 int i;
2429
2430 cinfo = get_call_info (NULL, sig);
2431
2432 if (!dyn_call_supported (sig, cinfo)) {
2433 g_free (cinfo);
2434 return NULL;
2435 }
2436
2437 info = g_new0 (ArchDynCallInfo, 1);
2438 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2439 info->sig = sig;
2440 info->cinfo = cinfo;
2441 info->nstack_args = 0;
2442
2443 for (i = 0; i < cinfo->nargs; ++i) {
2444 ArgInfo *ainfo = &cinfo->args [i];
2445 switch (ainfo->storage) {
2446 case ArgOnStack:
2447 info->nstack_args = MAX (info->nstack_args, ainfo->offset + (ainfo->arg_size / 8));
2448 break;
2449 default:
2450 break;
2451 }
2452 }
2453 /* Align to 16 bytes */
2454 if (info->nstack_args & 1)
2455 info->nstack_args ++;
2456
2457 return (MonoDynCallInfo*)info;
2458 }
2459
2460 /*
2461 * mono_arch_dyn_call_free:
2462 *
2463 * Free a MonoDynCallInfo structure.
2464 */
2465 void
mono_arch_dyn_call_free(MonoDynCallInfo * info)2466 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2467 {
2468 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2469
2470 g_free (ainfo->cinfo);
2471 g_free (ainfo);
2472 }
2473
2474 int
mono_arch_dyn_call_get_buf_size(MonoDynCallInfo * info)2475 mono_arch_dyn_call_get_buf_size (MonoDynCallInfo *info)
2476 {
2477 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2478
2479 /* Extend the 'regs' field dynamically */
2480 return sizeof (DynCallArgs) + (ainfo->nstack_args * sizeof (mgreg_t));
2481 }
2482
2483 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2484 #define GREG_TO_PTR(greg) (gpointer)(greg)
2485
2486 /*
2487 * mono_arch_get_start_dyn_call:
2488 *
2489 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2490 * store the result into BUF.
2491 * ARGS should be an array of pointers pointing to the arguments.
2492 * RET should point to a memory buffer large enought to hold the result of the
2493 * call.
2494 * This function should be as fast as possible, any work which does not depend
2495 * on the actual values of the arguments should be done in
2496 * mono_arch_dyn_call_prepare ().
2497 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2498 * libffi.
2499 */
2500 void
mono_arch_start_dyn_call(MonoDynCallInfo * info,gpointer ** args,guint8 * ret,guint8 * buf)2501 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf)
2502 {
2503 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2504 DynCallArgs *p = (DynCallArgs*)buf;
2505 int arg_index, greg, freg, i, pindex;
2506 MonoMethodSignature *sig = dinfo->sig;
2507 int buffer_offset = 0;
2508 static int param_reg_to_index [16];
2509 static gboolean param_reg_to_index_inited;
2510
2511 if (!param_reg_to_index_inited) {
2512 for (i = 0; i < PARAM_REGS; ++i)
2513 param_reg_to_index [param_regs [i]] = i;
2514 mono_memory_barrier ();
2515 param_reg_to_index_inited = 1;
2516 }
2517
2518 p->res = 0;
2519 p->ret = ret;
2520 p->nstack_args = dinfo->nstack_args;
2521
2522 arg_index = 0;
2523 greg = 0;
2524 freg = 0;
2525 pindex = 0;
2526
2527 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2528 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2529 if (!sig->hasthis)
2530 pindex = 1;
2531 }
2532
2533 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2534 p->regs [greg ++] = PTR_TO_GREG(ret);
2535
2536 for (; pindex < sig->param_count; pindex++) {
2537 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2538 gpointer *arg = args [arg_index ++];
2539 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2540 int slot;
2541
2542 if (ainfo->storage == ArgOnStack) {
2543 slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2544 } else {
2545 slot = param_reg_to_index [ainfo->reg];
2546 }
2547
2548 if (t->byref) {
2549 p->regs [slot] = PTR_TO_GREG(*(arg));
2550 greg ++;
2551 continue;
2552 }
2553
2554 switch (t->type) {
2555 case MONO_TYPE_OBJECT:
2556 case MONO_TYPE_PTR:
2557 case MONO_TYPE_I:
2558 case MONO_TYPE_U:
2559 #if !defined(__mono_ilp32__)
2560 case MONO_TYPE_I8:
2561 case MONO_TYPE_U8:
2562 #endif
2563 p->regs [slot] = PTR_TO_GREG(*(arg));
2564 break;
2565 #if defined(__mono_ilp32__)
2566 case MONO_TYPE_I8:
2567 case MONO_TYPE_U8:
2568 p->regs [slot] = *(guint64*)(arg);
2569 break;
2570 #endif
2571 case MONO_TYPE_U1:
2572 p->regs [slot] = *(guint8*)(arg);
2573 break;
2574 case MONO_TYPE_I1:
2575 p->regs [slot] = *(gint8*)(arg);
2576 break;
2577 case MONO_TYPE_I2:
2578 p->regs [slot] = *(gint16*)(arg);
2579 break;
2580 case MONO_TYPE_U2:
2581 p->regs [slot] = *(guint16*)(arg);
2582 break;
2583 case MONO_TYPE_I4:
2584 p->regs [slot] = *(gint32*)(arg);
2585 break;
2586 case MONO_TYPE_U4:
2587 p->regs [slot] = *(guint32*)(arg);
2588 break;
2589 case MONO_TYPE_R4: {
2590 double d;
2591
2592 *(float*)&d = *(float*)(arg);
2593 p->has_fp = 1;
2594 p->fregs [freg ++] = d;
2595 break;
2596 }
2597 case MONO_TYPE_R8:
2598 p->has_fp = 1;
2599 p->fregs [freg ++] = *(double*)(arg);
2600 break;
2601 case MONO_TYPE_GENERICINST:
2602 if (MONO_TYPE_IS_REFERENCE (t)) {
2603 p->regs [slot] = PTR_TO_GREG(*(arg));
2604 break;
2605 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2606 MonoClass *klass = mono_class_from_mono_type (t);
2607 guint8 *nullable_buf;
2608 int size;
2609
2610 size = mono_class_value_size (klass, NULL);
2611 nullable_buf = p->buffer + buffer_offset;
2612 buffer_offset += size;
2613 g_assert (buffer_offset <= 256);
2614
2615 /* The argument pointed to by arg is either a boxed vtype or null */
2616 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2617
2618 arg = (gpointer*)nullable_buf;
2619 /* Fall though */
2620
2621 } else {
2622 /* Fall through */
2623 }
2624 case MONO_TYPE_VALUETYPE: {
2625 switch (ainfo->storage) {
2626 case ArgValuetypeInReg:
2627 for (i = 0; i < 2; ++i) {
2628 switch (ainfo->pair_storage [i]) {
2629 case ArgNone:
2630 break;
2631 case ArgInIReg:
2632 slot = param_reg_to_index [ainfo->pair_regs [i]];
2633 p->regs [slot] = ((mgreg_t*)(arg))[i];
2634 break;
2635 case ArgInDoubleSSEReg:
2636 p->has_fp = 1;
2637 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2638 break;
2639 default:
2640 g_assert_not_reached ();
2641 break;
2642 }
2643 }
2644 break;
2645 case ArgOnStack:
2646 for (i = 0; i < ainfo->arg_size / 8; ++i)
2647 p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2648 break;
2649 default:
2650 g_assert_not_reached ();
2651 break;
2652 }
2653 break;
2654 }
2655 default:
2656 g_assert_not_reached ();
2657 }
2658 }
2659 }
2660
2661 /*
2662 * mono_arch_finish_dyn_call:
2663 *
2664 * Store the result of a dyn call into the return value buffer passed to
2665 * start_dyn_call ().
2666 * This function should be as fast as possible, any work which does not depend
2667 * on the actual values of the arguments should be done in
2668 * mono_arch_dyn_call_prepare ().
2669 */
2670 void
mono_arch_finish_dyn_call(MonoDynCallInfo * info,guint8 * buf)2671 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2672 {
2673 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2674 MonoMethodSignature *sig = dinfo->sig;
2675 DynCallArgs *dargs = (DynCallArgs*)buf;
2676 guint8 *ret = dargs->ret;
2677 mgreg_t res = dargs->res;
2678 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2679 int i;
2680
2681 switch (sig_ret->type) {
2682 case MONO_TYPE_VOID:
2683 *(gpointer*)ret = NULL;
2684 break;
2685 case MONO_TYPE_OBJECT:
2686 case MONO_TYPE_I:
2687 case MONO_TYPE_U:
2688 case MONO_TYPE_PTR:
2689 *(gpointer*)ret = GREG_TO_PTR(res);
2690 break;
2691 case MONO_TYPE_I1:
2692 *(gint8*)ret = res;
2693 break;
2694 case MONO_TYPE_U1:
2695 *(guint8*)ret = res;
2696 break;
2697 case MONO_TYPE_I2:
2698 *(gint16*)ret = res;
2699 break;
2700 case MONO_TYPE_U2:
2701 *(guint16*)ret = res;
2702 break;
2703 case MONO_TYPE_I4:
2704 *(gint32*)ret = res;
2705 break;
2706 case MONO_TYPE_U4:
2707 *(guint32*)ret = res;
2708 break;
2709 case MONO_TYPE_I8:
2710 *(gint64*)ret = res;
2711 break;
2712 case MONO_TYPE_U8:
2713 *(guint64*)ret = res;
2714 break;
2715 case MONO_TYPE_R4:
2716 *(float*)ret = *(float*)&(dargs->fregs [0]);
2717 break;
2718 case MONO_TYPE_R8:
2719 *(double*)ret = dargs->fregs [0];
2720 break;
2721 case MONO_TYPE_GENERICINST:
2722 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2723 *(gpointer*)ret = GREG_TO_PTR(res);
2724 break;
2725 } else {
2726 /* Fall through */
2727 }
2728 case MONO_TYPE_VALUETYPE:
2729 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2730 /* Nothing to do */
2731 } else {
2732 ArgInfo *ainfo = &dinfo->cinfo->ret;
2733
2734 g_assert (ainfo->storage == ArgValuetypeInReg);
2735
2736 for (i = 0; i < 2; ++i) {
2737 switch (ainfo->pair_storage [0]) {
2738 case ArgInIReg:
2739 ((mgreg_t*)ret)[i] = res;
2740 break;
2741 case ArgInDoubleSSEReg:
2742 ((double*)ret)[i] = dargs->fregs [i];
2743 break;
2744 case ArgNone:
2745 break;
2746 default:
2747 g_assert_not_reached ();
2748 break;
2749 }
2750 }
2751 }
2752 break;
2753 default:
2754 g_assert_not_reached ();
2755 }
2756 }
2757
2758 /* emit an exception if condition is fail */
2759 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2760 do { \
2761 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2762 if (tins == NULL) { \
2763 mono_add_patch_info (cfg, code - cfg->native_code, \
2764 MONO_PATCH_INFO_EXC, exc_name); \
2765 x86_branch32 (code, cond, 0, signed); \
2766 } else { \
2767 EMIT_COND_BRANCH (tins, cond, signed); \
2768 } \
2769 } while (0);
2770
2771 #define EMIT_FPCOMPARE(code) do { \
2772 amd64_fcompp (code); \
2773 amd64_fnstsw (code); \
2774 } while (0);
2775
2776 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2777 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2778 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2779 amd64_ ##op (code); \
2780 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2781 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2782 } while (0);
2783
2784 static guint8*
emit_call_body(MonoCompile * cfg,guint8 * code,MonoJumpInfoType patch_type,gconstpointer data)2785 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2786 {
2787 gboolean no_patch = FALSE;
2788
2789 /*
2790 * FIXME: Add support for thunks
2791 */
2792 {
2793 gboolean near_call = FALSE;
2794
2795 /*
2796 * Indirect calls are expensive so try to make a near call if possible.
2797 * The caller memory is allocated by the code manager so it is
2798 * guaranteed to be at a 32 bit offset.
2799 */
2800
2801 if (patch_type != MONO_PATCH_INFO_ABS) {
2802 /* The target is in memory allocated using the code manager */
2803 near_call = TRUE;
2804
2805 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2806 if (((MonoMethod*)data)->klass->image->aot_module)
2807 /* The callee might be an AOT method */
2808 near_call = FALSE;
2809 if (((MonoMethod*)data)->dynamic)
2810 /* The target is in malloc-ed memory */
2811 near_call = FALSE;
2812 }
2813
2814 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2815 /*
2816 * The call might go directly to a native function without
2817 * the wrapper.
2818 */
2819 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2820 if (mi) {
2821 gconstpointer target = mono_icall_get_wrapper (mi);
2822 if ((((guint64)target) >> 32) != 0)
2823 near_call = FALSE;
2824 }
2825 }
2826 }
2827 else {
2828 MonoJumpInfo *jinfo = NULL;
2829
2830 if (cfg->abs_patches)
2831 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2832 if (jinfo) {
2833 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2834 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2835 if (mi && (((guint64)mi->func) >> 32) == 0)
2836 near_call = TRUE;
2837 no_patch = TRUE;
2838 } else {
2839 /*
2840 * This is not really an optimization, but required because the
2841 * generic class init trampolines use R11 to pass the vtable.
2842 */
2843 near_call = TRUE;
2844 }
2845 } else {
2846 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2847 if (info) {
2848 if (info->func == info->wrapper) {
2849 /* No wrapper */
2850 if ((((guint64)info->func) >> 32) == 0)
2851 near_call = TRUE;
2852 }
2853 else {
2854 /* See the comment in mono_codegen () */
2855 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2856 near_call = TRUE;
2857 }
2858 }
2859 else if ((((guint64)data) >> 32) == 0) {
2860 near_call = TRUE;
2861 no_patch = TRUE;
2862 }
2863 }
2864 }
2865
2866 if (cfg->method->dynamic)
2867 /* These methods are allocated using malloc */
2868 near_call = FALSE;
2869
2870 #ifdef MONO_ARCH_NOMAP32BIT
2871 near_call = FALSE;
2872 #endif
2873 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2874 if (optimize_for_xen)
2875 near_call = FALSE;
2876
2877 if (cfg->compile_aot) {
2878 near_call = TRUE;
2879 no_patch = TRUE;
2880 }
2881
2882 if (near_call) {
2883 /*
2884 * Align the call displacement to an address divisible by 4 so it does
2885 * not span cache lines. This is required for code patching to work on SMP
2886 * systems.
2887 */
2888 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2889 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2890 amd64_padding (code, pad_size);
2891 }
2892 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2893 amd64_call_code (code, 0);
2894 }
2895 else {
2896 if (!no_patch && ((guint32)(code + 2 - cfg->native_code) % 8) != 0) {
2897 guint32 pad_size = 8 - ((guint32)(code + 2 - cfg->native_code) % 8);
2898 amd64_padding (code, pad_size);
2899 g_assert ((guint64)(code + 2 - cfg->native_code) % 8 == 0);
2900 }
2901 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2902 amd64_set_reg_template (code, GP_SCRATCH_REG);
2903 amd64_call_reg (code, GP_SCRATCH_REG);
2904 }
2905 }
2906
2907 return code;
2908 }
2909
2910 static inline guint8*
emit_call(MonoCompile * cfg,guint8 * code,MonoJumpInfoType patch_type,gconstpointer data,gboolean win64_adjust_stack)2911 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2912 {
2913 #ifdef TARGET_WIN32
2914 if (win64_adjust_stack)
2915 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2916 #endif
2917 code = emit_call_body (cfg, code, patch_type, data);
2918 #ifdef TARGET_WIN32
2919 if (win64_adjust_stack)
2920 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2921 #endif
2922
2923 return code;
2924 }
2925
2926 static inline int
store_membase_imm_to_store_membase_reg(int opcode)2927 store_membase_imm_to_store_membase_reg (int opcode)
2928 {
2929 switch (opcode) {
2930 case OP_STORE_MEMBASE_IMM:
2931 return OP_STORE_MEMBASE_REG;
2932 case OP_STOREI4_MEMBASE_IMM:
2933 return OP_STOREI4_MEMBASE_REG;
2934 case OP_STOREI8_MEMBASE_IMM:
2935 return OP_STOREI8_MEMBASE_REG;
2936 }
2937
2938 return -1;
2939 }
2940
2941 #ifndef DISABLE_JIT
2942
2943 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2944
2945 /*
2946 * mono_arch_peephole_pass_1:
2947 *
2948 * Perform peephole opts which should/can be performed before local regalloc
2949 */
2950 void
mono_arch_peephole_pass_1(MonoCompile * cfg,MonoBasicBlock * bb)2951 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2952 {
2953 MonoInst *ins, *n;
2954
2955 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2956 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2957
2958 switch (ins->opcode) {
2959 case OP_ADD_IMM:
2960 case OP_IADD_IMM:
2961 case OP_LADD_IMM:
2962 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2963 /*
2964 * X86_LEA is like ADD, but doesn't have the
2965 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2966 * its operand to 64 bit.
2967 */
2968 ins->opcode = OP_X86_LEA_MEMBASE;
2969 ins->inst_basereg = ins->sreg1;
2970 }
2971 break;
2972 case OP_LXOR:
2973 case OP_IXOR:
2974 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2975 MonoInst *ins2;
2976
2977 /*
2978 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2979 * the latter has length 2-3 instead of 6 (reverse constant
2980 * propagation). These instruction sequences are very common
2981 * in the initlocals bblock.
2982 */
2983 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2984 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2985 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2986 ins2->sreg1 = ins->dreg;
2987 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2988 /* Continue */
2989 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2990 NULLIFY_INS (ins2);
2991 /* Continue */
2992 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2993 /* Continue */
2994 } else {
2995 break;
2996 }
2997 }
2998 }
2999 break;
3000 case OP_COMPARE_IMM:
3001 case OP_LCOMPARE_IMM:
3002 /* OP_COMPARE_IMM (reg, 0)
3003 * -->
3004 * OP_AMD64_TEST_NULL (reg)
3005 */
3006 if (!ins->inst_imm)
3007 ins->opcode = OP_AMD64_TEST_NULL;
3008 break;
3009 case OP_ICOMPARE_IMM:
3010 if (!ins->inst_imm)
3011 ins->opcode = OP_X86_TEST_NULL;
3012 break;
3013 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3014 /*
3015 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3016 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3017 * -->
3018 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3019 * OP_COMPARE_IMM reg, imm
3020 *
3021 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3022 */
3023 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3024 ins->inst_basereg == last_ins->inst_destbasereg &&
3025 ins->inst_offset == last_ins->inst_offset) {
3026 ins->opcode = OP_ICOMPARE_IMM;
3027 ins->sreg1 = last_ins->sreg1;
3028
3029 /* check if we can remove cmp reg,0 with test null */
3030 if (!ins->inst_imm)
3031 ins->opcode = OP_X86_TEST_NULL;
3032 }
3033
3034 break;
3035 }
3036
3037 mono_peephole_ins (bb, ins);
3038 }
3039 }
3040
3041 void
mono_arch_peephole_pass_2(MonoCompile * cfg,MonoBasicBlock * bb)3042 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3043 {
3044 MonoInst *ins, *n;
3045
3046 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3047 switch (ins->opcode) {
3048 case OP_ICONST:
3049 case OP_I8CONST: {
3050 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3051 /* reg = 0 -> XOR (reg, reg) */
3052 /* XOR sets cflags on x86, so we cant do it always */
3053 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3054 ins->opcode = OP_LXOR;
3055 ins->sreg1 = ins->dreg;
3056 ins->sreg2 = ins->dreg;
3057 /* Fall through */
3058 } else {
3059 break;
3060 }
3061 }
3062 case OP_LXOR:
3063 /*
3064 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3065 * 0 result into 64 bits.
3066 */
3067 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3068 ins->opcode = OP_IXOR;
3069 }
3070 /* Fall through */
3071 case OP_IXOR:
3072 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3073 MonoInst *ins2;
3074
3075 /*
3076 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3077 * the latter has length 2-3 instead of 6 (reverse constant
3078 * propagation). These instruction sequences are very common
3079 * in the initlocals bblock.
3080 */
3081 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3082 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3083 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3084 ins2->sreg1 = ins->dreg;
3085 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3086 /* Continue */
3087 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3088 NULLIFY_INS (ins2);
3089 /* Continue */
3090 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3091 /* Continue */
3092 } else {
3093 break;
3094 }
3095 }
3096 }
3097 break;
3098 case OP_IADD_IMM:
3099 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3100 ins->opcode = OP_X86_INC_REG;
3101 break;
3102 case OP_ISUB_IMM:
3103 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3104 ins->opcode = OP_X86_DEC_REG;
3105 break;
3106 }
3107
3108 mono_peephole_ins (bb, ins);
3109 }
3110 }
3111
3112 #define NEW_INS(cfg,ins,dest,op) do { \
3113 MONO_INST_NEW ((cfg), (dest), (op)); \
3114 (dest)->cil_code = (ins)->cil_code; \
3115 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3116 } while (0)
3117
3118 /*
3119 * mono_arch_lowering_pass:
3120 *
3121 * Converts complex opcodes into simpler ones so that each IR instruction
3122 * corresponds to one machine instruction.
3123 */
3124 void
mono_arch_lowering_pass(MonoCompile * cfg,MonoBasicBlock * bb)3125 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3126 {
3127 MonoInst *ins, *n, *temp;
3128
3129 /*
3130 * FIXME: Need to add more instructions, but the current machine
3131 * description can't model some parts of the composite instructions like
3132 * cdq.
3133 */
3134 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3135 switch (ins->opcode) {
3136 case OP_DIV_IMM:
3137 case OP_REM_IMM:
3138 case OP_IDIV_IMM:
3139 case OP_IDIV_UN_IMM:
3140 case OP_IREM_UN_IMM:
3141 case OP_LREM_IMM:
3142 case OP_IREM_IMM:
3143 mono_decompose_op_imm (cfg, bb, ins);
3144 break;
3145 case OP_COMPARE_IMM:
3146 case OP_LCOMPARE_IMM:
3147 if (!amd64_use_imm32 (ins->inst_imm)) {
3148 NEW_INS (cfg, ins, temp, OP_I8CONST);
3149 temp->inst_c0 = ins->inst_imm;
3150 temp->dreg = mono_alloc_ireg (cfg);
3151 ins->opcode = OP_COMPARE;
3152 ins->sreg2 = temp->dreg;
3153 }
3154 break;
3155 #ifndef __mono_ilp32__
3156 case OP_LOAD_MEMBASE:
3157 #endif
3158 case OP_LOADI8_MEMBASE:
3159 /* Don't generate memindex opcodes (to simplify */
3160 /* read sandboxing) */
3161 if (!amd64_use_imm32 (ins->inst_offset)) {
3162 NEW_INS (cfg, ins, temp, OP_I8CONST);
3163 temp->inst_c0 = ins->inst_offset;
3164 temp->dreg = mono_alloc_ireg (cfg);
3165 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3166 ins->inst_indexreg = temp->dreg;
3167 }
3168 break;
3169 #ifndef __mono_ilp32__
3170 case OP_STORE_MEMBASE_IMM:
3171 #endif
3172 case OP_STOREI8_MEMBASE_IMM:
3173 if (!amd64_use_imm32 (ins->inst_imm)) {
3174 NEW_INS (cfg, ins, temp, OP_I8CONST);
3175 temp->inst_c0 = ins->inst_imm;
3176 temp->dreg = mono_alloc_ireg (cfg);
3177 ins->opcode = OP_STOREI8_MEMBASE_REG;
3178 ins->sreg1 = temp->dreg;
3179 }
3180 break;
3181 #ifdef MONO_ARCH_SIMD_INTRINSICS
3182 case OP_EXPAND_I1: {
3183 int temp_reg1 = mono_alloc_ireg (cfg);
3184 int temp_reg2 = mono_alloc_ireg (cfg);
3185 int original_reg = ins->sreg1;
3186
3187 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3188 temp->sreg1 = original_reg;
3189 temp->dreg = temp_reg1;
3190
3191 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3192 temp->sreg1 = temp_reg1;
3193 temp->dreg = temp_reg2;
3194 temp->inst_imm = 8;
3195
3196 NEW_INS (cfg, ins, temp, OP_LOR);
3197 temp->sreg1 = temp->dreg = temp_reg2;
3198 temp->sreg2 = temp_reg1;
3199
3200 ins->opcode = OP_EXPAND_I2;
3201 ins->sreg1 = temp_reg2;
3202 }
3203 break;
3204 #endif
3205 default:
3206 break;
3207 }
3208 }
3209
3210 bb->max_vreg = cfg->next_vreg;
3211 }
3212
3213 static const int
3214 branch_cc_table [] = {
3215 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3216 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3217 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3218 };
3219
3220 /* Maps CMP_... constants to X86_CC_... constants */
3221 static const int
3222 cc_table [] = {
3223 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3224 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3225 };
3226
3227 static const int
3228 cc_signed_table [] = {
3229 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3230 FALSE, FALSE, FALSE, FALSE
3231 };
3232
3233 /*#include "cprop.c"*/
3234
3235 static unsigned char*
emit_float_to_int(MonoCompile * cfg,guchar * code,int dreg,int sreg,int size,gboolean is_signed)3236 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3237 {
3238 if (size == 8)
3239 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3240 else
3241 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3242
3243 if (size == 1)
3244 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3245 else if (size == 2)
3246 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3247 return code;
3248 }
3249
3250 static unsigned char*
mono_emit_stack_alloc(MonoCompile * cfg,guchar * code,MonoInst * tree)3251 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3252 {
3253 int sreg = tree->sreg1;
3254 int need_touch = FALSE;
3255
3256 #if defined(TARGET_WIN32)
3257 need_touch = TRUE;
3258 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3259 if (!(tree->flags & MONO_INST_INIT))
3260 need_touch = TRUE;
3261 #endif
3262
3263 if (need_touch) {
3264 guint8* br[5];
3265
3266 /*
3267 * Under Windows:
3268 * If requested stack size is larger than one page,
3269 * perform stack-touch operation
3270 */
3271 /*
3272 * Generate stack probe code.
3273 * Under Windows, it is necessary to allocate one page at a time,
3274 * "touching" stack after each successful sub-allocation. This is
3275 * because of the way stack growth is implemented - there is a
3276 * guard page before the lowest stack page that is currently commited.
3277 * Stack normally grows sequentially so OS traps access to the
3278 * guard page and commits more pages when needed.
3279 */
3280 amd64_test_reg_imm (code, sreg, ~0xFFF);
3281 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3282
3283 br[2] = code; /* loop */
3284 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3285 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3286 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3287 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3288 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3289 amd64_patch (br[3], br[2]);
3290 amd64_test_reg_reg (code, sreg, sreg);
3291 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3292 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3293
3294 br[1] = code; x86_jump8 (code, 0);
3295
3296 amd64_patch (br[0], code);
3297 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3298 amd64_patch (br[1], code);
3299 amd64_patch (br[4], code);
3300 }
3301 else
3302 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3303
3304 if (tree->flags & MONO_INST_INIT) {
3305 int offset = 0;
3306 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3307 amd64_push_reg (code, AMD64_RAX);
3308 offset += 8;
3309 }
3310 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3311 amd64_push_reg (code, AMD64_RCX);
3312 offset += 8;
3313 }
3314 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3315 amd64_push_reg (code, AMD64_RDI);
3316 offset += 8;
3317 }
3318
3319 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3320 if (sreg != AMD64_RCX)
3321 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3322 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3323
3324 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3325 if (cfg->param_area)
3326 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3327 amd64_cld (code);
3328 amd64_prefix (code, X86_REP_PREFIX);
3329 amd64_stosl (code);
3330
3331 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3332 amd64_pop_reg (code, AMD64_RDI);
3333 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3334 amd64_pop_reg (code, AMD64_RCX);
3335 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3336 amd64_pop_reg (code, AMD64_RAX);
3337 }
3338 return code;
3339 }
3340
3341 static guint8*
emit_move_return_value(MonoCompile * cfg,MonoInst * ins,guint8 * code)3342 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3343 {
3344 CallInfo *cinfo;
3345 guint32 quad;
3346
3347 /* Move return value to the target register */
3348 /* FIXME: do this in the local reg allocator */
3349 switch (ins->opcode) {
3350 case OP_CALL:
3351 case OP_CALL_REG:
3352 case OP_CALL_MEMBASE:
3353 case OP_LCALL:
3354 case OP_LCALL_REG:
3355 case OP_LCALL_MEMBASE:
3356 g_assert (ins->dreg == AMD64_RAX);
3357 break;
3358 case OP_FCALL:
3359 case OP_FCALL_REG:
3360 case OP_FCALL_MEMBASE: {
3361 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3362 if (rtype->type == MONO_TYPE_R4) {
3363 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3364 }
3365 else {
3366 if (ins->dreg != AMD64_XMM0)
3367 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3368 }
3369 break;
3370 }
3371 case OP_RCALL:
3372 case OP_RCALL_REG:
3373 case OP_RCALL_MEMBASE:
3374 if (ins->dreg != AMD64_XMM0)
3375 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3376 break;
3377 case OP_VCALL:
3378 case OP_VCALL_REG:
3379 case OP_VCALL_MEMBASE:
3380 case OP_VCALL2:
3381 case OP_VCALL2_REG:
3382 case OP_VCALL2_MEMBASE:
3383 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3384 if (cinfo->ret.storage == ArgValuetypeInReg) {
3385 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3386
3387 /* Load the destination address */
3388 g_assert (loc->opcode == OP_REGOFFSET);
3389 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3390
3391 for (quad = 0; quad < 2; quad ++) {
3392 switch (cinfo->ret.pair_storage [quad]) {
3393 case ArgInIReg:
3394 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3395 break;
3396 case ArgInFloatSSEReg:
3397 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3398 break;
3399 case ArgInDoubleSSEReg:
3400 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3401 break;
3402 case ArgNone:
3403 break;
3404 default:
3405 NOT_IMPLEMENTED;
3406 }
3407 }
3408 }
3409 break;
3410 }
3411
3412 return code;
3413 }
3414
3415 #endif /* DISABLE_JIT */
3416
3417 #ifdef TARGET_MACH
3418 static int tls_gs_offset;
3419 #endif
3420
3421 gboolean
mono_arch_have_fast_tls(void)3422 mono_arch_have_fast_tls (void)
3423 {
3424 #ifdef TARGET_MACH
3425 static gboolean have_fast_tls = FALSE;
3426 static gboolean inited = FALSE;
3427 guint8 *ins;
3428
3429 if (mini_get_debug_options ()->use_fallback_tls)
3430 return FALSE;
3431
3432 if (inited)
3433 return have_fast_tls;
3434
3435 ins = (guint8*)pthread_getspecific;
3436
3437 /*
3438 * We're looking for these two instructions:
3439 *
3440 * mov %gs:[offset](,%rdi,8),%rax
3441 * retq
3442 */
3443 have_fast_tls = ins [0] == 0x65 &&
3444 ins [1] == 0x48 &&
3445 ins [2] == 0x8b &&
3446 ins [3] == 0x04 &&
3447 ins [4] == 0xfd &&
3448 ins [6] == 0x00 &&
3449 ins [7] == 0x00 &&
3450 ins [8] == 0x00 &&
3451 ins [9] == 0xc3;
3452
3453 tls_gs_offset = ins[5];
3454
3455 /*
3456 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3457 * For that version we're looking for these instructions:
3458 *
3459 * pushq %rbp
3460 * movq %rsp, %rbp
3461 * mov %gs:[offset](,%rdi,8),%rax
3462 * popq %rbp
3463 * retq
3464 */
3465 if (!have_fast_tls) {
3466 have_fast_tls = ins [0] == 0x55 &&
3467 ins [1] == 0x48 &&
3468 ins [2] == 0x89 &&
3469 ins [3] == 0xe5 &&
3470 ins [4] == 0x65 &&
3471 ins [5] == 0x48 &&
3472 ins [6] == 0x8b &&
3473 ins [7] == 0x04 &&
3474 ins [8] == 0xfd &&
3475 ins [10] == 0x00 &&
3476 ins [11] == 0x00 &&
3477 ins [12] == 0x00 &&
3478 ins [13] == 0x5d &&
3479 ins [14] == 0xc3;
3480
3481 tls_gs_offset = ins[9];
3482 }
3483 inited = TRUE;
3484
3485 return have_fast_tls;
3486 #elif defined(TARGET_ANDROID)
3487 return FALSE;
3488 #else
3489 if (mini_get_debug_options ()->use_fallback_tls)
3490 return FALSE;
3491 return TRUE;
3492 #endif
3493 }
3494
3495 int
mono_amd64_get_tls_gs_offset(void)3496 mono_amd64_get_tls_gs_offset (void)
3497 {
3498 #ifdef TARGET_OSX
3499 return tls_gs_offset;
3500 #else
3501 g_assert_not_reached ();
3502 return -1;
3503 #endif
3504 }
3505
3506 /*
3507 * \param code buffer to store code to
3508 * \param dreg hard register where to place the result
3509 * \param tls_offset offset info
3510 * \return a pointer to the end of the stored code
3511 *
3512 * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3513 * the dreg register the item in the thread local storage identified
3514 * by tls_offset.
3515 */
3516 static guint8*
mono_amd64_emit_tls_get(guint8 * code,int dreg,int tls_offset)3517 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3518 {
3519 #ifdef TARGET_WIN32
3520 if (tls_offset < 64) {
3521 x86_prefix (code, X86_GS_PREFIX);
3522 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3523 } else {
3524 guint8 *buf [16];
3525
3526 g_assert (tls_offset < 0x440);
3527 /* Load TEB->TlsExpansionSlots */
3528 x86_prefix (code, X86_GS_PREFIX);
3529 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3530 amd64_test_reg_reg (code, dreg, dreg);
3531 buf [0] = code;
3532 amd64_branch (code, X86_CC_EQ, code, TRUE);
3533 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3534 amd64_patch (buf [0], code);
3535 }
3536 #elif defined(TARGET_MACH)
3537 x86_prefix (code, X86_GS_PREFIX);
3538 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3539 #else
3540 if (optimize_for_xen) {
3541 x86_prefix (code, X86_FS_PREFIX);
3542 amd64_mov_reg_mem (code, dreg, 0, 8);
3543 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3544 } else {
3545 x86_prefix (code, X86_FS_PREFIX);
3546 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3547 }
3548 #endif
3549 return code;
3550 }
3551
3552 static guint8*
mono_amd64_emit_tls_set(guint8 * code,int sreg,int tls_offset)3553 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3554 {
3555 #ifdef TARGET_WIN32
3556 g_assert_not_reached ();
3557 #elif defined(TARGET_MACH)
3558 x86_prefix (code, X86_GS_PREFIX);
3559 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3560 #else
3561 g_assert (!optimize_for_xen);
3562 x86_prefix (code, X86_FS_PREFIX);
3563 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3564 #endif
3565 return code;
3566 }
3567
3568 /*
3569 * emit_setup_lmf:
3570 *
3571 * Emit code to initialize an LMF structure at LMF_OFFSET.
3572 */
3573 static guint8*
emit_setup_lmf(MonoCompile * cfg,guint8 * code,gint32 lmf_offset,int cfa_offset)3574 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3575 {
3576 /*
3577 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3578 */
3579 /*
3580 * sp is saved right before calls but we need to save it here too so
3581 * async stack walks would work.
3582 */
3583 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3584 /* Save rbp */
3585 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3586 if (cfg->arch.omit_fp && cfa_offset != -1)
3587 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3588
3589 /* These can't contain refs */
3590 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3591 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3592 /* These are handled automatically by the stack marking code */
3593 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3594
3595 return code;
3596 }
3597
3598 #ifdef TARGET_WIN32
3599
3600 #define TEB_LAST_ERROR_OFFSET 0x068
3601
3602 static guint8*
emit_get_last_error(guint8 * code,int dreg)3603 emit_get_last_error (guint8* code, int dreg)
3604 {
3605 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3606 x86_prefix (code, X86_GS_PREFIX);
3607 amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3608
3609 return code;
3610 }
3611
3612 #else
3613
3614 static guint8*
emit_get_last_error(guint8 * code,int dreg)3615 emit_get_last_error (guint8* code, int dreg)
3616 {
3617 g_assert_not_reached ();
3618 }
3619
3620 #endif
3621
3622 /* benchmark and set based on cpu */
3623 #define LOOP_ALIGNMENT 8
3624 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3625
3626 #ifndef DISABLE_JIT
3627 void
mono_arch_output_basic_block(MonoCompile * cfg,MonoBasicBlock * bb)3628 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3629 {
3630 MonoInst *ins;
3631 MonoCallInst *call;
3632 guint offset;
3633 guint8 *code = cfg->native_code + cfg->code_len;
3634 int max_len;
3635
3636 /* Fix max_offset estimate for each successor bb */
3637 if (cfg->opt & MONO_OPT_BRANCH) {
3638 int current_offset = cfg->code_len;
3639 MonoBasicBlock *current_bb;
3640 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3641 current_bb->max_offset = current_offset;
3642 current_offset += current_bb->max_length;
3643 }
3644 }
3645
3646 if (cfg->opt & MONO_OPT_LOOP) {
3647 int pad, align = LOOP_ALIGNMENT;
3648 /* set alignment depending on cpu */
3649 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3650 pad = align - pad;
3651 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3652 amd64_padding (code, pad);
3653 cfg->code_len += pad;
3654 bb->native_offset = cfg->code_len;
3655 }
3656 }
3657
3658 if (cfg->verbose_level > 2)
3659 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3660
3661 offset = code - cfg->native_code;
3662
3663 mono_debug_open_block (cfg, bb, offset);
3664
3665 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3666 x86_breakpoint (code);
3667
3668 MONO_BB_FOR_EACH_INS (bb, ins) {
3669 offset = code - cfg->native_code;
3670
3671 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3672
3673 #define EXTRA_CODE_SPACE (16)
3674
3675 if (G_UNLIKELY ((offset + max_len + EXTRA_CODE_SPACE) > cfg->code_size)) {
3676 cfg->code_size *= 2;
3677 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3678 code = cfg->native_code + offset;
3679 cfg->stat_code_reallocs++;
3680 }
3681
3682 if (cfg->debug_info)
3683 mono_debug_record_line_number (cfg, ins, offset);
3684
3685 switch (ins->opcode) {
3686 case OP_BIGMUL:
3687 amd64_mul_reg (code, ins->sreg2, TRUE);
3688 break;
3689 case OP_BIGMUL_UN:
3690 amd64_mul_reg (code, ins->sreg2, FALSE);
3691 break;
3692 case OP_X86_SETEQ_MEMBASE:
3693 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3694 break;
3695 case OP_STOREI1_MEMBASE_IMM:
3696 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3697 break;
3698 case OP_STOREI2_MEMBASE_IMM:
3699 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3700 break;
3701 case OP_STOREI4_MEMBASE_IMM:
3702 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3703 break;
3704 case OP_STOREI1_MEMBASE_REG:
3705 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3706 break;
3707 case OP_STOREI2_MEMBASE_REG:
3708 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3709 break;
3710 /* In AMD64 NaCl, pointers are 4 bytes, */
3711 /* so STORE_* != STOREI8_*. Likewise below. */
3712 case OP_STORE_MEMBASE_REG:
3713 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3714 break;
3715 case OP_STOREI8_MEMBASE_REG:
3716 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3717 break;
3718 case OP_STOREI4_MEMBASE_REG:
3719 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3720 break;
3721 case OP_STORE_MEMBASE_IMM:
3722 /* In NaCl, this could be a PCONST type, which could */
3723 /* mean a pointer type was copied directly into the */
3724 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3725 /* the value would be 0x00000000FFFFFFFF which is */
3726 /* not proper for an imm32 unless you cast it. */
3727 g_assert (amd64_is_imm32 (ins->inst_imm));
3728 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3729 break;
3730 case OP_STOREI8_MEMBASE_IMM:
3731 g_assert (amd64_is_imm32 (ins->inst_imm));
3732 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3733 break;
3734 case OP_LOAD_MEM:
3735 #ifdef __mono_ilp32__
3736 /* In ILP32, pointers are 4 bytes, so separate these */
3737 /* cases, use literal 8 below where we really want 8 */
3738 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3739 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3740 break;
3741 #endif
3742 case OP_LOADI8_MEM:
3743 // FIXME: Decompose this earlier
3744 if (amd64_use_imm32 (ins->inst_imm))
3745 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3746 else {
3747 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3748 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3749 }
3750 break;
3751 case OP_LOADI4_MEM:
3752 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3753 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3754 break;
3755 case OP_LOADU4_MEM:
3756 // FIXME: Decompose this earlier
3757 if (amd64_use_imm32 (ins->inst_imm))
3758 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3759 else {
3760 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3761 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3762 }
3763 break;
3764 case OP_LOADU1_MEM:
3765 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3766 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3767 break;
3768 case OP_LOADU2_MEM:
3769 /* For NaCl, pointers are 4 bytes, so separate these */
3770 /* cases, use literal 8 below where we really want 8 */
3771 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3772 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3773 break;
3774 case OP_LOAD_MEMBASE:
3775 g_assert (amd64_is_imm32 (ins->inst_offset));
3776 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3777 break;
3778 case OP_LOADI8_MEMBASE:
3779 /* Use literal 8 instead of sizeof pointer or */
3780 /* register, we really want 8 for this opcode */
3781 g_assert (amd64_is_imm32 (ins->inst_offset));
3782 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3783 break;
3784 case OP_LOADI4_MEMBASE:
3785 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3786 break;
3787 case OP_LOADU4_MEMBASE:
3788 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3789 break;
3790 case OP_LOADU1_MEMBASE:
3791 /* The cpu zero extends the result into 64 bits */
3792 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3793 break;
3794 case OP_LOADI1_MEMBASE:
3795 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3796 break;
3797 case OP_LOADU2_MEMBASE:
3798 /* The cpu zero extends the result into 64 bits */
3799 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3800 break;
3801 case OP_LOADI2_MEMBASE:
3802 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3803 break;
3804 case OP_AMD64_LOADI8_MEMINDEX:
3805 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3806 break;
3807 case OP_LCONV_TO_I1:
3808 case OP_ICONV_TO_I1:
3809 case OP_SEXT_I1:
3810 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3811 break;
3812 case OP_LCONV_TO_I2:
3813 case OP_ICONV_TO_I2:
3814 case OP_SEXT_I2:
3815 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3816 break;
3817 case OP_LCONV_TO_U1:
3818 case OP_ICONV_TO_U1:
3819 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3820 break;
3821 case OP_LCONV_TO_U2:
3822 case OP_ICONV_TO_U2:
3823 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3824 break;
3825 case OP_ZEXT_I4:
3826 /* Clean out the upper word */
3827 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3828 break;
3829 case OP_SEXT_I4:
3830 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3831 break;
3832 case OP_COMPARE:
3833 case OP_LCOMPARE:
3834 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3835 break;
3836 case OP_COMPARE_IMM:
3837 #if defined(__mono_ilp32__)
3838 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3839 g_assert (amd64_is_imm32 (ins->inst_imm));
3840 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3841 break;
3842 #endif
3843 case OP_LCOMPARE_IMM:
3844 g_assert (amd64_is_imm32 (ins->inst_imm));
3845 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3846 break;
3847 case OP_X86_COMPARE_REG_MEMBASE:
3848 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3849 break;
3850 case OP_X86_TEST_NULL:
3851 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3852 break;
3853 case OP_AMD64_TEST_NULL:
3854 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3855 break;
3856
3857 case OP_X86_ADD_REG_MEMBASE:
3858 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3859 break;
3860 case OP_X86_SUB_REG_MEMBASE:
3861 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3862 break;
3863 case OP_X86_AND_REG_MEMBASE:
3864 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3865 break;
3866 case OP_X86_OR_REG_MEMBASE:
3867 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3868 break;
3869 case OP_X86_XOR_REG_MEMBASE:
3870 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3871 break;
3872
3873 case OP_X86_ADD_MEMBASE_IMM:
3874 /* FIXME: Make a 64 version too */
3875 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3876 break;
3877 case OP_X86_SUB_MEMBASE_IMM:
3878 g_assert (amd64_is_imm32 (ins->inst_imm));
3879 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3880 break;
3881 case OP_X86_AND_MEMBASE_IMM:
3882 g_assert (amd64_is_imm32 (ins->inst_imm));
3883 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3884 break;
3885 case OP_X86_OR_MEMBASE_IMM:
3886 g_assert (amd64_is_imm32 (ins->inst_imm));
3887 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3888 break;
3889 case OP_X86_XOR_MEMBASE_IMM:
3890 g_assert (amd64_is_imm32 (ins->inst_imm));
3891 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3892 break;
3893 case OP_X86_ADD_MEMBASE_REG:
3894 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3895 break;
3896 case OP_X86_SUB_MEMBASE_REG:
3897 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3898 break;
3899 case OP_X86_AND_MEMBASE_REG:
3900 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3901 break;
3902 case OP_X86_OR_MEMBASE_REG:
3903 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3904 break;
3905 case OP_X86_XOR_MEMBASE_REG:
3906 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3907 break;
3908 case OP_X86_INC_MEMBASE:
3909 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3910 break;
3911 case OP_X86_INC_REG:
3912 amd64_inc_reg_size (code, ins->dreg, 4);
3913 break;
3914 case OP_X86_DEC_MEMBASE:
3915 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3916 break;
3917 case OP_X86_DEC_REG:
3918 amd64_dec_reg_size (code, ins->dreg, 4);
3919 break;
3920 case OP_X86_MUL_REG_MEMBASE:
3921 case OP_X86_MUL_MEMBASE_REG:
3922 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3923 break;
3924 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3925 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3926 break;
3927 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3928 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3929 break;
3930 case OP_AMD64_COMPARE_MEMBASE_REG:
3931 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3932 break;
3933 case OP_AMD64_COMPARE_MEMBASE_IMM:
3934 g_assert (amd64_is_imm32 (ins->inst_imm));
3935 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3936 break;
3937 case OP_X86_COMPARE_MEMBASE8_IMM:
3938 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3939 break;
3940 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3941 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3942 break;
3943 case OP_AMD64_COMPARE_REG_MEMBASE:
3944 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3945 break;
3946
3947 case OP_AMD64_ADD_REG_MEMBASE:
3948 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3949 break;
3950 case OP_AMD64_SUB_REG_MEMBASE:
3951 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3952 break;
3953 case OP_AMD64_AND_REG_MEMBASE:
3954 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3955 break;
3956 case OP_AMD64_OR_REG_MEMBASE:
3957 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3958 break;
3959 case OP_AMD64_XOR_REG_MEMBASE:
3960 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3961 break;
3962
3963 case OP_AMD64_ADD_MEMBASE_REG:
3964 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3965 break;
3966 case OP_AMD64_SUB_MEMBASE_REG:
3967 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3968 break;
3969 case OP_AMD64_AND_MEMBASE_REG:
3970 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3971 break;
3972 case OP_AMD64_OR_MEMBASE_REG:
3973 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3974 break;
3975 case OP_AMD64_XOR_MEMBASE_REG:
3976 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3977 break;
3978
3979 case OP_AMD64_ADD_MEMBASE_IMM:
3980 g_assert (amd64_is_imm32 (ins->inst_imm));
3981 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3982 break;
3983 case OP_AMD64_SUB_MEMBASE_IMM:
3984 g_assert (amd64_is_imm32 (ins->inst_imm));
3985 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3986 break;
3987 case OP_AMD64_AND_MEMBASE_IMM:
3988 g_assert (amd64_is_imm32 (ins->inst_imm));
3989 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3990 break;
3991 case OP_AMD64_OR_MEMBASE_IMM:
3992 g_assert (amd64_is_imm32 (ins->inst_imm));
3993 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3994 break;
3995 case OP_AMD64_XOR_MEMBASE_IMM:
3996 g_assert (amd64_is_imm32 (ins->inst_imm));
3997 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3998 break;
3999
4000 case OP_BREAK:
4001 amd64_breakpoint (code);
4002 break;
4003 case OP_RELAXED_NOP:
4004 x86_prefix (code, X86_REP_PREFIX);
4005 x86_nop (code);
4006 break;
4007 case OP_HARD_NOP:
4008 x86_nop (code);
4009 break;
4010 case OP_NOP:
4011 case OP_DUMMY_USE:
4012 case OP_DUMMY_STORE:
4013 case OP_DUMMY_ICONST:
4014 case OP_DUMMY_R8CONST:
4015 case OP_NOT_REACHED:
4016 case OP_NOT_NULL:
4017 break;
4018 case OP_IL_SEQ_POINT:
4019 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4020 break;
4021 case OP_SEQ_POINT: {
4022 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4023 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4024 guint8 *label;
4025
4026 /* Load ss_tramp_var */
4027 /* This is equal to &ss_trampoline */
4028 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4029 /* Load the trampoline address */
4030 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4031 /* Call it if it is non-null */
4032 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4033 label = code;
4034 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4035 amd64_call_reg (code, AMD64_R11);
4036 amd64_patch (label, code);
4037 }
4038
4039 /*
4040 * This is the address which is saved in seq points,
4041 */
4042 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4043
4044 if (cfg->compile_aot) {
4045 guint32 offset = code - cfg->native_code;
4046 guint32 val;
4047 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4048 guint8 *label;
4049
4050 /* Load info var */
4051 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4052 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4053 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4054 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4055 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4056 label = code;
4057 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4058 /* Call the trampoline */
4059 amd64_call_reg (code, AMD64_R11);
4060 amd64_patch (label, code);
4061 } else {
4062 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4063 guint8 *label;
4064
4065 /*
4066 * Emit a test+branch against a constant, the constant will be overwritten
4067 * by mono_arch_set_breakpoint () to cause the test to fail.
4068 */
4069 amd64_mov_reg_imm (code, AMD64_R11, 0);
4070 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4071 label = code;
4072 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4073
4074 g_assert (var);
4075 g_assert (var->opcode == OP_REGOFFSET);
4076 /* Load bp_tramp_var */
4077 /* This is equal to &bp_trampoline */
4078 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4079 /* Call the trampoline */
4080 amd64_call_membase (code, AMD64_R11, 0);
4081 amd64_patch (label, code);
4082 }
4083 /*
4084 * Add an additional nop so skipping the bp doesn't cause the ip to point
4085 * to another IL offset.
4086 */
4087 x86_nop (code);
4088 break;
4089 }
4090 case OP_ADDCC:
4091 case OP_LADDCC:
4092 case OP_LADD:
4093 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4094 break;
4095 case OP_ADC:
4096 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4097 break;
4098 case OP_ADD_IMM:
4099 case OP_LADD_IMM:
4100 g_assert (amd64_is_imm32 (ins->inst_imm));
4101 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4102 break;
4103 case OP_ADC_IMM:
4104 g_assert (amd64_is_imm32 (ins->inst_imm));
4105 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4106 break;
4107 case OP_SUBCC:
4108 case OP_LSUBCC:
4109 case OP_LSUB:
4110 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4111 break;
4112 case OP_SBB:
4113 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4114 break;
4115 case OP_SUB_IMM:
4116 case OP_LSUB_IMM:
4117 g_assert (amd64_is_imm32 (ins->inst_imm));
4118 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4119 break;
4120 case OP_SBB_IMM:
4121 g_assert (amd64_is_imm32 (ins->inst_imm));
4122 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4123 break;
4124 case OP_LAND:
4125 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4126 break;
4127 case OP_AND_IMM:
4128 case OP_LAND_IMM:
4129 g_assert (amd64_is_imm32 (ins->inst_imm));
4130 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4131 break;
4132 case OP_LMUL:
4133 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4134 break;
4135 case OP_MUL_IMM:
4136 case OP_LMUL_IMM:
4137 case OP_IMUL_IMM: {
4138 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4139
4140 switch (ins->inst_imm) {
4141 case 2:
4142 /* MOV r1, r2 */
4143 /* ADD r1, r1 */
4144 if (ins->dreg != ins->sreg1)
4145 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4146 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4147 break;
4148 case 3:
4149 /* LEA r1, [r2 + r2*2] */
4150 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4151 break;
4152 case 5:
4153 /* LEA r1, [r2 + r2*4] */
4154 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4155 break;
4156 case 6:
4157 /* LEA r1, [r2 + r2*2] */
4158 /* ADD r1, r1 */
4159 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4160 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4161 break;
4162 case 9:
4163 /* LEA r1, [r2 + r2*8] */
4164 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4165 break;
4166 case 10:
4167 /* LEA r1, [r2 + r2*4] */
4168 /* ADD r1, r1 */
4169 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4170 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4171 break;
4172 case 12:
4173 /* LEA r1, [r2 + r2*2] */
4174 /* SHL r1, 2 */
4175 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4176 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4177 break;
4178 case 25:
4179 /* LEA r1, [r2 + r2*4] */
4180 /* LEA r1, [r1 + r1*4] */
4181 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4182 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4183 break;
4184 case 100:
4185 /* LEA r1, [r2 + r2*4] */
4186 /* SHL r1, 2 */
4187 /* LEA r1, [r1 + r1*4] */
4188 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4189 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4190 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4191 break;
4192 default:
4193 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4194 break;
4195 }
4196 break;
4197 }
4198 case OP_LDIV:
4199 case OP_LREM:
4200 /* Regalloc magic makes the div/rem cases the same */
4201 if (ins->sreg2 == AMD64_RDX) {
4202 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4203 amd64_cdq (code);
4204 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4205 } else {
4206 amd64_cdq (code);
4207 amd64_div_reg (code, ins->sreg2, TRUE);
4208 }
4209 break;
4210 case OP_LDIV_UN:
4211 case OP_LREM_UN:
4212 if (ins->sreg2 == AMD64_RDX) {
4213 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4214 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4215 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4216 } else {
4217 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4218 amd64_div_reg (code, ins->sreg2, FALSE);
4219 }
4220 break;
4221 case OP_IDIV:
4222 case OP_IREM:
4223 if (ins->sreg2 == AMD64_RDX) {
4224 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4225 amd64_cdq_size (code, 4);
4226 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4227 } else {
4228 amd64_cdq_size (code, 4);
4229 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4230 }
4231 break;
4232 case OP_IDIV_UN:
4233 case OP_IREM_UN:
4234 if (ins->sreg2 == AMD64_RDX) {
4235 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4236 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4237 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4238 } else {
4239 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4240 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4241 }
4242 break;
4243 case OP_LMUL_OVF:
4244 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4245 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4246 break;
4247 case OP_LOR:
4248 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4249 break;
4250 case OP_OR_IMM:
4251 case OP_LOR_IMM:
4252 g_assert (amd64_is_imm32 (ins->inst_imm));
4253 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4254 break;
4255 case OP_LXOR:
4256 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4257 break;
4258 case OP_XOR_IMM:
4259 case OP_LXOR_IMM:
4260 g_assert (amd64_is_imm32 (ins->inst_imm));
4261 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4262 break;
4263 case OP_LSHL:
4264 g_assert (ins->sreg2 == AMD64_RCX);
4265 amd64_shift_reg (code, X86_SHL, ins->dreg);
4266 break;
4267 case OP_LSHR:
4268 g_assert (ins->sreg2 == AMD64_RCX);
4269 amd64_shift_reg (code, X86_SAR, ins->dreg);
4270 break;
4271 case OP_SHR_IMM:
4272 case OP_LSHR_IMM:
4273 g_assert (amd64_is_imm32 (ins->inst_imm));
4274 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4275 break;
4276 case OP_SHR_UN_IMM:
4277 g_assert (amd64_is_imm32 (ins->inst_imm));
4278 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4279 break;
4280 case OP_LSHR_UN_IMM:
4281 g_assert (amd64_is_imm32 (ins->inst_imm));
4282 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4283 break;
4284 case OP_LSHR_UN:
4285 g_assert (ins->sreg2 == AMD64_RCX);
4286 amd64_shift_reg (code, X86_SHR, ins->dreg);
4287 break;
4288 case OP_SHL_IMM:
4289 case OP_LSHL_IMM:
4290 g_assert (amd64_is_imm32 (ins->inst_imm));
4291 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4292 break;
4293
4294 case OP_IADDCC:
4295 case OP_IADD:
4296 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4297 break;
4298 case OP_IADC:
4299 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4300 break;
4301 case OP_IADD_IMM:
4302 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4303 break;
4304 case OP_IADC_IMM:
4305 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4306 break;
4307 case OP_ISUBCC:
4308 case OP_ISUB:
4309 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4310 break;
4311 case OP_ISBB:
4312 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4313 break;
4314 case OP_ISUB_IMM:
4315 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4316 break;
4317 case OP_ISBB_IMM:
4318 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4319 break;
4320 case OP_IAND:
4321 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4322 break;
4323 case OP_IAND_IMM:
4324 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4325 break;
4326 case OP_IOR:
4327 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4328 break;
4329 case OP_IOR_IMM:
4330 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4331 break;
4332 case OP_IXOR:
4333 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4334 break;
4335 case OP_IXOR_IMM:
4336 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4337 break;
4338 case OP_INEG:
4339 amd64_neg_reg_size (code, ins->sreg1, 4);
4340 break;
4341 case OP_INOT:
4342 amd64_not_reg_size (code, ins->sreg1, 4);
4343 break;
4344 case OP_ISHL:
4345 g_assert (ins->sreg2 == AMD64_RCX);
4346 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4347 break;
4348 case OP_ISHR:
4349 g_assert (ins->sreg2 == AMD64_RCX);
4350 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4351 break;
4352 case OP_ISHR_IMM:
4353 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4354 break;
4355 case OP_ISHR_UN_IMM:
4356 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4357 break;
4358 case OP_ISHR_UN:
4359 g_assert (ins->sreg2 == AMD64_RCX);
4360 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4361 break;
4362 case OP_ISHL_IMM:
4363 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4364 break;
4365 case OP_IMUL:
4366 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4367 break;
4368 case OP_IMUL_OVF:
4369 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4370 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4371 break;
4372 case OP_IMUL_OVF_UN:
4373 case OP_LMUL_OVF_UN: {
4374 /* the mul operation and the exception check should most likely be split */
4375 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4376 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4377 /*g_assert (ins->sreg2 == X86_EAX);
4378 g_assert (ins->dreg == X86_EAX);*/
4379 if (ins->sreg2 == X86_EAX) {
4380 non_eax_reg = ins->sreg1;
4381 } else if (ins->sreg1 == X86_EAX) {
4382 non_eax_reg = ins->sreg2;
4383 } else {
4384 /* no need to save since we're going to store to it anyway */
4385 if (ins->dreg != X86_EAX) {
4386 saved_eax = TRUE;
4387 amd64_push_reg (code, X86_EAX);
4388 }
4389 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4390 non_eax_reg = ins->sreg2;
4391 }
4392 if (ins->dreg == X86_EDX) {
4393 if (!saved_eax) {
4394 saved_eax = TRUE;
4395 amd64_push_reg (code, X86_EAX);
4396 }
4397 } else {
4398 saved_edx = TRUE;
4399 amd64_push_reg (code, X86_EDX);
4400 }
4401 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4402 /* save before the check since pop and mov don't change the flags */
4403 if (ins->dreg != X86_EAX)
4404 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4405 if (saved_edx)
4406 amd64_pop_reg (code, X86_EDX);
4407 if (saved_eax)
4408 amd64_pop_reg (code, X86_EAX);
4409 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4410 break;
4411 }
4412 case OP_ICOMPARE:
4413 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4414 break;
4415 case OP_ICOMPARE_IMM:
4416 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4417 break;
4418 case OP_IBEQ:
4419 case OP_IBLT:
4420 case OP_IBGT:
4421 case OP_IBGE:
4422 case OP_IBLE:
4423 case OP_LBEQ:
4424 case OP_LBLT:
4425 case OP_LBGT:
4426 case OP_LBGE:
4427 case OP_LBLE:
4428 case OP_IBNE_UN:
4429 case OP_IBLT_UN:
4430 case OP_IBGT_UN:
4431 case OP_IBGE_UN:
4432 case OP_IBLE_UN:
4433 case OP_LBNE_UN:
4434 case OP_LBLT_UN:
4435 case OP_LBGT_UN:
4436 case OP_LBGE_UN:
4437 case OP_LBLE_UN:
4438 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4439 break;
4440
4441 case OP_CMOV_IEQ:
4442 case OP_CMOV_IGE:
4443 case OP_CMOV_IGT:
4444 case OP_CMOV_ILE:
4445 case OP_CMOV_ILT:
4446 case OP_CMOV_INE_UN:
4447 case OP_CMOV_IGE_UN:
4448 case OP_CMOV_IGT_UN:
4449 case OP_CMOV_ILE_UN:
4450 case OP_CMOV_ILT_UN:
4451 case OP_CMOV_LEQ:
4452 case OP_CMOV_LGE:
4453 case OP_CMOV_LGT:
4454 case OP_CMOV_LLE:
4455 case OP_CMOV_LLT:
4456 case OP_CMOV_LNE_UN:
4457 case OP_CMOV_LGE_UN:
4458 case OP_CMOV_LGT_UN:
4459 case OP_CMOV_LLE_UN:
4460 case OP_CMOV_LLT_UN:
4461 g_assert (ins->dreg == ins->sreg1);
4462 /* This needs to operate on 64 bit values */
4463 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4464 break;
4465
4466 case OP_LNOT:
4467 amd64_not_reg (code, ins->sreg1);
4468 break;
4469 case OP_LNEG:
4470 amd64_neg_reg (code, ins->sreg1);
4471 break;
4472
4473 case OP_ICONST:
4474 case OP_I8CONST:
4475 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4476 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4477 else
4478 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4479 break;
4480 case OP_AOTCONST:
4481 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4482 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4483 break;
4484 case OP_JUMP_TABLE:
4485 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4486 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4487 break;
4488 case OP_MOVE:
4489 if (ins->dreg != ins->sreg1)
4490 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4491 break;
4492 case OP_AMD64_SET_XMMREG_R4: {
4493 if (cfg->r4fp) {
4494 if (ins->dreg != ins->sreg1)
4495 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4496 } else {
4497 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4498 }
4499 break;
4500 }
4501 case OP_AMD64_SET_XMMREG_R8: {
4502 if (ins->dreg != ins->sreg1)
4503 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4504 break;
4505 }
4506 case OP_TAILCALL: {
4507 MonoCallInst *call = (MonoCallInst*)ins;
4508 int i, save_area_offset;
4509
4510 g_assert (!cfg->method->save_lmf);
4511
4512 /* the size of the tailcall op depends on signature, let's check for enough
4513 * space in the code buffer here again */
4514 max_len += AMD64_NREG * 4 + call->stack_usage * 15 + EXTRA_CODE_SPACE;
4515
4516 if (G_UNLIKELY (offset + max_len > cfg->code_size)) {
4517 cfg->code_size *= 2;
4518 cfg->native_code = (unsigned char *) mono_realloc_native_code(cfg);
4519 code = cfg->native_code + offset;
4520 cfg->stat_code_reallocs++;
4521 }
4522
4523 /* Restore callee saved registers */
4524 save_area_offset = cfg->arch.reg_save_area_offset;
4525 for (i = 0; i < AMD64_NREG; ++i)
4526 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4527 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4528 save_area_offset += 8;
4529 }
4530
4531 if (cfg->arch.omit_fp) {
4532 if (cfg->arch.stack_alloc_size)
4533 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4534 // FIXME:
4535 if (call->stack_usage)
4536 NOT_IMPLEMENTED;
4537 } else {
4538 /* Copy arguments on the stack to our argument area */
4539 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4540 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4541 amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4542 }
4543
4544 #ifdef TARGET_WIN32
4545 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4546 amd64_pop_reg (code, AMD64_RBP);
4547 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4548 #else
4549 amd64_leave (code);
4550 #endif
4551 }
4552
4553 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4554 if (cfg->compile_aot)
4555 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4556 else
4557 amd64_set_reg_template (code, AMD64_R11);
4558 amd64_jump_reg (code, AMD64_R11);
4559 ins->flags |= MONO_INST_GC_CALLSITE;
4560 ins->backend.pc_offset = code - cfg->native_code;
4561 break;
4562 }
4563 case OP_CHECK_THIS:
4564 /* ensure ins->sreg1 is not NULL */
4565 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4566 break;
4567 case OP_ARGLIST: {
4568 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4569 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4570 break;
4571 }
4572 case OP_CALL:
4573 case OP_FCALL:
4574 case OP_RCALL:
4575 case OP_LCALL:
4576 case OP_VCALL:
4577 case OP_VCALL2:
4578 case OP_VOIDCALL:
4579 call = (MonoCallInst*)ins;
4580 /*
4581 * The AMD64 ABI forces callers to know about varargs.
4582 */
4583 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4584 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4585 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4586 /*
4587 * Since the unmanaged calling convention doesn't contain a
4588 * 'vararg' entry, we have to treat every pinvoke call as a
4589 * potential vararg call.
4590 */
4591 guint32 nregs, i;
4592 nregs = 0;
4593 for (i = 0; i < AMD64_XMM_NREG; ++i)
4594 if (call->used_fregs & (1 << i))
4595 nregs ++;
4596 if (!nregs)
4597 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4598 else
4599 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4600 }
4601
4602 if (ins->flags & MONO_INST_HAS_METHOD)
4603 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4604 else
4605 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4606 ins->flags |= MONO_INST_GC_CALLSITE;
4607 ins->backend.pc_offset = code - cfg->native_code;
4608 code = emit_move_return_value (cfg, ins, code);
4609 break;
4610 case OP_FCALL_REG:
4611 case OP_RCALL_REG:
4612 case OP_LCALL_REG:
4613 case OP_VCALL_REG:
4614 case OP_VCALL2_REG:
4615 case OP_VOIDCALL_REG:
4616 case OP_CALL_REG:
4617 call = (MonoCallInst*)ins;
4618
4619 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4620 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4621 ins->sreg1 = AMD64_R11;
4622 }
4623
4624 /*
4625 * The AMD64 ABI forces callers to know about varargs.
4626 */
4627 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4628 if (ins->sreg1 == AMD64_RAX) {
4629 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4630 ins->sreg1 = AMD64_R11;
4631 }
4632 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4633 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4634 /*
4635 * Since the unmanaged calling convention doesn't contain a
4636 * 'vararg' entry, we have to treat every pinvoke call as a
4637 * potential vararg call.
4638 */
4639 guint32 nregs, i;
4640 nregs = 0;
4641 for (i = 0; i < AMD64_XMM_NREG; ++i)
4642 if (call->used_fregs & (1 << i))
4643 nregs ++;
4644 if (ins->sreg1 == AMD64_RAX) {
4645 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4646 ins->sreg1 = AMD64_R11;
4647 }
4648 if (!nregs)
4649 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4650 else
4651 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4652 }
4653
4654 amd64_call_reg (code, ins->sreg1);
4655 ins->flags |= MONO_INST_GC_CALLSITE;
4656 ins->backend.pc_offset = code - cfg->native_code;
4657 code = emit_move_return_value (cfg, ins, code);
4658 break;
4659 case OP_FCALL_MEMBASE:
4660 case OP_RCALL_MEMBASE:
4661 case OP_LCALL_MEMBASE:
4662 case OP_VCALL_MEMBASE:
4663 case OP_VCALL2_MEMBASE:
4664 case OP_VOIDCALL_MEMBASE:
4665 case OP_CALL_MEMBASE:
4666 call = (MonoCallInst*)ins;
4667
4668 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4669 ins->flags |= MONO_INST_GC_CALLSITE;
4670 ins->backend.pc_offset = code - cfg->native_code;
4671 code = emit_move_return_value (cfg, ins, code);
4672 break;
4673 case OP_DYN_CALL: {
4674 int i, limit_reg, index_reg, src_reg, dst_reg;
4675 MonoInst *var = cfg->dyn_call_var;
4676 guint8 *label;
4677 guint8 *buf [16];
4678
4679 g_assert (var->opcode == OP_REGOFFSET);
4680
4681 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4682 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4683 /* r10 = ftn */
4684 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4685
4686 /* Save args buffer */
4687 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4688
4689 /* Set fp arg regs */
4690 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4691 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4692 label = code;
4693 amd64_branch8 (code, X86_CC_Z, -1, 1);
4694 for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4695 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4696 amd64_patch (label, code);
4697
4698 /* Allocate param area */
4699 /* This doesn't need to be freed since OP_DYN_CALL is never called in a loop */
4700 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
4701 amd64_shift_reg_imm (code, X86_SHL, AMD64_RAX, 3);
4702 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, AMD64_RAX);
4703 /* Set stack args */
4704 /* rax/rcx/rdx/r8/r9 is scratch */
4705 limit_reg = AMD64_RAX;
4706 index_reg = AMD64_RCX;
4707 src_reg = AMD64_R8;
4708 dst_reg = AMD64_R9;
4709 amd64_mov_reg_membase (code, limit_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, nstack_args), 8);
4710 amd64_mov_reg_imm (code, index_reg, 0);
4711 amd64_lea_membase (code, src_reg, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS) * sizeof(mgreg_t)));
4712 amd64_mov_reg_reg (code, dst_reg, AMD64_RSP, 8);
4713 buf [0] = code;
4714 x86_jump8 (code, 0);
4715 buf [1] = code;
4716 amd64_mov_reg_membase (code, AMD64_RDX, src_reg, 0, 8);
4717 amd64_mov_membase_reg (code, dst_reg, 0, AMD64_RDX, 8);
4718 amd64_alu_reg_imm (code, X86_ADD, index_reg, 1);
4719 amd64_alu_reg_imm (code, X86_ADD, src_reg, 8);
4720 amd64_alu_reg_imm (code, X86_ADD, dst_reg, 8);
4721 amd64_patch (buf [0], code);
4722 amd64_alu_reg_reg (code, X86_CMP, index_reg, limit_reg);
4723 buf [2] = code;
4724 x86_branch8 (code, X86_CC_LT, 0, FALSE);
4725 amd64_patch (buf [2], buf [1]);
4726
4727 /* Set argument registers */
4728 for (i = 0; i < PARAM_REGS; ++i)
4729 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + (i * sizeof(mgreg_t)), sizeof(mgreg_t));
4730
4731 /* Make the call */
4732 amd64_call_reg (code, AMD64_R10);
4733
4734 ins->flags |= MONO_INST_GC_CALLSITE;
4735 ins->backend.pc_offset = code - cfg->native_code;
4736
4737 /* Save result */
4738 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4739 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4740 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4741 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4742 break;
4743 }
4744 case OP_AMD64_SAVE_SP_TO_LMF: {
4745 MonoInst *lmf_var = cfg->lmf_var;
4746 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4747 break;
4748 }
4749 case OP_X86_PUSH:
4750 g_assert_not_reached ();
4751 amd64_push_reg (code, ins->sreg1);
4752 break;
4753 case OP_X86_PUSH_IMM:
4754 g_assert_not_reached ();
4755 g_assert (amd64_is_imm32 (ins->inst_imm));
4756 amd64_push_imm (code, ins->inst_imm);
4757 break;
4758 case OP_X86_PUSH_MEMBASE:
4759 g_assert_not_reached ();
4760 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4761 break;
4762 case OP_X86_PUSH_OBJ: {
4763 int size = ALIGN_TO (ins->inst_imm, 8);
4764
4765 g_assert_not_reached ();
4766
4767 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4768 amd64_push_reg (code, AMD64_RDI);
4769 amd64_push_reg (code, AMD64_RSI);
4770 amd64_push_reg (code, AMD64_RCX);
4771 if (ins->inst_offset)
4772 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4773 else
4774 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4775 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4776 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4777 amd64_cld (code);
4778 amd64_prefix (code, X86_REP_PREFIX);
4779 amd64_movsd (code);
4780 amd64_pop_reg (code, AMD64_RCX);
4781 amd64_pop_reg (code, AMD64_RSI);
4782 amd64_pop_reg (code, AMD64_RDI);
4783 break;
4784 }
4785 case OP_GENERIC_CLASS_INIT: {
4786 guint8 *jump;
4787
4788 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4789
4790 amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4791 jump = code;
4792 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4793
4794 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4795 ins->flags |= MONO_INST_GC_CALLSITE;
4796 ins->backend.pc_offset = code - cfg->native_code;
4797
4798 x86_patch (jump, code);
4799 break;
4800 }
4801
4802 case OP_X86_LEA:
4803 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4804 break;
4805 case OP_X86_LEA_MEMBASE:
4806 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4807 break;
4808 case OP_X86_XCHG:
4809 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4810 break;
4811 case OP_LOCALLOC:
4812 /* keep alignment */
4813 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4814 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4815 code = mono_emit_stack_alloc (cfg, code, ins);
4816 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4817 if (cfg->param_area)
4818 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4819 break;
4820 case OP_LOCALLOC_IMM: {
4821 guint32 size = ins->inst_imm;
4822 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4823
4824 if (ins->flags & MONO_INST_INIT) {
4825 if (size < 64) {
4826 int i;
4827
4828 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4829 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4830
4831 for (i = 0; i < size; i += 8)
4832 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4833 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4834 } else {
4835 amd64_mov_reg_imm (code, ins->dreg, size);
4836 ins->sreg1 = ins->dreg;
4837
4838 code = mono_emit_stack_alloc (cfg, code, ins);
4839 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4840 }
4841 } else {
4842 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4843 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4844 }
4845 if (cfg->param_area)
4846 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4847 break;
4848 }
4849 case OP_THROW: {
4850 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4851 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4852 (gpointer)"mono_arch_throw_exception", FALSE);
4853 ins->flags |= MONO_INST_GC_CALLSITE;
4854 ins->backend.pc_offset = code - cfg->native_code;
4855 break;
4856 }
4857 case OP_RETHROW: {
4858 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4859 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4860 (gpointer)"mono_arch_rethrow_exception", FALSE);
4861 ins->flags |= MONO_INST_GC_CALLSITE;
4862 ins->backend.pc_offset = code - cfg->native_code;
4863 break;
4864 }
4865 case OP_CALL_HANDLER:
4866 /* Align stack */
4867 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4868 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4869 amd64_call_imm (code, 0);
4870 /*
4871 * ins->inst_eh_blocks and bb->clause_holes are part of same GList.
4872 * Holes from bb->clause_holes will be added separately for the entire
4873 * basic block. Add only the rest of them.
4874 */
4875 for (GList *tmp = ins->inst_eh_blocks; tmp != bb->clause_holes; tmp = tmp->prev)
4876 mono_cfg_add_try_hole (cfg, (MonoExceptionClause *)tmp->data, code, bb);
4877 /* Restore stack alignment */
4878 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4879 break;
4880 case OP_START_HANDLER: {
4881 /* Even though we're saving RSP, use sizeof */
4882 /* gpointer because spvar is of type IntPtr */
4883 /* see: mono_create_spvar_for_region */
4884 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4885 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4886
4887 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4888 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FILTER)) &&
4889 cfg->param_area) {
4890 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4891 }
4892 break;
4893 }
4894 case OP_ENDFINALLY: {
4895 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4896 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4897 amd64_ret (code);
4898 break;
4899 }
4900 case OP_ENDFILTER: {
4901 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4902 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4903 /* The local allocator will put the result into RAX */
4904 amd64_ret (code);
4905 break;
4906 }
4907 case OP_GET_EX_OBJ:
4908 if (ins->dreg != AMD64_RAX)
4909 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4910 break;
4911 case OP_LABEL:
4912 ins->inst_c0 = code - cfg->native_code;
4913 break;
4914 case OP_BR:
4915 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4916 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4917 //break;
4918 if (ins->inst_target_bb->native_offset) {
4919 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4920 } else {
4921 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4922 if ((cfg->opt & MONO_OPT_BRANCH) &&
4923 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4924 x86_jump8 (code, 0);
4925 else
4926 x86_jump32 (code, 0);
4927 }
4928 break;
4929 case OP_BR_REG:
4930 amd64_jump_reg (code, ins->sreg1);
4931 break;
4932 case OP_ICNEQ:
4933 case OP_ICGE:
4934 case OP_ICLE:
4935 case OP_ICGE_UN:
4936 case OP_ICLE_UN:
4937
4938 case OP_CEQ:
4939 case OP_LCEQ:
4940 case OP_ICEQ:
4941 case OP_CLT:
4942 case OP_LCLT:
4943 case OP_ICLT:
4944 case OP_CGT:
4945 case OP_ICGT:
4946 case OP_LCGT:
4947 case OP_CLT_UN:
4948 case OP_LCLT_UN:
4949 case OP_ICLT_UN:
4950 case OP_CGT_UN:
4951 case OP_LCGT_UN:
4952 case OP_ICGT_UN:
4953 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4954 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4955 break;
4956 case OP_COND_EXC_EQ:
4957 case OP_COND_EXC_NE_UN:
4958 case OP_COND_EXC_LT:
4959 case OP_COND_EXC_LT_UN:
4960 case OP_COND_EXC_GT:
4961 case OP_COND_EXC_GT_UN:
4962 case OP_COND_EXC_GE:
4963 case OP_COND_EXC_GE_UN:
4964 case OP_COND_EXC_LE:
4965 case OP_COND_EXC_LE_UN:
4966 case OP_COND_EXC_IEQ:
4967 case OP_COND_EXC_INE_UN:
4968 case OP_COND_EXC_ILT:
4969 case OP_COND_EXC_ILT_UN:
4970 case OP_COND_EXC_IGT:
4971 case OP_COND_EXC_IGT_UN:
4972 case OP_COND_EXC_IGE:
4973 case OP_COND_EXC_IGE_UN:
4974 case OP_COND_EXC_ILE:
4975 case OP_COND_EXC_ILE_UN:
4976 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4977 break;
4978 case OP_COND_EXC_OV:
4979 case OP_COND_EXC_NO:
4980 case OP_COND_EXC_C:
4981 case OP_COND_EXC_NC:
4982 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4983 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4984 break;
4985 case OP_COND_EXC_IOV:
4986 case OP_COND_EXC_INO:
4987 case OP_COND_EXC_IC:
4988 case OP_COND_EXC_INC:
4989 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4990 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4991 break;
4992
4993 /* floating point opcodes */
4994 case OP_R8CONST: {
4995 double d = *(double *)ins->inst_p0;
4996
4997 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4998 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4999 }
5000 else {
5001 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5002 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5003 }
5004 break;
5005 }
5006 case OP_R4CONST: {
5007 float f = *(float *)ins->inst_p0;
5008
5009 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5010 if (cfg->r4fp)
5011 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5012 else
5013 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5014 }
5015 else {
5016 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5017 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5018 if (!cfg->r4fp)
5019 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5020 }
5021 break;
5022 }
5023 case OP_STORER8_MEMBASE_REG:
5024 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5025 break;
5026 case OP_LOADR8_MEMBASE:
5027 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5028 break;
5029 case OP_STORER4_MEMBASE_REG:
5030 if (cfg->r4fp) {
5031 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5032 } else {
5033 /* This requires a double->single conversion */
5034 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5035 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5036 }
5037 break;
5038 case OP_LOADR4_MEMBASE:
5039 if (cfg->r4fp) {
5040 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5041 } else {
5042 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5043 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5044 }
5045 break;
5046 case OP_ICONV_TO_R4:
5047 if (cfg->r4fp) {
5048 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5049 } else {
5050 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5051 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5052 }
5053 break;
5054 case OP_ICONV_TO_R8:
5055 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5056 break;
5057 case OP_LCONV_TO_R4:
5058 if (cfg->r4fp) {
5059 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5060 } else {
5061 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5062 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5063 }
5064 break;
5065 case OP_LCONV_TO_R8:
5066 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5067 break;
5068 case OP_FCONV_TO_R4:
5069 if (cfg->r4fp) {
5070 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5071 } else {
5072 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5073 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5074 }
5075 break;
5076 case OP_FCONV_TO_I1:
5077 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5078 break;
5079 case OP_FCONV_TO_U1:
5080 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5081 break;
5082 case OP_FCONV_TO_I2:
5083 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5084 break;
5085 case OP_FCONV_TO_U2:
5086 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5087 break;
5088 case OP_FCONV_TO_U4:
5089 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5090 break;
5091 case OP_FCONV_TO_I4:
5092 case OP_FCONV_TO_I:
5093 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5094 break;
5095 case OP_FCONV_TO_I8:
5096 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5097 break;
5098
5099 case OP_RCONV_TO_I1:
5100 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5101 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5102 break;
5103 case OP_RCONV_TO_U1:
5104 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5105 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5106 break;
5107 case OP_RCONV_TO_I2:
5108 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5109 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5110 break;
5111 case OP_RCONV_TO_U2:
5112 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5113 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5114 break;
5115 case OP_RCONV_TO_I4:
5116 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5117 break;
5118 case OP_RCONV_TO_U4:
5119 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5120 break;
5121 case OP_RCONV_TO_I8:
5122 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5123 break;
5124 case OP_RCONV_TO_R8:
5125 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5126 break;
5127 case OP_RCONV_TO_R4:
5128 if (ins->dreg != ins->sreg1)
5129 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5130 break;
5131
5132 case OP_LCONV_TO_R_UN: {
5133 guint8 *br [2];
5134
5135 /* Based on gcc code */
5136 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5137 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5138
5139 /* Positive case */
5140 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5141 br [1] = code; x86_jump8 (code, 0);
5142 amd64_patch (br [0], code);
5143
5144 /* Negative case */
5145 /* Save to the red zone */
5146 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5147 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5148 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5149 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5150 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5151 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5152 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5153 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5154 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5155 /* Restore */
5156 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5157 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5158 amd64_patch (br [1], code);
5159 break;
5160 }
5161 case OP_LCONV_TO_OVF_U4:
5162 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5163 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5164 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5165 break;
5166 case OP_LCONV_TO_OVF_I4_UN:
5167 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5168 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5169 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5170 break;
5171 case OP_FMOVE:
5172 if (ins->dreg != ins->sreg1)
5173 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5174 break;
5175 case OP_RMOVE:
5176 if (ins->dreg != ins->sreg1)
5177 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5178 break;
5179 case OP_MOVE_F_TO_I4:
5180 if (cfg->r4fp) {
5181 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5182 } else {
5183 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5184 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5185 }
5186 break;
5187 case OP_MOVE_I4_TO_F:
5188 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5189 if (!cfg->r4fp)
5190 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5191 break;
5192 case OP_MOVE_F_TO_I8:
5193 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5194 break;
5195 case OP_MOVE_I8_TO_F:
5196 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5197 break;
5198 case OP_FADD:
5199 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5200 break;
5201 case OP_FSUB:
5202 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5203 break;
5204 case OP_FMUL:
5205 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5206 break;
5207 case OP_FDIV:
5208 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5209 break;
5210 case OP_FNEG: {
5211 static double r8_0 = -0.0;
5212
5213 g_assert (ins->sreg1 == ins->dreg);
5214
5215 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5216 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5217 break;
5218 }
5219 case OP_SIN:
5220 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5221 break;
5222 case OP_COS:
5223 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5224 break;
5225 case OP_ABS: {
5226 static guint64 d = 0x7fffffffffffffffUL;
5227
5228 g_assert (ins->sreg1 == ins->dreg);
5229
5230 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5231 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5232 break;
5233 }
5234 case OP_SQRT:
5235 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5236 break;
5237
5238 case OP_RADD:
5239 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5240 break;
5241 case OP_RSUB:
5242 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5243 break;
5244 case OP_RMUL:
5245 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5246 break;
5247 case OP_RDIV:
5248 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5249 break;
5250 case OP_RNEG: {
5251 static float r4_0 = -0.0;
5252
5253 g_assert (ins->sreg1 == ins->dreg);
5254
5255 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5256 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5257 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5258 break;
5259 }
5260
5261 case OP_IMIN:
5262 g_assert (cfg->opt & MONO_OPT_CMOV);
5263 g_assert (ins->dreg == ins->sreg1);
5264 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5265 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5266 break;
5267 case OP_IMIN_UN:
5268 g_assert (cfg->opt & MONO_OPT_CMOV);
5269 g_assert (ins->dreg == ins->sreg1);
5270 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5271 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5272 break;
5273 case OP_IMAX:
5274 g_assert (cfg->opt & MONO_OPT_CMOV);
5275 g_assert (ins->dreg == ins->sreg1);
5276 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5277 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5278 break;
5279 case OP_IMAX_UN:
5280 g_assert (cfg->opt & MONO_OPT_CMOV);
5281 g_assert (ins->dreg == ins->sreg1);
5282 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5283 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5284 break;
5285 case OP_LMIN:
5286 g_assert (cfg->opt & MONO_OPT_CMOV);
5287 g_assert (ins->dreg == ins->sreg1);
5288 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5289 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5290 break;
5291 case OP_LMIN_UN:
5292 g_assert (cfg->opt & MONO_OPT_CMOV);
5293 g_assert (ins->dreg == ins->sreg1);
5294 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5295 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5296 break;
5297 case OP_LMAX:
5298 g_assert (cfg->opt & MONO_OPT_CMOV);
5299 g_assert (ins->dreg == ins->sreg1);
5300 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5301 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5302 break;
5303 case OP_LMAX_UN:
5304 g_assert (cfg->opt & MONO_OPT_CMOV);
5305 g_assert (ins->dreg == ins->sreg1);
5306 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5307 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5308 break;
5309 case OP_X86_FPOP:
5310 break;
5311 case OP_FCOMPARE:
5312 /*
5313 * The two arguments are swapped because the fbranch instructions
5314 * depend on this for the non-sse case to work.
5315 */
5316 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5317 break;
5318 case OP_RCOMPARE:
5319 /*
5320 * FIXME: Get rid of this.
5321 * The two arguments are swapped because the fbranch instructions
5322 * depend on this for the non-sse case to work.
5323 */
5324 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5325 break;
5326 case OP_FCNEQ:
5327 case OP_FCEQ: {
5328 /* zeroing the register at the start results in
5329 * shorter and faster code (we can also remove the widening op)
5330 */
5331 guchar *unordered_check;
5332
5333 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5334 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5335 unordered_check = code;
5336 x86_branch8 (code, X86_CC_P, 0, FALSE);
5337
5338 if (ins->opcode == OP_FCEQ) {
5339 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5340 amd64_patch (unordered_check, code);
5341 } else {
5342 guchar *jump_to_end;
5343 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5344 jump_to_end = code;
5345 x86_jump8 (code, 0);
5346 amd64_patch (unordered_check, code);
5347 amd64_inc_reg (code, ins->dreg);
5348 amd64_patch (jump_to_end, code);
5349 }
5350 break;
5351 }
5352 case OP_FCLT:
5353 case OP_FCLT_UN: {
5354 /* zeroing the register at the start results in
5355 * shorter and faster code (we can also remove the widening op)
5356 */
5357 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5358 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5359 if (ins->opcode == OP_FCLT_UN) {
5360 guchar *unordered_check = code;
5361 guchar *jump_to_end;
5362 x86_branch8 (code, X86_CC_P, 0, FALSE);
5363 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5364 jump_to_end = code;
5365 x86_jump8 (code, 0);
5366 amd64_patch (unordered_check, code);
5367 amd64_inc_reg (code, ins->dreg);
5368 amd64_patch (jump_to_end, code);
5369 } else {
5370 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5371 }
5372 break;
5373 }
5374 case OP_FCLE: {
5375 guchar *unordered_check;
5376 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5377 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5378 unordered_check = code;
5379 x86_branch8 (code, X86_CC_P, 0, FALSE);
5380 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5381 amd64_patch (unordered_check, code);
5382 break;
5383 }
5384 case OP_FCGT:
5385 case OP_FCGT_UN: {
5386 /* zeroing the register at the start results in
5387 * shorter and faster code (we can also remove the widening op)
5388 */
5389 guchar *unordered_check;
5390
5391 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5392 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5393 if (ins->opcode == OP_FCGT) {
5394 unordered_check = code;
5395 x86_branch8 (code, X86_CC_P, 0, FALSE);
5396 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5397 amd64_patch (unordered_check, code);
5398 } else {
5399 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5400 }
5401 break;
5402 }
5403 case OP_FCGE: {
5404 guchar *unordered_check;
5405 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5406 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5407 unordered_check = code;
5408 x86_branch8 (code, X86_CC_P, 0, FALSE);
5409 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5410 amd64_patch (unordered_check, code);
5411 break;
5412 }
5413
5414 case OP_RCEQ:
5415 case OP_RCGT:
5416 case OP_RCLT:
5417 case OP_RCLT_UN:
5418 case OP_RCGT_UN: {
5419 int x86_cond;
5420 gboolean unordered = FALSE;
5421
5422 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5423 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5424
5425 switch (ins->opcode) {
5426 case OP_RCEQ:
5427 x86_cond = X86_CC_EQ;
5428 break;
5429 case OP_RCGT:
5430 x86_cond = X86_CC_LT;
5431 break;
5432 case OP_RCLT:
5433 x86_cond = X86_CC_GT;
5434 break;
5435 case OP_RCLT_UN:
5436 x86_cond = X86_CC_GT;
5437 unordered = TRUE;
5438 break;
5439 case OP_RCGT_UN:
5440 x86_cond = X86_CC_LT;
5441 unordered = TRUE;
5442 break;
5443 default:
5444 g_assert_not_reached ();
5445 break;
5446 }
5447
5448 if (unordered) {
5449 guchar *unordered_check;
5450 guchar *jump_to_end;
5451
5452 unordered_check = code;
5453 x86_branch8 (code, X86_CC_P, 0, FALSE);
5454 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5455 jump_to_end = code;
5456 x86_jump8 (code, 0);
5457 amd64_patch (unordered_check, code);
5458 amd64_inc_reg (code, ins->dreg);
5459 amd64_patch (jump_to_end, code);
5460 } else {
5461 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5462 }
5463 break;
5464 }
5465 case OP_FCLT_MEMBASE:
5466 case OP_FCGT_MEMBASE:
5467 case OP_FCLT_UN_MEMBASE:
5468 case OP_FCGT_UN_MEMBASE:
5469 case OP_FCEQ_MEMBASE: {
5470 guchar *unordered_check, *jump_to_end;
5471 int x86_cond;
5472
5473 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5474 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5475
5476 switch (ins->opcode) {
5477 case OP_FCEQ_MEMBASE:
5478 x86_cond = X86_CC_EQ;
5479 break;
5480 case OP_FCLT_MEMBASE:
5481 case OP_FCLT_UN_MEMBASE:
5482 x86_cond = X86_CC_LT;
5483 break;
5484 case OP_FCGT_MEMBASE:
5485 case OP_FCGT_UN_MEMBASE:
5486 x86_cond = X86_CC_GT;
5487 break;
5488 default:
5489 g_assert_not_reached ();
5490 }
5491
5492 unordered_check = code;
5493 x86_branch8 (code, X86_CC_P, 0, FALSE);
5494 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5495
5496 switch (ins->opcode) {
5497 case OP_FCEQ_MEMBASE:
5498 case OP_FCLT_MEMBASE:
5499 case OP_FCGT_MEMBASE:
5500 amd64_patch (unordered_check, code);
5501 break;
5502 case OP_FCLT_UN_MEMBASE:
5503 case OP_FCGT_UN_MEMBASE:
5504 jump_to_end = code;
5505 x86_jump8 (code, 0);
5506 amd64_patch (unordered_check, code);
5507 amd64_inc_reg (code, ins->dreg);
5508 amd64_patch (jump_to_end, code);
5509 break;
5510 default:
5511 break;
5512 }
5513 break;
5514 }
5515 case OP_FBEQ: {
5516 guchar *jump = code;
5517 x86_branch8 (code, X86_CC_P, 0, TRUE);
5518 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5519 amd64_patch (jump, code);
5520 break;
5521 }
5522 case OP_FBNE_UN:
5523 /* Branch if C013 != 100 */
5524 /* branch if !ZF or (PF|CF) */
5525 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5526 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5527 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5528 break;
5529 case OP_FBLT:
5530 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5531 break;
5532 case OP_FBLT_UN:
5533 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5534 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5535 break;
5536 case OP_FBGT:
5537 case OP_FBGT_UN:
5538 if (ins->opcode == OP_FBGT) {
5539 guchar *br1;
5540
5541 /* skip branch if C1=1 */
5542 br1 = code;
5543 x86_branch8 (code, X86_CC_P, 0, FALSE);
5544 /* branch if (C0 | C3) = 1 */
5545 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5546 amd64_patch (br1, code);
5547 break;
5548 } else {
5549 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5550 }
5551 break;
5552 case OP_FBGE: {
5553 /* Branch if C013 == 100 or 001 */
5554 guchar *br1;
5555
5556 /* skip branch if C1=1 */
5557 br1 = code;
5558 x86_branch8 (code, X86_CC_P, 0, FALSE);
5559 /* branch if (C0 | C3) = 1 */
5560 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5561 amd64_patch (br1, code);
5562 break;
5563 }
5564 case OP_FBGE_UN:
5565 /* Branch if C013 == 000 */
5566 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5567 break;
5568 case OP_FBLE: {
5569 /* Branch if C013=000 or 100 */
5570 guchar *br1;
5571
5572 /* skip branch if C1=1 */
5573 br1 = code;
5574 x86_branch8 (code, X86_CC_P, 0, FALSE);
5575 /* branch if C0=0 */
5576 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5577 amd64_patch (br1, code);
5578 break;
5579 }
5580 case OP_FBLE_UN:
5581 /* Branch if C013 != 001 */
5582 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5583 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5584 break;
5585 case OP_CKFINITE:
5586 /* Transfer value to the fp stack */
5587 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5588 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5589 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5590
5591 amd64_push_reg (code, AMD64_RAX);
5592 amd64_fxam (code);
5593 amd64_fnstsw (code);
5594 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5595 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5596 amd64_pop_reg (code, AMD64_RAX);
5597 amd64_fstp (code, 0);
5598 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5599 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5600 break;
5601 case OP_TLS_GET: {
5602 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5603 break;
5604 }
5605 case OP_TLS_SET: {
5606 code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5607 break;
5608 }
5609 case OP_MEMORY_BARRIER: {
5610 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5611 x86_mfence (code);
5612 break;
5613 }
5614 case OP_ATOMIC_ADD_I4:
5615 case OP_ATOMIC_ADD_I8: {
5616 int dreg = ins->dreg;
5617 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5618
5619 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5620 dreg = AMD64_R11;
5621
5622 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5623 amd64_prefix (code, X86_LOCK_PREFIX);
5624 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5625 /* dreg contains the old value, add with sreg2 value */
5626 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5627
5628 if (ins->dreg != dreg)
5629 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5630
5631 break;
5632 }
5633 case OP_ATOMIC_EXCHANGE_I4:
5634 case OP_ATOMIC_EXCHANGE_I8: {
5635 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5636
5637 /* LOCK prefix is implied. */
5638 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5639 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5640 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5641 break;
5642 }
5643 case OP_ATOMIC_CAS_I4:
5644 case OP_ATOMIC_CAS_I8: {
5645 guint32 size;
5646
5647 if (ins->opcode == OP_ATOMIC_CAS_I8)
5648 size = 8;
5649 else
5650 size = 4;
5651
5652 /*
5653 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5654 * an explanation of how this works.
5655 */
5656 g_assert (ins->sreg3 == AMD64_RAX);
5657 g_assert (ins->sreg1 != AMD64_RAX);
5658 g_assert (ins->sreg1 != ins->sreg2);
5659
5660 amd64_prefix (code, X86_LOCK_PREFIX);
5661 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5662
5663 if (ins->dreg != AMD64_RAX)
5664 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5665 break;
5666 }
5667 case OP_ATOMIC_LOAD_I1: {
5668 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5669 break;
5670 }
5671 case OP_ATOMIC_LOAD_U1: {
5672 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5673 break;
5674 }
5675 case OP_ATOMIC_LOAD_I2: {
5676 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5677 break;
5678 }
5679 case OP_ATOMIC_LOAD_U2: {
5680 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5681 break;
5682 }
5683 case OP_ATOMIC_LOAD_I4: {
5684 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5685 break;
5686 }
5687 case OP_ATOMIC_LOAD_U4:
5688 case OP_ATOMIC_LOAD_I8:
5689 case OP_ATOMIC_LOAD_U8: {
5690 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5691 break;
5692 }
5693 case OP_ATOMIC_LOAD_R4: {
5694 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5695 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5696 break;
5697 }
5698 case OP_ATOMIC_LOAD_R8: {
5699 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5700 break;
5701 }
5702 case OP_ATOMIC_STORE_I1:
5703 case OP_ATOMIC_STORE_U1:
5704 case OP_ATOMIC_STORE_I2:
5705 case OP_ATOMIC_STORE_U2:
5706 case OP_ATOMIC_STORE_I4:
5707 case OP_ATOMIC_STORE_U4:
5708 case OP_ATOMIC_STORE_I8:
5709 case OP_ATOMIC_STORE_U8: {
5710 int size;
5711
5712 switch (ins->opcode) {
5713 case OP_ATOMIC_STORE_I1:
5714 case OP_ATOMIC_STORE_U1:
5715 size = 1;
5716 break;
5717 case OP_ATOMIC_STORE_I2:
5718 case OP_ATOMIC_STORE_U2:
5719 size = 2;
5720 break;
5721 case OP_ATOMIC_STORE_I4:
5722 case OP_ATOMIC_STORE_U4:
5723 size = 4;
5724 break;
5725 case OP_ATOMIC_STORE_I8:
5726 case OP_ATOMIC_STORE_U8:
5727 size = 8;
5728 break;
5729 }
5730
5731 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5732
5733 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5734 x86_mfence (code);
5735 break;
5736 }
5737 case OP_ATOMIC_STORE_R4: {
5738 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5739 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5740
5741 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5742 x86_mfence (code);
5743 break;
5744 }
5745 case OP_ATOMIC_STORE_R8: {
5746 x86_nop (code);
5747 x86_nop (code);
5748 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5749 x86_nop (code);
5750 x86_nop (code);
5751
5752 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5753 x86_mfence (code);
5754 break;
5755 }
5756 case OP_CARD_TABLE_WBARRIER: {
5757 int ptr = ins->sreg1;
5758 int value = ins->sreg2;
5759 guchar *br = 0;
5760 int nursery_shift, card_table_shift;
5761 gpointer card_table_mask;
5762 size_t nursery_size;
5763
5764 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5765 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5766 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5767
5768 /*If either point to the stack we can simply avoid the WB. This happens due to
5769 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5770 */
5771 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5772 continue;
5773
5774 /*
5775 * We need one register we can clobber, we choose EDX and make sreg1
5776 * fixed EAX to work around limitations in the local register allocator.
5777 * sreg2 might get allocated to EDX, but that is not a problem since
5778 * we use it before clobbering EDX.
5779 */
5780 g_assert (ins->sreg1 == AMD64_RAX);
5781
5782 /*
5783 * This is the code we produce:
5784 *
5785 * edx = value
5786 * edx >>= nursery_shift
5787 * cmp edx, (nursery_start >> nursery_shift)
5788 * jne done
5789 * edx = ptr
5790 * edx >>= card_table_shift
5791 * edx += cardtable
5792 * [edx] = 1
5793 * done:
5794 */
5795
5796 if (mono_gc_card_table_nursery_check ()) {
5797 if (value != AMD64_RDX)
5798 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5799 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5800 if (shifted_nursery_start >> 31) {
5801 /*
5802 * The value we need to compare against is 64 bits, so we need
5803 * another spare register. We use RBX, which we save and
5804 * restore.
5805 */
5806 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5807 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5808 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5809 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5810 } else {
5811 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5812 }
5813 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5814 }
5815 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5816 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5817 if (card_table_mask)
5818 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5819
5820 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5821 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5822
5823 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5824
5825 if (mono_gc_card_table_nursery_check ())
5826 x86_patch (br, code);
5827 break;
5828 }
5829 #ifdef MONO_ARCH_SIMD_INTRINSICS
5830 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5831 case OP_ADDPS:
5832 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5833 break;
5834 case OP_DIVPS:
5835 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5836 break;
5837 case OP_MULPS:
5838 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5839 break;
5840 case OP_SUBPS:
5841 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5842 break;
5843 case OP_MAXPS:
5844 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5845 break;
5846 case OP_MINPS:
5847 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5848 break;
5849 case OP_COMPPS:
5850 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5851 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5852 break;
5853 case OP_ANDPS:
5854 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5855 break;
5856 case OP_ANDNPS:
5857 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5858 break;
5859 case OP_ORPS:
5860 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5861 break;
5862 case OP_XORPS:
5863 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5864 break;
5865 case OP_SQRTPS:
5866 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5867 break;
5868 case OP_RSQRTPS:
5869 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5870 break;
5871 case OP_RCPPS:
5872 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5873 break;
5874 case OP_ADDSUBPS:
5875 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5876 break;
5877 case OP_HADDPS:
5878 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5879 break;
5880 case OP_HSUBPS:
5881 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5882 break;
5883 case OP_DUPPS_HIGH:
5884 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5885 break;
5886 case OP_DUPPS_LOW:
5887 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5888 break;
5889
5890 case OP_PSHUFLEW_HIGH:
5891 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5892 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5893 break;
5894 case OP_PSHUFLEW_LOW:
5895 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5896 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5897 break;
5898 case OP_PSHUFLED:
5899 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5900 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5901 break;
5902 case OP_SHUFPS:
5903 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5904 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5905 break;
5906 case OP_SHUFPD:
5907 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5908 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5909 break;
5910
5911 case OP_ADDPD:
5912 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5913 break;
5914 case OP_DIVPD:
5915 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5916 break;
5917 case OP_MULPD:
5918 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5919 break;
5920 case OP_SUBPD:
5921 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5922 break;
5923 case OP_MAXPD:
5924 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5925 break;
5926 case OP_MINPD:
5927 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5928 break;
5929 case OP_COMPPD:
5930 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5931 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5932 break;
5933 case OP_ANDPD:
5934 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5935 break;
5936 case OP_ANDNPD:
5937 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5938 break;
5939 case OP_ORPD:
5940 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5941 break;
5942 case OP_XORPD:
5943 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5944 break;
5945 case OP_SQRTPD:
5946 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5947 break;
5948 case OP_ADDSUBPD:
5949 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5950 break;
5951 case OP_HADDPD:
5952 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5953 break;
5954 case OP_HSUBPD:
5955 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5956 break;
5957 case OP_DUPPD:
5958 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5959 break;
5960
5961 case OP_EXTRACT_MASK:
5962 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5963 break;
5964
5965 case OP_PAND:
5966 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5967 break;
5968 case OP_POR:
5969 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5970 break;
5971 case OP_PXOR:
5972 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5973 break;
5974
5975 case OP_PADDB:
5976 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5977 break;
5978 case OP_PADDW:
5979 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5980 break;
5981 case OP_PADDD:
5982 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5983 break;
5984 case OP_PADDQ:
5985 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5986 break;
5987
5988 case OP_PSUBB:
5989 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5990 break;
5991 case OP_PSUBW:
5992 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5993 break;
5994 case OP_PSUBD:
5995 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5996 break;
5997 case OP_PSUBQ:
5998 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5999 break;
6000
6001 case OP_PMAXB_UN:
6002 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6003 break;
6004 case OP_PMAXW_UN:
6005 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6006 break;
6007 case OP_PMAXD_UN:
6008 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6009 break;
6010
6011 case OP_PMAXB:
6012 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6013 break;
6014 case OP_PMAXW:
6015 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6016 break;
6017 case OP_PMAXD:
6018 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6019 break;
6020
6021 case OP_PAVGB_UN:
6022 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6023 break;
6024 case OP_PAVGW_UN:
6025 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6026 break;
6027
6028 case OP_PMINB_UN:
6029 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6030 break;
6031 case OP_PMINW_UN:
6032 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6033 break;
6034 case OP_PMIND_UN:
6035 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6036 break;
6037
6038 case OP_PMINB:
6039 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6040 break;
6041 case OP_PMINW:
6042 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6043 break;
6044 case OP_PMIND:
6045 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6046 break;
6047
6048 case OP_PCMPEQB:
6049 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6050 break;
6051 case OP_PCMPEQW:
6052 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6053 break;
6054 case OP_PCMPEQD:
6055 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6056 break;
6057 case OP_PCMPEQQ:
6058 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6059 break;
6060
6061 case OP_PCMPGTB:
6062 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6063 break;
6064 case OP_PCMPGTW:
6065 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6066 break;
6067 case OP_PCMPGTD:
6068 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6069 break;
6070 case OP_PCMPGTQ:
6071 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6072 break;
6073
6074 case OP_PSUM_ABS_DIFF:
6075 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6076 break;
6077
6078 case OP_UNPACK_LOWB:
6079 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6080 break;
6081 case OP_UNPACK_LOWW:
6082 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6083 break;
6084 case OP_UNPACK_LOWD:
6085 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6086 break;
6087 case OP_UNPACK_LOWQ:
6088 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6089 break;
6090 case OP_UNPACK_LOWPS:
6091 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6092 break;
6093 case OP_UNPACK_LOWPD:
6094 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6095 break;
6096
6097 case OP_UNPACK_HIGHB:
6098 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6099 break;
6100 case OP_UNPACK_HIGHW:
6101 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6102 break;
6103 case OP_UNPACK_HIGHD:
6104 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6105 break;
6106 case OP_UNPACK_HIGHQ:
6107 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6108 break;
6109 case OP_UNPACK_HIGHPS:
6110 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6111 break;
6112 case OP_UNPACK_HIGHPD:
6113 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6114 break;
6115
6116 case OP_PACKW:
6117 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6118 break;
6119 case OP_PACKD:
6120 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6121 break;
6122 case OP_PACKW_UN:
6123 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6124 break;
6125 case OP_PACKD_UN:
6126 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6127 break;
6128
6129 case OP_PADDB_SAT_UN:
6130 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6131 break;
6132 case OP_PSUBB_SAT_UN:
6133 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6134 break;
6135 case OP_PADDW_SAT_UN:
6136 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6137 break;
6138 case OP_PSUBW_SAT_UN:
6139 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6140 break;
6141
6142 case OP_PADDB_SAT:
6143 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6144 break;
6145 case OP_PSUBB_SAT:
6146 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6147 break;
6148 case OP_PADDW_SAT:
6149 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6150 break;
6151 case OP_PSUBW_SAT:
6152 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6153 break;
6154
6155 case OP_PMULW:
6156 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6157 break;
6158 case OP_PMULD:
6159 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6160 break;
6161 case OP_PMULQ:
6162 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6163 break;
6164 case OP_PMULW_HIGH_UN:
6165 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6166 break;
6167 case OP_PMULW_HIGH:
6168 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6169 break;
6170
6171 case OP_PSHRW:
6172 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6173 break;
6174 case OP_PSHRW_REG:
6175 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6176 break;
6177
6178 case OP_PSARW:
6179 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6180 break;
6181 case OP_PSARW_REG:
6182 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6183 break;
6184
6185 case OP_PSHLW:
6186 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6187 break;
6188 case OP_PSHLW_REG:
6189 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6190 break;
6191
6192 case OP_PSHRD:
6193 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6194 break;
6195 case OP_PSHRD_REG:
6196 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6197 break;
6198
6199 case OP_PSARD:
6200 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6201 break;
6202 case OP_PSARD_REG:
6203 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6204 break;
6205
6206 case OP_PSHLD:
6207 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6208 break;
6209 case OP_PSHLD_REG:
6210 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6211 break;
6212
6213 case OP_PSHRQ:
6214 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6215 break;
6216 case OP_PSHRQ_REG:
6217 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6218 break;
6219
6220 /*TODO: This is appart of the sse spec but not added
6221 case OP_PSARQ:
6222 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6223 break;
6224 case OP_PSARQ_REG:
6225 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6226 break;
6227 */
6228
6229 case OP_PSHLQ:
6230 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6231 break;
6232 case OP_PSHLQ_REG:
6233 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6234 break;
6235 case OP_CVTDQ2PD:
6236 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6237 break;
6238 case OP_CVTDQ2PS:
6239 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6240 break;
6241 case OP_CVTPD2DQ:
6242 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6243 break;
6244 case OP_CVTPD2PS:
6245 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6246 break;
6247 case OP_CVTPS2DQ:
6248 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6249 break;
6250 case OP_CVTPS2PD:
6251 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6252 break;
6253 case OP_CVTTPD2DQ:
6254 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6255 break;
6256 case OP_CVTTPS2DQ:
6257 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6258 break;
6259
6260 case OP_ICONV_TO_X:
6261 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6262 break;
6263 case OP_EXTRACT_I4:
6264 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6265 break;
6266 case OP_EXTRACT_I8:
6267 if (ins->inst_c0) {
6268 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6269 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6270 } else {
6271 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6272 }
6273 break;
6274 case OP_EXTRACT_I1:
6275 case OP_EXTRACT_U1:
6276 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6277 if (ins->inst_c0)
6278 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6279 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6280 break;
6281 case OP_EXTRACT_I2:
6282 case OP_EXTRACT_U2:
6283 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6284 if (ins->inst_c0)
6285 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6286 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6287 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6288 break;
6289 case OP_EXTRACT_R8:
6290 if (ins->inst_c0)
6291 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6292 else
6293 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6294 break;
6295 case OP_INSERT_I2:
6296 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6297 break;
6298 case OP_EXTRACTX_U2:
6299 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6300 break;
6301 case OP_INSERTX_U1_SLOW:
6302 /*sreg1 is the extracted ireg (scratch)
6303 /sreg2 is the to be inserted ireg (scratch)
6304 /dreg is the xreg to receive the value*/
6305
6306 /*clear the bits from the extracted word*/
6307 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6308 /*shift the value to insert if needed*/
6309 if (ins->inst_c0 & 1)
6310 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6311 /*join them together*/
6312 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6313 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6314 break;
6315 case OP_INSERTX_I4_SLOW:
6316 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6317 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6318 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6319 break;
6320 case OP_INSERTX_I8_SLOW:
6321 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6322 if (ins->inst_c0)
6323 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6324 else
6325 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6326 break;
6327
6328 case OP_INSERTX_R4_SLOW:
6329 switch (ins->inst_c0) {
6330 case 0:
6331 if (cfg->r4fp)
6332 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6333 else
6334 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6335 break;
6336 case 1:
6337 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6338 if (cfg->r4fp)
6339 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6340 else
6341 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6342 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6343 break;
6344 case 2:
6345 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6346 if (cfg->r4fp)
6347 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6348 else
6349 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6350 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6351 break;
6352 case 3:
6353 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6354 if (cfg->r4fp)
6355 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6356 else
6357 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6358 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6359 break;
6360 }
6361 break;
6362 case OP_INSERTX_R8_SLOW:
6363 if (ins->inst_c0)
6364 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6365 else
6366 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6367 break;
6368 case OP_STOREX_MEMBASE_REG:
6369 case OP_STOREX_MEMBASE:
6370 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6371 break;
6372 case OP_LOADX_MEMBASE:
6373 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6374 break;
6375 case OP_LOADX_ALIGNED_MEMBASE:
6376 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6377 break;
6378 case OP_STOREX_ALIGNED_MEMBASE_REG:
6379 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6380 break;
6381 case OP_STOREX_NTA_MEMBASE_REG:
6382 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6383 break;
6384 case OP_PREFETCH_MEMBASE:
6385 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6386 break;
6387
6388 case OP_XMOVE:
6389 /*FIXME the peephole pass should have killed this*/
6390 if (ins->dreg != ins->sreg1)
6391 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6392 break;
6393 case OP_XZERO:
6394 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6395 break;
6396 case OP_XONES:
6397 amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6398 break;
6399 case OP_ICONV_TO_R4_RAW:
6400 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6401 if (!cfg->r4fp)
6402 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6403 break;
6404
6405 case OP_FCONV_TO_R8_X:
6406 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6407 break;
6408
6409 case OP_XCONV_R8_TO_I4:
6410 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6411 switch (ins->backend.source_opcode) {
6412 case OP_FCONV_TO_I1:
6413 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6414 break;
6415 case OP_FCONV_TO_U1:
6416 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6417 break;
6418 case OP_FCONV_TO_I2:
6419 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6420 break;
6421 case OP_FCONV_TO_U2:
6422 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6423 break;
6424 }
6425 break;
6426
6427 case OP_EXPAND_I2:
6428 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6429 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6430 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6431 break;
6432 case OP_EXPAND_I4:
6433 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6434 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6435 break;
6436 case OP_EXPAND_I8:
6437 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6438 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6439 break;
6440 case OP_EXPAND_R4:
6441 if (cfg->r4fp) {
6442 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6443 } else {
6444 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6445 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6446 }
6447 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6448 break;
6449 case OP_EXPAND_R8:
6450 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6451 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6452 break;
6453 #endif
6454 case OP_LIVERANGE_START: {
6455 if (cfg->verbose_level > 1)
6456 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6457 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6458 break;
6459 }
6460 case OP_LIVERANGE_END: {
6461 if (cfg->verbose_level > 1)
6462 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6463 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6464 break;
6465 }
6466 case OP_GC_SAFE_POINT: {
6467 guint8 *br [1];
6468
6469 g_assert (mono_threads_is_coop_enabled ());
6470
6471 amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6472 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6473 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6474 amd64_patch (br[0], code);
6475 break;
6476 }
6477
6478 case OP_GC_LIVENESS_DEF:
6479 case OP_GC_LIVENESS_USE:
6480 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6481 ins->backend.pc_offset = code - cfg->native_code;
6482 break;
6483 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6484 ins->backend.pc_offset = code - cfg->native_code;
6485 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6486 break;
6487 case OP_GET_LAST_ERROR:
6488 emit_get_last_error(code, ins->dreg);
6489 break;
6490 case OP_FILL_PROF_CALL_CTX:
6491 for (int i = 0; i < AMD64_NREG; i++)
6492 if (AMD64_IS_CALLEE_SAVED_REG (i) || i == AMD64_RSP)
6493 amd64_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, gregs) + i * sizeof (mgreg_t), i, sizeof (mgreg_t));
6494 break;
6495 default:
6496 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6497 g_assert_not_reached ();
6498 }
6499
6500 if ((code - cfg->native_code - offset) > max_len) {
6501 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6502 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6503 g_assert_not_reached ();
6504 }
6505 }
6506
6507 cfg->code_len = code - cfg->native_code;
6508 }
6509
6510 #endif /* DISABLE_JIT */
6511
6512 void
mono_arch_register_lowlevel_calls(void)6513 mono_arch_register_lowlevel_calls (void)
6514 {
6515 /* The signature doesn't matter */
6516 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6517
6518 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6519 #if _MSC_VER
6520 extern void __chkstk (void);
6521 mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, "__chkstk");
6522 #else
6523 extern void ___chkstk_ms (void);
6524 mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, "___chkstk_ms");
6525 #endif
6526 #endif
6527 }
6528
6529 void
mono_arch_patch_code_new(MonoCompile * cfg,MonoDomain * domain,guint8 * code,MonoJumpInfo * ji,gpointer target)6530 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6531 {
6532 unsigned char *ip = ji->ip.i + code;
6533
6534 /*
6535 * Debug code to help track down problems where the target of a near call is
6536 * is not valid.
6537 */
6538 if (amd64_is_near_call (ip)) {
6539 gint64 disp = (guint8*)target - (guint8*)ip;
6540
6541 if (!amd64_is_imm32 (disp)) {
6542 printf ("TYPE: %d\n", ji->type);
6543 switch (ji->type) {
6544 case MONO_PATCH_INFO_INTERNAL_METHOD:
6545 printf ("V: %s\n", ji->data.name);
6546 break;
6547 case MONO_PATCH_INFO_METHOD_JUMP:
6548 case MONO_PATCH_INFO_METHOD:
6549 printf ("V: %s\n", ji->data.method->name);
6550 break;
6551 default:
6552 break;
6553 }
6554 }
6555 }
6556
6557 amd64_patch (ip, (gpointer)target);
6558 }
6559
6560 #ifndef DISABLE_JIT
6561
6562 static int
get_max_epilog_size(MonoCompile * cfg)6563 get_max_epilog_size (MonoCompile *cfg)
6564 {
6565 int max_epilog_size = 16;
6566
6567 if (cfg->method->save_lmf)
6568 max_epilog_size += 256;
6569
6570 if (mono_jit_trace_calls != NULL)
6571 max_epilog_size += 50;
6572
6573 max_epilog_size += (AMD64_NREG * 2);
6574
6575 return max_epilog_size;
6576 }
6577
6578 /*
6579 * This macro is used for testing whenever the unwinder works correctly at every point
6580 * where an async exception can happen.
6581 */
6582 /* This will generate a SIGSEGV at the given point in the code */
6583 #define async_exc_point(code) do { \
6584 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6585 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6586 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6587 cfg->arch.async_point_count ++; \
6588 } \
6589 } while (0)
6590
6591 #ifdef TARGET_WIN32
6592 static guint8 *
emit_prolog_setup_sp_win64(MonoCompile * cfg,guint8 * code,int alloc_size,int * cfa_offset_input)6593 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6594 {
6595 int cfa_offset = *cfa_offset_input;
6596
6597 /* Allocate windows stack frame using stack probing method */
6598 if (alloc_size) {
6599
6600 if (alloc_size >= 0x1000) {
6601 amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6602 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6603 }
6604
6605 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6606 if (cfg->arch.omit_fp) {
6607 cfa_offset += alloc_size;
6608 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6609 async_exc_point (code);
6610 }
6611
6612 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6613 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6614 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6615 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6616 // that will retrieve the expected results.
6617 if (cfg->arch.omit_fp)
6618 mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6619 }
6620
6621 *cfa_offset_input = cfa_offset;
6622 return code;
6623 }
6624 #endif /* TARGET_WIN32 */
6625
6626 guint8 *
mono_arch_emit_prolog(MonoCompile * cfg)6627 mono_arch_emit_prolog (MonoCompile *cfg)
6628 {
6629 MonoMethod *method = cfg->method;
6630 MonoBasicBlock *bb;
6631 MonoMethodSignature *sig;
6632 MonoInst *ins;
6633 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6634 guint8 *code;
6635 CallInfo *cinfo;
6636 MonoInst *lmf_var = cfg->lmf_var;
6637 gboolean args_clobbered = FALSE;
6638 gboolean trace = FALSE;
6639
6640 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6641
6642 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6643
6644 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6645 trace = TRUE;
6646
6647 /* Amount of stack space allocated by register saving code */
6648 pos = 0;
6649
6650 /* Offset between RSP and the CFA */
6651 cfa_offset = 0;
6652
6653 /*
6654 * The prolog consists of the following parts:
6655 * FP present:
6656 * - push rbp
6657 * - mov rbp, rsp
6658 * - save callee saved regs using moves
6659 * - allocate frame
6660 * - save rgctx if needed
6661 * - save lmf if needed
6662 * FP not present:
6663 * - allocate frame
6664 * - save rgctx if needed
6665 * - save lmf if needed
6666 * - save callee saved regs using moves
6667 */
6668
6669 // CFA = sp + 8
6670 cfa_offset = 8;
6671 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6672 // IP saved at CFA - 8
6673 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6674 async_exc_point (code);
6675 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6676
6677 if (!cfg->arch.omit_fp) {
6678 amd64_push_reg (code, AMD64_RBP);
6679 cfa_offset += 8;
6680 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6681 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6682 async_exc_point (code);
6683 /* These are handled automatically by the stack marking code */
6684 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6685
6686 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6687 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6688 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6689 async_exc_point (code);
6690 }
6691
6692 /* The param area is always at offset 0 from sp */
6693 /* This needs to be allocated here, since it has to come after the spill area */
6694 if (cfg->param_area) {
6695 if (cfg->arch.omit_fp)
6696 // FIXME:
6697 g_assert_not_reached ();
6698 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6699 }
6700
6701 if (cfg->arch.omit_fp) {
6702 /*
6703 * On enter, the stack is misaligned by the pushing of the return
6704 * address. It is either made aligned by the pushing of %rbp, or by
6705 * this.
6706 */
6707 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6708 if ((alloc_size % 16) == 0) {
6709 alloc_size += 8;
6710 /* Mark the padding slot as NOREF */
6711 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6712 }
6713 } else {
6714 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6715 if (cfg->stack_offset != alloc_size) {
6716 /* Mark the padding slot as NOREF */
6717 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6718 }
6719 cfg->arch.sp_fp_offset = alloc_size;
6720 alloc_size -= pos;
6721 }
6722
6723 cfg->arch.stack_alloc_size = alloc_size;
6724
6725 /* Allocate stack frame */
6726 #ifdef TARGET_WIN32
6727 code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6728 #else
6729 if (alloc_size) {
6730 /* See mono_emit_stack_alloc */
6731 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6732 guint32 remaining_size = alloc_size;
6733
6734 /* Use a loop for large sizes */
6735 if (remaining_size > 10 * 0x1000) {
6736 amd64_mov_reg_imm (code, X86_EAX, remaining_size / 0x1000);
6737 guint8 *label = code;
6738 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6739 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6740 amd64_alu_reg_imm (code, X86_SUB, AMD64_RAX, 1);
6741 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6742 guint8 *label2 = code;
6743 x86_branch8 (code, X86_CC_NE, 0, FALSE);
6744 amd64_patch (label2, label);
6745 if (cfg->arch.omit_fp) {
6746 cfa_offset += (remaining_size / 0x1000) * 0x1000;
6747 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6748 }
6749
6750 remaining_size = remaining_size % 0x1000;
6751 }
6752
6753 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6754 guint32 offset = code - cfg->native_code;
6755 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6756 while (required_code_size >= (cfg->code_size - offset))
6757 cfg->code_size *= 2;
6758 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6759 code = cfg->native_code + offset;
6760 cfg->stat_code_reallocs++;
6761 }
6762
6763 while (remaining_size >= 0x1000) {
6764 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6765 if (cfg->arch.omit_fp) {
6766 cfa_offset += 0x1000;
6767 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6768 }
6769 async_exc_point (code);
6770
6771 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6772 remaining_size -= 0x1000;
6773 }
6774 if (remaining_size) {
6775 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6776 if (cfg->arch.omit_fp) {
6777 cfa_offset += remaining_size;
6778 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6779 async_exc_point (code);
6780 }
6781 }
6782 #else
6783 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6784 if (cfg->arch.omit_fp) {
6785 cfa_offset += alloc_size;
6786 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6787 async_exc_point (code);
6788 }
6789 #endif
6790 }
6791 #endif
6792
6793 /* Stack alignment check */
6794 #if 0
6795 {
6796 guint8 *buf;
6797
6798 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6799 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6800 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6801 buf = code;
6802 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6803 amd64_breakpoint (code);
6804 amd64_patch (buf, code);
6805 }
6806 #endif
6807
6808 if (mini_get_debug_options ()->init_stacks) {
6809 /* Fill the stack frame with a dummy value to force deterministic behavior */
6810
6811 /* Save registers to the red zone */
6812 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6813 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6814
6815 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6816 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6817 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6818
6819 amd64_cld (code);
6820 amd64_prefix (code, X86_REP_PREFIX);
6821 amd64_stosl (code);
6822
6823 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6824 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6825 }
6826
6827 /* Save LMF */
6828 if (method->save_lmf)
6829 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6830
6831 /* Save callee saved registers */
6832 if (cfg->arch.omit_fp) {
6833 save_area_offset = cfg->arch.reg_save_area_offset;
6834 /* Save caller saved registers after sp is adjusted */
6835 /* The registers are saved at the bottom of the frame */
6836 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6837 } else {
6838 /* The registers are saved just below the saved rbp */
6839 save_area_offset = cfg->arch.reg_save_area_offset;
6840 }
6841
6842 for (i = 0; i < AMD64_NREG; ++i) {
6843 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6844 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6845
6846 if (cfg->arch.omit_fp) {
6847 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6848 /* These are handled automatically by the stack marking code */
6849 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6850 } else {
6851 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6852 // FIXME: GC
6853 }
6854
6855 save_area_offset += 8;
6856 async_exc_point (code);
6857 }
6858 }
6859
6860 /* store runtime generic context */
6861 if (cfg->rgctx_var) {
6862 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6863 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6864
6865 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6866
6867 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6868 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6869 }
6870
6871 /* compute max_length in order to use short forward jumps */
6872 max_epilog_size = get_max_epilog_size (cfg);
6873 if (cfg->opt & MONO_OPT_BRANCH) {
6874 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6875 MonoInst *ins;
6876 int max_length = 0;
6877
6878 /* max alignment for loops */
6879 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6880 max_length += LOOP_ALIGNMENT;
6881
6882 MONO_BB_FOR_EACH_INS (bb, ins) {
6883 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6884 }
6885
6886 /* Take prolog and epilog instrumentation into account */
6887 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6888 max_length += max_epilog_size;
6889
6890 bb->max_length = max_length;
6891 }
6892 }
6893
6894 sig = mono_method_signature (method);
6895 pos = 0;
6896
6897 cinfo = (CallInfo *)cfg->arch.cinfo;
6898
6899 if (sig->ret->type != MONO_TYPE_VOID) {
6900 /* Save volatile arguments to the stack */
6901 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6902 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6903 }
6904
6905 /* Keep this in sync with emit_load_volatile_arguments */
6906 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6907 ArgInfo *ainfo = cinfo->args + i;
6908
6909 ins = cfg->args [i];
6910
6911 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6912 /* Unused arguments */
6913 continue;
6914
6915 /* Save volatile arguments to the stack */
6916 if (ins->opcode != OP_REGVAR) {
6917 switch (ainfo->storage) {
6918 case ArgInIReg: {
6919 guint32 size = 8;
6920
6921 /* FIXME: I1 etc */
6922 /*
6923 if (stack_offset & 0x1)
6924 size = 1;
6925 else if (stack_offset & 0x2)
6926 size = 2;
6927 else if (stack_offset & 0x4)
6928 size = 4;
6929 else
6930 size = 8;
6931 */
6932 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6933
6934 /*
6935 * Save the original location of 'this',
6936 * get_generic_info_from_stack_frame () needs this to properly look up
6937 * the argument value during the handling of async exceptions.
6938 */
6939 if (ins == cfg->args [0]) {
6940 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6941 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6942 }
6943 break;
6944 }
6945 case ArgInFloatSSEReg:
6946 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6947 break;
6948 case ArgInDoubleSSEReg:
6949 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6950 break;
6951 case ArgValuetypeInReg:
6952 for (quad = 0; quad < 2; quad ++) {
6953 switch (ainfo->pair_storage [quad]) {
6954 case ArgInIReg:
6955 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6956 break;
6957 case ArgInFloatSSEReg:
6958 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6959 break;
6960 case ArgInDoubleSSEReg:
6961 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6962 break;
6963 case ArgNone:
6964 break;
6965 default:
6966 g_assert_not_reached ();
6967 }
6968 }
6969 break;
6970 case ArgValuetypeAddrInIReg:
6971 if (ainfo->pair_storage [0] == ArgInIReg)
6972 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6973 break;
6974 case ArgValuetypeAddrOnStack:
6975 break;
6976 case ArgGSharedVtInReg:
6977 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6978 break;
6979 default:
6980 break;
6981 }
6982 } else {
6983 /* Argument allocated to (non-volatile) register */
6984 switch (ainfo->storage) {
6985 case ArgInIReg:
6986 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6987 break;
6988 case ArgOnStack:
6989 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6990 break;
6991 default:
6992 g_assert_not_reached ();
6993 }
6994
6995 if (ins == cfg->args [0]) {
6996 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6997 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6998 }
6999 }
7000 }
7001
7002 if (cfg->method->save_lmf)
7003 args_clobbered = TRUE;
7004
7005 if (trace) {
7006 args_clobbered = TRUE;
7007 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7008 }
7009
7010 /*
7011 * Optimize the common case of the first bblock making a call with the same
7012 * arguments as the method. This works because the arguments are still in their
7013 * original argument registers.
7014 * FIXME: Generalize this
7015 */
7016 if (!args_clobbered) {
7017 MonoBasicBlock *first_bb = cfg->bb_entry;
7018 MonoInst *next;
7019 int filter = FILTER_IL_SEQ_POINT;
7020
7021 next = mono_bb_first_inst (first_bb, filter);
7022 if (!next && first_bb->next_bb) {
7023 first_bb = first_bb->next_bb;
7024 next = mono_bb_first_inst (first_bb, filter);
7025 }
7026
7027 if (first_bb->in_count > 1)
7028 next = NULL;
7029
7030 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7031 ArgInfo *ainfo = cinfo->args + i;
7032 gboolean match = FALSE;
7033
7034 ins = cfg->args [i];
7035 if (ins->opcode != OP_REGVAR) {
7036 switch (ainfo->storage) {
7037 case ArgInIReg: {
7038 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7039 if (next->dreg == ainfo->reg) {
7040 NULLIFY_INS (next);
7041 match = TRUE;
7042 } else {
7043 next->opcode = OP_MOVE;
7044 next->sreg1 = ainfo->reg;
7045 /* Only continue if the instruction doesn't change argument regs */
7046 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7047 match = TRUE;
7048 }
7049 }
7050 break;
7051 }
7052 default:
7053 break;
7054 }
7055 } else {
7056 /* Argument allocated to (non-volatile) register */
7057 switch (ainfo->storage) {
7058 case ArgInIReg:
7059 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7060 NULLIFY_INS (next);
7061 match = TRUE;
7062 }
7063 break;
7064 default:
7065 break;
7066 }
7067 }
7068
7069 if (match) {
7070 next = mono_inst_next (next, filter);
7071 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7072 if (!next)
7073 break;
7074 }
7075 }
7076 }
7077
7078 if (cfg->gen_sdb_seq_points) {
7079 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7080
7081 /* Initialize seq_point_info_var */
7082 if (cfg->compile_aot) {
7083 /* Initialize the variable from a GOT slot */
7084 /* Same as OP_AOTCONST */
7085 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7086 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7087 g_assert (info_var->opcode == OP_REGOFFSET);
7088 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7089 }
7090
7091 if (cfg->compile_aot) {
7092 /* Initialize ss_tramp_var */
7093 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7094 g_assert (ins->opcode == OP_REGOFFSET);
7095
7096 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7097 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7098 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7099 } else {
7100 /* Initialize ss_tramp_var */
7101 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7102 g_assert (ins->opcode == OP_REGOFFSET);
7103
7104 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7105 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7106
7107 /* Initialize bp_tramp_var */
7108 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7109 g_assert (ins->opcode == OP_REGOFFSET);
7110
7111 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7112 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7113 }
7114 }
7115
7116 cfg->code_len = code - cfg->native_code;
7117
7118 g_assert (cfg->code_len < cfg->code_size);
7119
7120 return code;
7121 }
7122
7123 void
mono_arch_emit_epilog(MonoCompile * cfg)7124 mono_arch_emit_epilog (MonoCompile *cfg)
7125 {
7126 MonoMethod *method = cfg->method;
7127 int quad, i;
7128 guint8 *code;
7129 int max_epilog_size;
7130 CallInfo *cinfo;
7131 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7132 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7133
7134 max_epilog_size = get_max_epilog_size (cfg);
7135
7136 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7137 cfg->code_size *= 2;
7138 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7139 cfg->stat_code_reallocs++;
7140 }
7141 code = cfg->native_code + cfg->code_len;
7142
7143 cfg->has_unwind_info_for_epilog = TRUE;
7144
7145 /* Mark the start of the epilog */
7146 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7147
7148 /* Save the uwind state which is needed by the out-of-line code */
7149 mono_emit_unwind_op_remember_state (cfg, code);
7150
7151 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7152 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7153
7154 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7155
7156 if (method->save_lmf) {
7157 /* check if we need to restore protection of the stack after a stack overflow */
7158 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7159 guint8 *patch;
7160 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7161 /* we load the value in a separate instruction: this mechanism may be
7162 * used later as a safer way to do thread interruption
7163 */
7164 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7165 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7166 patch = code;
7167 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7168 /* note that the call trampoline will preserve eax/edx */
7169 x86_call_reg (code, X86_ECX);
7170 x86_patch (patch, code);
7171 } else {
7172 /* FIXME: maybe save the jit tls in the prolog */
7173 }
7174 if (cfg->used_int_regs & (1 << AMD64_RBP))
7175 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7176 if (cfg->arch.omit_fp)
7177 /*
7178 * emit_setup_lmf () marks RBP as saved, we have to mark it as same value here before clearing up the stack
7179 * since its stack slot will become invalid.
7180 */
7181 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7182 }
7183
7184 /* Restore callee saved regs */
7185 for (i = 0; i < AMD64_NREG; ++i) {
7186 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7187 /* Restore only used_int_regs, not arch.saved_iregs */
7188 #if defined(MONO_SUPPORT_TASKLETS)
7189 int restore_reg = 1;
7190 #else
7191 int restore_reg = (cfg->used_int_regs & (1 << i));
7192 #endif
7193 if (restore_reg) {
7194 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7195 mono_emit_unwind_op_same_value (cfg, code, i);
7196 async_exc_point (code);
7197 }
7198 save_area_offset += 8;
7199 }
7200 }
7201
7202 /* Load returned vtypes into registers if needed */
7203 cinfo = (CallInfo *)cfg->arch.cinfo;
7204 if (cinfo->ret.storage == ArgValuetypeInReg) {
7205 ArgInfo *ainfo = &cinfo->ret;
7206 MonoInst *inst = cfg->ret;
7207
7208 for (quad = 0; quad < 2; quad ++) {
7209 switch (ainfo->pair_storage [quad]) {
7210 case ArgInIReg:
7211 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7212 break;
7213 case ArgInFloatSSEReg:
7214 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7215 break;
7216 case ArgInDoubleSSEReg:
7217 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7218 break;
7219 case ArgNone:
7220 break;
7221 default:
7222 g_assert_not_reached ();
7223 }
7224 }
7225 }
7226
7227 if (cfg->arch.omit_fp) {
7228 if (cfg->arch.stack_alloc_size) {
7229 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7230 }
7231 } else {
7232 #ifdef TARGET_WIN32
7233 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7234 amd64_pop_reg (code, AMD64_RBP);
7235 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7236 #else
7237 amd64_leave (code);
7238 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7239 #endif
7240 }
7241 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7242 async_exc_point (code);
7243 amd64_ret (code);
7244
7245 /* Restore the unwind state to be the same as before the epilog */
7246 mono_emit_unwind_op_restore_state (cfg, code);
7247
7248 cfg->code_len = code - cfg->native_code;
7249
7250 g_assert (cfg->code_len < cfg->code_size);
7251 }
7252
7253 void
mono_arch_emit_exceptions(MonoCompile * cfg)7254 mono_arch_emit_exceptions (MonoCompile *cfg)
7255 {
7256 MonoJumpInfo *patch_info;
7257 int nthrows, i;
7258 guint8 *code;
7259 MonoClass *exc_classes [16];
7260 guint8 *exc_throw_start [16], *exc_throw_end [16];
7261 guint32 code_size = 0;
7262
7263 /* Compute needed space */
7264 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7265 if (patch_info->type == MONO_PATCH_INFO_EXC)
7266 code_size += 40;
7267 if (patch_info->type == MONO_PATCH_INFO_R8)
7268 code_size += 8 + 15; /* sizeof (double) + alignment */
7269 if (patch_info->type == MONO_PATCH_INFO_R4)
7270 code_size += 4 + 15; /* sizeof (float) + alignment */
7271 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7272 code_size += 8 + 7; /*sizeof (void*) + alignment */
7273 }
7274
7275 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7276 cfg->code_size *= 2;
7277 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7278 cfg->stat_code_reallocs++;
7279 }
7280
7281 code = cfg->native_code + cfg->code_len;
7282
7283 /* add code to raise exceptions */
7284 nthrows = 0;
7285 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7286 switch (patch_info->type) {
7287 case MONO_PATCH_INFO_EXC: {
7288 MonoClass *exc_class;
7289 guint8 *buf, *buf2;
7290 guint32 throw_ip;
7291
7292 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7293
7294 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7295 throw_ip = patch_info->ip.i;
7296
7297 //x86_breakpoint (code);
7298 /* Find a throw sequence for the same exception class */
7299 for (i = 0; i < nthrows; ++i)
7300 if (exc_classes [i] == exc_class)
7301 break;
7302 if (i < nthrows) {
7303 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7304 x86_jump_code (code, exc_throw_start [i]);
7305 patch_info->type = MONO_PATCH_INFO_NONE;
7306 }
7307 else {
7308 buf = code;
7309 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7310 buf2 = code;
7311
7312 if (nthrows < 16) {
7313 exc_classes [nthrows] = exc_class;
7314 exc_throw_start [nthrows] = code;
7315 }
7316 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7317
7318 patch_info->type = MONO_PATCH_INFO_NONE;
7319
7320 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7321
7322 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7323 while (buf < buf2)
7324 x86_nop (buf);
7325
7326 if (nthrows < 16) {
7327 exc_throw_end [nthrows] = code;
7328 nthrows ++;
7329 }
7330 }
7331 break;
7332 }
7333 default:
7334 /* do nothing */
7335 break;
7336 }
7337 g_assert(code < cfg->native_code + cfg->code_size);
7338 }
7339
7340 /* Handle relocations with RIP relative addressing */
7341 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7342 gboolean remove = FALSE;
7343 guint8 *orig_code = code;
7344
7345 switch (patch_info->type) {
7346 case MONO_PATCH_INFO_R8:
7347 case MONO_PATCH_INFO_R4: {
7348 guint8 *pos, *patch_pos;
7349 guint32 target_pos;
7350
7351 /* The SSE opcodes require a 16 byte alignment */
7352 code = (guint8*)ALIGN_TO (code, 16);
7353
7354 pos = cfg->native_code + patch_info->ip.i;
7355 if (IS_REX (pos [1])) {
7356 patch_pos = pos + 5;
7357 target_pos = code - pos - 9;
7358 }
7359 else {
7360 patch_pos = pos + 4;
7361 target_pos = code - pos - 8;
7362 }
7363
7364 if (patch_info->type == MONO_PATCH_INFO_R8) {
7365 *(double*)code = *(double*)patch_info->data.target;
7366 code += sizeof (double);
7367 } else {
7368 *(float*)code = *(float*)patch_info->data.target;
7369 code += sizeof (float);
7370 }
7371
7372 *(guint32*)(patch_pos) = target_pos;
7373
7374 remove = TRUE;
7375 break;
7376 }
7377 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7378 guint8 *pos;
7379
7380 if (cfg->compile_aot)
7381 continue;
7382
7383 /*loading is faster against aligned addresses.*/
7384 code = (guint8*)ALIGN_TO (code, 8);
7385 memset (orig_code, 0, code - orig_code);
7386
7387 pos = cfg->native_code + patch_info->ip.i;
7388
7389 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7390 if (IS_REX (pos [1]))
7391 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7392 else
7393 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7394
7395 *(gpointer*)code = (gpointer)patch_info->data.target;
7396 code += sizeof (gpointer);
7397
7398 remove = TRUE;
7399 break;
7400 }
7401 default:
7402 break;
7403 }
7404
7405 if (remove) {
7406 if (patch_info == cfg->patch_info)
7407 cfg->patch_info = patch_info->next;
7408 else {
7409 MonoJumpInfo *tmp;
7410
7411 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7412 ;
7413 tmp->next = patch_info->next;
7414 }
7415 }
7416 g_assert (code < cfg->native_code + cfg->code_size);
7417 }
7418
7419 cfg->code_len = code - cfg->native_code;
7420
7421 g_assert (cfg->code_len < cfg->code_size);
7422
7423 }
7424
7425 #endif /* DISABLE_JIT */
7426
7427 void*
mono_arch_instrument_prolog(MonoCompile * cfg,void * func,void * p,gboolean enable_arguments)7428 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7429 {
7430 guchar *code = (guchar *)p;
7431 MonoMethodSignature *sig;
7432 MonoInst *inst;
7433 int i, n, stack_area = 0;
7434
7435 /* Keep this in sync with mono_arch_get_argument_info */
7436
7437 if (enable_arguments) {
7438 /* Allocate a new area on the stack and save arguments there */
7439 sig = mono_method_signature (cfg->method);
7440
7441 n = sig->param_count + sig->hasthis;
7442
7443 stack_area = ALIGN_TO (n * 8, 16);
7444
7445 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7446
7447 for (i = 0; i < n; ++i) {
7448 inst = cfg->args [i];
7449
7450 if (inst->opcode == OP_REGVAR)
7451 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7452 else {
7453 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7454 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7455 }
7456 }
7457 }
7458
7459 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7460 amd64_set_reg_template (code, AMD64_ARG_REG1);
7461 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7462 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7463
7464 if (enable_arguments)
7465 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7466
7467 return code;
7468 }
7469
7470 enum {
7471 SAVE_NONE,
7472 SAVE_STRUCT,
7473 SAVE_EAX,
7474 SAVE_EAX_EDX,
7475 SAVE_XMM
7476 };
7477
7478 void*
mono_arch_instrument_epilog_full(MonoCompile * cfg,void * func,void * p,gboolean enable_arguments,gboolean preserve_argument_registers)7479 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7480 {
7481 guchar *code = (guchar *)p;
7482 int save_mode = SAVE_NONE;
7483 MonoMethod *method = cfg->method;
7484 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7485 int i;
7486
7487 switch (ret_type->type) {
7488 case MONO_TYPE_VOID:
7489 /* special case string .ctor icall */
7490 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7491 save_mode = SAVE_EAX;
7492 else
7493 save_mode = SAVE_NONE;
7494 break;
7495 case MONO_TYPE_I8:
7496 case MONO_TYPE_U8:
7497 save_mode = SAVE_EAX;
7498 break;
7499 case MONO_TYPE_R4:
7500 case MONO_TYPE_R8:
7501 save_mode = SAVE_XMM;
7502 break;
7503 case MONO_TYPE_GENERICINST:
7504 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7505 save_mode = SAVE_EAX;
7506 break;
7507 }
7508 /* Fall through */
7509 case MONO_TYPE_VALUETYPE:
7510 save_mode = SAVE_STRUCT;
7511 break;
7512 default:
7513 save_mode = SAVE_EAX;
7514 break;
7515 }
7516
7517 /* Save the result and copy it into the proper argument register */
7518 switch (save_mode) {
7519 case SAVE_EAX:
7520 amd64_push_reg (code, AMD64_RAX);
7521 /* Align stack */
7522 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7523 if (enable_arguments)
7524 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7525 break;
7526 case SAVE_STRUCT:
7527 /* FIXME: */
7528 if (enable_arguments)
7529 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7530 break;
7531 case SAVE_XMM:
7532 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7533 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7534 /* Align stack */
7535 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7536 /*
7537 * The result is already in the proper argument register so no copying
7538 * needed.
7539 */
7540 break;
7541 case SAVE_NONE:
7542 break;
7543 default:
7544 g_assert_not_reached ();
7545 }
7546
7547 /* Set %al since this is a varargs call */
7548 if (save_mode == SAVE_XMM)
7549 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7550 else
7551 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7552
7553 if (preserve_argument_registers) {
7554 for (i = 0; i < PARAM_REGS; ++i)
7555 amd64_push_reg (code, param_regs [i]);
7556 }
7557
7558 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7559 amd64_set_reg_template (code, AMD64_ARG_REG1);
7560 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7561
7562 if (preserve_argument_registers) {
7563 for (i = PARAM_REGS - 1; i >= 0; --i)
7564 amd64_pop_reg (code, param_regs [i]);
7565 }
7566
7567 /* Restore result */
7568 switch (save_mode) {
7569 case SAVE_EAX:
7570 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7571 amd64_pop_reg (code, AMD64_RAX);
7572 break;
7573 case SAVE_STRUCT:
7574 /* FIXME: */
7575 break;
7576 case SAVE_XMM:
7577 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7578 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7579 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7580 break;
7581 case SAVE_NONE:
7582 break;
7583 default:
7584 g_assert_not_reached ();
7585 }
7586
7587 return code;
7588 }
7589
7590 void
mono_arch_flush_icache(guint8 * code,gint size)7591 mono_arch_flush_icache (guint8 *code, gint size)
7592 {
7593 /* Not needed */
7594 }
7595
7596 void
mono_arch_flush_register_windows(void)7597 mono_arch_flush_register_windows (void)
7598 {
7599 }
7600
7601 gboolean
mono_arch_is_inst_imm(gint64 imm)7602 mono_arch_is_inst_imm (gint64 imm)
7603 {
7604 return amd64_use_imm32 (imm);
7605 }
7606
7607 /*
7608 * Determine whenever the trap whose info is in SIGINFO is caused by
7609 * integer overflow.
7610 */
7611 gboolean
mono_arch_is_int_overflow(void * sigctx,void * info)7612 mono_arch_is_int_overflow (void *sigctx, void *info)
7613 {
7614 MonoContext ctx;
7615 guint8* rip;
7616 int reg;
7617 gint64 value;
7618
7619 mono_sigctx_to_monoctx (sigctx, &ctx);
7620
7621 rip = (guint8*)ctx.gregs [AMD64_RIP];
7622
7623 if (IS_REX (rip [0])) {
7624 reg = amd64_rex_b (rip [0]);
7625 rip ++;
7626 }
7627 else
7628 reg = 0;
7629
7630 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7631 /* idiv REG */
7632 reg += x86_modrm_rm (rip [1]);
7633
7634 value = ctx.gregs [reg];
7635
7636 if (value == -1)
7637 return TRUE;
7638 }
7639
7640 return FALSE;
7641 }
7642
7643 guint32
mono_arch_get_patch_offset(guint8 * code)7644 mono_arch_get_patch_offset (guint8 *code)
7645 {
7646 return 3;
7647 }
7648
7649 /**
7650 * \return TRUE if no sw breakpoint was present.
7651 *
7652 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7653 * breakpoints in the original code, they are removed in the copy.
7654 */
7655 gboolean
mono_breakpoint_clean_code(guint8 * method_start,guint8 * code,int offset,guint8 * buf,int size)7656 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7657 {
7658 /*
7659 * If method_start is non-NULL we need to perform bound checks, since we access memory
7660 * at code - offset we could go before the start of the method and end up in a different
7661 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7662 * instead.
7663 */
7664 if (!method_start || code - offset >= method_start) {
7665 memcpy (buf, code - offset, size);
7666 } else {
7667 int diff = code - method_start;
7668 memset (buf, 0, size);
7669 memcpy (buf + offset - diff, method_start, diff + size - offset);
7670 }
7671 return TRUE;
7672 }
7673
7674 int
mono_arch_get_this_arg_reg(guint8 * code)7675 mono_arch_get_this_arg_reg (guint8 *code)
7676 {
7677 return AMD64_ARG_REG1;
7678 }
7679
7680 gpointer
mono_arch_get_this_arg_from_call(mgreg_t * regs,guint8 * code)7681 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7682 {
7683 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7684 }
7685
7686 #define MAX_ARCH_DELEGATE_PARAMS 10
7687
7688 static gpointer
get_delegate_invoke_impl(MonoTrampInfo ** info,gboolean has_target,guint32 param_count)7689 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7690 {
7691 guint8 *code, *start;
7692 GSList *unwind_ops = NULL;
7693 int i;
7694
7695 unwind_ops = mono_arch_get_cie_program ();
7696
7697 if (has_target) {
7698 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7699
7700 /* Replace the this argument with the target */
7701 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7702 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7703 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7704
7705 g_assert ((code - start) < 64);
7706 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7707 } else {
7708 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7709
7710 if (param_count == 0) {
7711 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7712 } else {
7713 /* We have to shift the arguments left */
7714 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7715 for (i = 0; i < param_count; ++i) {
7716 #ifdef TARGET_WIN32
7717 if (i < 3)
7718 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7719 else
7720 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7721 #else
7722 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7723 #endif
7724 }
7725
7726 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7727 }
7728 g_assert ((code - start) < 64);
7729 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7730 }
7731
7732 mono_arch_flush_icache (start, code - start);
7733
7734 if (has_target) {
7735 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7736 } else {
7737 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7738 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7739 g_free (name);
7740 }
7741
7742 if (mono_jit_map_is_enabled ()) {
7743 char *buff;
7744 if (has_target)
7745 buff = (char*)"delegate_invoke_has_target";
7746 else
7747 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7748 mono_emit_jit_tramp (start, code - start, buff);
7749 if (!has_target)
7750 g_free (buff);
7751 }
7752 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
7753
7754 return start;
7755 }
7756
7757 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7758
7759 static gpointer
get_delegate_virtual_invoke_impl(MonoTrampInfo ** info,gboolean load_imt_reg,int offset)7760 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7761 {
7762 guint8 *code, *start;
7763 int size = 20;
7764 char *tramp_name;
7765 GSList *unwind_ops;
7766
7767 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7768 return NULL;
7769
7770 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7771
7772 unwind_ops = mono_arch_get_cie_program ();
7773
7774 /* Replace the this argument with the target */
7775 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7776 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7777
7778 if (load_imt_reg) {
7779 /* Load the IMT reg */
7780 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7781 }
7782
7783 /* Load the vtable */
7784 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7785 amd64_jump_membase (code, AMD64_RAX, offset);
7786 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
7787
7788 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7789 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7790 g_free (tramp_name);
7791
7792 return start;
7793 }
7794
7795 /*
7796 * mono_arch_get_delegate_invoke_impls:
7797 *
7798 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7799 * trampolines.
7800 */
7801 GSList*
mono_arch_get_delegate_invoke_impls(void)7802 mono_arch_get_delegate_invoke_impls (void)
7803 {
7804 GSList *res = NULL;
7805 MonoTrampInfo *info;
7806 int i;
7807
7808 get_delegate_invoke_impl (&info, TRUE, 0);
7809 res = g_slist_prepend (res, info);
7810
7811 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7812 get_delegate_invoke_impl (&info, FALSE, i);
7813 res = g_slist_prepend (res, info);
7814 }
7815
7816 for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7817 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7818 res = g_slist_prepend (res, info);
7819 }
7820
7821 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7822 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7823 res = g_slist_prepend (res, info);
7824 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7825 res = g_slist_prepend (res, info);
7826 }
7827
7828 return res;
7829 }
7830
7831 gpointer
mono_arch_get_delegate_invoke_impl(MonoMethodSignature * sig,gboolean has_target)7832 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7833 {
7834 guint8 *code, *start;
7835 int i;
7836
7837 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7838 return NULL;
7839
7840 /* FIXME: Support more cases */
7841 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7842 return NULL;
7843
7844 if (has_target) {
7845 static guint8* cached = NULL;
7846
7847 if (cached)
7848 return cached;
7849
7850 if (mono_aot_only) {
7851 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7852 } else {
7853 MonoTrampInfo *info;
7854 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7855 mono_tramp_info_register (info, NULL);
7856 }
7857
7858 mono_memory_barrier ();
7859
7860 cached = start;
7861 } else {
7862 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7863 for (i = 0; i < sig->param_count; ++i)
7864 if (!mono_is_regsize_var (sig->params [i]))
7865 return NULL;
7866 if (sig->param_count > 4)
7867 return NULL;
7868
7869 code = cache [sig->param_count];
7870 if (code)
7871 return code;
7872
7873 if (mono_aot_only) {
7874 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7875 start = (guint8 *)mono_aot_get_trampoline (name);
7876 g_free (name);
7877 } else {
7878 MonoTrampInfo *info;
7879 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7880 mono_tramp_info_register (info, NULL);
7881 }
7882
7883 mono_memory_barrier ();
7884
7885 cache [sig->param_count] = start;
7886 }
7887
7888 return start;
7889 }
7890
7891 gpointer
mono_arch_get_delegate_virtual_invoke_impl(MonoMethodSignature * sig,MonoMethod * method,int offset,gboolean load_imt_reg)7892 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7893 {
7894 MonoTrampInfo *info;
7895 gpointer code;
7896
7897 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7898 if (code)
7899 mono_tramp_info_register (info, NULL);
7900 return code;
7901 }
7902
7903 void
mono_arch_finish_init(void)7904 mono_arch_finish_init (void)
7905 {
7906 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7907 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7908 #endif
7909 }
7910
7911 void
mono_arch_free_jit_tls_data(MonoJitTlsData * tls)7912 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7913 {
7914 }
7915
7916 #define CMP_SIZE (6 + 1)
7917 #define CMP_REG_REG_SIZE (4 + 1)
7918 #define BR_SMALL_SIZE 2
7919 #define BR_LARGE_SIZE 6
7920 #define MOV_REG_IMM_SIZE 10
7921 #define MOV_REG_IMM_32BIT_SIZE 6
7922 #define JUMP_REG_SIZE (2 + 1)
7923
7924 static int
imt_branch_distance(MonoIMTCheckItem ** imt_entries,int start,int target)7925 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7926 {
7927 int i, distance = 0;
7928 for (i = start; i < target; ++i)
7929 distance += imt_entries [i]->chunk_size;
7930 return distance;
7931 }
7932
7933 /*
7934 * LOCKING: called with the domain lock held
7935 */
7936 gpointer
mono_arch_build_imt_trampoline(MonoVTable * vtable,MonoDomain * domain,MonoIMTCheckItem ** imt_entries,int count,gpointer fail_tramp)7937 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7938 gpointer fail_tramp)
7939 {
7940 int i;
7941 int size = 0;
7942 guint8 *code, *start;
7943 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7944 GSList *unwind_ops;
7945
7946 for (i = 0; i < count; ++i) {
7947 MonoIMTCheckItem *item = imt_entries [i];
7948 if (item->is_equals) {
7949 if (item->check_target_idx) {
7950 if (!item->compare_done) {
7951 if (amd64_use_imm32 ((gint64)item->key))
7952 item->chunk_size += CMP_SIZE;
7953 else
7954 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7955 }
7956 if (item->has_target_code) {
7957 item->chunk_size += MOV_REG_IMM_SIZE;
7958 } else {
7959 if (vtable_is_32bit)
7960 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7961 else
7962 item->chunk_size += MOV_REG_IMM_SIZE;
7963 }
7964 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7965 } else {
7966 if (fail_tramp) {
7967 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7968 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7969 } else {
7970 if (vtable_is_32bit)
7971 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7972 else
7973 item->chunk_size += MOV_REG_IMM_SIZE;
7974 item->chunk_size += JUMP_REG_SIZE;
7975 /* with assert below:
7976 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7977 */
7978 }
7979 }
7980 } else {
7981 if (amd64_use_imm32 ((gint64)item->key))
7982 item->chunk_size += CMP_SIZE;
7983 else
7984 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7985 item->chunk_size += BR_LARGE_SIZE;
7986 imt_entries [item->check_target_idx]->compare_done = TRUE;
7987 }
7988 size += item->chunk_size;
7989 }
7990 if (fail_tramp)
7991 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7992 else
7993 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7994 start = code;
7995
7996 unwind_ops = mono_arch_get_cie_program ();
7997
7998 for (i = 0; i < count; ++i) {
7999 MonoIMTCheckItem *item = imt_entries [i];
8000 item->code_target = code;
8001 if (item->is_equals) {
8002 gboolean fail_case = !item->check_target_idx && fail_tramp;
8003
8004 if (item->check_target_idx || fail_case) {
8005 if (!item->compare_done || fail_case) {
8006 if (amd64_use_imm32 ((gint64)item->key))
8007 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8008 else {
8009 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8010 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8011 }
8012 }
8013 item->jmp_code = code;
8014 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8015 if (item->has_target_code) {
8016 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8017 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8018 } else {
8019 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8020 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8021 }
8022
8023 if (fail_case) {
8024 amd64_patch (item->jmp_code, code);
8025 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8026 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8027 item->jmp_code = NULL;
8028 }
8029 } else {
8030 /* enable the commented code to assert on wrong method */
8031 #if 0
8032 if (amd64_is_imm32 (item->key))
8033 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8034 else {
8035 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8036 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8037 }
8038 item->jmp_code = code;
8039 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8040 /* See the comment below about R10 */
8041 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8042 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8043 amd64_patch (item->jmp_code, code);
8044 amd64_breakpoint (code);
8045 item->jmp_code = NULL;
8046 #else
8047 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8048 needs to be preserved. R10 needs
8049 to be preserved for calls which
8050 require a runtime generic context,
8051 but interface calls don't. */
8052 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8053 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8054 #endif
8055 }
8056 } else {
8057 if (amd64_use_imm32 ((gint64)item->key))
8058 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8059 else {
8060 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8061 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8062 }
8063 item->jmp_code = code;
8064 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8065 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8066 else
8067 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8068 }
8069 g_assert (code - item->code_target <= item->chunk_size);
8070 }
8071 /* patch the branches to get to the target items */
8072 for (i = 0; i < count; ++i) {
8073 MonoIMTCheckItem *item = imt_entries [i];
8074 if (item->jmp_code) {
8075 if (item->check_target_idx) {
8076 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8077 }
8078 }
8079 }
8080
8081 if (!fail_tramp)
8082 UnlockedAdd (&mono_stats.imt_trampolines_size, code - start);
8083 g_assert (code - start <= size);
8084 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8085
8086 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
8087
8088 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8089
8090 return start;
8091 }
8092
8093 MonoMethod*
mono_arch_find_imt_method(mgreg_t * regs,guint8 * code)8094 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8095 {
8096 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8097 }
8098
8099 MonoVTable*
mono_arch_find_static_call_vtable(mgreg_t * regs,guint8 * code)8100 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8101 {
8102 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8103 }
8104
8105 GSList*
mono_arch_get_cie_program(void)8106 mono_arch_get_cie_program (void)
8107 {
8108 GSList *l = NULL;
8109
8110 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8111 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8112
8113 return l;
8114 }
8115
8116 #ifndef DISABLE_JIT
8117
8118 MonoInst*
mono_arch_emit_inst_for_method(MonoCompile * cfg,MonoMethod * cmethod,MonoMethodSignature * fsig,MonoInst ** args)8119 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8120 {
8121 MonoInst *ins = NULL;
8122 int opcode = 0;
8123
8124 if (cmethod->klass == mono_defaults.math_class) {
8125 if (strcmp (cmethod->name, "Sin") == 0) {
8126 opcode = OP_SIN;
8127 } else if (strcmp (cmethod->name, "Cos") == 0) {
8128 opcode = OP_COS;
8129 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8130 opcode = OP_SQRT;
8131 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8132 opcode = OP_ABS;
8133 }
8134
8135 if (opcode && fsig->param_count == 1) {
8136 MONO_INST_NEW (cfg, ins, opcode);
8137 ins->type = STACK_R8;
8138 ins->dreg = mono_alloc_freg (cfg);
8139 ins->sreg1 = args [0]->dreg;
8140 MONO_ADD_INS (cfg->cbb, ins);
8141 }
8142
8143 opcode = 0;
8144 if (cfg->opt & MONO_OPT_CMOV) {
8145 if (strcmp (cmethod->name, "Min") == 0) {
8146 if (fsig->params [0]->type == MONO_TYPE_I4)
8147 opcode = OP_IMIN;
8148 if (fsig->params [0]->type == MONO_TYPE_U4)
8149 opcode = OP_IMIN_UN;
8150 else if (fsig->params [0]->type == MONO_TYPE_I8)
8151 opcode = OP_LMIN;
8152 else if (fsig->params [0]->type == MONO_TYPE_U8)
8153 opcode = OP_LMIN_UN;
8154 } else if (strcmp (cmethod->name, "Max") == 0) {
8155 if (fsig->params [0]->type == MONO_TYPE_I4)
8156 opcode = OP_IMAX;
8157 if (fsig->params [0]->type == MONO_TYPE_U4)
8158 opcode = OP_IMAX_UN;
8159 else if (fsig->params [0]->type == MONO_TYPE_I8)
8160 opcode = OP_LMAX;
8161 else if (fsig->params [0]->type == MONO_TYPE_U8)
8162 opcode = OP_LMAX_UN;
8163 }
8164 }
8165
8166 if (opcode && fsig->param_count == 2) {
8167 MONO_INST_NEW (cfg, ins, opcode);
8168 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8169 ins->dreg = mono_alloc_ireg (cfg);
8170 ins->sreg1 = args [0]->dreg;
8171 ins->sreg2 = args [1]->dreg;
8172 MONO_ADD_INS (cfg->cbb, ins);
8173 }
8174
8175 #if 0
8176 /* OP_FREM is not IEEE compatible */
8177 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8178 MONO_INST_NEW (cfg, ins, OP_FREM);
8179 ins->inst_i0 = args [0];
8180 ins->inst_i1 = args [1];
8181 }
8182 #endif
8183 }
8184
8185 return ins;
8186 }
8187 #endif
8188
8189 mgreg_t
mono_arch_context_get_int_reg(MonoContext * ctx,int reg)8190 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8191 {
8192 return ctx->gregs [reg];
8193 }
8194
8195 void
mono_arch_context_set_int_reg(MonoContext * ctx,int reg,mgreg_t val)8196 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8197 {
8198 ctx->gregs [reg] = val;
8199 }
8200
8201 /*
8202 * mono_arch_emit_load_aotconst:
8203 *
8204 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8205 * TARGET from the mscorlib GOT in full-aot code.
8206 * On AMD64, the result is placed into R11.
8207 */
8208 guint8*
mono_arch_emit_load_aotconst(guint8 * start,guint8 * code,MonoJumpInfo ** ji,MonoJumpInfoType tramp_type,gconstpointer target)8209 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8210 {
8211 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8212 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8213
8214 return code;
8215 }
8216
8217 /*
8218 * mono_arch_get_trampolines:
8219 *
8220 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8221 * for AOT.
8222 */
8223 GSList *
mono_arch_get_trampolines(gboolean aot)8224 mono_arch_get_trampolines (gboolean aot)
8225 {
8226 return mono_amd64_get_exception_trampolines (aot);
8227 }
8228
8229 /* Soft Debug support */
8230 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8231
8232 /*
8233 * mono_arch_set_breakpoint:
8234 *
8235 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8236 * The location should contain code emitted by OP_SEQ_POINT.
8237 */
8238 void
mono_arch_set_breakpoint(MonoJitInfo * ji,guint8 * ip)8239 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8240 {
8241 guint8 *code = ip;
8242
8243 if (ji->from_aot) {
8244 guint32 native_offset = ip - (guint8*)ji->code_start;
8245 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8246
8247 g_assert (info->bp_addrs [native_offset] == 0);
8248 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8249 } else {
8250 /* ip points to a mov r11, 0 */
8251 g_assert (code [0] == 0x41);
8252 g_assert (code [1] == 0xbb);
8253 amd64_mov_reg_imm (code, AMD64_R11, 1);
8254 }
8255 }
8256
8257 /*
8258 * mono_arch_clear_breakpoint:
8259 *
8260 * Clear the breakpoint at IP.
8261 */
8262 void
mono_arch_clear_breakpoint(MonoJitInfo * ji,guint8 * ip)8263 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8264 {
8265 guint8 *code = ip;
8266
8267 if (ji->from_aot) {
8268 guint32 native_offset = ip - (guint8*)ji->code_start;
8269 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8270
8271 info->bp_addrs [native_offset] = NULL;
8272 } else {
8273 amd64_mov_reg_imm (code, AMD64_R11, 0);
8274 }
8275 }
8276
8277 gboolean
mono_arch_is_breakpoint_event(void * info,void * sigctx)8278 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8279 {
8280 /* We use soft breakpoints on amd64 */
8281 return FALSE;
8282 }
8283
8284 /*
8285 * mono_arch_skip_breakpoint:
8286 *
8287 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8288 * we resume, the instruction is not executed again.
8289 */
8290 void
mono_arch_skip_breakpoint(MonoContext * ctx,MonoJitInfo * ji)8291 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8292 {
8293 g_assert_not_reached ();
8294 }
8295
8296 /*
8297 * mono_arch_start_single_stepping:
8298 *
8299 * Start single stepping.
8300 */
8301 void
mono_arch_start_single_stepping(void)8302 mono_arch_start_single_stepping (void)
8303 {
8304 ss_trampoline = mini_get_single_step_trampoline ();
8305 }
8306
8307 /*
8308 * mono_arch_stop_single_stepping:
8309 *
8310 * Stop single stepping.
8311 */
8312 void
mono_arch_stop_single_stepping(void)8313 mono_arch_stop_single_stepping (void)
8314 {
8315 ss_trampoline = NULL;
8316 }
8317
8318 /*
8319 * mono_arch_is_single_step_event:
8320 *
8321 * Return whenever the machine state in SIGCTX corresponds to a single
8322 * step event.
8323 */
8324 gboolean
mono_arch_is_single_step_event(void * info,void * sigctx)8325 mono_arch_is_single_step_event (void *info, void *sigctx)
8326 {
8327 /* We use soft breakpoints on amd64 */
8328 return FALSE;
8329 }
8330
8331 /*
8332 * mono_arch_skip_single_step:
8333 *
8334 * Modify CTX so the ip is placed after the single step trigger instruction,
8335 * we resume, the instruction is not executed again.
8336 */
8337 void
mono_arch_skip_single_step(MonoContext * ctx)8338 mono_arch_skip_single_step (MonoContext *ctx)
8339 {
8340 g_assert_not_reached ();
8341 }
8342
8343 /*
8344 * mono_arch_create_seq_point_info:
8345 *
8346 * Return a pointer to a data structure which is used by the sequence
8347 * point implementation in AOTed code.
8348 */
8349 gpointer
mono_arch_get_seq_point_info(MonoDomain * domain,guint8 * code)8350 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8351 {
8352 SeqPointInfo *info;
8353 MonoJitInfo *ji;
8354
8355 // FIXME: Add a free function
8356
8357 mono_domain_lock (domain);
8358 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8359 code);
8360 mono_domain_unlock (domain);
8361
8362 if (!info) {
8363 ji = mono_jit_info_table_find (domain, (char*)code);
8364 g_assert (ji);
8365
8366 // FIXME: Optimize the size
8367 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8368
8369 info->ss_tramp_addr = &ss_trampoline;
8370
8371 mono_domain_lock (domain);
8372 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8373 code, info);
8374 mono_domain_unlock (domain);
8375 }
8376
8377 return info;
8378 }
8379
8380 #endif
8381
8382 gboolean
mono_arch_opcode_supported(int opcode)8383 mono_arch_opcode_supported (int opcode)
8384 {
8385 switch (opcode) {
8386 case OP_ATOMIC_ADD_I4:
8387 case OP_ATOMIC_ADD_I8:
8388 case OP_ATOMIC_EXCHANGE_I4:
8389 case OP_ATOMIC_EXCHANGE_I8:
8390 case OP_ATOMIC_CAS_I4:
8391 case OP_ATOMIC_CAS_I8:
8392 case OP_ATOMIC_LOAD_I1:
8393 case OP_ATOMIC_LOAD_I2:
8394 case OP_ATOMIC_LOAD_I4:
8395 case OP_ATOMIC_LOAD_I8:
8396 case OP_ATOMIC_LOAD_U1:
8397 case OP_ATOMIC_LOAD_U2:
8398 case OP_ATOMIC_LOAD_U4:
8399 case OP_ATOMIC_LOAD_U8:
8400 case OP_ATOMIC_LOAD_R4:
8401 case OP_ATOMIC_LOAD_R8:
8402 case OP_ATOMIC_STORE_I1:
8403 case OP_ATOMIC_STORE_I2:
8404 case OP_ATOMIC_STORE_I4:
8405 case OP_ATOMIC_STORE_I8:
8406 case OP_ATOMIC_STORE_U1:
8407 case OP_ATOMIC_STORE_U2:
8408 case OP_ATOMIC_STORE_U4:
8409 case OP_ATOMIC_STORE_U8:
8410 case OP_ATOMIC_STORE_R4:
8411 case OP_ATOMIC_STORE_R8:
8412 return TRUE;
8413 default:
8414 return FALSE;
8415 }
8416 }
8417
8418 CallInfo*
mono_arch_get_call_info(MonoMemPool * mp,MonoMethodSignature * sig)8419 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8420 {
8421 return get_call_info (mp, sig);
8422 }
8423