1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
8
9 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
15 // expected-no-diagnostics
16 #ifndef HEADER
17 #define HEADER
18
19
20
21 double Ga = 1.0;
22 double Gb = 2.0;
23 double Gc = 3.0;
24 double Gd = 4.0;
25
foo(short a,short b,short c,short d)26 int foo(short a, short b, short c, short d){
27 static float Sa = 5.0;
28 static float Sb = 6.0;
29 static float Sc = 7.0;
30 static float Sd = 8.0;
31
32
33 // 3 local vars being captured.
34
35
36
37
38 // 3 static vars being captured.
39
40
41
42
43 // 3 static global vars being captured.
44
45
46
47
48 // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd
49 #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0)
50 {
51 b += 1;
52 Gb += 1.0;
53 Sb += 1.0;
54
55 // The parallel region only uses 3 captures.
56 // Capture d, Gd, Sd,
57
58 #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0)
59 {
60 d += 1;
61 Gd += 1.0;
62 Sd += 1.0;
63 }
64 }
65 return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd;
66 }
67
bar(short a,short b,short c,short d)68 int bar(short a, short b, short c, short d){
69 static float Sa = 9.0;
70 static float Sb = 10.0;
71 static float Sc = 11.0;
72 static float Sd = 12.0;
73
74 // Capture a, b, c, d
75 #pragma omp parallel
76 {
77
78 // 3 local vars being captured.
79
80
81
82
83 // 3 static vars being captured.
84
85
86
87
88 // 3 static global vars being captured.
89
90
91
92
93 // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd
94 #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0)
95 {
96 b += 1;
97 Gb += 1.0;
98 Sb += 1.0;
99
100
101 // Capture d, Gd, Sd
102 #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0)
103 {
104 d += 1;
105 Gd += 1.0;
106 Sd += 1.0;
107 }
108 }
109 }
110 return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd;
111 }
112
113 ///
114 /// Tests with template functions.
115 ///
116
117
118 template<typename T>
tbar(T a,T b,T c,T d)119 int tbar(T a, T b, T c, T d){
120 static float Sa = 17.0;
121 static float Sb = 18.0;
122 static float Sc = 19.0;
123 static float Sd = 20.0;
124
125 // Capture a, b, c, d
126 #pragma omp parallel
127 {
128
129 // 3 local vars being captured.
130
131
132
133
134 // 3 static vars being captured.
135
136
137
138
139 // 3 static global vars being captured.
140
141
142
143
144 // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd
145 #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0)
146 {
147 b += 1;
148 Gb += 1.0;
149 Sb += 1.0;
150
151
152 // Capture d, Gd, Sd
153 #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0)
154 {
155 d += 1;
156 Gd += 1.0;
157 Sd += 1.0;
158 }
159 }
160 }
161 return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd;
162 }
163
tbar2(short a,short b,short c,short d)164 int tbar2(short a, short b, short c, short d){
165 return tbar(a, b, c, d);
166 }
167
168 #endif
169 // CHECK1-LABEL: define {{[^@]+}}@_Z3foossss
170 // CHECK1-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] {
171 // CHECK1-NEXT: entry:
172 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
173 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
174 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
175 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
176 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
177 // CHECK1-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8
178 // CHECK1-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8
179 // CHECK1-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8
180 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
181 // CHECK1-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8
182 // CHECK1-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8
183 // CHECK1-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8
184 // CHECK1-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8
185 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8
186 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8
187 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8
188 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
189 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
190 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
191 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
192 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2
193 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16*
194 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
195 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_CASTED]], align 8
196 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* @Gb, align 8
197 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double*
198 // CHECK1-NEXT: store double [[TMP2]], double* [[CONV1]], align 8
199 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[GB_CASTED]], align 8
200 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
201 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float*
202 // CHECK1-NEXT: store float [[TMP4]], float* [[CONV2]], align 4
203 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[SB_CASTED]], align 8
204 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* @Gc, align 8
205 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double*
206 // CHECK1-NEXT: store double [[TMP6]], double* [[CONV3]], align 8
207 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[GC_CASTED]], align 8
208 // CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2
209 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16*
210 // CHECK1-NEXT: store i16 [[TMP8]], i16* [[CONV4]], align 2
211 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8
212 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
213 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float*
214 // CHECK1-NEXT: store float [[TMP10]], float* [[CONV5]], align 4
215 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[SC_CASTED]], align 8
216 // CHECK1-NEXT: [[TMP12:%.*]] = load i16, i16* [[D_ADDR]], align 2
217 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16*
218 // CHECK1-NEXT: store i16 [[TMP12]], i16* [[CONV6]], align 2
219 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[D_CASTED]], align 8
220 // CHECK1-NEXT: [[TMP14:%.*]] = load double, double* @Gd, align 8
221 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double*
222 // CHECK1-NEXT: store double [[TMP14]], double* [[CONV7]], align 8
223 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[GD_CASTED]], align 8
224 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
225 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float*
226 // CHECK1-NEXT: store float [[TMP16]], float* [[CONV8]], align 4
227 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[SD_CASTED]], align 8
228 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* @Ga, align 8
229 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP18]], 0.000000e+00
230 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
231 // CHECK1: land.lhs.true:
232 // CHECK1-NEXT: [[TMP19:%.*]] = load i16, i16* [[A_ADDR]], align 2
233 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP19]] to i32
234 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
235 // CHECK1-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
236 // CHECK1: land.lhs.true11:
237 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
238 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP20]] to double
239 // CHECK1-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
240 // CHECK1-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
241 // CHECK1: omp_if.then:
242 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
243 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
244 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP22]], align 8
245 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
246 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
247 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8
248 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
249 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8
250 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
251 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
252 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8
253 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
254 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
255 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8
256 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
257 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8
258 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
259 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
260 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP32]], align 8
261 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
262 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
263 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP34]], align 8
264 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
265 // CHECK1-NEXT: store i8* null, i8** [[TMP35]], align 8
266 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
267 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
268 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP37]], align 8
269 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
270 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64*
271 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP39]], align 8
272 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
273 // CHECK1-NEXT: store i8* null, i8** [[TMP40]], align 8
274 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
275 // CHECK1-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64*
276 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP42]], align 8
277 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
278 // CHECK1-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64*
279 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP44]], align 8
280 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
281 // CHECK1-NEXT: store i8* null, i8** [[TMP45]], align 8
282 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
283 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64*
284 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP47]], align 8
285 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
286 // CHECK1-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64*
287 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP49]], align 8
288 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
289 // CHECK1-NEXT: store i8* null, i8** [[TMP50]], align 8
290 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
291 // CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
292 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP52]], align 8
293 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
294 // CHECK1-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*
295 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP54]], align 8
296 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
297 // CHECK1-NEXT: store i8* null, i8** [[TMP55]], align 8
298 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
299 // CHECK1-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to i64*
300 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP57]], align 8
301 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
302 // CHECK1-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i64*
303 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP59]], align 8
304 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
305 // CHECK1-NEXT: store i8* null, i8** [[TMP60]], align 8
306 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
307 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
308 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP62]], align 8
309 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
310 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
311 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP64]], align 8
312 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
313 // CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8
314 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
315 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
316 // CHECK1-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.region_id, i32 9, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null)
317 // CHECK1-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
318 // CHECK1-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
319 // CHECK1: omp_offload.failed:
320 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]]) #[[ATTR2:[0-9]+]]
321 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
322 // CHECK1: omp_offload.cont:
323 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
324 // CHECK1: omp_if.else:
325 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]]) #[[ATTR2]]
326 // CHECK1-NEXT: br label [[OMP_IF_END]]
327 // CHECK1: omp_if.end:
328 // CHECK1-NEXT: [[TMP70:%.*]] = load i16, i16* [[A_ADDR]], align 2
329 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP70]] to i32
330 // CHECK1-NEXT: [[TMP71:%.*]] = load i16, i16* [[B_ADDR]], align 2
331 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP71]] to i32
332 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV14]], [[CONV15]]
333 // CHECK1-NEXT: [[TMP72:%.*]] = load i16, i16* [[C_ADDR]], align 2
334 // CHECK1-NEXT: [[CONV16:%.*]] = sext i16 [[TMP72]] to i32
335 // CHECK1-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD]], [[CONV16]]
336 // CHECK1-NEXT: [[TMP73:%.*]] = load i16, i16* [[D_ADDR]], align 2
337 // CHECK1-NEXT: [[CONV18:%.*]] = sext i16 [[TMP73]] to i32
338 // CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]]
339 // CHECK1-NEXT: [[TMP74:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
340 // CHECK1-NEXT: [[CONV20:%.*]] = fptosi float [[TMP74]] to i32
341 // CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]]
342 // CHECK1-NEXT: [[TMP75:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
343 // CHECK1-NEXT: [[CONV22:%.*]] = fptosi float [[TMP75]] to i32
344 // CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]]
345 // CHECK1-NEXT: [[TMP76:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
346 // CHECK1-NEXT: [[CONV24:%.*]] = fptosi float [[TMP76]] to i32
347 // CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]]
348 // CHECK1-NEXT: [[TMP77:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
349 // CHECK1-NEXT: [[CONV26:%.*]] = fptosi float [[TMP77]] to i32
350 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]]
351 // CHECK1-NEXT: ret i32 [[ADD27]]
352 //
353 //
354 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49
355 // CHECK1-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1:[0-9]+]] {
356 // CHECK1-NEXT: entry:
357 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
358 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8
359 // CHECK1-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8
360 // CHECK1-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8
361 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
362 // CHECK1-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8
363 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8
364 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8
365 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8
366 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
367 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
368 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
369 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
370 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
371 // CHECK1-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8
372 // CHECK1-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8
373 // CHECK1-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8
374 // CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
375 // CHECK1-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8
376 // CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8
377 // CHECK1-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8
378 // CHECK1-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8
379 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16*
380 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
381 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
382 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
383 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
384 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
385 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
386 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
387 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
388 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
389 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
390 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
391 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
392 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
393 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
394 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
395 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
396 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
397 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
398 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
399 // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
400 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
401 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
402 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
403 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
404 // CHECK1: land.lhs.true:
405 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
406 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
407 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
408 // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
409 // CHECK1: land.lhs.true17:
410 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
411 // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
412 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
413 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
414 // CHECK1: omp_if.then:
415 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
416 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
417 // CHECK1: omp_if.else:
418 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
419 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
420 // CHECK1-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]]
421 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
422 // CHECK1-NEXT: br label [[OMP_IF_END]]
423 // CHECK1: omp_if.end:
424 // CHECK1-NEXT: ret void
425 //
426 //
427 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
428 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
429 // CHECK1-NEXT: entry:
430 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
431 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
432 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
433 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8
434 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8
435 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
436 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
437 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
438 // CHECK1-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8
439 // CHECK1-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8
440 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8
441 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8
442 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8
443 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
444 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
445 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
446 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
447 // CHECK1-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
448 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
449 // CHECK1-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
450 // CHECK1-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
451 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
452 // CHECK1-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
453 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
454 // CHECK1-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
455 // CHECK1-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
456 // CHECK1-NEXT: ret void
457 //
458 //
459 // CHECK1-LABEL: define {{[^@]+}}@_Z3barssss
460 // CHECK1-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] {
461 // CHECK1-NEXT: entry:
462 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
463 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
464 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
465 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
466 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
467 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
468 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
469 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
470 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
471 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
472 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
473 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
474 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
475 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
476 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
477 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
478 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
479 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
480 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
481 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
482 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
483 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
484 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
485 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
486 // CHECK1-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
487 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
488 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
489 // CHECK1-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
490 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
491 // CHECK1-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
492 // CHECK1-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
493 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
494 // CHECK1-NEXT: ret i32 [[ADD13]]
495 //
496 //
497 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
498 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
499 // CHECK1-NEXT: entry:
500 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
501 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
502 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 8
503 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 8
504 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
505 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
506 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
507 // CHECK1-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8
508 // CHECK1-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8
509 // CHECK1-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8
510 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
511 // CHECK1-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8
512 // CHECK1-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8
513 // CHECK1-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8
514 // CHECK1-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8
515 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8
516 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8
517 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8
518 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
519 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
520 // CHECK1-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 8
521 // CHECK1-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 8
522 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
523 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
524 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 8
525 // CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 8
526 // CHECK1-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 8
527 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 8
528 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
529 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16*
530 // CHECK1-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
531 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
532 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* @Gb, align 8
533 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double*
534 // CHECK1-NEXT: store double [[TMP6]], double* [[CONV1]], align 8
535 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[GB_CASTED]], align 8
536 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
537 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float*
538 // CHECK1-NEXT: store float [[TMP8]], float* [[CONV2]], align 4
539 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[SB_CASTED]], align 8
540 // CHECK1-NEXT: [[TMP10:%.*]] = load double, double* @Gc, align 8
541 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double*
542 // CHECK1-NEXT: store double [[TMP10]], double* [[CONV3]], align 8
543 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[GC_CASTED]], align 8
544 // CHECK1-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP2]], align 2
545 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16*
546 // CHECK1-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
547 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[C_CASTED]], align 8
548 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
549 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float*
550 // CHECK1-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
551 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[SC_CASTED]], align 8
552 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[TMP3]], align 2
553 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16*
554 // CHECK1-NEXT: store i16 [[TMP16]], i16* [[CONV6]], align 2
555 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[D_CASTED]], align 8
556 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* @Gd, align 8
557 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double*
558 // CHECK1-NEXT: store double [[TMP18]], double* [[CONV7]], align 8
559 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[GD_CASTED]], align 8
560 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
561 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float*
562 // CHECK1-NEXT: store float [[TMP20]], float* [[CONV8]], align 4
563 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SD_CASTED]], align 8
564 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* @Ga, align 8
565 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP22]], 0.000000e+00
566 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
567 // CHECK1: land.lhs.true:
568 // CHECK1-NEXT: [[TMP23:%.*]] = load i16, i16* [[TMP0]], align 2
569 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP23]] to i32
570 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
571 // CHECK1-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
572 // CHECK1: land.lhs.true11:
573 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
574 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP24]] to double
575 // CHECK1-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
576 // CHECK1-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
577 // CHECK1: omp_if.then:
578 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
579 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
580 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP26]], align 8
581 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
582 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
583 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP28]], align 8
584 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
585 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8
586 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
587 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
588 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP31]], align 8
589 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
590 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64*
591 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP33]], align 8
592 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
593 // CHECK1-NEXT: store i8* null, i8** [[TMP34]], align 8
594 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
595 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
596 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP36]], align 8
597 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
598 // CHECK1-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64*
599 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
600 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
601 // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8
602 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
603 // CHECK1-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
604 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP41]], align 8
605 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
606 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
607 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP43]], align 8
608 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
609 // CHECK1-NEXT: store i8* null, i8** [[TMP44]], align 8
610 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
611 // CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
612 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP46]], align 8
613 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
614 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
615 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP48]], align 8
616 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
617 // CHECK1-NEXT: store i8* null, i8** [[TMP49]], align 8
618 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
619 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
620 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP51]], align 8
621 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
622 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
623 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP53]], align 8
624 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
625 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8
626 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
627 // CHECK1-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i64*
628 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP56]], align 8
629 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
630 // CHECK1-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64*
631 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP58]], align 8
632 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
633 // CHECK1-NEXT: store i8* null, i8** [[TMP59]], align 8
634 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
635 // CHECK1-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64*
636 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP61]], align 8
637 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
638 // CHECK1-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64*
639 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP63]], align 8
640 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
641 // CHECK1-NEXT: store i8* null, i8** [[TMP64]], align 8
642 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
643 // CHECK1-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to i64*
644 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP66]], align 8
645 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
646 // CHECK1-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i64*
647 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP68]], align 8
648 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
649 // CHECK1-NEXT: store i8* null, i8** [[TMP69]], align 8
650 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
651 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
652 // CHECK1-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.region_id, i32 9, i8** [[TMP70]], i8** [[TMP71]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null)
653 // CHECK1-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0
654 // CHECK1-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
655 // CHECK1: omp_offload.failed:
656 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
657 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
658 // CHECK1: omp_offload.cont:
659 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
660 // CHECK1: omp_if.else:
661 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
662 // CHECK1-NEXT: br label [[OMP_IF_END]]
663 // CHECK1: omp_if.end:
664 // CHECK1-NEXT: ret void
665 //
666 //
667 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94
668 // CHECK1-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1]] {
669 // CHECK1-NEXT: entry:
670 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
671 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8
672 // CHECK1-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8
673 // CHECK1-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8
674 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
675 // CHECK1-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8
676 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8
677 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8
678 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8
679 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
680 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
681 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
682 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
683 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
684 // CHECK1-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8
685 // CHECK1-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8
686 // CHECK1-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8
687 // CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
688 // CHECK1-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8
689 // CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8
690 // CHECK1-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8
691 // CHECK1-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8
692 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16*
693 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
694 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
695 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
696 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
697 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
698 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
699 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
700 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
701 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
702 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
703 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
704 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
705 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
706 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
707 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
708 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
709 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
710 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
711 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
712 // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
713 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
714 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
715 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
716 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
717 // CHECK1: land.lhs.true:
718 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
719 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
720 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
721 // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
722 // CHECK1: land.lhs.true17:
723 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
724 // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
725 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
726 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
727 // CHECK1: omp_if.then:
728 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
729 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
730 // CHECK1: omp_if.else:
731 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
732 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
733 // CHECK1-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]]
734 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
735 // CHECK1-NEXT: br label [[OMP_IF_END]]
736 // CHECK1: omp_if.end:
737 // CHECK1-NEXT: ret void
738 //
739 //
740 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
741 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
742 // CHECK1-NEXT: entry:
743 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
744 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
745 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
746 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8
747 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8
748 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
749 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
750 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
751 // CHECK1-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8
752 // CHECK1-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8
753 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8
754 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8
755 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8
756 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
757 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
758 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
759 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
760 // CHECK1-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
761 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
762 // CHECK1-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
763 // CHECK1-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
764 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
765 // CHECK1-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
766 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
767 // CHECK1-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
768 // CHECK1-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
769 // CHECK1-NEXT: ret void
770 //
771 //
772 // CHECK1-LABEL: define {{[^@]+}}@_Z5tbar2ssss
773 // CHECK1-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] {
774 // CHECK1-NEXT: entry:
775 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
776 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
777 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
778 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
779 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
780 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
781 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
782 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
783 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
784 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
785 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
786 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
787 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]])
788 // CHECK1-NEXT: ret i32 [[CALL]]
789 //
790 //
791 // CHECK1-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_
792 // CHECK1-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat {
793 // CHECK1-NEXT: entry:
794 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
795 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
796 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
797 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
798 // CHECK1-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
799 // CHECK1-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
800 // CHECK1-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
801 // CHECK1-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
802 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
803 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
804 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
805 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
806 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
807 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
808 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
809 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
810 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
811 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
812 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
813 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
814 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
815 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
816 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
817 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
818 // CHECK1-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
819 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
820 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
821 // CHECK1-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
822 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
823 // CHECK1-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
824 // CHECK1-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
825 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
826 // CHECK1-NEXT: ret i32 [[ADD13]]
827 //
828 //
829 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
830 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
831 // CHECK1-NEXT: entry:
832 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
833 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
834 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 8
835 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 8
836 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
837 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
838 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
839 // CHECK1-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8
840 // CHECK1-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8
841 // CHECK1-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8
842 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
843 // CHECK1-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8
844 // CHECK1-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8
845 // CHECK1-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8
846 // CHECK1-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8
847 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8
848 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8
849 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8
850 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
851 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
852 // CHECK1-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 8
853 // CHECK1-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 8
854 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
855 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
856 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 8
857 // CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 8
858 // CHECK1-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 8
859 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 8
860 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
861 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16*
862 // CHECK1-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
863 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
864 // CHECK1-NEXT: [[TMP6:%.*]] = load double, double* @Gb, align 8
865 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double*
866 // CHECK1-NEXT: store double [[TMP6]], double* [[CONV1]], align 8
867 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[GB_CASTED]], align 8
868 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
869 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float*
870 // CHECK1-NEXT: store float [[TMP8]], float* [[CONV2]], align 4
871 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[SB_CASTED]], align 8
872 // CHECK1-NEXT: [[TMP10:%.*]] = load double, double* @Gc, align 8
873 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double*
874 // CHECK1-NEXT: store double [[TMP10]], double* [[CONV3]], align 8
875 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[GC_CASTED]], align 8
876 // CHECK1-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP2]], align 2
877 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16*
878 // CHECK1-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
879 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[C_CASTED]], align 8
880 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
881 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float*
882 // CHECK1-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
883 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[SC_CASTED]], align 8
884 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[TMP3]], align 2
885 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16*
886 // CHECK1-NEXT: store i16 [[TMP16]], i16* [[CONV6]], align 2
887 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[D_CASTED]], align 8
888 // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* @Gd, align 8
889 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double*
890 // CHECK1-NEXT: store double [[TMP18]], double* [[CONV7]], align 8
891 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[GD_CASTED]], align 8
892 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
893 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float*
894 // CHECK1-NEXT: store float [[TMP20]], float* [[CONV8]], align 4
895 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SD_CASTED]], align 8
896 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* @Ga, align 8
897 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP22]], 0.000000e+00
898 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
899 // CHECK1: land.lhs.true:
900 // CHECK1-NEXT: [[TMP23:%.*]] = load i16, i16* [[TMP0]], align 2
901 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP23]] to i32
902 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
903 // CHECK1-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
904 // CHECK1: land.lhs.true11:
905 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
906 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP24]] to double
907 // CHECK1-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
908 // CHECK1-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
909 // CHECK1: omp_if.then:
910 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
911 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
912 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP26]], align 8
913 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
914 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
915 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP28]], align 8
916 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
917 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8
918 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
919 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
920 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP31]], align 8
921 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
922 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64*
923 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP33]], align 8
924 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
925 // CHECK1-NEXT: store i8* null, i8** [[TMP34]], align 8
926 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
927 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
928 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP36]], align 8
929 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
930 // CHECK1-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64*
931 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
932 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
933 // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8
934 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
935 // CHECK1-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
936 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP41]], align 8
937 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
938 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
939 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[TMP43]], align 8
940 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
941 // CHECK1-NEXT: store i8* null, i8** [[TMP44]], align 8
942 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
943 // CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
944 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP46]], align 8
945 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
946 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
947 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[TMP48]], align 8
948 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
949 // CHECK1-NEXT: store i8* null, i8** [[TMP49]], align 8
950 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
951 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
952 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP51]], align 8
953 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
954 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
955 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP53]], align 8
956 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
957 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8
958 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
959 // CHECK1-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i64*
960 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP56]], align 8
961 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
962 // CHECK1-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64*
963 // CHECK1-NEXT: store i64 [[TMP17]], i64* [[TMP58]], align 8
964 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
965 // CHECK1-NEXT: store i8* null, i8** [[TMP59]], align 8
966 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
967 // CHECK1-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64*
968 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP61]], align 8
969 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
970 // CHECK1-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64*
971 // CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP63]], align 8
972 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
973 // CHECK1-NEXT: store i8* null, i8** [[TMP64]], align 8
974 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
975 // CHECK1-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to i64*
976 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP66]], align 8
977 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
978 // CHECK1-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i64*
979 // CHECK1-NEXT: store i64 [[TMP21]], i64* [[TMP68]], align 8
980 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
981 // CHECK1-NEXT: store i8* null, i8** [[TMP69]], align 8
982 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
983 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
984 // CHECK1-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.region_id, i32 9, i8** [[TMP70]], i8** [[TMP71]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null)
985 // CHECK1-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0
986 // CHECK1-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
987 // CHECK1: omp_offload.failed:
988 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
989 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
990 // CHECK1: omp_offload.cont:
991 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
992 // CHECK1: omp_if.else:
993 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
994 // CHECK1-NEXT: br label [[OMP_IF_END]]
995 // CHECK1: omp_if.end:
996 // CHECK1-NEXT: ret void
997 //
998 //
999 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145
1000 // CHECK1-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1]] {
1001 // CHECK1-NEXT: entry:
1002 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1003 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8
1004 // CHECK1-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8
1005 // CHECK1-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8
1006 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
1007 // CHECK1-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8
1008 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8
1009 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8
1010 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8
1011 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1012 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1013 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1014 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1015 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
1016 // CHECK1-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8
1017 // CHECK1-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8
1018 // CHECK1-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8
1019 // CHECK1-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
1020 // CHECK1-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8
1021 // CHECK1-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8
1022 // CHECK1-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8
1023 // CHECK1-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8
1024 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16*
1025 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
1026 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
1027 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
1028 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
1029 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
1030 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
1031 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
1032 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
1033 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
1034 // CHECK1-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
1035 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
1036 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
1037 // CHECK1-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
1038 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
1039 // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
1040 // CHECK1-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
1041 // CHECK1-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
1042 // CHECK1-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
1043 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
1044 // CHECK1-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
1045 // CHECK1-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
1046 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
1047 // CHECK1-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
1048 // CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1049 // CHECK1: land.lhs.true:
1050 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
1051 // CHECK1-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
1052 // CHECK1-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
1053 // CHECK1-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
1054 // CHECK1: land.lhs.true17:
1055 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
1056 // CHECK1-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
1057 // CHECK1-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
1058 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1059 // CHECK1: omp_if.then:
1060 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
1061 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1062 // CHECK1: omp_if.else:
1063 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1064 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1065 // CHECK1-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]]
1066 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1067 // CHECK1-NEXT: br label [[OMP_IF_END]]
1068 // CHECK1: omp_if.end:
1069 // CHECK1-NEXT: ret void
1070 //
1071 //
1072 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
1073 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
1074 // CHECK1-NEXT: entry:
1075 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1076 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1077 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
1078 // CHECK1-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8
1079 // CHECK1-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8
1080 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1081 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1082 // CHECK1-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
1083 // CHECK1-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8
1084 // CHECK1-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8
1085 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8
1086 // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8
1087 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8
1088 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
1089 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
1090 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1091 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1092 // CHECK1-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
1093 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
1094 // CHECK1-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
1095 // CHECK1-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
1096 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
1097 // CHECK1-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
1098 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1099 // CHECK1-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1100 // CHECK1-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
1101 // CHECK1-NEXT: ret void
1102 //
1103 //
1104 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1105 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
1106 // CHECK1-NEXT: entry:
1107 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
1108 // CHECK1-NEXT: ret void
1109 //
1110 //
1111 // CHECK2-LABEL: define {{[^@]+}}@_Z3foossss
1112 // CHECK2-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1113 // CHECK2-NEXT: entry:
1114 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
1115 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
1116 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
1117 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
1118 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
1119 // CHECK2-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8
1120 // CHECK2-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8
1121 // CHECK2-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8
1122 // CHECK2-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
1123 // CHECK2-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8
1124 // CHECK2-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8
1125 // CHECK2-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8
1126 // CHECK2-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8
1127 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8
1128 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8
1129 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8
1130 // CHECK2-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
1131 // CHECK2-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
1132 // CHECK2-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
1133 // CHECK2-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
1134 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2
1135 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16*
1136 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
1137 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_CASTED]], align 8
1138 // CHECK2-NEXT: [[TMP2:%.*]] = load double, double* @Gb, align 8
1139 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double*
1140 // CHECK2-NEXT: store double [[TMP2]], double* [[CONV1]], align 8
1141 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[GB_CASTED]], align 8
1142 // CHECK2-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
1143 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float*
1144 // CHECK2-NEXT: store float [[TMP4]], float* [[CONV2]], align 4
1145 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[SB_CASTED]], align 8
1146 // CHECK2-NEXT: [[TMP6:%.*]] = load double, double* @Gc, align 8
1147 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double*
1148 // CHECK2-NEXT: store double [[TMP6]], double* [[CONV3]], align 8
1149 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[GC_CASTED]], align 8
1150 // CHECK2-NEXT: [[TMP8:%.*]] = load i16, i16* [[C_ADDR]], align 2
1151 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16*
1152 // CHECK2-NEXT: store i16 [[TMP8]], i16* [[CONV4]], align 2
1153 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8
1154 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
1155 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float*
1156 // CHECK2-NEXT: store float [[TMP10]], float* [[CONV5]], align 4
1157 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[SC_CASTED]], align 8
1158 // CHECK2-NEXT: [[TMP12:%.*]] = load i16, i16* [[D_ADDR]], align 2
1159 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16*
1160 // CHECK2-NEXT: store i16 [[TMP12]], i16* [[CONV6]], align 2
1161 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[D_CASTED]], align 8
1162 // CHECK2-NEXT: [[TMP14:%.*]] = load double, double* @Gd, align 8
1163 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double*
1164 // CHECK2-NEXT: store double [[TMP14]], double* [[CONV7]], align 8
1165 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[GD_CASTED]], align 8
1166 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
1167 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float*
1168 // CHECK2-NEXT: store float [[TMP16]], float* [[CONV8]], align 4
1169 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[SD_CASTED]], align 8
1170 // CHECK2-NEXT: [[TMP18:%.*]] = load double, double* @Ga, align 8
1171 // CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP18]], 0.000000e+00
1172 // CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1173 // CHECK2: land.lhs.true:
1174 // CHECK2-NEXT: [[TMP19:%.*]] = load i16, i16* [[A_ADDR]], align 2
1175 // CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP19]] to i32
1176 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
1177 // CHECK2-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
1178 // CHECK2: land.lhs.true11:
1179 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
1180 // CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP20]] to double
1181 // CHECK2-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
1182 // CHECK2-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1183 // CHECK2: omp_if.then:
1184 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1185 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
1186 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP22]], align 8
1187 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1188 // CHECK2-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
1189 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8
1190 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1191 // CHECK2-NEXT: store i8* null, i8** [[TMP25]], align 8
1192 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1193 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1194 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8
1195 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1196 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
1197 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8
1198 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1199 // CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8
1200 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1201 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
1202 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP32]], align 8
1203 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1204 // CHECK2-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
1205 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP34]], align 8
1206 // CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1207 // CHECK2-NEXT: store i8* null, i8** [[TMP35]], align 8
1208 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1209 // CHECK2-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
1210 // CHECK2-NEXT: store i64 [[TMP7]], i64* [[TMP37]], align 8
1211 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1212 // CHECK2-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64*
1213 // CHECK2-NEXT: store i64 [[TMP7]], i64* [[TMP39]], align 8
1214 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1215 // CHECK2-NEXT: store i8* null, i8** [[TMP40]], align 8
1216 // CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1217 // CHECK2-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64*
1218 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP42]], align 8
1219 // CHECK2-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1220 // CHECK2-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64*
1221 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP44]], align 8
1222 // CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1223 // CHECK2-NEXT: store i8* null, i8** [[TMP45]], align 8
1224 // CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
1225 // CHECK2-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64*
1226 // CHECK2-NEXT: store i64 [[TMP11]], i64* [[TMP47]], align 8
1227 // CHECK2-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
1228 // CHECK2-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64*
1229 // CHECK2-NEXT: store i64 [[TMP11]], i64* [[TMP49]], align 8
1230 // CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
1231 // CHECK2-NEXT: store i8* null, i8** [[TMP50]], align 8
1232 // CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
1233 // CHECK2-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
1234 // CHECK2-NEXT: store i64 [[TMP13]], i64* [[TMP52]], align 8
1235 // CHECK2-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
1236 // CHECK2-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*
1237 // CHECK2-NEXT: store i64 [[TMP13]], i64* [[TMP54]], align 8
1238 // CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
1239 // CHECK2-NEXT: store i8* null, i8** [[TMP55]], align 8
1240 // CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
1241 // CHECK2-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to i64*
1242 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP57]], align 8
1243 // CHECK2-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
1244 // CHECK2-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i64*
1245 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP59]], align 8
1246 // CHECK2-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
1247 // CHECK2-NEXT: store i8* null, i8** [[TMP60]], align 8
1248 // CHECK2-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
1249 // CHECK2-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
1250 // CHECK2-NEXT: store i64 [[TMP17]], i64* [[TMP62]], align 8
1251 // CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
1252 // CHECK2-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
1253 // CHECK2-NEXT: store i64 [[TMP17]], i64* [[TMP64]], align 8
1254 // CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
1255 // CHECK2-NEXT: store i8* null, i8** [[TMP65]], align 8
1256 // CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1257 // CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1258 // CHECK2-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.region_id, i32 9, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null)
1259 // CHECK2-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
1260 // CHECK2-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1261 // CHECK2: omp_offload.failed:
1262 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]]) #[[ATTR2:[0-9]+]]
1263 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1264 // CHECK2: omp_offload.cont:
1265 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
1266 // CHECK2: omp_if.else:
1267 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]]) #[[ATTR2]]
1268 // CHECK2-NEXT: br label [[OMP_IF_END]]
1269 // CHECK2: omp_if.end:
1270 // CHECK2-NEXT: [[TMP70:%.*]] = load i16, i16* [[A_ADDR]], align 2
1271 // CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP70]] to i32
1272 // CHECK2-NEXT: [[TMP71:%.*]] = load i16, i16* [[B_ADDR]], align 2
1273 // CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP71]] to i32
1274 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV14]], [[CONV15]]
1275 // CHECK2-NEXT: [[TMP72:%.*]] = load i16, i16* [[C_ADDR]], align 2
1276 // CHECK2-NEXT: [[CONV16:%.*]] = sext i16 [[TMP72]] to i32
1277 // CHECK2-NEXT: [[ADD17:%.*]] = add nsw i32 [[ADD]], [[CONV16]]
1278 // CHECK2-NEXT: [[TMP73:%.*]] = load i16, i16* [[D_ADDR]], align 2
1279 // CHECK2-NEXT: [[CONV18:%.*]] = sext i16 [[TMP73]] to i32
1280 // CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 [[ADD17]], [[CONV18]]
1281 // CHECK2-NEXT: [[TMP74:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
1282 // CHECK2-NEXT: [[CONV20:%.*]] = fptosi float [[TMP74]] to i32
1283 // CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[CONV20]]
1284 // CHECK2-NEXT: [[TMP75:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
1285 // CHECK2-NEXT: [[CONV22:%.*]] = fptosi float [[TMP75]] to i32
1286 // CHECK2-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD21]], [[CONV22]]
1287 // CHECK2-NEXT: [[TMP76:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
1288 // CHECK2-NEXT: [[CONV24:%.*]] = fptosi float [[TMP76]] to i32
1289 // CHECK2-NEXT: [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[CONV24]]
1290 // CHECK2-NEXT: [[TMP77:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
1291 // CHECK2-NEXT: [[CONV26:%.*]] = fptosi float [[TMP77]] to i32
1292 // CHECK2-NEXT: [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[CONV26]]
1293 // CHECK2-NEXT: ret i32 [[ADD27]]
1294 //
1295 //
1296 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49
1297 // CHECK2-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1:[0-9]+]] {
1298 // CHECK2-NEXT: entry:
1299 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1300 // CHECK2-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8
1301 // CHECK2-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8
1302 // CHECK2-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8
1303 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
1304 // CHECK2-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8
1305 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8
1306 // CHECK2-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8
1307 // CHECK2-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8
1308 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1309 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1310 // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1311 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1312 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
1313 // CHECK2-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8
1314 // CHECK2-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8
1315 // CHECK2-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8
1316 // CHECK2-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
1317 // CHECK2-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8
1318 // CHECK2-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8
1319 // CHECK2-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8
1320 // CHECK2-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8
1321 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16*
1322 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
1323 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
1324 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
1325 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
1326 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
1327 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
1328 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
1329 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
1330 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
1331 // CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
1332 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
1333 // CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
1334 // CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
1335 // CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
1336 // CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
1337 // CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
1338 // CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
1339 // CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
1340 // CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
1341 // CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
1342 // CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
1343 // CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
1344 // CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
1345 // CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1346 // CHECK2: land.lhs.true:
1347 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
1348 // CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
1349 // CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
1350 // CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
1351 // CHECK2: land.lhs.true17:
1352 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
1353 // CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
1354 // CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
1355 // CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1356 // CHECK2: omp_if.then:
1357 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
1358 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
1359 // CHECK2: omp_if.else:
1360 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1361 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1362 // CHECK2-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]]
1363 // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1364 // CHECK2-NEXT: br label [[OMP_IF_END]]
1365 // CHECK2: omp_if.end:
1366 // CHECK2-NEXT: ret void
1367 //
1368 //
1369 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
1370 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
1371 // CHECK2-NEXT: entry:
1372 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1373 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1374 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
1375 // CHECK2-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8
1376 // CHECK2-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8
1377 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1378 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1379 // CHECK2-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
1380 // CHECK2-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8
1381 // CHECK2-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8
1382 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8
1383 // CHECK2-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8
1384 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8
1385 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
1386 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
1387 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1388 // CHECK2-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1389 // CHECK2-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
1390 // CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
1391 // CHECK2-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
1392 // CHECK2-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
1393 // CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
1394 // CHECK2-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
1395 // CHECK2-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1396 // CHECK2-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1397 // CHECK2-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
1398 // CHECK2-NEXT: ret void
1399 //
1400 //
1401 // CHECK2-LABEL: define {{[^@]+}}@_Z3barssss
1402 // CHECK2-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] {
1403 // CHECK2-NEXT: entry:
1404 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
1405 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
1406 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
1407 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
1408 // CHECK2-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
1409 // CHECK2-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
1410 // CHECK2-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
1411 // CHECK2-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
1412 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
1413 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
1414 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
1415 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
1416 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
1417 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
1418 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
1419 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
1420 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
1421 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
1422 // CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
1423 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
1424 // CHECK2-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
1425 // CHECK2-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
1426 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
1427 // CHECK2-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
1428 // CHECK2-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
1429 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
1430 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
1431 // CHECK2-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
1432 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
1433 // CHECK2-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
1434 // CHECK2-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
1435 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
1436 // CHECK2-NEXT: ret i32 [[ADD13]]
1437 //
1438 //
1439 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
1440 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
1441 // CHECK2-NEXT: entry:
1442 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1443 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1444 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 8
1445 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 8
1446 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
1447 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
1448 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
1449 // CHECK2-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8
1450 // CHECK2-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8
1451 // CHECK2-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8
1452 // CHECK2-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
1453 // CHECK2-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8
1454 // CHECK2-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8
1455 // CHECK2-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8
1456 // CHECK2-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8
1457 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8
1458 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8
1459 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8
1460 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1461 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1462 // CHECK2-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 8
1463 // CHECK2-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 8
1464 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
1465 // CHECK2-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
1466 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 8
1467 // CHECK2-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 8
1468 // CHECK2-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1469 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 8
1470 // CHECK2-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
1471 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16*
1472 // CHECK2-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
1473 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
1474 // CHECK2-NEXT: [[TMP6:%.*]] = load double, double* @Gb, align 8
1475 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double*
1476 // CHECK2-NEXT: store double [[TMP6]], double* [[CONV1]], align 8
1477 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[GB_CASTED]], align 8
1478 // CHECK2-NEXT: [[TMP8:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
1479 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float*
1480 // CHECK2-NEXT: store float [[TMP8]], float* [[CONV2]], align 4
1481 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[SB_CASTED]], align 8
1482 // CHECK2-NEXT: [[TMP10:%.*]] = load double, double* @Gc, align 8
1483 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double*
1484 // CHECK2-NEXT: store double [[TMP10]], double* [[CONV3]], align 8
1485 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[GC_CASTED]], align 8
1486 // CHECK2-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP2]], align 2
1487 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16*
1488 // CHECK2-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
1489 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[C_CASTED]], align 8
1490 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
1491 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float*
1492 // CHECK2-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
1493 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[SC_CASTED]], align 8
1494 // CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[TMP3]], align 2
1495 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16*
1496 // CHECK2-NEXT: store i16 [[TMP16]], i16* [[CONV6]], align 2
1497 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[D_CASTED]], align 8
1498 // CHECK2-NEXT: [[TMP18:%.*]] = load double, double* @Gd, align 8
1499 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double*
1500 // CHECK2-NEXT: store double [[TMP18]], double* [[CONV7]], align 8
1501 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[GD_CASTED]], align 8
1502 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
1503 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float*
1504 // CHECK2-NEXT: store float [[TMP20]], float* [[CONV8]], align 4
1505 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SD_CASTED]], align 8
1506 // CHECK2-NEXT: [[TMP22:%.*]] = load double, double* @Ga, align 8
1507 // CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP22]], 0.000000e+00
1508 // CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1509 // CHECK2: land.lhs.true:
1510 // CHECK2-NEXT: [[TMP23:%.*]] = load i16, i16* [[TMP0]], align 2
1511 // CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP23]] to i32
1512 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
1513 // CHECK2-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
1514 // CHECK2: land.lhs.true11:
1515 // CHECK2-NEXT: [[TMP24:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
1516 // CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP24]] to double
1517 // CHECK2-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
1518 // CHECK2-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1519 // CHECK2: omp_if.then:
1520 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1521 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
1522 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP26]], align 8
1523 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1524 // CHECK2-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
1525 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP28]], align 8
1526 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1527 // CHECK2-NEXT: store i8* null, i8** [[TMP29]], align 8
1528 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1529 // CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
1530 // CHECK2-NEXT: store i64 [[TMP7]], i64* [[TMP31]], align 8
1531 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1532 // CHECK2-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64*
1533 // CHECK2-NEXT: store i64 [[TMP7]], i64* [[TMP33]], align 8
1534 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1535 // CHECK2-NEXT: store i8* null, i8** [[TMP34]], align 8
1536 // CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1537 // CHECK2-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
1538 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP36]], align 8
1539 // CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1540 // CHECK2-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64*
1541 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
1542 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1543 // CHECK2-NEXT: store i8* null, i8** [[TMP39]], align 8
1544 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1545 // CHECK2-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
1546 // CHECK2-NEXT: store i64 [[TMP11]], i64* [[TMP41]], align 8
1547 // CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1548 // CHECK2-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
1549 // CHECK2-NEXT: store i64 [[TMP11]], i64* [[TMP43]], align 8
1550 // CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1551 // CHECK2-NEXT: store i8* null, i8** [[TMP44]], align 8
1552 // CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1553 // CHECK2-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
1554 // CHECK2-NEXT: store i64 [[TMP13]], i64* [[TMP46]], align 8
1555 // CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1556 // CHECK2-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
1557 // CHECK2-NEXT: store i64 [[TMP13]], i64* [[TMP48]], align 8
1558 // CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1559 // CHECK2-NEXT: store i8* null, i8** [[TMP49]], align 8
1560 // CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
1561 // CHECK2-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
1562 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP51]], align 8
1563 // CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
1564 // CHECK2-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
1565 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP53]], align 8
1566 // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
1567 // CHECK2-NEXT: store i8* null, i8** [[TMP54]], align 8
1568 // CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
1569 // CHECK2-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i64*
1570 // CHECK2-NEXT: store i64 [[TMP17]], i64* [[TMP56]], align 8
1571 // CHECK2-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
1572 // CHECK2-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64*
1573 // CHECK2-NEXT: store i64 [[TMP17]], i64* [[TMP58]], align 8
1574 // CHECK2-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
1575 // CHECK2-NEXT: store i8* null, i8** [[TMP59]], align 8
1576 // CHECK2-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
1577 // CHECK2-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64*
1578 // CHECK2-NEXT: store i64 [[TMP19]], i64* [[TMP61]], align 8
1579 // CHECK2-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
1580 // CHECK2-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64*
1581 // CHECK2-NEXT: store i64 [[TMP19]], i64* [[TMP63]], align 8
1582 // CHECK2-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
1583 // CHECK2-NEXT: store i8* null, i8** [[TMP64]], align 8
1584 // CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
1585 // CHECK2-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to i64*
1586 // CHECK2-NEXT: store i64 [[TMP21]], i64* [[TMP66]], align 8
1587 // CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
1588 // CHECK2-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i64*
1589 // CHECK2-NEXT: store i64 [[TMP21]], i64* [[TMP68]], align 8
1590 // CHECK2-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
1591 // CHECK2-NEXT: store i8* null, i8** [[TMP69]], align 8
1592 // CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1593 // CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1594 // CHECK2-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.region_id, i32 9, i8** [[TMP70]], i8** [[TMP71]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null)
1595 // CHECK2-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0
1596 // CHECK2-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1597 // CHECK2: omp_offload.failed:
1598 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
1599 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1600 // CHECK2: omp_offload.cont:
1601 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
1602 // CHECK2: omp_if.else:
1603 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
1604 // CHECK2-NEXT: br label [[OMP_IF_END]]
1605 // CHECK2: omp_if.end:
1606 // CHECK2-NEXT: ret void
1607 //
1608 //
1609 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94
1610 // CHECK2-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1]] {
1611 // CHECK2-NEXT: entry:
1612 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1613 // CHECK2-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8
1614 // CHECK2-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8
1615 // CHECK2-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8
1616 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
1617 // CHECK2-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8
1618 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8
1619 // CHECK2-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8
1620 // CHECK2-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8
1621 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1622 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1623 // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1624 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1625 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
1626 // CHECK2-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8
1627 // CHECK2-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8
1628 // CHECK2-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8
1629 // CHECK2-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
1630 // CHECK2-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8
1631 // CHECK2-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8
1632 // CHECK2-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8
1633 // CHECK2-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8
1634 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16*
1635 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
1636 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
1637 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
1638 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
1639 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
1640 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
1641 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
1642 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
1643 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
1644 // CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
1645 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
1646 // CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
1647 // CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
1648 // CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
1649 // CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
1650 // CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
1651 // CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
1652 // CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
1653 // CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
1654 // CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
1655 // CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
1656 // CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
1657 // CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
1658 // CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1659 // CHECK2: land.lhs.true:
1660 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
1661 // CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
1662 // CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
1663 // CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
1664 // CHECK2: land.lhs.true17:
1665 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
1666 // CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
1667 // CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
1668 // CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1669 // CHECK2: omp_if.then:
1670 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
1671 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
1672 // CHECK2: omp_if.else:
1673 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1674 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1675 // CHECK2-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]]
1676 // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1677 // CHECK2-NEXT: br label [[OMP_IF_END]]
1678 // CHECK2: omp_if.end:
1679 // CHECK2-NEXT: ret void
1680 //
1681 //
1682 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
1683 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
1684 // CHECK2-NEXT: entry:
1685 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1686 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1687 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
1688 // CHECK2-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8
1689 // CHECK2-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8
1690 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1691 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1692 // CHECK2-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
1693 // CHECK2-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8
1694 // CHECK2-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8
1695 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8
1696 // CHECK2-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8
1697 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8
1698 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
1699 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
1700 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1701 // CHECK2-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1702 // CHECK2-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
1703 // CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
1704 // CHECK2-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
1705 // CHECK2-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
1706 // CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
1707 // CHECK2-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
1708 // CHECK2-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1709 // CHECK2-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1710 // CHECK2-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
1711 // CHECK2-NEXT: ret void
1712 //
1713 //
1714 // CHECK2-LABEL: define {{[^@]+}}@_Z5tbar2ssss
1715 // CHECK2-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] {
1716 // CHECK2-NEXT: entry:
1717 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
1718 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
1719 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
1720 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
1721 // CHECK2-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
1722 // CHECK2-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
1723 // CHECK2-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
1724 // CHECK2-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
1725 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
1726 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
1727 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
1728 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
1729 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]])
1730 // CHECK2-NEXT: ret i32 [[CALL]]
1731 //
1732 //
1733 // CHECK2-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_
1734 // CHECK2-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat {
1735 // CHECK2-NEXT: entry:
1736 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
1737 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
1738 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
1739 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
1740 // CHECK2-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
1741 // CHECK2-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
1742 // CHECK2-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
1743 // CHECK2-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
1744 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
1745 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
1746 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
1747 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
1748 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
1749 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
1750 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
1751 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
1752 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
1753 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
1754 // CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
1755 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
1756 // CHECK2-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
1757 // CHECK2-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
1758 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
1759 // CHECK2-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
1760 // CHECK2-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
1761 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
1762 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
1763 // CHECK2-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
1764 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
1765 // CHECK2-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
1766 // CHECK2-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
1767 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
1768 // CHECK2-NEXT: ret i32 [[ADD13]]
1769 //
1770 //
1771 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5
1772 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
1773 // CHECK2-NEXT: entry:
1774 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1775 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1776 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 8
1777 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 8
1778 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
1779 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
1780 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
1781 // CHECK2-NEXT: [[GB_CASTED:%.*]] = alloca i64, align 8
1782 // CHECK2-NEXT: [[SB_CASTED:%.*]] = alloca i64, align 8
1783 // CHECK2-NEXT: [[GC_CASTED:%.*]] = alloca i64, align 8
1784 // CHECK2-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8
1785 // CHECK2-NEXT: [[SC_CASTED:%.*]] = alloca i64, align 8
1786 // CHECK2-NEXT: [[D_CASTED:%.*]] = alloca i64, align 8
1787 // CHECK2-NEXT: [[GD_CASTED:%.*]] = alloca i64, align 8
1788 // CHECK2-NEXT: [[SD_CASTED:%.*]] = alloca i64, align 8
1789 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 8
1790 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 8
1791 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 8
1792 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1793 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1794 // CHECK2-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 8
1795 // CHECK2-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 8
1796 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
1797 // CHECK2-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
1798 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 8
1799 // CHECK2-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 8
1800 // CHECK2-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1801 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 8
1802 // CHECK2-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
1803 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i16*
1804 // CHECK2-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
1805 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
1806 // CHECK2-NEXT: [[TMP6:%.*]] = load double, double* @Gb, align 8
1807 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_CASTED]] to double*
1808 // CHECK2-NEXT: store double [[TMP6]], double* [[CONV1]], align 8
1809 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[GB_CASTED]], align 8
1810 // CHECK2-NEXT: [[TMP8:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
1811 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_CASTED]] to float*
1812 // CHECK2-NEXT: store float [[TMP8]], float* [[CONV2]], align 4
1813 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[SB_CASTED]], align 8
1814 // CHECK2-NEXT: [[TMP10:%.*]] = load double, double* @Gc, align 8
1815 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_CASTED]] to double*
1816 // CHECK2-NEXT: store double [[TMP10]], double* [[CONV3]], align 8
1817 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[GC_CASTED]], align 8
1818 // CHECK2-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP2]], align 2
1819 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_CASTED]] to i16*
1820 // CHECK2-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
1821 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[C_CASTED]], align 8
1822 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
1823 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_CASTED]] to float*
1824 // CHECK2-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
1825 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[SC_CASTED]], align 8
1826 // CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[TMP3]], align 2
1827 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_CASTED]] to i16*
1828 // CHECK2-NEXT: store i16 [[TMP16]], i16* [[CONV6]], align 2
1829 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[D_CASTED]], align 8
1830 // CHECK2-NEXT: [[TMP18:%.*]] = load double, double* @Gd, align 8
1831 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_CASTED]] to double*
1832 // CHECK2-NEXT: store double [[TMP18]], double* [[CONV7]], align 8
1833 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[GD_CASTED]], align 8
1834 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
1835 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_CASTED]] to float*
1836 // CHECK2-NEXT: store float [[TMP20]], float* [[CONV8]], align 4
1837 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SD_CASTED]], align 8
1838 // CHECK2-NEXT: [[TMP22:%.*]] = load double, double* @Ga, align 8
1839 // CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP22]], 0.000000e+00
1840 // CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1841 // CHECK2: land.lhs.true:
1842 // CHECK2-NEXT: [[TMP23:%.*]] = load i16, i16* [[TMP0]], align 2
1843 // CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP23]] to i32
1844 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
1845 // CHECK2-NEXT: br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
1846 // CHECK2: land.lhs.true11:
1847 // CHECK2-NEXT: [[TMP24:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
1848 // CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP24]] to double
1849 // CHECK2-NEXT: [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
1850 // CHECK2-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1851 // CHECK2: omp_if.then:
1852 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1853 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
1854 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP26]], align 8
1855 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1856 // CHECK2-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
1857 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP28]], align 8
1858 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1859 // CHECK2-NEXT: store i8* null, i8** [[TMP29]], align 8
1860 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1861 // CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
1862 // CHECK2-NEXT: store i64 [[TMP7]], i64* [[TMP31]], align 8
1863 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1864 // CHECK2-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i64*
1865 // CHECK2-NEXT: store i64 [[TMP7]], i64* [[TMP33]], align 8
1866 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1867 // CHECK2-NEXT: store i8* null, i8** [[TMP34]], align 8
1868 // CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1869 // CHECK2-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
1870 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP36]], align 8
1871 // CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1872 // CHECK2-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64*
1873 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8
1874 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1875 // CHECK2-NEXT: store i8* null, i8** [[TMP39]], align 8
1876 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1877 // CHECK2-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
1878 // CHECK2-NEXT: store i64 [[TMP11]], i64* [[TMP41]], align 8
1879 // CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1880 // CHECK2-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
1881 // CHECK2-NEXT: store i64 [[TMP11]], i64* [[TMP43]], align 8
1882 // CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1883 // CHECK2-NEXT: store i8* null, i8** [[TMP44]], align 8
1884 // CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1885 // CHECK2-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
1886 // CHECK2-NEXT: store i64 [[TMP13]], i64* [[TMP46]], align 8
1887 // CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1888 // CHECK2-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
1889 // CHECK2-NEXT: store i64 [[TMP13]], i64* [[TMP48]], align 8
1890 // CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1891 // CHECK2-NEXT: store i8* null, i8** [[TMP49]], align 8
1892 // CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
1893 // CHECK2-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
1894 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP51]], align 8
1895 // CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
1896 // CHECK2-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
1897 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP53]], align 8
1898 // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
1899 // CHECK2-NEXT: store i8* null, i8** [[TMP54]], align 8
1900 // CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
1901 // CHECK2-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i64*
1902 // CHECK2-NEXT: store i64 [[TMP17]], i64* [[TMP56]], align 8
1903 // CHECK2-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
1904 // CHECK2-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64*
1905 // CHECK2-NEXT: store i64 [[TMP17]], i64* [[TMP58]], align 8
1906 // CHECK2-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
1907 // CHECK2-NEXT: store i8* null, i8** [[TMP59]], align 8
1908 // CHECK2-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
1909 // CHECK2-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64*
1910 // CHECK2-NEXT: store i64 [[TMP19]], i64* [[TMP61]], align 8
1911 // CHECK2-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
1912 // CHECK2-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64*
1913 // CHECK2-NEXT: store i64 [[TMP19]], i64* [[TMP63]], align 8
1914 // CHECK2-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
1915 // CHECK2-NEXT: store i8* null, i8** [[TMP64]], align 8
1916 // CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
1917 // CHECK2-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to i64*
1918 // CHECK2-NEXT: store i64 [[TMP21]], i64* [[TMP66]], align 8
1919 // CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
1920 // CHECK2-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i64*
1921 // CHECK2-NEXT: store i64 [[TMP21]], i64* [[TMP68]], align 8
1922 // CHECK2-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
1923 // CHECK2-NEXT: store i8* null, i8** [[TMP69]], align 8
1924 // CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1925 // CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1926 // CHECK2-NEXT: [[TMP72:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.region_id, i32 9, i8** [[TMP70]], i8** [[TMP71]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null)
1927 // CHECK2-NEXT: [[TMP73:%.*]] = icmp ne i32 [[TMP72]], 0
1928 // CHECK2-NEXT: br i1 [[TMP73]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1929 // CHECK2: omp_offload.failed:
1930 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
1931 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1932 // CHECK2: omp_offload.cont:
1933 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
1934 // CHECK2: omp_if.else:
1935 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
1936 // CHECK2-NEXT: br label [[OMP_IF_END]]
1937 // CHECK2: omp_if.end:
1938 // CHECK2-NEXT: ret void
1939 //
1940 //
1941 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145
1942 // CHECK2-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1]] {
1943 // CHECK2-NEXT: entry:
1944 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1945 // CHECK2-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8
1946 // CHECK2-NEXT: [[SB_ADDR:%.*]] = alloca i64, align 8
1947 // CHECK2-NEXT: [[GC_ADDR:%.*]] = alloca i64, align 8
1948 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
1949 // CHECK2-NEXT: [[SC_ADDR:%.*]] = alloca i64, align 8
1950 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8
1951 // CHECK2-NEXT: [[GD_ADDR:%.*]] = alloca i64, align 8
1952 // CHECK2-NEXT: [[SD_ADDR:%.*]] = alloca i64, align 8
1953 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1954 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1955 // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1956 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1957 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
1958 // CHECK2-NEXT: store i64 [[GB]], i64* [[GB_ADDR]], align 8
1959 // CHECK2-NEXT: store i64 [[SB]], i64* [[SB_ADDR]], align 8
1960 // CHECK2-NEXT: store i64 [[GC]], i64* [[GC_ADDR]], align 8
1961 // CHECK2-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8
1962 // CHECK2-NEXT: store i64 [[SC]], i64* [[SC_ADDR]], align 8
1963 // CHECK2-NEXT: store i64 [[D]], i64* [[D_ADDR]], align 8
1964 // CHECK2-NEXT: store i64 [[GD]], i64* [[GD_ADDR]], align 8
1965 // CHECK2-NEXT: store i64 [[SD]], i64* [[SD_ADDR]], align 8
1966 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i16*
1967 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[GB_ADDR]] to double*
1968 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SB_ADDR]] to float*
1969 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[GC_ADDR]] to double*
1970 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[C_ADDR]] to i16*
1971 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SC_ADDR]] to float*
1972 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[D_ADDR]] to i16*
1973 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[GD_ADDR]] to double*
1974 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[SD_ADDR]] to float*
1975 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 8
1976 // CHECK2-NEXT: [[CONV9:%.*]] = sext i16 [[TMP1]] to i32
1977 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
1978 // CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
1979 // CHECK2-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 8
1980 // CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[CONV1]], align 8
1981 // CHECK2-NEXT: [[ADD11:%.*]] = fadd double [[TMP2]], 1.000000e+00
1982 // CHECK2-NEXT: store double [[ADD11]], double* [[CONV1]], align 8
1983 // CHECK2-NEXT: [[TMP3:%.*]] = load float, float* [[CONV2]], align 8
1984 // CHECK2-NEXT: [[CONV12:%.*]] = fpext float [[TMP3]] to double
1985 // CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
1986 // CHECK2-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
1987 // CHECK2-NEXT: store float [[CONV14]], float* [[CONV2]], align 8
1988 // CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[CONV3]], align 8
1989 // CHECK2-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
1990 // CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1991 // CHECK2: land.lhs.true:
1992 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV4]], align 8
1993 // CHECK2-NEXT: [[CONV15:%.*]] = sext i16 [[TMP5]] to i32
1994 // CHECK2-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
1995 // CHECK2-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
1996 // CHECK2: land.lhs.true17:
1997 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[CONV5]], align 8
1998 // CHECK2-NEXT: [[CONV18:%.*]] = fpext float [[TMP6]] to double
1999 // CHECK2-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
2000 // CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
2001 // CHECK2: omp_if.then:
2002 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]])
2003 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
2004 // CHECK2: omp_if.else:
2005 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2006 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2007 // CHECK2-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV6]], double* [[CONV7]], float* [[CONV8]]) #[[ATTR2]]
2008 // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2009 // CHECK2-NEXT: br label [[OMP_IF_END]]
2010 // CHECK2: omp_if.end:
2011 // CHECK2-NEXT: ret void
2012 //
2013 //
2014 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6
2015 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
2016 // CHECK2-NEXT: entry:
2017 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2018 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2019 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 8
2020 // CHECK2-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 8
2021 // CHECK2-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 8
2022 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2023 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2024 // CHECK2-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 8
2025 // CHECK2-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 8
2026 // CHECK2-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 8
2027 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 8
2028 // CHECK2-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 8
2029 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 8
2030 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
2031 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
2032 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
2033 // CHECK2-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
2034 // CHECK2-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
2035 // CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
2036 // CHECK2-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
2037 // CHECK2-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
2038 // CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
2039 // CHECK2-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
2040 // CHECK2-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
2041 // CHECK2-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
2042 // CHECK2-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
2043 // CHECK2-NEXT: ret void
2044 //
2045 //
2046 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2047 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
2048 // CHECK2-NEXT: entry:
2049 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
2050 // CHECK2-NEXT: ret void
2051 //
2052 //
2053 // CHECK3-LABEL: define {{[^@]+}}@_Z3foossss
2054 // CHECK3-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] {
2055 // CHECK3-NEXT: entry:
2056 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
2057 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
2058 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
2059 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
2060 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
2061 // CHECK3-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4
2062 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
2063 // CHECK3-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4
2064 // CHECK3-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4
2065 // CHECK3-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4
2066 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4
2067 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4
2068 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4
2069 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
2070 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
2071 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
2072 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
2073 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2
2074 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
2075 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
2076 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_CASTED]], align 4
2077 // CHECK3-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
2078 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float*
2079 // CHECK3-NEXT: store float [[TMP2]], float* [[CONV1]], align 4
2080 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SB_CASTED]], align 4
2081 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[C_ADDR]], align 2
2082 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16*
2083 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2
2084 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[C_CASTED]], align 4
2085 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
2086 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float*
2087 // CHECK3-NEXT: store float [[TMP6]], float* [[CONV3]], align 4
2088 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[SC_CASTED]], align 4
2089 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[D_ADDR]], align 2
2090 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16*
2091 // CHECK3-NEXT: store i16 [[TMP8]], i16* [[CONV4]], align 2
2092 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[D_CASTED]], align 4
2093 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
2094 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float*
2095 // CHECK3-NEXT: store float [[TMP10]], float* [[CONV5]], align 4
2096 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[SD_CASTED]], align 4
2097 // CHECK3-NEXT: [[TMP12:%.*]] = load double, double* @Ga, align 8
2098 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP12]], 0.000000e+00
2099 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
2100 // CHECK3: land.lhs.true:
2101 // CHECK3-NEXT: [[TMP13:%.*]] = load i16, i16* [[A_ADDR]], align 2
2102 // CHECK3-NEXT: [[CONV6:%.*]] = sext i16 [[TMP13]] to i32
2103 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
2104 // CHECK3-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
2105 // CHECK3: land.lhs.true8:
2106 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
2107 // CHECK3-NEXT: [[CONV9:%.*]] = fpext float [[TMP14]] to double
2108 // CHECK3-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
2109 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
2110 // CHECK3: omp_if.then:
2111 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2112 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
2113 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP16]], align 4
2114 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2115 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
2116 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP18]], align 4
2117 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2118 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4
2119 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2120 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double**
2121 // CHECK3-NEXT: store double* @Gb, double** [[TMP21]], align 4
2122 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2123 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double**
2124 // CHECK3-NEXT: store double* @Gb, double** [[TMP23]], align 4
2125 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2126 // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4
2127 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2128 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
2129 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP26]], align 4
2130 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2131 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
2132 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP28]], align 4
2133 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2134 // CHECK3-NEXT: store i8* null, i8** [[TMP29]], align 4
2135 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2136 // CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to double**
2137 // CHECK3-NEXT: store double* @Gc, double** [[TMP31]], align 4
2138 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2139 // CHECK3-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
2140 // CHECK3-NEXT: store double* @Gc, double** [[TMP33]], align 4
2141 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2142 // CHECK3-NEXT: store i8* null, i8** [[TMP34]], align 4
2143 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2144 // CHECK3-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32*
2145 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP36]], align 4
2146 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2147 // CHECK3-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32*
2148 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP38]], align 4
2149 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
2150 // CHECK3-NEXT: store i8* null, i8** [[TMP39]], align 4
2151 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
2152 // CHECK3-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32*
2153 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP41]], align 4
2154 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
2155 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32*
2156 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP43]], align 4
2157 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
2158 // CHECK3-NEXT: store i8* null, i8** [[TMP44]], align 4
2159 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
2160 // CHECK3-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
2161 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP46]], align 4
2162 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
2163 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32*
2164 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP48]], align 4
2165 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
2166 // CHECK3-NEXT: store i8* null, i8** [[TMP49]], align 4
2167 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
2168 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double**
2169 // CHECK3-NEXT: store double* @Gd, double** [[TMP51]], align 4
2170 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
2171 // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double**
2172 // CHECK3-NEXT: store double* @Gd, double** [[TMP53]], align 4
2173 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
2174 // CHECK3-NEXT: store i8* null, i8** [[TMP54]], align 4
2175 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
2176 // CHECK3-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32*
2177 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP56]], align 4
2178 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
2179 // CHECK3-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32*
2180 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP58]], align 4
2181 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
2182 // CHECK3-NEXT: store i8* null, i8** [[TMP59]], align 4
2183 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2184 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2185 // CHECK3-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.region_id, i32 9, i8** [[TMP60]], i8** [[TMP61]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null)
2186 // CHECK3-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0
2187 // CHECK3-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2188 // CHECK3: omp_offload.failed:
2189 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i32 [[TMP1]], double* @Gb, i32 [[TMP3]], double* @Gc, i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP9]], double* @Gd, i32 [[TMP11]]) #[[ATTR2:[0-9]+]]
2190 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2191 // CHECK3: omp_offload.cont:
2192 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
2193 // CHECK3: omp_if.else:
2194 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i32 [[TMP1]], double* @Gb, i32 [[TMP3]], double* @Gc, i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP9]], double* @Gd, i32 [[TMP11]]) #[[ATTR2]]
2195 // CHECK3-NEXT: br label [[OMP_IF_END]]
2196 // CHECK3: omp_if.end:
2197 // CHECK3-NEXT: [[TMP64:%.*]] = load i16, i16* [[A_ADDR]], align 2
2198 // CHECK3-NEXT: [[CONV11:%.*]] = sext i16 [[TMP64]] to i32
2199 // CHECK3-NEXT: [[TMP65:%.*]] = load i16, i16* [[B_ADDR]], align 2
2200 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP65]] to i32
2201 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV11]], [[CONV12]]
2202 // CHECK3-NEXT: [[TMP66:%.*]] = load i16, i16* [[C_ADDR]], align 2
2203 // CHECK3-NEXT: [[CONV13:%.*]] = sext i16 [[TMP66]] to i32
2204 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CONV13]]
2205 // CHECK3-NEXT: [[TMP67:%.*]] = load i16, i16* [[D_ADDR]], align 2
2206 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP67]] to i32
2207 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CONV15]]
2208 // CHECK3-NEXT: [[TMP68:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
2209 // CHECK3-NEXT: [[CONV17:%.*]] = fptosi float [[TMP68]] to i32
2210 // CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[ADD16]], [[CONV17]]
2211 // CHECK3-NEXT: [[TMP69:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
2212 // CHECK3-NEXT: [[CONV19:%.*]] = fptosi float [[TMP69]] to i32
2213 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[ADD18]], [[CONV19]]
2214 // CHECK3-NEXT: [[TMP70:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
2215 // CHECK3-NEXT: [[CONV21:%.*]] = fptosi float [[TMP70]] to i32
2216 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[ADD20]], [[CONV21]]
2217 // CHECK3-NEXT: [[TMP71:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
2218 // CHECK3-NEXT: [[CONV23:%.*]] = fptosi float [[TMP71]] to i32
2219 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[ADD22]], [[CONV23]]
2220 // CHECK3-NEXT: ret i32 [[ADD24]]
2221 //
2222 //
2223 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49
2224 // CHECK3-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1:[0-9]+]] {
2225 // CHECK3-NEXT: entry:
2226 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
2227 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4
2228 // CHECK3-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4
2229 // CHECK3-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4
2230 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
2231 // CHECK3-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4
2232 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4
2233 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
2234 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4
2235 // CHECK3-NEXT: [[GB6:%.*]] = alloca double, align 8
2236 // CHECK3-NEXT: [[GC7:%.*]] = alloca double, align 8
2237 // CHECK3-NEXT: [[GD8:%.*]] = alloca double, align 8
2238 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2239 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2240 // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2241 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2242 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
2243 // CHECK3-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4
2244 // CHECK3-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4
2245 // CHECK3-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4
2246 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
2247 // CHECK3-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4
2248 // CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
2249 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
2250 // CHECK3-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4
2251 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
2252 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4
2253 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float*
2254 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4
2255 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16*
2256 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float*
2257 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16*
2258 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
2259 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
2260 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
2261 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8
2262 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
2263 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
2264 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
2265 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
2266 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
2267 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
2268 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
2269 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
2270 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
2271 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
2272 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
2273 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
2274 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
2275 // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
2276 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
2277 // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
2278 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
2279 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
2280 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
2281 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
2282 // CHECK3: land.lhs.true:
2283 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
2284 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
2285 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
2286 // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
2287 // CHECK3: land.lhs.true17:
2288 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
2289 // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
2290 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
2291 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
2292 // CHECK3: omp_if.then:
2293 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]])
2294 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
2295 // CHECK3: omp_if.else:
2296 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2297 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2298 // CHECK3-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]]
2299 // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2300 // CHECK3-NEXT: br label [[OMP_IF_END]]
2301 // CHECK3: omp_if.end:
2302 // CHECK3-NEXT: ret void
2303 //
2304 //
2305 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
2306 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
2307 // CHECK3-NEXT: entry:
2308 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2309 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2310 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
2311 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
2312 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4
2313 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2314 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2315 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
2316 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
2317 // CHECK3-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4
2318 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4
2319 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4
2320 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4
2321 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
2322 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
2323 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
2324 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
2325 // CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
2326 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
2327 // CHECK3-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
2328 // CHECK3-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
2329 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
2330 // CHECK3-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
2331 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
2332 // CHECK3-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
2333 // CHECK3-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
2334 // CHECK3-NEXT: ret void
2335 //
2336 //
2337 // CHECK3-LABEL: define {{[^@]+}}@_Z3barssss
2338 // CHECK3-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] {
2339 // CHECK3-NEXT: entry:
2340 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
2341 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
2342 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
2343 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
2344 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
2345 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
2346 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
2347 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
2348 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
2349 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
2350 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
2351 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
2352 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
2353 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
2354 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
2355 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
2356 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
2357 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
2358 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
2359 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
2360 // CHECK3-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
2361 // CHECK3-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
2362 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
2363 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
2364 // CHECK3-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
2365 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
2366 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
2367 // CHECK3-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
2368 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
2369 // CHECK3-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
2370 // CHECK3-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
2371 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
2372 // CHECK3-NEXT: ret i32 [[ADD13]]
2373 //
2374 //
2375 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
2376 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
2377 // CHECK3-NEXT: entry:
2378 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2379 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2380 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 4
2381 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 4
2382 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
2383 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
2384 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
2385 // CHECK3-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4
2386 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
2387 // CHECK3-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4
2388 // CHECK3-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4
2389 // CHECK3-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4
2390 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4
2391 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4
2392 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4
2393 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2394 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2395 // CHECK3-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 4
2396 // CHECK3-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 4
2397 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
2398 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
2399 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 4
2400 // CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 4
2401 // CHECK3-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 4
2402 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 4
2403 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
2404 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
2405 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
2406 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
2407 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
2408 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float*
2409 // CHECK3-NEXT: store float [[TMP6]], float* [[CONV1]], align 4
2410 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[SB_CASTED]], align 4
2411 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[TMP2]], align 2
2412 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16*
2413 // CHECK3-NEXT: store i16 [[TMP8]], i16* [[CONV2]], align 2
2414 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4
2415 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
2416 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float*
2417 // CHECK3-NEXT: store float [[TMP10]], float* [[CONV3]], align 4
2418 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[SC_CASTED]], align 4
2419 // CHECK3-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP3]], align 2
2420 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16*
2421 // CHECK3-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
2422 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[D_CASTED]], align 4
2423 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
2424 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float*
2425 // CHECK3-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
2426 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[SD_CASTED]], align 4
2427 // CHECK3-NEXT: [[TMP16:%.*]] = load double, double* @Ga, align 8
2428 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP16]], 0.000000e+00
2429 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
2430 // CHECK3: land.lhs.true:
2431 // CHECK3-NEXT: [[TMP17:%.*]] = load i16, i16* [[TMP0]], align 2
2432 // CHECK3-NEXT: [[CONV6:%.*]] = sext i16 [[TMP17]] to i32
2433 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
2434 // CHECK3-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
2435 // CHECK3: land.lhs.true8:
2436 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
2437 // CHECK3-NEXT: [[CONV9:%.*]] = fpext float [[TMP18]] to double
2438 // CHECK3-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
2439 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
2440 // CHECK3: omp_if.then:
2441 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2442 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
2443 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
2444 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2445 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
2446 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4
2447 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2448 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
2449 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2450 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to double**
2451 // CHECK3-NEXT: store double* @Gb, double** [[TMP25]], align 4
2452 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2453 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to double**
2454 // CHECK3-NEXT: store double* @Gb, double** [[TMP27]], align 4
2455 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2456 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4
2457 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2458 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
2459 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP30]], align 4
2460 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2461 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
2462 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP32]], align 4
2463 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2464 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4
2465 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2466 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to double**
2467 // CHECK3-NEXT: store double* @Gc, double** [[TMP35]], align 4
2468 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2469 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to double**
2470 // CHECK3-NEXT: store double* @Gc, double** [[TMP37]], align 4
2471 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2472 // CHECK3-NEXT: store i8* null, i8** [[TMP38]], align 4
2473 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2474 // CHECK3-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32*
2475 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP40]], align 4
2476 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2477 // CHECK3-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
2478 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP42]], align 4
2479 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
2480 // CHECK3-NEXT: store i8* null, i8** [[TMP43]], align 4
2481 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
2482 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32*
2483 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP45]], align 4
2484 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
2485 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
2486 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP47]], align 4
2487 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
2488 // CHECK3-NEXT: store i8* null, i8** [[TMP48]], align 4
2489 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
2490 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32*
2491 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP50]], align 4
2492 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
2493 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
2494 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP52]], align 4
2495 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
2496 // CHECK3-NEXT: store i8* null, i8** [[TMP53]], align 4
2497 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
2498 // CHECK3-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double**
2499 // CHECK3-NEXT: store double* @Gd, double** [[TMP55]], align 4
2500 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
2501 // CHECK3-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to double**
2502 // CHECK3-NEXT: store double* @Gd, double** [[TMP57]], align 4
2503 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
2504 // CHECK3-NEXT: store i8* null, i8** [[TMP58]], align 4
2505 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
2506 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
2507 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP60]], align 4
2508 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
2509 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
2510 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP62]], align 4
2511 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
2512 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4
2513 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2514 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2515 // CHECK3-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.region_id, i32 9, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null)
2516 // CHECK3-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
2517 // CHECK3-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2518 // CHECK3: omp_offload.failed:
2519 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
2520 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2521 // CHECK3: omp_offload.cont:
2522 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
2523 // CHECK3: omp_if.else:
2524 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
2525 // CHECK3-NEXT: br label [[OMP_IF_END]]
2526 // CHECK3: omp_if.end:
2527 // CHECK3-NEXT: ret void
2528 //
2529 //
2530 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94
2531 // CHECK3-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1]] {
2532 // CHECK3-NEXT: entry:
2533 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
2534 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4
2535 // CHECK3-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4
2536 // CHECK3-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4
2537 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
2538 // CHECK3-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4
2539 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4
2540 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
2541 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4
2542 // CHECK3-NEXT: [[GB6:%.*]] = alloca double, align 8
2543 // CHECK3-NEXT: [[GC7:%.*]] = alloca double, align 8
2544 // CHECK3-NEXT: [[GD8:%.*]] = alloca double, align 8
2545 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2546 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2547 // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2548 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2549 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
2550 // CHECK3-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4
2551 // CHECK3-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4
2552 // CHECK3-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4
2553 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
2554 // CHECK3-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4
2555 // CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
2556 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
2557 // CHECK3-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4
2558 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
2559 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4
2560 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float*
2561 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4
2562 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16*
2563 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float*
2564 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16*
2565 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
2566 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
2567 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
2568 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8
2569 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
2570 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
2571 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
2572 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
2573 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
2574 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
2575 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
2576 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
2577 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
2578 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
2579 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
2580 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
2581 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
2582 // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
2583 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
2584 // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
2585 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
2586 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
2587 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
2588 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
2589 // CHECK3: land.lhs.true:
2590 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
2591 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
2592 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
2593 // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
2594 // CHECK3: land.lhs.true17:
2595 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
2596 // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
2597 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
2598 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
2599 // CHECK3: omp_if.then:
2600 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]])
2601 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
2602 // CHECK3: omp_if.else:
2603 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2604 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2605 // CHECK3-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]]
2606 // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2607 // CHECK3-NEXT: br label [[OMP_IF_END]]
2608 // CHECK3: omp_if.end:
2609 // CHECK3-NEXT: ret void
2610 //
2611 //
2612 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
2613 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
2614 // CHECK3-NEXT: entry:
2615 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2616 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2617 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
2618 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
2619 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4
2620 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2621 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2622 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
2623 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
2624 // CHECK3-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4
2625 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4
2626 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4
2627 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4
2628 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
2629 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
2630 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
2631 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
2632 // CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
2633 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
2634 // CHECK3-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
2635 // CHECK3-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
2636 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
2637 // CHECK3-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
2638 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
2639 // CHECK3-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
2640 // CHECK3-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
2641 // CHECK3-NEXT: ret void
2642 //
2643 //
2644 // CHECK3-LABEL: define {{[^@]+}}@_Z5tbar2ssss
2645 // CHECK3-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] {
2646 // CHECK3-NEXT: entry:
2647 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
2648 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
2649 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
2650 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
2651 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
2652 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
2653 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
2654 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
2655 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
2656 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
2657 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
2658 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
2659 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]])
2660 // CHECK3-NEXT: ret i32 [[CALL]]
2661 //
2662 //
2663 // CHECK3-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_
2664 // CHECK3-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat {
2665 // CHECK3-NEXT: entry:
2666 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
2667 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
2668 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
2669 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
2670 // CHECK3-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
2671 // CHECK3-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
2672 // CHECK3-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
2673 // CHECK3-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
2674 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
2675 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
2676 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
2677 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
2678 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
2679 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
2680 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
2681 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
2682 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
2683 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
2684 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
2685 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
2686 // CHECK3-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
2687 // CHECK3-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
2688 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
2689 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
2690 // CHECK3-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
2691 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
2692 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
2693 // CHECK3-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
2694 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
2695 // CHECK3-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
2696 // CHECK3-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
2697 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
2698 // CHECK3-NEXT: ret i32 [[ADD13]]
2699 //
2700 //
2701 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5
2702 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
2703 // CHECK3-NEXT: entry:
2704 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2705 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2706 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 4
2707 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 4
2708 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
2709 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
2710 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
2711 // CHECK3-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4
2712 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
2713 // CHECK3-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4
2714 // CHECK3-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4
2715 // CHECK3-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4
2716 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4
2717 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4
2718 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4
2719 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2720 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2721 // CHECK3-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 4
2722 // CHECK3-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 4
2723 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
2724 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
2725 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 4
2726 // CHECK3-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 4
2727 // CHECK3-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 4
2728 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 4
2729 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
2730 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
2731 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
2732 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
2733 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
2734 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float*
2735 // CHECK3-NEXT: store float [[TMP6]], float* [[CONV1]], align 4
2736 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[SB_CASTED]], align 4
2737 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[TMP2]], align 2
2738 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16*
2739 // CHECK3-NEXT: store i16 [[TMP8]], i16* [[CONV2]], align 2
2740 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4
2741 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
2742 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float*
2743 // CHECK3-NEXT: store float [[TMP10]], float* [[CONV3]], align 4
2744 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[SC_CASTED]], align 4
2745 // CHECK3-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP3]], align 2
2746 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16*
2747 // CHECK3-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
2748 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[D_CASTED]], align 4
2749 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
2750 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float*
2751 // CHECK3-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
2752 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[SD_CASTED]], align 4
2753 // CHECK3-NEXT: [[TMP16:%.*]] = load double, double* @Ga, align 8
2754 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP16]], 0.000000e+00
2755 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
2756 // CHECK3: land.lhs.true:
2757 // CHECK3-NEXT: [[TMP17:%.*]] = load i16, i16* [[TMP0]], align 2
2758 // CHECK3-NEXT: [[CONV6:%.*]] = sext i16 [[TMP17]] to i32
2759 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
2760 // CHECK3-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
2761 // CHECK3: land.lhs.true8:
2762 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
2763 // CHECK3-NEXT: [[CONV9:%.*]] = fpext float [[TMP18]] to double
2764 // CHECK3-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
2765 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
2766 // CHECK3: omp_if.then:
2767 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2768 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
2769 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
2770 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2771 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
2772 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4
2773 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2774 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
2775 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2776 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to double**
2777 // CHECK3-NEXT: store double* @Gb, double** [[TMP25]], align 4
2778 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2779 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to double**
2780 // CHECK3-NEXT: store double* @Gb, double** [[TMP27]], align 4
2781 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2782 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4
2783 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2784 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
2785 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP30]], align 4
2786 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2787 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
2788 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP32]], align 4
2789 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2790 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4
2791 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2792 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to double**
2793 // CHECK3-NEXT: store double* @Gc, double** [[TMP35]], align 4
2794 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2795 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to double**
2796 // CHECK3-NEXT: store double* @Gc, double** [[TMP37]], align 4
2797 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2798 // CHECK3-NEXT: store i8* null, i8** [[TMP38]], align 4
2799 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2800 // CHECK3-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32*
2801 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP40]], align 4
2802 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2803 // CHECK3-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
2804 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[TMP42]], align 4
2805 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
2806 // CHECK3-NEXT: store i8* null, i8** [[TMP43]], align 4
2807 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
2808 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32*
2809 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP45]], align 4
2810 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
2811 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
2812 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[TMP47]], align 4
2813 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
2814 // CHECK3-NEXT: store i8* null, i8** [[TMP48]], align 4
2815 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
2816 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32*
2817 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP50]], align 4
2818 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
2819 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
2820 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[TMP52]], align 4
2821 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
2822 // CHECK3-NEXT: store i8* null, i8** [[TMP53]], align 4
2823 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
2824 // CHECK3-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double**
2825 // CHECK3-NEXT: store double* @Gd, double** [[TMP55]], align 4
2826 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
2827 // CHECK3-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to double**
2828 // CHECK3-NEXT: store double* @Gd, double** [[TMP57]], align 4
2829 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
2830 // CHECK3-NEXT: store i8* null, i8** [[TMP58]], align 4
2831 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
2832 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
2833 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP60]], align 4
2834 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
2835 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
2836 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP62]], align 4
2837 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
2838 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4
2839 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2840 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2841 // CHECK3-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.region_id, i32 9, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null)
2842 // CHECK3-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
2843 // CHECK3-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2844 // CHECK3: omp_offload.failed:
2845 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
2846 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2847 // CHECK3: omp_offload.cont:
2848 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
2849 // CHECK3: omp_if.else:
2850 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
2851 // CHECK3-NEXT: br label [[OMP_IF_END]]
2852 // CHECK3: omp_if.end:
2853 // CHECK3-NEXT: ret void
2854 //
2855 //
2856 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145
2857 // CHECK3-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1]] {
2858 // CHECK3-NEXT: entry:
2859 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
2860 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4
2861 // CHECK3-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4
2862 // CHECK3-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4
2863 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
2864 // CHECK3-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4
2865 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4
2866 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
2867 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4
2868 // CHECK3-NEXT: [[GB6:%.*]] = alloca double, align 8
2869 // CHECK3-NEXT: [[GC7:%.*]] = alloca double, align 8
2870 // CHECK3-NEXT: [[GD8:%.*]] = alloca double, align 8
2871 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2872 // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2873 // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2874 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2875 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
2876 // CHECK3-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4
2877 // CHECK3-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4
2878 // CHECK3-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4
2879 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
2880 // CHECK3-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4
2881 // CHECK3-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
2882 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
2883 // CHECK3-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4
2884 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
2885 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4
2886 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float*
2887 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4
2888 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16*
2889 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float*
2890 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16*
2891 // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
2892 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
2893 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
2894 // CHECK3-NEXT: store double [[TMP4]], double* [[GB6]], align 8
2895 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
2896 // CHECK3-NEXT: store double [[TMP5]], double* [[GC7]], align 8
2897 // CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
2898 // CHECK3-NEXT: store double [[TMP6]], double* [[GD8]], align 8
2899 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
2900 // CHECK3-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
2901 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
2902 // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
2903 // CHECK3-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
2904 // CHECK3-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
2905 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
2906 // CHECK3-NEXT: store double [[ADD11]], double* [[GB6]], align 8
2907 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
2908 // CHECK3-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
2909 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
2910 // CHECK3-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
2911 // CHECK3-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
2912 // CHECK3-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
2913 // CHECK3-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
2914 // CHECK3-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
2915 // CHECK3: land.lhs.true:
2916 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
2917 // CHECK3-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
2918 // CHECK3-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
2919 // CHECK3-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
2920 // CHECK3: land.lhs.true17:
2921 // CHECK3-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
2922 // CHECK3-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
2923 // CHECK3-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
2924 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
2925 // CHECK3: omp_if.then:
2926 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]])
2927 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
2928 // CHECK3: omp_if.else:
2929 // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2930 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2931 // CHECK3-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]]
2932 // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2933 // CHECK3-NEXT: br label [[OMP_IF_END]]
2934 // CHECK3: omp_if.end:
2935 // CHECK3-NEXT: ret void
2936 //
2937 //
2938 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6
2939 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
2940 // CHECK3-NEXT: entry:
2941 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2942 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2943 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
2944 // CHECK3-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
2945 // CHECK3-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4
2946 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2947 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2948 // CHECK3-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
2949 // CHECK3-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
2950 // CHECK3-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4
2951 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4
2952 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4
2953 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4
2954 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
2955 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
2956 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
2957 // CHECK3-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
2958 // CHECK3-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
2959 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
2960 // CHECK3-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
2961 // CHECK3-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
2962 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
2963 // CHECK3-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
2964 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
2965 // CHECK3-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
2966 // CHECK3-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
2967 // CHECK3-NEXT: ret void
2968 //
2969 //
2970 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2971 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
2972 // CHECK3-NEXT: entry:
2973 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
2974 // CHECK3-NEXT: ret void
2975 //
2976 //
2977 // CHECK4-LABEL: define {{[^@]+}}@_Z3foossss
2978 // CHECK4-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] {
2979 // CHECK4-NEXT: entry:
2980 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
2981 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
2982 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
2983 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
2984 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
2985 // CHECK4-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4
2986 // CHECK4-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
2987 // CHECK4-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4
2988 // CHECK4-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4
2989 // CHECK4-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4
2990 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4
2991 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4
2992 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4
2993 // CHECK4-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
2994 // CHECK4-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
2995 // CHECK4-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
2996 // CHECK4-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
2997 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[B_ADDR]], align 2
2998 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
2999 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
3000 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_CASTED]], align 4
3001 // CHECK4-NEXT: [[TMP2:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
3002 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float*
3003 // CHECK4-NEXT: store float [[TMP2]], float* [[CONV1]], align 4
3004 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SB_CASTED]], align 4
3005 // CHECK4-NEXT: [[TMP4:%.*]] = load i16, i16* [[C_ADDR]], align 2
3006 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16*
3007 // CHECK4-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2
3008 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[C_CASTED]], align 4
3009 // CHECK4-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
3010 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float*
3011 // CHECK4-NEXT: store float [[TMP6]], float* [[CONV3]], align 4
3012 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[SC_CASTED]], align 4
3013 // CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[D_ADDR]], align 2
3014 // CHECK4-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16*
3015 // CHECK4-NEXT: store i16 [[TMP8]], i16* [[CONV4]], align 2
3016 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[D_CASTED]], align 4
3017 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
3018 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float*
3019 // CHECK4-NEXT: store float [[TMP10]], float* [[CONV5]], align 4
3020 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[SD_CASTED]], align 4
3021 // CHECK4-NEXT: [[TMP12:%.*]] = load double, double* @Ga, align 8
3022 // CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP12]], 0.000000e+00
3023 // CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
3024 // CHECK4: land.lhs.true:
3025 // CHECK4-NEXT: [[TMP13:%.*]] = load i16, i16* [[A_ADDR]], align 2
3026 // CHECK4-NEXT: [[CONV6:%.*]] = sext i16 [[TMP13]] to i32
3027 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
3028 // CHECK4-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
3029 // CHECK4: land.lhs.true8:
3030 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
3031 // CHECK4-NEXT: [[CONV9:%.*]] = fpext float [[TMP14]] to double
3032 // CHECK4-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
3033 // CHECK4-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
3034 // CHECK4: omp_if.then:
3035 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3036 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
3037 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP16]], align 4
3038 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3039 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
3040 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP18]], align 4
3041 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3042 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4
3043 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3044 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to double**
3045 // CHECK4-NEXT: store double* @Gb, double** [[TMP21]], align 4
3046 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3047 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to double**
3048 // CHECK4-NEXT: store double* @Gb, double** [[TMP23]], align 4
3049 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3050 // CHECK4-NEXT: store i8* null, i8** [[TMP24]], align 4
3051 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3052 // CHECK4-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
3053 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP26]], align 4
3054 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3055 // CHECK4-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
3056 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP28]], align 4
3057 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3058 // CHECK4-NEXT: store i8* null, i8** [[TMP29]], align 4
3059 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3060 // CHECK4-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to double**
3061 // CHECK4-NEXT: store double* @Gc, double** [[TMP31]], align 4
3062 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3063 // CHECK4-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
3064 // CHECK4-NEXT: store double* @Gc, double** [[TMP33]], align 4
3065 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3066 // CHECK4-NEXT: store i8* null, i8** [[TMP34]], align 4
3067 // CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3068 // CHECK4-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32*
3069 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP36]], align 4
3070 // CHECK4-NEXT: [[TMP37:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3071 // CHECK4-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32*
3072 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP38]], align 4
3073 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3074 // CHECK4-NEXT: store i8* null, i8** [[TMP39]], align 4
3075 // CHECK4-NEXT: [[TMP40:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
3076 // CHECK4-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32*
3077 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[TMP41]], align 4
3078 // CHECK4-NEXT: [[TMP42:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
3079 // CHECK4-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32*
3080 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[TMP43]], align 4
3081 // CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
3082 // CHECK4-NEXT: store i8* null, i8** [[TMP44]], align 4
3083 // CHECK4-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
3084 // CHECK4-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
3085 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[TMP46]], align 4
3086 // CHECK4-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
3087 // CHECK4-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32*
3088 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[TMP48]], align 4
3089 // CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
3090 // CHECK4-NEXT: store i8* null, i8** [[TMP49]], align 4
3091 // CHECK4-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
3092 // CHECK4-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double**
3093 // CHECK4-NEXT: store double* @Gd, double** [[TMP51]], align 4
3094 // CHECK4-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
3095 // CHECK4-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double**
3096 // CHECK4-NEXT: store double* @Gd, double** [[TMP53]], align 4
3097 // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
3098 // CHECK4-NEXT: store i8* null, i8** [[TMP54]], align 4
3099 // CHECK4-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
3100 // CHECK4-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32*
3101 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[TMP56]], align 4
3102 // CHECK4-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
3103 // CHECK4-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32*
3104 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[TMP58]], align 4
3105 // CHECK4-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
3106 // CHECK4-NEXT: store i8* null, i8** [[TMP59]], align 4
3107 // CHECK4-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3108 // CHECK4-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3109 // CHECK4-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.region_id, i32 9, i8** [[TMP60]], i8** [[TMP61]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null)
3110 // CHECK4-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0
3111 // CHECK4-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3112 // CHECK4: omp_offload.failed:
3113 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i32 [[TMP1]], double* @Gb, i32 [[TMP3]], double* @Gc, i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP9]], double* @Gd, i32 [[TMP11]]) #[[ATTR2:[0-9]+]]
3114 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3115 // CHECK4: omp_offload.cont:
3116 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
3117 // CHECK4: omp_if.else:
3118 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i32 [[TMP1]], double* @Gb, i32 [[TMP3]], double* @Gc, i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP9]], double* @Gd, i32 [[TMP11]]) #[[ATTR2]]
3119 // CHECK4-NEXT: br label [[OMP_IF_END]]
3120 // CHECK4: omp_if.end:
3121 // CHECK4-NEXT: [[TMP64:%.*]] = load i16, i16* [[A_ADDR]], align 2
3122 // CHECK4-NEXT: [[CONV11:%.*]] = sext i16 [[TMP64]] to i32
3123 // CHECK4-NEXT: [[TMP65:%.*]] = load i16, i16* [[B_ADDR]], align 2
3124 // CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP65]] to i32
3125 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV11]], [[CONV12]]
3126 // CHECK4-NEXT: [[TMP66:%.*]] = load i16, i16* [[C_ADDR]], align 2
3127 // CHECK4-NEXT: [[CONV13:%.*]] = sext i16 [[TMP66]] to i32
3128 // CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[ADD]], [[CONV13]]
3129 // CHECK4-NEXT: [[TMP67:%.*]] = load i16, i16* [[D_ADDR]], align 2
3130 // CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP67]] to i32
3131 // CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CONV15]]
3132 // CHECK4-NEXT: [[TMP68:%.*]] = load float, float* @_ZZ3foossssE2Sa, align 4
3133 // CHECK4-NEXT: [[CONV17:%.*]] = fptosi float [[TMP68]] to i32
3134 // CHECK4-NEXT: [[ADD18:%.*]] = add nsw i32 [[ADD16]], [[CONV17]]
3135 // CHECK4-NEXT: [[TMP69:%.*]] = load float, float* @_ZZ3foossssE2Sb, align 4
3136 // CHECK4-NEXT: [[CONV19:%.*]] = fptosi float [[TMP69]] to i32
3137 // CHECK4-NEXT: [[ADD20:%.*]] = add nsw i32 [[ADD18]], [[CONV19]]
3138 // CHECK4-NEXT: [[TMP70:%.*]] = load float, float* @_ZZ3foossssE2Sc, align 4
3139 // CHECK4-NEXT: [[CONV21:%.*]] = fptosi float [[TMP70]] to i32
3140 // CHECK4-NEXT: [[ADD22:%.*]] = add nsw i32 [[ADD20]], [[CONV21]]
3141 // CHECK4-NEXT: [[TMP71:%.*]] = load float, float* @_ZZ3foossssE2Sd, align 4
3142 // CHECK4-NEXT: [[CONV23:%.*]] = fptosi float [[TMP71]] to i32
3143 // CHECK4-NEXT: [[ADD24:%.*]] = add nsw i32 [[ADD22]], [[CONV23]]
3144 // CHECK4-NEXT: ret i32 [[ADD24]]
3145 //
3146 //
3147 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49
3148 // CHECK4-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1:[0-9]+]] {
3149 // CHECK4-NEXT: entry:
3150 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
3151 // CHECK4-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4
3152 // CHECK4-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4
3153 // CHECK4-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4
3154 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
3155 // CHECK4-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4
3156 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4
3157 // CHECK4-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
3158 // CHECK4-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4
3159 // CHECK4-NEXT: [[GB6:%.*]] = alloca double, align 8
3160 // CHECK4-NEXT: [[GC7:%.*]] = alloca double, align 8
3161 // CHECK4-NEXT: [[GD8:%.*]] = alloca double, align 8
3162 // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3163 // CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3164 // CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3165 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3166 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
3167 // CHECK4-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4
3168 // CHECK4-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4
3169 // CHECK4-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4
3170 // CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
3171 // CHECK4-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4
3172 // CHECK4-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
3173 // CHECK4-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
3174 // CHECK4-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4
3175 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
3176 // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4
3177 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float*
3178 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4
3179 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16*
3180 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float*
3181 // CHECK4-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16*
3182 // CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
3183 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
3184 // CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
3185 // CHECK4-NEXT: store double [[TMP4]], double* [[GB6]], align 8
3186 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
3187 // CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8
3188 // CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
3189 // CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8
3190 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
3191 // CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
3192 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
3193 // CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
3194 // CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
3195 // CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
3196 // CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
3197 // CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8
3198 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
3199 // CHECK4-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
3200 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
3201 // CHECK4-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
3202 // CHECK4-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
3203 // CHECK4-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
3204 // CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
3205 // CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
3206 // CHECK4: land.lhs.true:
3207 // CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
3208 // CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
3209 // CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
3210 // CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
3211 // CHECK4: land.lhs.true17:
3212 // CHECK4-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
3213 // CHECK4-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
3214 // CHECK4-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
3215 // CHECK4-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
3216 // CHECK4: omp_if.then:
3217 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]])
3218 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
3219 // CHECK4: omp_if.else:
3220 // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3221 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3222 // CHECK4-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]]
3223 // CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3224 // CHECK4-NEXT: br label [[OMP_IF_END]]
3225 // CHECK4: omp_if.end:
3226 // CHECK4-NEXT: ret void
3227 //
3228 //
3229 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
3230 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
3231 // CHECK4-NEXT: entry:
3232 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3233 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3234 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
3235 // CHECK4-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
3236 // CHECK4-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4
3237 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3238 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3239 // CHECK4-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
3240 // CHECK4-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
3241 // CHECK4-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4
3242 // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4
3243 // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4
3244 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4
3245 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
3246 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
3247 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
3248 // CHECK4-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
3249 // CHECK4-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
3250 // CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
3251 // CHECK4-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
3252 // CHECK4-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
3253 // CHECK4-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
3254 // CHECK4-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
3255 // CHECK4-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
3256 // CHECK4-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
3257 // CHECK4-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
3258 // CHECK4-NEXT: ret void
3259 //
3260 //
3261 // CHECK4-LABEL: define {{[^@]+}}@_Z3barssss
3262 // CHECK4-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] {
3263 // CHECK4-NEXT: entry:
3264 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
3265 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
3266 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
3267 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
3268 // CHECK4-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
3269 // CHECK4-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
3270 // CHECK4-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
3271 // CHECK4-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
3272 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
3273 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
3274 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
3275 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
3276 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
3277 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
3278 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
3279 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
3280 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
3281 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
3282 // CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
3283 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
3284 // CHECK4-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
3285 // CHECK4-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
3286 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
3287 // CHECK4-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
3288 // CHECK4-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
3289 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
3290 // CHECK4-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
3291 // CHECK4-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
3292 // CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
3293 // CHECK4-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
3294 // CHECK4-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
3295 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
3296 // CHECK4-NEXT: ret i32 [[ADD13]]
3297 //
3298 //
3299 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
3300 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
3301 // CHECK4-NEXT: entry:
3302 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3303 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3304 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 4
3305 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 4
3306 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
3307 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
3308 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
3309 // CHECK4-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4
3310 // CHECK4-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
3311 // CHECK4-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4
3312 // CHECK4-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4
3313 // CHECK4-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4
3314 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4
3315 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4
3316 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4
3317 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3318 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3319 // CHECK4-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 4
3320 // CHECK4-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 4
3321 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
3322 // CHECK4-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
3323 // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 4
3324 // CHECK4-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 4
3325 // CHECK4-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 4
3326 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 4
3327 // CHECK4-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
3328 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
3329 // CHECK4-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
3330 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
3331 // CHECK4-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ3barssssE2Sb, align 4
3332 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float*
3333 // CHECK4-NEXT: store float [[TMP6]], float* [[CONV1]], align 4
3334 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[SB_CASTED]], align 4
3335 // CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[TMP2]], align 2
3336 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16*
3337 // CHECK4-NEXT: store i16 [[TMP8]], i16* [[CONV2]], align 2
3338 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4
3339 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ3barssssE2Sc, align 4
3340 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float*
3341 // CHECK4-NEXT: store float [[TMP10]], float* [[CONV3]], align 4
3342 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[SC_CASTED]], align 4
3343 // CHECK4-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP3]], align 2
3344 // CHECK4-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16*
3345 // CHECK4-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
3346 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[D_CASTED]], align 4
3347 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ3barssssE2Sd, align 4
3348 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float*
3349 // CHECK4-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
3350 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[SD_CASTED]], align 4
3351 // CHECK4-NEXT: [[TMP16:%.*]] = load double, double* @Ga, align 8
3352 // CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP16]], 0.000000e+00
3353 // CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
3354 // CHECK4: land.lhs.true:
3355 // CHECK4-NEXT: [[TMP17:%.*]] = load i16, i16* [[TMP0]], align 2
3356 // CHECK4-NEXT: [[CONV6:%.*]] = sext i16 [[TMP17]] to i32
3357 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
3358 // CHECK4-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
3359 // CHECK4: land.lhs.true8:
3360 // CHECK4-NEXT: [[TMP18:%.*]] = load float, float* @_ZZ3barssssE2Sa, align 4
3361 // CHECK4-NEXT: [[CONV9:%.*]] = fpext float [[TMP18]] to double
3362 // CHECK4-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
3363 // CHECK4-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
3364 // CHECK4: omp_if.then:
3365 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3366 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
3367 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
3368 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3369 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
3370 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4
3371 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3372 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4
3373 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3374 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to double**
3375 // CHECK4-NEXT: store double* @Gb, double** [[TMP25]], align 4
3376 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3377 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to double**
3378 // CHECK4-NEXT: store double* @Gb, double** [[TMP27]], align 4
3379 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3380 // CHECK4-NEXT: store i8* null, i8** [[TMP28]], align 4
3381 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3382 // CHECK4-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
3383 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[TMP30]], align 4
3384 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3385 // CHECK4-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
3386 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[TMP32]], align 4
3387 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3388 // CHECK4-NEXT: store i8* null, i8** [[TMP33]], align 4
3389 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3390 // CHECK4-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to double**
3391 // CHECK4-NEXT: store double* @Gc, double** [[TMP35]], align 4
3392 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3393 // CHECK4-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to double**
3394 // CHECK4-NEXT: store double* @Gc, double** [[TMP37]], align 4
3395 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3396 // CHECK4-NEXT: store i8* null, i8** [[TMP38]], align 4
3397 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3398 // CHECK4-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32*
3399 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[TMP40]], align 4
3400 // CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3401 // CHECK4-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
3402 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[TMP42]], align 4
3403 // CHECK4-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3404 // CHECK4-NEXT: store i8* null, i8** [[TMP43]], align 4
3405 // CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
3406 // CHECK4-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32*
3407 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[TMP45]], align 4
3408 // CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
3409 // CHECK4-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
3410 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[TMP47]], align 4
3411 // CHECK4-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
3412 // CHECK4-NEXT: store i8* null, i8** [[TMP48]], align 4
3413 // CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
3414 // CHECK4-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32*
3415 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[TMP50]], align 4
3416 // CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
3417 // CHECK4-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
3418 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[TMP52]], align 4
3419 // CHECK4-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
3420 // CHECK4-NEXT: store i8* null, i8** [[TMP53]], align 4
3421 // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
3422 // CHECK4-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double**
3423 // CHECK4-NEXT: store double* @Gd, double** [[TMP55]], align 4
3424 // CHECK4-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
3425 // CHECK4-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to double**
3426 // CHECK4-NEXT: store double* @Gd, double** [[TMP57]], align 4
3427 // CHECK4-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
3428 // CHECK4-NEXT: store i8* null, i8** [[TMP58]], align 4
3429 // CHECK4-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
3430 // CHECK4-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
3431 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[TMP60]], align 4
3432 // CHECK4-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
3433 // CHECK4-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
3434 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[TMP62]], align 4
3435 // CHECK4-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
3436 // CHECK4-NEXT: store i8* null, i8** [[TMP63]], align 4
3437 // CHECK4-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3438 // CHECK4-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3439 // CHECK4-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.region_id, i32 9, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null)
3440 // CHECK4-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
3441 // CHECK4-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3442 // CHECK4: omp_offload.failed:
3443 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
3444 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3445 // CHECK4: omp_offload.cont:
3446 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
3447 // CHECK4: omp_if.else:
3448 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
3449 // CHECK4-NEXT: br label [[OMP_IF_END]]
3450 // CHECK4: omp_if.end:
3451 // CHECK4-NEXT: ret void
3452 //
3453 //
3454 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94
3455 // CHECK4-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1]] {
3456 // CHECK4-NEXT: entry:
3457 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
3458 // CHECK4-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4
3459 // CHECK4-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4
3460 // CHECK4-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4
3461 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
3462 // CHECK4-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4
3463 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4
3464 // CHECK4-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
3465 // CHECK4-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4
3466 // CHECK4-NEXT: [[GB6:%.*]] = alloca double, align 8
3467 // CHECK4-NEXT: [[GC7:%.*]] = alloca double, align 8
3468 // CHECK4-NEXT: [[GD8:%.*]] = alloca double, align 8
3469 // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3470 // CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3471 // CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3472 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3473 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
3474 // CHECK4-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4
3475 // CHECK4-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4
3476 // CHECK4-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4
3477 // CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
3478 // CHECK4-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4
3479 // CHECK4-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
3480 // CHECK4-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
3481 // CHECK4-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4
3482 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
3483 // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4
3484 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float*
3485 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4
3486 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16*
3487 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float*
3488 // CHECK4-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16*
3489 // CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
3490 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
3491 // CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
3492 // CHECK4-NEXT: store double [[TMP4]], double* [[GB6]], align 8
3493 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
3494 // CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8
3495 // CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
3496 // CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8
3497 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
3498 // CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
3499 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
3500 // CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
3501 // CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
3502 // CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
3503 // CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
3504 // CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8
3505 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
3506 // CHECK4-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
3507 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
3508 // CHECK4-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
3509 // CHECK4-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
3510 // CHECK4-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
3511 // CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
3512 // CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
3513 // CHECK4: land.lhs.true:
3514 // CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
3515 // CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
3516 // CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
3517 // CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
3518 // CHECK4: land.lhs.true17:
3519 // CHECK4-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
3520 // CHECK4-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
3521 // CHECK4-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
3522 // CHECK4-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
3523 // CHECK4: omp_if.then:
3524 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]])
3525 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
3526 // CHECK4: omp_if.else:
3527 // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3528 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3529 // CHECK4-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]]
3530 // CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3531 // CHECK4-NEXT: br label [[OMP_IF_END]]
3532 // CHECK4: omp_if.end:
3533 // CHECK4-NEXT: ret void
3534 //
3535 //
3536 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
3537 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
3538 // CHECK4-NEXT: entry:
3539 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3540 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3541 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
3542 // CHECK4-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
3543 // CHECK4-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4
3544 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3545 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3546 // CHECK4-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
3547 // CHECK4-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
3548 // CHECK4-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4
3549 // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4
3550 // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4
3551 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4
3552 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
3553 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
3554 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
3555 // CHECK4-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
3556 // CHECK4-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
3557 // CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
3558 // CHECK4-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
3559 // CHECK4-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
3560 // CHECK4-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
3561 // CHECK4-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
3562 // CHECK4-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
3563 // CHECK4-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
3564 // CHECK4-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
3565 // CHECK4-NEXT: ret void
3566 //
3567 //
3568 // CHECK4-LABEL: define {{[^@]+}}@_Z5tbar2ssss
3569 // CHECK4-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] {
3570 // CHECK4-NEXT: entry:
3571 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
3572 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
3573 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
3574 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
3575 // CHECK4-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
3576 // CHECK4-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
3577 // CHECK4-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
3578 // CHECK4-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
3579 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
3580 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
3581 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
3582 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
3583 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]])
3584 // CHECK4-NEXT: ret i32 [[CALL]]
3585 //
3586 //
3587 // CHECK4-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_
3588 // CHECK4-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat {
3589 // CHECK4-NEXT: entry:
3590 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2
3591 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2
3592 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16, align 2
3593 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i16, align 2
3594 // CHECK4-NEXT: store i16 [[A]], i16* [[A_ADDR]], align 2
3595 // CHECK4-NEXT: store i16 [[B]], i16* [[B_ADDR]], align 2
3596 // CHECK4-NEXT: store i16 [[C]], i16* [[C_ADDR]], align 2
3597 // CHECK4-NEXT: store i16 [[D]], i16* [[D_ADDR]], align 2
3598 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, i16*, i16*, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i16* [[A_ADDR]], i16* [[B_ADDR]], i16* [[C_ADDR]], i16* [[D_ADDR]])
3599 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[A_ADDR]], align 2
3600 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32
3601 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2
3602 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
3603 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
3604 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2
3605 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
3606 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
3607 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2
3608 // CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
3609 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
3610 // CHECK4-NEXT: [[TMP4:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
3611 // CHECK4-NEXT: [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
3612 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
3613 // CHECK4-NEXT: [[TMP5:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
3614 // CHECK4-NEXT: [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
3615 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
3616 // CHECK4-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
3617 // CHECK4-NEXT: [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
3618 // CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
3619 // CHECK4-NEXT: [[TMP7:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
3620 // CHECK4-NEXT: [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
3621 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
3622 // CHECK4-NEXT: ret i32 [[ADD13]]
3623 //
3624 //
3625 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5
3626 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
3627 // CHECK4-NEXT: entry:
3628 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3629 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3630 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i16*, align 4
3631 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i16*, align 4
3632 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
3633 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
3634 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
3635 // CHECK4-NEXT: [[SB_CASTED:%.*]] = alloca i32, align 4
3636 // CHECK4-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4
3637 // CHECK4-NEXT: [[SC_CASTED:%.*]] = alloca i32, align 4
3638 // CHECK4-NEXT: [[D_CASTED:%.*]] = alloca i32, align 4
3639 // CHECK4-NEXT: [[SD_CASTED:%.*]] = alloca i32, align 4
3640 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x i8*], align 4
3641 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x i8*], align 4
3642 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x i8*], align 4
3643 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3644 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3645 // CHECK4-NEXT: store i16* [[A]], i16** [[A_ADDR]], align 4
3646 // CHECK4-NEXT: store i16* [[B]], i16** [[B_ADDR]], align 4
3647 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
3648 // CHECK4-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
3649 // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[A_ADDR]], align 4
3650 // CHECK4-NEXT: [[TMP1:%.*]] = load i16*, i16** [[B_ADDR]], align 4
3651 // CHECK4-NEXT: [[TMP2:%.*]] = load i16*, i16** [[C_ADDR]], align 4
3652 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[D_ADDR]], align 4
3653 // CHECK4-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2
3654 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
3655 // CHECK4-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2
3656 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
3657 // CHECK4-NEXT: [[TMP6:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
3658 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_CASTED]] to float*
3659 // CHECK4-NEXT: store float [[TMP6]], float* [[CONV1]], align 4
3660 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[SB_CASTED]], align 4
3661 // CHECK4-NEXT: [[TMP8:%.*]] = load i16, i16* [[TMP2]], align 2
3662 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_CASTED]] to i16*
3663 // CHECK4-NEXT: store i16 [[TMP8]], i16* [[CONV2]], align 2
3664 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4
3665 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
3666 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_CASTED]] to float*
3667 // CHECK4-NEXT: store float [[TMP10]], float* [[CONV3]], align 4
3668 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[SC_CASTED]], align 4
3669 // CHECK4-NEXT: [[TMP12:%.*]] = load i16, i16* [[TMP3]], align 2
3670 // CHECK4-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_CASTED]] to i16*
3671 // CHECK4-NEXT: store i16 [[TMP12]], i16* [[CONV4]], align 2
3672 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[D_CASTED]], align 4
3673 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
3674 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_CASTED]] to float*
3675 // CHECK4-NEXT: store float [[TMP14]], float* [[CONV5]], align 4
3676 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[SD_CASTED]], align 4
3677 // CHECK4-NEXT: [[TMP16:%.*]] = load double, double* @Ga, align 8
3678 // CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP16]], 0.000000e+00
3679 // CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
3680 // CHECK4: land.lhs.true:
3681 // CHECK4-NEXT: [[TMP17:%.*]] = load i16, i16* [[TMP0]], align 2
3682 // CHECK4-NEXT: [[CONV6:%.*]] = sext i16 [[TMP17]] to i32
3683 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
3684 // CHECK4-NEXT: br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
3685 // CHECK4: land.lhs.true8:
3686 // CHECK4-NEXT: [[TMP18:%.*]] = load float, float* @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
3687 // CHECK4-NEXT: [[CONV9:%.*]] = fpext float [[TMP18]] to double
3688 // CHECK4-NEXT: [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
3689 // CHECK4-NEXT: br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
3690 // CHECK4: omp_if.then:
3691 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3692 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
3693 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
3694 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3695 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
3696 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4
3697 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3698 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4
3699 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3700 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to double**
3701 // CHECK4-NEXT: store double* @Gb, double** [[TMP25]], align 4
3702 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3703 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to double**
3704 // CHECK4-NEXT: store double* @Gb, double** [[TMP27]], align 4
3705 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3706 // CHECK4-NEXT: store i8* null, i8** [[TMP28]], align 4
3707 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3708 // CHECK4-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
3709 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[TMP30]], align 4
3710 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3711 // CHECK4-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
3712 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[TMP32]], align 4
3713 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3714 // CHECK4-NEXT: store i8* null, i8** [[TMP33]], align 4
3715 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3716 // CHECK4-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to double**
3717 // CHECK4-NEXT: store double* @Gc, double** [[TMP35]], align 4
3718 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3719 // CHECK4-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to double**
3720 // CHECK4-NEXT: store double* @Gc, double** [[TMP37]], align 4
3721 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3722 // CHECK4-NEXT: store i8* null, i8** [[TMP38]], align 4
3723 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3724 // CHECK4-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32*
3725 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[TMP40]], align 4
3726 // CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3727 // CHECK4-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
3728 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[TMP42]], align 4
3729 // CHECK4-NEXT: [[TMP43:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3730 // CHECK4-NEXT: store i8* null, i8** [[TMP43]], align 4
3731 // CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
3732 // CHECK4-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32*
3733 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[TMP45]], align 4
3734 // CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
3735 // CHECK4-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
3736 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[TMP47]], align 4
3737 // CHECK4-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
3738 // CHECK4-NEXT: store i8* null, i8** [[TMP48]], align 4
3739 // CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
3740 // CHECK4-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32*
3741 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[TMP50]], align 4
3742 // CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6
3743 // CHECK4-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
3744 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[TMP52]], align 4
3745 // CHECK4-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
3746 // CHECK4-NEXT: store i8* null, i8** [[TMP53]], align 4
3747 // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
3748 // CHECK4-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double**
3749 // CHECK4-NEXT: store double* @Gd, double** [[TMP55]], align 4
3750 // CHECK4-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7
3751 // CHECK4-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to double**
3752 // CHECK4-NEXT: store double* @Gd, double** [[TMP57]], align 4
3753 // CHECK4-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
3754 // CHECK4-NEXT: store i8* null, i8** [[TMP58]], align 4
3755 // CHECK4-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
3756 // CHECK4-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
3757 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[TMP60]], align 4
3758 // CHECK4-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8
3759 // CHECK4-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
3760 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[TMP62]], align 4
3761 // CHECK4-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
3762 // CHECK4-NEXT: store i8* null, i8** [[TMP63]], align 4
3763 // CHECK4-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3764 // CHECK4-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3765 // CHECK4-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.region_id, i32 9, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null)
3766 // CHECK4-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
3767 // CHECK4-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3768 // CHECK4: omp_offload.failed:
3769 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
3770 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3771 // CHECK4: omp_offload.cont:
3772 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
3773 // CHECK4: omp_if.else:
3774 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i32 [[TMP5]], double* @Gb, i32 [[TMP7]], double* @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], double* @Gd, i32 [[TMP15]]) #[[ATTR2]]
3775 // CHECK4-NEXT: br label [[OMP_IF_END]]
3776 // CHECK4: omp_if.end:
3777 // CHECK4-NEXT: ret void
3778 //
3779 //
3780 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145
3781 // CHECK4-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1]] {
3782 // CHECK4-NEXT: entry:
3783 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
3784 // CHECK4-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4
3785 // CHECK4-NEXT: [[SB_ADDR:%.*]] = alloca i32, align 4
3786 // CHECK4-NEXT: [[GC_ADDR:%.*]] = alloca double*, align 4
3787 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
3788 // CHECK4-NEXT: [[SC_ADDR:%.*]] = alloca i32, align 4
3789 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4
3790 // CHECK4-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
3791 // CHECK4-NEXT: [[SD_ADDR:%.*]] = alloca i32, align 4
3792 // CHECK4-NEXT: [[GB6:%.*]] = alloca double, align 8
3793 // CHECK4-NEXT: [[GC7:%.*]] = alloca double, align 8
3794 // CHECK4-NEXT: [[GD8:%.*]] = alloca double, align 8
3795 // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3796 // CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3797 // CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3798 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3799 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
3800 // CHECK4-NEXT: store double* [[GB]], double** [[GB_ADDR]], align 4
3801 // CHECK4-NEXT: store i32 [[SB]], i32* [[SB_ADDR]], align 4
3802 // CHECK4-NEXT: store double* [[GC]], double** [[GC_ADDR]], align 4
3803 // CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4
3804 // CHECK4-NEXT: store i32 [[SC]], i32* [[SC_ADDR]], align 4
3805 // CHECK4-NEXT: store i32 [[D]], i32* [[D_ADDR]], align 4
3806 // CHECK4-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
3807 // CHECK4-NEXT: store i32 [[SD]], i32* [[SD_ADDR]], align 4
3808 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
3809 // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[GB_ADDR]], align 4
3810 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[SB_ADDR]] to float*
3811 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[GC_ADDR]], align 4
3812 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[C_ADDR]] to i16*
3813 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[SC_ADDR]] to float*
3814 // CHECK4-NEXT: [[CONV4:%.*]] = bitcast i32* [[D_ADDR]] to i16*
3815 // CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[GD_ADDR]], align 4
3816 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[SD_ADDR]] to float*
3817 // CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
3818 // CHECK4-NEXT: store double [[TMP4]], double* [[GB6]], align 8
3819 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[TMP2]], align 8
3820 // CHECK4-NEXT: store double [[TMP5]], double* [[GC7]], align 8
3821 // CHECK4-NEXT: [[TMP6:%.*]] = load double, double* [[TMP3]], align 8
3822 // CHECK4-NEXT: store double [[TMP6]], double* [[GD8]], align 8
3823 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[CONV]], align 4
3824 // CHECK4-NEXT: [[CONV9:%.*]] = sext i16 [[TMP7]] to i32
3825 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 1
3826 // CHECK4-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16
3827 // CHECK4-NEXT: store i16 [[CONV10]], i16* [[CONV]], align 4
3828 // CHECK4-NEXT: [[TMP8:%.*]] = load double, double* [[GB6]], align 8
3829 // CHECK4-NEXT: [[ADD11:%.*]] = fadd double [[TMP8]], 1.000000e+00
3830 // CHECK4-NEXT: store double [[ADD11]], double* [[GB6]], align 8
3831 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[CONV1]], align 4
3832 // CHECK4-NEXT: [[CONV12:%.*]] = fpext float [[TMP9]] to double
3833 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[CONV12]], 1.000000e+00
3834 // CHECK4-NEXT: [[CONV14:%.*]] = fptrunc double [[ADD13]] to float
3835 // CHECK4-NEXT: store float [[CONV14]], float* [[CONV1]], align 4
3836 // CHECK4-NEXT: [[TMP10:%.*]] = load double, double* [[GC7]], align 8
3837 // CHECK4-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
3838 // CHECK4-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
3839 // CHECK4: land.lhs.true:
3840 // CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[CONV2]], align 4
3841 // CHECK4-NEXT: [[CONV15:%.*]] = sext i16 [[TMP11]] to i32
3842 // CHECK4-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[CONV15]], 0
3843 // CHECK4-NEXT: br i1 [[CMP16]], label [[LAND_LHS_TRUE17:%.*]], label [[OMP_IF_ELSE]]
3844 // CHECK4: land.lhs.true17:
3845 // CHECK4-NEXT: [[TMP12:%.*]] = load float, float* [[CONV3]], align 4
3846 // CHECK4-NEXT: [[CONV18:%.*]] = fpext float [[TMP12]] to double
3847 // CHECK4-NEXT: [[CMP19:%.*]] = fcmp ogt double [[CONV18]], 0.000000e+00
3848 // CHECK4-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
3849 // CHECK4: omp_if.then:
3850 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*, double*, float*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i16* [[CONV4]], double* [[GD8]], float* [[CONV5]])
3851 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
3852 // CHECK4: omp_if.else:
3853 // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3854 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3855 // CHECK4-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i16* [[CONV4]], double* [[GD8]], float* [[CONV5]]) #[[ATTR2]]
3856 // CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3857 // CHECK4-NEXT: br label [[OMP_IF_END]]
3858 // CHECK4: omp_if.end:
3859 // CHECK4-NEXT: ret void
3860 //
3861 //
3862 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6
3863 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
3864 // CHECK4-NEXT: entry:
3865 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3866 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3867 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i16*, align 4
3868 // CHECK4-NEXT: [[GD_ADDR:%.*]] = alloca double*, align 4
3869 // CHECK4-NEXT: [[SD_ADDR:%.*]] = alloca float*, align 4
3870 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3871 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3872 // CHECK4-NEXT: store i16* [[D]], i16** [[D_ADDR]], align 4
3873 // CHECK4-NEXT: store double* [[GD]], double** [[GD_ADDR]], align 4
3874 // CHECK4-NEXT: store float* [[SD]], float** [[SD_ADDR]], align 4
3875 // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[D_ADDR]], align 4
3876 // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[GD_ADDR]], align 4
3877 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[SD_ADDR]], align 4
3878 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP0]], align 2
3879 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP3]] to i32
3880 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
3881 // CHECK4-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
3882 // CHECK4-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2
3883 // CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[TMP1]], align 8
3884 // CHECK4-NEXT: [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
3885 // CHECK4-NEXT: store double [[ADD2]], double* [[TMP1]], align 8
3886 // CHECK4-NEXT: [[TMP5:%.*]] = load float, float* [[TMP2]], align 4
3887 // CHECK4-NEXT: [[CONV3:%.*]] = fpext float [[TMP5]] to double
3888 // CHECK4-NEXT: [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
3889 // CHECK4-NEXT: [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
3890 // CHECK4-NEXT: store float [[CONV5]], float* [[TMP2]], align 4
3891 // CHECK4-NEXT: ret void
3892 //
3893 //
3894 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3895 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
3896 // CHECK4-NEXT: entry:
3897 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
3898 // CHECK4-NEXT: ret void
3899 //
3900 //