1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK2
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK4
9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK6
12 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK8
15 
16 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK10
19 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
20 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
21 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK12
22 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK13
23 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
24 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK14
25 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK15
26 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
27 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK16
28 
29 // Test target codegen - host bc file has to be created first.
30 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
31 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK17
32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
33 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK18
34 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
35 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK19
36 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
37 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK20
38 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
39 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK21
40 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
41 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK22
42 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
43 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK23
44 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
45 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK24
46 
47 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
48 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK25
49 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
50 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK26
51 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK27
53 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
54 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK28
55 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
56 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK29
57 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
58 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK30
59 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
60 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK31
61 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
62 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK32
63 
64 // expected-no-diagnostics
65 #ifndef HEADER
66 #define HEADER
67 
68 
69 
70 // We have 8 target regions, but only 7 that actually will generate offloading
71 // code, only 6 will have mapped arguments, and only 4 have all-constant map
72 // sizes.
73 
74 
75 
76 // Check target registration is registered as a Ctor.
77 
78 
79 template<typename tx, typename ty>
80 struct TT{
81   tx X;
82   ty Y;
83 };
84 
get_val()85 long long get_val() { return 0; }
86 
foo(int n)87 int foo(int n) {
88   int a = 0;
89   short aa = 0;
90   float b[10];
91   float bn[n];
92   double c[5][10];
93   double cn[5][n];
94   TT<long long, char> d;
95 
96   #pragma omp target parallel for simd nowait
97   for (int i = 3; i < 32; i += 5) {
98   }
99 
100   long long k = get_val();
101   #pragma omp target parallel for simd if(target: 0) linear(k : 3) schedule(dynamic)
102   for (int i = 10; i > 1; i--) {
103     a += 1;
104   }
105 
106 
107   int lin = 12;
108   #pragma omp target parallel for simd if(target: 1) linear(lin, a : get_val())
109   for (unsigned long long it = 2000; it >= 600; it-=400) {
110     aa += 1;
111   }
112 
113 
114 
115 
116   #pragma omp target parallel for simd if(target: n>10)
117   for (short it = 6; it <= 20; it-=-4) {
118     a += 1;
119     aa += 1;
120   }
121 
122   // We capture 3 VLA sizes in this target region
123 
124 
125 
126 
127 
128   // The names below are not necessarily consistent with the names used for the
129   // addresses above as some are repeated.
130 
131 
132 
133 
134 
135 
136 
137 
138 
139 
140   #pragma omp target parallel for simd if(target: n>20) schedule(static, a)
141   for (unsigned char it = 'z'; it >= 'a'; it+=-1) {
142     a += 1;
143     b[2] += 1.0;
144     bn[3] += 1.0;
145     c[1][2] += 1.0;
146     cn[1][3] += 1.0;
147     d.X += 1;
148     d.Y += 1;
149   }
150 
151   return a;
152 }
153 
154 // Check that the offloading functions are emitted and that the arguments are
155 // correct and loaded correctly for the target regions in foo().
156 
157 
158 
159 
160 // Create stack storage and store argument in there.
161 
162 // Create stack storage and store argument in there.
163 
164 // Create stack storage and store argument in there.
165 
166 // Create local storage for each capture.
167 
168 
169 
170 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
171 
172 template<typename tx>
ftemplate(int n)173 tx ftemplate(int n) {
174   tx a = 0;
175   short aa = 0;
176   tx b[10];
177 
178   #pragma omp target parallel for simd if(target: n>40)
179   for (long long i = -10; i < 10; i += 3) {
180     a += 1;
181     aa += 1;
182     b[2] += 1;
183   }
184 
185   return a;
186 }
187 
188 static
fstatic(int n)189 int fstatic(int n) {
190   int a = 0;
191   short aa = 0;
192   char aaa = 0;
193   int b[10];
194 
195   #pragma omp target parallel for simd if(target: n>50)
196   for (unsigned i=100; i<10; i+=10) {
197     a += 1;
198     aa += 1;
199     aaa += 1;
200     b[2] += 1;
201   }
202 
203   return a;
204 }
205 
206 struct S1 {
207   double a;
208 
r1S1209   int r1(int n){
210     int b = n+1;
211     short int c[2][n];
212 
213 #ifdef OMP5
214     #pragma omp target parallel for simd if(n>60) nontemporal(a)
215 #else
216     #pragma omp target parallel for simd if(target: n>60)
217 #endif // OMP5
218     for (unsigned long long it = 2000; it >= 600; it -= 400) {
219       this->a = (double)b + 1.5;
220       c[1][1] = ++a;
221     }
222 
223     return c[1][1] + (int)b;
224   }
225 };
226 
bar(int n)227 int bar(int n){
228   int a = 0;
229 
230   a += foo(n);
231 
232   S1 S;
233   a += S.r1(n);
234 
235   a += fstatic(n);
236 
237   a += ftemplate<int>(n);
238 
239   return a;
240 }
241 
242 
243 
244 // We capture 2 VLA sizes in this target region
245 
246 
247 // The names below are not necessarily consistent with the names used for the
248 // addresses above as some are repeated.
249 
250 
251 
252 
253 
254 
255 
256 
257 
258 
259 
260 
261 
262 
263 
264 
265 
266 
267 
268 // Check that the offloading functions are emitted and that the arguments are
269 // correct and loaded correctly for the target regions of the callees of bar().
270 
271 // Create local storage for each capture.
272 // Store captures in the context.
273 
274 
275 
276 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
277 
278 
279 // Create local storage for each capture.
280 // Store captures in the context.
281 
282 
283 
284 
285 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
286 
287 // Create local storage for each capture.
288 // Store captures in the context.
289 
290 
291 
292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
293 
294 
295 #endif
296 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv
297 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
298 // CHECK1-NEXT:  entry:
299 // CHECK1-NEXT:    ret i64 0
300 //
301 //
302 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
303 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
304 // CHECK1-NEXT:  entry:
305 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
306 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
307 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
308 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
309 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
310 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
311 // CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
312 // CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
313 // CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
314 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
315 // CHECK1-NEXT:    [[K:%.*]] = alloca i64, align 8
316 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
317 // CHECK1-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
318 // CHECK1-NEXT:    [[LIN:%.*]] = alloca i32, align 4
319 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
320 // CHECK1-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
321 // CHECK1-NEXT:    [[A_CASTED4:%.*]] = alloca i64, align 8
322 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
323 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
324 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
325 // CHECK1-NEXT:    [[A_CASTED6:%.*]] = alloca i64, align 8
326 // CHECK1-NEXT:    [[AA_CASTED8:%.*]] = alloca i64, align 8
327 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
328 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
329 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
330 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
331 // CHECK1-NEXT:    [[A_CASTED15:%.*]] = alloca i64, align 8
332 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
333 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
334 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
335 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
336 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
337 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
338 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
339 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
340 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
341 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
342 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
343 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
344 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
345 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
346 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
347 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
348 // CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
349 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
350 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
351 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
352 // CHECK1-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
353 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
354 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
355 // CHECK1-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]])
356 // CHECK1-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
357 // CHECK1-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
358 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
359 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
360 // CHECK1-NEXT:    store i32 [[TMP11]], i32* [[CONV]], align 4
361 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
362 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, i64* [[K]], align 8
363 // CHECK1-NEXT:    store i64 [[TMP13]], i64* [[K_CASTED]], align 8
364 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8
365 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]]
366 // CHECK1-NEXT:    store i32 12, i32* [[LIN]], align 4
367 // CHECK1-NEXT:    [[TMP15:%.*]] = load i16, i16* [[AA]], align 2
368 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
369 // CHECK1-NEXT:    store i16 [[TMP15]], i16* [[CONV2]], align 2
370 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8
371 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4
372 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
373 // CHECK1-NEXT:    store i32 [[TMP17]], i32* [[CONV3]], align 4
374 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
375 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A]], align 4
376 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
377 // CHECK1-NEXT:    store i32 [[TMP19]], i32* [[CONV5]], align 4
378 // CHECK1-NEXT:    [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8
379 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
380 // CHECK1-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
381 // CHECK1-NEXT:    store i64 [[TMP16]], i64* [[TMP22]], align 8
382 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
383 // CHECK1-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
384 // CHECK1-NEXT:    store i64 [[TMP16]], i64* [[TMP24]], align 8
385 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
386 // CHECK1-NEXT:    store i8* null, i8** [[TMP25]], align 8
387 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
388 // CHECK1-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
389 // CHECK1-NEXT:    store i64 [[TMP18]], i64* [[TMP27]], align 8
390 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
391 // CHECK1-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
392 // CHECK1-NEXT:    store i64 [[TMP18]], i64* [[TMP29]], align 8
393 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
394 // CHECK1-NEXT:    store i8* null, i8** [[TMP30]], align 8
395 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
396 // CHECK1-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
397 // CHECK1-NEXT:    store i64 [[TMP20]], i64* [[TMP32]], align 8
398 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
399 // CHECK1-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
400 // CHECK1-NEXT:    store i64 [[TMP20]], i64* [[TMP34]], align 8
401 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
402 // CHECK1-NEXT:    store i8* null, i8** [[TMP35]], align 8
403 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
404 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
405 // CHECK1-NEXT:    [[TMP38:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
406 // CHECK1-NEXT:    [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
407 // CHECK1-NEXT:    br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
408 // CHECK1:       omp_offload.failed:
409 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]]
410 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
411 // CHECK1:       omp_offload.cont:
412 // CHECK1-NEXT:    [[TMP40:%.*]] = load i32, i32* [[A]], align 4
413 // CHECK1-NEXT:    [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
414 // CHECK1-NEXT:    store i32 [[TMP40]], i32* [[CONV7]], align 4
415 // CHECK1-NEXT:    [[TMP41:%.*]] = load i64, i64* [[A_CASTED6]], align 8
416 // CHECK1-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2
417 // CHECK1-NEXT:    [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
418 // CHECK1-NEXT:    store i16 [[TMP42]], i16* [[CONV9]], align 2
419 // CHECK1-NEXT:    [[TMP43:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
420 // CHECK1-NEXT:    [[TMP44:%.*]] = load i32, i32* [[N_ADDR]], align 4
421 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP44]], 10
422 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
423 // CHECK1:       omp_if.then:
424 // CHECK1-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
425 // CHECK1-NEXT:    [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
426 // CHECK1-NEXT:    store i64 [[TMP41]], i64* [[TMP46]], align 8
427 // CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
428 // CHECK1-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
429 // CHECK1-NEXT:    store i64 [[TMP41]], i64* [[TMP48]], align 8
430 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
431 // CHECK1-NEXT:    store i8* null, i8** [[TMP49]], align 8
432 // CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
433 // CHECK1-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
434 // CHECK1-NEXT:    store i64 [[TMP43]], i64* [[TMP51]], align 8
435 // CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
436 // CHECK1-NEXT:    [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
437 // CHECK1-NEXT:    store i64 [[TMP43]], i64* [[TMP53]], align 8
438 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
439 // CHECK1-NEXT:    store i8* null, i8** [[TMP54]], align 8
440 // CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
441 // CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
442 // CHECK1-NEXT:    [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
443 // CHECK1-NEXT:    [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
444 // CHECK1-NEXT:    br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
445 // CHECK1:       omp_offload.failed13:
446 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
447 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT14]]
448 // CHECK1:       omp_offload.cont14:
449 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
450 // CHECK1:       omp_if.else:
451 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
452 // CHECK1-NEXT:    br label [[OMP_IF_END]]
453 // CHECK1:       omp_if.end:
454 // CHECK1-NEXT:    [[TMP59:%.*]] = load i32, i32* [[A]], align 4
455 // CHECK1-NEXT:    store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_]], align 4
456 // CHECK1-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
457 // CHECK1-NEXT:    [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
458 // CHECK1-NEXT:    store i32 [[TMP60]], i32* [[CONV16]], align 4
459 // CHECK1-NEXT:    [[TMP61:%.*]] = load i64, i64* [[A_CASTED15]], align 8
460 // CHECK1-NEXT:    [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
461 // CHECK1-NEXT:    [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
462 // CHECK1-NEXT:    store i32 [[TMP62]], i32* [[CONV17]], align 4
463 // CHECK1-NEXT:    [[TMP63:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
464 // CHECK1-NEXT:    [[TMP64:%.*]] = load i32, i32* [[N_ADDR]], align 4
465 // CHECK1-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP64]], 20
466 // CHECK1-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
467 // CHECK1:       omp_if.then19:
468 // CHECK1-NEXT:    [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4
469 // CHECK1-NEXT:    [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]]
470 // CHECK1-NEXT:    [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8
471 // CHECK1-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
472 // CHECK1-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
473 // CHECK1-NEXT:    store i64 [[TMP61]], i64* [[TMP69]], align 8
474 // CHECK1-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
475 // CHECK1-NEXT:    [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64*
476 // CHECK1-NEXT:    store i64 [[TMP61]], i64* [[TMP71]], align 8
477 // CHECK1-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
478 // CHECK1-NEXT:    store i64 4, i64* [[TMP72]], align 8
479 // CHECK1-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
480 // CHECK1-NEXT:    store i8* null, i8** [[TMP73]], align 8
481 // CHECK1-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
482 // CHECK1-NEXT:    [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
483 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 8
484 // CHECK1-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
485 // CHECK1-NEXT:    [[TMP77:%.*]] = bitcast i8** [[TMP76]] to [10 x float]**
486 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP77]], align 8
487 // CHECK1-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
488 // CHECK1-NEXT:    store i64 40, i64* [[TMP78]], align 8
489 // CHECK1-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
490 // CHECK1-NEXT:    store i8* null, i8** [[TMP79]], align 8
491 // CHECK1-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
492 // CHECK1-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
493 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP81]], align 8
494 // CHECK1-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
495 // CHECK1-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
496 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP83]], align 8
497 // CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
498 // CHECK1-NEXT:    store i64 8, i64* [[TMP84]], align 8
499 // CHECK1-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
500 // CHECK1-NEXT:    store i8* null, i8** [[TMP85]], align 8
501 // CHECK1-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
502 // CHECK1-NEXT:    [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
503 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP87]], align 8
504 // CHECK1-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
505 // CHECK1-NEXT:    [[TMP89:%.*]] = bitcast i8** [[TMP88]] to float**
506 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP89]], align 8
507 // CHECK1-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
508 // CHECK1-NEXT:    store i64 [[TMP65]], i64* [[TMP90]], align 8
509 // CHECK1-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
510 // CHECK1-NEXT:    store i8* null, i8** [[TMP91]], align 8
511 // CHECK1-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
512 // CHECK1-NEXT:    [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
513 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 8
514 // CHECK1-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
515 // CHECK1-NEXT:    [[TMP95:%.*]] = bitcast i8** [[TMP94]] to [5 x [10 x double]]**
516 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP95]], align 8
517 // CHECK1-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
518 // CHECK1-NEXT:    store i64 400, i64* [[TMP96]], align 8
519 // CHECK1-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
520 // CHECK1-NEXT:    store i8* null, i8** [[TMP97]], align 8
521 // CHECK1-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
522 // CHECK1-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
523 // CHECK1-NEXT:    store i64 5, i64* [[TMP99]], align 8
524 // CHECK1-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
525 // CHECK1-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
526 // CHECK1-NEXT:    store i64 5, i64* [[TMP101]], align 8
527 // CHECK1-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
528 // CHECK1-NEXT:    store i64 8, i64* [[TMP102]], align 8
529 // CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
530 // CHECK1-NEXT:    store i8* null, i8** [[TMP103]], align 8
531 // CHECK1-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
532 // CHECK1-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64*
533 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP105]], align 8
534 // CHECK1-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
535 // CHECK1-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
536 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP107]], align 8
537 // CHECK1-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
538 // CHECK1-NEXT:    store i64 8, i64* [[TMP108]], align 8
539 // CHECK1-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
540 // CHECK1-NEXT:    store i8* null, i8** [[TMP109]], align 8
541 // CHECK1-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
542 // CHECK1-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
543 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP111]], align 8
544 // CHECK1-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
545 // CHECK1-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to double**
546 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP113]], align 8
547 // CHECK1-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
548 // CHECK1-NEXT:    store i64 [[TMP67]], i64* [[TMP114]], align 8
549 // CHECK1-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
550 // CHECK1-NEXT:    store i8* null, i8** [[TMP115]], align 8
551 // CHECK1-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
552 // CHECK1-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
553 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 8
554 // CHECK1-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
555 // CHECK1-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to %struct.TT**
556 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP119]], align 8
557 // CHECK1-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
558 // CHECK1-NEXT:    store i64 16, i64* [[TMP120]], align 8
559 // CHECK1-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
560 // CHECK1-NEXT:    store i8* null, i8** [[TMP121]], align 8
561 // CHECK1-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
562 // CHECK1-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
563 // CHECK1-NEXT:    store i64 [[TMP63]], i64* [[TMP123]], align 8
564 // CHECK1-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
565 // CHECK1-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
566 // CHECK1-NEXT:    store i64 [[TMP63]], i64* [[TMP125]], align 8
567 // CHECK1-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
568 // CHECK1-NEXT:    store i64 4, i64* [[TMP126]], align 8
569 // CHECK1-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
570 // CHECK1-NEXT:    store i8* null, i8** [[TMP127]], align 8
571 // CHECK1-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
572 // CHECK1-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
573 // CHECK1-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
574 // CHECK1-NEXT:    [[TMP131:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP128]], i8** [[TMP129]], i64* [[TMP130]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
575 // CHECK1-NEXT:    [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0
576 // CHECK1-NEXT:    br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
577 // CHECK1:       omp_offload.failed23:
578 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
579 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT24]]
580 // CHECK1:       omp_offload.cont24:
581 // CHECK1-NEXT:    br label [[OMP_IF_END26:%.*]]
582 // CHECK1:       omp_if.else25:
583 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
584 // CHECK1-NEXT:    br label [[OMP_IF_END26]]
585 // CHECK1:       omp_if.end26:
586 // CHECK1-NEXT:    [[TMP133:%.*]] = load i32, i32* [[A]], align 4
587 // CHECK1-NEXT:    [[TMP134:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
588 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP134]])
589 // CHECK1-NEXT:    ret i32 [[TMP133]]
590 //
591 //
592 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
593 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
594 // CHECK1-NEXT:  entry:
595 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
596 // CHECK1-NEXT:    ret void
597 //
598 //
599 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
600 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
601 // CHECK1-NEXT:  entry:
602 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
603 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
604 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
605 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
606 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
607 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
608 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
609 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
610 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
611 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
612 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
613 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
614 // CHECK1-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
615 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
616 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
617 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
618 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
619 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
620 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
621 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
622 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
623 // CHECK1:       cond.true:
624 // CHECK1-NEXT:    br label [[COND_END:%.*]]
625 // CHECK1:       cond.false:
626 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
627 // CHECK1-NEXT:    br label [[COND_END]]
628 // CHECK1:       cond.end:
629 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
630 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
631 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
632 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
633 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
634 // CHECK1:       omp.inner.for.cond:
635 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
636 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
637 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
638 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
639 // CHECK1:       omp.inner.for.body:
640 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
641 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
642 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
643 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
644 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
645 // CHECK1:       omp.body.continue:
646 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
647 // CHECK1:       omp.inner.for.inc:
648 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
649 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
650 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
651 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
652 // CHECK1:       omp.inner.for.end:
653 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
654 // CHECK1:       omp.loop.exit:
655 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
656 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
657 // CHECK1-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
658 // CHECK1-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
659 // CHECK1:       .omp.final.then:
660 // CHECK1-NEXT:    store i32 33, i32* [[I]], align 4
661 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
662 // CHECK1:       .omp.final.done:
663 // CHECK1-NEXT:    ret void
664 //
665 //
666 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
667 // CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
668 // CHECK1-NEXT:  entry:
669 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
670 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
671 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
672 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
673 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
674 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
675 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
676 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
677 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
678 // CHECK1-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
679 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
680 // CHECK1-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
681 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
682 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
683 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
684 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
685 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
686 // CHECK1-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
687 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
688 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
689 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
690 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
691 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
692 // CHECK1-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25
693 // CHECK1-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25
694 // CHECK1-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25
695 // CHECK1-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25
696 // CHECK1-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
697 // CHECK1-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
698 // CHECK1-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
699 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
700 // CHECK1-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
701 // CHECK1:       omp_offload.failed.i:
702 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
703 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
704 // CHECK1:       .omp_outlined..1.exit:
705 // CHECK1-NEXT:    ret i32 0
706 //
707 //
708 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
709 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
710 // CHECK1-NEXT:  entry:
711 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
712 // CHECK1-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
713 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
714 // CHECK1-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
715 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
716 // CHECK1-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
717 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
718 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
719 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
720 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
721 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
722 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
723 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[K_CASTED]], align 8
724 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
725 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
726 // CHECK1-NEXT:    ret void
727 //
728 //
729 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
730 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
731 // CHECK1-NEXT:  entry:
732 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
733 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
734 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
735 // CHECK1-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
736 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
737 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
738 // CHECK1-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
739 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
740 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
741 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
742 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
743 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
744 // CHECK1-NEXT:    [[K1:%.*]] = alloca i64, align 8
745 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
746 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
747 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
748 // CHECK1-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
749 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
750 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
751 // CHECK1-NEXT:    store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
752 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
753 // CHECK1-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
754 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
755 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
756 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
757 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
758 // CHECK1-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
759 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
760 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
761 // CHECK1:       omp.dispatch.cond:
762 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
763 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
764 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
765 // CHECK1:       omp.dispatch.body:
766 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
767 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
768 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
769 // CHECK1:       omp.inner.for.cond:
770 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
771 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
772 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
773 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
774 // CHECK1:       omp.inner.for.body:
775 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
776 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
777 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
778 // CHECK1-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
779 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
780 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
781 // CHECK1-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
782 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
783 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
784 // CHECK1-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
785 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
786 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
787 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
788 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
789 // CHECK1:       omp.body.continue:
790 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
791 // CHECK1:       omp.inner.for.inc:
792 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
793 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
794 // CHECK1-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
795 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
796 // CHECK1:       omp.inner.for.end:
797 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
798 // CHECK1:       omp.dispatch.inc:
799 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
800 // CHECK1:       omp.dispatch.end:
801 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
802 // CHECK1-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
803 // CHECK1-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
804 // CHECK1:       .omp.final.then:
805 // CHECK1-NEXT:    store i32 1, i32* [[I]], align 4
806 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
807 // CHECK1:       .omp.final.done:
808 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
809 // CHECK1-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
810 // CHECK1-NEXT:    br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
811 // CHECK1:       .omp.linear.pu:
812 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
813 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP16]], 27
814 // CHECK1-NEXT:    store i64 [[ADD6]], i64* [[K_ADDR]], align 8
815 // CHECK1-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
816 // CHECK1:       .omp.linear.pu.done:
817 // CHECK1-NEXT:    ret void
818 //
819 //
820 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
821 // CHECK1-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
822 // CHECK1-NEXT:  entry:
823 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
824 // CHECK1-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
825 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
826 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
827 // CHECK1-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
828 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
829 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
830 // CHECK1-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
831 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
832 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
833 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
834 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
835 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
836 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
837 // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
838 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
839 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
840 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
841 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
842 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
843 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
844 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
845 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
846 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
847 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
848 // CHECK1-NEXT:    ret void
849 //
850 //
851 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
852 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
853 // CHECK1-NEXT:  entry:
854 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
855 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
856 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
857 // CHECK1-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
858 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
859 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
860 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
861 // CHECK1-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
862 // CHECK1-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
863 // CHECK1-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
864 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
865 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
866 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
867 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
868 // CHECK1-NEXT:    [[IT:%.*]] = alloca i64, align 8
869 // CHECK1-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
870 // CHECK1-NEXT:    [[A5:%.*]] = alloca i32, align 4
871 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
872 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
873 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
874 // CHECK1-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
875 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
876 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
877 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
878 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
879 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
880 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
881 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
882 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
883 // CHECK1-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
884 // CHECK1-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
885 // CHECK1-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
886 // CHECK1-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
887 // CHECK1-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
888 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
889 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
890 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
891 // CHECK1-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
892 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
893 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
894 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
895 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
896 // CHECK1:       cond.true:
897 // CHECK1-NEXT:    br label [[COND_END:%.*]]
898 // CHECK1:       cond.false:
899 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
900 // CHECK1-NEXT:    br label [[COND_END]]
901 // CHECK1:       cond.end:
902 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
903 // CHECK1-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
904 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
905 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
906 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
907 // CHECK1:       omp.inner.for.cond:
908 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
909 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
910 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
911 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
912 // CHECK1:       omp.inner.for.body:
913 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
914 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
915 // CHECK1-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
916 // CHECK1-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !29
917 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !29
918 // CHECK1-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
919 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
920 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
921 // CHECK1-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
922 // CHECK1-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
923 // CHECK1-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
924 // CHECK1-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !29
925 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
926 // CHECK1-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
927 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
928 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
929 // CHECK1-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
930 // CHECK1-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
931 // CHECK1-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
932 // CHECK1-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
933 // CHECK1-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
934 // CHECK1-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
935 // CHECK1-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
936 // CHECK1-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
937 // CHECK1-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
938 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
939 // CHECK1:       omp.body.continue:
940 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
941 // CHECK1:       omp.inner.for.inc:
942 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
943 // CHECK1-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
944 // CHECK1-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
945 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
946 // CHECK1:       omp.inner.for.end:
947 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
948 // CHECK1:       omp.loop.exit:
949 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
950 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
951 // CHECK1-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
952 // CHECK1-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
953 // CHECK1:       .omp.final.then:
954 // CHECK1-NEXT:    store i64 400, i64* [[IT]], align 8
955 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
956 // CHECK1:       .omp.final.done:
957 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
958 // CHECK1-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
959 // CHECK1-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
960 // CHECK1:       .omp.linear.pu:
961 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
962 // CHECK1-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
963 // CHECK1-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
964 // CHECK1-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP23]]
965 // CHECK1-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
966 // CHECK1-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
967 // CHECK1-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
968 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
969 // CHECK1-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
970 // CHECK1-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
971 // CHECK1-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP25]]
972 // CHECK1-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
973 // CHECK1-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
974 // CHECK1-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
975 // CHECK1-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
976 // CHECK1:       .omp.linear.pu.done:
977 // CHECK1-NEXT:    ret void
978 //
979 //
980 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
981 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
982 // CHECK1-NEXT:  entry:
983 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
984 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
985 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
986 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
987 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
988 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
989 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
990 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
991 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
992 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
993 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
994 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
995 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
996 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
997 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
998 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
999 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
1000 // CHECK1-NEXT:    ret void
1001 //
1002 //
1003 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
1004 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
1005 // CHECK1-NEXT:  entry:
1006 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1007 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1008 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1009 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1010 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1011 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i16, align 2
1012 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1013 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1014 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1015 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1016 // CHECK1-NEXT:    [[IT:%.*]] = alloca i16, align 2
1017 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1018 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1019 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1020 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1021 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1022 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1023 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1024 // CHECK1-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
1025 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1026 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1027 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1028 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1029 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1030 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1031 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
1032 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1033 // CHECK1:       cond.true:
1034 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1035 // CHECK1:       cond.false:
1036 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1037 // CHECK1-NEXT:    br label [[COND_END]]
1038 // CHECK1:       cond.end:
1039 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1040 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1041 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1042 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1043 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1044 // CHECK1:       omp.inner.for.cond:
1045 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1046 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
1047 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1048 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1049 // CHECK1:       omp.inner.for.body:
1050 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1051 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
1052 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
1053 // CHECK1-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
1054 // CHECK1-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
1055 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
1056 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
1057 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
1058 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
1059 // CHECK1-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
1060 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
1061 // CHECK1-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
1062 // CHECK1-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
1063 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1064 // CHECK1:       omp.body.continue:
1065 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1066 // CHECK1:       omp.inner.for.inc:
1067 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1068 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
1069 // CHECK1-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1070 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
1071 // CHECK1:       omp.inner.for.end:
1072 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1073 // CHECK1:       omp.loop.exit:
1074 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1075 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1076 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
1077 // CHECK1-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1078 // CHECK1:       .omp.final.then:
1079 // CHECK1-NEXT:    store i16 22, i16* [[IT]], align 2
1080 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1081 // CHECK1:       .omp.final.done:
1082 // CHECK1-NEXT:    ret void
1083 //
1084 //
1085 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
1086 // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
1087 // CHECK1-NEXT:  entry:
1088 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1089 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1090 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1091 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1092 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1093 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1094 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1095 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1096 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1097 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1098 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1099 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1100 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1101 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1102 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1103 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1104 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1105 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1106 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1107 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1108 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1109 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1110 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1111 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1112 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1113 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1114 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1115 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1116 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1117 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1118 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1119 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
1120 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
1121 // CHECK1-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1122 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
1123 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
1124 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
1125 // CHECK1-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
1126 // CHECK1-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
1127 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
1128 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
1129 // CHECK1-NEXT:    ret void
1130 //
1131 //
1132 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
1133 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
1134 // CHECK1-NEXT:  entry:
1135 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1136 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1137 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1138 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1139 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1140 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1141 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1142 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1143 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1144 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1145 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1146 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1147 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1148 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1149 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1150 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1151 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1152 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1153 // CHECK1-NEXT:    [[IT:%.*]] = alloca i8, align 1
1154 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1155 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1156 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1157 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1158 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1159 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1160 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1161 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1162 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1163 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1164 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1165 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1166 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1167 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1168 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1169 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1170 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1171 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1172 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1173 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1174 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1175 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
1176 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1177 // CHECK1-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
1178 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1179 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1180 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
1181 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1182 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1183 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
1184 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1185 // CHECK1:       omp.dispatch.cond:
1186 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1187 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
1188 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1189 // CHECK1:       cond.true:
1190 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1191 // CHECK1:       cond.false:
1192 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1193 // CHECK1-NEXT:    br label [[COND_END]]
1194 // CHECK1:       cond.end:
1195 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1196 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1197 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1198 // CHECK1-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1199 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1200 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1201 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1202 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1203 // CHECK1:       omp.dispatch.body:
1204 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1205 // CHECK1:       omp.inner.for.cond:
1206 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1207 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
1208 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
1209 // CHECK1-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1210 // CHECK1:       omp.inner.for.body:
1211 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1212 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
1213 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
1214 // CHECK1-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
1215 // CHECK1-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
1216 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
1217 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
1218 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
1219 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
1220 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
1221 // CHECK1-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
1222 // CHECK1-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
1223 // CHECK1-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
1224 // CHECK1-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
1225 // CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
1226 // CHECK1-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
1227 // CHECK1-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
1228 // CHECK1-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
1229 // CHECK1-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
1230 // CHECK1-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
1231 // CHECK1-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
1232 // CHECK1-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
1233 // CHECK1-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
1234 // CHECK1-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
1235 // CHECK1-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
1236 // CHECK1-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
1237 // CHECK1-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
1238 // CHECK1-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
1239 // CHECK1-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
1240 // CHECK1-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
1241 // CHECK1-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
1242 // CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
1243 // CHECK1-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
1244 // CHECK1-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
1245 // CHECK1-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !35
1246 // CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
1247 // CHECK1-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
1248 // CHECK1-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
1249 // CHECK1-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
1250 // CHECK1-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
1251 // CHECK1-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !35
1252 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1253 // CHECK1:       omp.body.continue:
1254 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1255 // CHECK1:       omp.inner.for.inc:
1256 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1257 // CHECK1-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
1258 // CHECK1-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1259 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
1260 // CHECK1:       omp.inner.for.end:
1261 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1262 // CHECK1:       omp.dispatch.inc:
1263 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1264 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1265 // CHECK1-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
1266 // CHECK1-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
1267 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1268 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1269 // CHECK1-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
1270 // CHECK1-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
1271 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
1272 // CHECK1:       omp.dispatch.end:
1273 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
1274 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1275 // CHECK1-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
1276 // CHECK1-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1277 // CHECK1:       .omp.final.then:
1278 // CHECK1-NEXT:    store i8 96, i8* [[IT]], align 1
1279 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1280 // CHECK1:       .omp.final.done:
1281 // CHECK1-NEXT:    ret void
1282 //
1283 //
1284 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1285 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1286 // CHECK1-NEXT:  entry:
1287 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1288 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1289 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1290 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1291 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1292 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1293 // CHECK1-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
1294 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
1295 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1296 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
1297 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1298 // CHECK1-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
1299 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
1300 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1301 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
1302 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1303 // CHECK1-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
1304 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
1305 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1306 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
1307 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1308 // CHECK1-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
1309 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
1310 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1311 // CHECK1-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
1312 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
1313 // CHECK1-NEXT:    ret i32 [[TMP8]]
1314 //
1315 //
1316 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1317 // CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
1318 // CHECK1-NEXT:  entry:
1319 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1320 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1321 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
1322 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
1323 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1324 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1325 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1326 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1327 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1328 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1329 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1330 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1331 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1332 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1333 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1334 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
1335 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1336 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1337 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
1338 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1339 // CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1340 // CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1341 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1342 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
1343 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1344 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
1345 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
1346 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
1347 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1348 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1349 // CHECK1:       omp_if.then:
1350 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
1351 // CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1352 // CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1353 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1354 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
1355 // CHECK1-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
1356 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1357 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
1358 // CHECK1-NEXT:    store double* [[A]], double** [[TMP13]], align 8
1359 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1360 // CHECK1-NEXT:    store i64 8, i64* [[TMP14]], align 8
1361 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1362 // CHECK1-NEXT:    store i8* null, i8** [[TMP15]], align 8
1363 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1364 // CHECK1-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1365 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
1366 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1367 // CHECK1-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1368 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
1369 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
1370 // CHECK1-NEXT:    store i64 4, i64* [[TMP20]], align 8
1371 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1372 // CHECK1-NEXT:    store i8* null, i8** [[TMP21]], align 8
1373 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1374 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
1375 // CHECK1-NEXT:    store i64 2, i64* [[TMP23]], align 8
1376 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1377 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1378 // CHECK1-NEXT:    store i64 2, i64* [[TMP25]], align 8
1379 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
1380 // CHECK1-NEXT:    store i64 8, i64* [[TMP26]], align 8
1381 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1382 // CHECK1-NEXT:    store i8* null, i8** [[TMP27]], align 8
1383 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1384 // CHECK1-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
1385 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
1386 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1387 // CHECK1-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
1388 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
1389 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1390 // CHECK1-NEXT:    store i64 8, i64* [[TMP32]], align 8
1391 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1392 // CHECK1-NEXT:    store i8* null, i8** [[TMP33]], align 8
1393 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1394 // CHECK1-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
1395 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
1396 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1397 // CHECK1-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
1398 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
1399 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1400 // CHECK1-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
1401 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1402 // CHECK1-NEXT:    store i8* null, i8** [[TMP39]], align 8
1403 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1404 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1405 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1406 // CHECK1-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1407 // CHECK1-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
1408 // CHECK1-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1409 // CHECK1:       omp_offload.failed:
1410 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
1411 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1412 // CHECK1:       omp_offload.cont:
1413 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1414 // CHECK1:       omp_if.else:
1415 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
1416 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1417 // CHECK1:       omp_if.end:
1418 // CHECK1-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
1419 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
1420 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1421 // CHECK1-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
1422 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
1423 // CHECK1-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
1424 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
1425 // CHECK1-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1426 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
1427 // CHECK1-NEXT:    ret i32 [[ADD4]]
1428 //
1429 //
1430 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1431 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1432 // CHECK1-NEXT:  entry:
1433 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1434 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1435 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1436 // CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 1
1437 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1438 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1439 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1440 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1441 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1442 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1443 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1444 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1445 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1446 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1447 // CHECK1-NEXT:    store i8 0, i8* [[AAA]], align 1
1448 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1449 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1450 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1451 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1452 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1453 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1454 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
1455 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1456 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
1457 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1458 // CHECK1-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
1459 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1460 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1461 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
1462 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1463 // CHECK1:       omp_if.then:
1464 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1465 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1466 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
1467 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1468 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1469 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
1470 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1471 // CHECK1-NEXT:    store i8* null, i8** [[TMP11]], align 8
1472 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1473 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1474 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
1475 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1476 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1477 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
1478 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1479 // CHECK1-NEXT:    store i8* null, i8** [[TMP16]], align 8
1480 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1481 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
1482 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
1483 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1484 // CHECK1-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
1485 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
1486 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1487 // CHECK1-NEXT:    store i8* null, i8** [[TMP21]], align 8
1488 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1489 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
1490 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
1491 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1492 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
1493 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
1494 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1495 // CHECK1-NEXT:    store i8* null, i8** [[TMP26]], align 8
1496 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1497 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1498 // CHECK1-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1499 // CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1500 // CHECK1-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1501 // CHECK1:       omp_offload.failed:
1502 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
1503 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1504 // CHECK1:       omp_offload.cont:
1505 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1506 // CHECK1:       omp_if.else:
1507 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
1508 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1509 // CHECK1:       omp_if.end:
1510 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
1511 // CHECK1-NEXT:    ret i32 [[TMP31]]
1512 //
1513 //
1514 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1515 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
1516 // CHECK1-NEXT:  entry:
1517 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1518 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1519 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1520 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1521 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1522 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1523 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1524 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1525 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1526 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1527 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1528 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1529 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1530 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1531 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1532 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1533 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1534 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1535 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
1536 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1537 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1538 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1539 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1540 // CHECK1:       omp_if.then:
1541 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1542 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
1543 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
1544 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1545 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1546 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
1547 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1548 // CHECK1-NEXT:    store i8* null, i8** [[TMP9]], align 8
1549 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1550 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1551 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
1552 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1553 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1554 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
1555 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1556 // CHECK1-NEXT:    store i8* null, i8** [[TMP14]], align 8
1557 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1558 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
1559 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
1560 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1561 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
1562 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
1563 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1564 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
1565 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1566 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1567 // CHECK1-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1568 // CHECK1-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1569 // CHECK1-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1570 // CHECK1:       omp_offload.failed:
1571 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
1572 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1573 // CHECK1:       omp_offload.cont:
1574 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1575 // CHECK1:       omp_if.else:
1576 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
1577 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1578 // CHECK1:       omp_if.end:
1579 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
1580 // CHECK1-NEXT:    ret i32 [[TMP24]]
1581 //
1582 //
1583 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
1584 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1585 // CHECK1-NEXT:  entry:
1586 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1587 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1588 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1589 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1590 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1591 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1592 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1593 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1594 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1595 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1596 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1597 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1598 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1599 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1600 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1601 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1602 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
1603 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1604 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
1605 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
1606 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
1607 // CHECK1-NEXT:    ret void
1608 //
1609 //
1610 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
1611 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
1612 // CHECK1-NEXT:  entry:
1613 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1614 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1615 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1616 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1617 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1618 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1619 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1620 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1621 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1622 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1623 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1624 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1625 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1626 // CHECK1-NEXT:    [[IT:%.*]] = alloca i64, align 8
1627 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1628 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1629 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1630 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1631 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1632 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1633 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1634 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1635 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1636 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1637 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1638 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1639 // CHECK1-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
1640 // CHECK1-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
1641 // CHECK1-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
1642 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1643 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1644 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1645 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
1646 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1647 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
1648 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1649 // CHECK1:       cond.true:
1650 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1651 // CHECK1:       cond.false:
1652 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1653 // CHECK1-NEXT:    br label [[COND_END]]
1654 // CHECK1:       cond.end:
1655 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1656 // CHECK1-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
1657 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
1658 // CHECK1-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
1659 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1660 // CHECK1:       omp.inner.for.cond:
1661 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
1662 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
1663 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
1664 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1665 // CHECK1:       omp.inner.for.body:
1666 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
1667 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
1668 // CHECK1-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
1669 // CHECK1-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
1670 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
1671 // CHECK1-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
1672 // CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
1673 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1674 // CHECK1-NEXT:    store double [[ADD]], double* [[A]], align 8, !llvm.access.group !38
1675 // CHECK1-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
1676 // CHECK1-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !38
1677 // CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
1678 // CHECK1-NEXT:    store double [[INC]], double* [[A5]], align 8, !llvm.access.group !38
1679 // CHECK1-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
1680 // CHECK1-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
1681 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
1682 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1683 // CHECK1-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !38
1684 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1685 // CHECK1:       omp.body.continue:
1686 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1687 // CHECK1:       omp.inner.for.inc:
1688 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
1689 // CHECK1-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
1690 // CHECK1-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
1691 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
1692 // CHECK1:       omp.inner.for.end:
1693 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1694 // CHECK1:       omp.loop.exit:
1695 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
1696 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1697 // CHECK1-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
1698 // CHECK1-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1699 // CHECK1:       .omp.final.then:
1700 // CHECK1-NEXT:    store i64 400, i64* [[IT]], align 8
1701 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1702 // CHECK1:       .omp.final.done:
1703 // CHECK1-NEXT:    ret void
1704 //
1705 //
1706 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
1707 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1708 // CHECK1-NEXT:  entry:
1709 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1710 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1711 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1712 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1713 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1714 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1715 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1716 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1717 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1718 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1719 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1720 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1721 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1722 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1723 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1724 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1725 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1726 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
1727 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1728 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
1729 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1730 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
1731 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1732 // CHECK1-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
1733 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1734 // CHECK1-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
1735 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1736 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
1737 // CHECK1-NEXT:    ret void
1738 //
1739 //
1740 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
1741 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
1742 // CHECK1-NEXT:  entry:
1743 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1744 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1745 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1746 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1747 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1748 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1749 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1750 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1751 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1752 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1753 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1754 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1755 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1756 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1757 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1758 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1759 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1760 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1761 // CHECK1-NEXT:    ret void
1762 //
1763 //
1764 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
1765 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1766 // CHECK1-NEXT:  entry:
1767 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1768 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1769 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1770 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1771 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1772 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1773 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1774 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1775 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1776 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1777 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1778 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1779 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1780 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
1781 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1782 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
1783 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1784 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
1785 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1786 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
1787 // CHECK1-NEXT:    ret void
1788 //
1789 //
1790 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14
1791 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
1792 // CHECK1-NEXT:  entry:
1793 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1794 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1795 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1796 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1797 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1798 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1799 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1800 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1801 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1802 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1803 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1804 // CHECK1-NEXT:    [[I:%.*]] = alloca i64, align 8
1805 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1806 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1807 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1808 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1809 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1810 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1811 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1812 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1813 // CHECK1-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
1814 // CHECK1-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
1815 // CHECK1-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
1816 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1817 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1818 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1819 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
1820 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1821 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
1822 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1823 // CHECK1:       cond.true:
1824 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1825 // CHECK1:       cond.false:
1826 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1827 // CHECK1-NEXT:    br label [[COND_END]]
1828 // CHECK1:       cond.end:
1829 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1830 // CHECK1-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
1831 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
1832 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
1833 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1834 // CHECK1:       omp.inner.for.cond:
1835 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
1836 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !41
1837 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
1838 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1839 // CHECK1:       omp.inner.for.body:
1840 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
1841 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
1842 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
1843 // CHECK1-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41
1844 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41
1845 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
1846 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !41
1847 // CHECK1-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !41
1848 // CHECK1-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
1849 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
1850 // CHECK1-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
1851 // CHECK1-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !41
1852 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1853 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
1854 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
1855 // CHECK1-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
1856 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1857 // CHECK1:       omp.body.continue:
1858 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1859 // CHECK1:       omp.inner.for.inc:
1860 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
1861 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
1862 // CHECK1-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
1863 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
1864 // CHECK1:       omp.inner.for.end:
1865 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1866 // CHECK1:       omp.loop.exit:
1867 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
1868 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1869 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1870 // CHECK1-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1871 // CHECK1:       .omp.final.then:
1872 // CHECK1-NEXT:    store i64 11, i64* [[I]], align 8
1873 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1874 // CHECK1:       .omp.final.done:
1875 // CHECK1-NEXT:    ret void
1876 //
1877 //
1878 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1879 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] {
1880 // CHECK1-NEXT:  entry:
1881 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
1882 // CHECK1-NEXT:    ret void
1883 //
1884 //
1885 // CHECK2-LABEL: define {{[^@]+}}@_Z7get_valv
1886 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
1887 // CHECK2-NEXT:  entry:
1888 // CHECK2-NEXT:    ret i64 0
1889 //
1890 //
1891 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi
1892 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1893 // CHECK2-NEXT:  entry:
1894 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1895 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
1896 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
1897 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
1898 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
1899 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1900 // CHECK2-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
1901 // CHECK2-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
1902 // CHECK2-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
1903 // CHECK2-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
1904 // CHECK2-NEXT:    [[K:%.*]] = alloca i64, align 8
1905 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1906 // CHECK2-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
1907 // CHECK2-NEXT:    [[LIN:%.*]] = alloca i32, align 4
1908 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1909 // CHECK2-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
1910 // CHECK2-NEXT:    [[A_CASTED4:%.*]] = alloca i64, align 8
1911 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1912 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1913 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1914 // CHECK2-NEXT:    [[A_CASTED6:%.*]] = alloca i64, align 8
1915 // CHECK2-NEXT:    [[AA_CASTED8:%.*]] = alloca i64, align 8
1916 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
1917 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
1918 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
1919 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1920 // CHECK2-NEXT:    [[A_CASTED15:%.*]] = alloca i64, align 8
1921 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1922 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
1923 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
1924 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
1925 // CHECK2-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
1926 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
1927 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1928 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
1929 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
1930 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1931 // CHECK2-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1932 // CHECK2-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
1933 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1934 // CHECK2-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
1935 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1936 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1937 // CHECK2-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
1938 // CHECK2-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
1939 // CHECK2-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
1940 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
1941 // CHECK2-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
1942 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
1943 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
1944 // CHECK2-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]])
1945 // CHECK2-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
1946 // CHECK2-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
1947 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
1948 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1949 // CHECK2-NEXT:    store i32 [[TMP11]], i32* [[CONV]], align 4
1950 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
1951 // CHECK2-NEXT:    [[TMP13:%.*]] = load i64, i64* [[K]], align 8
1952 // CHECK2-NEXT:    store i64 [[TMP13]], i64* [[K_CASTED]], align 8
1953 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8
1954 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]]
1955 // CHECK2-NEXT:    store i32 12, i32* [[LIN]], align 4
1956 // CHECK2-NEXT:    [[TMP15:%.*]] = load i16, i16* [[AA]], align 2
1957 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1958 // CHECK2-NEXT:    store i16 [[TMP15]], i16* [[CONV2]], align 2
1959 // CHECK2-NEXT:    [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1960 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4
1961 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
1962 // CHECK2-NEXT:    store i32 [[TMP17]], i32* [[CONV3]], align 4
1963 // CHECK2-NEXT:    [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
1964 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A]], align 4
1965 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
1966 // CHECK2-NEXT:    store i32 [[TMP19]], i32* [[CONV5]], align 4
1967 // CHECK2-NEXT:    [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8
1968 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1969 // CHECK2-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
1970 // CHECK2-NEXT:    store i64 [[TMP16]], i64* [[TMP22]], align 8
1971 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1972 // CHECK2-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
1973 // CHECK2-NEXT:    store i64 [[TMP16]], i64* [[TMP24]], align 8
1974 // CHECK2-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1975 // CHECK2-NEXT:    store i8* null, i8** [[TMP25]], align 8
1976 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1977 // CHECK2-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1978 // CHECK2-NEXT:    store i64 [[TMP18]], i64* [[TMP27]], align 8
1979 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1980 // CHECK2-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
1981 // CHECK2-NEXT:    store i64 [[TMP18]], i64* [[TMP29]], align 8
1982 // CHECK2-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1983 // CHECK2-NEXT:    store i8* null, i8** [[TMP30]], align 8
1984 // CHECK2-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1985 // CHECK2-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
1986 // CHECK2-NEXT:    store i64 [[TMP20]], i64* [[TMP32]], align 8
1987 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1988 // CHECK2-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
1989 // CHECK2-NEXT:    store i64 [[TMP20]], i64* [[TMP34]], align 8
1990 // CHECK2-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1991 // CHECK2-NEXT:    store i8* null, i8** [[TMP35]], align 8
1992 // CHECK2-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1993 // CHECK2-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1994 // CHECK2-NEXT:    [[TMP38:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1995 // CHECK2-NEXT:    [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
1996 // CHECK2-NEXT:    br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1997 // CHECK2:       omp_offload.failed:
1998 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]]
1999 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2000 // CHECK2:       omp_offload.cont:
2001 // CHECK2-NEXT:    [[TMP40:%.*]] = load i32, i32* [[A]], align 4
2002 // CHECK2-NEXT:    [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
2003 // CHECK2-NEXT:    store i32 [[TMP40]], i32* [[CONV7]], align 4
2004 // CHECK2-NEXT:    [[TMP41:%.*]] = load i64, i64* [[A_CASTED6]], align 8
2005 // CHECK2-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2
2006 // CHECK2-NEXT:    [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
2007 // CHECK2-NEXT:    store i16 [[TMP42]], i16* [[CONV9]], align 2
2008 // CHECK2-NEXT:    [[TMP43:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
2009 // CHECK2-NEXT:    [[TMP44:%.*]] = load i32, i32* [[N_ADDR]], align 4
2010 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP44]], 10
2011 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2012 // CHECK2:       omp_if.then:
2013 // CHECK2-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
2014 // CHECK2-NEXT:    [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
2015 // CHECK2-NEXT:    store i64 [[TMP41]], i64* [[TMP46]], align 8
2016 // CHECK2-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
2017 // CHECK2-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
2018 // CHECK2-NEXT:    store i64 [[TMP41]], i64* [[TMP48]], align 8
2019 // CHECK2-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
2020 // CHECK2-NEXT:    store i8* null, i8** [[TMP49]], align 8
2021 // CHECK2-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
2022 // CHECK2-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
2023 // CHECK2-NEXT:    store i64 [[TMP43]], i64* [[TMP51]], align 8
2024 // CHECK2-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
2025 // CHECK2-NEXT:    [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
2026 // CHECK2-NEXT:    store i64 [[TMP43]], i64* [[TMP53]], align 8
2027 // CHECK2-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
2028 // CHECK2-NEXT:    store i8* null, i8** [[TMP54]], align 8
2029 // CHECK2-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
2030 // CHECK2-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
2031 // CHECK2-NEXT:    [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2032 // CHECK2-NEXT:    [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
2033 // CHECK2-NEXT:    br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
2034 // CHECK2:       omp_offload.failed13:
2035 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
2036 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT14]]
2037 // CHECK2:       omp_offload.cont14:
2038 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
2039 // CHECK2:       omp_if.else:
2040 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
2041 // CHECK2-NEXT:    br label [[OMP_IF_END]]
2042 // CHECK2:       omp_if.end:
2043 // CHECK2-NEXT:    [[TMP59:%.*]] = load i32, i32* [[A]], align 4
2044 // CHECK2-NEXT:    store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_]], align 4
2045 // CHECK2-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
2046 // CHECK2-NEXT:    [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
2047 // CHECK2-NEXT:    store i32 [[TMP60]], i32* [[CONV16]], align 4
2048 // CHECK2-NEXT:    [[TMP61:%.*]] = load i64, i64* [[A_CASTED15]], align 8
2049 // CHECK2-NEXT:    [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2050 // CHECK2-NEXT:    [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
2051 // CHECK2-NEXT:    store i32 [[TMP62]], i32* [[CONV17]], align 4
2052 // CHECK2-NEXT:    [[TMP63:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
2053 // CHECK2-NEXT:    [[TMP64:%.*]] = load i32, i32* [[N_ADDR]], align 4
2054 // CHECK2-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP64]], 20
2055 // CHECK2-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
2056 // CHECK2:       omp_if.then19:
2057 // CHECK2-NEXT:    [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4
2058 // CHECK2-NEXT:    [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]]
2059 // CHECK2-NEXT:    [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8
2060 // CHECK2-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
2061 // CHECK2-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
2062 // CHECK2-NEXT:    store i64 [[TMP61]], i64* [[TMP69]], align 8
2063 // CHECK2-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
2064 // CHECK2-NEXT:    [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64*
2065 // CHECK2-NEXT:    store i64 [[TMP61]], i64* [[TMP71]], align 8
2066 // CHECK2-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2067 // CHECK2-NEXT:    store i64 4, i64* [[TMP72]], align 8
2068 // CHECK2-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
2069 // CHECK2-NEXT:    store i8* null, i8** [[TMP73]], align 8
2070 // CHECK2-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
2071 // CHECK2-NEXT:    [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
2072 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 8
2073 // CHECK2-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
2074 // CHECK2-NEXT:    [[TMP77:%.*]] = bitcast i8** [[TMP76]] to [10 x float]**
2075 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP77]], align 8
2076 // CHECK2-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
2077 // CHECK2-NEXT:    store i64 40, i64* [[TMP78]], align 8
2078 // CHECK2-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
2079 // CHECK2-NEXT:    store i8* null, i8** [[TMP79]], align 8
2080 // CHECK2-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
2081 // CHECK2-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
2082 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP81]], align 8
2083 // CHECK2-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
2084 // CHECK2-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
2085 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP83]], align 8
2086 // CHECK2-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
2087 // CHECK2-NEXT:    store i64 8, i64* [[TMP84]], align 8
2088 // CHECK2-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
2089 // CHECK2-NEXT:    store i8* null, i8** [[TMP85]], align 8
2090 // CHECK2-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
2091 // CHECK2-NEXT:    [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
2092 // CHECK2-NEXT:    store float* [[VLA]], float** [[TMP87]], align 8
2093 // CHECK2-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
2094 // CHECK2-NEXT:    [[TMP89:%.*]] = bitcast i8** [[TMP88]] to float**
2095 // CHECK2-NEXT:    store float* [[VLA]], float** [[TMP89]], align 8
2096 // CHECK2-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2097 // CHECK2-NEXT:    store i64 [[TMP65]], i64* [[TMP90]], align 8
2098 // CHECK2-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
2099 // CHECK2-NEXT:    store i8* null, i8** [[TMP91]], align 8
2100 // CHECK2-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
2101 // CHECK2-NEXT:    [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
2102 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 8
2103 // CHECK2-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
2104 // CHECK2-NEXT:    [[TMP95:%.*]] = bitcast i8** [[TMP94]] to [5 x [10 x double]]**
2105 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP95]], align 8
2106 // CHECK2-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2107 // CHECK2-NEXT:    store i64 400, i64* [[TMP96]], align 8
2108 // CHECK2-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
2109 // CHECK2-NEXT:    store i8* null, i8** [[TMP97]], align 8
2110 // CHECK2-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
2111 // CHECK2-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
2112 // CHECK2-NEXT:    store i64 5, i64* [[TMP99]], align 8
2113 // CHECK2-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
2114 // CHECK2-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
2115 // CHECK2-NEXT:    store i64 5, i64* [[TMP101]], align 8
2116 // CHECK2-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
2117 // CHECK2-NEXT:    store i64 8, i64* [[TMP102]], align 8
2118 // CHECK2-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
2119 // CHECK2-NEXT:    store i8* null, i8** [[TMP103]], align 8
2120 // CHECK2-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
2121 // CHECK2-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64*
2122 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP105]], align 8
2123 // CHECK2-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
2124 // CHECK2-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
2125 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP107]], align 8
2126 // CHECK2-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
2127 // CHECK2-NEXT:    store i64 8, i64* [[TMP108]], align 8
2128 // CHECK2-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
2129 // CHECK2-NEXT:    store i8* null, i8** [[TMP109]], align 8
2130 // CHECK2-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
2131 // CHECK2-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
2132 // CHECK2-NEXT:    store double* [[VLA1]], double** [[TMP111]], align 8
2133 // CHECK2-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
2134 // CHECK2-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to double**
2135 // CHECK2-NEXT:    store double* [[VLA1]], double** [[TMP113]], align 8
2136 // CHECK2-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2137 // CHECK2-NEXT:    store i64 [[TMP67]], i64* [[TMP114]], align 8
2138 // CHECK2-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
2139 // CHECK2-NEXT:    store i8* null, i8** [[TMP115]], align 8
2140 // CHECK2-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
2141 // CHECK2-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
2142 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 8
2143 // CHECK2-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
2144 // CHECK2-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to %struct.TT**
2145 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP119]], align 8
2146 // CHECK2-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
2147 // CHECK2-NEXT:    store i64 16, i64* [[TMP120]], align 8
2148 // CHECK2-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
2149 // CHECK2-NEXT:    store i8* null, i8** [[TMP121]], align 8
2150 // CHECK2-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
2151 // CHECK2-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
2152 // CHECK2-NEXT:    store i64 [[TMP63]], i64* [[TMP123]], align 8
2153 // CHECK2-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
2154 // CHECK2-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
2155 // CHECK2-NEXT:    store i64 [[TMP63]], i64* [[TMP125]], align 8
2156 // CHECK2-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
2157 // CHECK2-NEXT:    store i64 4, i64* [[TMP126]], align 8
2158 // CHECK2-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
2159 // CHECK2-NEXT:    store i8* null, i8** [[TMP127]], align 8
2160 // CHECK2-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
2161 // CHECK2-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
2162 // CHECK2-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2163 // CHECK2-NEXT:    [[TMP131:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP128]], i8** [[TMP129]], i64* [[TMP130]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2164 // CHECK2-NEXT:    [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0
2165 // CHECK2-NEXT:    br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
2166 // CHECK2:       omp_offload.failed23:
2167 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
2168 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT24]]
2169 // CHECK2:       omp_offload.cont24:
2170 // CHECK2-NEXT:    br label [[OMP_IF_END26:%.*]]
2171 // CHECK2:       omp_if.else25:
2172 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
2173 // CHECK2-NEXT:    br label [[OMP_IF_END26]]
2174 // CHECK2:       omp_if.end26:
2175 // CHECK2-NEXT:    [[TMP133:%.*]] = load i32, i32* [[A]], align 4
2176 // CHECK2-NEXT:    [[TMP134:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
2177 // CHECK2-NEXT:    call void @llvm.stackrestore(i8* [[TMP134]])
2178 // CHECK2-NEXT:    ret i32 [[TMP133]]
2179 //
2180 //
2181 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
2182 // CHECK2-SAME: () #[[ATTR2:[0-9]+]] {
2183 // CHECK2-NEXT:  entry:
2184 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2185 // CHECK2-NEXT:    ret void
2186 //
2187 //
2188 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
2189 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
2190 // CHECK2-NEXT:  entry:
2191 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2192 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2193 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2194 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2195 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2196 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2197 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2198 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2199 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2200 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2201 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2202 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2203 // CHECK2-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
2204 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2205 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2206 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2207 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2208 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2209 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2210 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
2211 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2212 // CHECK2:       cond.true:
2213 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2214 // CHECK2:       cond.false:
2215 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2216 // CHECK2-NEXT:    br label [[COND_END]]
2217 // CHECK2:       cond.end:
2218 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2219 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2220 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2221 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2222 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2223 // CHECK2:       omp.inner.for.cond:
2224 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
2225 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
2226 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2227 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2228 // CHECK2:       omp.inner.for.body:
2229 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
2230 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
2231 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
2232 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
2233 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2234 // CHECK2:       omp.body.continue:
2235 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2236 // CHECK2:       omp.inner.for.inc:
2237 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
2238 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2239 // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
2240 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
2241 // CHECK2:       omp.inner.for.end:
2242 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2243 // CHECK2:       omp.loop.exit:
2244 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2245 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2246 // CHECK2-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
2247 // CHECK2-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2248 // CHECK2:       .omp.final.then:
2249 // CHECK2-NEXT:    store i32 33, i32* [[I]], align 4
2250 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2251 // CHECK2:       .omp.final.done:
2252 // CHECK2-NEXT:    ret void
2253 //
2254 //
2255 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry.
2256 // CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
2257 // CHECK2-NEXT:  entry:
2258 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2259 // CHECK2-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
2260 // CHECK2-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
2261 // CHECK2-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
2262 // CHECK2-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
2263 // CHECK2-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
2264 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2265 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
2266 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
2267 // CHECK2-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
2268 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
2269 // CHECK2-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
2270 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
2271 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
2272 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
2273 // CHECK2-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
2274 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
2275 // CHECK2-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
2276 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
2277 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
2278 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
2279 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
2280 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
2281 // CHECK2-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25
2282 // CHECK2-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25
2283 // CHECK2-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25
2284 // CHECK2-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25
2285 // CHECK2-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
2286 // CHECK2-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
2287 // CHECK2-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
2288 // CHECK2-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2289 // CHECK2-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
2290 // CHECK2:       omp_offload.failed.i:
2291 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
2292 // CHECK2-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
2293 // CHECK2:       .omp_outlined..1.exit:
2294 // CHECK2-NEXT:    ret i32 0
2295 //
2296 //
2297 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
2298 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
2299 // CHECK2-NEXT:  entry:
2300 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2301 // CHECK2-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
2302 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2303 // CHECK2-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
2304 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2305 // CHECK2-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
2306 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2307 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2308 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2309 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
2310 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2311 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
2312 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[K_CASTED]], align 8
2313 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
2314 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
2315 // CHECK2-NEXT:    ret void
2316 //
2317 //
2318 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
2319 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
2320 // CHECK2-NEXT:  entry:
2321 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2322 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2323 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2324 // CHECK2-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
2325 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2326 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2327 // CHECK2-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
2328 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2329 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2330 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2331 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2332 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2333 // CHECK2-NEXT:    [[K1:%.*]] = alloca i64, align 8
2334 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2335 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2336 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2337 // CHECK2-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
2338 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2339 // CHECK2-NEXT:    [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
2340 // CHECK2-NEXT:    store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
2341 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2342 // CHECK2-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
2343 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2344 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2345 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2346 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
2347 // CHECK2-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
2348 // CHECK2-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
2349 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2350 // CHECK2:       omp.dispatch.cond:
2351 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
2352 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
2353 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2354 // CHECK2:       omp.dispatch.body:
2355 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2356 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2357 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2358 // CHECK2:       omp.inner.for.cond:
2359 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
2360 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
2361 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2362 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2363 // CHECK2:       omp.inner.for.body:
2364 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
2365 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2366 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
2367 // CHECK2-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
2368 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
2369 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
2370 // CHECK2-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
2371 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
2372 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
2373 // CHECK2-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
2374 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
2375 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
2376 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
2377 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2378 // CHECK2:       omp.body.continue:
2379 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2380 // CHECK2:       omp.inner.for.inc:
2381 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
2382 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
2383 // CHECK2-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
2384 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
2385 // CHECK2:       omp.inner.for.end:
2386 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2387 // CHECK2:       omp.dispatch.inc:
2388 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
2389 // CHECK2:       omp.dispatch.end:
2390 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2391 // CHECK2-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
2392 // CHECK2-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2393 // CHECK2:       .omp.final.then:
2394 // CHECK2-NEXT:    store i32 1, i32* [[I]], align 4
2395 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2396 // CHECK2:       .omp.final.done:
2397 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2398 // CHECK2-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
2399 // CHECK2-NEXT:    br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
2400 // CHECK2:       .omp.linear.pu:
2401 // CHECK2-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
2402 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP16]], 27
2403 // CHECK2-NEXT:    store i64 [[ADD6]], i64* [[K_ADDR]], align 8
2404 // CHECK2-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
2405 // CHECK2:       .omp.linear.pu.done:
2406 // CHECK2-NEXT:    ret void
2407 //
2408 //
2409 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
2410 // CHECK2-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
2411 // CHECK2-NEXT:  entry:
2412 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2413 // CHECK2-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
2414 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2415 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2416 // CHECK2-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
2417 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2418 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2419 // CHECK2-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
2420 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2421 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2422 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
2423 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2424 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
2425 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2426 // CHECK2-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
2427 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2428 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
2429 // CHECK2-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
2430 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
2431 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
2432 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
2433 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2434 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
2435 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
2436 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
2437 // CHECK2-NEXT:    ret void
2438 //
2439 //
2440 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
2441 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
2442 // CHECK2-NEXT:  entry:
2443 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2444 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2445 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2446 // CHECK2-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
2447 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2448 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
2449 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i64, align 8
2450 // CHECK2-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
2451 // CHECK2-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
2452 // CHECK2-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
2453 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2454 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2455 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2456 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2457 // CHECK2-NEXT:    [[IT:%.*]] = alloca i64, align 8
2458 // CHECK2-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
2459 // CHECK2-NEXT:    [[A5:%.*]] = alloca i32, align 4
2460 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2461 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2462 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2463 // CHECK2-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
2464 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2465 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2466 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
2467 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2468 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
2469 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
2470 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
2471 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
2472 // CHECK2-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
2473 // CHECK2-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
2474 // CHECK2-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
2475 // CHECK2-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
2476 // CHECK2-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
2477 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2478 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2479 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2480 // CHECK2-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
2481 // CHECK2-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
2482 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2483 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
2484 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2485 // CHECK2:       cond.true:
2486 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2487 // CHECK2:       cond.false:
2488 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
2489 // CHECK2-NEXT:    br label [[COND_END]]
2490 // CHECK2:       cond.end:
2491 // CHECK2-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2492 // CHECK2-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
2493 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
2494 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
2495 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2496 // CHECK2:       omp.inner.for.cond:
2497 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
2498 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
2499 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
2500 // CHECK2-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2501 // CHECK2:       omp.inner.for.body:
2502 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
2503 // CHECK2-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
2504 // CHECK2-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
2505 // CHECK2-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !29
2506 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !29
2507 // CHECK2-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
2508 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
2509 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
2510 // CHECK2-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
2511 // CHECK2-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
2512 // CHECK2-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
2513 // CHECK2-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !29
2514 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
2515 // CHECK2-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
2516 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
2517 // CHECK2-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
2518 // CHECK2-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
2519 // CHECK2-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
2520 // CHECK2-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
2521 // CHECK2-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
2522 // CHECK2-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
2523 // CHECK2-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
2524 // CHECK2-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
2525 // CHECK2-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
2526 // CHECK2-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
2527 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2528 // CHECK2:       omp.body.continue:
2529 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2530 // CHECK2:       omp.inner.for.inc:
2531 // CHECK2-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
2532 // CHECK2-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
2533 // CHECK2-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
2534 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
2535 // CHECK2:       omp.inner.for.end:
2536 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2537 // CHECK2:       omp.loop.exit:
2538 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2539 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2540 // CHECK2-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
2541 // CHECK2-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2542 // CHECK2:       .omp.final.then:
2543 // CHECK2-NEXT:    store i64 400, i64* [[IT]], align 8
2544 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2545 // CHECK2:       .omp.final.done:
2546 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2547 // CHECK2-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
2548 // CHECK2-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
2549 // CHECK2:       .omp.linear.pu:
2550 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
2551 // CHECK2-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
2552 // CHECK2-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
2553 // CHECK2-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP23]]
2554 // CHECK2-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
2555 // CHECK2-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
2556 // CHECK2-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
2557 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
2558 // CHECK2-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
2559 // CHECK2-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
2560 // CHECK2-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP25]]
2561 // CHECK2-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
2562 // CHECK2-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
2563 // CHECK2-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
2564 // CHECK2-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
2565 // CHECK2:       .omp.linear.pu.done:
2566 // CHECK2-NEXT:    ret void
2567 //
2568 //
2569 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
2570 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2571 // CHECK2-NEXT:  entry:
2572 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2573 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2574 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2575 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2576 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2577 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2578 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2579 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2580 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2581 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2582 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
2583 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2584 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
2585 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2586 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
2587 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2588 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
2589 // CHECK2-NEXT:    ret void
2590 //
2591 //
2592 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
2593 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
2594 // CHECK2-NEXT:  entry:
2595 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2596 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2597 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2598 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2599 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2600 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i16, align 2
2601 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2602 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2603 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2604 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2605 // CHECK2-NEXT:    [[IT:%.*]] = alloca i16, align 2
2606 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2607 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2608 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2609 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2610 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2611 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2612 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2613 // CHECK2-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
2614 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2615 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2616 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2617 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2618 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2619 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2620 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
2621 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2622 // CHECK2:       cond.true:
2623 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2624 // CHECK2:       cond.false:
2625 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2626 // CHECK2-NEXT:    br label [[COND_END]]
2627 // CHECK2:       cond.end:
2628 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2629 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2630 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2631 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2632 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2633 // CHECK2:       omp.inner.for.cond:
2634 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
2635 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
2636 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2637 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2638 // CHECK2:       omp.inner.for.body:
2639 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
2640 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
2641 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
2642 // CHECK2-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
2643 // CHECK2-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
2644 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
2645 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
2646 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
2647 // CHECK2-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
2648 // CHECK2-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
2649 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
2650 // CHECK2-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
2651 // CHECK2-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
2652 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2653 // CHECK2:       omp.body.continue:
2654 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2655 // CHECK2:       omp.inner.for.inc:
2656 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
2657 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
2658 // CHECK2-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
2659 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
2660 // CHECK2:       omp.inner.for.end:
2661 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2662 // CHECK2:       omp.loop.exit:
2663 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2664 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2665 // CHECK2-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2666 // CHECK2-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2667 // CHECK2:       .omp.final.then:
2668 // CHECK2-NEXT:    store i16 22, i16* [[IT]], align 2
2669 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2670 // CHECK2:       .omp.final.done:
2671 // CHECK2-NEXT:    ret void
2672 //
2673 //
2674 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
2675 // CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
2676 // CHECK2-NEXT:  entry:
2677 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2678 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
2679 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2680 // CHECK2-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
2681 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
2682 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2683 // CHECK2-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
2684 // CHECK2-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
2685 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
2686 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2687 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2688 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2689 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2690 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
2691 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2692 // CHECK2-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
2693 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
2694 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2695 // CHECK2-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
2696 // CHECK2-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
2697 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
2698 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2699 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2700 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
2701 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2702 // CHECK2-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
2703 // CHECK2-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
2704 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2705 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
2706 // CHECK2-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
2707 // CHECK2-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
2708 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
2709 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
2710 // CHECK2-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2711 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
2712 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
2713 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
2714 // CHECK2-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
2715 // CHECK2-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
2716 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
2717 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
2718 // CHECK2-NEXT:    ret void
2719 //
2720 //
2721 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
2722 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
2723 // CHECK2-NEXT:  entry:
2724 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2725 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2726 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2727 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
2728 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2729 // CHECK2-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
2730 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
2731 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2732 // CHECK2-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
2733 // CHECK2-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
2734 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
2735 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2736 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2737 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2738 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2739 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2740 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2741 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2742 // CHECK2-NEXT:    [[IT:%.*]] = alloca i8, align 1
2743 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2744 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2745 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2746 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
2747 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2748 // CHECK2-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
2749 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
2750 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2751 // CHECK2-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
2752 // CHECK2-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
2753 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
2754 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2755 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2756 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
2757 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2758 // CHECK2-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
2759 // CHECK2-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
2760 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2761 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
2762 // CHECK2-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
2763 // CHECK2-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
2764 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
2765 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2766 // CHECK2-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
2767 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2768 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2769 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
2770 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2771 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
2772 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
2773 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2774 // CHECK2:       omp.dispatch.cond:
2775 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2776 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
2777 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2778 // CHECK2:       cond.true:
2779 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2780 // CHECK2:       cond.false:
2781 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2782 // CHECK2-NEXT:    br label [[COND_END]]
2783 // CHECK2:       cond.end:
2784 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
2785 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2786 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2787 // CHECK2-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
2788 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2789 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2790 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
2791 // CHECK2-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2792 // CHECK2:       omp.dispatch.body:
2793 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2794 // CHECK2:       omp.inner.for.cond:
2795 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
2796 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
2797 // CHECK2-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
2798 // CHECK2-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2799 // CHECK2:       omp.inner.for.body:
2800 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
2801 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
2802 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
2803 // CHECK2-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
2804 // CHECK2-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
2805 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
2806 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
2807 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
2808 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
2809 // CHECK2-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
2810 // CHECK2-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
2811 // CHECK2-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
2812 // CHECK2-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
2813 // CHECK2-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
2814 // CHECK2-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
2815 // CHECK2-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
2816 // CHECK2-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
2817 // CHECK2-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
2818 // CHECK2-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
2819 // CHECK2-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
2820 // CHECK2-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
2821 // CHECK2-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
2822 // CHECK2-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
2823 // CHECK2-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
2824 // CHECK2-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
2825 // CHECK2-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
2826 // CHECK2-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
2827 // CHECK2-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
2828 // CHECK2-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
2829 // CHECK2-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
2830 // CHECK2-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
2831 // CHECK2-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
2832 // CHECK2-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
2833 // CHECK2-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
2834 // CHECK2-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !35
2835 // CHECK2-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
2836 // CHECK2-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
2837 // CHECK2-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
2838 // CHECK2-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
2839 // CHECK2-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
2840 // CHECK2-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !35
2841 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2842 // CHECK2:       omp.body.continue:
2843 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2844 // CHECK2:       omp.inner.for.inc:
2845 // CHECK2-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
2846 // CHECK2-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
2847 // CHECK2-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
2848 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
2849 // CHECK2:       omp.inner.for.end:
2850 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2851 // CHECK2:       omp.dispatch.inc:
2852 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2853 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2854 // CHECK2-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
2855 // CHECK2-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
2856 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2857 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2858 // CHECK2-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
2859 // CHECK2-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
2860 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
2861 // CHECK2:       omp.dispatch.end:
2862 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
2863 // CHECK2-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2864 // CHECK2-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
2865 // CHECK2-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2866 // CHECK2:       .omp.final.then:
2867 // CHECK2-NEXT:    store i8 96, i8* [[IT]], align 1
2868 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2869 // CHECK2:       .omp.final.done:
2870 // CHECK2-NEXT:    ret void
2871 //
2872 //
2873 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari
2874 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
2875 // CHECK2-NEXT:  entry:
2876 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2877 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
2878 // CHECK2-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
2879 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2880 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
2881 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2882 // CHECK2-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
2883 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
2884 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
2885 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2886 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2887 // CHECK2-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
2888 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2889 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
2890 // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
2891 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2892 // CHECK2-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
2893 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
2894 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
2895 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
2896 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
2897 // CHECK2-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
2898 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
2899 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
2900 // CHECK2-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
2901 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
2902 // CHECK2-NEXT:    ret i32 [[TMP8]]
2903 //
2904 //
2905 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
2906 // CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
2907 // CHECK2-NEXT:  entry:
2908 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2909 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2910 // CHECK2-NEXT:    [[B:%.*]] = alloca i32, align 4
2911 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
2912 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2913 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
2914 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
2915 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
2916 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
2917 // CHECK2-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
2918 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2919 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2920 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2921 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2922 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2923 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
2924 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2925 // CHECK2-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2926 // CHECK2-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
2927 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
2928 // CHECK2-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
2929 // CHECK2-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
2930 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
2931 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
2932 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
2933 // CHECK2-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
2934 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
2935 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
2936 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
2937 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2938 // CHECK2:       omp_if.then:
2939 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
2940 // CHECK2-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
2941 // CHECK2-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
2942 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2943 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
2944 // CHECK2-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
2945 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2946 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
2947 // CHECK2-NEXT:    store double* [[A]], double** [[TMP13]], align 8
2948 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2949 // CHECK2-NEXT:    store i64 8, i64* [[TMP14]], align 8
2950 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2951 // CHECK2-NEXT:    store i8* null, i8** [[TMP15]], align 8
2952 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2953 // CHECK2-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
2954 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
2955 // CHECK2-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2956 // CHECK2-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
2957 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
2958 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
2959 // CHECK2-NEXT:    store i64 4, i64* [[TMP20]], align 8
2960 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2961 // CHECK2-NEXT:    store i8* null, i8** [[TMP21]], align 8
2962 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2963 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
2964 // CHECK2-NEXT:    store i64 2, i64* [[TMP23]], align 8
2965 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2966 // CHECK2-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
2967 // CHECK2-NEXT:    store i64 2, i64* [[TMP25]], align 8
2968 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
2969 // CHECK2-NEXT:    store i64 8, i64* [[TMP26]], align 8
2970 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2971 // CHECK2-NEXT:    store i8* null, i8** [[TMP27]], align 8
2972 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2973 // CHECK2-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
2974 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
2975 // CHECK2-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2976 // CHECK2-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
2977 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
2978 // CHECK2-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2979 // CHECK2-NEXT:    store i64 8, i64* [[TMP32]], align 8
2980 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2981 // CHECK2-NEXT:    store i8* null, i8** [[TMP33]], align 8
2982 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2983 // CHECK2-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
2984 // CHECK2-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
2985 // CHECK2-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2986 // CHECK2-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
2987 // CHECK2-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
2988 // CHECK2-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2989 // CHECK2-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
2990 // CHECK2-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
2991 // CHECK2-NEXT:    store i8* null, i8** [[TMP39]], align 8
2992 // CHECK2-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2993 // CHECK2-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2994 // CHECK2-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2995 // CHECK2-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2996 // CHECK2-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
2997 // CHECK2-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2998 // CHECK2:       omp_offload.failed:
2999 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
3000 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3001 // CHECK2:       omp_offload.cont:
3002 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3003 // CHECK2:       omp_if.else:
3004 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
3005 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3006 // CHECK2:       omp_if.end:
3007 // CHECK2-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
3008 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
3009 // CHECK2-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
3010 // CHECK2-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
3011 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
3012 // CHECK2-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
3013 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
3014 // CHECK2-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
3015 // CHECK2-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
3016 // CHECK2-NEXT:    ret i32 [[ADD4]]
3017 //
3018 //
3019 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
3020 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
3021 // CHECK2-NEXT:  entry:
3022 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3023 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
3024 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
3025 // CHECK2-NEXT:    [[AAA:%.*]] = alloca i8, align 1
3026 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3027 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3028 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3029 // CHECK2-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
3030 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
3031 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
3032 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
3033 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3034 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
3035 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
3036 // CHECK2-NEXT:    store i8 0, i8* [[AAA]], align 1
3037 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3038 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3039 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
3040 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
3041 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3042 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3043 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
3044 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3045 // CHECK2-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
3046 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
3047 // CHECK2-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
3048 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
3049 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3050 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
3051 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3052 // CHECK2:       omp_if.then:
3053 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3054 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
3055 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
3056 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3057 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
3058 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
3059 // CHECK2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3060 // CHECK2-NEXT:    store i8* null, i8** [[TMP11]], align 8
3061 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3062 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
3063 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
3064 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3065 // CHECK2-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
3066 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
3067 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3068 // CHECK2-NEXT:    store i8* null, i8** [[TMP16]], align 8
3069 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3070 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
3071 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
3072 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3073 // CHECK2-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
3074 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
3075 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3076 // CHECK2-NEXT:    store i8* null, i8** [[TMP21]], align 8
3077 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3078 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
3079 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
3080 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3081 // CHECK2-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
3082 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
3083 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
3084 // CHECK2-NEXT:    store i8* null, i8** [[TMP26]], align 8
3085 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3086 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3087 // CHECK2-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3088 // CHECK2-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
3089 // CHECK2-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3090 // CHECK2:       omp_offload.failed:
3091 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
3092 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3093 // CHECK2:       omp_offload.cont:
3094 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3095 // CHECK2:       omp_if.else:
3096 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
3097 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3098 // CHECK2:       omp_if.end:
3099 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
3100 // CHECK2-NEXT:    ret i32 [[TMP31]]
3101 //
3102 //
3103 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3104 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
3105 // CHECK2-NEXT:  entry:
3106 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3107 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
3108 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
3109 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3110 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3111 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3112 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
3113 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
3114 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
3115 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3116 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
3117 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
3118 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3119 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3120 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
3121 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
3122 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3123 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3124 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
3125 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3126 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3127 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3128 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3129 // CHECK2:       omp_if.then:
3130 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3131 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
3132 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
3133 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3134 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
3135 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
3136 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3137 // CHECK2-NEXT:    store i8* null, i8** [[TMP9]], align 8
3138 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3139 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
3140 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
3141 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3142 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
3143 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
3144 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3145 // CHECK2-NEXT:    store i8* null, i8** [[TMP14]], align 8
3146 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3147 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
3148 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
3149 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3150 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
3151 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
3152 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3153 // CHECK2-NEXT:    store i8* null, i8** [[TMP19]], align 8
3154 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3155 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3156 // CHECK2-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3157 // CHECK2-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
3158 // CHECK2-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3159 // CHECK2:       omp_offload.failed:
3160 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
3161 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3162 // CHECK2:       omp_offload.cont:
3163 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3164 // CHECK2:       omp_if.else:
3165 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
3166 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3167 // CHECK2:       omp_if.end:
3168 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
3169 // CHECK2-NEXT:    ret i32 [[TMP24]]
3170 //
3171 //
3172 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
3173 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3174 // CHECK2-NEXT:  entry:
3175 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3176 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3177 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3178 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3179 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
3180 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
3181 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3182 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3183 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
3184 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
3185 // CHECK2-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
3186 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3187 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
3188 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
3189 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
3190 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
3191 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
3192 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
3193 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
3194 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
3195 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
3196 // CHECK2-NEXT:    ret void
3197 //
3198 //
3199 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
3200 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
3201 // CHECK2-NEXT:  entry:
3202 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3203 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3204 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3205 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3206 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3207 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3208 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
3209 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3210 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i64, align 8
3211 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3212 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3213 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3214 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3215 // CHECK2-NEXT:    [[IT:%.*]] = alloca i64, align 8
3216 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3217 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3218 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3219 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3220 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
3221 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
3222 // CHECK2-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
3223 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3224 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
3225 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
3226 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
3227 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
3228 // CHECK2-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
3229 // CHECK2-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
3230 // CHECK2-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
3231 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3232 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3233 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3234 // CHECK2-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
3235 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3236 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
3237 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3238 // CHECK2:       cond.true:
3239 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3240 // CHECK2:       cond.false:
3241 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3242 // CHECK2-NEXT:    br label [[COND_END]]
3243 // CHECK2:       cond.end:
3244 // CHECK2-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3245 // CHECK2-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
3246 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
3247 // CHECK2-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
3248 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3249 // CHECK2:       omp.inner.for.cond:
3250 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
3251 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
3252 // CHECK2-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
3253 // CHECK2-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3254 // CHECK2:       omp.inner.for.body:
3255 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
3256 // CHECK2-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
3257 // CHECK2-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
3258 // CHECK2-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
3259 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
3260 // CHECK2-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
3261 // CHECK2-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
3262 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3263 // CHECK2-NEXT:    store double [[ADD]], double* [[A]], align 8, !llvm.access.group !38
3264 // CHECK2-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
3265 // CHECK2-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !38
3266 // CHECK2-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
3267 // CHECK2-NEXT:    store double [[INC]], double* [[A5]], align 8, !llvm.access.group !38
3268 // CHECK2-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
3269 // CHECK2-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
3270 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
3271 // CHECK2-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
3272 // CHECK2-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !38
3273 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3274 // CHECK2:       omp.body.continue:
3275 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3276 // CHECK2:       omp.inner.for.inc:
3277 // CHECK2-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
3278 // CHECK2-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
3279 // CHECK2-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
3280 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
3281 // CHECK2:       omp.inner.for.end:
3282 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3283 // CHECK2:       omp.loop.exit:
3284 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3285 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3286 // CHECK2-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
3287 // CHECK2-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3288 // CHECK2:       .omp.final.then:
3289 // CHECK2-NEXT:    store i64 400, i64* [[IT]], align 8
3290 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3291 // CHECK2:       .omp.final.done:
3292 // CHECK2-NEXT:    ret void
3293 //
3294 //
3295 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
3296 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3297 // CHECK2-NEXT:  entry:
3298 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3299 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3300 // CHECK2-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
3301 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3302 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3303 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3304 // CHECK2-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
3305 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3306 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3307 // CHECK2-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
3308 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3309 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3310 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3311 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
3312 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3313 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3314 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3315 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
3316 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
3317 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
3318 // CHECK2-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3319 // CHECK2-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
3320 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3321 // CHECK2-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
3322 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
3323 // CHECK2-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
3324 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
3325 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
3326 // CHECK2-NEXT:    ret void
3327 //
3328 //
3329 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
3330 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
3331 // CHECK2-NEXT:  entry:
3332 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3333 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3334 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3335 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3336 // CHECK2-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
3337 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3338 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3339 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3340 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3341 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3342 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3343 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3344 // CHECK2-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
3345 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3346 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3347 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3348 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
3349 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3350 // CHECK2-NEXT:    ret void
3351 //
3352 //
3353 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
3354 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3355 // CHECK2-NEXT:  entry:
3356 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3357 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3358 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3359 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3360 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3361 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3362 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3363 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3364 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3365 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3366 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3367 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3368 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3369 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
3370 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
3371 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
3372 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3373 // CHECK2-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
3374 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3375 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
3376 // CHECK2-NEXT:    ret void
3377 //
3378 //
3379 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14
3380 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
3381 // CHECK2-NEXT:  entry:
3382 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3383 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3384 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3385 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3386 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3387 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3388 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i64, align 8
3389 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3390 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3391 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3392 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3393 // CHECK2-NEXT:    [[I:%.*]] = alloca i64, align 8
3394 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3395 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3396 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3397 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3398 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3399 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3400 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3401 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3402 // CHECK2-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
3403 // CHECK2-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
3404 // CHECK2-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
3405 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3406 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3407 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
3408 // CHECK2-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
3409 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3410 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
3411 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3412 // CHECK2:       cond.true:
3413 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3414 // CHECK2:       cond.false:
3415 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
3416 // CHECK2-NEXT:    br label [[COND_END]]
3417 // CHECK2:       cond.end:
3418 // CHECK2-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3419 // CHECK2-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
3420 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
3421 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
3422 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3423 // CHECK2:       omp.inner.for.cond:
3424 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
3425 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !41
3426 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
3427 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3428 // CHECK2:       omp.inner.for.body:
3429 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
3430 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
3431 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
3432 // CHECK2-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41
3433 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !41
3434 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
3435 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !41
3436 // CHECK2-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !41
3437 // CHECK2-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
3438 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
3439 // CHECK2-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
3440 // CHECK2-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !41
3441 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
3442 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
3443 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
3444 // CHECK2-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
3445 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3446 // CHECK2:       omp.body.continue:
3447 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3448 // CHECK2:       omp.inner.for.inc:
3449 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
3450 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
3451 // CHECK2-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41
3452 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
3453 // CHECK2:       omp.inner.for.end:
3454 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3455 // CHECK2:       omp.loop.exit:
3456 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
3457 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3458 // CHECK2-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
3459 // CHECK2-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3460 // CHECK2:       .omp.final.then:
3461 // CHECK2-NEXT:    store i64 11, i64* [[I]], align 8
3462 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3463 // CHECK2:       .omp.final.done:
3464 // CHECK2-NEXT:    ret void
3465 //
3466 //
3467 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3468 // CHECK2-SAME: () #[[ATTR7:[0-9]+]] {
3469 // CHECK2-NEXT:  entry:
3470 // CHECK2-NEXT:    call void @__tgt_register_requires(i64 1)
3471 // CHECK2-NEXT:    ret void
3472 //
3473 //
3474 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv
3475 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
3476 // CHECK3-NEXT:  entry:
3477 // CHECK3-NEXT:    ret i64 0
3478 //
3479 //
3480 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
3481 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
3482 // CHECK3-NEXT:  entry:
3483 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3484 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3485 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3486 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
3487 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
3488 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3489 // CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
3490 // CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
3491 // CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
3492 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
3493 // CHECK3-NEXT:    [[K:%.*]] = alloca i64, align 8
3494 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3495 // CHECK3-NEXT:    [[LIN:%.*]] = alloca i32, align 4
3496 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3497 // CHECK3-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
3498 // CHECK3-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
3499 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
3500 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
3501 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
3502 // CHECK3-NEXT:    [[A_CASTED3:%.*]] = alloca i32, align 4
3503 // CHECK3-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
3504 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
3505 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
3506 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
3507 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3508 // CHECK3-NEXT:    [[A_CASTED11:%.*]] = alloca i32, align 4
3509 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
3510 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
3511 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
3512 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
3513 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
3514 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
3515 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3516 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
3517 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
3518 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3519 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
3520 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3521 // CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
3522 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
3523 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3524 // CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
3525 // CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
3526 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
3527 // CHECK3-NEXT:    [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
3528 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
3529 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
3530 // CHECK3-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]])
3531 // CHECK3-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
3532 // CHECK3-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
3533 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
3534 // CHECK3-NEXT:    store i32 [[TMP9]], i32* [[A_CASTED]], align 4
3535 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
3536 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]]
3537 // CHECK3-NEXT:    store i32 12, i32* [[LIN]], align 4
3538 // CHECK3-NEXT:    [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
3539 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3540 // CHECK3-NEXT:    store i16 [[TMP11]], i16* [[CONV]], align 2
3541 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3542 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4
3543 // CHECK3-NEXT:    store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4
3544 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
3545 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
3546 // CHECK3-NEXT:    store i32 [[TMP15]], i32* [[A_CASTED2]], align 4
3547 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4
3548 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3549 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
3550 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP18]], align 4
3551 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3552 // CHECK3-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
3553 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP20]], align 4
3554 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3555 // CHECK3-NEXT:    store i8* null, i8** [[TMP21]], align 4
3556 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3557 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
3558 // CHECK3-NEXT:    store i32 [[TMP14]], i32* [[TMP23]], align 4
3559 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3560 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
3561 // CHECK3-NEXT:    store i32 [[TMP14]], i32* [[TMP25]], align 4
3562 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3563 // CHECK3-NEXT:    store i8* null, i8** [[TMP26]], align 4
3564 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3565 // CHECK3-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
3566 // CHECK3-NEXT:    store i32 [[TMP16]], i32* [[TMP28]], align 4
3567 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3568 // CHECK3-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
3569 // CHECK3-NEXT:    store i32 [[TMP16]], i32* [[TMP30]], align 4
3570 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3571 // CHECK3-NEXT:    store i8* null, i8** [[TMP31]], align 4
3572 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3573 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3574 // CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3575 // CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
3576 // CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3577 // CHECK3:       omp_offload.failed:
3578 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]]
3579 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3580 // CHECK3:       omp_offload.cont:
3581 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
3582 // CHECK3-NEXT:    store i32 [[TMP36]], i32* [[A_CASTED3]], align 4
3583 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A_CASTED3]], align 4
3584 // CHECK3-NEXT:    [[TMP38:%.*]] = load i16, i16* [[AA]], align 2
3585 // CHECK3-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
3586 // CHECK3-NEXT:    store i16 [[TMP38]], i16* [[CONV5]], align 2
3587 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
3588 // CHECK3-NEXT:    [[TMP40:%.*]] = load i32, i32* [[N_ADDR]], align 4
3589 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP40]], 10
3590 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3591 // CHECK3:       omp_if.then:
3592 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
3593 // CHECK3-NEXT:    [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
3594 // CHECK3-NEXT:    store i32 [[TMP37]], i32* [[TMP42]], align 4
3595 // CHECK3-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
3596 // CHECK3-NEXT:    [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
3597 // CHECK3-NEXT:    store i32 [[TMP37]], i32* [[TMP44]], align 4
3598 // CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
3599 // CHECK3-NEXT:    store i8* null, i8** [[TMP45]], align 4
3600 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
3601 // CHECK3-NEXT:    [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
3602 // CHECK3-NEXT:    store i32 [[TMP39]], i32* [[TMP47]], align 4
3603 // CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
3604 // CHECK3-NEXT:    [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32*
3605 // CHECK3-NEXT:    store i32 [[TMP39]], i32* [[TMP49]], align 4
3606 // CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
3607 // CHECK3-NEXT:    store i8* null, i8** [[TMP50]], align 4
3608 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
3609 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
3610 // CHECK3-NEXT:    [[TMP53:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP51]], i8** [[TMP52]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3611 // CHECK3-NEXT:    [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
3612 // CHECK3-NEXT:    br i1 [[TMP54]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
3613 // CHECK3:       omp_offload.failed9:
3614 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
3615 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
3616 // CHECK3:       omp_offload.cont10:
3617 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3618 // CHECK3:       omp_if.else:
3619 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
3620 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3621 // CHECK3:       omp_if.end:
3622 // CHECK3-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
3623 // CHECK3-NEXT:    store i32 [[TMP55]], i32* [[DOTCAPTURE_EXPR_]], align 4
3624 // CHECK3-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A]], align 4
3625 // CHECK3-NEXT:    store i32 [[TMP56]], i32* [[A_CASTED11]], align 4
3626 // CHECK3-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A_CASTED11]], align 4
3627 // CHECK3-NEXT:    [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3628 // CHECK3-NEXT:    store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3629 // CHECK3-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3630 // CHECK3-NEXT:    [[TMP60:%.*]] = load i32, i32* [[N_ADDR]], align 4
3631 // CHECK3-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP60]], 20
3632 // CHECK3-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
3633 // CHECK3:       omp_if.then13:
3634 // CHECK3-NEXT:    [[TMP61:%.*]] = mul nuw i32 [[TMP1]], 4
3635 // CHECK3-NEXT:    [[TMP62:%.*]] = sext i32 [[TMP61]] to i64
3636 // CHECK3-NEXT:    [[TMP63:%.*]] = mul nuw i32 5, [[TMP3]]
3637 // CHECK3-NEXT:    [[TMP64:%.*]] = mul nuw i32 [[TMP63]], 8
3638 // CHECK3-NEXT:    [[TMP65:%.*]] = sext i32 [[TMP64]] to i64
3639 // CHECK3-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
3640 // CHECK3-NEXT:    [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32*
3641 // CHECK3-NEXT:    store i32 [[TMP57]], i32* [[TMP67]], align 4
3642 // CHECK3-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
3643 // CHECK3-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
3644 // CHECK3-NEXT:    store i32 [[TMP57]], i32* [[TMP69]], align 4
3645 // CHECK3-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3646 // CHECK3-NEXT:    store i64 4, i64* [[TMP70]], align 4
3647 // CHECK3-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
3648 // CHECK3-NEXT:    store i8* null, i8** [[TMP71]], align 4
3649 // CHECK3-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
3650 // CHECK3-NEXT:    [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [10 x float]**
3651 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP73]], align 4
3652 // CHECK3-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
3653 // CHECK3-NEXT:    [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
3654 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 4
3655 // CHECK3-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
3656 // CHECK3-NEXT:    store i64 40, i64* [[TMP76]], align 4
3657 // CHECK3-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
3658 // CHECK3-NEXT:    store i8* null, i8** [[TMP77]], align 4
3659 // CHECK3-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
3660 // CHECK3-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
3661 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP79]], align 4
3662 // CHECK3-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
3663 // CHECK3-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
3664 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP81]], align 4
3665 // CHECK3-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
3666 // CHECK3-NEXT:    store i64 4, i64* [[TMP82]], align 4
3667 // CHECK3-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
3668 // CHECK3-NEXT:    store i8* null, i8** [[TMP83]], align 4
3669 // CHECK3-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
3670 // CHECK3-NEXT:    [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float**
3671 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP85]], align 4
3672 // CHECK3-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
3673 // CHECK3-NEXT:    [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
3674 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP87]], align 4
3675 // CHECK3-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
3676 // CHECK3-NEXT:    store i64 [[TMP62]], i64* [[TMP88]], align 4
3677 // CHECK3-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
3678 // CHECK3-NEXT:    store i8* null, i8** [[TMP89]], align 4
3679 // CHECK3-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
3680 // CHECK3-NEXT:    [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]**
3681 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 4
3682 // CHECK3-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
3683 // CHECK3-NEXT:    [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
3684 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 4
3685 // CHECK3-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3686 // CHECK3-NEXT:    store i64 400, i64* [[TMP94]], align 4
3687 // CHECK3-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
3688 // CHECK3-NEXT:    store i8* null, i8** [[TMP95]], align 4
3689 // CHECK3-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
3690 // CHECK3-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
3691 // CHECK3-NEXT:    store i32 5, i32* [[TMP97]], align 4
3692 // CHECK3-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
3693 // CHECK3-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
3694 // CHECK3-NEXT:    store i32 5, i32* [[TMP99]], align 4
3695 // CHECK3-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
3696 // CHECK3-NEXT:    store i64 4, i64* [[TMP100]], align 4
3697 // CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
3698 // CHECK3-NEXT:    store i8* null, i8** [[TMP101]], align 4
3699 // CHECK3-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
3700 // CHECK3-NEXT:    [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i32*
3701 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP103]], align 4
3702 // CHECK3-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
3703 // CHECK3-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i32*
3704 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP105]], align 4
3705 // CHECK3-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
3706 // CHECK3-NEXT:    store i64 4, i64* [[TMP106]], align 4
3707 // CHECK3-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
3708 // CHECK3-NEXT:    store i8* null, i8** [[TMP107]], align 4
3709 // CHECK3-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
3710 // CHECK3-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to double**
3711 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP109]], align 4
3712 // CHECK3-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
3713 // CHECK3-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
3714 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP111]], align 4
3715 // CHECK3-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
3716 // CHECK3-NEXT:    store i64 [[TMP65]], i64* [[TMP112]], align 4
3717 // CHECK3-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
3718 // CHECK3-NEXT:    store i8* null, i8** [[TMP113]], align 4
3719 // CHECK3-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
3720 // CHECK3-NEXT:    [[TMP115:%.*]] = bitcast i8** [[TMP114]] to %struct.TT**
3721 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP115]], align 4
3722 // CHECK3-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
3723 // CHECK3-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
3724 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 4
3725 // CHECK3-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
3726 // CHECK3-NEXT:    store i64 12, i64* [[TMP118]], align 4
3727 // CHECK3-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
3728 // CHECK3-NEXT:    store i8* null, i8** [[TMP119]], align 4
3729 // CHECK3-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
3730 // CHECK3-NEXT:    [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32*
3731 // CHECK3-NEXT:    store i32 [[TMP59]], i32* [[TMP121]], align 4
3732 // CHECK3-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
3733 // CHECK3-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
3734 // CHECK3-NEXT:    store i32 [[TMP59]], i32* [[TMP123]], align 4
3735 // CHECK3-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
3736 // CHECK3-NEXT:    store i64 4, i64* [[TMP124]], align 4
3737 // CHECK3-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
3738 // CHECK3-NEXT:    store i8* null, i8** [[TMP125]], align 4
3739 // CHECK3-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
3740 // CHECK3-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
3741 // CHECK3-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3742 // CHECK3-NEXT:    [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3743 // CHECK3-NEXT:    [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0
3744 // CHECK3-NEXT:    br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
3745 // CHECK3:       omp_offload.failed17:
3746 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
3747 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
3748 // CHECK3:       omp_offload.cont18:
3749 // CHECK3-NEXT:    br label [[OMP_IF_END20:%.*]]
3750 // CHECK3:       omp_if.else19:
3751 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
3752 // CHECK3-NEXT:    br label [[OMP_IF_END20]]
3753 // CHECK3:       omp_if.end20:
3754 // CHECK3-NEXT:    [[TMP131:%.*]] = load i32, i32* [[A]], align 4
3755 // CHECK3-NEXT:    [[TMP132:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
3756 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP132]])
3757 // CHECK3-NEXT:    ret i32 [[TMP131]]
3758 //
3759 //
3760 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
3761 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
3762 // CHECK3-NEXT:  entry:
3763 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3764 // CHECK3-NEXT:    ret void
3765 //
3766 //
3767 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
3768 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
3769 // CHECK3-NEXT:  entry:
3770 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3771 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3772 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3773 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3774 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3775 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3776 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3777 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3778 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3779 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3780 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3781 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3782 // CHECK3-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
3783 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3784 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3785 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3786 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3787 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3788 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3789 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
3790 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3791 // CHECK3:       cond.true:
3792 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3793 // CHECK3:       cond.false:
3794 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3795 // CHECK3-NEXT:    br label [[COND_END]]
3796 // CHECK3:       cond.end:
3797 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3798 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3799 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3800 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
3801 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3802 // CHECK3:       omp.inner.for.cond:
3803 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
3804 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
3805 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3806 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3807 // CHECK3:       omp.inner.for.body:
3808 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
3809 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
3810 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
3811 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
3812 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3813 // CHECK3:       omp.body.continue:
3814 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3815 // CHECK3:       omp.inner.for.inc:
3816 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
3817 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
3818 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
3819 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
3820 // CHECK3:       omp.inner.for.end:
3821 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3822 // CHECK3:       omp.loop.exit:
3823 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
3824 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3825 // CHECK3-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
3826 // CHECK3-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3827 // CHECK3:       .omp.final.then:
3828 // CHECK3-NEXT:    store i32 33, i32* [[I]], align 4
3829 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3830 // CHECK3:       .omp.final.done:
3831 // CHECK3-NEXT:    ret void
3832 //
3833 //
3834 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
3835 // CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
3836 // CHECK3-NEXT:  entry:
3837 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
3838 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
3839 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
3840 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
3841 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
3842 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
3843 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
3844 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
3845 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
3846 // CHECK3-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
3847 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
3848 // CHECK3-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
3849 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
3850 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
3851 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
3852 // CHECK3-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
3853 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
3854 // CHECK3-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
3855 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
3856 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
3857 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
3858 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
3859 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
3860 // CHECK3-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26
3861 // CHECK3-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26
3862 // CHECK3-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26
3863 // CHECK3-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26
3864 // CHECK3-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
3865 // CHECK3-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
3866 // CHECK3-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
3867 // CHECK3-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
3868 // CHECK3-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
3869 // CHECK3:       omp_offload.failed.i:
3870 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
3871 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
3872 // CHECK3:       .omp_outlined..1.exit:
3873 // CHECK3-NEXT:    ret i32 0
3874 //
3875 //
3876 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
3877 // CHECK3-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
3878 // CHECK3-NEXT:  entry:
3879 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3880 // CHECK3-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
3881 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3882 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3883 // CHECK3-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
3884 // CHECK3-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
3885 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3886 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
3887 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
3888 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
3889 // CHECK3-NEXT:    ret void
3890 //
3891 //
3892 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
3893 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
3894 // CHECK3-NEXT:  entry:
3895 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3896 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3897 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3898 // CHECK3-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
3899 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3900 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3901 // CHECK3-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
3902 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3903 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3904 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3905 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3906 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3907 // CHECK3-NEXT:    [[K1:%.*]] = alloca i64, align 8
3908 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3909 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3910 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3911 // CHECK3-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
3912 // CHECK3-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
3913 // CHECK3-NEXT:    [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
3914 // CHECK3-NEXT:    store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
3915 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3916 // CHECK3-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
3917 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3918 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3919 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3920 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
3921 // CHECK3-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
3922 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
3923 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
3924 // CHECK3:       omp.dispatch.cond:
3925 // CHECK3-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
3926 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
3927 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3928 // CHECK3:       omp.dispatch.body:
3929 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3930 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
3931 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3932 // CHECK3:       omp.inner.for.cond:
3933 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
3934 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
3935 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
3936 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3937 // CHECK3:       omp.inner.for.body:
3938 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
3939 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
3940 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
3941 // CHECK3-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !27
3942 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !27
3943 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
3944 // CHECK3-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
3945 // CHECK3-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
3946 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
3947 // CHECK3-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !27
3948 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !27
3949 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
3950 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !27
3951 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3952 // CHECK3:       omp.body.continue:
3953 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3954 // CHECK3:       omp.inner.for.inc:
3955 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
3956 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
3957 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
3958 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
3959 // CHECK3:       omp.inner.for.end:
3960 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
3961 // CHECK3:       omp.dispatch.inc:
3962 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
3963 // CHECK3:       omp.dispatch.end:
3964 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3965 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
3966 // CHECK3-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3967 // CHECK3:       .omp.final.then:
3968 // CHECK3-NEXT:    store i32 1, i32* [[I]], align 4
3969 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3970 // CHECK3:       .omp.final.done:
3971 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3972 // CHECK3-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
3973 // CHECK3-NEXT:    br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
3974 // CHECK3:       .omp.linear.pu:
3975 // CHECK3-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
3976 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP17]], 27
3977 // CHECK3-NEXT:    store i64 [[ADD5]], i64* [[TMP0]], align 8
3978 // CHECK3-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
3979 // CHECK3:       .omp.linear.pu.done:
3980 // CHECK3-NEXT:    ret void
3981 //
3982 //
3983 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
3984 // CHECK3-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
3985 // CHECK3-NEXT:  entry:
3986 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3987 // CHECK3-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
3988 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3989 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3990 // CHECK3-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
3991 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3992 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3993 // CHECK3-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
3994 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3995 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3996 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
3997 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3998 // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
3999 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4000 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
4001 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
4002 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
4003 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
4004 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
4005 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
4006 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
4007 // CHECK3-NEXT:    ret void
4008 //
4009 //
4010 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
4011 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {
4012 // CHECK3-NEXT:  entry:
4013 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4014 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4015 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4016 // CHECK3-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
4017 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4018 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4019 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 4
4020 // CHECK3-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
4021 // CHECK3-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
4022 // CHECK3-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
4023 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4024 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4025 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4026 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4027 // CHECK3-NEXT:    [[IT:%.*]] = alloca i64, align 8
4028 // CHECK3-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
4029 // CHECK3-NEXT:    [[A3:%.*]] = alloca i32, align 4
4030 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4031 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4032 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4033 // CHECK3-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
4034 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4035 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4036 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
4037 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
4038 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4039 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
4040 // CHECK3-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
4041 // CHECK3-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
4042 // CHECK3-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
4043 // CHECK3-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
4044 // CHECK3-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
4045 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4046 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4047 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
4048 // CHECK3-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
4049 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
4050 // CHECK3-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4051 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
4052 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4053 // CHECK3:       cond.true:
4054 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4055 // CHECK3:       cond.false:
4056 // CHECK3-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4057 // CHECK3-NEXT:    br label [[COND_END]]
4058 // CHECK3:       cond.end:
4059 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
4060 // CHECK3-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
4061 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4062 // CHECK3-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
4063 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4064 // CHECK3:       omp.inner.for.cond:
4065 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
4066 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
4067 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
4068 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4069 // CHECK3:       omp.inner.for.body:
4070 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
4071 // CHECK3-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
4072 // CHECK3-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
4073 // CHECK3-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !30
4074 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !30
4075 // CHECK3-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
4076 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
4077 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
4078 // CHECK3-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
4079 // CHECK3-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
4080 // CHECK3-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
4081 // CHECK3-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !30
4082 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
4083 // CHECK3-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
4084 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
4085 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
4086 // CHECK3-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
4087 // CHECK3-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
4088 // CHECK3-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
4089 // CHECK3-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
4090 // CHECK3-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
4091 // CHECK3-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
4092 // CHECK3-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
4093 // CHECK3-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
4094 // CHECK3-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
4095 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4096 // CHECK3:       omp.body.continue:
4097 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4098 // CHECK3:       omp.inner.for.inc:
4099 // CHECK3-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
4100 // CHECK3-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
4101 // CHECK3-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
4102 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
4103 // CHECK3:       omp.inner.for.end:
4104 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4105 // CHECK3:       omp.loop.exit:
4106 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
4107 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4108 // CHECK3-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
4109 // CHECK3-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4110 // CHECK3:       .omp.final.then:
4111 // CHECK3-NEXT:    store i64 400, i64* [[IT]], align 8
4112 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4113 // CHECK3:       .omp.final.done:
4114 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4115 // CHECK3-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
4116 // CHECK3-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
4117 // CHECK3:       .omp.linear.pu:
4118 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
4119 // CHECK3-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
4120 // CHECK3-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
4121 // CHECK3-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP23]]
4122 // CHECK3-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
4123 // CHECK3-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
4124 // CHECK3-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
4125 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
4126 // CHECK3-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
4127 // CHECK3-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
4128 // CHECK3-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP25]]
4129 // CHECK3-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
4130 // CHECK3-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
4131 // CHECK3-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
4132 // CHECK3-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
4133 // CHECK3:       .omp.linear.pu.done:
4134 // CHECK3-NEXT:    ret void
4135 //
4136 //
4137 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
4138 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4139 // CHECK3-NEXT:  entry:
4140 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4141 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4142 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4143 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4144 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4145 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4146 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4147 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4148 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4149 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4150 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
4151 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4152 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
4153 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4154 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
4155 // CHECK3-NEXT:    ret void
4156 //
4157 //
4158 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
4159 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
4160 // CHECK3-NEXT:  entry:
4161 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4162 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4163 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4164 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4165 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4166 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i16, align 2
4167 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4168 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4169 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4170 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4171 // CHECK3-NEXT:    [[IT:%.*]] = alloca i16, align 2
4172 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4173 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4174 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4175 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4176 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4177 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4178 // CHECK3-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
4179 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4180 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4181 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4182 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4183 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4184 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4185 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
4186 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4187 // CHECK3:       cond.true:
4188 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4189 // CHECK3:       cond.false:
4190 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4191 // CHECK3-NEXT:    br label [[COND_END]]
4192 // CHECK3:       cond.end:
4193 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4194 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4195 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4196 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4197 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4198 // CHECK3:       omp.inner.for.cond:
4199 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4200 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
4201 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4202 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4203 // CHECK3:       omp.inner.for.body:
4204 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4205 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
4206 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
4207 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
4208 // CHECK3-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
4209 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
4210 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
4211 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
4212 // CHECK3-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
4213 // CHECK3-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
4214 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
4215 // CHECK3-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
4216 // CHECK3-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
4217 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4218 // CHECK3:       omp.body.continue:
4219 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4220 // CHECK3:       omp.inner.for.inc:
4221 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4222 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
4223 // CHECK3-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4224 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
4225 // CHECK3:       omp.inner.for.end:
4226 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4227 // CHECK3:       omp.loop.exit:
4228 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4229 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4230 // CHECK3-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
4231 // CHECK3-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4232 // CHECK3:       .omp.final.then:
4233 // CHECK3-NEXT:    store i16 22, i16* [[IT]], align 2
4234 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4235 // CHECK3:       .omp.final.done:
4236 // CHECK3-NEXT:    ret void
4237 //
4238 //
4239 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
4240 // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
4241 // CHECK3-NEXT:  entry:
4242 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4243 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
4244 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4245 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
4246 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
4247 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4248 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4249 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
4250 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
4251 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4252 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4253 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
4254 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4255 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
4256 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4257 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
4258 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
4259 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4260 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
4261 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
4262 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
4263 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4264 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
4265 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4266 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
4267 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
4268 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4269 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
4270 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
4271 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
4272 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
4273 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
4274 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
4275 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4276 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
4277 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
4278 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
4279 // CHECK3-NEXT:    ret void
4280 //
4281 //
4282 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
4283 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
4284 // CHECK3-NEXT:  entry:
4285 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4286 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4287 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4288 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
4289 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4290 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
4291 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
4292 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4293 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4294 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
4295 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
4296 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4297 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4298 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 1
4299 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4300 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4301 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4302 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4303 // CHECK3-NEXT:    [[IT:%.*]] = alloca i8, align 1
4304 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4305 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4306 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4307 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
4308 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4309 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
4310 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
4311 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4312 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
4313 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
4314 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
4315 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4316 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
4317 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4318 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
4319 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
4320 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4321 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
4322 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
4323 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
4324 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4325 // CHECK3-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
4326 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4327 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4328 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4329 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4330 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
4331 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
4332 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4333 // CHECK3:       omp.dispatch.cond:
4334 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4335 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
4336 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4337 // CHECK3:       cond.true:
4338 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4339 // CHECK3:       cond.false:
4340 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4341 // CHECK3-NEXT:    br label [[COND_END]]
4342 // CHECK3:       cond.end:
4343 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
4344 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4345 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4346 // CHECK3-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
4347 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4348 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4349 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
4350 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4351 // CHECK3:       omp.dispatch.body:
4352 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4353 // CHECK3:       omp.inner.for.cond:
4354 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4355 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
4356 // CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
4357 // CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4358 // CHECK3:       omp.inner.for.body:
4359 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4360 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
4361 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
4362 // CHECK3-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
4363 // CHECK3-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !36
4364 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
4365 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
4366 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
4367 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
4368 // CHECK3-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
4369 // CHECK3-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
4370 // CHECK3-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
4371 // CHECK3-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
4372 // CHECK3-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
4373 // CHECK3-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
4374 // CHECK3-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
4375 // CHECK3-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
4376 // CHECK3-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
4377 // CHECK3-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
4378 // CHECK3-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
4379 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
4380 // CHECK3-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
4381 // CHECK3-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
4382 // CHECK3-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
4383 // CHECK3-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
4384 // CHECK3-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
4385 // CHECK3-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
4386 // CHECK3-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
4387 // CHECK3-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
4388 // CHECK3-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
4389 // CHECK3-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
4390 // CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
4391 // CHECK3-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
4392 // CHECK3-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
4393 // CHECK3-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !36
4394 // CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
4395 // CHECK3-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
4396 // CHECK3-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
4397 // CHECK3-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
4398 // CHECK3-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
4399 // CHECK3-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !36
4400 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4401 // CHECK3:       omp.body.continue:
4402 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4403 // CHECK3:       omp.inner.for.inc:
4404 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4405 // CHECK3-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
4406 // CHECK3-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4407 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
4408 // CHECK3:       omp.inner.for.end:
4409 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4410 // CHECK3:       omp.dispatch.inc:
4411 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4412 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4413 // CHECK3-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
4414 // CHECK3-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
4415 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4416 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4417 // CHECK3-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
4418 // CHECK3-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
4419 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
4420 // CHECK3:       omp.dispatch.end:
4421 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
4422 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4423 // CHECK3-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
4424 // CHECK3-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4425 // CHECK3:       .omp.final.then:
4426 // CHECK3-NEXT:    store i8 96, i8* [[IT]], align 1
4427 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4428 // CHECK3:       .omp.final.done:
4429 // CHECK3-NEXT:    ret void
4430 //
4431 //
4432 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
4433 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4434 // CHECK3-NEXT:  entry:
4435 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4436 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4437 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
4438 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4439 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4440 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4441 // CHECK3-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
4442 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
4443 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
4444 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4445 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4446 // CHECK3-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
4447 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4448 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
4449 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
4450 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4451 // CHECK3-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
4452 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
4453 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
4454 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4455 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4456 // CHECK3-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
4457 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
4458 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
4459 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
4460 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4461 // CHECK3-NEXT:    ret i32 [[TMP8]]
4462 //
4463 //
4464 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
4465 // CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
4466 // CHECK3-NEXT:  entry:
4467 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4468 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4469 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
4470 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
4471 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
4472 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
4473 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
4474 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
4475 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
4476 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
4477 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4478 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4479 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4480 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4481 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4482 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
4483 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
4484 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
4485 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
4486 // CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
4487 // CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
4488 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
4489 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
4490 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
4491 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
4492 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4493 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
4494 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4495 // CHECK3:       omp_if.then:
4496 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
4497 // CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
4498 // CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
4499 // CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
4500 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4501 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
4502 // CHECK3-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
4503 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4504 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
4505 // CHECK3-NEXT:    store double* [[A]], double** [[TMP13]], align 4
4506 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4507 // CHECK3-NEXT:    store i64 8, i64* [[TMP14]], align 4
4508 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4509 // CHECK3-NEXT:    store i8* null, i8** [[TMP15]], align 4
4510 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4511 // CHECK3-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
4512 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
4513 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4514 // CHECK3-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
4515 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
4516 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
4517 // CHECK3-NEXT:    store i64 4, i64* [[TMP20]], align 4
4518 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4519 // CHECK3-NEXT:    store i8* null, i8** [[TMP21]], align 4
4520 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4521 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
4522 // CHECK3-NEXT:    store i32 2, i32* [[TMP23]], align 4
4523 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4524 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
4525 // CHECK3-NEXT:    store i32 2, i32* [[TMP25]], align 4
4526 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
4527 // CHECK3-NEXT:    store i64 4, i64* [[TMP26]], align 4
4528 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4529 // CHECK3-NEXT:    store i8* null, i8** [[TMP27]], align 4
4530 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4531 // CHECK3-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
4532 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
4533 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4534 // CHECK3-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
4535 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
4536 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
4537 // CHECK3-NEXT:    store i64 4, i64* [[TMP32]], align 4
4538 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4539 // CHECK3-NEXT:    store i8* null, i8** [[TMP33]], align 4
4540 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
4541 // CHECK3-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
4542 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
4543 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
4544 // CHECK3-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
4545 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
4546 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
4547 // CHECK3-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
4548 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
4549 // CHECK3-NEXT:    store i8* null, i8** [[TMP39]], align 4
4550 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4551 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4552 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4553 // CHECK3-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
4554 // CHECK3-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
4555 // CHECK3-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4556 // CHECK3:       omp_offload.failed:
4557 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
4558 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4559 // CHECK3:       omp_offload.cont:
4560 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
4561 // CHECK3:       omp_if.else:
4562 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
4563 // CHECK3-NEXT:    br label [[OMP_IF_END]]
4564 // CHECK3:       omp_if.end:
4565 // CHECK3-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
4566 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
4567 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
4568 // CHECK3-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
4569 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
4570 // CHECK3-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
4571 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
4572 // CHECK3-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4573 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
4574 // CHECK3-NEXT:    ret i32 [[ADD3]]
4575 //
4576 //
4577 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
4578 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4579 // CHECK3-NEXT:  entry:
4580 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4581 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4582 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
4583 // CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 1
4584 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4585 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4586 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4587 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
4588 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
4589 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
4590 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
4591 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4592 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4593 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
4594 // CHECK3-NEXT:    store i8 0, i8* [[AAA]], align 1
4595 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4596 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4597 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4598 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
4599 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4600 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
4601 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4602 // CHECK3-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
4603 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
4604 // CHECK3-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
4605 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
4606 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4607 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
4608 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4609 // CHECK3:       omp_if.then:
4610 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4611 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
4612 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
4613 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4614 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
4615 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
4616 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4617 // CHECK3-NEXT:    store i8* null, i8** [[TMP11]], align 4
4618 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4619 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4620 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
4621 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4622 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
4623 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
4624 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4625 // CHECK3-NEXT:    store i8* null, i8** [[TMP16]], align 4
4626 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4627 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
4628 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
4629 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4630 // CHECK3-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
4631 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
4632 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4633 // CHECK3-NEXT:    store i8* null, i8** [[TMP21]], align 4
4634 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4635 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
4636 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
4637 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4638 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
4639 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
4640 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4641 // CHECK3-NEXT:    store i8* null, i8** [[TMP26]], align 4
4642 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4643 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4644 // CHECK3-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
4645 // CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
4646 // CHECK3-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4647 // CHECK3:       omp_offload.failed:
4648 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
4649 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4650 // CHECK3:       omp_offload.cont:
4651 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
4652 // CHECK3:       omp_if.else:
4653 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
4654 // CHECK3-NEXT:    br label [[OMP_IF_END]]
4655 // CHECK3:       omp_if.end:
4656 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
4657 // CHECK3-NEXT:    ret i32 [[TMP31]]
4658 //
4659 //
4660 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4661 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
4662 // CHECK3-NEXT:  entry:
4663 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4664 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4665 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
4666 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4667 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4668 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4669 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
4670 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
4671 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
4672 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4673 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4674 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
4675 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4676 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4677 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4678 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
4679 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4680 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
4681 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4682 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4683 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
4684 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4685 // CHECK3:       omp_if.then:
4686 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4687 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
4688 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
4689 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4690 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
4691 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
4692 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4693 // CHECK3-NEXT:    store i8* null, i8** [[TMP9]], align 4
4694 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4695 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
4696 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
4697 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4698 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4699 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
4700 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4701 // CHECK3-NEXT:    store i8* null, i8** [[TMP14]], align 4
4702 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4703 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
4704 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
4705 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4706 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
4707 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
4708 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4709 // CHECK3-NEXT:    store i8* null, i8** [[TMP19]], align 4
4710 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4711 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4712 // CHECK3-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
4713 // CHECK3-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
4714 // CHECK3-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4715 // CHECK3:       omp_offload.failed:
4716 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
4717 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4718 // CHECK3:       omp_offload.cont:
4719 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
4720 // CHECK3:       omp_if.else:
4721 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
4722 // CHECK3-NEXT:    br label [[OMP_IF_END]]
4723 // CHECK3:       omp_if.end:
4724 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
4725 // CHECK3-NEXT:    ret i32 [[TMP24]]
4726 //
4727 //
4728 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
4729 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
4730 // CHECK3-NEXT:  entry:
4731 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4732 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
4733 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4734 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4735 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
4736 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
4737 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4738 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
4739 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4740 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4741 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
4742 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4743 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4744 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4745 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
4746 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
4747 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
4748 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
4749 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
4750 // CHECK3-NEXT:    ret void
4751 //
4752 //
4753 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9
4754 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
4755 // CHECK3-NEXT:  entry:
4756 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4757 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4758 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4759 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
4760 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4761 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4762 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
4763 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4764 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 4
4765 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4766 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4767 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4768 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4769 // CHECK3-NEXT:    [[IT:%.*]] = alloca i64, align 8
4770 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4771 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4772 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4773 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
4774 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4775 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4776 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
4777 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4778 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4779 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4780 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
4781 // CHECK3-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
4782 // CHECK3-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
4783 // CHECK3-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
4784 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4785 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4786 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
4787 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
4788 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4789 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
4790 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4791 // CHECK3:       cond.true:
4792 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4793 // CHECK3:       cond.false:
4794 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4795 // CHECK3-NEXT:    br label [[COND_END]]
4796 // CHECK3:       cond.end:
4797 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
4798 // CHECK3-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
4799 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4800 // CHECK3-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
4801 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4802 // CHECK3:       omp.inner.for.cond:
4803 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
4804 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !39
4805 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
4806 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4807 // CHECK3:       omp.inner.for.body:
4808 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
4809 // CHECK3-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
4810 // CHECK3-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
4811 // CHECK3-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !39
4812 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
4813 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
4814 // CHECK3-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
4815 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
4816 // CHECK3-NEXT:    store double [[ADD]], double* [[A]], align 4, !llvm.access.group !39
4817 // CHECK3-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
4818 // CHECK3-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !39
4819 // CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
4820 // CHECK3-NEXT:    store double [[INC]], double* [[A4]], align 4, !llvm.access.group !39
4821 // CHECK3-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
4822 // CHECK3-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
4823 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
4824 // CHECK3-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
4825 // CHECK3-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !39
4826 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4827 // CHECK3:       omp.body.continue:
4828 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4829 // CHECK3:       omp.inner.for.inc:
4830 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
4831 // CHECK3-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
4832 // CHECK3-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
4833 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
4834 // CHECK3:       omp.inner.for.end:
4835 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4836 // CHECK3:       omp.loop.exit:
4837 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
4838 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4839 // CHECK3-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
4840 // CHECK3-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4841 // CHECK3:       .omp.final.then:
4842 // CHECK3-NEXT:    store i64 400, i64* [[IT]], align 8
4843 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4844 // CHECK3:       .omp.final.done:
4845 // CHECK3-NEXT:    ret void
4846 //
4847 //
4848 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
4849 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4850 // CHECK3-NEXT:  entry:
4851 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4852 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4853 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
4854 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4855 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4856 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4857 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
4858 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4859 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4860 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
4861 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4862 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4863 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
4864 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4865 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4866 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
4867 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
4868 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
4869 // CHECK3-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4870 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
4871 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4872 // CHECK3-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
4873 // CHECK3-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
4874 // CHECK3-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
4875 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
4876 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
4877 // CHECK3-NEXT:    ret void
4878 //
4879 //
4880 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
4881 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
4882 // CHECK3-NEXT:  entry:
4883 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4884 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4885 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4886 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4887 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
4888 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4889 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4890 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4891 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4892 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4893 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4894 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4895 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
4896 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4897 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4898 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
4899 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4900 // CHECK3-NEXT:    ret void
4901 //
4902 //
4903 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
4904 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4905 // CHECK3-NEXT:  entry:
4906 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4907 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4908 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4909 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4910 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4911 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4912 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4913 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4914 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4915 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4916 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4917 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
4918 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
4919 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
4920 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4921 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
4922 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4923 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
4924 // CHECK3-NEXT:    ret void
4925 //
4926 //
4927 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14
4928 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
4929 // CHECK3-NEXT:  entry:
4930 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4931 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4932 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4933 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4934 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4935 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4936 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 4
4937 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4938 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4939 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4940 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4941 // CHECK3-NEXT:    [[I:%.*]] = alloca i64, align 8
4942 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4943 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4944 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4945 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4946 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4947 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4948 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4949 // CHECK3-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
4950 // CHECK3-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
4951 // CHECK3-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
4952 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4953 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4954 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
4955 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
4956 // CHECK3-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4957 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
4958 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4959 // CHECK3:       cond.true:
4960 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4961 // CHECK3:       cond.false:
4962 // CHECK3-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
4963 // CHECK3-NEXT:    br label [[COND_END]]
4964 // CHECK3:       cond.end:
4965 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
4966 // CHECK3-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
4967 // CHECK3-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
4968 // CHECK3-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
4969 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4970 // CHECK3:       omp.inner.for.cond:
4971 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
4972 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !42
4973 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
4974 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4975 // CHECK3:       omp.inner.for.body:
4976 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
4977 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
4978 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
4979 // CHECK3-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !42
4980 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
4981 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
4982 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
4983 // CHECK3-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42
4984 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
4985 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
4986 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
4987 // CHECK3-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !42
4988 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
4989 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
4990 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
4991 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
4992 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4993 // CHECK3:       omp.body.continue:
4994 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4995 // CHECK3:       omp.inner.for.inc:
4996 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
4997 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
4998 // CHECK3-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
4999 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
5000 // CHECK3:       omp.inner.for.end:
5001 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5002 // CHECK3:       omp.loop.exit:
5003 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
5004 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5005 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
5006 // CHECK3-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5007 // CHECK3:       .omp.final.then:
5008 // CHECK3-NEXT:    store i64 11, i64* [[I]], align 8
5009 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5010 // CHECK3:       .omp.final.done:
5011 // CHECK3-NEXT:    ret void
5012 //
5013 //
5014 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5015 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] {
5016 // CHECK3-NEXT:  entry:
5017 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
5018 // CHECK3-NEXT:    ret void
5019 //
5020 //
5021 // CHECK4-LABEL: define {{[^@]+}}@_Z7get_valv
5022 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
5023 // CHECK4-NEXT:  entry:
5024 // CHECK4-NEXT:    ret i64 0
5025 //
5026 //
5027 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi
5028 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
5029 // CHECK4-NEXT:  entry:
5030 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5031 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
5032 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
5033 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
5034 // CHECK4-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
5035 // CHECK4-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
5036 // CHECK4-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
5037 // CHECK4-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
5038 // CHECK4-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
5039 // CHECK4-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
5040 // CHECK4-NEXT:    [[K:%.*]] = alloca i64, align 8
5041 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5042 // CHECK4-NEXT:    [[LIN:%.*]] = alloca i32, align 4
5043 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5044 // CHECK4-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
5045 // CHECK4-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
5046 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
5047 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
5048 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
5049 // CHECK4-NEXT:    [[A_CASTED3:%.*]] = alloca i32, align 4
5050 // CHECK4-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
5051 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
5052 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
5053 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
5054 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5055 // CHECK4-NEXT:    [[A_CASTED11:%.*]] = alloca i32, align 4
5056 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5057 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
5058 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
5059 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
5060 // CHECK4-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
5061 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
5062 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5063 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
5064 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
5065 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
5066 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
5067 // CHECK4-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
5068 // CHECK4-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
5069 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
5070 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
5071 // CHECK4-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
5072 // CHECK4-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
5073 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
5074 // CHECK4-NEXT:    [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
5075 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
5076 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
5077 // CHECK4-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]])
5078 // CHECK4-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
5079 // CHECK4-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
5080 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
5081 // CHECK4-NEXT:    store i32 [[TMP9]], i32* [[A_CASTED]], align 4
5082 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
5083 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]]
5084 // CHECK4-NEXT:    store i32 12, i32* [[LIN]], align 4
5085 // CHECK4-NEXT:    [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
5086 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5087 // CHECK4-NEXT:    store i16 [[TMP11]], i16* [[CONV]], align 2
5088 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5089 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4
5090 // CHECK4-NEXT:    store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4
5091 // CHECK4-NEXT:    [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
5092 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
5093 // CHECK4-NEXT:    store i32 [[TMP15]], i32* [[A_CASTED2]], align 4
5094 // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4
5095 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5096 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
5097 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP18]], align 4
5098 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5099 // CHECK4-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
5100 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP20]], align 4
5101 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5102 // CHECK4-NEXT:    store i8* null, i8** [[TMP21]], align 4
5103 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5104 // CHECK4-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
5105 // CHECK4-NEXT:    store i32 [[TMP14]], i32* [[TMP23]], align 4
5106 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5107 // CHECK4-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
5108 // CHECK4-NEXT:    store i32 [[TMP14]], i32* [[TMP25]], align 4
5109 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5110 // CHECK4-NEXT:    store i8* null, i8** [[TMP26]], align 4
5111 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5112 // CHECK4-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
5113 // CHECK4-NEXT:    store i32 [[TMP16]], i32* [[TMP28]], align 4
5114 // CHECK4-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5115 // CHECK4-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
5116 // CHECK4-NEXT:    store i32 [[TMP16]], i32* [[TMP30]], align 4
5117 // CHECK4-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5118 // CHECK4-NEXT:    store i8* null, i8** [[TMP31]], align 4
5119 // CHECK4-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5120 // CHECK4-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5121 // CHECK4-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
5122 // CHECK4-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
5123 // CHECK4-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5124 // CHECK4:       omp_offload.failed:
5125 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]]
5126 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5127 // CHECK4:       omp_offload.cont:
5128 // CHECK4-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
5129 // CHECK4-NEXT:    store i32 [[TMP36]], i32* [[A_CASTED3]], align 4
5130 // CHECK4-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A_CASTED3]], align 4
5131 // CHECK4-NEXT:    [[TMP38:%.*]] = load i16, i16* [[AA]], align 2
5132 // CHECK4-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
5133 // CHECK4-NEXT:    store i16 [[TMP38]], i16* [[CONV5]], align 2
5134 // CHECK4-NEXT:    [[TMP39:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
5135 // CHECK4-NEXT:    [[TMP40:%.*]] = load i32, i32* [[N_ADDR]], align 4
5136 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP40]], 10
5137 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5138 // CHECK4:       omp_if.then:
5139 // CHECK4-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
5140 // CHECK4-NEXT:    [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
5141 // CHECK4-NEXT:    store i32 [[TMP37]], i32* [[TMP42]], align 4
5142 // CHECK4-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
5143 // CHECK4-NEXT:    [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
5144 // CHECK4-NEXT:    store i32 [[TMP37]], i32* [[TMP44]], align 4
5145 // CHECK4-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
5146 // CHECK4-NEXT:    store i8* null, i8** [[TMP45]], align 4
5147 // CHECK4-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
5148 // CHECK4-NEXT:    [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
5149 // CHECK4-NEXT:    store i32 [[TMP39]], i32* [[TMP47]], align 4
5150 // CHECK4-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
5151 // CHECK4-NEXT:    [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32*
5152 // CHECK4-NEXT:    store i32 [[TMP39]], i32* [[TMP49]], align 4
5153 // CHECK4-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
5154 // CHECK4-NEXT:    store i8* null, i8** [[TMP50]], align 4
5155 // CHECK4-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
5156 // CHECK4-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
5157 // CHECK4-NEXT:    [[TMP53:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP51]], i8** [[TMP52]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
5158 // CHECK4-NEXT:    [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
5159 // CHECK4-NEXT:    br i1 [[TMP54]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
5160 // CHECK4:       omp_offload.failed9:
5161 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
5162 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
5163 // CHECK4:       omp_offload.cont10:
5164 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
5165 // CHECK4:       omp_if.else:
5166 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
5167 // CHECK4-NEXT:    br label [[OMP_IF_END]]
5168 // CHECK4:       omp_if.end:
5169 // CHECK4-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
5170 // CHECK4-NEXT:    store i32 [[TMP55]], i32* [[DOTCAPTURE_EXPR_]], align 4
5171 // CHECK4-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A]], align 4
5172 // CHECK4-NEXT:    store i32 [[TMP56]], i32* [[A_CASTED11]], align 4
5173 // CHECK4-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A_CASTED11]], align 4
5174 // CHECK4-NEXT:    [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5175 // CHECK4-NEXT:    store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5176 // CHECK4-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5177 // CHECK4-NEXT:    [[TMP60:%.*]] = load i32, i32* [[N_ADDR]], align 4
5178 // CHECK4-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP60]], 20
5179 // CHECK4-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
5180 // CHECK4:       omp_if.then13:
5181 // CHECK4-NEXT:    [[TMP61:%.*]] = mul nuw i32 [[TMP1]], 4
5182 // CHECK4-NEXT:    [[TMP62:%.*]] = sext i32 [[TMP61]] to i64
5183 // CHECK4-NEXT:    [[TMP63:%.*]] = mul nuw i32 5, [[TMP3]]
5184 // CHECK4-NEXT:    [[TMP64:%.*]] = mul nuw i32 [[TMP63]], 8
5185 // CHECK4-NEXT:    [[TMP65:%.*]] = sext i32 [[TMP64]] to i64
5186 // CHECK4-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
5187 // CHECK4-NEXT:    [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32*
5188 // CHECK4-NEXT:    store i32 [[TMP57]], i32* [[TMP67]], align 4
5189 // CHECK4-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
5190 // CHECK4-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
5191 // CHECK4-NEXT:    store i32 [[TMP57]], i32* [[TMP69]], align 4
5192 // CHECK4-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5193 // CHECK4-NEXT:    store i64 4, i64* [[TMP70]], align 4
5194 // CHECK4-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
5195 // CHECK4-NEXT:    store i8* null, i8** [[TMP71]], align 4
5196 // CHECK4-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
5197 // CHECK4-NEXT:    [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [10 x float]**
5198 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP73]], align 4
5199 // CHECK4-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
5200 // CHECK4-NEXT:    [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
5201 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 4
5202 // CHECK4-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
5203 // CHECK4-NEXT:    store i64 40, i64* [[TMP76]], align 4
5204 // CHECK4-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
5205 // CHECK4-NEXT:    store i8* null, i8** [[TMP77]], align 4
5206 // CHECK4-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
5207 // CHECK4-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
5208 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP79]], align 4
5209 // CHECK4-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
5210 // CHECK4-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
5211 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP81]], align 4
5212 // CHECK4-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
5213 // CHECK4-NEXT:    store i64 4, i64* [[TMP82]], align 4
5214 // CHECK4-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
5215 // CHECK4-NEXT:    store i8* null, i8** [[TMP83]], align 4
5216 // CHECK4-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
5217 // CHECK4-NEXT:    [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float**
5218 // CHECK4-NEXT:    store float* [[VLA]], float** [[TMP85]], align 4
5219 // CHECK4-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
5220 // CHECK4-NEXT:    [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
5221 // CHECK4-NEXT:    store float* [[VLA]], float** [[TMP87]], align 4
5222 // CHECK4-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
5223 // CHECK4-NEXT:    store i64 [[TMP62]], i64* [[TMP88]], align 4
5224 // CHECK4-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
5225 // CHECK4-NEXT:    store i8* null, i8** [[TMP89]], align 4
5226 // CHECK4-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
5227 // CHECK4-NEXT:    [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]**
5228 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 4
5229 // CHECK4-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
5230 // CHECK4-NEXT:    [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
5231 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 4
5232 // CHECK4-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
5233 // CHECK4-NEXT:    store i64 400, i64* [[TMP94]], align 4
5234 // CHECK4-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
5235 // CHECK4-NEXT:    store i8* null, i8** [[TMP95]], align 4
5236 // CHECK4-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
5237 // CHECK4-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
5238 // CHECK4-NEXT:    store i32 5, i32* [[TMP97]], align 4
5239 // CHECK4-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
5240 // CHECK4-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
5241 // CHECK4-NEXT:    store i32 5, i32* [[TMP99]], align 4
5242 // CHECK4-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
5243 // CHECK4-NEXT:    store i64 4, i64* [[TMP100]], align 4
5244 // CHECK4-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
5245 // CHECK4-NEXT:    store i8* null, i8** [[TMP101]], align 4
5246 // CHECK4-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
5247 // CHECK4-NEXT:    [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i32*
5248 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP103]], align 4
5249 // CHECK4-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
5250 // CHECK4-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i32*
5251 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP105]], align 4
5252 // CHECK4-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
5253 // CHECK4-NEXT:    store i64 4, i64* [[TMP106]], align 4
5254 // CHECK4-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
5255 // CHECK4-NEXT:    store i8* null, i8** [[TMP107]], align 4
5256 // CHECK4-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
5257 // CHECK4-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to double**
5258 // CHECK4-NEXT:    store double* [[VLA1]], double** [[TMP109]], align 4
5259 // CHECK4-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
5260 // CHECK4-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
5261 // CHECK4-NEXT:    store double* [[VLA1]], double** [[TMP111]], align 4
5262 // CHECK4-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
5263 // CHECK4-NEXT:    store i64 [[TMP65]], i64* [[TMP112]], align 4
5264 // CHECK4-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
5265 // CHECK4-NEXT:    store i8* null, i8** [[TMP113]], align 4
5266 // CHECK4-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
5267 // CHECK4-NEXT:    [[TMP115:%.*]] = bitcast i8** [[TMP114]] to %struct.TT**
5268 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP115]], align 4
5269 // CHECK4-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
5270 // CHECK4-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
5271 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 4
5272 // CHECK4-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
5273 // CHECK4-NEXT:    store i64 12, i64* [[TMP118]], align 4
5274 // CHECK4-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
5275 // CHECK4-NEXT:    store i8* null, i8** [[TMP119]], align 4
5276 // CHECK4-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
5277 // CHECK4-NEXT:    [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32*
5278 // CHECK4-NEXT:    store i32 [[TMP59]], i32* [[TMP121]], align 4
5279 // CHECK4-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
5280 // CHECK4-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
5281 // CHECK4-NEXT:    store i32 [[TMP59]], i32* [[TMP123]], align 4
5282 // CHECK4-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
5283 // CHECK4-NEXT:    store i64 4, i64* [[TMP124]], align 4
5284 // CHECK4-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
5285 // CHECK4-NEXT:    store i8* null, i8** [[TMP125]], align 4
5286 // CHECK4-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
5287 // CHECK4-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
5288 // CHECK4-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5289 // CHECK4-NEXT:    [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
5290 // CHECK4-NEXT:    [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0
5291 // CHECK4-NEXT:    br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
5292 // CHECK4:       omp_offload.failed17:
5293 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
5294 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
5295 // CHECK4:       omp_offload.cont18:
5296 // CHECK4-NEXT:    br label [[OMP_IF_END20:%.*]]
5297 // CHECK4:       omp_if.else19:
5298 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
5299 // CHECK4-NEXT:    br label [[OMP_IF_END20]]
5300 // CHECK4:       omp_if.end20:
5301 // CHECK4-NEXT:    [[TMP131:%.*]] = load i32, i32* [[A]], align 4
5302 // CHECK4-NEXT:    [[TMP132:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
5303 // CHECK4-NEXT:    call void @llvm.stackrestore(i8* [[TMP132]])
5304 // CHECK4-NEXT:    ret i32 [[TMP131]]
5305 //
5306 //
5307 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
5308 // CHECK4-SAME: () #[[ATTR2:[0-9]+]] {
5309 // CHECK4-NEXT:  entry:
5310 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
5311 // CHECK4-NEXT:    ret void
5312 //
5313 //
5314 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
5315 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
5316 // CHECK4-NEXT:  entry:
5317 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5318 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5319 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5320 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5321 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5322 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5323 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5324 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5325 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
5326 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5327 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5328 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5329 // CHECK4-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
5330 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5331 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5332 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5333 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5334 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5335 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5336 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
5337 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5338 // CHECK4:       cond.true:
5339 // CHECK4-NEXT:    br label [[COND_END:%.*]]
5340 // CHECK4:       cond.false:
5341 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5342 // CHECK4-NEXT:    br label [[COND_END]]
5343 // CHECK4:       cond.end:
5344 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5345 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5346 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5347 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5348 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5349 // CHECK4:       omp.inner.for.cond:
5350 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5351 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
5352 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5353 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5354 // CHECK4:       omp.inner.for.body:
5355 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5356 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
5357 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
5358 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
5359 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5360 // CHECK4:       omp.body.continue:
5361 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5362 // CHECK4:       omp.inner.for.inc:
5363 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5364 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
5365 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5366 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
5367 // CHECK4:       omp.inner.for.end:
5368 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5369 // CHECK4:       omp.loop.exit:
5370 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5371 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5372 // CHECK4-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
5373 // CHECK4-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5374 // CHECK4:       .omp.final.then:
5375 // CHECK4-NEXT:    store i32 33, i32* [[I]], align 4
5376 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5377 // CHECK4:       .omp.final.done:
5378 // CHECK4-NEXT:    ret void
5379 //
5380 //
5381 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry.
5382 // CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
5383 // CHECK4-NEXT:  entry:
5384 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
5385 // CHECK4-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
5386 // CHECK4-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
5387 // CHECK4-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
5388 // CHECK4-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
5389 // CHECK4-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
5390 // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
5391 // CHECK4-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
5392 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
5393 // CHECK4-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
5394 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
5395 // CHECK4-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
5396 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
5397 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
5398 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
5399 // CHECK4-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
5400 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
5401 // CHECK4-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
5402 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
5403 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
5404 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
5405 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
5406 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
5407 // CHECK4-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26
5408 // CHECK4-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26
5409 // CHECK4-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26
5410 // CHECK4-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26
5411 // CHECK4-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
5412 // CHECK4-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
5413 // CHECK4-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
5414 // CHECK4-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
5415 // CHECK4-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
5416 // CHECK4:       omp_offload.failed.i:
5417 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
5418 // CHECK4-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
5419 // CHECK4:       .omp_outlined..1.exit:
5420 // CHECK4-NEXT:    ret i32 0
5421 //
5422 //
5423 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
5424 // CHECK4-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
5425 // CHECK4-NEXT:  entry:
5426 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5427 // CHECK4-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
5428 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5429 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5430 // CHECK4-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
5431 // CHECK4-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
5432 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5433 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5434 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5435 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
5436 // CHECK4-NEXT:    ret void
5437 //
5438 //
5439 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
5440 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
5441 // CHECK4-NEXT:  entry:
5442 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5443 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5444 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5445 // CHECK4-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
5446 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5447 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5448 // CHECK4-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
5449 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5450 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5451 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5452 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5453 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
5454 // CHECK4-NEXT:    [[K1:%.*]] = alloca i64, align 8
5455 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5456 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5457 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5458 // CHECK4-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
5459 // CHECK4-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
5460 // CHECK4-NEXT:    [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
5461 // CHECK4-NEXT:    store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
5462 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5463 // CHECK4-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
5464 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5465 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5466 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5467 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
5468 // CHECK4-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
5469 // CHECK4-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
5470 // CHECK4-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
5471 // CHECK4:       omp.dispatch.cond:
5472 // CHECK4-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
5473 // CHECK4-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
5474 // CHECK4-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
5475 // CHECK4:       omp.dispatch.body:
5476 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5477 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
5478 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5479 // CHECK4:       omp.inner.for.cond:
5480 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
5481 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
5482 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
5483 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5484 // CHECK4:       omp.inner.for.body:
5485 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
5486 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
5487 // CHECK4-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
5488 // CHECK4-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !27
5489 // CHECK4-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !27
5490 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
5491 // CHECK4-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
5492 // CHECK4-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
5493 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
5494 // CHECK4-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !27
5495 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !27
5496 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
5497 // CHECK4-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !27
5498 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5499 // CHECK4:       omp.body.continue:
5500 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5501 // CHECK4:       omp.inner.for.inc:
5502 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
5503 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
5504 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
5505 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
5506 // CHECK4:       omp.inner.for.end:
5507 // CHECK4-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
5508 // CHECK4:       omp.dispatch.inc:
5509 // CHECK4-NEXT:    br label [[OMP_DISPATCH_COND]]
5510 // CHECK4:       omp.dispatch.end:
5511 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5512 // CHECK4-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
5513 // CHECK4-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5514 // CHECK4:       .omp.final.then:
5515 // CHECK4-NEXT:    store i32 1, i32* [[I]], align 4
5516 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5517 // CHECK4:       .omp.final.done:
5518 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5519 // CHECK4-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
5520 // CHECK4-NEXT:    br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
5521 // CHECK4:       .omp.linear.pu:
5522 // CHECK4-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
5523 // CHECK4-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP17]], 27
5524 // CHECK4-NEXT:    store i64 [[ADD5]], i64* [[TMP0]], align 8
5525 // CHECK4-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
5526 // CHECK4:       .omp.linear.pu.done:
5527 // CHECK4-NEXT:    ret void
5528 //
5529 //
5530 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
5531 // CHECK4-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
5532 // CHECK4-NEXT:  entry:
5533 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5534 // CHECK4-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
5535 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5536 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5537 // CHECK4-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
5538 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5539 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5540 // CHECK4-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
5541 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5542 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5543 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
5544 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5545 // CHECK4-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
5546 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5547 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
5548 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
5549 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
5550 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
5551 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
5552 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
5553 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
5554 // CHECK4-NEXT:    ret void
5555 //
5556 //
5557 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
5558 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {
5559 // CHECK4-NEXT:  entry:
5560 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5561 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5562 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5563 // CHECK4-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
5564 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5565 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
5566 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i64, align 4
5567 // CHECK4-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
5568 // CHECK4-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
5569 // CHECK4-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
5570 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
5571 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
5572 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
5573 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5574 // CHECK4-NEXT:    [[IT:%.*]] = alloca i64, align 8
5575 // CHECK4-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
5576 // CHECK4-NEXT:    [[A3:%.*]] = alloca i32, align 4
5577 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5578 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5579 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5580 // CHECK4-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
5581 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5582 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5583 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
5584 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
5585 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5586 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
5587 // CHECK4-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
5588 // CHECK4-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
5589 // CHECK4-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
5590 // CHECK4-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
5591 // CHECK4-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
5592 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5593 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5594 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
5595 // CHECK4-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
5596 // CHECK4-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
5597 // CHECK4-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5598 // CHECK4-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
5599 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5600 // CHECK4:       cond.true:
5601 // CHECK4-NEXT:    br label [[COND_END:%.*]]
5602 // CHECK4:       cond.false:
5603 // CHECK4-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
5604 // CHECK4-NEXT:    br label [[COND_END]]
5605 // CHECK4:       cond.end:
5606 // CHECK4-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
5607 // CHECK4-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
5608 // CHECK4-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
5609 // CHECK4-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
5610 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5611 // CHECK4:       omp.inner.for.cond:
5612 // CHECK4-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
5613 // CHECK4-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
5614 // CHECK4-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
5615 // CHECK4-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5616 // CHECK4:       omp.inner.for.body:
5617 // CHECK4-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
5618 // CHECK4-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
5619 // CHECK4-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
5620 // CHECK4-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !30
5621 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !30
5622 // CHECK4-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
5623 // CHECK4-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
5624 // CHECK4-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
5625 // CHECK4-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
5626 // CHECK4-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
5627 // CHECK4-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
5628 // CHECK4-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !30
5629 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
5630 // CHECK4-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
5631 // CHECK4-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
5632 // CHECK4-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
5633 // CHECK4-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
5634 // CHECK4-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
5635 // CHECK4-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
5636 // CHECK4-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
5637 // CHECK4-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
5638 // CHECK4-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
5639 // CHECK4-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
5640 // CHECK4-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
5641 // CHECK4-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
5642 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5643 // CHECK4:       omp.body.continue:
5644 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5645 // CHECK4:       omp.inner.for.inc:
5646 // CHECK4-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
5647 // CHECK4-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
5648 // CHECK4-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
5649 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
5650 // CHECK4:       omp.inner.for.end:
5651 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5652 // CHECK4:       omp.loop.exit:
5653 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
5654 // CHECK4-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5655 // CHECK4-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
5656 // CHECK4-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5657 // CHECK4:       .omp.final.then:
5658 // CHECK4-NEXT:    store i64 400, i64* [[IT]], align 8
5659 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5660 // CHECK4:       .omp.final.done:
5661 // CHECK4-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5662 // CHECK4-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
5663 // CHECK4-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
5664 // CHECK4:       .omp.linear.pu:
5665 // CHECK4-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
5666 // CHECK4-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
5667 // CHECK4-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
5668 // CHECK4-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP23]]
5669 // CHECK4-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
5670 // CHECK4-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
5671 // CHECK4-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
5672 // CHECK4-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
5673 // CHECK4-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
5674 // CHECK4-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
5675 // CHECK4-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP25]]
5676 // CHECK4-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
5677 // CHECK4-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
5678 // CHECK4-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
5679 // CHECK4-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
5680 // CHECK4:       .omp.linear.pu.done:
5681 // CHECK4-NEXT:    ret void
5682 //
5683 //
5684 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
5685 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
5686 // CHECK4-NEXT:  entry:
5687 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5688 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5689 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5690 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5691 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5692 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5693 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5694 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5695 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
5696 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
5697 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
5698 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5699 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
5700 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5701 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
5702 // CHECK4-NEXT:    ret void
5703 //
5704 //
5705 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
5706 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
5707 // CHECK4-NEXT:  entry:
5708 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5709 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5710 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5711 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5712 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5713 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i16, align 2
5714 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5715 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5716 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5717 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5718 // CHECK4-NEXT:    [[IT:%.*]] = alloca i16, align 2
5719 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5720 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5721 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5722 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5723 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5724 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5725 // CHECK4-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
5726 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5727 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5728 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5729 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5730 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5731 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5732 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
5733 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5734 // CHECK4:       cond.true:
5735 // CHECK4-NEXT:    br label [[COND_END:%.*]]
5736 // CHECK4:       cond.false:
5737 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5738 // CHECK4-NEXT:    br label [[COND_END]]
5739 // CHECK4:       cond.end:
5740 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5741 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5742 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5743 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5744 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5745 // CHECK4:       omp.inner.for.cond:
5746 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
5747 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
5748 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5749 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5750 // CHECK4:       omp.inner.for.body:
5751 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
5752 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
5753 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
5754 // CHECK4-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
5755 // CHECK4-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
5756 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
5757 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
5758 // CHECK4-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
5759 // CHECK4-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
5760 // CHECK4-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
5761 // CHECK4-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
5762 // CHECK4-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
5763 // CHECK4-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
5764 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5765 // CHECK4:       omp.body.continue:
5766 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5767 // CHECK4:       omp.inner.for.inc:
5768 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
5769 // CHECK4-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
5770 // CHECK4-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
5771 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
5772 // CHECK4:       omp.inner.for.end:
5773 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5774 // CHECK4:       omp.loop.exit:
5775 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5776 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5777 // CHECK4-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
5778 // CHECK4-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5779 // CHECK4:       .omp.final.then:
5780 // CHECK4-NEXT:    store i16 22, i16* [[IT]], align 2
5781 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5782 // CHECK4:       .omp.final.done:
5783 // CHECK4-NEXT:    ret void
5784 //
5785 //
5786 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
5787 // CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
5788 // CHECK4-NEXT:  entry:
5789 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5790 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
5791 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
5792 // CHECK4-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
5793 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
5794 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
5795 // CHECK4-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
5796 // CHECK4-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
5797 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
5798 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
5799 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5800 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5801 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5802 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
5803 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5804 // CHECK4-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
5805 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
5806 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5807 // CHECK4-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
5808 // CHECK4-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
5809 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
5810 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5811 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
5812 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5813 // CHECK4-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
5814 // CHECK4-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
5815 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5816 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
5817 // CHECK4-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
5818 // CHECK4-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
5819 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
5820 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
5821 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
5822 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5823 // CHECK4-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5824 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5825 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
5826 // CHECK4-NEXT:    ret void
5827 //
5828 //
5829 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7
5830 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
5831 // CHECK4-NEXT:  entry:
5832 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5833 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5834 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5835 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
5836 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
5837 // CHECK4-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
5838 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
5839 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
5840 // CHECK4-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
5841 // CHECK4-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
5842 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
5843 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
5844 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5845 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i8, align 1
5846 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5847 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5848 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5849 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5850 // CHECK4-NEXT:    [[IT:%.*]] = alloca i8, align 1
5851 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5852 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5853 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5854 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
5855 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5856 // CHECK4-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
5857 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
5858 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5859 // CHECK4-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
5860 // CHECK4-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
5861 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
5862 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5863 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
5864 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5865 // CHECK4-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
5866 // CHECK4-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
5867 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5868 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
5869 // CHECK4-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
5870 // CHECK4-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
5871 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5872 // CHECK4-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
5873 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5874 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5875 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5876 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5877 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
5878 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
5879 // CHECK4-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
5880 // CHECK4:       omp.dispatch.cond:
5881 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5882 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
5883 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5884 // CHECK4:       cond.true:
5885 // CHECK4-NEXT:    br label [[COND_END:%.*]]
5886 // CHECK4:       cond.false:
5887 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5888 // CHECK4-NEXT:    br label [[COND_END]]
5889 // CHECK4:       cond.end:
5890 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
5891 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5892 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5893 // CHECK4-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
5894 // CHECK4-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5895 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5896 // CHECK4-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
5897 // CHECK4-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
5898 // CHECK4:       omp.dispatch.body:
5899 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5900 // CHECK4:       omp.inner.for.cond:
5901 // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
5902 // CHECK4-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
5903 // CHECK4-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
5904 // CHECK4-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5905 // CHECK4:       omp.inner.for.body:
5906 // CHECK4-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
5907 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
5908 // CHECK4-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
5909 // CHECK4-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
5910 // CHECK4-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !36
5911 // CHECK4-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
5912 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
5913 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
5914 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
5915 // CHECK4-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
5916 // CHECK4-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
5917 // CHECK4-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
5918 // CHECK4-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
5919 // CHECK4-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
5920 // CHECK4-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
5921 // CHECK4-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
5922 // CHECK4-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
5923 // CHECK4-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
5924 // CHECK4-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
5925 // CHECK4-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
5926 // CHECK4-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
5927 // CHECK4-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
5928 // CHECK4-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
5929 // CHECK4-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
5930 // CHECK4-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
5931 // CHECK4-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
5932 // CHECK4-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
5933 // CHECK4-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
5934 // CHECK4-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
5935 // CHECK4-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
5936 // CHECK4-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
5937 // CHECK4-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
5938 // CHECK4-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
5939 // CHECK4-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
5940 // CHECK4-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !36
5941 // CHECK4-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
5942 // CHECK4-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
5943 // CHECK4-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
5944 // CHECK4-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
5945 // CHECK4-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
5946 // CHECK4-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !36
5947 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5948 // CHECK4:       omp.body.continue:
5949 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5950 // CHECK4:       omp.inner.for.inc:
5951 // CHECK4-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
5952 // CHECK4-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
5953 // CHECK4-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
5954 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
5955 // CHECK4:       omp.inner.for.end:
5956 // CHECK4-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
5957 // CHECK4:       omp.dispatch.inc:
5958 // CHECK4-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5959 // CHECK4-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5960 // CHECK4-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
5961 // CHECK4-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
5962 // CHECK4-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5963 // CHECK4-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5964 // CHECK4-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
5965 // CHECK4-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
5966 // CHECK4-NEXT:    br label [[OMP_DISPATCH_COND]]
5967 // CHECK4:       omp.dispatch.end:
5968 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
5969 // CHECK4-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5970 // CHECK4-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
5971 // CHECK4-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5972 // CHECK4:       .omp.final.then:
5973 // CHECK4-NEXT:    store i8 96, i8* [[IT]], align 1
5974 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5975 // CHECK4:       .omp.final.done:
5976 // CHECK4-NEXT:    ret void
5977 //
5978 //
5979 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari
5980 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
5981 // CHECK4-NEXT:  entry:
5982 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5983 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
5984 // CHECK4-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
5985 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5986 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
5987 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5988 // CHECK4-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
5989 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
5990 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
5991 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
5992 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
5993 // CHECK4-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
5994 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
5995 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
5996 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
5997 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
5998 // CHECK4-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
5999 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6000 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6001 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6002 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6003 // CHECK4-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
6004 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
6005 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
6006 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
6007 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
6008 // CHECK4-NEXT:    ret i32 [[TMP8]]
6009 //
6010 //
6011 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6012 // CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6013 // CHECK4-NEXT:  entry:
6014 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6015 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6016 // CHECK4-NEXT:    [[B:%.*]] = alloca i32, align 4
6017 // CHECK4-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
6018 // CHECK4-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
6019 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6020 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
6021 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
6022 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
6023 // CHECK4-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
6024 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6025 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6026 // CHECK4-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6027 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6028 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6029 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
6030 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6031 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
6032 // CHECK4-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
6033 // CHECK4-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
6034 // CHECK4-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
6035 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
6036 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
6037 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
6038 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
6039 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6040 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
6041 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6042 // CHECK4:       omp_if.then:
6043 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
6044 // CHECK4-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
6045 // CHECK4-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
6046 // CHECK4-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
6047 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6048 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
6049 // CHECK4-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
6050 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6051 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
6052 // CHECK4-NEXT:    store double* [[A]], double** [[TMP13]], align 4
6053 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6054 // CHECK4-NEXT:    store i64 8, i64* [[TMP14]], align 4
6055 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6056 // CHECK4-NEXT:    store i8* null, i8** [[TMP15]], align 4
6057 // CHECK4-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6058 // CHECK4-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
6059 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
6060 // CHECK4-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6061 // CHECK4-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
6062 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
6063 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
6064 // CHECK4-NEXT:    store i64 4, i64* [[TMP20]], align 4
6065 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6066 // CHECK4-NEXT:    store i8* null, i8** [[TMP21]], align 4
6067 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6068 // CHECK4-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
6069 // CHECK4-NEXT:    store i32 2, i32* [[TMP23]], align 4
6070 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6071 // CHECK4-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
6072 // CHECK4-NEXT:    store i32 2, i32* [[TMP25]], align 4
6073 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
6074 // CHECK4-NEXT:    store i64 4, i64* [[TMP26]], align 4
6075 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6076 // CHECK4-NEXT:    store i8* null, i8** [[TMP27]], align 4
6077 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6078 // CHECK4-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
6079 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
6080 // CHECK4-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6081 // CHECK4-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
6082 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
6083 // CHECK4-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
6084 // CHECK4-NEXT:    store i64 4, i64* [[TMP32]], align 4
6085 // CHECK4-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6086 // CHECK4-NEXT:    store i8* null, i8** [[TMP33]], align 4
6087 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
6088 // CHECK4-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
6089 // CHECK4-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
6090 // CHECK4-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
6091 // CHECK4-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
6092 // CHECK4-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
6093 // CHECK4-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
6094 // CHECK4-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
6095 // CHECK4-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
6096 // CHECK4-NEXT:    store i8* null, i8** [[TMP39]], align 4
6097 // CHECK4-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6098 // CHECK4-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6099 // CHECK4-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6100 // CHECK4-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
6101 // CHECK4-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
6102 // CHECK4-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6103 // CHECK4:       omp_offload.failed:
6104 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
6105 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6106 // CHECK4:       omp_offload.cont:
6107 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6108 // CHECK4:       omp_if.else:
6109 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
6110 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6111 // CHECK4:       omp_if.end:
6112 // CHECK4-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
6113 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
6114 // CHECK4-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
6115 // CHECK4-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
6116 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
6117 // CHECK4-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
6118 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
6119 // CHECK4-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
6120 // CHECK4-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
6121 // CHECK4-NEXT:    ret i32 [[ADD3]]
6122 //
6123 //
6124 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici
6125 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
6126 // CHECK4-NEXT:  entry:
6127 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6128 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6129 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
6130 // CHECK4-NEXT:    [[AAA:%.*]] = alloca i8, align 1
6131 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6132 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6133 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6134 // CHECK4-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6135 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
6136 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
6137 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
6138 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6139 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6140 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
6141 // CHECK4-NEXT:    store i8 0, i8* [[AAA]], align 1
6142 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6143 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6144 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6145 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
6146 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6147 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
6148 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6149 // CHECK4-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
6150 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
6151 // CHECK4-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
6152 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
6153 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6154 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
6155 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6156 // CHECK4:       omp_if.then:
6157 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6158 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
6159 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
6160 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6161 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
6162 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
6163 // CHECK4-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6164 // CHECK4-NEXT:    store i8* null, i8** [[TMP11]], align 4
6165 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6166 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
6167 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
6168 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6169 // CHECK4-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
6170 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
6171 // CHECK4-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6172 // CHECK4-NEXT:    store i8* null, i8** [[TMP16]], align 4
6173 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6174 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
6175 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
6176 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6177 // CHECK4-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
6178 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
6179 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6180 // CHECK4-NEXT:    store i8* null, i8** [[TMP21]], align 4
6181 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6182 // CHECK4-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
6183 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
6184 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6185 // CHECK4-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
6186 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
6187 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6188 // CHECK4-NEXT:    store i8* null, i8** [[TMP26]], align 4
6189 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6190 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6191 // CHECK4-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
6192 // CHECK4-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
6193 // CHECK4-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6194 // CHECK4:       omp_offload.failed:
6195 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
6196 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6197 // CHECK4:       omp_offload.cont:
6198 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6199 // CHECK4:       omp_if.else:
6200 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
6201 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6202 // CHECK4:       omp_if.end:
6203 // CHECK4-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
6204 // CHECK4-NEXT:    ret i32 [[TMP31]]
6205 //
6206 //
6207 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6208 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
6209 // CHECK4-NEXT:  entry:
6210 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6211 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6212 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
6213 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6214 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6215 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6216 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
6217 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
6218 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
6219 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6220 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6221 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
6222 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6223 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6224 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6225 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
6226 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6227 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
6228 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6229 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6230 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
6231 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6232 // CHECK4:       omp_if.then:
6233 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6234 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
6235 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
6236 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6237 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
6238 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
6239 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6240 // CHECK4-NEXT:    store i8* null, i8** [[TMP9]], align 4
6241 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6242 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
6243 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
6244 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6245 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
6246 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
6247 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6248 // CHECK4-NEXT:    store i8* null, i8** [[TMP14]], align 4
6249 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6250 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
6251 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
6252 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6253 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
6254 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
6255 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6256 // CHECK4-NEXT:    store i8* null, i8** [[TMP19]], align 4
6257 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6258 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6259 // CHECK4-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
6260 // CHECK4-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
6261 // CHECK4-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6262 // CHECK4:       omp_offload.failed:
6263 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
6264 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6265 // CHECK4:       omp_offload.cont:
6266 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6267 // CHECK4:       omp_if.else:
6268 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
6269 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6270 // CHECK4:       omp_if.end:
6271 // CHECK4-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
6272 // CHECK4-NEXT:    ret i32 [[TMP24]]
6273 //
6274 //
6275 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
6276 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
6277 // CHECK4-NEXT:  entry:
6278 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6279 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6280 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6281 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6282 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6283 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6284 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6285 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6286 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6287 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6288 // CHECK4-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6289 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6290 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6291 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6292 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6293 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
6294 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
6295 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
6296 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
6297 // CHECK4-NEXT:    ret void
6298 //
6299 //
6300 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9
6301 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
6302 // CHECK4-NEXT:  entry:
6303 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6304 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6305 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6306 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6307 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6308 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6309 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6310 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
6311 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i64, align 4
6312 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
6313 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
6314 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
6315 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6316 // CHECK4-NEXT:    [[IT:%.*]] = alloca i64, align 8
6317 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6318 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6319 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6320 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6321 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6322 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6323 // CHECK4-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6324 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6325 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6326 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6327 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6328 // CHECK4-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
6329 // CHECK4-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
6330 // CHECK4-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
6331 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6332 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6333 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6334 // CHECK4-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
6335 // CHECK4-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6336 // CHECK4-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
6337 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6338 // CHECK4:       cond.true:
6339 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6340 // CHECK4:       cond.false:
6341 // CHECK4-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6342 // CHECK4-NEXT:    br label [[COND_END]]
6343 // CHECK4:       cond.end:
6344 // CHECK4-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6345 // CHECK4-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
6346 // CHECK4-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
6347 // CHECK4-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
6348 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6349 // CHECK4:       omp.inner.for.cond:
6350 // CHECK4-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
6351 // CHECK4-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !39
6352 // CHECK4-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
6353 // CHECK4-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6354 // CHECK4:       omp.inner.for.body:
6355 // CHECK4-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
6356 // CHECK4-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
6357 // CHECK4-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
6358 // CHECK4-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !39
6359 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
6360 // CHECK4-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
6361 // CHECK4-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
6362 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6363 // CHECK4-NEXT:    store double [[ADD]], double* [[A]], align 4, !llvm.access.group !39
6364 // CHECK4-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
6365 // CHECK4-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !39
6366 // CHECK4-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
6367 // CHECK4-NEXT:    store double [[INC]], double* [[A4]], align 4, !llvm.access.group !39
6368 // CHECK4-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
6369 // CHECK4-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
6370 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
6371 // CHECK4-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
6372 // CHECK4-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !39
6373 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6374 // CHECK4:       omp.body.continue:
6375 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6376 // CHECK4:       omp.inner.for.inc:
6377 // CHECK4-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
6378 // CHECK4-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
6379 // CHECK4-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
6380 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
6381 // CHECK4:       omp.inner.for.end:
6382 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6383 // CHECK4:       omp.loop.exit:
6384 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
6385 // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6386 // CHECK4-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
6387 // CHECK4-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6388 // CHECK4:       .omp.final.then:
6389 // CHECK4-NEXT:    store i64 400, i64* [[IT]], align 8
6390 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6391 // CHECK4:       .omp.final.done:
6392 // CHECK4-NEXT:    ret void
6393 //
6394 //
6395 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
6396 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6397 // CHECK4-NEXT:  entry:
6398 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6399 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6400 // CHECK4-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6401 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6402 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6403 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6404 // CHECK4-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6405 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6406 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6407 // CHECK4-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6408 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6409 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6410 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6411 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6412 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6413 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
6414 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
6415 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
6416 // CHECK4-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6417 // CHECK4-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
6418 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6419 // CHECK4-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
6420 // CHECK4-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
6421 // CHECK4-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
6422 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
6423 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
6424 // CHECK4-NEXT:    ret void
6425 //
6426 //
6427 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
6428 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
6429 // CHECK4-NEXT:  entry:
6430 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6431 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6432 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6433 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6434 // CHECK4-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6435 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6436 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6437 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6438 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6439 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6440 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6441 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6442 // CHECK4-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6443 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6444 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6445 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6446 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6447 // CHECK4-NEXT:    ret void
6448 //
6449 //
6450 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
6451 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6452 // CHECK4-NEXT:  entry:
6453 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6454 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6455 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6456 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6457 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6458 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6459 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6460 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6461 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6462 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6463 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6464 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
6465 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
6466 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
6467 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6468 // CHECK4-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
6469 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6470 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
6471 // CHECK4-NEXT:    ret void
6472 //
6473 //
6474 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14
6475 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
6476 // CHECK4-NEXT:  entry:
6477 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6478 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6479 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6480 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6481 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6482 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
6483 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i64, align 4
6484 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
6485 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
6486 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
6487 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6488 // CHECK4-NEXT:    [[I:%.*]] = alloca i64, align 8
6489 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6490 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6491 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6492 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6493 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6494 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6495 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6496 // CHECK4-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
6497 // CHECK4-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
6498 // CHECK4-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
6499 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6500 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6501 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
6502 // CHECK4-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
6503 // CHECK4-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6504 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
6505 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6506 // CHECK4:       cond.true:
6507 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6508 // CHECK4:       cond.false:
6509 // CHECK4-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
6510 // CHECK4-NEXT:    br label [[COND_END]]
6511 // CHECK4:       cond.end:
6512 // CHECK4-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
6513 // CHECK4-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
6514 // CHECK4-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
6515 // CHECK4-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
6516 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6517 // CHECK4:       omp.inner.for.cond:
6518 // CHECK4-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
6519 // CHECK4-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !42
6520 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
6521 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6522 // CHECK4:       omp.inner.for.body:
6523 // CHECK4-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
6524 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
6525 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
6526 // CHECK4-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !42
6527 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
6528 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
6529 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
6530 // CHECK4-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !42
6531 // CHECK4-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
6532 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
6533 // CHECK4-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
6534 // CHECK4-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !42
6535 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
6536 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
6537 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
6538 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
6539 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6540 // CHECK4:       omp.body.continue:
6541 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6542 // CHECK4:       omp.inner.for.inc:
6543 // CHECK4-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
6544 // CHECK4-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
6545 // CHECK4-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42
6546 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
6547 // CHECK4:       omp.inner.for.end:
6548 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6549 // CHECK4:       omp.loop.exit:
6550 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
6551 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6552 // CHECK4-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
6553 // CHECK4-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6554 // CHECK4:       .omp.final.then:
6555 // CHECK4-NEXT:    store i64 11, i64* [[I]], align 8
6556 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6557 // CHECK4:       .omp.final.done:
6558 // CHECK4-NEXT:    ret void
6559 //
6560 //
6561 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
6562 // CHECK4-SAME: () #[[ATTR7:[0-9]+]] {
6563 // CHECK4-NEXT:  entry:
6564 // CHECK4-NEXT:    call void @__tgt_register_requires(i64 1)
6565 // CHECK4-NEXT:    ret void
6566 //
6567 //
6568 // CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv
6569 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
6570 // CHECK5-NEXT:  entry:
6571 // CHECK5-NEXT:    ret i64 0
6572 //
6573 //
6574 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi
6575 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
6576 // CHECK5-NEXT:  entry:
6577 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6578 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
6579 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
6580 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
6581 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
6582 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
6583 // CHECK5-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
6584 // CHECK5-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
6585 // CHECK5-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
6586 // CHECK5-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
6587 // CHECK5-NEXT:    [[K:%.*]] = alloca i64, align 8
6588 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6589 // CHECK5-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
6590 // CHECK5-NEXT:    [[LIN:%.*]] = alloca i32, align 4
6591 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
6592 // CHECK5-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
6593 // CHECK5-NEXT:    [[A_CASTED4:%.*]] = alloca i64, align 8
6594 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
6595 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
6596 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
6597 // CHECK5-NEXT:    [[A_CASTED6:%.*]] = alloca i64, align 8
6598 // CHECK5-NEXT:    [[AA_CASTED8:%.*]] = alloca i64, align 8
6599 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
6600 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
6601 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
6602 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
6603 // CHECK5-NEXT:    [[A_CASTED15:%.*]] = alloca i64, align 8
6604 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
6605 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
6606 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
6607 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
6608 // CHECK5-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
6609 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
6610 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6611 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
6612 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
6613 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6614 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
6615 // CHECK5-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
6616 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
6617 // CHECK5-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
6618 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
6619 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6620 // CHECK5-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
6621 // CHECK5-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
6622 // CHECK5-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
6623 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
6624 // CHECK5-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
6625 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
6626 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
6627 // CHECK5-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]])
6628 // CHECK5-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
6629 // CHECK5-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
6630 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
6631 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6632 // CHECK5-NEXT:    store i32 [[TMP11]], i32* [[CONV]], align 4
6633 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
6634 // CHECK5-NEXT:    [[TMP13:%.*]] = load i64, i64* [[K]], align 8
6635 // CHECK5-NEXT:    store i64 [[TMP13]], i64* [[K_CASTED]], align 8
6636 // CHECK5-NEXT:    [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8
6637 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]]
6638 // CHECK5-NEXT:    store i32 12, i32* [[LIN]], align 4
6639 // CHECK5-NEXT:    [[TMP15:%.*]] = load i16, i16* [[AA]], align 2
6640 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6641 // CHECK5-NEXT:    store i16 [[TMP15]], i16* [[CONV2]], align 2
6642 // CHECK5-NEXT:    [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6643 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4
6644 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
6645 // CHECK5-NEXT:    store i32 [[TMP17]], i32* [[CONV3]], align 4
6646 // CHECK5-NEXT:    [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
6647 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A]], align 4
6648 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
6649 // CHECK5-NEXT:    store i32 [[TMP19]], i32* [[CONV5]], align 4
6650 // CHECK5-NEXT:    [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8
6651 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6652 // CHECK5-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
6653 // CHECK5-NEXT:    store i64 [[TMP16]], i64* [[TMP22]], align 8
6654 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6655 // CHECK5-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
6656 // CHECK5-NEXT:    store i64 [[TMP16]], i64* [[TMP24]], align 8
6657 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
6658 // CHECK5-NEXT:    store i8* null, i8** [[TMP25]], align 8
6659 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6660 // CHECK5-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
6661 // CHECK5-NEXT:    store i64 [[TMP18]], i64* [[TMP27]], align 8
6662 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6663 // CHECK5-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
6664 // CHECK5-NEXT:    store i64 [[TMP18]], i64* [[TMP29]], align 8
6665 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
6666 // CHECK5-NEXT:    store i8* null, i8** [[TMP30]], align 8
6667 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6668 // CHECK5-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
6669 // CHECK5-NEXT:    store i64 [[TMP20]], i64* [[TMP32]], align 8
6670 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6671 // CHECK5-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
6672 // CHECK5-NEXT:    store i64 [[TMP20]], i64* [[TMP34]], align 8
6673 // CHECK5-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
6674 // CHECK5-NEXT:    store i8* null, i8** [[TMP35]], align 8
6675 // CHECK5-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6676 // CHECK5-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6677 // CHECK5-NEXT:    [[TMP38:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
6678 // CHECK5-NEXT:    [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
6679 // CHECK5-NEXT:    br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6680 // CHECK5:       omp_offload.failed:
6681 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]]
6682 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6683 // CHECK5:       omp_offload.cont:
6684 // CHECK5-NEXT:    [[TMP40:%.*]] = load i32, i32* [[A]], align 4
6685 // CHECK5-NEXT:    [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
6686 // CHECK5-NEXT:    store i32 [[TMP40]], i32* [[CONV7]], align 4
6687 // CHECK5-NEXT:    [[TMP41:%.*]] = load i64, i64* [[A_CASTED6]], align 8
6688 // CHECK5-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2
6689 // CHECK5-NEXT:    [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
6690 // CHECK5-NEXT:    store i16 [[TMP42]], i16* [[CONV9]], align 2
6691 // CHECK5-NEXT:    [[TMP43:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
6692 // CHECK5-NEXT:    [[TMP44:%.*]] = load i32, i32* [[N_ADDR]], align 4
6693 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP44]], 10
6694 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6695 // CHECK5:       omp_if.then:
6696 // CHECK5-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
6697 // CHECK5-NEXT:    [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
6698 // CHECK5-NEXT:    store i64 [[TMP41]], i64* [[TMP46]], align 8
6699 // CHECK5-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
6700 // CHECK5-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
6701 // CHECK5-NEXT:    store i64 [[TMP41]], i64* [[TMP48]], align 8
6702 // CHECK5-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
6703 // CHECK5-NEXT:    store i8* null, i8** [[TMP49]], align 8
6704 // CHECK5-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
6705 // CHECK5-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
6706 // CHECK5-NEXT:    store i64 [[TMP43]], i64* [[TMP51]], align 8
6707 // CHECK5-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
6708 // CHECK5-NEXT:    [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
6709 // CHECK5-NEXT:    store i64 [[TMP43]], i64* [[TMP53]], align 8
6710 // CHECK5-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
6711 // CHECK5-NEXT:    store i8* null, i8** [[TMP54]], align 8
6712 // CHECK5-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
6713 // CHECK5-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
6714 // CHECK5-NEXT:    [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
6715 // CHECK5-NEXT:    [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
6716 // CHECK5-NEXT:    br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
6717 // CHECK5:       omp_offload.failed13:
6718 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
6719 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT14]]
6720 // CHECK5:       omp_offload.cont14:
6721 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
6722 // CHECK5:       omp_if.else:
6723 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
6724 // CHECK5-NEXT:    br label [[OMP_IF_END]]
6725 // CHECK5:       omp_if.end:
6726 // CHECK5-NEXT:    [[TMP59:%.*]] = load i32, i32* [[A]], align 4
6727 // CHECK5-NEXT:    store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_]], align 4
6728 // CHECK5-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
6729 // CHECK5-NEXT:    [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
6730 // CHECK5-NEXT:    store i32 [[TMP60]], i32* [[CONV16]], align 4
6731 // CHECK5-NEXT:    [[TMP61:%.*]] = load i64, i64* [[A_CASTED15]], align 8
6732 // CHECK5-NEXT:    [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6733 // CHECK5-NEXT:    [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
6734 // CHECK5-NEXT:    store i32 [[TMP62]], i32* [[CONV17]], align 4
6735 // CHECK5-NEXT:    [[TMP63:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
6736 // CHECK5-NEXT:    [[TMP64:%.*]] = load i32, i32* [[N_ADDR]], align 4
6737 // CHECK5-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP64]], 20
6738 // CHECK5-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
6739 // CHECK5:       omp_if.then19:
6740 // CHECK5-NEXT:    [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4
6741 // CHECK5-NEXT:    [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]]
6742 // CHECK5-NEXT:    [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8
6743 // CHECK5-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
6744 // CHECK5-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
6745 // CHECK5-NEXT:    store i64 [[TMP61]], i64* [[TMP69]], align 8
6746 // CHECK5-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
6747 // CHECK5-NEXT:    [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64*
6748 // CHECK5-NEXT:    store i64 [[TMP61]], i64* [[TMP71]], align 8
6749 // CHECK5-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6750 // CHECK5-NEXT:    store i64 4, i64* [[TMP72]], align 8
6751 // CHECK5-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
6752 // CHECK5-NEXT:    store i8* null, i8** [[TMP73]], align 8
6753 // CHECK5-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
6754 // CHECK5-NEXT:    [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
6755 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 8
6756 // CHECK5-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
6757 // CHECK5-NEXT:    [[TMP77:%.*]] = bitcast i8** [[TMP76]] to [10 x float]**
6758 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP77]], align 8
6759 // CHECK5-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
6760 // CHECK5-NEXT:    store i64 40, i64* [[TMP78]], align 8
6761 // CHECK5-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
6762 // CHECK5-NEXT:    store i8* null, i8** [[TMP79]], align 8
6763 // CHECK5-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
6764 // CHECK5-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
6765 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP81]], align 8
6766 // CHECK5-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
6767 // CHECK5-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
6768 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP83]], align 8
6769 // CHECK5-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
6770 // CHECK5-NEXT:    store i64 8, i64* [[TMP84]], align 8
6771 // CHECK5-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
6772 // CHECK5-NEXT:    store i8* null, i8** [[TMP85]], align 8
6773 // CHECK5-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
6774 // CHECK5-NEXT:    [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
6775 // CHECK5-NEXT:    store float* [[VLA]], float** [[TMP87]], align 8
6776 // CHECK5-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
6777 // CHECK5-NEXT:    [[TMP89:%.*]] = bitcast i8** [[TMP88]] to float**
6778 // CHECK5-NEXT:    store float* [[VLA]], float** [[TMP89]], align 8
6779 // CHECK5-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
6780 // CHECK5-NEXT:    store i64 [[TMP65]], i64* [[TMP90]], align 8
6781 // CHECK5-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
6782 // CHECK5-NEXT:    store i8* null, i8** [[TMP91]], align 8
6783 // CHECK5-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
6784 // CHECK5-NEXT:    [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
6785 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 8
6786 // CHECK5-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
6787 // CHECK5-NEXT:    [[TMP95:%.*]] = bitcast i8** [[TMP94]] to [5 x [10 x double]]**
6788 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP95]], align 8
6789 // CHECK5-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
6790 // CHECK5-NEXT:    store i64 400, i64* [[TMP96]], align 8
6791 // CHECK5-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
6792 // CHECK5-NEXT:    store i8* null, i8** [[TMP97]], align 8
6793 // CHECK5-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
6794 // CHECK5-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
6795 // CHECK5-NEXT:    store i64 5, i64* [[TMP99]], align 8
6796 // CHECK5-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
6797 // CHECK5-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
6798 // CHECK5-NEXT:    store i64 5, i64* [[TMP101]], align 8
6799 // CHECK5-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
6800 // CHECK5-NEXT:    store i64 8, i64* [[TMP102]], align 8
6801 // CHECK5-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
6802 // CHECK5-NEXT:    store i8* null, i8** [[TMP103]], align 8
6803 // CHECK5-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
6804 // CHECK5-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64*
6805 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP105]], align 8
6806 // CHECK5-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
6807 // CHECK5-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
6808 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP107]], align 8
6809 // CHECK5-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
6810 // CHECK5-NEXT:    store i64 8, i64* [[TMP108]], align 8
6811 // CHECK5-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
6812 // CHECK5-NEXT:    store i8* null, i8** [[TMP109]], align 8
6813 // CHECK5-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
6814 // CHECK5-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
6815 // CHECK5-NEXT:    store double* [[VLA1]], double** [[TMP111]], align 8
6816 // CHECK5-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
6817 // CHECK5-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to double**
6818 // CHECK5-NEXT:    store double* [[VLA1]], double** [[TMP113]], align 8
6819 // CHECK5-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
6820 // CHECK5-NEXT:    store i64 [[TMP67]], i64* [[TMP114]], align 8
6821 // CHECK5-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
6822 // CHECK5-NEXT:    store i8* null, i8** [[TMP115]], align 8
6823 // CHECK5-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
6824 // CHECK5-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
6825 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 8
6826 // CHECK5-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
6827 // CHECK5-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to %struct.TT**
6828 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP119]], align 8
6829 // CHECK5-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
6830 // CHECK5-NEXT:    store i64 16, i64* [[TMP120]], align 8
6831 // CHECK5-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
6832 // CHECK5-NEXT:    store i8* null, i8** [[TMP121]], align 8
6833 // CHECK5-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
6834 // CHECK5-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
6835 // CHECK5-NEXT:    store i64 [[TMP63]], i64* [[TMP123]], align 8
6836 // CHECK5-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
6837 // CHECK5-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
6838 // CHECK5-NEXT:    store i64 [[TMP63]], i64* [[TMP125]], align 8
6839 // CHECK5-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
6840 // CHECK5-NEXT:    store i64 4, i64* [[TMP126]], align 8
6841 // CHECK5-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
6842 // CHECK5-NEXT:    store i8* null, i8** [[TMP127]], align 8
6843 // CHECK5-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
6844 // CHECK5-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
6845 // CHECK5-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6846 // CHECK5-NEXT:    [[TMP131:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP128]], i8** [[TMP129]], i64* [[TMP130]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
6847 // CHECK5-NEXT:    [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0
6848 // CHECK5-NEXT:    br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
6849 // CHECK5:       omp_offload.failed23:
6850 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
6851 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT24]]
6852 // CHECK5:       omp_offload.cont24:
6853 // CHECK5-NEXT:    br label [[OMP_IF_END26:%.*]]
6854 // CHECK5:       omp_if.else25:
6855 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
6856 // CHECK5-NEXT:    br label [[OMP_IF_END26]]
6857 // CHECK5:       omp_if.end26:
6858 // CHECK5-NEXT:    [[TMP133:%.*]] = load i32, i32* [[A]], align 4
6859 // CHECK5-NEXT:    [[TMP134:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
6860 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP134]])
6861 // CHECK5-NEXT:    ret i32 [[TMP133]]
6862 //
6863 //
6864 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
6865 // CHECK5-SAME: () #[[ATTR2:[0-9]+]] {
6866 // CHECK5-NEXT:  entry:
6867 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
6868 // CHECK5-NEXT:    ret void
6869 //
6870 //
6871 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
6872 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
6873 // CHECK5-NEXT:  entry:
6874 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6875 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6876 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6877 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6878 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6879 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6880 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6881 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6882 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
6883 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6884 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6885 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6886 // CHECK5-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
6887 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6888 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6889 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6890 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6891 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6892 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6893 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
6894 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6895 // CHECK5:       cond.true:
6896 // CHECK5-NEXT:    br label [[COND_END:%.*]]
6897 // CHECK5:       cond.false:
6898 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6899 // CHECK5-NEXT:    br label [[COND_END]]
6900 // CHECK5:       cond.end:
6901 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6902 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6903 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6904 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6905 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6906 // CHECK5:       omp.inner.for.cond:
6907 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
6908 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
6909 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6910 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6911 // CHECK5:       omp.inner.for.body:
6912 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
6913 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
6914 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
6915 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
6916 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6917 // CHECK5:       omp.body.continue:
6918 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6919 // CHECK5:       omp.inner.for.inc:
6920 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
6921 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
6922 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
6923 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
6924 // CHECK5:       omp.inner.for.end:
6925 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6926 // CHECK5:       omp.loop.exit:
6927 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6928 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6929 // CHECK5-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
6930 // CHECK5-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6931 // CHECK5:       .omp.final.then:
6932 // CHECK5-NEXT:    store i32 33, i32* [[I]], align 4
6933 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6934 // CHECK5:       .omp.final.done:
6935 // CHECK5-NEXT:    ret void
6936 //
6937 //
6938 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry.
6939 // CHECK5-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
6940 // CHECK5-NEXT:  entry:
6941 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
6942 // CHECK5-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
6943 // CHECK5-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
6944 // CHECK5-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
6945 // CHECK5-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
6946 // CHECK5-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
6947 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
6948 // CHECK5-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
6949 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
6950 // CHECK5-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
6951 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
6952 // CHECK5-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
6953 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
6954 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
6955 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
6956 // CHECK5-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
6957 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
6958 // CHECK5-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
6959 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
6960 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
6961 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
6962 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
6963 // CHECK5-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
6964 // CHECK5-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25
6965 // CHECK5-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25
6966 // CHECK5-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25
6967 // CHECK5-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25
6968 // CHECK5-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
6969 // CHECK5-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
6970 // CHECK5-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
6971 // CHECK5-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
6972 // CHECK5-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
6973 // CHECK5:       omp_offload.failed.i:
6974 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
6975 // CHECK5-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
6976 // CHECK5:       .omp_outlined..1.exit:
6977 // CHECK5-NEXT:    ret i32 0
6978 //
6979 //
6980 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
6981 // CHECK5-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
6982 // CHECK5-NEXT:  entry:
6983 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6984 // CHECK5-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
6985 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6986 // CHECK5-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
6987 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
6988 // CHECK5-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
6989 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6990 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6991 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6992 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
6993 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
6994 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
6995 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[K_CASTED]], align 8
6996 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
6997 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
6998 // CHECK5-NEXT:    ret void
6999 //
7000 //
7001 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
7002 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
7003 // CHECK5-NEXT:  entry:
7004 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7005 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7006 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7007 // CHECK5-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
7008 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7009 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7010 // CHECK5-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
7011 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7012 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7013 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7014 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7015 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
7016 // CHECK5-NEXT:    [[K1:%.*]] = alloca i64, align 8
7017 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7018 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7019 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7020 // CHECK5-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
7021 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7022 // CHECK5-NEXT:    [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
7023 // CHECK5-NEXT:    store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
7024 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7025 // CHECK5-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
7026 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7027 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7028 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7029 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
7030 // CHECK5-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
7031 // CHECK5-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
7032 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
7033 // CHECK5:       omp.dispatch.cond:
7034 // CHECK5-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
7035 // CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
7036 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7037 // CHECK5:       omp.dispatch.body:
7038 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7039 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
7040 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7041 // CHECK5:       omp.inner.for.cond:
7042 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
7043 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
7044 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
7045 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7046 // CHECK5:       omp.inner.for.body:
7047 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
7048 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
7049 // CHECK5-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
7050 // CHECK5-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
7051 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
7052 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
7053 // CHECK5-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
7054 // CHECK5-NEXT:    [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
7055 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
7056 // CHECK5-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
7057 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
7058 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
7059 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
7060 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7061 // CHECK5:       omp.body.continue:
7062 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7063 // CHECK5:       omp.inner.for.inc:
7064 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
7065 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
7066 // CHECK5-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
7067 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
7068 // CHECK5:       omp.inner.for.end:
7069 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
7070 // CHECK5:       omp.dispatch.inc:
7071 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]]
7072 // CHECK5:       omp.dispatch.end:
7073 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7074 // CHECK5-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
7075 // CHECK5-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7076 // CHECK5:       .omp.final.then:
7077 // CHECK5-NEXT:    store i32 1, i32* [[I]], align 4
7078 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7079 // CHECK5:       .omp.final.done:
7080 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7081 // CHECK5-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
7082 // CHECK5-NEXT:    br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
7083 // CHECK5:       .omp.linear.pu:
7084 // CHECK5-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
7085 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP16]], 27
7086 // CHECK5-NEXT:    store i64 [[ADD6]], i64* [[K_ADDR]], align 8
7087 // CHECK5-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
7088 // CHECK5:       .omp.linear.pu.done:
7089 // CHECK5-NEXT:    ret void
7090 //
7091 //
7092 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
7093 // CHECK5-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
7094 // CHECK5-NEXT:  entry:
7095 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7096 // CHECK5-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
7097 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7098 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
7099 // CHECK5-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
7100 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7101 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
7102 // CHECK5-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
7103 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7104 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7105 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
7106 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7107 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
7108 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7109 // CHECK5-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
7110 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7111 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
7112 // CHECK5-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
7113 // CHECK5-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
7114 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
7115 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
7116 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7117 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
7118 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
7119 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
7120 // CHECK5-NEXT:    ret void
7121 //
7122 //
7123 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
7124 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
7125 // CHECK5-NEXT:  entry:
7126 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7127 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7128 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7129 // CHECK5-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
7130 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7131 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
7132 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i64, align 8
7133 // CHECK5-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
7134 // CHECK5-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
7135 // CHECK5-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
7136 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
7137 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
7138 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
7139 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7140 // CHECK5-NEXT:    [[IT:%.*]] = alloca i64, align 8
7141 // CHECK5-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
7142 // CHECK5-NEXT:    [[A5:%.*]] = alloca i32, align 4
7143 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7144 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7145 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
7146 // CHECK5-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
7147 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7148 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7149 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
7150 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7151 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
7152 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
7153 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
7154 // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
7155 // CHECK5-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
7156 // CHECK5-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
7157 // CHECK5-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
7158 // CHECK5-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
7159 // CHECK5-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
7160 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7161 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7162 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
7163 // CHECK5-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
7164 // CHECK5-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
7165 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
7166 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
7167 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7168 // CHECK5:       cond.true:
7169 // CHECK5-NEXT:    br label [[COND_END:%.*]]
7170 // CHECK5:       cond.false:
7171 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
7172 // CHECK5-NEXT:    br label [[COND_END]]
7173 // CHECK5:       cond.end:
7174 // CHECK5-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
7175 // CHECK5-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
7176 // CHECK5-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
7177 // CHECK5-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
7178 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7179 // CHECK5:       omp.inner.for.cond:
7180 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
7181 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
7182 // CHECK5-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
7183 // CHECK5-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7184 // CHECK5:       omp.inner.for.body:
7185 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
7186 // CHECK5-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
7187 // CHECK5-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
7188 // CHECK5-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !29
7189 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !29
7190 // CHECK5-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
7191 // CHECK5-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
7192 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
7193 // CHECK5-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
7194 // CHECK5-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
7195 // CHECK5-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
7196 // CHECK5-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !29
7197 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
7198 // CHECK5-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
7199 // CHECK5-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
7200 // CHECK5-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
7201 // CHECK5-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
7202 // CHECK5-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
7203 // CHECK5-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
7204 // CHECK5-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
7205 // CHECK5-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
7206 // CHECK5-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
7207 // CHECK5-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
7208 // CHECK5-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
7209 // CHECK5-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
7210 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7211 // CHECK5:       omp.body.continue:
7212 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7213 // CHECK5:       omp.inner.for.inc:
7214 // CHECK5-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
7215 // CHECK5-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
7216 // CHECK5-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
7217 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
7218 // CHECK5:       omp.inner.for.end:
7219 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7220 // CHECK5:       omp.loop.exit:
7221 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
7222 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7223 // CHECK5-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
7224 // CHECK5-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7225 // CHECK5:       .omp.final.then:
7226 // CHECK5-NEXT:    store i64 400, i64* [[IT]], align 8
7227 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7228 // CHECK5:       .omp.final.done:
7229 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7230 // CHECK5-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
7231 // CHECK5-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
7232 // CHECK5:       .omp.linear.pu:
7233 // CHECK5-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
7234 // CHECK5-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
7235 // CHECK5-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
7236 // CHECK5-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP23]]
7237 // CHECK5-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
7238 // CHECK5-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
7239 // CHECK5-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
7240 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
7241 // CHECK5-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
7242 // CHECK5-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
7243 // CHECK5-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP25]]
7244 // CHECK5-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
7245 // CHECK5-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
7246 // CHECK5-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
7247 // CHECK5-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
7248 // CHECK5:       .omp.linear.pu.done:
7249 // CHECK5-NEXT:    ret void
7250 //
7251 //
7252 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
7253 // CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
7254 // CHECK5-NEXT:  entry:
7255 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7256 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7257 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7258 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
7259 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7260 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
7261 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7262 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7263 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
7264 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7265 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
7266 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
7267 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
7268 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7269 // CHECK5-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
7270 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7271 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
7272 // CHECK5-NEXT:    ret void
7273 //
7274 //
7275 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4
7276 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
7277 // CHECK5-NEXT:  entry:
7278 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7279 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7280 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7281 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7282 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7283 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i16, align 2
7284 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7285 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7286 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7287 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7288 // CHECK5-NEXT:    [[IT:%.*]] = alloca i16, align 2
7289 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7290 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7291 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7292 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
7293 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7294 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7295 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7296 // CHECK5-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
7297 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7298 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7299 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7300 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
7301 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7302 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7303 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
7304 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7305 // CHECK5:       cond.true:
7306 // CHECK5-NEXT:    br label [[COND_END:%.*]]
7307 // CHECK5:       cond.false:
7308 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7309 // CHECK5-NEXT:    br label [[COND_END]]
7310 // CHECK5:       cond.end:
7311 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
7312 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7313 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7314 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
7315 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7316 // CHECK5:       omp.inner.for.cond:
7317 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
7318 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
7319 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
7320 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7321 // CHECK5:       omp.inner.for.body:
7322 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
7323 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
7324 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
7325 // CHECK5-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
7326 // CHECK5-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
7327 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
7328 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
7329 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
7330 // CHECK5-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
7331 // CHECK5-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
7332 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
7333 // CHECK5-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
7334 // CHECK5-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
7335 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7336 // CHECK5:       omp.body.continue:
7337 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7338 // CHECK5:       omp.inner.for.inc:
7339 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
7340 // CHECK5-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
7341 // CHECK5-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
7342 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
7343 // CHECK5:       omp.inner.for.end:
7344 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7345 // CHECK5:       omp.loop.exit:
7346 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
7347 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7348 // CHECK5-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
7349 // CHECK5-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7350 // CHECK5:       .omp.final.then:
7351 // CHECK5-NEXT:    store i16 22, i16* [[IT]], align 2
7352 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7353 // CHECK5:       .omp.final.done:
7354 // CHECK5-NEXT:    ret void
7355 //
7356 //
7357 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
7358 // CHECK5-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
7359 // CHECK5-NEXT:  entry:
7360 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7361 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
7362 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
7363 // CHECK5-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
7364 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
7365 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
7366 // CHECK5-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
7367 // CHECK5-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
7368 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
7369 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
7370 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7371 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
7372 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7373 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
7374 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
7375 // CHECK5-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
7376 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
7377 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
7378 // CHECK5-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
7379 // CHECK5-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
7380 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
7381 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
7382 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7383 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
7384 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
7385 // CHECK5-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
7386 // CHECK5-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
7387 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
7388 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
7389 // CHECK5-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
7390 // CHECK5-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
7391 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
7392 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
7393 // CHECK5-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7394 // CHECK5-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
7395 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
7396 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
7397 // CHECK5-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
7398 // CHECK5-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
7399 // CHECK5-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
7400 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
7401 // CHECK5-NEXT:    ret void
7402 //
7403 //
7404 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7
7405 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
7406 // CHECK5-NEXT:  entry:
7407 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7408 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7409 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7410 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
7411 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
7412 // CHECK5-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
7413 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
7414 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
7415 // CHECK5-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
7416 // CHECK5-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
7417 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
7418 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
7419 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7420 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i8, align 1
7421 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7422 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7423 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7424 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7425 // CHECK5-NEXT:    [[IT:%.*]] = alloca i8, align 1
7426 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7427 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7428 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7429 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
7430 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
7431 // CHECK5-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
7432 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
7433 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
7434 // CHECK5-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
7435 // CHECK5-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
7436 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
7437 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
7438 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7439 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
7440 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
7441 // CHECK5-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
7442 // CHECK5-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
7443 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
7444 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
7445 // CHECK5-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
7446 // CHECK5-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
7447 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
7448 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7449 // CHECK5-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
7450 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7451 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7452 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
7453 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7454 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
7455 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
7456 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
7457 // CHECK5:       omp.dispatch.cond:
7458 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7459 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
7460 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7461 // CHECK5:       cond.true:
7462 // CHECK5-NEXT:    br label [[COND_END:%.*]]
7463 // CHECK5:       cond.false:
7464 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7465 // CHECK5-NEXT:    br label [[COND_END]]
7466 // CHECK5:       cond.end:
7467 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
7468 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7469 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7470 // CHECK5-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
7471 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7472 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7473 // CHECK5-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
7474 // CHECK5-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7475 // CHECK5:       omp.dispatch.body:
7476 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7477 // CHECK5:       omp.inner.for.cond:
7478 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
7479 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
7480 // CHECK5-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
7481 // CHECK5-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7482 // CHECK5:       omp.inner.for.body:
7483 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
7484 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
7485 // CHECK5-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
7486 // CHECK5-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
7487 // CHECK5-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
7488 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
7489 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
7490 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
7491 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
7492 // CHECK5-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
7493 // CHECK5-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
7494 // CHECK5-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
7495 // CHECK5-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
7496 // CHECK5-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
7497 // CHECK5-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
7498 // CHECK5-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
7499 // CHECK5-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
7500 // CHECK5-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
7501 // CHECK5-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
7502 // CHECK5-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
7503 // CHECK5-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
7504 // CHECK5-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
7505 // CHECK5-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
7506 // CHECK5-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
7507 // CHECK5-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
7508 // CHECK5-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
7509 // CHECK5-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
7510 // CHECK5-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
7511 // CHECK5-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
7512 // CHECK5-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
7513 // CHECK5-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
7514 // CHECK5-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
7515 // CHECK5-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
7516 // CHECK5-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
7517 // CHECK5-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !35
7518 // CHECK5-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
7519 // CHECK5-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
7520 // CHECK5-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
7521 // CHECK5-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
7522 // CHECK5-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
7523 // CHECK5-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !35
7524 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7525 // CHECK5:       omp.body.continue:
7526 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7527 // CHECK5:       omp.inner.for.inc:
7528 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
7529 // CHECK5-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
7530 // CHECK5-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
7531 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
7532 // CHECK5:       omp.inner.for.end:
7533 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
7534 // CHECK5:       omp.dispatch.inc:
7535 // CHECK5-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7536 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7537 // CHECK5-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
7538 // CHECK5-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
7539 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7540 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7541 // CHECK5-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
7542 // CHECK5-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
7543 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]]
7544 // CHECK5:       omp.dispatch.end:
7545 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
7546 // CHECK5-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7547 // CHECK5-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
7548 // CHECK5-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7549 // CHECK5:       .omp.final.then:
7550 // CHECK5-NEXT:    store i8 96, i8* [[IT]], align 1
7551 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7552 // CHECK5:       .omp.final.done:
7553 // CHECK5-NEXT:    ret void
7554 //
7555 //
7556 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari
7557 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7558 // CHECK5-NEXT:  entry:
7559 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7560 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7561 // CHECK5-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
7562 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7563 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7564 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7565 // CHECK5-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
7566 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7567 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7568 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7569 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7570 // CHECK5-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
7571 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7572 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7573 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7574 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7575 // CHECK5-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
7576 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7577 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7578 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7579 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7580 // CHECK5-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
7581 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7582 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7583 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7584 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7585 // CHECK5-NEXT:    ret i32 [[TMP8]]
7586 //
7587 //
7588 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7589 // CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7590 // CHECK5-NEXT:  entry:
7591 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
7592 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7593 // CHECK5-NEXT:    [[B:%.*]] = alloca i32, align 4
7594 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7595 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7596 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7597 // CHECK5-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
7598 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
7599 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 8
7600 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 8
7601 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 8
7602 // CHECK5-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8
7603 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
7604 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7605 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
7606 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7607 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7608 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
7609 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7610 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
7611 // CHECK5-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
7612 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
7613 // CHECK5-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
7614 // CHECK5-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
7615 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
7616 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
7617 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
7618 // CHECK5-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
7619 // CHECK5-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
7620 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
7621 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
7622 // CHECK5-NEXT:    store i32 [[TMP6]], i32* [[CONV]], align 4
7623 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, i64* [[B_CASTED]], align 8
7624 // CHECK5-NEXT:    [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7625 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
7626 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
7627 // CHECK5-NEXT:    [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
7628 // CHECK5-NEXT:    store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
7629 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
7630 // CHECK5-NEXT:    [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7631 // CHECK5-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP10]] to i1
7632 // CHECK5-NEXT:    br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7633 // CHECK5:       omp_if.then:
7634 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7635 // CHECK5-NEXT:    [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]]
7636 // CHECK5-NEXT:    [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2
7637 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7638 // CHECK5-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to %struct.S1**
7639 // CHECK5-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP14]], align 8
7640 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7641 // CHECK5-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double**
7642 // CHECK5-NEXT:    store double* [[A]], double** [[TMP16]], align 8
7643 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
7644 // CHECK5-NEXT:    store i64 8, i64* [[TMP17]], align 8
7645 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
7646 // CHECK5-NEXT:    store i8* null, i8** [[TMP18]], align 8
7647 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7648 // CHECK5-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
7649 // CHECK5-NEXT:    store i64 [[TMP7]], i64* [[TMP20]], align 8
7650 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7651 // CHECK5-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
7652 // CHECK5-NEXT:    store i64 [[TMP7]], i64* [[TMP22]], align 8
7653 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
7654 // CHECK5-NEXT:    store i64 4, i64* [[TMP23]], align 8
7655 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
7656 // CHECK5-NEXT:    store i8* null, i8** [[TMP24]], align 8
7657 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
7658 // CHECK5-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
7659 // CHECK5-NEXT:    store i64 2, i64* [[TMP26]], align 8
7660 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7661 // CHECK5-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
7662 // CHECK5-NEXT:    store i64 2, i64* [[TMP28]], align 8
7663 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
7664 // CHECK5-NEXT:    store i64 8, i64* [[TMP29]], align 8
7665 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
7666 // CHECK5-NEXT:    store i8* null, i8** [[TMP30]], align 8
7667 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
7668 // CHECK5-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
7669 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP32]], align 8
7670 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
7671 // CHECK5-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
7672 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP34]], align 8
7673 // CHECK5-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
7674 // CHECK5-NEXT:    store i64 8, i64* [[TMP35]], align 8
7675 // CHECK5-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
7676 // CHECK5-NEXT:    store i8* null, i8** [[TMP36]], align 8
7677 // CHECK5-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
7678 // CHECK5-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i16**
7679 // CHECK5-NEXT:    store i16* [[VLA]], i16** [[TMP38]], align 8
7680 // CHECK5-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
7681 // CHECK5-NEXT:    [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i16**
7682 // CHECK5-NEXT:    store i16* [[VLA]], i16** [[TMP40]], align 8
7683 // CHECK5-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
7684 // CHECK5-NEXT:    store i64 [[TMP12]], i64* [[TMP41]], align 8
7685 // CHECK5-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
7686 // CHECK5-NEXT:    store i8* null, i8** [[TMP42]], align 8
7687 // CHECK5-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
7688 // CHECK5-NEXT:    [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64*
7689 // CHECK5-NEXT:    store i64 [[TMP9]], i64* [[TMP44]], align 8
7690 // CHECK5-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
7691 // CHECK5-NEXT:    [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
7692 // CHECK5-NEXT:    store i64 [[TMP9]], i64* [[TMP46]], align 8
7693 // CHECK5-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
7694 // CHECK5-NEXT:    store i64 1, i64* [[TMP47]], align 8
7695 // CHECK5-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
7696 // CHECK5-NEXT:    store i8* null, i8** [[TMP48]], align 8
7697 // CHECK5-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7698 // CHECK5-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7699 // CHECK5-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
7700 // CHECK5-NEXT:    [[TMP52:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7701 // CHECK5-NEXT:    [[TOBOOL5:%.*]] = trunc i8 [[TMP52]] to i1
7702 // CHECK5-NEXT:    [[TMP53:%.*]] = select i1 [[TOBOOL5]], i32 0, i32 1
7703 // CHECK5-NEXT:    [[TMP54:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, i32 6, i8** [[TMP49]], i8** [[TMP50]], i64* [[TMP51]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP53]])
7704 // CHECK5-NEXT:    [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0
7705 // CHECK5-NEXT:    br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7706 // CHECK5:       omp_offload.failed:
7707 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
7708 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
7709 // CHECK5:       omp_offload.cont:
7710 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
7711 // CHECK5:       omp_if.else:
7712 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
7713 // CHECK5-NEXT:    br label [[OMP_IF_END]]
7714 // CHECK5:       omp_if.end:
7715 // CHECK5-NEXT:    [[TMP56:%.*]] = mul nsw i64 1, [[TMP2]]
7716 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP56]]
7717 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
7718 // CHECK5-NEXT:    [[TMP57:%.*]] = load i16, i16* [[ARRAYIDX6]], align 2
7719 // CHECK5-NEXT:    [[CONV7:%.*]] = sext i16 [[TMP57]] to i32
7720 // CHECK5-NEXT:    [[TMP58:%.*]] = load i32, i32* [[B]], align 4
7721 // CHECK5-NEXT:    [[ADD8:%.*]] = add nsw i32 [[CONV7]], [[TMP58]]
7722 // CHECK5-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7723 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
7724 // CHECK5-NEXT:    ret i32 [[ADD8]]
7725 //
7726 //
7727 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
7728 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7729 // CHECK5-NEXT:  entry:
7730 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7731 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7732 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
7733 // CHECK5-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7734 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7735 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7736 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
7737 // CHECK5-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
7738 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
7739 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
7740 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
7741 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7742 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7743 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
7744 // CHECK5-NEXT:    store i8 0, i8* [[AAA]], align 1
7745 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7746 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7747 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
7748 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
7749 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7750 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7751 // CHECK5-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
7752 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7753 // CHECK5-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
7754 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
7755 // CHECK5-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
7756 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
7757 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7758 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
7759 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7760 // CHECK5:       omp_if.then:
7761 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7762 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
7763 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
7764 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7765 // CHECK5-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
7766 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
7767 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
7768 // CHECK5-NEXT:    store i8* null, i8** [[TMP11]], align 8
7769 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7770 // CHECK5-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
7771 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
7772 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7773 // CHECK5-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
7774 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
7775 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
7776 // CHECK5-NEXT:    store i8* null, i8** [[TMP16]], align 8
7777 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
7778 // CHECK5-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
7779 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
7780 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7781 // CHECK5-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
7782 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
7783 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
7784 // CHECK5-NEXT:    store i8* null, i8** [[TMP21]], align 8
7785 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
7786 // CHECK5-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
7787 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
7788 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
7789 // CHECK5-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
7790 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
7791 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
7792 // CHECK5-NEXT:    store i8* null, i8** [[TMP26]], align 8
7793 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7794 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7795 // CHECK5-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
7796 // CHECK5-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
7797 // CHECK5-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7798 // CHECK5:       omp_offload.failed:
7799 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
7800 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
7801 // CHECK5:       omp_offload.cont:
7802 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
7803 // CHECK5:       omp_if.else:
7804 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
7805 // CHECK5-NEXT:    br label [[OMP_IF_END]]
7806 // CHECK5:       omp_if.end:
7807 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
7808 // CHECK5-NEXT:    ret i32 [[TMP31]]
7809 //
7810 //
7811 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7812 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
7813 // CHECK5-NEXT:  entry:
7814 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7815 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7816 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
7817 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7818 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7819 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
7820 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
7821 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
7822 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
7823 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7824 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7825 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
7826 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7827 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7828 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
7829 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
7830 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7831 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7832 // CHECK5-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
7833 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7834 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7835 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
7836 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7837 // CHECK5:       omp_if.then:
7838 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7839 // CHECK5-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
7840 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
7841 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7842 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
7843 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
7844 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
7845 // CHECK5-NEXT:    store i8* null, i8** [[TMP9]], align 8
7846 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7847 // CHECK5-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
7848 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
7849 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7850 // CHECK5-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
7851 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
7852 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
7853 // CHECK5-NEXT:    store i8* null, i8** [[TMP14]], align 8
7854 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
7855 // CHECK5-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
7856 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
7857 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7858 // CHECK5-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
7859 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
7860 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
7861 // CHECK5-NEXT:    store i8* null, i8** [[TMP19]], align 8
7862 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7863 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7864 // CHECK5-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
7865 // CHECK5-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
7866 // CHECK5-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7867 // CHECK5:       omp_offload.failed:
7868 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
7869 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
7870 // CHECK5:       omp_offload.cont:
7871 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
7872 // CHECK5:       omp_if.else:
7873 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
7874 // CHECK5-NEXT:    br label [[OMP_IF_END]]
7875 // CHECK5:       omp_if.end:
7876 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
7877 // CHECK5-NEXT:    ret i32 [[TMP24]]
7878 //
7879 //
7880 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
7881 // CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
7882 // CHECK5-NEXT:  entry:
7883 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
7884 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
7885 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
7886 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
7887 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
7888 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
7889 // CHECK5-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
7890 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
7891 // CHECK5-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
7892 // CHECK5-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
7893 // CHECK5-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
7894 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
7895 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
7896 // CHECK5-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
7897 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
7898 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
7899 // CHECK5-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
7900 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
7901 // CHECK5-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
7902 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
7903 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
7904 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
7905 // CHECK5-NEXT:    [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
7906 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
7907 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
7908 // CHECK5-NEXT:    [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
7909 // CHECK5-NEXT:    store i32 [[TMP5]], i32* [[CONV4]], align 4
7910 // CHECK5-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
7911 // CHECK5-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
7912 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
7913 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
7914 // CHECK5-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
7915 // CHECK5-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
7916 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
7917 // CHECK5-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
7918 // CHECK5-NEXT:    [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
7919 // CHECK5-NEXT:    br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7920 // CHECK5:       omp_if.then:
7921 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
7922 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
7923 // CHECK5:       omp_if.else:
7924 // CHECK5-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
7925 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
7926 // CHECK5-NEXT:    call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR4]]
7927 // CHECK5-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
7928 // CHECK5-NEXT:    br label [[OMP_IF_END]]
7929 // CHECK5:       omp_if.end:
7930 // CHECK5-NEXT:    ret void
7931 //
7932 //
7933 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9
7934 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
7935 // CHECK5-NEXT:  entry:
7936 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7937 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7938 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
7939 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
7940 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
7941 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
7942 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
7943 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
7944 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
7945 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i64, align 8
7946 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
7947 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
7948 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
7949 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7950 // CHECK5-NEXT:    [[IT:%.*]] = alloca i64, align 8
7951 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7952 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7953 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
7954 // CHECK5-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
7955 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
7956 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
7957 // CHECK5-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
7958 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
7959 // CHECK5-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
7960 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
7961 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
7962 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
7963 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
7964 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
7965 // CHECK5-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
7966 // CHECK5-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
7967 // CHECK5-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
7968 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7969 // CHECK5-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
7970 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
7971 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7972 // CHECK5:       omp_if.then:
7973 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7974 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
7975 // CHECK5-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
7976 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
7977 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
7978 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7979 // CHECK5:       cond.true:
7980 // CHECK5-NEXT:    br label [[COND_END:%.*]]
7981 // CHECK5:       cond.false:
7982 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
7983 // CHECK5-NEXT:    br label [[COND_END]]
7984 // CHECK5:       cond.end:
7985 // CHECK5-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
7986 // CHECK5-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
7987 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
7988 // CHECK5-NEXT:    store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
7989 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7990 // CHECK5:       omp.inner.for.cond:
7991 // CHECK5-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
7992 // CHECK5-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
7993 // CHECK5-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
7994 // CHECK5-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7995 // CHECK5:       omp.inner.for.body:
7996 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
7997 // CHECK5-NEXT:    [[MUL:%.*]] = mul i64 [[TMP12]], 400
7998 // CHECK5-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
7999 // CHECK5-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
8000 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
8001 // CHECK5-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
8002 // CHECK5-NEXT:    [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
8003 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
8004 // CHECK5-NEXT:    store double [[ADD]], double* [[A]], align 8, !nontemporal !39, !llvm.access.group !38
8005 // CHECK5-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
8006 // CHECK5-NEXT:    [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
8007 // CHECK5-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
8008 // CHECK5-NEXT:    store double [[INC]], double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
8009 // CHECK5-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
8010 // CHECK5-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
8011 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
8012 // CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
8013 // CHECK5-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !38
8014 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8015 // CHECK5:       omp.body.continue:
8016 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8017 // CHECK5:       omp.inner.for.inc:
8018 // CHECK5-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
8019 // CHECK5-NEXT:    [[ADD9:%.*]] = add i64 [[TMP16]], 1
8020 // CHECK5-NEXT:    store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
8021 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
8022 // CHECK5:       omp.inner.for.end:
8023 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
8024 // CHECK5:       omp_if.else:
8025 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8026 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
8027 // CHECK5-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
8028 // CHECK5-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8029 // CHECK5-NEXT:    [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3
8030 // CHECK5-NEXT:    br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
8031 // CHECK5:       cond.true11:
8032 // CHECK5-NEXT:    br label [[COND_END13:%.*]]
8033 // CHECK5:       cond.false12:
8034 // CHECK5-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8035 // CHECK5-NEXT:    br label [[COND_END13]]
8036 // CHECK5:       cond.end13:
8037 // CHECK5-NEXT:    [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ]
8038 // CHECK5-NEXT:    store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8
8039 // CHECK5-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
8040 // CHECK5-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
8041 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND15:%.*]]
8042 // CHECK5:       omp.inner.for.cond15:
8043 // CHECK5-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8044 // CHECK5-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8045 // CHECK5-NEXT:    [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
8046 // CHECK5-NEXT:    br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
8047 // CHECK5:       omp.inner.for.body17:
8048 // CHECK5-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8049 // CHECK5-NEXT:    [[MUL18:%.*]] = mul i64 [[TMP24]], 400
8050 // CHECK5-NEXT:    [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
8051 // CHECK5-NEXT:    store i64 [[SUB19]], i64* [[IT]], align 8
8052 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
8053 // CHECK5-NEXT:    [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
8054 // CHECK5-NEXT:    [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
8055 // CHECK5-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
8056 // CHECK5-NEXT:    store double [[ADD21]], double* [[A22]], align 8
8057 // CHECK5-NEXT:    [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
8058 // CHECK5-NEXT:    [[TMP26:%.*]] = load double, double* [[A23]], align 8
8059 // CHECK5-NEXT:    [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
8060 // CHECK5-NEXT:    store double [[INC24]], double* [[A23]], align 8
8061 // CHECK5-NEXT:    [[CONV25:%.*]] = fptosi double [[INC24]] to i16
8062 // CHECK5-NEXT:    [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]]
8063 // CHECK5-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]]
8064 // CHECK5-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
8065 // CHECK5-NEXT:    store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2
8066 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE28:%.*]]
8067 // CHECK5:       omp.body.continue28:
8068 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC29:%.*]]
8069 // CHECK5:       omp.inner.for.inc29:
8070 // CHECK5-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
8071 // CHECK5-NEXT:    [[ADD30:%.*]] = add i64 [[TMP28]], 1
8072 // CHECK5-NEXT:    store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8
8073 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP42:![0-9]+]]
8074 // CHECK5:       omp.inner.for.end31:
8075 // CHECK5-NEXT:    br label [[OMP_IF_END]]
8076 // CHECK5:       omp_if.end:
8077 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8078 // CHECK5:       omp.loop.exit:
8079 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8080 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
8081 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
8082 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8083 // CHECK5-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
8084 // CHECK5-NEXT:    br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
8085 // CHECK5:       .omp.final.then:
8086 // CHECK5-NEXT:    store i64 400, i64* [[IT]], align 8
8087 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
8088 // CHECK5:       .omp.final.done:
8089 // CHECK5-NEXT:    ret void
8090 //
8091 //
8092 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
8093 // CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8094 // CHECK5-NEXT:  entry:
8095 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8096 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8097 // CHECK5-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
8098 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8099 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8100 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8101 // CHECK5-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
8102 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8103 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8104 // CHECK5-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
8105 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8106 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8107 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8108 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
8109 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8110 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
8111 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8112 // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
8113 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
8114 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
8115 // CHECK5-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8116 // CHECK5-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
8117 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8118 // CHECK5-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
8119 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
8120 // CHECK5-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
8121 // CHECK5-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
8122 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
8123 // CHECK5-NEXT:    ret void
8124 //
8125 //
8126 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11
8127 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
8128 // CHECK5-NEXT:  entry:
8129 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8130 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8131 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8132 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8133 // CHECK5-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
8134 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8135 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8136 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8137 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8138 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8139 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8140 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8141 // CHECK5-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
8142 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8143 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8144 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8145 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
8146 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8147 // CHECK5-NEXT:    ret void
8148 //
8149 //
8150 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
8151 // CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8152 // CHECK5-NEXT:  entry:
8153 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8154 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8155 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8156 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8157 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8158 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8159 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8160 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8161 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8162 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8163 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8164 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
8165 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8166 // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
8167 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
8168 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
8169 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8170 // CHECK5-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
8171 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8172 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
8173 // CHECK5-NEXT:    ret void
8174 //
8175 //
8176 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14
8177 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
8178 // CHECK5-NEXT:  entry:
8179 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8180 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8181 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8182 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8183 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8184 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
8185 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i64, align 8
8186 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
8187 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
8188 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
8189 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8190 // CHECK5-NEXT:    [[I:%.*]] = alloca i64, align 8
8191 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8192 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8193 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8194 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8195 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8196 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8197 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8198 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8199 // CHECK5-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
8200 // CHECK5-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
8201 // CHECK5-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
8202 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8203 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8204 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
8205 // CHECK5-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
8206 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8207 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
8208 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8209 // CHECK5:       cond.true:
8210 // CHECK5-NEXT:    br label [[COND_END:%.*]]
8211 // CHECK5:       cond.false:
8212 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8213 // CHECK5-NEXT:    br label [[COND_END]]
8214 // CHECK5:       cond.end:
8215 // CHECK5-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
8216 // CHECK5-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
8217 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
8218 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
8219 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8220 // CHECK5:       omp.inner.for.cond:
8221 // CHECK5-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
8222 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !44
8223 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
8224 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8225 // CHECK5:       omp.inner.for.body:
8226 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
8227 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
8228 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
8229 // CHECK5-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44
8230 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44
8231 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
8232 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44
8233 // CHECK5-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44
8234 // CHECK5-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
8235 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
8236 // CHECK5-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
8237 // CHECK5-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44
8238 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
8239 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
8240 // CHECK5-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
8241 // CHECK5-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
8242 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8243 // CHECK5:       omp.body.continue:
8244 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8245 // CHECK5:       omp.inner.for.inc:
8246 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
8247 // CHECK5-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
8248 // CHECK5-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
8249 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
8250 // CHECK5:       omp.inner.for.end:
8251 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8252 // CHECK5:       omp.loop.exit:
8253 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
8254 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8255 // CHECK5-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
8256 // CHECK5-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
8257 // CHECK5:       .omp.final.then:
8258 // CHECK5-NEXT:    store i64 11, i64* [[I]], align 8
8259 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
8260 // CHECK5:       .omp.final.done:
8261 // CHECK5-NEXT:    ret void
8262 //
8263 //
8264 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
8265 // CHECK5-SAME: () #[[ATTR7:[0-9]+]] {
8266 // CHECK5-NEXT:  entry:
8267 // CHECK5-NEXT:    call void @__tgt_register_requires(i64 1)
8268 // CHECK5-NEXT:    ret void
8269 //
8270 //
8271 // CHECK6-LABEL: define {{[^@]+}}@_Z7get_valv
8272 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
8273 // CHECK6-NEXT:  entry:
8274 // CHECK6-NEXT:    ret i64 0
8275 //
8276 //
8277 // CHECK6-LABEL: define {{[^@]+}}@_Z3fooi
8278 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
8279 // CHECK6-NEXT:  entry:
8280 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8281 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
8282 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
8283 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
8284 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
8285 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
8286 // CHECK6-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
8287 // CHECK6-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
8288 // CHECK6-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
8289 // CHECK6-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
8290 // CHECK6-NEXT:    [[K:%.*]] = alloca i64, align 8
8291 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8292 // CHECK6-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
8293 // CHECK6-NEXT:    [[LIN:%.*]] = alloca i32, align 4
8294 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8295 // CHECK6-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
8296 // CHECK6-NEXT:    [[A_CASTED4:%.*]] = alloca i64, align 8
8297 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
8298 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
8299 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
8300 // CHECK6-NEXT:    [[A_CASTED6:%.*]] = alloca i64, align 8
8301 // CHECK6-NEXT:    [[AA_CASTED8:%.*]] = alloca i64, align 8
8302 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
8303 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
8304 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
8305 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8306 // CHECK6-NEXT:    [[A_CASTED15:%.*]] = alloca i64, align 8
8307 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
8308 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
8309 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
8310 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
8311 // CHECK6-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
8312 // CHECK6-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
8313 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8314 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
8315 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
8316 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8317 // CHECK6-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
8318 // CHECK6-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
8319 // CHECK6-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
8320 // CHECK6-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
8321 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
8322 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8323 // CHECK6-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
8324 // CHECK6-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
8325 // CHECK6-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
8326 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
8327 // CHECK6-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
8328 // CHECK6-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
8329 // CHECK6-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
8330 // CHECK6-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]])
8331 // CHECK6-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
8332 // CHECK6-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
8333 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
8334 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8335 // CHECK6-NEXT:    store i32 [[TMP11]], i32* [[CONV]], align 4
8336 // CHECK6-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
8337 // CHECK6-NEXT:    [[TMP13:%.*]] = load i64, i64* [[K]], align 8
8338 // CHECK6-NEXT:    store i64 [[TMP13]], i64* [[K_CASTED]], align 8
8339 // CHECK6-NEXT:    [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8
8340 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]]
8341 // CHECK6-NEXT:    store i32 12, i32* [[LIN]], align 4
8342 // CHECK6-NEXT:    [[TMP15:%.*]] = load i16, i16* [[AA]], align 2
8343 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8344 // CHECK6-NEXT:    store i16 [[TMP15]], i16* [[CONV2]], align 2
8345 // CHECK6-NEXT:    [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8346 // CHECK6-NEXT:    [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4
8347 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
8348 // CHECK6-NEXT:    store i32 [[TMP17]], i32* [[CONV3]], align 4
8349 // CHECK6-NEXT:    [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
8350 // CHECK6-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A]], align 4
8351 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
8352 // CHECK6-NEXT:    store i32 [[TMP19]], i32* [[CONV5]], align 4
8353 // CHECK6-NEXT:    [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8
8354 // CHECK6-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8355 // CHECK6-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
8356 // CHECK6-NEXT:    store i64 [[TMP16]], i64* [[TMP22]], align 8
8357 // CHECK6-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8358 // CHECK6-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
8359 // CHECK6-NEXT:    store i64 [[TMP16]], i64* [[TMP24]], align 8
8360 // CHECK6-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8361 // CHECK6-NEXT:    store i8* null, i8** [[TMP25]], align 8
8362 // CHECK6-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8363 // CHECK6-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
8364 // CHECK6-NEXT:    store i64 [[TMP18]], i64* [[TMP27]], align 8
8365 // CHECK6-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8366 // CHECK6-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
8367 // CHECK6-NEXT:    store i64 [[TMP18]], i64* [[TMP29]], align 8
8368 // CHECK6-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
8369 // CHECK6-NEXT:    store i8* null, i8** [[TMP30]], align 8
8370 // CHECK6-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8371 // CHECK6-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
8372 // CHECK6-NEXT:    store i64 [[TMP20]], i64* [[TMP32]], align 8
8373 // CHECK6-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8374 // CHECK6-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
8375 // CHECK6-NEXT:    store i64 [[TMP20]], i64* [[TMP34]], align 8
8376 // CHECK6-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
8377 // CHECK6-NEXT:    store i8* null, i8** [[TMP35]], align 8
8378 // CHECK6-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8379 // CHECK6-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8380 // CHECK6-NEXT:    [[TMP38:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
8381 // CHECK6-NEXT:    [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
8382 // CHECK6-NEXT:    br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8383 // CHECK6:       omp_offload.failed:
8384 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]]
8385 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8386 // CHECK6:       omp_offload.cont:
8387 // CHECK6-NEXT:    [[TMP40:%.*]] = load i32, i32* [[A]], align 4
8388 // CHECK6-NEXT:    [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
8389 // CHECK6-NEXT:    store i32 [[TMP40]], i32* [[CONV7]], align 4
8390 // CHECK6-NEXT:    [[TMP41:%.*]] = load i64, i64* [[A_CASTED6]], align 8
8391 // CHECK6-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2
8392 // CHECK6-NEXT:    [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
8393 // CHECK6-NEXT:    store i16 [[TMP42]], i16* [[CONV9]], align 2
8394 // CHECK6-NEXT:    [[TMP43:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
8395 // CHECK6-NEXT:    [[TMP44:%.*]] = load i32, i32* [[N_ADDR]], align 4
8396 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP44]], 10
8397 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8398 // CHECK6:       omp_if.then:
8399 // CHECK6-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
8400 // CHECK6-NEXT:    [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
8401 // CHECK6-NEXT:    store i64 [[TMP41]], i64* [[TMP46]], align 8
8402 // CHECK6-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
8403 // CHECK6-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64*
8404 // CHECK6-NEXT:    store i64 [[TMP41]], i64* [[TMP48]], align 8
8405 // CHECK6-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
8406 // CHECK6-NEXT:    store i8* null, i8** [[TMP49]], align 8
8407 // CHECK6-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
8408 // CHECK6-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64*
8409 // CHECK6-NEXT:    store i64 [[TMP43]], i64* [[TMP51]], align 8
8410 // CHECK6-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
8411 // CHECK6-NEXT:    [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64*
8412 // CHECK6-NEXT:    store i64 [[TMP43]], i64* [[TMP53]], align 8
8413 // CHECK6-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
8414 // CHECK6-NEXT:    store i8* null, i8** [[TMP54]], align 8
8415 // CHECK6-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
8416 // CHECK6-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
8417 // CHECK6-NEXT:    [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
8418 // CHECK6-NEXT:    [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
8419 // CHECK6-NEXT:    br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
8420 // CHECK6:       omp_offload.failed13:
8421 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
8422 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT14]]
8423 // CHECK6:       omp_offload.cont14:
8424 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
8425 // CHECK6:       omp_if.else:
8426 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]]
8427 // CHECK6-NEXT:    br label [[OMP_IF_END]]
8428 // CHECK6:       omp_if.end:
8429 // CHECK6-NEXT:    [[TMP59:%.*]] = load i32, i32* [[A]], align 4
8430 // CHECK6-NEXT:    store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_]], align 4
8431 // CHECK6-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
8432 // CHECK6-NEXT:    [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
8433 // CHECK6-NEXT:    store i32 [[TMP60]], i32* [[CONV16]], align 4
8434 // CHECK6-NEXT:    [[TMP61:%.*]] = load i64, i64* [[A_CASTED15]], align 8
8435 // CHECK6-NEXT:    [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8436 // CHECK6-NEXT:    [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
8437 // CHECK6-NEXT:    store i32 [[TMP62]], i32* [[CONV17]], align 4
8438 // CHECK6-NEXT:    [[TMP63:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
8439 // CHECK6-NEXT:    [[TMP64:%.*]] = load i32, i32* [[N_ADDR]], align 4
8440 // CHECK6-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP64]], 20
8441 // CHECK6-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
8442 // CHECK6:       omp_if.then19:
8443 // CHECK6-NEXT:    [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4
8444 // CHECK6-NEXT:    [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]]
8445 // CHECK6-NEXT:    [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8
8446 // CHECK6-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
8447 // CHECK6-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
8448 // CHECK6-NEXT:    store i64 [[TMP61]], i64* [[TMP69]], align 8
8449 // CHECK6-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
8450 // CHECK6-NEXT:    [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64*
8451 // CHECK6-NEXT:    store i64 [[TMP61]], i64* [[TMP71]], align 8
8452 // CHECK6-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8453 // CHECK6-NEXT:    store i64 4, i64* [[TMP72]], align 8
8454 // CHECK6-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
8455 // CHECK6-NEXT:    store i8* null, i8** [[TMP73]], align 8
8456 // CHECK6-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
8457 // CHECK6-NEXT:    [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
8458 // CHECK6-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 8
8459 // CHECK6-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
8460 // CHECK6-NEXT:    [[TMP77:%.*]] = bitcast i8** [[TMP76]] to [10 x float]**
8461 // CHECK6-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP77]], align 8
8462 // CHECK6-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
8463 // CHECK6-NEXT:    store i64 40, i64* [[TMP78]], align 8
8464 // CHECK6-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
8465 // CHECK6-NEXT:    store i8* null, i8** [[TMP79]], align 8
8466 // CHECK6-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
8467 // CHECK6-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
8468 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[TMP81]], align 8
8469 // CHECK6-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
8470 // CHECK6-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
8471 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[TMP83]], align 8
8472 // CHECK6-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
8473 // CHECK6-NEXT:    store i64 8, i64* [[TMP84]], align 8
8474 // CHECK6-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
8475 // CHECK6-NEXT:    store i8* null, i8** [[TMP85]], align 8
8476 // CHECK6-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
8477 // CHECK6-NEXT:    [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
8478 // CHECK6-NEXT:    store float* [[VLA]], float** [[TMP87]], align 8
8479 // CHECK6-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
8480 // CHECK6-NEXT:    [[TMP89:%.*]] = bitcast i8** [[TMP88]] to float**
8481 // CHECK6-NEXT:    store float* [[VLA]], float** [[TMP89]], align 8
8482 // CHECK6-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
8483 // CHECK6-NEXT:    store i64 [[TMP65]], i64* [[TMP90]], align 8
8484 // CHECK6-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
8485 // CHECK6-NEXT:    store i8* null, i8** [[TMP91]], align 8
8486 // CHECK6-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
8487 // CHECK6-NEXT:    [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
8488 // CHECK6-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 8
8489 // CHECK6-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
8490 // CHECK6-NEXT:    [[TMP95:%.*]] = bitcast i8** [[TMP94]] to [5 x [10 x double]]**
8491 // CHECK6-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP95]], align 8
8492 // CHECK6-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
8493 // CHECK6-NEXT:    store i64 400, i64* [[TMP96]], align 8
8494 // CHECK6-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
8495 // CHECK6-NEXT:    store i8* null, i8** [[TMP97]], align 8
8496 // CHECK6-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
8497 // CHECK6-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
8498 // CHECK6-NEXT:    store i64 5, i64* [[TMP99]], align 8
8499 // CHECK6-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
8500 // CHECK6-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
8501 // CHECK6-NEXT:    store i64 5, i64* [[TMP101]], align 8
8502 // CHECK6-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
8503 // CHECK6-NEXT:    store i64 8, i64* [[TMP102]], align 8
8504 // CHECK6-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
8505 // CHECK6-NEXT:    store i8* null, i8** [[TMP103]], align 8
8506 // CHECK6-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
8507 // CHECK6-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i64*
8508 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[TMP105]], align 8
8509 // CHECK6-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
8510 // CHECK6-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
8511 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[TMP107]], align 8
8512 // CHECK6-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
8513 // CHECK6-NEXT:    store i64 8, i64* [[TMP108]], align 8
8514 // CHECK6-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
8515 // CHECK6-NEXT:    store i8* null, i8** [[TMP109]], align 8
8516 // CHECK6-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
8517 // CHECK6-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
8518 // CHECK6-NEXT:    store double* [[VLA1]], double** [[TMP111]], align 8
8519 // CHECK6-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
8520 // CHECK6-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to double**
8521 // CHECK6-NEXT:    store double* [[VLA1]], double** [[TMP113]], align 8
8522 // CHECK6-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
8523 // CHECK6-NEXT:    store i64 [[TMP67]], i64* [[TMP114]], align 8
8524 // CHECK6-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
8525 // CHECK6-NEXT:    store i8* null, i8** [[TMP115]], align 8
8526 // CHECK6-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
8527 // CHECK6-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
8528 // CHECK6-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 8
8529 // CHECK6-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
8530 // CHECK6-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to %struct.TT**
8531 // CHECK6-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP119]], align 8
8532 // CHECK6-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
8533 // CHECK6-NEXT:    store i64 16, i64* [[TMP120]], align 8
8534 // CHECK6-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
8535 // CHECK6-NEXT:    store i8* null, i8** [[TMP121]], align 8
8536 // CHECK6-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
8537 // CHECK6-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
8538 // CHECK6-NEXT:    store i64 [[TMP63]], i64* [[TMP123]], align 8
8539 // CHECK6-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
8540 // CHECK6-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
8541 // CHECK6-NEXT:    store i64 [[TMP63]], i64* [[TMP125]], align 8
8542 // CHECK6-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
8543 // CHECK6-NEXT:    store i64 4, i64* [[TMP126]], align 8
8544 // CHECK6-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
8545 // CHECK6-NEXT:    store i8* null, i8** [[TMP127]], align 8
8546 // CHECK6-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
8547 // CHECK6-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
8548 // CHECK6-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8549 // CHECK6-NEXT:    [[TMP131:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP128]], i8** [[TMP129]], i64* [[TMP130]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
8550 // CHECK6-NEXT:    [[TMP132:%.*]] = icmp ne i32 [[TMP131]], 0
8551 // CHECK6-NEXT:    br i1 [[TMP132]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
8552 // CHECK6:       omp_offload.failed23:
8553 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
8554 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT24]]
8555 // CHECK6:       omp_offload.cont24:
8556 // CHECK6-NEXT:    br label [[OMP_IF_END26:%.*]]
8557 // CHECK6:       omp_if.else25:
8558 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]]
8559 // CHECK6-NEXT:    br label [[OMP_IF_END26]]
8560 // CHECK6:       omp_if.end26:
8561 // CHECK6-NEXT:    [[TMP133:%.*]] = load i32, i32* [[A]], align 4
8562 // CHECK6-NEXT:    [[TMP134:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
8563 // CHECK6-NEXT:    call void @llvm.stackrestore(i8* [[TMP134]])
8564 // CHECK6-NEXT:    ret i32 [[TMP133]]
8565 //
8566 //
8567 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
8568 // CHECK6-SAME: () #[[ATTR2:[0-9]+]] {
8569 // CHECK6-NEXT:  entry:
8570 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
8571 // CHECK6-NEXT:    ret void
8572 //
8573 //
8574 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
8575 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
8576 // CHECK6-NEXT:  entry:
8577 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8578 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8579 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8580 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8581 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8582 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8583 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8584 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8585 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
8586 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8587 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8588 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8589 // CHECK6-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
8590 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8591 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8592 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8593 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
8594 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8595 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8596 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
8597 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8598 // CHECK6:       cond.true:
8599 // CHECK6-NEXT:    br label [[COND_END:%.*]]
8600 // CHECK6:       cond.false:
8601 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8602 // CHECK6-NEXT:    br label [[COND_END]]
8603 // CHECK6:       cond.end:
8604 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
8605 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8606 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8607 // CHECK6-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
8608 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8609 // CHECK6:       omp.inner.for.cond:
8610 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8611 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
8612 // CHECK6-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
8613 // CHECK6-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8614 // CHECK6:       omp.inner.for.body:
8615 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8616 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
8617 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
8618 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
8619 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8620 // CHECK6:       omp.body.continue:
8621 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8622 // CHECK6:       omp.inner.for.inc:
8623 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8624 // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
8625 // CHECK6-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8626 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
8627 // CHECK6:       omp.inner.for.end:
8628 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8629 // CHECK6:       omp.loop.exit:
8630 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
8631 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8632 // CHECK6-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
8633 // CHECK6-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
8634 // CHECK6:       .omp.final.then:
8635 // CHECK6-NEXT:    store i32 33, i32* [[I]], align 4
8636 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
8637 // CHECK6:       .omp.final.done:
8638 // CHECK6-NEXT:    ret void
8639 //
8640 //
8641 // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry.
8642 // CHECK6-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
8643 // CHECK6-NEXT:  entry:
8644 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
8645 // CHECK6-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
8646 // CHECK6-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
8647 // CHECK6-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
8648 // CHECK6-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
8649 // CHECK6-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
8650 // CHECK6-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
8651 // CHECK6-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
8652 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
8653 // CHECK6-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
8654 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
8655 // CHECK6-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
8656 // CHECK6-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
8657 // CHECK6-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
8658 // CHECK6-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
8659 // CHECK6-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
8660 // CHECK6-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
8661 // CHECK6-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
8662 // CHECK6-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
8663 // CHECK6-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
8664 // CHECK6-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
8665 // CHECK6-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
8666 // CHECK6-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
8667 // CHECK6-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25
8668 // CHECK6-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25
8669 // CHECK6-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25
8670 // CHECK6-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25
8671 // CHECK6-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
8672 // CHECK6-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25
8673 // CHECK6-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
8674 // CHECK6-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
8675 // CHECK6-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
8676 // CHECK6:       omp_offload.failed.i:
8677 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
8678 // CHECK6-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
8679 // CHECK6:       .omp_outlined..1.exit:
8680 // CHECK6-NEXT:    ret i32 0
8681 //
8682 //
8683 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
8684 // CHECK6-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
8685 // CHECK6-NEXT:  entry:
8686 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8687 // CHECK6-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
8688 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8689 // CHECK6-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
8690 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8691 // CHECK6-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
8692 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8693 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8694 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8695 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
8696 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8697 // CHECK6-NEXT:    [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
8698 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[K_CASTED]], align 8
8699 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
8700 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
8701 // CHECK6-NEXT:    ret void
8702 //
8703 //
8704 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2
8705 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] {
8706 // CHECK6-NEXT:  entry:
8707 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8708 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8709 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8710 // CHECK6-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
8711 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8712 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8713 // CHECK6-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
8714 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8715 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8716 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8717 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8718 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
8719 // CHECK6-NEXT:    [[K1:%.*]] = alloca i64, align 8
8720 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8721 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8722 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8723 // CHECK6-NEXT:    store i64 [[K]], i64* [[K_ADDR]], align 8
8724 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8725 // CHECK6-NEXT:    [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
8726 // CHECK6-NEXT:    store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
8727 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8728 // CHECK6-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
8729 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8730 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8731 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8732 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
8733 // CHECK6-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
8734 // CHECK6-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
8735 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
8736 // CHECK6:       omp.dispatch.cond:
8737 // CHECK6-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
8738 // CHECK6-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
8739 // CHECK6-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
8740 // CHECK6:       omp.dispatch.body:
8741 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8742 // CHECK6-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
8743 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8744 // CHECK6:       omp.inner.for.cond:
8745 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
8746 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
8747 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
8748 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8749 // CHECK6:       omp.inner.for.body:
8750 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
8751 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
8752 // CHECK6-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
8753 // CHECK6-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26
8754 // CHECK6-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26
8755 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
8756 // CHECK6-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
8757 // CHECK6-NEXT:    [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
8758 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
8759 // CHECK6-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26
8760 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
8761 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
8762 // CHECK6-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !26
8763 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8764 // CHECK6:       omp.body.continue:
8765 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8766 // CHECK6:       omp.inner.for.inc:
8767 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
8768 // CHECK6-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
8769 // CHECK6-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
8770 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
8771 // CHECK6:       omp.inner.for.end:
8772 // CHECK6-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
8773 // CHECK6:       omp.dispatch.inc:
8774 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND]]
8775 // CHECK6:       omp.dispatch.end:
8776 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8777 // CHECK6-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
8778 // CHECK6-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
8779 // CHECK6:       .omp.final.then:
8780 // CHECK6-NEXT:    store i32 1, i32* [[I]], align 4
8781 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
8782 // CHECK6:       .omp.final.done:
8783 // CHECK6-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8784 // CHECK6-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
8785 // CHECK6-NEXT:    br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
8786 // CHECK6:       .omp.linear.pu:
8787 // CHECK6-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
8788 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP16]], 27
8789 // CHECK6-NEXT:    store i64 [[ADD6]], i64* [[K_ADDR]], align 8
8790 // CHECK6-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
8791 // CHECK6:       .omp.linear.pu.done:
8792 // CHECK6-NEXT:    ret void
8793 //
8794 //
8795 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
8796 // CHECK6-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
8797 // CHECK6-NEXT:  entry:
8798 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8799 // CHECK6-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
8800 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8801 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8802 // CHECK6-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
8803 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8804 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8805 // CHECK6-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
8806 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8807 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8808 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
8809 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8810 // CHECK6-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
8811 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8812 // CHECK6-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
8813 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8814 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
8815 // CHECK6-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
8816 // CHECK6-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
8817 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
8818 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
8819 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8820 // CHECK6-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
8821 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
8822 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
8823 // CHECK6-NEXT:    ret void
8824 //
8825 //
8826 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3
8827 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
8828 // CHECK6-NEXT:  entry:
8829 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8830 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8831 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8832 // CHECK6-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
8833 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8834 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
8835 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i64, align 8
8836 // CHECK6-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
8837 // CHECK6-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
8838 // CHECK6-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
8839 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
8840 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
8841 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
8842 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8843 // CHECK6-NEXT:    [[IT:%.*]] = alloca i64, align 8
8844 // CHECK6-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
8845 // CHECK6-NEXT:    [[A5:%.*]] = alloca i32, align 4
8846 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8847 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8848 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8849 // CHECK6-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
8850 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8851 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8852 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
8853 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8854 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
8855 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
8856 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
8857 // CHECK6-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
8858 // CHECK6-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
8859 // CHECK6-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
8860 // CHECK6-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
8861 // CHECK6-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
8862 // CHECK6-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
8863 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8864 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8865 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
8866 // CHECK6-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
8867 // CHECK6-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
8868 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8869 // CHECK6-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
8870 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8871 // CHECK6:       cond.true:
8872 // CHECK6-NEXT:    br label [[COND_END:%.*]]
8873 // CHECK6:       cond.false:
8874 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
8875 // CHECK6-NEXT:    br label [[COND_END]]
8876 // CHECK6:       cond.end:
8877 // CHECK6-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
8878 // CHECK6-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
8879 // CHECK6-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
8880 // CHECK6-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
8881 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8882 // CHECK6:       omp.inner.for.cond:
8883 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
8884 // CHECK6-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
8885 // CHECK6-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
8886 // CHECK6-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8887 // CHECK6:       omp.inner.for.body:
8888 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
8889 // CHECK6-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
8890 // CHECK6-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
8891 // CHECK6-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !29
8892 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !29
8893 // CHECK6-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
8894 // CHECK6-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
8895 // CHECK6-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
8896 // CHECK6-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
8897 // CHECK6-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
8898 // CHECK6-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
8899 // CHECK6-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !29
8900 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29
8901 // CHECK6-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
8902 // CHECK6-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
8903 // CHECK6-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29
8904 // CHECK6-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
8905 // CHECK6-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
8906 // CHECK6-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
8907 // CHECK6-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29
8908 // CHECK6-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !29
8909 // CHECK6-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
8910 // CHECK6-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
8911 // CHECK6-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
8912 // CHECK6-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !29
8913 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8914 // CHECK6:       omp.body.continue:
8915 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8916 // CHECK6:       omp.inner.for.inc:
8917 // CHECK6-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
8918 // CHECK6-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
8919 // CHECK6-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
8920 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
8921 // CHECK6:       omp.inner.for.end:
8922 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8923 // CHECK6:       omp.loop.exit:
8924 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
8925 // CHECK6-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8926 // CHECK6-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
8927 // CHECK6-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
8928 // CHECK6:       .omp.final.then:
8929 // CHECK6-NEXT:    store i64 400, i64* [[IT]], align 8
8930 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
8931 // CHECK6:       .omp.final.done:
8932 // CHECK6-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8933 // CHECK6-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
8934 // CHECK6-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
8935 // CHECK6:       .omp.linear.pu:
8936 // CHECK6-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
8937 // CHECK6-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
8938 // CHECK6-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
8939 // CHECK6-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP23]]
8940 // CHECK6-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
8941 // CHECK6-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
8942 // CHECK6-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
8943 // CHECK6-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
8944 // CHECK6-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
8945 // CHECK6-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
8946 // CHECK6-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP25]]
8947 // CHECK6-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
8948 // CHECK6-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
8949 // CHECK6-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
8950 // CHECK6-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
8951 // CHECK6:       .omp.linear.pu.done:
8952 // CHECK6-NEXT:    ret void
8953 //
8954 //
8955 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
8956 // CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
8957 // CHECK6-NEXT:  entry:
8958 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8959 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8960 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8961 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8962 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8963 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8964 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8965 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8966 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8967 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8968 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
8969 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8970 // CHECK6-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
8971 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8972 // CHECK6-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
8973 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8974 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
8975 // CHECK6-NEXT:    ret void
8976 //
8977 //
8978 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4
8979 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] {
8980 // CHECK6-NEXT:  entry:
8981 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8982 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8983 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8984 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8985 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8986 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i16, align 2
8987 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8988 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8989 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8990 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8991 // CHECK6-NEXT:    [[IT:%.*]] = alloca i16, align 2
8992 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8993 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8994 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8995 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8996 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8997 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8998 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8999 // CHECK6-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
9000 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9001 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9002 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9003 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9004 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9005 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9006 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
9007 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9008 // CHECK6:       cond.true:
9009 // CHECK6-NEXT:    br label [[COND_END:%.*]]
9010 // CHECK6:       cond.false:
9011 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9012 // CHECK6-NEXT:    br label [[COND_END]]
9013 // CHECK6:       cond.end:
9014 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9015 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9016 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9017 // CHECK6-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9018 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9019 // CHECK6:       omp.inner.for.cond:
9020 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
9021 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
9022 // CHECK6-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9023 // CHECK6-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9024 // CHECK6:       omp.inner.for.body:
9025 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
9026 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
9027 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
9028 // CHECK6-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
9029 // CHECK6-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32
9030 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
9031 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
9032 // CHECK6-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !32
9033 // CHECK6-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
9034 // CHECK6-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
9035 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
9036 // CHECK6-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
9037 // CHECK6-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !32
9038 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9039 // CHECK6:       omp.body.continue:
9040 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9041 // CHECK6:       omp.inner.for.inc:
9042 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
9043 // CHECK6-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
9044 // CHECK6-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
9045 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
9046 // CHECK6:       omp.inner.for.end:
9047 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9048 // CHECK6:       omp.loop.exit:
9049 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9050 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9051 // CHECK6-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
9052 // CHECK6-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9053 // CHECK6:       .omp.final.then:
9054 // CHECK6-NEXT:    store i16 22, i16* [[IT]], align 2
9055 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9056 // CHECK6:       .omp.final.done:
9057 // CHECK6-NEXT:    ret void
9058 //
9059 //
9060 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
9061 // CHECK6-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
9062 // CHECK6-NEXT:  entry:
9063 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9064 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9065 // CHECK6-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9066 // CHECK6-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
9067 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9068 // CHECK6-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9069 // CHECK6-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9070 // CHECK6-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
9071 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9072 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9073 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9074 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
9075 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9076 // CHECK6-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9077 // CHECK6-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9078 // CHECK6-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
9079 // CHECK6-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9080 // CHECK6-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9081 // CHECK6-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9082 // CHECK6-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
9083 // CHECK6-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9084 // CHECK6-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9085 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9086 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9087 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9088 // CHECK6-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9089 // CHECK6-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9090 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9091 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9092 // CHECK6-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9093 // CHECK6-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9094 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
9095 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
9096 // CHECK6-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9097 // CHECK6-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
9098 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
9099 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
9100 // CHECK6-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
9101 // CHECK6-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
9102 // CHECK6-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
9103 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
9104 // CHECK6-NEXT:    ret void
9105 //
9106 //
9107 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7
9108 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
9109 // CHECK6-NEXT:  entry:
9110 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9111 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9112 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9113 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9114 // CHECK6-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9115 // CHECK6-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
9116 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9117 // CHECK6-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9118 // CHECK6-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9119 // CHECK6-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
9120 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9121 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9122 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9123 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i8, align 1
9124 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9125 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9126 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9127 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9128 // CHECK6-NEXT:    [[IT:%.*]] = alloca i8, align 1
9129 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9130 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9131 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9132 // CHECK6-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9133 // CHECK6-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9134 // CHECK6-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
9135 // CHECK6-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9136 // CHECK6-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9137 // CHECK6-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9138 // CHECK6-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
9139 // CHECK6-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9140 // CHECK6-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9141 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9142 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9143 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9144 // CHECK6-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9145 // CHECK6-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9146 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9147 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9148 // CHECK6-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9149 // CHECK6-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9150 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
9151 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9152 // CHECK6-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
9153 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9154 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9155 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
9156 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9157 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
9158 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
9159 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
9160 // CHECK6:       omp.dispatch.cond:
9161 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9162 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
9163 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9164 // CHECK6:       cond.true:
9165 // CHECK6-NEXT:    br label [[COND_END:%.*]]
9166 // CHECK6:       cond.false:
9167 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9168 // CHECK6-NEXT:    br label [[COND_END]]
9169 // CHECK6:       cond.end:
9170 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
9171 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9172 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9173 // CHECK6-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
9174 // CHECK6-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9175 // CHECK6-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9176 // CHECK6-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
9177 // CHECK6-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
9178 // CHECK6:       omp.dispatch.body:
9179 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9180 // CHECK6:       omp.inner.for.cond:
9181 // CHECK6-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
9182 // CHECK6-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
9183 // CHECK6-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
9184 // CHECK6-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9185 // CHECK6:       omp.inner.for.body:
9186 // CHECK6-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
9187 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
9188 // CHECK6-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
9189 // CHECK6-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
9190 // CHECK6-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35
9191 // CHECK6-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !35
9192 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
9193 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !35
9194 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
9195 // CHECK6-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
9196 // CHECK6-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
9197 // CHECK6-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
9198 // CHECK6-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
9199 // CHECK6-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
9200 // CHECK6-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
9201 // CHECK6-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
9202 // CHECK6-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
9203 // CHECK6-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
9204 // CHECK6-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
9205 // CHECK6-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !35
9206 // CHECK6-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
9207 // CHECK6-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
9208 // CHECK6-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
9209 // CHECK6-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
9210 // CHECK6-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !35
9211 // CHECK6-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
9212 // CHECK6-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
9213 // CHECK6-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
9214 // CHECK6-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
9215 // CHECK6-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
9216 // CHECK6-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !35
9217 // CHECK6-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
9218 // CHECK6-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
9219 // CHECK6-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
9220 // CHECK6-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !35
9221 // CHECK6-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
9222 // CHECK6-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
9223 // CHECK6-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
9224 // CHECK6-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
9225 // CHECK6-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
9226 // CHECK6-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !35
9227 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9228 // CHECK6:       omp.body.continue:
9229 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9230 // CHECK6:       omp.inner.for.inc:
9231 // CHECK6-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
9232 // CHECK6-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
9233 // CHECK6-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
9234 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
9235 // CHECK6:       omp.inner.for.end:
9236 // CHECK6-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
9237 // CHECK6:       omp.dispatch.inc:
9238 // CHECK6-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9239 // CHECK6-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
9240 // CHECK6-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
9241 // CHECK6-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
9242 // CHECK6-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9243 // CHECK6-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
9244 // CHECK6-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
9245 // CHECK6-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
9246 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND]]
9247 // CHECK6:       omp.dispatch.end:
9248 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
9249 // CHECK6-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9250 // CHECK6-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
9251 // CHECK6-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9252 // CHECK6:       .omp.final.then:
9253 // CHECK6-NEXT:    store i8 96, i8* [[IT]], align 1
9254 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9255 // CHECK6:       .omp.final.done:
9256 // CHECK6-NEXT:    ret void
9257 //
9258 //
9259 // CHECK6-LABEL: define {{[^@]+}}@_Z3bari
9260 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
9261 // CHECK6-NEXT:  entry:
9262 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9263 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
9264 // CHECK6-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
9265 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9266 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
9267 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9268 // CHECK6-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
9269 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
9270 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
9271 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
9272 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
9273 // CHECK6-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
9274 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
9275 // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
9276 // CHECK6-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
9277 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
9278 // CHECK6-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
9279 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
9280 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
9281 // CHECK6-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
9282 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
9283 // CHECK6-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
9284 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
9285 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
9286 // CHECK6-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
9287 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
9288 // CHECK6-NEXT:    ret i32 [[TMP8]]
9289 //
9290 //
9291 // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
9292 // CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
9293 // CHECK6-NEXT:  entry:
9294 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9295 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9296 // CHECK6-NEXT:    [[B:%.*]] = alloca i32, align 4
9297 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
9298 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
9299 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
9300 // CHECK6-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
9301 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
9302 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 8
9303 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 8
9304 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 8
9305 // CHECK6-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8
9306 // CHECK6-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9307 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9308 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9309 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9310 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
9311 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
9312 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
9313 // CHECK6-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
9314 // CHECK6-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
9315 // CHECK6-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
9316 // CHECK6-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
9317 // CHECK6-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
9318 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
9319 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
9320 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
9321 // CHECK6-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
9322 // CHECK6-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
9323 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
9324 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
9325 // CHECK6-NEXT:    store i32 [[TMP6]], i32* [[CONV]], align 4
9326 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, i64* [[B_CASTED]], align 8
9327 // CHECK6-NEXT:    [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9328 // CHECK6-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
9329 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
9330 // CHECK6-NEXT:    [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
9331 // CHECK6-NEXT:    store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
9332 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
9333 // CHECK6-NEXT:    [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9334 // CHECK6-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP10]] to i1
9335 // CHECK6-NEXT:    br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9336 // CHECK6:       omp_if.then:
9337 // CHECK6-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
9338 // CHECK6-NEXT:    [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]]
9339 // CHECK6-NEXT:    [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2
9340 // CHECK6-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9341 // CHECK6-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to %struct.S1**
9342 // CHECK6-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP14]], align 8
9343 // CHECK6-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9344 // CHECK6-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double**
9345 // CHECK6-NEXT:    store double* [[A]], double** [[TMP16]], align 8
9346 // CHECK6-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
9347 // CHECK6-NEXT:    store i64 8, i64* [[TMP17]], align 8
9348 // CHECK6-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
9349 // CHECK6-NEXT:    store i8* null, i8** [[TMP18]], align 8
9350 // CHECK6-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
9351 // CHECK6-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
9352 // CHECK6-NEXT:    store i64 [[TMP7]], i64* [[TMP20]], align 8
9353 // CHECK6-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
9354 // CHECK6-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
9355 // CHECK6-NEXT:    store i64 [[TMP7]], i64* [[TMP22]], align 8
9356 // CHECK6-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
9357 // CHECK6-NEXT:    store i64 4, i64* [[TMP23]], align 8
9358 // CHECK6-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
9359 // CHECK6-NEXT:    store i8* null, i8** [[TMP24]], align 8
9360 // CHECK6-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
9361 // CHECK6-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
9362 // CHECK6-NEXT:    store i64 2, i64* [[TMP26]], align 8
9363 // CHECK6-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
9364 // CHECK6-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
9365 // CHECK6-NEXT:    store i64 2, i64* [[TMP28]], align 8
9366 // CHECK6-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
9367 // CHECK6-NEXT:    store i64 8, i64* [[TMP29]], align 8
9368 // CHECK6-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
9369 // CHECK6-NEXT:    store i8* null, i8** [[TMP30]], align 8
9370 // CHECK6-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
9371 // CHECK6-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
9372 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[TMP32]], align 8
9373 // CHECK6-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
9374 // CHECK6-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64*
9375 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[TMP34]], align 8
9376 // CHECK6-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
9377 // CHECK6-NEXT:    store i64 8, i64* [[TMP35]], align 8
9378 // CHECK6-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
9379 // CHECK6-NEXT:    store i8* null, i8** [[TMP36]], align 8
9380 // CHECK6-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
9381 // CHECK6-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i16**
9382 // CHECK6-NEXT:    store i16* [[VLA]], i16** [[TMP38]], align 8
9383 // CHECK6-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
9384 // CHECK6-NEXT:    [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i16**
9385 // CHECK6-NEXT:    store i16* [[VLA]], i16** [[TMP40]], align 8
9386 // CHECK6-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
9387 // CHECK6-NEXT:    store i64 [[TMP12]], i64* [[TMP41]], align 8
9388 // CHECK6-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
9389 // CHECK6-NEXT:    store i8* null, i8** [[TMP42]], align 8
9390 // CHECK6-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
9391 // CHECK6-NEXT:    [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64*
9392 // CHECK6-NEXT:    store i64 [[TMP9]], i64* [[TMP44]], align 8
9393 // CHECK6-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
9394 // CHECK6-NEXT:    [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64*
9395 // CHECK6-NEXT:    store i64 [[TMP9]], i64* [[TMP46]], align 8
9396 // CHECK6-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
9397 // CHECK6-NEXT:    store i64 1, i64* [[TMP47]], align 8
9398 // CHECK6-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
9399 // CHECK6-NEXT:    store i8* null, i8** [[TMP48]], align 8
9400 // CHECK6-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9401 // CHECK6-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9402 // CHECK6-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
9403 // CHECK6-NEXT:    [[TMP52:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9404 // CHECK6-NEXT:    [[TOBOOL5:%.*]] = trunc i8 [[TMP52]] to i1
9405 // CHECK6-NEXT:    [[TMP53:%.*]] = select i1 [[TOBOOL5]], i32 0, i32 1
9406 // CHECK6-NEXT:    [[TMP54:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, i32 6, i8** [[TMP49]], i8** [[TMP50]], i64* [[TMP51]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP53]])
9407 // CHECK6-NEXT:    [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0
9408 // CHECK6-NEXT:    br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
9409 // CHECK6:       omp_offload.failed:
9410 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
9411 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT]]
9412 // CHECK6:       omp_offload.cont:
9413 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
9414 // CHECK6:       omp_if.else:
9415 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
9416 // CHECK6-NEXT:    br label [[OMP_IF_END]]
9417 // CHECK6:       omp_if.end:
9418 // CHECK6-NEXT:    [[TMP56:%.*]] = mul nsw i64 1, [[TMP2]]
9419 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP56]]
9420 // CHECK6-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
9421 // CHECK6-NEXT:    [[TMP57:%.*]] = load i16, i16* [[ARRAYIDX6]], align 2
9422 // CHECK6-NEXT:    [[CONV7:%.*]] = sext i16 [[TMP57]] to i32
9423 // CHECK6-NEXT:    [[TMP58:%.*]] = load i32, i32* [[B]], align 4
9424 // CHECK6-NEXT:    [[ADD8:%.*]] = add nsw i32 [[CONV7]], [[TMP58]]
9425 // CHECK6-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
9426 // CHECK6-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
9427 // CHECK6-NEXT:    ret i32 [[ADD8]]
9428 //
9429 //
9430 // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici
9431 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
9432 // CHECK6-NEXT:  entry:
9433 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9434 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
9435 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
9436 // CHECK6-NEXT:    [[AAA:%.*]] = alloca i8, align 1
9437 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9438 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9439 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9440 // CHECK6-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
9441 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
9442 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
9443 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
9444 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9445 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
9446 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
9447 // CHECK6-NEXT:    store i8 0, i8* [[AAA]], align 1
9448 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
9449 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9450 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
9451 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9452 // CHECK6-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
9453 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9454 // CHECK6-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
9455 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9456 // CHECK6-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
9457 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
9458 // CHECK6-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
9459 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
9460 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
9461 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
9462 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9463 // CHECK6:       omp_if.then:
9464 // CHECK6-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9465 // CHECK6-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
9466 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
9467 // CHECK6-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9468 // CHECK6-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
9469 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
9470 // CHECK6-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
9471 // CHECK6-NEXT:    store i8* null, i8** [[TMP11]], align 8
9472 // CHECK6-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
9473 // CHECK6-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
9474 // CHECK6-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
9475 // CHECK6-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
9476 // CHECK6-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
9477 // CHECK6-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
9478 // CHECK6-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
9479 // CHECK6-NEXT:    store i8* null, i8** [[TMP16]], align 8
9480 // CHECK6-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
9481 // CHECK6-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
9482 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
9483 // CHECK6-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
9484 // CHECK6-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
9485 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
9486 // CHECK6-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
9487 // CHECK6-NEXT:    store i8* null, i8** [[TMP21]], align 8
9488 // CHECK6-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
9489 // CHECK6-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
9490 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
9491 // CHECK6-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
9492 // CHECK6-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
9493 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
9494 // CHECK6-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
9495 // CHECK6-NEXT:    store i8* null, i8** [[TMP26]], align 8
9496 // CHECK6-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9497 // CHECK6-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9498 // CHECK6-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
9499 // CHECK6-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
9500 // CHECK6-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
9501 // CHECK6:       omp_offload.failed:
9502 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
9503 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT]]
9504 // CHECK6:       omp_offload.cont:
9505 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
9506 // CHECK6:       omp_if.else:
9507 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
9508 // CHECK6-NEXT:    br label [[OMP_IF_END]]
9509 // CHECK6:       omp_if.end:
9510 // CHECK6-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
9511 // CHECK6-NEXT:    ret i32 [[TMP31]]
9512 //
9513 //
9514 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
9515 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
9516 // CHECK6-NEXT:  entry:
9517 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9518 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
9519 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
9520 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9521 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9522 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9523 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
9524 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
9525 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
9526 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9527 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
9528 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
9529 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
9530 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9531 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
9532 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9533 // CHECK6-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
9534 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9535 // CHECK6-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
9536 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9537 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
9538 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
9539 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9540 // CHECK6:       omp_if.then:
9541 // CHECK6-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9542 // CHECK6-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
9543 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
9544 // CHECK6-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9545 // CHECK6-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
9546 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
9547 // CHECK6-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
9548 // CHECK6-NEXT:    store i8* null, i8** [[TMP9]], align 8
9549 // CHECK6-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
9550 // CHECK6-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
9551 // CHECK6-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
9552 // CHECK6-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
9553 // CHECK6-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
9554 // CHECK6-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
9555 // CHECK6-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
9556 // CHECK6-NEXT:    store i8* null, i8** [[TMP14]], align 8
9557 // CHECK6-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
9558 // CHECK6-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
9559 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
9560 // CHECK6-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
9561 // CHECK6-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
9562 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
9563 // CHECK6-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
9564 // CHECK6-NEXT:    store i8* null, i8** [[TMP19]], align 8
9565 // CHECK6-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9566 // CHECK6-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9567 // CHECK6-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
9568 // CHECK6-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
9569 // CHECK6-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
9570 // CHECK6:       omp_offload.failed:
9571 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
9572 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT]]
9573 // CHECK6:       omp_offload.cont:
9574 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
9575 // CHECK6:       omp_if.else:
9576 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
9577 // CHECK6-NEXT:    br label [[OMP_IF_END]]
9578 // CHECK6:       omp_if.end:
9579 // CHECK6-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
9580 // CHECK6-NEXT:    ret i32 [[TMP24]]
9581 //
9582 //
9583 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
9584 // CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
9585 // CHECK6-NEXT:  entry:
9586 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9587 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
9588 // CHECK6-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9589 // CHECK6-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9590 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
9591 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9592 // CHECK6-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
9593 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
9594 // CHECK6-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
9595 // CHECK6-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
9596 // CHECK6-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
9597 // CHECK6-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
9598 // CHECK6-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9599 // CHECK6-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
9600 // CHECK6-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9601 // CHECK6-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9602 // CHECK6-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
9603 // CHECK6-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9604 // CHECK6-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9605 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9606 // CHECK6-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9607 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9608 // CHECK6-NEXT:    [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9609 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
9610 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
9611 // CHECK6-NEXT:    [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
9612 // CHECK6-NEXT:    store i32 [[TMP5]], i32* [[CONV4]], align 4
9613 // CHECK6-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
9614 // CHECK6-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
9615 // CHECK6-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
9616 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
9617 // CHECK6-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
9618 // CHECK6-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
9619 // CHECK6-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
9620 // CHECK6-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
9621 // CHECK6-NEXT:    [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
9622 // CHECK6-NEXT:    br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9623 // CHECK6:       omp_if.then:
9624 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
9625 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
9626 // CHECK6:       omp_if.else:
9627 // CHECK6-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
9628 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
9629 // CHECK6-NEXT:    call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR4]]
9630 // CHECK6-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
9631 // CHECK6-NEXT:    br label [[OMP_IF_END]]
9632 // CHECK6:       omp_if.end:
9633 // CHECK6-NEXT:    ret void
9634 //
9635 //
9636 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9
9637 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
9638 // CHECK6-NEXT:  entry:
9639 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9640 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9641 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9642 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
9643 // CHECK6-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9644 // CHECK6-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9645 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
9646 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9647 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
9648 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i64, align 8
9649 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
9650 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
9651 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
9652 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9653 // CHECK6-NEXT:    [[IT:%.*]] = alloca i64, align 8
9654 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9655 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9656 // CHECK6-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9657 // CHECK6-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
9658 // CHECK6-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9659 // CHECK6-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9660 // CHECK6-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
9661 // CHECK6-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9662 // CHECK6-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9663 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9664 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9665 // CHECK6-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9666 // CHECK6-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9667 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
9668 // CHECK6-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
9669 // CHECK6-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
9670 // CHECK6-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
9671 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9672 // CHECK6-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
9673 // CHECK6-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
9674 // CHECK6-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9675 // CHECK6:       omp_if.then:
9676 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9677 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
9678 // CHECK6-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
9679 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9680 // CHECK6-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
9681 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9682 // CHECK6:       cond.true:
9683 // CHECK6-NEXT:    br label [[COND_END:%.*]]
9684 // CHECK6:       cond.false:
9685 // CHECK6-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9686 // CHECK6-NEXT:    br label [[COND_END]]
9687 // CHECK6:       cond.end:
9688 // CHECK6-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
9689 // CHECK6-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
9690 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
9691 // CHECK6-NEXT:    store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
9692 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9693 // CHECK6:       omp.inner.for.cond:
9694 // CHECK6-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
9695 // CHECK6-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38
9696 // CHECK6-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
9697 // CHECK6-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9698 // CHECK6:       omp.inner.for.body:
9699 // CHECK6-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
9700 // CHECK6-NEXT:    [[MUL:%.*]] = mul i64 [[TMP12]], 400
9701 // CHECK6-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
9702 // CHECK6-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38
9703 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !38
9704 // CHECK6-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
9705 // CHECK6-NEXT:    [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
9706 // CHECK6-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
9707 // CHECK6-NEXT:    store double [[ADD]], double* [[A]], align 8, !nontemporal !39, !llvm.access.group !38
9708 // CHECK6-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
9709 // CHECK6-NEXT:    [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
9710 // CHECK6-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
9711 // CHECK6-NEXT:    store double [[INC]], double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38
9712 // CHECK6-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
9713 // CHECK6-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
9714 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
9715 // CHECK6-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
9716 // CHECK6-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !38
9717 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9718 // CHECK6:       omp.body.continue:
9719 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9720 // CHECK6:       omp.inner.for.inc:
9721 // CHECK6-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
9722 // CHECK6-NEXT:    [[ADD9:%.*]] = add i64 [[TMP16]], 1
9723 // CHECK6-NEXT:    store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38
9724 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
9725 // CHECK6:       omp.inner.for.end:
9726 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
9727 // CHECK6:       omp_if.else:
9728 // CHECK6-NEXT:    [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9729 // CHECK6-NEXT:    [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
9730 // CHECK6-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
9731 // CHECK6-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9732 // CHECK6-NEXT:    [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3
9733 // CHECK6-NEXT:    br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
9734 // CHECK6:       cond.true11:
9735 // CHECK6-NEXT:    br label [[COND_END13:%.*]]
9736 // CHECK6:       cond.false12:
9737 // CHECK6-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9738 // CHECK6-NEXT:    br label [[COND_END13]]
9739 // CHECK6:       cond.end13:
9740 // CHECK6-NEXT:    [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ]
9741 // CHECK6-NEXT:    store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8
9742 // CHECK6-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
9743 // CHECK6-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
9744 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND15:%.*]]
9745 // CHECK6:       omp.inner.for.cond15:
9746 // CHECK6-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9747 // CHECK6-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9748 // CHECK6-NEXT:    [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
9749 // CHECK6-NEXT:    br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
9750 // CHECK6:       omp.inner.for.body17:
9751 // CHECK6-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9752 // CHECK6-NEXT:    [[MUL18:%.*]] = mul i64 [[TMP24]], 400
9753 // CHECK6-NEXT:    [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
9754 // CHECK6-NEXT:    store i64 [[SUB19]], i64* [[IT]], align 8
9755 // CHECK6-NEXT:    [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
9756 // CHECK6-NEXT:    [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
9757 // CHECK6-NEXT:    [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
9758 // CHECK6-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
9759 // CHECK6-NEXT:    store double [[ADD21]], double* [[A22]], align 8
9760 // CHECK6-NEXT:    [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
9761 // CHECK6-NEXT:    [[TMP26:%.*]] = load double, double* [[A23]], align 8
9762 // CHECK6-NEXT:    [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
9763 // CHECK6-NEXT:    store double [[INC24]], double* [[A23]], align 8
9764 // CHECK6-NEXT:    [[CONV25:%.*]] = fptosi double [[INC24]] to i16
9765 // CHECK6-NEXT:    [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]]
9766 // CHECK6-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]]
9767 // CHECK6-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
9768 // CHECK6-NEXT:    store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2
9769 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE28:%.*]]
9770 // CHECK6:       omp.body.continue28:
9771 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC29:%.*]]
9772 // CHECK6:       omp.inner.for.inc29:
9773 // CHECK6-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
9774 // CHECK6-NEXT:    [[ADD30:%.*]] = add i64 [[TMP28]], 1
9775 // CHECK6-NEXT:    store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8
9776 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP42:![0-9]+]]
9777 // CHECK6:       omp.inner.for.end31:
9778 // CHECK6-NEXT:    br label [[OMP_IF_END]]
9779 // CHECK6:       omp_if.end:
9780 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9781 // CHECK6:       omp.loop.exit:
9782 // CHECK6-NEXT:    [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9783 // CHECK6-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
9784 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
9785 // CHECK6-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9786 // CHECK6-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
9787 // CHECK6-NEXT:    br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9788 // CHECK6:       .omp.final.then:
9789 // CHECK6-NEXT:    store i64 400, i64* [[IT]], align 8
9790 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9791 // CHECK6:       .omp.final.done:
9792 // CHECK6-NEXT:    ret void
9793 //
9794 //
9795 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
9796 // CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
9797 // CHECK6-NEXT:  entry:
9798 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9799 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9800 // CHECK6-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
9801 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9802 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9803 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9804 // CHECK6-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
9805 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9806 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9807 // CHECK6-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9808 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9809 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9810 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9811 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9812 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9813 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9814 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9815 // CHECK6-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
9816 // CHECK6-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
9817 // CHECK6-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
9818 // CHECK6-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9819 // CHECK6-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
9820 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9821 // CHECK6-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
9822 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
9823 // CHECK6-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
9824 // CHECK6-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
9825 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
9826 // CHECK6-NEXT:    ret void
9827 //
9828 //
9829 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11
9830 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
9831 // CHECK6-NEXT:  entry:
9832 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9833 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9834 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9835 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9836 // CHECK6-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
9837 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9838 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9839 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9840 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9841 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9842 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9843 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9844 // CHECK6-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9845 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9846 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9847 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9848 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9849 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9850 // CHECK6-NEXT:    ret void
9851 //
9852 //
9853 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
9854 // CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
9855 // CHECK6-NEXT:  entry:
9856 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9857 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9858 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9859 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9860 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9861 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9862 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9863 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9864 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9865 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9866 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9867 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9868 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9869 // CHECK6-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
9870 // CHECK6-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
9871 // CHECK6-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
9872 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9873 // CHECK6-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
9874 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9875 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
9876 // CHECK6-NEXT:    ret void
9877 //
9878 //
9879 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14
9880 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
9881 // CHECK6-NEXT:  entry:
9882 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9883 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9884 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9885 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9886 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9887 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
9888 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i64, align 8
9889 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
9890 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
9891 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
9892 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9893 // CHECK6-NEXT:    [[I:%.*]] = alloca i64, align 8
9894 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9895 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9896 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9897 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9898 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9899 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9900 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9901 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9902 // CHECK6-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
9903 // CHECK6-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
9904 // CHECK6-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
9905 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9906 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9907 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
9908 // CHECK6-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
9909 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9910 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
9911 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9912 // CHECK6:       cond.true:
9913 // CHECK6-NEXT:    br label [[COND_END:%.*]]
9914 // CHECK6:       cond.false:
9915 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
9916 // CHECK6-NEXT:    br label [[COND_END]]
9917 // CHECK6:       cond.end:
9918 // CHECK6-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
9919 // CHECK6-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
9920 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
9921 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
9922 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9923 // CHECK6:       omp.inner.for.cond:
9924 // CHECK6-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
9925 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !44
9926 // CHECK6-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
9927 // CHECK6-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9928 // CHECK6:       omp.inner.for.body:
9929 // CHECK6-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
9930 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
9931 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
9932 // CHECK6-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44
9933 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !44
9934 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
9935 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !44
9936 // CHECK6-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !44
9937 // CHECK6-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
9938 // CHECK6-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
9939 // CHECK6-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
9940 // CHECK6-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !44
9941 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
9942 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
9943 // CHECK6-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
9944 // CHECK6-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
9945 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9946 // CHECK6:       omp.body.continue:
9947 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9948 // CHECK6:       omp.inner.for.inc:
9949 // CHECK6-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
9950 // CHECK6-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
9951 // CHECK6-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44
9952 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
9953 // CHECK6:       omp.inner.for.end:
9954 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9955 // CHECK6:       omp.loop.exit:
9956 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
9957 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9958 // CHECK6-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
9959 // CHECK6-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9960 // CHECK6:       .omp.final.then:
9961 // CHECK6-NEXT:    store i64 11, i64* [[I]], align 8
9962 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9963 // CHECK6:       .omp.final.done:
9964 // CHECK6-NEXT:    ret void
9965 //
9966 //
9967 // CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
9968 // CHECK6-SAME: () #[[ATTR7:[0-9]+]] {
9969 // CHECK6-NEXT:  entry:
9970 // CHECK6-NEXT:    call void @__tgt_register_requires(i64 1)
9971 // CHECK6-NEXT:    ret void
9972 //
9973 //
9974 // CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv
9975 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
9976 // CHECK7-NEXT:  entry:
9977 // CHECK7-NEXT:    ret i64 0
9978 //
9979 //
9980 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi
9981 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
9982 // CHECK7-NEXT:  entry:
9983 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9984 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
9985 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
9986 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
9987 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
9988 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
9989 // CHECK7-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
9990 // CHECK7-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
9991 // CHECK7-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
9992 // CHECK7-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
9993 // CHECK7-NEXT:    [[K:%.*]] = alloca i64, align 8
9994 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
9995 // CHECK7-NEXT:    [[LIN:%.*]] = alloca i32, align 4
9996 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
9997 // CHECK7-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
9998 // CHECK7-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
9999 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
10000 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
10001 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
10002 // CHECK7-NEXT:    [[A_CASTED3:%.*]] = alloca i32, align 4
10003 // CHECK7-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
10004 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
10005 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
10006 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
10007 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
10008 // CHECK7-NEXT:    [[A_CASTED11:%.*]] = alloca i32, align 4
10009 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
10010 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
10011 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
10012 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
10013 // CHECK7-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
10014 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
10015 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10016 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
10017 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
10018 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
10019 // CHECK7-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
10020 // CHECK7-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
10021 // CHECK7-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
10022 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
10023 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
10024 // CHECK7-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
10025 // CHECK7-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
10026 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
10027 // CHECK7-NEXT:    [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
10028 // CHECK7-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
10029 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
10030 // CHECK7-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]])
10031 // CHECK7-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
10032 // CHECK7-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
10033 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
10034 // CHECK7-NEXT:    store i32 [[TMP9]], i32* [[A_CASTED]], align 4
10035 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
10036 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]]
10037 // CHECK7-NEXT:    store i32 12, i32* [[LIN]], align 4
10038 // CHECK7-NEXT:    [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
10039 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10040 // CHECK7-NEXT:    store i16 [[TMP11]], i16* [[CONV]], align 2
10041 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10042 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4
10043 // CHECK7-NEXT:    store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4
10044 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
10045 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
10046 // CHECK7-NEXT:    store i32 [[TMP15]], i32* [[A_CASTED2]], align 4
10047 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4
10048 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10049 // CHECK7-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
10050 // CHECK7-NEXT:    store i32 [[TMP12]], i32* [[TMP18]], align 4
10051 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10052 // CHECK7-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
10053 // CHECK7-NEXT:    store i32 [[TMP12]], i32* [[TMP20]], align 4
10054 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
10055 // CHECK7-NEXT:    store i8* null, i8** [[TMP21]], align 4
10056 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10057 // CHECK7-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
10058 // CHECK7-NEXT:    store i32 [[TMP14]], i32* [[TMP23]], align 4
10059 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10060 // CHECK7-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
10061 // CHECK7-NEXT:    store i32 [[TMP14]], i32* [[TMP25]], align 4
10062 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
10063 // CHECK7-NEXT:    store i8* null, i8** [[TMP26]], align 4
10064 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10065 // CHECK7-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
10066 // CHECK7-NEXT:    store i32 [[TMP16]], i32* [[TMP28]], align 4
10067 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10068 // CHECK7-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
10069 // CHECK7-NEXT:    store i32 [[TMP16]], i32* [[TMP30]], align 4
10070 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
10071 // CHECK7-NEXT:    store i8* null, i8** [[TMP31]], align 4
10072 // CHECK7-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10073 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10074 // CHECK7-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
10075 // CHECK7-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
10076 // CHECK7-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10077 // CHECK7:       omp_offload.failed:
10078 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]]
10079 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
10080 // CHECK7:       omp_offload.cont:
10081 // CHECK7-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
10082 // CHECK7-NEXT:    store i32 [[TMP36]], i32* [[A_CASTED3]], align 4
10083 // CHECK7-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A_CASTED3]], align 4
10084 // CHECK7-NEXT:    [[TMP38:%.*]] = load i16, i16* [[AA]], align 2
10085 // CHECK7-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
10086 // CHECK7-NEXT:    store i16 [[TMP38]], i16* [[CONV5]], align 2
10087 // CHECK7-NEXT:    [[TMP39:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
10088 // CHECK7-NEXT:    [[TMP40:%.*]] = load i32, i32* [[N_ADDR]], align 4
10089 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP40]], 10
10090 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10091 // CHECK7:       omp_if.then:
10092 // CHECK7-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
10093 // CHECK7-NEXT:    [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
10094 // CHECK7-NEXT:    store i32 [[TMP37]], i32* [[TMP42]], align 4
10095 // CHECK7-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
10096 // CHECK7-NEXT:    [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
10097 // CHECK7-NEXT:    store i32 [[TMP37]], i32* [[TMP44]], align 4
10098 // CHECK7-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
10099 // CHECK7-NEXT:    store i8* null, i8** [[TMP45]], align 4
10100 // CHECK7-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
10101 // CHECK7-NEXT:    [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
10102 // CHECK7-NEXT:    store i32 [[TMP39]], i32* [[TMP47]], align 4
10103 // CHECK7-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
10104 // CHECK7-NEXT:    [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32*
10105 // CHECK7-NEXT:    store i32 [[TMP39]], i32* [[TMP49]], align 4
10106 // CHECK7-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
10107 // CHECK7-NEXT:    store i8* null, i8** [[TMP50]], align 4
10108 // CHECK7-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
10109 // CHECK7-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
10110 // CHECK7-NEXT:    [[TMP53:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP51]], i8** [[TMP52]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
10111 // CHECK7-NEXT:    [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
10112 // CHECK7-NEXT:    br i1 [[TMP54]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
10113 // CHECK7:       omp_offload.failed9:
10114 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
10115 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
10116 // CHECK7:       omp_offload.cont10:
10117 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
10118 // CHECK7:       omp_if.else:
10119 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
10120 // CHECK7-NEXT:    br label [[OMP_IF_END]]
10121 // CHECK7:       omp_if.end:
10122 // CHECK7-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
10123 // CHECK7-NEXT:    store i32 [[TMP55]], i32* [[DOTCAPTURE_EXPR_]], align 4
10124 // CHECK7-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A]], align 4
10125 // CHECK7-NEXT:    store i32 [[TMP56]], i32* [[A_CASTED11]], align 4
10126 // CHECK7-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A_CASTED11]], align 4
10127 // CHECK7-NEXT:    [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10128 // CHECK7-NEXT:    store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10129 // CHECK7-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10130 // CHECK7-NEXT:    [[TMP60:%.*]] = load i32, i32* [[N_ADDR]], align 4
10131 // CHECK7-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP60]], 20
10132 // CHECK7-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
10133 // CHECK7:       omp_if.then13:
10134 // CHECK7-NEXT:    [[TMP61:%.*]] = mul nuw i32 [[TMP1]], 4
10135 // CHECK7-NEXT:    [[TMP62:%.*]] = sext i32 [[TMP61]] to i64
10136 // CHECK7-NEXT:    [[TMP63:%.*]] = mul nuw i32 5, [[TMP3]]
10137 // CHECK7-NEXT:    [[TMP64:%.*]] = mul nuw i32 [[TMP63]], 8
10138 // CHECK7-NEXT:    [[TMP65:%.*]] = sext i32 [[TMP64]] to i64
10139 // CHECK7-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
10140 // CHECK7-NEXT:    [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32*
10141 // CHECK7-NEXT:    store i32 [[TMP57]], i32* [[TMP67]], align 4
10142 // CHECK7-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
10143 // CHECK7-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
10144 // CHECK7-NEXT:    store i32 [[TMP57]], i32* [[TMP69]], align 4
10145 // CHECK7-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10146 // CHECK7-NEXT:    store i64 4, i64* [[TMP70]], align 4
10147 // CHECK7-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
10148 // CHECK7-NEXT:    store i8* null, i8** [[TMP71]], align 4
10149 // CHECK7-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
10150 // CHECK7-NEXT:    [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [10 x float]**
10151 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP73]], align 4
10152 // CHECK7-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
10153 // CHECK7-NEXT:    [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
10154 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 4
10155 // CHECK7-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
10156 // CHECK7-NEXT:    store i64 40, i64* [[TMP76]], align 4
10157 // CHECK7-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
10158 // CHECK7-NEXT:    store i8* null, i8** [[TMP77]], align 4
10159 // CHECK7-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
10160 // CHECK7-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
10161 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP79]], align 4
10162 // CHECK7-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
10163 // CHECK7-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
10164 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP81]], align 4
10165 // CHECK7-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
10166 // CHECK7-NEXT:    store i64 4, i64* [[TMP82]], align 4
10167 // CHECK7-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
10168 // CHECK7-NEXT:    store i8* null, i8** [[TMP83]], align 4
10169 // CHECK7-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
10170 // CHECK7-NEXT:    [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float**
10171 // CHECK7-NEXT:    store float* [[VLA]], float** [[TMP85]], align 4
10172 // CHECK7-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
10173 // CHECK7-NEXT:    [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
10174 // CHECK7-NEXT:    store float* [[VLA]], float** [[TMP87]], align 4
10175 // CHECK7-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
10176 // CHECK7-NEXT:    store i64 [[TMP62]], i64* [[TMP88]], align 4
10177 // CHECK7-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
10178 // CHECK7-NEXT:    store i8* null, i8** [[TMP89]], align 4
10179 // CHECK7-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
10180 // CHECK7-NEXT:    [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]**
10181 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 4
10182 // CHECK7-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
10183 // CHECK7-NEXT:    [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
10184 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 4
10185 // CHECK7-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
10186 // CHECK7-NEXT:    store i64 400, i64* [[TMP94]], align 4
10187 // CHECK7-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
10188 // CHECK7-NEXT:    store i8* null, i8** [[TMP95]], align 4
10189 // CHECK7-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
10190 // CHECK7-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
10191 // CHECK7-NEXT:    store i32 5, i32* [[TMP97]], align 4
10192 // CHECK7-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
10193 // CHECK7-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
10194 // CHECK7-NEXT:    store i32 5, i32* [[TMP99]], align 4
10195 // CHECK7-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
10196 // CHECK7-NEXT:    store i64 4, i64* [[TMP100]], align 4
10197 // CHECK7-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
10198 // CHECK7-NEXT:    store i8* null, i8** [[TMP101]], align 4
10199 // CHECK7-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
10200 // CHECK7-NEXT:    [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i32*
10201 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP103]], align 4
10202 // CHECK7-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
10203 // CHECK7-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i32*
10204 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP105]], align 4
10205 // CHECK7-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
10206 // CHECK7-NEXT:    store i64 4, i64* [[TMP106]], align 4
10207 // CHECK7-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
10208 // CHECK7-NEXT:    store i8* null, i8** [[TMP107]], align 4
10209 // CHECK7-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
10210 // CHECK7-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to double**
10211 // CHECK7-NEXT:    store double* [[VLA1]], double** [[TMP109]], align 4
10212 // CHECK7-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
10213 // CHECK7-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
10214 // CHECK7-NEXT:    store double* [[VLA1]], double** [[TMP111]], align 4
10215 // CHECK7-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
10216 // CHECK7-NEXT:    store i64 [[TMP65]], i64* [[TMP112]], align 4
10217 // CHECK7-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
10218 // CHECK7-NEXT:    store i8* null, i8** [[TMP113]], align 4
10219 // CHECK7-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
10220 // CHECK7-NEXT:    [[TMP115:%.*]] = bitcast i8** [[TMP114]] to %struct.TT**
10221 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP115]], align 4
10222 // CHECK7-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
10223 // CHECK7-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
10224 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 4
10225 // CHECK7-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
10226 // CHECK7-NEXT:    store i64 12, i64* [[TMP118]], align 4
10227 // CHECK7-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
10228 // CHECK7-NEXT:    store i8* null, i8** [[TMP119]], align 4
10229 // CHECK7-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
10230 // CHECK7-NEXT:    [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32*
10231 // CHECK7-NEXT:    store i32 [[TMP59]], i32* [[TMP121]], align 4
10232 // CHECK7-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
10233 // CHECK7-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
10234 // CHECK7-NEXT:    store i32 [[TMP59]], i32* [[TMP123]], align 4
10235 // CHECK7-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
10236 // CHECK7-NEXT:    store i64 4, i64* [[TMP124]], align 4
10237 // CHECK7-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
10238 // CHECK7-NEXT:    store i8* null, i8** [[TMP125]], align 4
10239 // CHECK7-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
10240 // CHECK7-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
10241 // CHECK7-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10242 // CHECK7-NEXT:    [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
10243 // CHECK7-NEXT:    [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0
10244 // CHECK7-NEXT:    br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
10245 // CHECK7:       omp_offload.failed17:
10246 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
10247 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
10248 // CHECK7:       omp_offload.cont18:
10249 // CHECK7-NEXT:    br label [[OMP_IF_END20:%.*]]
10250 // CHECK7:       omp_if.else19:
10251 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
10252 // CHECK7-NEXT:    br label [[OMP_IF_END20]]
10253 // CHECK7:       omp_if.end20:
10254 // CHECK7-NEXT:    [[TMP131:%.*]] = load i32, i32* [[A]], align 4
10255 // CHECK7-NEXT:    [[TMP132:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
10256 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP132]])
10257 // CHECK7-NEXT:    ret i32 [[TMP131]]
10258 //
10259 //
10260 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
10261 // CHECK7-SAME: () #[[ATTR2:[0-9]+]] {
10262 // CHECK7-NEXT:  entry:
10263 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
10264 // CHECK7-NEXT:    ret void
10265 //
10266 //
10267 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined.
10268 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
10269 // CHECK7-NEXT:  entry:
10270 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10271 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10272 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10273 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10274 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10275 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10276 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10277 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10278 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
10279 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10280 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10281 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10282 // CHECK7-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
10283 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10284 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10285 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10286 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10287 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10288 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10289 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
10290 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10291 // CHECK7:       cond.true:
10292 // CHECK7-NEXT:    br label [[COND_END:%.*]]
10293 // CHECK7:       cond.false:
10294 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10295 // CHECK7-NEXT:    br label [[COND_END]]
10296 // CHECK7:       cond.end:
10297 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10298 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10299 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10300 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10301 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10302 // CHECK7:       omp.inner.for.cond:
10303 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
10304 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
10305 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10306 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10307 // CHECK7:       omp.inner.for.body:
10308 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
10309 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
10310 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
10311 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
10312 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10313 // CHECK7:       omp.body.continue:
10314 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10315 // CHECK7:       omp.inner.for.inc:
10316 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
10317 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
10318 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
10319 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
10320 // CHECK7:       omp.inner.for.end:
10321 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10322 // CHECK7:       omp.loop.exit:
10323 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10324 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10325 // CHECK7-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
10326 // CHECK7-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10327 // CHECK7:       .omp.final.then:
10328 // CHECK7-NEXT:    store i32 33, i32* [[I]], align 4
10329 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10330 // CHECK7:       .omp.final.done:
10331 // CHECK7-NEXT:    ret void
10332 //
10333 //
10334 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry.
10335 // CHECK7-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
10336 // CHECK7-NEXT:  entry:
10337 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
10338 // CHECK7-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
10339 // CHECK7-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
10340 // CHECK7-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
10341 // CHECK7-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
10342 // CHECK7-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
10343 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
10344 // CHECK7-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
10345 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
10346 // CHECK7-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
10347 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
10348 // CHECK7-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
10349 // CHECK7-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
10350 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
10351 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
10352 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
10353 // CHECK7-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
10354 // CHECK7-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
10355 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
10356 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
10357 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
10358 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
10359 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
10360 // CHECK7-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26
10361 // CHECK7-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26
10362 // CHECK7-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26
10363 // CHECK7-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26
10364 // CHECK7-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
10365 // CHECK7-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
10366 // CHECK7-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
10367 // CHECK7-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
10368 // CHECK7-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
10369 // CHECK7:       omp_offload.failed.i:
10370 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
10371 // CHECK7-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
10372 // CHECK7:       .omp_outlined..1.exit:
10373 // CHECK7-NEXT:    ret i32 0
10374 //
10375 //
10376 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
10377 // CHECK7-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
10378 // CHECK7-NEXT:  entry:
10379 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10380 // CHECK7-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
10381 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10382 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10383 // CHECK7-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
10384 // CHECK7-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
10385 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10386 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
10387 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
10388 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
10389 // CHECK7-NEXT:    ret void
10390 //
10391 //
10392 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2
10393 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
10394 // CHECK7-NEXT:  entry:
10395 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10396 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10397 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10398 // CHECK7-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
10399 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10400 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10401 // CHECK7-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
10402 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10403 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10404 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10405 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10406 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
10407 // CHECK7-NEXT:    [[K1:%.*]] = alloca i64, align 8
10408 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10409 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10410 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10411 // CHECK7-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
10412 // CHECK7-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
10413 // CHECK7-NEXT:    [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
10414 // CHECK7-NEXT:    store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
10415 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10416 // CHECK7-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
10417 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10418 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10419 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10420 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
10421 // CHECK7-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
10422 // CHECK7-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
10423 // CHECK7-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
10424 // CHECK7:       omp.dispatch.cond:
10425 // CHECK7-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
10426 // CHECK7-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
10427 // CHECK7-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
10428 // CHECK7:       omp.dispatch.body:
10429 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10430 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
10431 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10432 // CHECK7:       omp.inner.for.cond:
10433 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
10434 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
10435 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
10436 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10437 // CHECK7:       omp.inner.for.body:
10438 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
10439 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
10440 // CHECK7-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
10441 // CHECK7-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !27
10442 // CHECK7-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !27
10443 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
10444 // CHECK7-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
10445 // CHECK7-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
10446 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
10447 // CHECK7-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !27
10448 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !27
10449 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
10450 // CHECK7-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !27
10451 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10452 // CHECK7:       omp.body.continue:
10453 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10454 // CHECK7:       omp.inner.for.inc:
10455 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
10456 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
10457 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
10458 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
10459 // CHECK7:       omp.inner.for.end:
10460 // CHECK7-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
10461 // CHECK7:       omp.dispatch.inc:
10462 // CHECK7-NEXT:    br label [[OMP_DISPATCH_COND]]
10463 // CHECK7:       omp.dispatch.end:
10464 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10465 // CHECK7-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
10466 // CHECK7-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10467 // CHECK7:       .omp.final.then:
10468 // CHECK7-NEXT:    store i32 1, i32* [[I]], align 4
10469 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10470 // CHECK7:       .omp.final.done:
10471 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10472 // CHECK7-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
10473 // CHECK7-NEXT:    br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
10474 // CHECK7:       .omp.linear.pu:
10475 // CHECK7-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
10476 // CHECK7-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP17]], 27
10477 // CHECK7-NEXT:    store i64 [[ADD5]], i64* [[TMP0]], align 8
10478 // CHECK7-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
10479 // CHECK7:       .omp.linear.pu.done:
10480 // CHECK7-NEXT:    ret void
10481 //
10482 //
10483 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
10484 // CHECK7-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
10485 // CHECK7-NEXT:  entry:
10486 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10487 // CHECK7-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
10488 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10489 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10490 // CHECK7-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
10491 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10492 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10493 // CHECK7-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
10494 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10495 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10496 // CHECK7-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
10497 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10498 // CHECK7-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
10499 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10500 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
10501 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
10502 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
10503 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
10504 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
10505 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
10506 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
10507 // CHECK7-NEXT:    ret void
10508 //
10509 //
10510 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3
10511 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {
10512 // CHECK7-NEXT:  entry:
10513 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10514 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10515 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10516 // CHECK7-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
10517 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10518 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
10519 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i64, align 4
10520 // CHECK7-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
10521 // CHECK7-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
10522 // CHECK7-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
10523 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
10524 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
10525 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
10526 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10527 // CHECK7-NEXT:    [[IT:%.*]] = alloca i64, align 8
10528 // CHECK7-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
10529 // CHECK7-NEXT:    [[A3:%.*]] = alloca i32, align 4
10530 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10531 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10532 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10533 // CHECK7-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
10534 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10535 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10536 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
10537 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
10538 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10539 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
10540 // CHECK7-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
10541 // CHECK7-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
10542 // CHECK7-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
10543 // CHECK7-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
10544 // CHECK7-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
10545 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10546 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10547 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
10548 // CHECK7-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
10549 // CHECK7-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
10550 // CHECK7-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10551 // CHECK7-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
10552 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10553 // CHECK7:       cond.true:
10554 // CHECK7-NEXT:    br label [[COND_END:%.*]]
10555 // CHECK7:       cond.false:
10556 // CHECK7-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
10557 // CHECK7-NEXT:    br label [[COND_END]]
10558 // CHECK7:       cond.end:
10559 // CHECK7-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
10560 // CHECK7-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
10561 // CHECK7-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
10562 // CHECK7-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
10563 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10564 // CHECK7:       omp.inner.for.cond:
10565 // CHECK7-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
10566 // CHECK7-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
10567 // CHECK7-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
10568 // CHECK7-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10569 // CHECK7:       omp.inner.for.body:
10570 // CHECK7-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
10571 // CHECK7-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
10572 // CHECK7-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
10573 // CHECK7-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !30
10574 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !30
10575 // CHECK7-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
10576 // CHECK7-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
10577 // CHECK7-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
10578 // CHECK7-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
10579 // CHECK7-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
10580 // CHECK7-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
10581 // CHECK7-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !30
10582 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
10583 // CHECK7-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
10584 // CHECK7-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
10585 // CHECK7-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
10586 // CHECK7-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
10587 // CHECK7-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
10588 // CHECK7-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
10589 // CHECK7-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
10590 // CHECK7-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
10591 // CHECK7-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
10592 // CHECK7-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
10593 // CHECK7-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
10594 // CHECK7-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
10595 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10596 // CHECK7:       omp.body.continue:
10597 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10598 // CHECK7:       omp.inner.for.inc:
10599 // CHECK7-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
10600 // CHECK7-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
10601 // CHECK7-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
10602 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
10603 // CHECK7:       omp.inner.for.end:
10604 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10605 // CHECK7:       omp.loop.exit:
10606 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
10607 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10608 // CHECK7-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
10609 // CHECK7-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10610 // CHECK7:       .omp.final.then:
10611 // CHECK7-NEXT:    store i64 400, i64* [[IT]], align 8
10612 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10613 // CHECK7:       .omp.final.done:
10614 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10615 // CHECK7-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
10616 // CHECK7-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
10617 // CHECK7:       .omp.linear.pu:
10618 // CHECK7-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
10619 // CHECK7-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
10620 // CHECK7-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
10621 // CHECK7-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP23]]
10622 // CHECK7-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
10623 // CHECK7-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
10624 // CHECK7-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
10625 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
10626 // CHECK7-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
10627 // CHECK7-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
10628 // CHECK7-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP25]]
10629 // CHECK7-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
10630 // CHECK7-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
10631 // CHECK7-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
10632 // CHECK7-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
10633 // CHECK7:       .omp.linear.pu.done:
10634 // CHECK7-NEXT:    ret void
10635 //
10636 //
10637 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
10638 // CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
10639 // CHECK7-NEXT:  entry:
10640 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10641 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10642 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10643 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10644 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10645 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10646 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10647 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
10648 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
10649 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
10650 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
10651 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10652 // CHECK7-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
10653 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10654 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
10655 // CHECK7-NEXT:    ret void
10656 //
10657 //
10658 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4
10659 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
10660 // CHECK7-NEXT:  entry:
10661 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10662 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10663 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10664 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10665 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10666 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i16, align 2
10667 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10668 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10669 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10670 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10671 // CHECK7-NEXT:    [[IT:%.*]] = alloca i16, align 2
10672 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10673 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10674 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10675 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10676 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10677 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10678 // CHECK7-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
10679 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10680 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10681 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10682 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10683 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10684 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10685 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
10686 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10687 // CHECK7:       cond.true:
10688 // CHECK7-NEXT:    br label [[COND_END:%.*]]
10689 // CHECK7:       cond.false:
10690 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10691 // CHECK7-NEXT:    br label [[COND_END]]
10692 // CHECK7:       cond.end:
10693 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10694 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10695 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10696 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10697 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10698 // CHECK7:       omp.inner.for.cond:
10699 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
10700 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
10701 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10702 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10703 // CHECK7:       omp.inner.for.body:
10704 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
10705 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
10706 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
10707 // CHECK7-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
10708 // CHECK7-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
10709 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
10710 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
10711 // CHECK7-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
10712 // CHECK7-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
10713 // CHECK7-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
10714 // CHECK7-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
10715 // CHECK7-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
10716 // CHECK7-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
10717 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10718 // CHECK7:       omp.body.continue:
10719 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10720 // CHECK7:       omp.inner.for.inc:
10721 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
10722 // CHECK7-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
10723 // CHECK7-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
10724 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
10725 // CHECK7:       omp.inner.for.end:
10726 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10727 // CHECK7:       omp.loop.exit:
10728 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10729 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10730 // CHECK7-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
10731 // CHECK7-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10732 // CHECK7:       .omp.final.then:
10733 // CHECK7-NEXT:    store i16 22, i16* [[IT]], align 2
10734 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10735 // CHECK7:       .omp.final.done:
10736 // CHECK7-NEXT:    ret void
10737 //
10738 //
10739 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
10740 // CHECK7-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
10741 // CHECK7-NEXT:  entry:
10742 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10743 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
10744 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10745 // CHECK7-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
10746 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
10747 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10748 // CHECK7-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
10749 // CHECK7-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
10750 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
10751 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
10752 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10753 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
10754 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10755 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
10756 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10757 // CHECK7-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
10758 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
10759 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10760 // CHECK7-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
10761 // CHECK7-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
10762 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
10763 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10764 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
10765 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10766 // CHECK7-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
10767 // CHECK7-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
10768 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10769 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
10770 // CHECK7-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
10771 // CHECK7-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
10772 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
10773 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
10774 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
10775 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10776 // CHECK7-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10777 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10778 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
10779 // CHECK7-NEXT:    ret void
10780 //
10781 //
10782 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7
10783 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
10784 // CHECK7-NEXT:  entry:
10785 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10786 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10787 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10788 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
10789 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10790 // CHECK7-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
10791 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
10792 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10793 // CHECK7-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
10794 // CHECK7-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
10795 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
10796 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
10797 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10798 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i8, align 1
10799 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10800 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10801 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10802 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10803 // CHECK7-NEXT:    [[IT:%.*]] = alloca i8, align 1
10804 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10805 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10806 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10807 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
10808 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10809 // CHECK7-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
10810 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
10811 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10812 // CHECK7-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
10813 // CHECK7-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
10814 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
10815 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10816 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
10817 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10818 // CHECK7-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
10819 // CHECK7-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
10820 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10821 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
10822 // CHECK7-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
10823 // CHECK7-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
10824 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10825 // CHECK7-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
10826 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10827 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10828 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10829 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10830 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
10831 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
10832 // CHECK7-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
10833 // CHECK7:       omp.dispatch.cond:
10834 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10835 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
10836 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10837 // CHECK7:       cond.true:
10838 // CHECK7-NEXT:    br label [[COND_END:%.*]]
10839 // CHECK7:       cond.false:
10840 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10841 // CHECK7-NEXT:    br label [[COND_END]]
10842 // CHECK7:       cond.end:
10843 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
10844 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10845 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10846 // CHECK7-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
10847 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10848 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10849 // CHECK7-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
10850 // CHECK7-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
10851 // CHECK7:       omp.dispatch.body:
10852 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10853 // CHECK7:       omp.inner.for.cond:
10854 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
10855 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
10856 // CHECK7-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
10857 // CHECK7-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10858 // CHECK7:       omp.inner.for.body:
10859 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
10860 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
10861 // CHECK7-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
10862 // CHECK7-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
10863 // CHECK7-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !36
10864 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
10865 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
10866 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
10867 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
10868 // CHECK7-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
10869 // CHECK7-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
10870 // CHECK7-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
10871 // CHECK7-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
10872 // CHECK7-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
10873 // CHECK7-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
10874 // CHECK7-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
10875 // CHECK7-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
10876 // CHECK7-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
10877 // CHECK7-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
10878 // CHECK7-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
10879 // CHECK7-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
10880 // CHECK7-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
10881 // CHECK7-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
10882 // CHECK7-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
10883 // CHECK7-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
10884 // CHECK7-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
10885 // CHECK7-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
10886 // CHECK7-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
10887 // CHECK7-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
10888 // CHECK7-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
10889 // CHECK7-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
10890 // CHECK7-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
10891 // CHECK7-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
10892 // CHECK7-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
10893 // CHECK7-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !36
10894 // CHECK7-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
10895 // CHECK7-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
10896 // CHECK7-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
10897 // CHECK7-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
10898 // CHECK7-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
10899 // CHECK7-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !36
10900 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10901 // CHECK7:       omp.body.continue:
10902 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10903 // CHECK7:       omp.inner.for.inc:
10904 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
10905 // CHECK7-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
10906 // CHECK7-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
10907 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
10908 // CHECK7:       omp.inner.for.end:
10909 // CHECK7-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
10910 // CHECK7:       omp.dispatch.inc:
10911 // CHECK7-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10912 // CHECK7-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
10913 // CHECK7-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
10914 // CHECK7-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
10915 // CHECK7-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10916 // CHECK7-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
10917 // CHECK7-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
10918 // CHECK7-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
10919 // CHECK7-NEXT:    br label [[OMP_DISPATCH_COND]]
10920 // CHECK7:       omp.dispatch.end:
10921 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
10922 // CHECK7-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10923 // CHECK7-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
10924 // CHECK7-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10925 // CHECK7:       .omp.final.then:
10926 // CHECK7-NEXT:    store i8 96, i8* [[IT]], align 1
10927 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10928 // CHECK7:       .omp.final.done:
10929 // CHECK7-NEXT:    ret void
10930 //
10931 //
10932 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari
10933 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
10934 // CHECK7-NEXT:  entry:
10935 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10936 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
10937 // CHECK7-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
10938 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10939 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
10940 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
10941 // CHECK7-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
10942 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
10943 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
10944 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
10945 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
10946 // CHECK7-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
10947 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
10948 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
10949 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
10950 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
10951 // CHECK7-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
10952 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
10953 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
10954 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
10955 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
10956 // CHECK7-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
10957 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
10958 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
10959 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
10960 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
10961 // CHECK7-NEXT:    ret i32 [[TMP8]]
10962 //
10963 //
10964 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
10965 // CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
10966 // CHECK7-NEXT:  entry:
10967 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
10968 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10969 // CHECK7-NEXT:    [[B:%.*]] = alloca i32, align 4
10970 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
10971 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
10972 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
10973 // CHECK7-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
10974 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
10975 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 4
10976 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 4
10977 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 4
10978 // CHECK7-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4
10979 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
10980 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10981 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
10982 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
10983 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
10984 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
10985 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
10986 // CHECK7-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
10987 // CHECK7-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
10988 // CHECK7-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
10989 // CHECK7-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
10990 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
10991 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
10992 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
10993 // CHECK7-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
10994 // CHECK7-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
10995 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
10996 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[B_CASTED]], align 4
10997 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
10998 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
10999 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
11000 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
11001 // CHECK7-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
11002 // CHECK7-NEXT:    store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
11003 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
11004 // CHECK7-NEXT:    [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11005 // CHECK7-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1
11006 // CHECK7-NEXT:    br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11007 // CHECK7:       omp_if.then:
11008 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
11009 // CHECK7-NEXT:    [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]]
11010 // CHECK7-NEXT:    [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2
11011 // CHECK7-NEXT:    [[TMP12:%.*]] = sext i32 [[TMP11]] to i64
11012 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11013 // CHECK7-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to %struct.S1**
11014 // CHECK7-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP14]], align 4
11015 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11016 // CHECK7-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double**
11017 // CHECK7-NEXT:    store double* [[A]], double** [[TMP16]], align 4
11018 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
11019 // CHECK7-NEXT:    store i64 8, i64* [[TMP17]], align 4
11020 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11021 // CHECK7-NEXT:    store i8* null, i8** [[TMP18]], align 4
11022 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11023 // CHECK7-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
11024 // CHECK7-NEXT:    store i32 [[TMP6]], i32* [[TMP20]], align 4
11025 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11026 // CHECK7-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
11027 // CHECK7-NEXT:    store i32 [[TMP6]], i32* [[TMP22]], align 4
11028 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
11029 // CHECK7-NEXT:    store i64 4, i64* [[TMP23]], align 4
11030 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11031 // CHECK7-NEXT:    store i8* null, i8** [[TMP24]], align 4
11032 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11033 // CHECK7-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
11034 // CHECK7-NEXT:    store i32 2, i32* [[TMP26]], align 4
11035 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11036 // CHECK7-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
11037 // CHECK7-NEXT:    store i32 2, i32* [[TMP28]], align 4
11038 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
11039 // CHECK7-NEXT:    store i64 4, i64* [[TMP29]], align 4
11040 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11041 // CHECK7-NEXT:    store i8* null, i8** [[TMP30]], align 4
11042 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
11043 // CHECK7-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
11044 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP32]], align 4
11045 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
11046 // CHECK7-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32*
11047 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP34]], align 4
11048 // CHECK7-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
11049 // CHECK7-NEXT:    store i64 4, i64* [[TMP35]], align 4
11050 // CHECK7-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
11051 // CHECK7-NEXT:    store i8* null, i8** [[TMP36]], align 4
11052 // CHECK7-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
11053 // CHECK7-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i16**
11054 // CHECK7-NEXT:    store i16* [[VLA]], i16** [[TMP38]], align 4
11055 // CHECK7-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
11056 // CHECK7-NEXT:    [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i16**
11057 // CHECK7-NEXT:    store i16* [[VLA]], i16** [[TMP40]], align 4
11058 // CHECK7-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
11059 // CHECK7-NEXT:    store i64 [[TMP12]], i64* [[TMP41]], align 4
11060 // CHECK7-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
11061 // CHECK7-NEXT:    store i8* null, i8** [[TMP42]], align 4
11062 // CHECK7-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
11063 // CHECK7-NEXT:    [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
11064 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[TMP44]], align 4
11065 // CHECK7-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
11066 // CHECK7-NEXT:    [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
11067 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[TMP46]], align 4
11068 // CHECK7-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
11069 // CHECK7-NEXT:    store i64 1, i64* [[TMP47]], align 4
11070 // CHECK7-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
11071 // CHECK7-NEXT:    store i8* null, i8** [[TMP48]], align 4
11072 // CHECK7-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11073 // CHECK7-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11074 // CHECK7-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
11075 // CHECK7-NEXT:    [[TMP52:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11076 // CHECK7-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP52]] to i1
11077 // CHECK7-NEXT:    [[TMP53:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1
11078 // CHECK7-NEXT:    [[TMP54:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, i32 6, i8** [[TMP49]], i8** [[TMP50]], i64* [[TMP51]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP53]])
11079 // CHECK7-NEXT:    [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0
11080 // CHECK7-NEXT:    br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11081 // CHECK7:       omp_offload.failed:
11082 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
11083 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
11084 // CHECK7:       omp_offload.cont:
11085 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
11086 // CHECK7:       omp_if.else:
11087 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
11088 // CHECK7-NEXT:    br label [[OMP_IF_END]]
11089 // CHECK7:       omp_if.end:
11090 // CHECK7-NEXT:    [[TMP56:%.*]] = mul nsw i32 1, [[TMP1]]
11091 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP56]]
11092 // CHECK7-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
11093 // CHECK7-NEXT:    [[TMP57:%.*]] = load i16, i16* [[ARRAYIDX5]], align 2
11094 // CHECK7-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP57]] to i32
11095 // CHECK7-NEXT:    [[TMP58:%.*]] = load i32, i32* [[B]], align 4
11096 // CHECK7-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], [[TMP58]]
11097 // CHECK7-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
11098 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
11099 // CHECK7-NEXT:    ret i32 [[ADD7]]
11100 //
11101 //
11102 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
11103 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
11104 // CHECK7-NEXT:  entry:
11105 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11106 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
11107 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
11108 // CHECK7-NEXT:    [[AAA:%.*]] = alloca i8, align 1
11109 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
11110 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11111 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11112 // CHECK7-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
11113 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
11114 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
11115 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
11116 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11117 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
11118 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
11119 // CHECK7-NEXT:    store i8 0, i8* [[AAA]], align 1
11120 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
11121 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11122 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11123 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
11124 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11125 // CHECK7-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
11126 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11127 // CHECK7-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
11128 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
11129 // CHECK7-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
11130 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
11131 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
11132 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
11133 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11134 // CHECK7:       omp_if.then:
11135 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11136 // CHECK7-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
11137 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
11138 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11139 // CHECK7-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
11140 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
11141 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11142 // CHECK7-NEXT:    store i8* null, i8** [[TMP11]], align 4
11143 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11144 // CHECK7-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
11145 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
11146 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11147 // CHECK7-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
11148 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
11149 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11150 // CHECK7-NEXT:    store i8* null, i8** [[TMP16]], align 4
11151 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11152 // CHECK7-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
11153 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
11154 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11155 // CHECK7-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
11156 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
11157 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11158 // CHECK7-NEXT:    store i8* null, i8** [[TMP21]], align 4
11159 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
11160 // CHECK7-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
11161 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
11162 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
11163 // CHECK7-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
11164 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
11165 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
11166 // CHECK7-NEXT:    store i8* null, i8** [[TMP26]], align 4
11167 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11168 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11169 // CHECK7-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
11170 // CHECK7-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
11171 // CHECK7-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11172 // CHECK7:       omp_offload.failed:
11173 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
11174 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
11175 // CHECK7:       omp_offload.cont:
11176 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
11177 // CHECK7:       omp_if.else:
11178 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
11179 // CHECK7-NEXT:    br label [[OMP_IF_END]]
11180 // CHECK7:       omp_if.end:
11181 // CHECK7-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
11182 // CHECK7-NEXT:    ret i32 [[TMP31]]
11183 //
11184 //
11185 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
11186 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
11187 // CHECK7-NEXT:  entry:
11188 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11189 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
11190 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
11191 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
11192 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11193 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11194 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
11195 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
11196 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
11197 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11198 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
11199 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
11200 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
11201 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11202 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11203 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
11204 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11205 // CHECK7-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
11206 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11207 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
11208 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
11209 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11210 // CHECK7:       omp_if.then:
11211 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11212 // CHECK7-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
11213 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
11214 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11215 // CHECK7-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
11216 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
11217 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11218 // CHECK7-NEXT:    store i8* null, i8** [[TMP9]], align 4
11219 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11220 // CHECK7-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
11221 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
11222 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11223 // CHECK7-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
11224 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
11225 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11226 // CHECK7-NEXT:    store i8* null, i8** [[TMP14]], align 4
11227 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11228 // CHECK7-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
11229 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
11230 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11231 // CHECK7-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
11232 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
11233 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11234 // CHECK7-NEXT:    store i8* null, i8** [[TMP19]], align 4
11235 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11236 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11237 // CHECK7-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
11238 // CHECK7-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
11239 // CHECK7-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11240 // CHECK7:       omp_offload.failed:
11241 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
11242 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
11243 // CHECK7:       omp_offload.cont:
11244 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
11245 // CHECK7:       omp_if.else:
11246 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
11247 // CHECK7-NEXT:    br label [[OMP_IF_END]]
11248 // CHECK7:       omp_if.end:
11249 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
11250 // CHECK7-NEXT:    ret i32 [[TMP24]]
11251 //
11252 //
11253 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
11254 // CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
11255 // CHECK7-NEXT:  entry:
11256 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11257 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11258 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11259 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11260 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
11261 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
11262 // CHECK7-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
11263 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
11264 // CHECK7-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
11265 // CHECK7-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
11266 // CHECK7-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
11267 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
11268 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11269 // CHECK7-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
11270 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11271 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11272 // CHECK7-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
11273 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11274 // CHECK7-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11275 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11276 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11277 // CHECK7-NEXT:    [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11278 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
11279 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
11280 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[B_CASTED]], align 4
11281 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
11282 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
11283 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
11284 // CHECK7-NEXT:    [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
11285 // CHECK7-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
11286 // CHECK7-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
11287 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
11288 // CHECK7-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
11289 // CHECK7-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
11290 // CHECK7-NEXT:    br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11291 // CHECK7:       omp_if.then:
11292 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
11293 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
11294 // CHECK7:       omp_if.else:
11295 // CHECK7-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
11296 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
11297 // CHECK7-NEXT:    call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR4]]
11298 // CHECK7-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
11299 // CHECK7-NEXT:    br label [[OMP_IF_END]]
11300 // CHECK7:       omp_if.end:
11301 // CHECK7-NEXT:    ret void
11302 //
11303 //
11304 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9
11305 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
11306 // CHECK7-NEXT:  entry:
11307 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11308 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11309 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11310 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11311 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11312 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11313 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
11314 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
11315 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
11316 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i64, align 4
11317 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
11318 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
11319 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
11320 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11321 // CHECK7-NEXT:    [[IT:%.*]] = alloca i64, align 8
11322 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11323 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11324 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11325 // CHECK7-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
11326 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11327 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11328 // CHECK7-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
11329 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11330 // CHECK7-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11331 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11332 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11333 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11334 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
11335 // CHECK7-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
11336 // CHECK7-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
11337 // CHECK7-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
11338 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11339 // CHECK7-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
11340 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
11341 // CHECK7-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11342 // CHECK7:       omp_if.then:
11343 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11344 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
11345 // CHECK7-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
11346 // CHECK7-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11347 // CHECK7-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
11348 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11349 // CHECK7:       cond.true:
11350 // CHECK7-NEXT:    br label [[COND_END:%.*]]
11351 // CHECK7:       cond.false:
11352 // CHECK7-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11353 // CHECK7-NEXT:    br label [[COND_END]]
11354 // CHECK7:       cond.end:
11355 // CHECK7-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
11356 // CHECK7-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
11357 // CHECK7-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
11358 // CHECK7-NEXT:    store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
11359 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11360 // CHECK7:       omp.inner.for.cond:
11361 // CHECK7-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
11362 // CHECK7-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !39
11363 // CHECK7-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
11364 // CHECK7-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11365 // CHECK7:       omp.inner.for.body:
11366 // CHECK7-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
11367 // CHECK7-NEXT:    [[MUL:%.*]] = mul i64 [[TMP12]], 400
11368 // CHECK7-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
11369 // CHECK7-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !39
11370 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
11371 // CHECK7-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
11372 // CHECK7-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
11373 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
11374 // CHECK7-NEXT:    store double [[ADD]], double* [[A]], align 4, !nontemporal !40, !llvm.access.group !39
11375 // CHECK7-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
11376 // CHECK7-NEXT:    [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !40, !llvm.access.group !39
11377 // CHECK7-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
11378 // CHECK7-NEXT:    store double [[INC]], double* [[A5]], align 4, !nontemporal !40, !llvm.access.group !39
11379 // CHECK7-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
11380 // CHECK7-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
11381 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
11382 // CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
11383 // CHECK7-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !39
11384 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11385 // CHECK7:       omp.body.continue:
11386 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11387 // CHECK7:       omp.inner.for.inc:
11388 // CHECK7-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
11389 // CHECK7-NEXT:    [[ADD8:%.*]] = add i64 [[TMP16]], 1
11390 // CHECK7-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
11391 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
11392 // CHECK7:       omp.inner.for.end:
11393 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
11394 // CHECK7:       omp_if.else:
11395 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11396 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
11397 // CHECK7-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
11398 // CHECK7-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11399 // CHECK7-NEXT:    [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3
11400 // CHECK7-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
11401 // CHECK7:       cond.true10:
11402 // CHECK7-NEXT:    br label [[COND_END12:%.*]]
11403 // CHECK7:       cond.false11:
11404 // CHECK7-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11405 // CHECK7-NEXT:    br label [[COND_END12]]
11406 // CHECK7:       cond.end12:
11407 // CHECK7-NEXT:    [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ]
11408 // CHECK7-NEXT:    store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8
11409 // CHECK7-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
11410 // CHECK7-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
11411 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND14:%.*]]
11412 // CHECK7:       omp.inner.for.cond14:
11413 // CHECK7-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
11414 // CHECK7-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11415 // CHECK7-NEXT:    [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
11416 // CHECK7-NEXT:    br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]]
11417 // CHECK7:       omp.inner.for.body16:
11418 // CHECK7-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
11419 // CHECK7-NEXT:    [[MUL17:%.*]] = mul i64 [[TMP24]], 400
11420 // CHECK7-NEXT:    [[SUB18:%.*]] = sub i64 2000, [[MUL17]]
11421 // CHECK7-NEXT:    store i64 [[SUB18]], i64* [[IT]], align 8
11422 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4
11423 // CHECK7-NEXT:    [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double
11424 // CHECK7-NEXT:    [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00
11425 // CHECK7-NEXT:    [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
11426 // CHECK7-NEXT:    store double [[ADD20]], double* [[A21]], align 4
11427 // CHECK7-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
11428 // CHECK7-NEXT:    [[TMP26:%.*]] = load double, double* [[A22]], align 4
11429 // CHECK7-NEXT:    [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00
11430 // CHECK7-NEXT:    store double [[INC23]], double* [[A22]], align 4
11431 // CHECK7-NEXT:    [[CONV24:%.*]] = fptosi double [[INC23]] to i16
11432 // CHECK7-NEXT:    [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]]
11433 // CHECK7-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]]
11434 // CHECK7-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
11435 // CHECK7-NEXT:    store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2
11436 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE27:%.*]]
11437 // CHECK7:       omp.body.continue27:
11438 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC28:%.*]]
11439 // CHECK7:       omp.inner.for.inc28:
11440 // CHECK7-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
11441 // CHECK7-NEXT:    [[ADD29:%.*]] = add i64 [[TMP28]], 1
11442 // CHECK7-NEXT:    store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8
11443 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP43:![0-9]+]]
11444 // CHECK7:       omp.inner.for.end30:
11445 // CHECK7-NEXT:    br label [[OMP_IF_END]]
11446 // CHECK7:       omp_if.end:
11447 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11448 // CHECK7:       omp.loop.exit:
11449 // CHECK7-NEXT:    [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11450 // CHECK7-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
11451 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
11452 // CHECK7-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11453 // CHECK7-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
11454 // CHECK7-NEXT:    br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11455 // CHECK7:       .omp.final.then:
11456 // CHECK7-NEXT:    store i64 400, i64* [[IT]], align 8
11457 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11458 // CHECK7:       .omp.final.done:
11459 // CHECK7-NEXT:    ret void
11460 //
11461 //
11462 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
11463 // CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
11464 // CHECK7-NEXT:  entry:
11465 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11466 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11467 // CHECK7-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11468 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11469 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11470 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11471 // CHECK7-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
11472 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11473 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11474 // CHECK7-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11475 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11476 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11477 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11478 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11479 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11480 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11481 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11482 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11483 // CHECK7-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11484 // CHECK7-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
11485 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11486 // CHECK7-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
11487 // CHECK7-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
11488 // CHECK7-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
11489 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
11490 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
11491 // CHECK7-NEXT:    ret void
11492 //
11493 //
11494 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11
11495 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
11496 // CHECK7-NEXT:  entry:
11497 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11498 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11499 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11500 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11501 // CHECK7-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11502 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11503 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11504 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11505 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11506 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11507 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11508 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11509 // CHECK7-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11510 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11511 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11512 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11513 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11514 // CHECK7-NEXT:    ret void
11515 //
11516 //
11517 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
11518 // CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
11519 // CHECK7-NEXT:  entry:
11520 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11521 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11522 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11523 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11524 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11525 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11526 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11527 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11528 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11529 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11530 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11531 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11532 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11533 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11534 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11535 // CHECK7-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
11536 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11537 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
11538 // CHECK7-NEXT:    ret void
11539 //
11540 //
11541 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14
11542 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
11543 // CHECK7-NEXT:  entry:
11544 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11545 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11546 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11547 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11548 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11549 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
11550 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i64, align 4
11551 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
11552 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
11553 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
11554 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11555 // CHECK7-NEXT:    [[I:%.*]] = alloca i64, align 8
11556 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11557 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11558 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11559 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11560 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11561 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11562 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11563 // CHECK7-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
11564 // CHECK7-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
11565 // CHECK7-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
11566 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11567 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11568 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
11569 // CHECK7-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
11570 // CHECK7-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11571 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
11572 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11573 // CHECK7:       cond.true:
11574 // CHECK7-NEXT:    br label [[COND_END:%.*]]
11575 // CHECK7:       cond.false:
11576 // CHECK7-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
11577 // CHECK7-NEXT:    br label [[COND_END]]
11578 // CHECK7:       cond.end:
11579 // CHECK7-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
11580 // CHECK7-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
11581 // CHECK7-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
11582 // CHECK7-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
11583 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11584 // CHECK7:       omp.inner.for.cond:
11585 // CHECK7-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
11586 // CHECK7-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !45
11587 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
11588 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11589 // CHECK7:       omp.inner.for.body:
11590 // CHECK7-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
11591 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
11592 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
11593 // CHECK7-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !45
11594 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
11595 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
11596 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
11597 // CHECK7-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45
11598 // CHECK7-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
11599 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
11600 // CHECK7-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
11601 // CHECK7-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45
11602 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11603 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
11604 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
11605 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
11606 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11607 // CHECK7:       omp.body.continue:
11608 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11609 // CHECK7:       omp.inner.for.inc:
11610 // CHECK7-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
11611 // CHECK7-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
11612 // CHECK7-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
11613 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
11614 // CHECK7:       omp.inner.for.end:
11615 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11616 // CHECK7:       omp.loop.exit:
11617 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
11618 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11619 // CHECK7-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
11620 // CHECK7-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11621 // CHECK7:       .omp.final.then:
11622 // CHECK7-NEXT:    store i64 11, i64* [[I]], align 8
11623 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11624 // CHECK7:       .omp.final.done:
11625 // CHECK7-NEXT:    ret void
11626 //
11627 //
11628 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
11629 // CHECK7-SAME: () #[[ATTR7:[0-9]+]] {
11630 // CHECK7-NEXT:  entry:
11631 // CHECK7-NEXT:    call void @__tgt_register_requires(i64 1)
11632 // CHECK7-NEXT:    ret void
11633 //
11634 //
11635 // CHECK8-LABEL: define {{[^@]+}}@_Z7get_valv
11636 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
11637 // CHECK8-NEXT:  entry:
11638 // CHECK8-NEXT:    ret i64 0
11639 //
11640 //
11641 // CHECK8-LABEL: define {{[^@]+}}@_Z3fooi
11642 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
11643 // CHECK8-NEXT:  entry:
11644 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11645 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
11646 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
11647 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
11648 // CHECK8-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
11649 // CHECK8-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
11650 // CHECK8-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
11651 // CHECK8-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
11652 // CHECK8-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
11653 // CHECK8-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
11654 // CHECK8-NEXT:    [[K:%.*]] = alloca i64, align 8
11655 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11656 // CHECK8-NEXT:    [[LIN:%.*]] = alloca i32, align 4
11657 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11658 // CHECK8-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
11659 // CHECK8-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
11660 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
11661 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
11662 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
11663 // CHECK8-NEXT:    [[A_CASTED3:%.*]] = alloca i32, align 4
11664 // CHECK8-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
11665 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
11666 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
11667 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
11668 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
11669 // CHECK8-NEXT:    [[A_CASTED11:%.*]] = alloca i32, align 4
11670 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
11671 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
11672 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
11673 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
11674 // CHECK8-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
11675 // CHECK8-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
11676 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11677 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
11678 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
11679 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
11680 // CHECK8-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
11681 // CHECK8-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
11682 // CHECK8-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
11683 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
11684 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
11685 // CHECK8-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
11686 // CHECK8-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
11687 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
11688 // CHECK8-NEXT:    [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
11689 // CHECK8-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
11690 // CHECK8-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
11691 // CHECK8-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]])
11692 // CHECK8-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
11693 // CHECK8-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
11694 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
11695 // CHECK8-NEXT:    store i32 [[TMP9]], i32* [[A_CASTED]], align 4
11696 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
11697 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]]
11698 // CHECK8-NEXT:    store i32 12, i32* [[LIN]], align 4
11699 // CHECK8-NEXT:    [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
11700 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11701 // CHECK8-NEXT:    store i16 [[TMP11]], i16* [[CONV]], align 2
11702 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11703 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4
11704 // CHECK8-NEXT:    store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4
11705 // CHECK8-NEXT:    [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
11706 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
11707 // CHECK8-NEXT:    store i32 [[TMP15]], i32* [[A_CASTED2]], align 4
11708 // CHECK8-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4
11709 // CHECK8-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11710 // CHECK8-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
11711 // CHECK8-NEXT:    store i32 [[TMP12]], i32* [[TMP18]], align 4
11712 // CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11713 // CHECK8-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
11714 // CHECK8-NEXT:    store i32 [[TMP12]], i32* [[TMP20]], align 4
11715 // CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11716 // CHECK8-NEXT:    store i8* null, i8** [[TMP21]], align 4
11717 // CHECK8-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11718 // CHECK8-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
11719 // CHECK8-NEXT:    store i32 [[TMP14]], i32* [[TMP23]], align 4
11720 // CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11721 // CHECK8-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
11722 // CHECK8-NEXT:    store i32 [[TMP14]], i32* [[TMP25]], align 4
11723 // CHECK8-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11724 // CHECK8-NEXT:    store i8* null, i8** [[TMP26]], align 4
11725 // CHECK8-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11726 // CHECK8-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
11727 // CHECK8-NEXT:    store i32 [[TMP16]], i32* [[TMP28]], align 4
11728 // CHECK8-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11729 // CHECK8-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
11730 // CHECK8-NEXT:    store i32 [[TMP16]], i32* [[TMP30]], align 4
11731 // CHECK8-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11732 // CHECK8-NEXT:    store i8* null, i8** [[TMP31]], align 4
11733 // CHECK8-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11734 // CHECK8-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11735 // CHECK8-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
11736 // CHECK8-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
11737 // CHECK8-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11738 // CHECK8:       omp_offload.failed:
11739 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]]
11740 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]
11741 // CHECK8:       omp_offload.cont:
11742 // CHECK8-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
11743 // CHECK8-NEXT:    store i32 [[TMP36]], i32* [[A_CASTED3]], align 4
11744 // CHECK8-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A_CASTED3]], align 4
11745 // CHECK8-NEXT:    [[TMP38:%.*]] = load i16, i16* [[AA]], align 2
11746 // CHECK8-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
11747 // CHECK8-NEXT:    store i16 [[TMP38]], i16* [[CONV5]], align 2
11748 // CHECK8-NEXT:    [[TMP39:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
11749 // CHECK8-NEXT:    [[TMP40:%.*]] = load i32, i32* [[N_ADDR]], align 4
11750 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP40]], 10
11751 // CHECK8-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11752 // CHECK8:       omp_if.then:
11753 // CHECK8-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
11754 // CHECK8-NEXT:    [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32*
11755 // CHECK8-NEXT:    store i32 [[TMP37]], i32* [[TMP42]], align 4
11756 // CHECK8-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
11757 // CHECK8-NEXT:    [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
11758 // CHECK8-NEXT:    store i32 [[TMP37]], i32* [[TMP44]], align 4
11759 // CHECK8-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
11760 // CHECK8-NEXT:    store i8* null, i8** [[TMP45]], align 4
11761 // CHECK8-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
11762 // CHECK8-NEXT:    [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32*
11763 // CHECK8-NEXT:    store i32 [[TMP39]], i32* [[TMP47]], align 4
11764 // CHECK8-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
11765 // CHECK8-NEXT:    [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32*
11766 // CHECK8-NEXT:    store i32 [[TMP39]], i32* [[TMP49]], align 4
11767 // CHECK8-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
11768 // CHECK8-NEXT:    store i8* null, i8** [[TMP50]], align 4
11769 // CHECK8-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
11770 // CHECK8-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
11771 // CHECK8-NEXT:    [[TMP53:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP51]], i8** [[TMP52]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
11772 // CHECK8-NEXT:    [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
11773 // CHECK8-NEXT:    br i1 [[TMP54]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
11774 // CHECK8:       omp_offload.failed9:
11775 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
11776 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
11777 // CHECK8:       omp_offload.cont10:
11778 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
11779 // CHECK8:       omp_if.else:
11780 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]]
11781 // CHECK8-NEXT:    br label [[OMP_IF_END]]
11782 // CHECK8:       omp_if.end:
11783 // CHECK8-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
11784 // CHECK8-NEXT:    store i32 [[TMP55]], i32* [[DOTCAPTURE_EXPR_]], align 4
11785 // CHECK8-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A]], align 4
11786 // CHECK8-NEXT:    store i32 [[TMP56]], i32* [[A_CASTED11]], align 4
11787 // CHECK8-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A_CASTED11]], align 4
11788 // CHECK8-NEXT:    [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11789 // CHECK8-NEXT:    store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
11790 // CHECK8-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
11791 // CHECK8-NEXT:    [[TMP60:%.*]] = load i32, i32* [[N_ADDR]], align 4
11792 // CHECK8-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP60]], 20
11793 // CHECK8-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
11794 // CHECK8:       omp_if.then13:
11795 // CHECK8-NEXT:    [[TMP61:%.*]] = mul nuw i32 [[TMP1]], 4
11796 // CHECK8-NEXT:    [[TMP62:%.*]] = sext i32 [[TMP61]] to i64
11797 // CHECK8-NEXT:    [[TMP63:%.*]] = mul nuw i32 5, [[TMP3]]
11798 // CHECK8-NEXT:    [[TMP64:%.*]] = mul nuw i32 [[TMP63]], 8
11799 // CHECK8-NEXT:    [[TMP65:%.*]] = sext i32 [[TMP64]] to i64
11800 // CHECK8-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
11801 // CHECK8-NEXT:    [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32*
11802 // CHECK8-NEXT:    store i32 [[TMP57]], i32* [[TMP67]], align 4
11803 // CHECK8-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
11804 // CHECK8-NEXT:    [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
11805 // CHECK8-NEXT:    store i32 [[TMP57]], i32* [[TMP69]], align 4
11806 // CHECK8-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
11807 // CHECK8-NEXT:    store i64 4, i64* [[TMP70]], align 4
11808 // CHECK8-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
11809 // CHECK8-NEXT:    store i8* null, i8** [[TMP71]], align 4
11810 // CHECK8-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
11811 // CHECK8-NEXT:    [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [10 x float]**
11812 // CHECK8-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP73]], align 4
11813 // CHECK8-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
11814 // CHECK8-NEXT:    [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]**
11815 // CHECK8-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 4
11816 // CHECK8-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
11817 // CHECK8-NEXT:    store i64 40, i64* [[TMP76]], align 4
11818 // CHECK8-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
11819 // CHECK8-NEXT:    store i8* null, i8** [[TMP77]], align 4
11820 // CHECK8-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
11821 // CHECK8-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
11822 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP79]], align 4
11823 // CHECK8-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
11824 // CHECK8-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
11825 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP81]], align 4
11826 // CHECK8-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
11827 // CHECK8-NEXT:    store i64 4, i64* [[TMP82]], align 4
11828 // CHECK8-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
11829 // CHECK8-NEXT:    store i8* null, i8** [[TMP83]], align 4
11830 // CHECK8-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
11831 // CHECK8-NEXT:    [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float**
11832 // CHECK8-NEXT:    store float* [[VLA]], float** [[TMP85]], align 4
11833 // CHECK8-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
11834 // CHECK8-NEXT:    [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float**
11835 // CHECK8-NEXT:    store float* [[VLA]], float** [[TMP87]], align 4
11836 // CHECK8-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
11837 // CHECK8-NEXT:    store i64 [[TMP62]], i64* [[TMP88]], align 4
11838 // CHECK8-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
11839 // CHECK8-NEXT:    store i8* null, i8** [[TMP89]], align 4
11840 // CHECK8-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
11841 // CHECK8-NEXT:    [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]**
11842 // CHECK8-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 4
11843 // CHECK8-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
11844 // CHECK8-NEXT:    [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]**
11845 // CHECK8-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 4
11846 // CHECK8-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
11847 // CHECK8-NEXT:    store i64 400, i64* [[TMP94]], align 4
11848 // CHECK8-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
11849 // CHECK8-NEXT:    store i8* null, i8** [[TMP95]], align 4
11850 // CHECK8-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
11851 // CHECK8-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
11852 // CHECK8-NEXT:    store i32 5, i32* [[TMP97]], align 4
11853 // CHECK8-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
11854 // CHECK8-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
11855 // CHECK8-NEXT:    store i32 5, i32* [[TMP99]], align 4
11856 // CHECK8-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
11857 // CHECK8-NEXT:    store i64 4, i64* [[TMP100]], align 4
11858 // CHECK8-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
11859 // CHECK8-NEXT:    store i8* null, i8** [[TMP101]], align 4
11860 // CHECK8-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
11861 // CHECK8-NEXT:    [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i32*
11862 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP103]], align 4
11863 // CHECK8-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
11864 // CHECK8-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to i32*
11865 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP105]], align 4
11866 // CHECK8-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
11867 // CHECK8-NEXT:    store i64 4, i64* [[TMP106]], align 4
11868 // CHECK8-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
11869 // CHECK8-NEXT:    store i8* null, i8** [[TMP107]], align 4
11870 // CHECK8-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
11871 // CHECK8-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to double**
11872 // CHECK8-NEXT:    store double* [[VLA1]], double** [[TMP109]], align 4
11873 // CHECK8-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
11874 // CHECK8-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to double**
11875 // CHECK8-NEXT:    store double* [[VLA1]], double** [[TMP111]], align 4
11876 // CHECK8-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
11877 // CHECK8-NEXT:    store i64 [[TMP65]], i64* [[TMP112]], align 4
11878 // CHECK8-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
11879 // CHECK8-NEXT:    store i8* null, i8** [[TMP113]], align 4
11880 // CHECK8-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
11881 // CHECK8-NEXT:    [[TMP115:%.*]] = bitcast i8** [[TMP114]] to %struct.TT**
11882 // CHECK8-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP115]], align 4
11883 // CHECK8-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
11884 // CHECK8-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to %struct.TT**
11885 // CHECK8-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP117]], align 4
11886 // CHECK8-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
11887 // CHECK8-NEXT:    store i64 12, i64* [[TMP118]], align 4
11888 // CHECK8-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
11889 // CHECK8-NEXT:    store i8* null, i8** [[TMP119]], align 4
11890 // CHECK8-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
11891 // CHECK8-NEXT:    [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i32*
11892 // CHECK8-NEXT:    store i32 [[TMP59]], i32* [[TMP121]], align 4
11893 // CHECK8-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
11894 // CHECK8-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
11895 // CHECK8-NEXT:    store i32 [[TMP59]], i32* [[TMP123]], align 4
11896 // CHECK8-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
11897 // CHECK8-NEXT:    store i64 4, i64* [[TMP124]], align 4
11898 // CHECK8-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
11899 // CHECK8-NEXT:    store i8* null, i8** [[TMP125]], align 4
11900 // CHECK8-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
11901 // CHECK8-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
11902 // CHECK8-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
11903 // CHECK8-NEXT:    [[TMP129:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP126]], i8** [[TMP127]], i64* [[TMP128]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
11904 // CHECK8-NEXT:    [[TMP130:%.*]] = icmp ne i32 [[TMP129]], 0
11905 // CHECK8-NEXT:    br i1 [[TMP130]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
11906 // CHECK8:       omp_offload.failed17:
11907 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
11908 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
11909 // CHECK8:       omp_offload.cont18:
11910 // CHECK8-NEXT:    br label [[OMP_IF_END20:%.*]]
11911 // CHECK8:       omp_if.else19:
11912 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]]
11913 // CHECK8-NEXT:    br label [[OMP_IF_END20]]
11914 // CHECK8:       omp_if.end20:
11915 // CHECK8-NEXT:    [[TMP131:%.*]] = load i32, i32* [[A]], align 4
11916 // CHECK8-NEXT:    [[TMP132:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
11917 // CHECK8-NEXT:    call void @llvm.stackrestore(i8* [[TMP132]])
11918 // CHECK8-NEXT:    ret i32 [[TMP131]]
11919 //
11920 //
11921 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
11922 // CHECK8-SAME: () #[[ATTR2:[0-9]+]] {
11923 // CHECK8-NEXT:  entry:
11924 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
11925 // CHECK8-NEXT:    ret void
11926 //
11927 //
11928 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined.
11929 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
11930 // CHECK8-NEXT:  entry:
11931 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11932 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11933 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11934 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11935 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11936 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11937 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11938 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11939 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
11940 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11941 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11942 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11943 // CHECK8-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
11944 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11945 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11946 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11947 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11948 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11949 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11950 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
11951 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11952 // CHECK8:       cond.true:
11953 // CHECK8-NEXT:    br label [[COND_END:%.*]]
11954 // CHECK8:       cond.false:
11955 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11956 // CHECK8-NEXT:    br label [[COND_END]]
11957 // CHECK8:       cond.end:
11958 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11959 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11960 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11961 // CHECK8-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11962 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11963 // CHECK8:       omp.inner.for.cond:
11964 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11965 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
11966 // CHECK8-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11967 // CHECK8-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11968 // CHECK8:       omp.inner.for.body:
11969 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11970 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
11971 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
11972 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
11973 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11974 // CHECK8:       omp.body.continue:
11975 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11976 // CHECK8:       omp.inner.for.inc:
11977 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11978 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
11979 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11980 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
11981 // CHECK8:       omp.inner.for.end:
11982 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11983 // CHECK8:       omp.loop.exit:
11984 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11985 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11986 // CHECK8-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
11987 // CHECK8-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11988 // CHECK8:       .omp.final.then:
11989 // CHECK8-NEXT:    store i32 33, i32* [[I]], align 4
11990 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11991 // CHECK8:       .omp.final.done:
11992 // CHECK8-NEXT:    ret void
11993 //
11994 //
11995 // CHECK8-LABEL: define {{[^@]+}}@.omp_task_entry.
11996 // CHECK8-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
11997 // CHECK8-NEXT:  entry:
11998 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
11999 // CHECK8-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
12000 // CHECK8-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
12001 // CHECK8-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
12002 // CHECK8-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
12003 // CHECK8-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
12004 // CHECK8-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
12005 // CHECK8-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
12006 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
12007 // CHECK8-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
12008 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
12009 // CHECK8-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
12010 // CHECK8-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
12011 // CHECK8-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
12012 // CHECK8-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
12013 // CHECK8-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
12014 // CHECK8-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
12015 // CHECK8-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
12016 // CHECK8-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
12017 // CHECK8-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
12018 // CHECK8-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
12019 // CHECK8-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
12020 // CHECK8-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
12021 // CHECK8-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26
12022 // CHECK8-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26
12023 // CHECK8-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26
12024 // CHECK8-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26
12025 // CHECK8-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
12026 // CHECK8-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26
12027 // CHECK8-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
12028 // CHECK8-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
12029 // CHECK8-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
12030 // CHECK8:       omp_offload.failed.i:
12031 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]]
12032 // CHECK8-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
12033 // CHECK8:       .omp_outlined..1.exit:
12034 // CHECK8-NEXT:    ret i32 0
12035 //
12036 //
12037 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
12038 // CHECK8-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
12039 // CHECK8-NEXT:  entry:
12040 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12041 // CHECK8-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
12042 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12043 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12044 // CHECK8-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
12045 // CHECK8-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
12046 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
12047 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
12048 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
12049 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
12050 // CHECK8-NEXT:    ret void
12051 //
12052 //
12053 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2
12054 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
12055 // CHECK8-NEXT:  entry:
12056 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12057 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12058 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12059 // CHECK8-NEXT:    [[K_ADDR:%.*]] = alloca i64*, align 4
12060 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12061 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12062 // CHECK8-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
12063 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12064 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12065 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12066 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12067 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
12068 // CHECK8-NEXT:    [[K1:%.*]] = alloca i64, align 8
12069 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12070 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12071 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12072 // CHECK8-NEXT:    store i64* [[K]], i64** [[K_ADDR]], align 4
12073 // CHECK8-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
12074 // CHECK8-NEXT:    [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
12075 // CHECK8-NEXT:    store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
12076 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12077 // CHECK8-NEXT:    store i32 8, i32* [[DOTOMP_UB]], align 4
12078 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12079 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12080 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12081 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
12082 // CHECK8-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
12083 // CHECK8-NEXT:    call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
12084 // CHECK8-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
12085 // CHECK8:       omp.dispatch.cond:
12086 // CHECK8-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
12087 // CHECK8-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
12088 // CHECK8-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
12089 // CHECK8:       omp.dispatch.body:
12090 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12091 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
12092 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12093 // CHECK8:       omp.inner.for.cond:
12094 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
12095 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
12096 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
12097 // CHECK8-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12098 // CHECK8:       omp.inner.for.body:
12099 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
12100 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
12101 // CHECK8-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
12102 // CHECK8-NEXT:    store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !27
12103 // CHECK8-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !27
12104 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
12105 // CHECK8-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
12106 // CHECK8-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
12107 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
12108 // CHECK8-NEXT:    store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !27
12109 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !27
12110 // CHECK8-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
12111 // CHECK8-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !27
12112 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12113 // CHECK8:       omp.body.continue:
12114 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12115 // CHECK8:       omp.inner.for.inc:
12116 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
12117 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
12118 // CHECK8-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
12119 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
12120 // CHECK8:       omp.inner.for.end:
12121 // CHECK8-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
12122 // CHECK8:       omp.dispatch.inc:
12123 // CHECK8-NEXT:    br label [[OMP_DISPATCH_COND]]
12124 // CHECK8:       omp.dispatch.end:
12125 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12126 // CHECK8-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
12127 // CHECK8-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12128 // CHECK8:       .omp.final.then:
12129 // CHECK8-NEXT:    store i32 1, i32* [[I]], align 4
12130 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12131 // CHECK8:       .omp.final.done:
12132 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12133 // CHECK8-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
12134 // CHECK8-NEXT:    br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
12135 // CHECK8:       .omp.linear.pu:
12136 // CHECK8-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
12137 // CHECK8-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP17]], 27
12138 // CHECK8-NEXT:    store i64 [[ADD5]], i64* [[TMP0]], align 8
12139 // CHECK8-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
12140 // CHECK8:       .omp.linear.pu.done:
12141 // CHECK8-NEXT:    ret void
12142 //
12143 //
12144 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
12145 // CHECK8-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
12146 // CHECK8-NEXT:  entry:
12147 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12148 // CHECK8-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
12149 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12150 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12151 // CHECK8-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
12152 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12153 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12154 // CHECK8-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
12155 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12156 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12157 // CHECK8-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
12158 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12159 // CHECK8-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
12160 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12161 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
12162 // CHECK8-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
12163 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
12164 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
12165 // CHECK8-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
12166 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
12167 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
12168 // CHECK8-NEXT:    ret void
12169 //
12170 //
12171 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3
12172 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {
12173 // CHECK8-NEXT:  entry:
12174 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12175 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12176 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12177 // CHECK8-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
12178 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12179 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
12180 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i64, align 4
12181 // CHECK8-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
12182 // CHECK8-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
12183 // CHECK8-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
12184 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
12185 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
12186 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
12187 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12188 // CHECK8-NEXT:    [[IT:%.*]] = alloca i64, align 8
12189 // CHECK8-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
12190 // CHECK8-NEXT:    [[A3:%.*]] = alloca i32, align 4
12191 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12192 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12193 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12194 // CHECK8-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
12195 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12196 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12197 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
12198 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
12199 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
12200 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
12201 // CHECK8-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
12202 // CHECK8-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
12203 // CHECK8-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
12204 // CHECK8-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
12205 // CHECK8-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
12206 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12207 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12208 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
12209 // CHECK8-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
12210 // CHECK8-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
12211 // CHECK8-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
12212 // CHECK8-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
12213 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12214 // CHECK8:       cond.true:
12215 // CHECK8-NEXT:    br label [[COND_END:%.*]]
12216 // CHECK8:       cond.false:
12217 // CHECK8-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
12218 // CHECK8-NEXT:    br label [[COND_END]]
12219 // CHECK8:       cond.end:
12220 // CHECK8-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
12221 // CHECK8-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
12222 // CHECK8-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
12223 // CHECK8-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
12224 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12225 // CHECK8:       omp.inner.for.cond:
12226 // CHECK8-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
12227 // CHECK8-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
12228 // CHECK8-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
12229 // CHECK8-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12230 // CHECK8:       omp.inner.for.body:
12231 // CHECK8-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
12232 // CHECK8-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
12233 // CHECK8-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
12234 // CHECK8-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !30
12235 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !30
12236 // CHECK8-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
12237 // CHECK8-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
12238 // CHECK8-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
12239 // CHECK8-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
12240 // CHECK8-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
12241 // CHECK8-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
12242 // CHECK8-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !30
12243 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30
12244 // CHECK8-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
12245 // CHECK8-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
12246 // CHECK8-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30
12247 // CHECK8-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
12248 // CHECK8-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
12249 // CHECK8-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
12250 // CHECK8-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30
12251 // CHECK8-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
12252 // CHECK8-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
12253 // CHECK8-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
12254 // CHECK8-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
12255 // CHECK8-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !30
12256 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12257 // CHECK8:       omp.body.continue:
12258 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12259 // CHECK8:       omp.inner.for.inc:
12260 // CHECK8-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
12261 // CHECK8-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
12262 // CHECK8-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
12263 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
12264 // CHECK8:       omp.inner.for.end:
12265 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12266 // CHECK8:       omp.loop.exit:
12267 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
12268 // CHECK8-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12269 // CHECK8-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
12270 // CHECK8-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12271 // CHECK8:       .omp.final.then:
12272 // CHECK8-NEXT:    store i64 400, i64* [[IT]], align 8
12273 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12274 // CHECK8:       .omp.final.done:
12275 // CHECK8-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12276 // CHECK8-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
12277 // CHECK8-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
12278 // CHECK8:       .omp.linear.pu:
12279 // CHECK8-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
12280 // CHECK8-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
12281 // CHECK8-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
12282 // CHECK8-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP23]]
12283 // CHECK8-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
12284 // CHECK8-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
12285 // CHECK8-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
12286 // CHECK8-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
12287 // CHECK8-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
12288 // CHECK8-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
12289 // CHECK8-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP25]]
12290 // CHECK8-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
12291 // CHECK8-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
12292 // CHECK8-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
12293 // CHECK8-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
12294 // CHECK8:       .omp.linear.pu.done:
12295 // CHECK8-NEXT:    ret void
12296 //
12297 //
12298 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
12299 // CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
12300 // CHECK8-NEXT:  entry:
12301 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12302 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12303 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12304 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12305 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12306 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12307 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12308 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
12309 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
12310 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
12311 // CHECK8-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
12312 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12313 // CHECK8-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
12314 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12315 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
12316 // CHECK8-NEXT:    ret void
12317 //
12318 //
12319 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4
12320 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] {
12321 // CHECK8-NEXT:  entry:
12322 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12323 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12324 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12325 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12326 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12327 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i16, align 2
12328 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12329 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12330 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12331 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12332 // CHECK8-NEXT:    [[IT:%.*]] = alloca i16, align 2
12333 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12334 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12335 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12336 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12337 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12338 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12339 // CHECK8-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
12340 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12341 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12342 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12343 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
12344 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12345 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12346 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
12347 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12348 // CHECK8:       cond.true:
12349 // CHECK8-NEXT:    br label [[COND_END:%.*]]
12350 // CHECK8:       cond.false:
12351 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12352 // CHECK8-NEXT:    br label [[COND_END]]
12353 // CHECK8:       cond.end:
12354 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
12355 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12356 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12357 // CHECK8-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
12358 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12359 // CHECK8:       omp.inner.for.cond:
12360 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
12361 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
12362 // CHECK8-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
12363 // CHECK8-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12364 // CHECK8:       omp.inner.for.body:
12365 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
12366 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
12367 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
12368 // CHECK8-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
12369 // CHECK8-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33
12370 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
12371 // CHECK8-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
12372 // CHECK8-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
12373 // CHECK8-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
12374 // CHECK8-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
12375 // CHECK8-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
12376 // CHECK8-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
12377 // CHECK8-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !33
12378 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12379 // CHECK8:       omp.body.continue:
12380 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12381 // CHECK8:       omp.inner.for.inc:
12382 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
12383 // CHECK8-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
12384 // CHECK8-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
12385 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
12386 // CHECK8:       omp.inner.for.end:
12387 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12388 // CHECK8:       omp.loop.exit:
12389 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
12390 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12391 // CHECK8-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
12392 // CHECK8-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12393 // CHECK8:       .omp.final.then:
12394 // CHECK8-NEXT:    store i16 22, i16* [[IT]], align 2
12395 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12396 // CHECK8:       .omp.final.done:
12397 // CHECK8-NEXT:    ret void
12398 //
12399 //
12400 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
12401 // CHECK8-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
12402 // CHECK8-NEXT:  entry:
12403 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12404 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
12405 // CHECK8-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12406 // CHECK8-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
12407 // CHECK8-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
12408 // CHECK8-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12409 // CHECK8-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
12410 // CHECK8-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
12411 // CHECK8-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
12412 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12413 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12414 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
12415 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12416 // CHECK8-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
12417 // CHECK8-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12418 // CHECK8-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
12419 // CHECK8-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
12420 // CHECK8-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
12421 // CHECK8-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
12422 // CHECK8-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
12423 // CHECK8-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
12424 // CHECK8-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12425 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
12426 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12427 // CHECK8-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
12428 // CHECK8-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
12429 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
12430 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
12431 // CHECK8-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
12432 // CHECK8-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
12433 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
12434 // CHECK8-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
12435 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
12436 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12437 // CHECK8-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
12438 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
12439 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
12440 // CHECK8-NEXT:    ret void
12441 //
12442 //
12443 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7
12444 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
12445 // CHECK8-NEXT:  entry:
12446 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12447 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12448 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12449 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
12450 // CHECK8-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12451 // CHECK8-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
12452 // CHECK8-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
12453 // CHECK8-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12454 // CHECK8-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
12455 // CHECK8-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
12456 // CHECK8-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
12457 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12458 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12459 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i8, align 1
12460 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12461 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12462 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12463 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12464 // CHECK8-NEXT:    [[IT:%.*]] = alloca i8, align 1
12465 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12466 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12467 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12468 // CHECK8-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
12469 // CHECK8-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12470 // CHECK8-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
12471 // CHECK8-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
12472 // CHECK8-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
12473 // CHECK8-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
12474 // CHECK8-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
12475 // CHECK8-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
12476 // CHECK8-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12477 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
12478 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12479 // CHECK8-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
12480 // CHECK8-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
12481 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
12482 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
12483 // CHECK8-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
12484 // CHECK8-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
12485 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12486 // CHECK8-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
12487 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12488 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12489 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12490 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12491 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
12492 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
12493 // CHECK8-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
12494 // CHECK8:       omp.dispatch.cond:
12495 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12496 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
12497 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12498 // CHECK8:       cond.true:
12499 // CHECK8-NEXT:    br label [[COND_END:%.*]]
12500 // CHECK8:       cond.false:
12501 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12502 // CHECK8-NEXT:    br label [[COND_END]]
12503 // CHECK8:       cond.end:
12504 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
12505 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12506 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12507 // CHECK8-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
12508 // CHECK8-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12509 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12510 // CHECK8-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
12511 // CHECK8-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
12512 // CHECK8:       omp.dispatch.body:
12513 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12514 // CHECK8:       omp.inner.for.cond:
12515 // CHECK8-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
12516 // CHECK8-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
12517 // CHECK8-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
12518 // CHECK8-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12519 // CHECK8:       omp.inner.for.body:
12520 // CHECK8-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
12521 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
12522 // CHECK8-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
12523 // CHECK8-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
12524 // CHECK8-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !36
12525 // CHECK8-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
12526 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
12527 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
12528 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
12529 // CHECK8-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
12530 // CHECK8-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
12531 // CHECK8-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
12532 // CHECK8-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
12533 // CHECK8-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
12534 // CHECK8-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
12535 // CHECK8-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
12536 // CHECK8-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
12537 // CHECK8-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
12538 // CHECK8-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
12539 // CHECK8-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
12540 // CHECK8-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
12541 // CHECK8-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
12542 // CHECK8-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
12543 // CHECK8-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
12544 // CHECK8-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
12545 // CHECK8-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
12546 // CHECK8-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
12547 // CHECK8-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
12548 // CHECK8-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
12549 // CHECK8-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
12550 // CHECK8-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
12551 // CHECK8-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
12552 // CHECK8-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
12553 // CHECK8-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
12554 // CHECK8-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !36
12555 // CHECK8-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
12556 // CHECK8-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
12557 // CHECK8-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
12558 // CHECK8-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
12559 // CHECK8-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
12560 // CHECK8-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !36
12561 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12562 // CHECK8:       omp.body.continue:
12563 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12564 // CHECK8:       omp.inner.for.inc:
12565 // CHECK8-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
12566 // CHECK8-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
12567 // CHECK8-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
12568 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
12569 // CHECK8:       omp.inner.for.end:
12570 // CHECK8-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
12571 // CHECK8:       omp.dispatch.inc:
12572 // CHECK8-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12573 // CHECK8-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
12574 // CHECK8-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
12575 // CHECK8-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
12576 // CHECK8-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12577 // CHECK8-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
12578 // CHECK8-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
12579 // CHECK8-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
12580 // CHECK8-NEXT:    br label [[OMP_DISPATCH_COND]]
12581 // CHECK8:       omp.dispatch.end:
12582 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
12583 // CHECK8-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12584 // CHECK8-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
12585 // CHECK8-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12586 // CHECK8:       .omp.final.then:
12587 // CHECK8-NEXT:    store i8 96, i8* [[IT]], align 1
12588 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12589 // CHECK8:       .omp.final.done:
12590 // CHECK8-NEXT:    ret void
12591 //
12592 //
12593 // CHECK8-LABEL: define {{[^@]+}}@_Z3bari
12594 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12595 // CHECK8-NEXT:  entry:
12596 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12597 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
12598 // CHECK8-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
12599 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12600 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
12601 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12602 // CHECK8-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
12603 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12604 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12605 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12606 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12607 // CHECK8-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
12608 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12609 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12610 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
12611 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12612 // CHECK8-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
12613 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12614 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12615 // CHECK8-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12616 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12617 // CHECK8-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
12618 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12619 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12620 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12621 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12622 // CHECK8-NEXT:    ret i32 [[TMP8]]
12623 //
12624 //
12625 // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12626 // CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12627 // CHECK8-NEXT:  entry:
12628 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12629 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12630 // CHECK8-NEXT:    [[B:%.*]] = alloca i32, align 4
12631 // CHECK8-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12632 // CHECK8-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12633 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
12634 // CHECK8-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
12635 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
12636 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 4
12637 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 4
12638 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 4
12639 // CHECK8-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4
12640 // CHECK8-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12641 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12642 // CHECK8-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12643 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12644 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12645 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
12646 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12647 // CHECK8-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
12648 // CHECK8-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
12649 // CHECK8-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
12650 // CHECK8-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
12651 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
12652 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12653 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
12654 // CHECK8-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
12655 // CHECK8-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
12656 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
12657 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[B_CASTED]], align 4
12658 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
12659 // CHECK8-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12660 // CHECK8-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
12661 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
12662 // CHECK8-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
12663 // CHECK8-NEXT:    store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
12664 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
12665 // CHECK8-NEXT:    [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12666 // CHECK8-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1
12667 // CHECK8-NEXT:    br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12668 // CHECK8:       omp_if.then:
12669 // CHECK8-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12670 // CHECK8-NEXT:    [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]]
12671 // CHECK8-NEXT:    [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2
12672 // CHECK8-NEXT:    [[TMP12:%.*]] = sext i32 [[TMP11]] to i64
12673 // CHECK8-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12674 // CHECK8-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to %struct.S1**
12675 // CHECK8-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP14]], align 4
12676 // CHECK8-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12677 // CHECK8-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to double**
12678 // CHECK8-NEXT:    store double* [[A]], double** [[TMP16]], align 4
12679 // CHECK8-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
12680 // CHECK8-NEXT:    store i64 8, i64* [[TMP17]], align 4
12681 // CHECK8-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
12682 // CHECK8-NEXT:    store i8* null, i8** [[TMP18]], align 4
12683 // CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
12684 // CHECK8-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
12685 // CHECK8-NEXT:    store i32 [[TMP6]], i32* [[TMP20]], align 4
12686 // CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
12687 // CHECK8-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
12688 // CHECK8-NEXT:    store i32 [[TMP6]], i32* [[TMP22]], align 4
12689 // CHECK8-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
12690 // CHECK8-NEXT:    store i64 4, i64* [[TMP23]], align 4
12691 // CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
12692 // CHECK8-NEXT:    store i8* null, i8** [[TMP24]], align 4
12693 // CHECK8-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
12694 // CHECK8-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
12695 // CHECK8-NEXT:    store i32 2, i32* [[TMP26]], align 4
12696 // CHECK8-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
12697 // CHECK8-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
12698 // CHECK8-NEXT:    store i32 2, i32* [[TMP28]], align 4
12699 // CHECK8-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
12700 // CHECK8-NEXT:    store i64 4, i64* [[TMP29]], align 4
12701 // CHECK8-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
12702 // CHECK8-NEXT:    store i8* null, i8** [[TMP30]], align 4
12703 // CHECK8-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
12704 // CHECK8-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
12705 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP32]], align 4
12706 // CHECK8-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
12707 // CHECK8-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32*
12708 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP34]], align 4
12709 // CHECK8-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
12710 // CHECK8-NEXT:    store i64 4, i64* [[TMP35]], align 4
12711 // CHECK8-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
12712 // CHECK8-NEXT:    store i8* null, i8** [[TMP36]], align 4
12713 // CHECK8-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
12714 // CHECK8-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i16**
12715 // CHECK8-NEXT:    store i16* [[VLA]], i16** [[TMP38]], align 4
12716 // CHECK8-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
12717 // CHECK8-NEXT:    [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i16**
12718 // CHECK8-NEXT:    store i16* [[VLA]], i16** [[TMP40]], align 4
12719 // CHECK8-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
12720 // CHECK8-NEXT:    store i64 [[TMP12]], i64* [[TMP41]], align 4
12721 // CHECK8-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
12722 // CHECK8-NEXT:    store i8* null, i8** [[TMP42]], align 4
12723 // CHECK8-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
12724 // CHECK8-NEXT:    [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
12725 // CHECK8-NEXT:    store i32 [[TMP8]], i32* [[TMP44]], align 4
12726 // CHECK8-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
12727 // CHECK8-NEXT:    [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
12728 // CHECK8-NEXT:    store i32 [[TMP8]], i32* [[TMP46]], align 4
12729 // CHECK8-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
12730 // CHECK8-NEXT:    store i64 1, i64* [[TMP47]], align 4
12731 // CHECK8-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
12732 // CHECK8-NEXT:    store i8* null, i8** [[TMP48]], align 4
12733 // CHECK8-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12734 // CHECK8-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12735 // CHECK8-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
12736 // CHECK8-NEXT:    [[TMP52:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12737 // CHECK8-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP52]] to i1
12738 // CHECK8-NEXT:    [[TMP53:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1
12739 // CHECK8-NEXT:    [[TMP54:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, i32 6, i8** [[TMP49]], i8** [[TMP50]], i64* [[TMP51]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP53]])
12740 // CHECK8-NEXT:    [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0
12741 // CHECK8-NEXT:    br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
12742 // CHECK8:       omp_offload.failed:
12743 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
12744 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]
12745 // CHECK8:       omp_offload.cont:
12746 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
12747 // CHECK8:       omp_if.else:
12748 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
12749 // CHECK8-NEXT:    br label [[OMP_IF_END]]
12750 // CHECK8:       omp_if.end:
12751 // CHECK8-NEXT:    [[TMP56:%.*]] = mul nsw i32 1, [[TMP1]]
12752 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP56]]
12753 // CHECK8-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
12754 // CHECK8-NEXT:    [[TMP57:%.*]] = load i16, i16* [[ARRAYIDX5]], align 2
12755 // CHECK8-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP57]] to i32
12756 // CHECK8-NEXT:    [[TMP58:%.*]] = load i32, i32* [[B]], align 4
12757 // CHECK8-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], [[TMP58]]
12758 // CHECK8-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12759 // CHECK8-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
12760 // CHECK8-NEXT:    ret i32 [[ADD7]]
12761 //
12762 //
12763 // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici
12764 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12765 // CHECK8-NEXT:  entry:
12766 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12767 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
12768 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
12769 // CHECK8-NEXT:    [[AAA:%.*]] = alloca i8, align 1
12770 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12771 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12772 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12773 // CHECK8-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
12774 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
12775 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
12776 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
12777 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12778 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
12779 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
12780 // CHECK8-NEXT:    store i8 0, i8* [[AAA]], align 1
12781 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12782 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
12783 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
12784 // CHECK8-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12785 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12786 // CHECK8-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
12787 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12788 // CHECK8-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
12789 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
12790 // CHECK8-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
12791 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
12792 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12793 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
12794 // CHECK8-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12795 // CHECK8:       omp_if.then:
12796 // CHECK8-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12797 // CHECK8-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
12798 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
12799 // CHECK8-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12800 // CHECK8-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
12801 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
12802 // CHECK8-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
12803 // CHECK8-NEXT:    store i8* null, i8** [[TMP11]], align 4
12804 // CHECK8-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
12805 // CHECK8-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
12806 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
12807 // CHECK8-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
12808 // CHECK8-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
12809 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
12810 // CHECK8-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
12811 // CHECK8-NEXT:    store i8* null, i8** [[TMP16]], align 4
12812 // CHECK8-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
12813 // CHECK8-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
12814 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
12815 // CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
12816 // CHECK8-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
12817 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
12818 // CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
12819 // CHECK8-NEXT:    store i8* null, i8** [[TMP21]], align 4
12820 // CHECK8-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
12821 // CHECK8-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
12822 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
12823 // CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
12824 // CHECK8-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
12825 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
12826 // CHECK8-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
12827 // CHECK8-NEXT:    store i8* null, i8** [[TMP26]], align 4
12828 // CHECK8-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12829 // CHECK8-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12830 // CHECK8-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
12831 // CHECK8-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
12832 // CHECK8-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
12833 // CHECK8:       omp_offload.failed:
12834 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
12835 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]
12836 // CHECK8:       omp_offload.cont:
12837 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
12838 // CHECK8:       omp_if.else:
12839 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
12840 // CHECK8-NEXT:    br label [[OMP_IF_END]]
12841 // CHECK8:       omp_if.end:
12842 // CHECK8-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
12843 // CHECK8-NEXT:    ret i32 [[TMP31]]
12844 //
12845 //
12846 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12847 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
12848 // CHECK8-NEXT:  entry:
12849 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12850 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
12851 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
12852 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12853 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12854 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12855 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
12856 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
12857 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
12858 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12859 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
12860 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
12861 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12862 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
12863 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
12864 // CHECK8-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12865 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12866 // CHECK8-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
12867 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12868 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12869 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
12870 // CHECK8-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12871 // CHECK8:       omp_if.then:
12872 // CHECK8-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12873 // CHECK8-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
12874 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
12875 // CHECK8-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12876 // CHECK8-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
12877 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
12878 // CHECK8-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
12879 // CHECK8-NEXT:    store i8* null, i8** [[TMP9]], align 4
12880 // CHECK8-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
12881 // CHECK8-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
12882 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
12883 // CHECK8-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
12884 // CHECK8-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
12885 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
12886 // CHECK8-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
12887 // CHECK8-NEXT:    store i8* null, i8** [[TMP14]], align 4
12888 // CHECK8-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
12889 // CHECK8-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
12890 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
12891 // CHECK8-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
12892 // CHECK8-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
12893 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
12894 // CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
12895 // CHECK8-NEXT:    store i8* null, i8** [[TMP19]], align 4
12896 // CHECK8-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12897 // CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12898 // CHECK8-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
12899 // CHECK8-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
12900 // CHECK8-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
12901 // CHECK8:       omp_offload.failed:
12902 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
12903 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]
12904 // CHECK8:       omp_offload.cont:
12905 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
12906 // CHECK8:       omp_if.else:
12907 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
12908 // CHECK8-NEXT:    br label [[OMP_IF_END]]
12909 // CHECK8:       omp_if.end:
12910 // CHECK8-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
12911 // CHECK8-NEXT:    ret i32 [[TMP24]]
12912 //
12913 //
12914 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
12915 // CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
12916 // CHECK8-NEXT:  entry:
12917 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12918 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
12919 // CHECK8-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12920 // CHECK8-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12921 // CHECK8-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
12922 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12923 // CHECK8-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
12924 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
12925 // CHECK8-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
12926 // CHECK8-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
12927 // CHECK8-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
12928 // CHECK8-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
12929 // CHECK8-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12930 // CHECK8-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
12931 // CHECK8-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12932 // CHECK8-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
12933 // CHECK8-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
12934 // CHECK8-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12935 // CHECK8-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12936 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12937 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
12938 // CHECK8-NEXT:    [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
12939 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
12940 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
12941 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[B_CASTED]], align 4
12942 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
12943 // CHECK8-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
12944 // CHECK8-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
12945 // CHECK8-NEXT:    [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
12946 // CHECK8-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
12947 // CHECK8-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
12948 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
12949 // CHECK8-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
12950 // CHECK8-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
12951 // CHECK8-NEXT:    br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12952 // CHECK8:       omp_if.then:
12953 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
12954 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
12955 // CHECK8:       omp_if.else:
12956 // CHECK8-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
12957 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
12958 // CHECK8-NEXT:    call void @.omp_outlined..9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR4]]
12959 // CHECK8-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
12960 // CHECK8-NEXT:    br label [[OMP_IF_END]]
12961 // CHECK8:       omp_if.end:
12962 // CHECK8-NEXT:    ret void
12963 //
12964 //
12965 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9
12966 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
12967 // CHECK8-NEXT:  entry:
12968 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12969 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12970 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12971 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
12972 // CHECK8-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12973 // CHECK8-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12974 // CHECK8-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
12975 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12976 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
12977 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i64, align 4
12978 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
12979 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
12980 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
12981 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12982 // CHECK8-NEXT:    [[IT:%.*]] = alloca i64, align 8
12983 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12984 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12985 // CHECK8-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12986 // CHECK8-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
12987 // CHECK8-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12988 // CHECK8-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
12989 // CHECK8-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
12990 // CHECK8-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12991 // CHECK8-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12992 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12993 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
12994 // CHECK8-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
12995 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
12996 // CHECK8-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
12997 // CHECK8-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
12998 // CHECK8-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
12999 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13000 // CHECK8-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
13001 // CHECK8-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
13002 // CHECK8-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
13003 // CHECK8:       omp_if.then:
13004 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13005 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
13006 // CHECK8-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
13007 // CHECK8-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
13008 // CHECK8-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
13009 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13010 // CHECK8:       cond.true:
13011 // CHECK8-NEXT:    br label [[COND_END:%.*]]
13012 // CHECK8:       cond.false:
13013 // CHECK8-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
13014 // CHECK8-NEXT:    br label [[COND_END]]
13015 // CHECK8:       cond.end:
13016 // CHECK8-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
13017 // CHECK8-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
13018 // CHECK8-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
13019 // CHECK8-NEXT:    store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
13020 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13021 // CHECK8:       omp.inner.for.cond:
13022 // CHECK8-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
13023 // CHECK8-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !39
13024 // CHECK8-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
13025 // CHECK8-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13026 // CHECK8:       omp.inner.for.body:
13027 // CHECK8-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
13028 // CHECK8-NEXT:    [[MUL:%.*]] = mul i64 [[TMP12]], 400
13029 // CHECK8-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
13030 // CHECK8-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !39
13031 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
13032 // CHECK8-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
13033 // CHECK8-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
13034 // CHECK8-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
13035 // CHECK8-NEXT:    store double [[ADD]], double* [[A]], align 4, !nontemporal !40, !llvm.access.group !39
13036 // CHECK8-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13037 // CHECK8-NEXT:    [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !40, !llvm.access.group !39
13038 // CHECK8-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
13039 // CHECK8-NEXT:    store double [[INC]], double* [[A5]], align 4, !nontemporal !40, !llvm.access.group !39
13040 // CHECK8-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
13041 // CHECK8-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
13042 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
13043 // CHECK8-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
13044 // CHECK8-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !39
13045 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13046 // CHECK8:       omp.body.continue:
13047 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13048 // CHECK8:       omp.inner.for.inc:
13049 // CHECK8-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
13050 // CHECK8-NEXT:    [[ADD8:%.*]] = add i64 [[TMP16]], 1
13051 // CHECK8-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39
13052 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
13053 // CHECK8:       omp.inner.for.end:
13054 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
13055 // CHECK8:       omp_if.else:
13056 // CHECK8-NEXT:    [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13057 // CHECK8-NEXT:    [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
13058 // CHECK8-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
13059 // CHECK8-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
13060 // CHECK8-NEXT:    [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3
13061 // CHECK8-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
13062 // CHECK8:       cond.true10:
13063 // CHECK8-NEXT:    br label [[COND_END12:%.*]]
13064 // CHECK8:       cond.false11:
13065 // CHECK8-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
13066 // CHECK8-NEXT:    br label [[COND_END12]]
13067 // CHECK8:       cond.end12:
13068 // CHECK8-NEXT:    [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ]
13069 // CHECK8-NEXT:    store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8
13070 // CHECK8-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
13071 // CHECK8-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
13072 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND14:%.*]]
13073 // CHECK8:       omp.inner.for.cond14:
13074 // CHECK8-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
13075 // CHECK8-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
13076 // CHECK8-NEXT:    [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
13077 // CHECK8-NEXT:    br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]]
13078 // CHECK8:       omp.inner.for.body16:
13079 // CHECK8-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
13080 // CHECK8-NEXT:    [[MUL17:%.*]] = mul i64 [[TMP24]], 400
13081 // CHECK8-NEXT:    [[SUB18:%.*]] = sub i64 2000, [[MUL17]]
13082 // CHECK8-NEXT:    store i64 [[SUB18]], i64* [[IT]], align 8
13083 // CHECK8-NEXT:    [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4
13084 // CHECK8-NEXT:    [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double
13085 // CHECK8-NEXT:    [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00
13086 // CHECK8-NEXT:    [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13087 // CHECK8-NEXT:    store double [[ADD20]], double* [[A21]], align 4
13088 // CHECK8-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13089 // CHECK8-NEXT:    [[TMP26:%.*]] = load double, double* [[A22]], align 4
13090 // CHECK8-NEXT:    [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00
13091 // CHECK8-NEXT:    store double [[INC23]], double* [[A22]], align 4
13092 // CHECK8-NEXT:    [[CONV24:%.*]] = fptosi double [[INC23]] to i16
13093 // CHECK8-NEXT:    [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]]
13094 // CHECK8-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]]
13095 // CHECK8-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
13096 // CHECK8-NEXT:    store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2
13097 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE27:%.*]]
13098 // CHECK8:       omp.body.continue27:
13099 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC28:%.*]]
13100 // CHECK8:       omp.inner.for.inc28:
13101 // CHECK8-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
13102 // CHECK8-NEXT:    [[ADD29:%.*]] = add i64 [[TMP28]], 1
13103 // CHECK8-NEXT:    store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8
13104 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP43:![0-9]+]]
13105 // CHECK8:       omp.inner.for.end30:
13106 // CHECK8-NEXT:    br label [[OMP_IF_END]]
13107 // CHECK8:       omp_if.end:
13108 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13109 // CHECK8:       omp.loop.exit:
13110 // CHECK8-NEXT:    [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13111 // CHECK8-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
13112 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
13113 // CHECK8-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13114 // CHECK8-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
13115 // CHECK8-NEXT:    br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13116 // CHECK8:       .omp.final.then:
13117 // CHECK8-NEXT:    store i64 400, i64* [[IT]], align 8
13118 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13119 // CHECK8:       .omp.final.done:
13120 // CHECK8-NEXT:    ret void
13121 //
13122 //
13123 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
13124 // CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
13125 // CHECK8-NEXT:  entry:
13126 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13127 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13128 // CHECK8-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
13129 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13130 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13131 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13132 // CHECK8-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
13133 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13134 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13135 // CHECK8-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
13136 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13137 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13138 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
13139 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13140 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13141 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
13142 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
13143 // CHECK8-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
13144 // CHECK8-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13145 // CHECK8-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
13146 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13147 // CHECK8-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
13148 // CHECK8-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
13149 // CHECK8-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
13150 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
13151 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
13152 // CHECK8-NEXT:    ret void
13153 //
13154 //
13155 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11
13156 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
13157 // CHECK8-NEXT:  entry:
13158 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13159 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13160 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13161 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13162 // CHECK8-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
13163 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13164 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13165 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13166 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13167 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13168 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13169 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13170 // CHECK8-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
13171 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13172 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13173 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
13174 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13175 // CHECK8-NEXT:    ret void
13176 //
13177 //
13178 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
13179 // CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
13180 // CHECK8-NEXT:  entry:
13181 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13182 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13183 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13184 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13185 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13186 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13187 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13188 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13189 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13190 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13191 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13192 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
13193 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
13194 // CHECK8-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
13195 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13196 // CHECK8-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
13197 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13198 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
13199 // CHECK8-NEXT:    ret void
13200 //
13201 //
13202 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14
13203 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
13204 // CHECK8-NEXT:  entry:
13205 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13206 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13207 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13208 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13209 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13210 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
13211 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i64, align 4
13212 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
13213 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
13214 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
13215 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13216 // CHECK8-NEXT:    [[I:%.*]] = alloca i64, align 8
13217 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13218 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13219 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13220 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13221 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13222 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13223 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13224 // CHECK8-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
13225 // CHECK8-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
13226 // CHECK8-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
13227 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13228 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13229 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
13230 // CHECK8-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
13231 // CHECK8-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
13232 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
13233 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13234 // CHECK8:       cond.true:
13235 // CHECK8-NEXT:    br label [[COND_END:%.*]]
13236 // CHECK8:       cond.false:
13237 // CHECK8-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
13238 // CHECK8-NEXT:    br label [[COND_END]]
13239 // CHECK8:       cond.end:
13240 // CHECK8-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
13241 // CHECK8-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
13242 // CHECK8-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
13243 // CHECK8-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
13244 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13245 // CHECK8:       omp.inner.for.cond:
13246 // CHECK8-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
13247 // CHECK8-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !45
13248 // CHECK8-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
13249 // CHECK8-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13250 // CHECK8:       omp.inner.for.body:
13251 // CHECK8-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
13252 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
13253 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
13254 // CHECK8-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !45
13255 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
13256 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
13257 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
13258 // CHECK8-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !45
13259 // CHECK8-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
13260 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
13261 // CHECK8-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
13262 // CHECK8-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !45
13263 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
13264 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
13265 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
13266 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
13267 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13268 // CHECK8:       omp.body.continue:
13269 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13270 // CHECK8:       omp.inner.for.inc:
13271 // CHECK8-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
13272 // CHECK8-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
13273 // CHECK8-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45
13274 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
13275 // CHECK8:       omp.inner.for.end:
13276 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13277 // CHECK8:       omp.loop.exit:
13278 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
13279 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13280 // CHECK8-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
13281 // CHECK8-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13282 // CHECK8:       .omp.final.then:
13283 // CHECK8-NEXT:    store i64 11, i64* [[I]], align 8
13284 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13285 // CHECK8:       .omp.final.done:
13286 // CHECK8-NEXT:    ret void
13287 //
13288 //
13289 // CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
13290 // CHECK8-SAME: () #[[ATTR7:[0-9]+]] {
13291 // CHECK8-NEXT:  entry:
13292 // CHECK8-NEXT:    call void @__tgt_register_requires(i64 1)
13293 // CHECK8-NEXT:    ret void
13294 //
13295 //
13296 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv
13297 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
13298 // CHECK9-NEXT:  entry:
13299 // CHECK9-NEXT:    ret i64 0
13300 //
13301 //
13302 // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi
13303 // CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
13304 // CHECK9-NEXT:  entry:
13305 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13306 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
13307 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
13308 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
13309 // CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
13310 // CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
13311 // CHECK9-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
13312 // CHECK9-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
13313 // CHECK9-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
13314 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13315 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13316 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13317 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13318 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
13319 // CHECK9-NEXT:    [[K:%.*]] = alloca i64, align 8
13320 // CHECK9-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
13321 // CHECK9-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
13322 // CHECK9-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
13323 // CHECK9-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
13324 // CHECK9-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
13325 // CHECK9-NEXT:    [[I7:%.*]] = alloca i32, align 4
13326 // CHECK9-NEXT:    [[K8:%.*]] = alloca i64, align 8
13327 // CHECK9-NEXT:    [[LIN:%.*]] = alloca i32, align 4
13328 // CHECK9-NEXT:    [[_TMP21:%.*]] = alloca i64, align 8
13329 // CHECK9-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
13330 // CHECK9-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
13331 // CHECK9-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
13332 // CHECK9-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
13333 // CHECK9-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
13334 // CHECK9-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
13335 // CHECK9-NEXT:    [[IT:%.*]] = alloca i64, align 8
13336 // CHECK9-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
13337 // CHECK9-NEXT:    [[A29:%.*]] = alloca i32, align 4
13338 // CHECK9-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
13339 // CHECK9-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
13340 // CHECK9-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
13341 // CHECK9-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
13342 // CHECK9-NEXT:    [[IT62:%.*]] = alloca i16, align 2
13343 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
13344 // CHECK9-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
13345 // CHECK9-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
13346 // CHECK9-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
13347 // CHECK9-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
13348 // CHECK9-NEXT:    [[IT81:%.*]] = alloca i8, align 1
13349 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13350 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
13351 // CHECK9-NEXT:    store i16 0, i16* [[AA]], align 2
13352 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
13353 // CHECK9-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
13354 // CHECK9-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
13355 // CHECK9-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
13356 // CHECK9-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
13357 // CHECK9-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
13358 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
13359 // CHECK9-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
13360 // CHECK9-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
13361 // CHECK9-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
13362 // CHECK9-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
13363 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13364 // CHECK9-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
13365 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13366 // CHECK9-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
13367 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13368 // CHECK9:       omp.inner.for.cond:
13369 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
13370 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
13371 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
13372 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13373 // CHECK9:       omp.inner.for.body:
13374 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
13375 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
13376 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
13377 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
13378 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13379 // CHECK9:       omp.body.continue:
13380 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13381 // CHECK9:       omp.inner.for.inc:
13382 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
13383 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
13384 // CHECK9-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
13385 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
13386 // CHECK9:       omp.inner.for.end:
13387 // CHECK9-NEXT:    store i32 33, i32* [[I]], align 4
13388 // CHECK9-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
13389 // CHECK9-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
13390 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
13391 // CHECK9-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
13392 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
13393 // CHECK9-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
13394 // CHECK9-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K]], align 8
13395 // CHECK9-NEXT:    store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
13396 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
13397 // CHECK9:       omp.inner.for.cond9:
13398 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
13399 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
13400 // CHECK9-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
13401 // CHECK9-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
13402 // CHECK9:       omp.inner.for.body11:
13403 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
13404 // CHECK9-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
13405 // CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
13406 // CHECK9-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
13407 // CHECK9-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
13408 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
13409 // CHECK9-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
13410 // CHECK9-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
13411 // CHECK9-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
13412 // CHECK9-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
13413 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
13414 // CHECK9-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
13415 // CHECK9-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
13416 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
13417 // CHECK9:       omp.body.continue16:
13418 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
13419 // CHECK9:       omp.inner.for.inc17:
13420 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
13421 // CHECK9-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
13422 // CHECK9-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
13423 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
13424 // CHECK9:       omp.inner.for.end19:
13425 // CHECK9-NEXT:    store i32 1, i32* [[I7]], align 4
13426 // CHECK9-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
13427 // CHECK9-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
13428 // CHECK9-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
13429 // CHECK9-NEXT:    store i32 12, i32* [[LIN]], align 4
13430 // CHECK9-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
13431 // CHECK9-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
13432 // CHECK9-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
13433 // CHECK9-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
13434 // CHECK9-NEXT:    [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
13435 // CHECK9-NEXT:    store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
13436 // CHECK9-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A]], align 4
13437 // CHECK9-NEXT:    store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
13438 // CHECK9-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
13439 // CHECK9-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
13440 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
13441 // CHECK9:       omp.inner.for.cond30:
13442 // CHECK9-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13443 // CHECK9-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
13444 // CHECK9-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
13445 // CHECK9-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
13446 // CHECK9:       omp.inner.for.body32:
13447 // CHECK9-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13448 // CHECK9-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP26]], 400
13449 // CHECK9-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
13450 // CHECK9-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
13451 // CHECK9-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
13452 // CHECK9-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
13453 // CHECK9-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13454 // CHECK9-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
13455 // CHECK9-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
13456 // CHECK9-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
13457 // CHECK9-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
13458 // CHECK9-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
13459 // CHECK9-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
13460 // CHECK9-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
13461 // CHECK9-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13462 // CHECK9-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
13463 // CHECK9-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
13464 // CHECK9-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
13465 // CHECK9-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
13466 // CHECK9-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
13467 // CHECK9-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
13468 // CHECK9-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
13469 // CHECK9-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
13470 // CHECK9-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
13471 // CHECK9-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
13472 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
13473 // CHECK9:       omp.body.continue46:
13474 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
13475 // CHECK9:       omp.inner.for.inc47:
13476 // CHECK9-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13477 // CHECK9-NEXT:    [[ADD48:%.*]] = add i64 [[TMP34]], 1
13478 // CHECK9-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13479 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
13480 // CHECK9:       omp.inner.for.end49:
13481 // CHECK9-NEXT:    store i64 400, i64* [[IT]], align 8
13482 // CHECK9-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
13483 // CHECK9-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
13484 // CHECK9-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
13485 // CHECK9-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP36]]
13486 // CHECK9-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
13487 // CHECK9-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
13488 // CHECK9-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
13489 // CHECK9-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
13490 // CHECK9-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
13491 // CHECK9-NEXT:    [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
13492 // CHECK9-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP38]]
13493 // CHECK9-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
13494 // CHECK9-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
13495 // CHECK9-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
13496 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
13497 // CHECK9-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
13498 // CHECK9-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
13499 // CHECK9-NEXT:    store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
13500 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
13501 // CHECK9:       omp.inner.for.cond63:
13502 // CHECK9-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
13503 // CHECK9-NEXT:    [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
13504 // CHECK9-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
13505 // CHECK9-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
13506 // CHECK9:       omp.inner.for.body65:
13507 // CHECK9-NEXT:    [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
13508 // CHECK9-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
13509 // CHECK9-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
13510 // CHECK9-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
13511 // CHECK9-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
13512 // CHECK9-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
13513 // CHECK9-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
13514 // CHECK9-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
13515 // CHECK9-NEXT:    [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
13516 // CHECK9-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
13517 // CHECK9-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
13518 // CHECK9-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
13519 // CHECK9-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
13520 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
13521 // CHECK9:       omp.body.continue73:
13522 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
13523 // CHECK9:       omp.inner.for.inc74:
13524 // CHECK9-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
13525 // CHECK9-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
13526 // CHECK9-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
13527 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
13528 // CHECK9:       omp.inner.for.end76:
13529 // CHECK9-NEXT:    store i16 22, i16* [[IT62]], align 2
13530 // CHECK9-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
13531 // CHECK9-NEXT:    store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
13532 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
13533 // CHECK9-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
13534 // CHECK9-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
13535 // CHECK9-NEXT:    store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
13536 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
13537 // CHECK9:       omp.inner.for.cond82:
13538 // CHECK9-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
13539 // CHECK9-NEXT:    [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
13540 // CHECK9-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
13541 // CHECK9-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
13542 // CHECK9:       omp.inner.for.body84:
13543 // CHECK9-NEXT:    [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
13544 // CHECK9-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
13545 // CHECK9-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
13546 // CHECK9-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
13547 // CHECK9-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
13548 // CHECK9-NEXT:    [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
13549 // CHECK9-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
13550 // CHECK9-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
13551 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
13552 // CHECK9-NEXT:    [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
13553 // CHECK9-NEXT:    [[CONV89:%.*]] = fpext float [[TMP52]] to double
13554 // CHECK9-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
13555 // CHECK9-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
13556 // CHECK9-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
13557 // CHECK9-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
13558 // CHECK9-NEXT:    [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
13559 // CHECK9-NEXT:    [[CONV93:%.*]] = fpext float [[TMP53]] to double
13560 // CHECK9-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
13561 // CHECK9-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
13562 // CHECK9-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
13563 // CHECK9-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
13564 // CHECK9-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
13565 // CHECK9-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
13566 // CHECK9-NEXT:    [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
13567 // CHECK9-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
13568 // CHECK9-NEXT:    [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
13569 // CHECK9-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
13570 // CHECK9-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
13571 // CHECK9-NEXT:    [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
13572 // CHECK9-NEXT:    [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
13573 // CHECK9-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
13574 // CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
13575 // CHECK9-NEXT:    [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
13576 // CHECK9-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
13577 // CHECK9-NEXT:    store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
13578 // CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
13579 // CHECK9-NEXT:    [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
13580 // CHECK9-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
13581 // CHECK9-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
13582 // CHECK9-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
13583 // CHECK9-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
13584 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
13585 // CHECK9:       omp.body.continue106:
13586 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
13587 // CHECK9:       omp.inner.for.inc107:
13588 // CHECK9-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
13589 // CHECK9-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
13590 // CHECK9-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
13591 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
13592 // CHECK9:       omp.inner.for.end109:
13593 // CHECK9-NEXT:    store i8 96, i8* [[IT81]], align 1
13594 // CHECK9-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
13595 // CHECK9-NEXT:    [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
13596 // CHECK9-NEXT:    call void @llvm.stackrestore(i8* [[TMP61]])
13597 // CHECK9-NEXT:    ret i32 [[TMP60]]
13598 //
13599 //
13600 // CHECK9-LABEL: define {{[^@]+}}@_Z3bari
13601 // CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
13602 // CHECK9-NEXT:  entry:
13603 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13604 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
13605 // CHECK9-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
13606 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13607 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
13608 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
13609 // CHECK9-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
13610 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
13611 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
13612 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
13613 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
13614 // CHECK9-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
13615 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
13616 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
13617 // CHECK9-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
13618 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
13619 // CHECK9-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
13620 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
13621 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
13622 // CHECK9-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
13623 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
13624 // CHECK9-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
13625 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
13626 // CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
13627 // CHECK9-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
13628 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
13629 // CHECK9-NEXT:    ret i32 [[TMP8]]
13630 //
13631 //
13632 // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
13633 // CHECK9-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
13634 // CHECK9-NEXT:  entry:
13635 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
13636 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13637 // CHECK9-NEXT:    [[B:%.*]] = alloca i32, align 4
13638 // CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
13639 // CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
13640 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i64, align 8
13641 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
13642 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
13643 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
13644 // CHECK9-NEXT:    [[IT:%.*]] = alloca i64, align 8
13645 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
13646 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13647 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
13648 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
13649 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
13650 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
13651 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
13652 // CHECK9-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
13653 // CHECK9-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
13654 // CHECK9-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
13655 // CHECK9-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
13656 // CHECK9-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
13657 // CHECK9-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
13658 // CHECK9-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
13659 // CHECK9-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
13660 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
13661 // CHECK9-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
13662 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13663 // CHECK9:       omp.inner.for.cond:
13664 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
13665 // CHECK9-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
13666 // CHECK9-NEXT:    [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]]
13667 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13668 // CHECK9:       omp.inner.for.body:
13669 // CHECK9-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
13670 // CHECK9-NEXT:    [[MUL:%.*]] = mul i64 [[TMP8]], 400
13671 // CHECK9-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
13672 // CHECK9-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
13673 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
13674 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
13675 // CHECK9-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
13676 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
13677 // CHECK9-NEXT:    store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18
13678 // CHECK9-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
13679 // CHECK9-NEXT:    [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18
13680 // CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
13681 // CHECK9-NEXT:    store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18
13682 // CHECK9-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
13683 // CHECK9-NEXT:    [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
13684 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
13685 // CHECK9-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
13686 // CHECK9-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18
13687 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13688 // CHECK9:       omp.body.continue:
13689 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13690 // CHECK9:       omp.inner.for.inc:
13691 // CHECK9-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
13692 // CHECK9-NEXT:    [[ADD6:%.*]] = add i64 [[TMP12]], 1
13693 // CHECK9-NEXT:    store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
13694 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
13695 // CHECK9:       omp.inner.for.end:
13696 // CHECK9-NEXT:    store i64 400, i64* [[IT]], align 8
13697 // CHECK9-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
13698 // CHECK9-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
13699 // CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
13700 // CHECK9-NEXT:    [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
13701 // CHECK9-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP14]] to i32
13702 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[B]], align 4
13703 // CHECK9-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]]
13704 // CHECK9-NEXT:    [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
13705 // CHECK9-NEXT:    call void @llvm.stackrestore(i8* [[TMP16]])
13706 // CHECK9-NEXT:    ret i32 [[ADD10]]
13707 //
13708 //
13709 // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici
13710 // CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
13711 // CHECK9-NEXT:  entry:
13712 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13713 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
13714 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
13715 // CHECK9-NEXT:    [[AAA:%.*]] = alloca i8, align 1
13716 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
13717 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13718 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13719 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13720 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13721 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
13722 // CHECK9-NEXT:    store i16 0, i16* [[AA]], align 2
13723 // CHECK9-NEXT:    store i8 0, i8* [[AAA]], align 1
13724 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13725 // CHECK9-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
13726 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
13727 // CHECK9-NEXT:    ret i32 [[TMP0]]
13728 //
13729 //
13730 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
13731 // CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
13732 // CHECK9-NEXT:  entry:
13733 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13734 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
13735 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
13736 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
13737 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i64, align 8
13738 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
13739 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
13740 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
13741 // CHECK9-NEXT:    [[I:%.*]] = alloca i64, align 8
13742 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13743 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
13744 // CHECK9-NEXT:    store i16 0, i16* [[AA]], align 2
13745 // CHECK9-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
13746 // CHECK9-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
13747 // CHECK9-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
13748 // CHECK9-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
13749 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13750 // CHECK9:       omp.inner.for.cond:
13751 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
13752 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21
13753 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
13754 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13755 // CHECK9:       omp.inner.for.body:
13756 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
13757 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
13758 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
13759 // CHECK9-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21
13760 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
13761 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
13762 // CHECK9-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21
13763 // CHECK9-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
13764 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
13765 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
13766 // CHECK9-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
13767 // CHECK9-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21
13768 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
13769 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
13770 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
13771 // CHECK9-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
13772 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13773 // CHECK9:       omp.body.continue:
13774 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13775 // CHECK9:       omp.inner.for.inc:
13776 // CHECK9-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
13777 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
13778 // CHECK9-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
13779 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
13780 // CHECK9:       omp.inner.for.end:
13781 // CHECK9-NEXT:    store i64 11, i64* [[I]], align 8
13782 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
13783 // CHECK9-NEXT:    ret i32 [[TMP8]]
13784 //
13785 //
13786 // CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv
13787 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
13788 // CHECK10-NEXT:  entry:
13789 // CHECK10-NEXT:    ret i64 0
13790 //
13791 //
13792 // CHECK10-LABEL: define {{[^@]+}}@_Z3fooi
13793 // CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
13794 // CHECK10-NEXT:  entry:
13795 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13796 // CHECK10-NEXT:    [[A:%.*]] = alloca i32, align 4
13797 // CHECK10-NEXT:    [[AA:%.*]] = alloca i16, align 2
13798 // CHECK10-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
13799 // CHECK10-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
13800 // CHECK10-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
13801 // CHECK10-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
13802 // CHECK10-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
13803 // CHECK10-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
13804 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13805 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13806 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13807 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13808 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
13809 // CHECK10-NEXT:    [[K:%.*]] = alloca i64, align 8
13810 // CHECK10-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
13811 // CHECK10-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
13812 // CHECK10-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
13813 // CHECK10-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
13814 // CHECK10-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
13815 // CHECK10-NEXT:    [[I7:%.*]] = alloca i32, align 4
13816 // CHECK10-NEXT:    [[K8:%.*]] = alloca i64, align 8
13817 // CHECK10-NEXT:    [[LIN:%.*]] = alloca i32, align 4
13818 // CHECK10-NEXT:    [[_TMP21:%.*]] = alloca i64, align 8
13819 // CHECK10-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
13820 // CHECK10-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
13821 // CHECK10-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
13822 // CHECK10-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
13823 // CHECK10-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
13824 // CHECK10-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
13825 // CHECK10-NEXT:    [[IT:%.*]] = alloca i64, align 8
13826 // CHECK10-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
13827 // CHECK10-NEXT:    [[A29:%.*]] = alloca i32, align 4
13828 // CHECK10-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
13829 // CHECK10-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
13830 // CHECK10-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
13831 // CHECK10-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
13832 // CHECK10-NEXT:    [[IT62:%.*]] = alloca i16, align 2
13833 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
13834 // CHECK10-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
13835 // CHECK10-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
13836 // CHECK10-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
13837 // CHECK10-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
13838 // CHECK10-NEXT:    [[IT81:%.*]] = alloca i8, align 1
13839 // CHECK10-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13840 // CHECK10-NEXT:    store i32 0, i32* [[A]], align 4
13841 // CHECK10-NEXT:    store i16 0, i16* [[AA]], align 2
13842 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
13843 // CHECK10-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
13844 // CHECK10-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
13845 // CHECK10-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
13846 // CHECK10-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
13847 // CHECK10-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
13848 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
13849 // CHECK10-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
13850 // CHECK10-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
13851 // CHECK10-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
13852 // CHECK10-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
13853 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13854 // CHECK10-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
13855 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13856 // CHECK10-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
13857 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13858 // CHECK10:       omp.inner.for.cond:
13859 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
13860 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
13861 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
13862 // CHECK10-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13863 // CHECK10:       omp.inner.for.body:
13864 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
13865 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
13866 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
13867 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
13868 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13869 // CHECK10:       omp.body.continue:
13870 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13871 // CHECK10:       omp.inner.for.inc:
13872 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
13873 // CHECK10-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
13874 // CHECK10-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
13875 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
13876 // CHECK10:       omp.inner.for.end:
13877 // CHECK10-NEXT:    store i32 33, i32* [[I]], align 4
13878 // CHECK10-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
13879 // CHECK10-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
13880 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
13881 // CHECK10-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
13882 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
13883 // CHECK10-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
13884 // CHECK10-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K]], align 8
13885 // CHECK10-NEXT:    store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
13886 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
13887 // CHECK10:       omp.inner.for.cond9:
13888 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
13889 // CHECK10-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
13890 // CHECK10-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
13891 // CHECK10-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
13892 // CHECK10:       omp.inner.for.body11:
13893 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
13894 // CHECK10-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
13895 // CHECK10-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
13896 // CHECK10-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
13897 // CHECK10-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
13898 // CHECK10-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
13899 // CHECK10-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
13900 // CHECK10-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
13901 // CHECK10-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
13902 // CHECK10-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
13903 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
13904 // CHECK10-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
13905 // CHECK10-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
13906 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
13907 // CHECK10:       omp.body.continue16:
13908 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
13909 // CHECK10:       omp.inner.for.inc17:
13910 // CHECK10-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
13911 // CHECK10-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
13912 // CHECK10-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
13913 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
13914 // CHECK10:       omp.inner.for.end19:
13915 // CHECK10-NEXT:    store i32 1, i32* [[I7]], align 4
13916 // CHECK10-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
13917 // CHECK10-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
13918 // CHECK10-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
13919 // CHECK10-NEXT:    store i32 12, i32* [[LIN]], align 4
13920 // CHECK10-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
13921 // CHECK10-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
13922 // CHECK10-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
13923 // CHECK10-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
13924 // CHECK10-NEXT:    [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
13925 // CHECK10-NEXT:    store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
13926 // CHECK10-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A]], align 4
13927 // CHECK10-NEXT:    store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
13928 // CHECK10-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
13929 // CHECK10-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
13930 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
13931 // CHECK10:       omp.inner.for.cond30:
13932 // CHECK10-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13933 // CHECK10-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
13934 // CHECK10-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
13935 // CHECK10-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
13936 // CHECK10:       omp.inner.for.body32:
13937 // CHECK10-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13938 // CHECK10-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP26]], 400
13939 // CHECK10-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
13940 // CHECK10-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
13941 // CHECK10-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
13942 // CHECK10-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
13943 // CHECK10-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13944 // CHECK10-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
13945 // CHECK10-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
13946 // CHECK10-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
13947 // CHECK10-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
13948 // CHECK10-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
13949 // CHECK10-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
13950 // CHECK10-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
13951 // CHECK10-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13952 // CHECK10-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
13953 // CHECK10-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
13954 // CHECK10-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
13955 // CHECK10-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
13956 // CHECK10-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
13957 // CHECK10-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
13958 // CHECK10-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
13959 // CHECK10-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
13960 // CHECK10-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
13961 // CHECK10-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
13962 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
13963 // CHECK10:       omp.body.continue46:
13964 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
13965 // CHECK10:       omp.inner.for.inc47:
13966 // CHECK10-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13967 // CHECK10-NEXT:    [[ADD48:%.*]] = add i64 [[TMP34]], 1
13968 // CHECK10-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
13969 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
13970 // CHECK10:       omp.inner.for.end49:
13971 // CHECK10-NEXT:    store i64 400, i64* [[IT]], align 8
13972 // CHECK10-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
13973 // CHECK10-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
13974 // CHECK10-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
13975 // CHECK10-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP36]]
13976 // CHECK10-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
13977 // CHECK10-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
13978 // CHECK10-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
13979 // CHECK10-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
13980 // CHECK10-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
13981 // CHECK10-NEXT:    [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
13982 // CHECK10-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP38]]
13983 // CHECK10-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
13984 // CHECK10-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
13985 // CHECK10-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
13986 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
13987 // CHECK10-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
13988 // CHECK10-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
13989 // CHECK10-NEXT:    store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
13990 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
13991 // CHECK10:       omp.inner.for.cond63:
13992 // CHECK10-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
13993 // CHECK10-NEXT:    [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
13994 // CHECK10-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
13995 // CHECK10-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
13996 // CHECK10:       omp.inner.for.body65:
13997 // CHECK10-NEXT:    [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
13998 // CHECK10-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
13999 // CHECK10-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
14000 // CHECK10-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
14001 // CHECK10-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
14002 // CHECK10-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
14003 // CHECK10-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
14004 // CHECK10-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
14005 // CHECK10-NEXT:    [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
14006 // CHECK10-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
14007 // CHECK10-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
14008 // CHECK10-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
14009 // CHECK10-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
14010 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
14011 // CHECK10:       omp.body.continue73:
14012 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
14013 // CHECK10:       omp.inner.for.inc74:
14014 // CHECK10-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
14015 // CHECK10-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
14016 // CHECK10-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
14017 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
14018 // CHECK10:       omp.inner.for.end76:
14019 // CHECK10-NEXT:    store i16 22, i16* [[IT62]], align 2
14020 // CHECK10-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
14021 // CHECK10-NEXT:    store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
14022 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
14023 // CHECK10-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
14024 // CHECK10-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
14025 // CHECK10-NEXT:    store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
14026 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
14027 // CHECK10:       omp.inner.for.cond82:
14028 // CHECK10-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
14029 // CHECK10-NEXT:    [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
14030 // CHECK10-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
14031 // CHECK10-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
14032 // CHECK10:       omp.inner.for.body84:
14033 // CHECK10-NEXT:    [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
14034 // CHECK10-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
14035 // CHECK10-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
14036 // CHECK10-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
14037 // CHECK10-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
14038 // CHECK10-NEXT:    [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
14039 // CHECK10-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
14040 // CHECK10-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
14041 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
14042 // CHECK10-NEXT:    [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
14043 // CHECK10-NEXT:    [[CONV89:%.*]] = fpext float [[TMP52]] to double
14044 // CHECK10-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
14045 // CHECK10-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
14046 // CHECK10-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
14047 // CHECK10-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
14048 // CHECK10-NEXT:    [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
14049 // CHECK10-NEXT:    [[CONV93:%.*]] = fpext float [[TMP53]] to double
14050 // CHECK10-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
14051 // CHECK10-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
14052 // CHECK10-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
14053 // CHECK10-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
14054 // CHECK10-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
14055 // CHECK10-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
14056 // CHECK10-NEXT:    [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
14057 // CHECK10-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
14058 // CHECK10-NEXT:    [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
14059 // CHECK10-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
14060 // CHECK10-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
14061 // CHECK10-NEXT:    [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
14062 // CHECK10-NEXT:    [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
14063 // CHECK10-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
14064 // CHECK10-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
14065 // CHECK10-NEXT:    [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
14066 // CHECK10-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
14067 // CHECK10-NEXT:    store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
14068 // CHECK10-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
14069 // CHECK10-NEXT:    [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
14070 // CHECK10-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
14071 // CHECK10-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
14072 // CHECK10-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
14073 // CHECK10-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
14074 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
14075 // CHECK10:       omp.body.continue106:
14076 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
14077 // CHECK10:       omp.inner.for.inc107:
14078 // CHECK10-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
14079 // CHECK10-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
14080 // CHECK10-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
14081 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
14082 // CHECK10:       omp.inner.for.end109:
14083 // CHECK10-NEXT:    store i8 96, i8* [[IT81]], align 1
14084 // CHECK10-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
14085 // CHECK10-NEXT:    [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14086 // CHECK10-NEXT:    call void @llvm.stackrestore(i8* [[TMP61]])
14087 // CHECK10-NEXT:    ret i32 [[TMP60]]
14088 //
14089 //
14090 // CHECK10-LABEL: define {{[^@]+}}@_Z3bari
14091 // CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
14092 // CHECK10-NEXT:  entry:
14093 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14094 // CHECK10-NEXT:    [[A:%.*]] = alloca i32, align 4
14095 // CHECK10-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
14096 // CHECK10-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14097 // CHECK10-NEXT:    store i32 0, i32* [[A]], align 4
14098 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14099 // CHECK10-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
14100 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
14101 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
14102 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14103 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14104 // CHECK10-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
14105 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
14106 // CHECK10-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
14107 // CHECK10-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
14108 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14109 // CHECK10-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
14110 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
14111 // CHECK10-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
14112 // CHECK10-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14113 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
14114 // CHECK10-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
14115 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
14116 // CHECK10-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
14117 // CHECK10-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
14118 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14119 // CHECK10-NEXT:    ret i32 [[TMP8]]
14120 //
14121 //
14122 // CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
14123 // CHECK10-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
14124 // CHECK10-NEXT:  entry:
14125 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14126 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14127 // CHECK10-NEXT:    [[B:%.*]] = alloca i32, align 4
14128 // CHECK10-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14129 // CHECK10-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14130 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i64, align 8
14131 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
14132 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
14133 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
14134 // CHECK10-NEXT:    [[IT:%.*]] = alloca i64, align 8
14135 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14136 // CHECK10-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14137 // CHECK10-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14138 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14139 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14140 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
14141 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
14142 // CHECK10-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
14143 // CHECK10-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
14144 // CHECK10-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
14145 // CHECK10-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
14146 // CHECK10-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
14147 // CHECK10-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
14148 // CHECK10-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
14149 // CHECK10-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
14150 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
14151 // CHECK10-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
14152 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14153 // CHECK10:       omp.inner.for.cond:
14154 // CHECK10-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
14155 // CHECK10-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
14156 // CHECK10-NEXT:    [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]]
14157 // CHECK10-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14158 // CHECK10:       omp.inner.for.body:
14159 // CHECK10-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
14160 // CHECK10-NEXT:    [[MUL:%.*]] = mul i64 [[TMP8]], 400
14161 // CHECK10-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
14162 // CHECK10-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
14163 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
14164 // CHECK10-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
14165 // CHECK10-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
14166 // CHECK10-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
14167 // CHECK10-NEXT:    store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18
14168 // CHECK10-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
14169 // CHECK10-NEXT:    [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18
14170 // CHECK10-NEXT:    [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
14171 // CHECK10-NEXT:    store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18
14172 // CHECK10-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
14173 // CHECK10-NEXT:    [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
14174 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
14175 // CHECK10-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
14176 // CHECK10-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18
14177 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14178 // CHECK10:       omp.body.continue:
14179 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14180 // CHECK10:       omp.inner.for.inc:
14181 // CHECK10-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
14182 // CHECK10-NEXT:    [[ADD6:%.*]] = add i64 [[TMP12]], 1
14183 // CHECK10-NEXT:    store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
14184 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
14185 // CHECK10:       omp.inner.for.end:
14186 // CHECK10-NEXT:    store i64 400, i64* [[IT]], align 8
14187 // CHECK10-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
14188 // CHECK10-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
14189 // CHECK10-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
14190 // CHECK10-NEXT:    [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
14191 // CHECK10-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP14]] to i32
14192 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, i32* [[B]], align 4
14193 // CHECK10-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]]
14194 // CHECK10-NEXT:    [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14195 // CHECK10-NEXT:    call void @llvm.stackrestore(i8* [[TMP16]])
14196 // CHECK10-NEXT:    ret i32 [[ADD10]]
14197 //
14198 //
14199 // CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici
14200 // CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
14201 // CHECK10-NEXT:  entry:
14202 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14203 // CHECK10-NEXT:    [[A:%.*]] = alloca i32, align 4
14204 // CHECK10-NEXT:    [[AA:%.*]] = alloca i16, align 2
14205 // CHECK10-NEXT:    [[AAA:%.*]] = alloca i8, align 1
14206 // CHECK10-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14207 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14208 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14209 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14210 // CHECK10-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14211 // CHECK10-NEXT:    store i32 0, i32* [[A]], align 4
14212 // CHECK10-NEXT:    store i16 0, i16* [[AA]], align 2
14213 // CHECK10-NEXT:    store i8 0, i8* [[AAA]], align 1
14214 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14215 // CHECK10-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
14216 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14217 // CHECK10-NEXT:    ret i32 [[TMP0]]
14218 //
14219 //
14220 // CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
14221 // CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
14222 // CHECK10-NEXT:  entry:
14223 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14224 // CHECK10-NEXT:    [[A:%.*]] = alloca i32, align 4
14225 // CHECK10-NEXT:    [[AA:%.*]] = alloca i16, align 2
14226 // CHECK10-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14227 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i64, align 8
14228 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
14229 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
14230 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
14231 // CHECK10-NEXT:    [[I:%.*]] = alloca i64, align 8
14232 // CHECK10-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14233 // CHECK10-NEXT:    store i32 0, i32* [[A]], align 4
14234 // CHECK10-NEXT:    store i16 0, i16* [[AA]], align 2
14235 // CHECK10-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
14236 // CHECK10-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
14237 // CHECK10-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
14238 // CHECK10-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
14239 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14240 // CHECK10:       omp.inner.for.cond:
14241 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
14242 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21
14243 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
14244 // CHECK10-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14245 // CHECK10:       omp.inner.for.body:
14246 // CHECK10-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
14247 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
14248 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
14249 // CHECK10-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21
14250 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
14251 // CHECK10-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
14252 // CHECK10-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21
14253 // CHECK10-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
14254 // CHECK10-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
14255 // CHECK10-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
14256 // CHECK10-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
14257 // CHECK10-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21
14258 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
14259 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
14260 // CHECK10-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
14261 // CHECK10-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
14262 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14263 // CHECK10:       omp.body.continue:
14264 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14265 // CHECK10:       omp.inner.for.inc:
14266 // CHECK10-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
14267 // CHECK10-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
14268 // CHECK10-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
14269 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
14270 // CHECK10:       omp.inner.for.end:
14271 // CHECK10-NEXT:    store i64 11, i64* [[I]], align 8
14272 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14273 // CHECK10-NEXT:    ret i32 [[TMP8]]
14274 //
14275 //
14276 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv
14277 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
14278 // CHECK11-NEXT:  entry:
14279 // CHECK11-NEXT:    ret i64 0
14280 //
14281 //
14282 // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi
14283 // CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
14284 // CHECK11-NEXT:  entry:
14285 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14286 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
14287 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
14288 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
14289 // CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
14290 // CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
14291 // CHECK11-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
14292 // CHECK11-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
14293 // CHECK11-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
14294 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14295 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14296 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14297 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14298 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
14299 // CHECK11-NEXT:    [[K:%.*]] = alloca i64, align 8
14300 // CHECK11-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
14301 // CHECK11-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
14302 // CHECK11-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
14303 // CHECK11-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
14304 // CHECK11-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
14305 // CHECK11-NEXT:    [[I7:%.*]] = alloca i32, align 4
14306 // CHECK11-NEXT:    [[K8:%.*]] = alloca i64, align 8
14307 // CHECK11-NEXT:    [[LIN:%.*]] = alloca i32, align 4
14308 // CHECK11-NEXT:    [[_TMP21:%.*]] = alloca i64, align 4
14309 // CHECK11-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
14310 // CHECK11-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
14311 // CHECK11-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
14312 // CHECK11-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
14313 // CHECK11-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
14314 // CHECK11-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
14315 // CHECK11-NEXT:    [[IT:%.*]] = alloca i64, align 8
14316 // CHECK11-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
14317 // CHECK11-NEXT:    [[A29:%.*]] = alloca i32, align 4
14318 // CHECK11-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
14319 // CHECK11-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
14320 // CHECK11-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
14321 // CHECK11-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
14322 // CHECK11-NEXT:    [[IT62:%.*]] = alloca i16, align 2
14323 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
14324 // CHECK11-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
14325 // CHECK11-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
14326 // CHECK11-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
14327 // CHECK11-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
14328 // CHECK11-NEXT:    [[IT81:%.*]] = alloca i8, align 1
14329 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14330 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
14331 // CHECK11-NEXT:    store i16 0, i16* [[AA]], align 2
14332 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14333 // CHECK11-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
14334 // CHECK11-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
14335 // CHECK11-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
14336 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
14337 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14338 // CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
14339 // CHECK11-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
14340 // CHECK11-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
14341 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14342 // CHECK11-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
14343 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14344 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
14345 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14346 // CHECK11:       omp.inner.for.cond:
14347 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
14348 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
14349 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
14350 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14351 // CHECK11:       omp.inner.for.body:
14352 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
14353 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
14354 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
14355 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
14356 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14357 // CHECK11:       omp.body.continue:
14358 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14359 // CHECK11:       omp.inner.for.inc:
14360 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
14361 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
14362 // CHECK11-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
14363 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
14364 // CHECK11:       omp.inner.for.end:
14365 // CHECK11-NEXT:    store i32 33, i32* [[I]], align 4
14366 // CHECK11-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
14367 // CHECK11-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
14368 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
14369 // CHECK11-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
14370 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
14371 // CHECK11-NEXT:    store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
14372 // CHECK11-NEXT:    [[TMP10:%.*]] = load i64, i64* [[K]], align 8
14373 // CHECK11-NEXT:    store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
14374 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
14375 // CHECK11:       omp.inner.for.cond9:
14376 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
14377 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
14378 // CHECK11-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
14379 // CHECK11-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
14380 // CHECK11:       omp.inner.for.body11:
14381 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
14382 // CHECK11-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
14383 // CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
14384 // CHECK11-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
14385 // CHECK11-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
14386 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
14387 // CHECK11-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
14388 // CHECK11-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
14389 // CHECK11-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
14390 // CHECK11-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
14391 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
14392 // CHECK11-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
14393 // CHECK11-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
14394 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
14395 // CHECK11:       omp.body.continue16:
14396 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
14397 // CHECK11:       omp.inner.for.inc17:
14398 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
14399 // CHECK11-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
14400 // CHECK11-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
14401 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
14402 // CHECK11:       omp.inner.for.end19:
14403 // CHECK11-NEXT:    store i32 1, i32* [[I7]], align 4
14404 // CHECK11-NEXT:    [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
14405 // CHECK11-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
14406 // CHECK11-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
14407 // CHECK11-NEXT:    store i32 12, i32* [[LIN]], align 4
14408 // CHECK11-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
14409 // CHECK11-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
14410 // CHECK11-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
14411 // CHECK11-NEXT:    store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
14412 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
14413 // CHECK11-NEXT:    store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
14414 // CHECK11-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
14415 // CHECK11-NEXT:    store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
14416 // CHECK11-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
14417 // CHECK11-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
14418 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
14419 // CHECK11:       omp.inner.for.cond30:
14420 // CHECK11-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14421 // CHECK11-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
14422 // CHECK11-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
14423 // CHECK11-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
14424 // CHECK11:       omp.inner.for.body32:
14425 // CHECK11-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14426 // CHECK11-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP24]], 400
14427 // CHECK11-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
14428 // CHECK11-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
14429 // CHECK11-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
14430 // CHECK11-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
14431 // CHECK11-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14432 // CHECK11-NEXT:    [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
14433 // CHECK11-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
14434 // CHECK11-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
14435 // CHECK11-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
14436 // CHECK11-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
14437 // CHECK11-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
14438 // CHECK11-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
14439 // CHECK11-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14440 // CHECK11-NEXT:    [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
14441 // CHECK11-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
14442 // CHECK11-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
14443 // CHECK11-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
14444 // CHECK11-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
14445 // CHECK11-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
14446 // CHECK11-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
14447 // CHECK11-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
14448 // CHECK11-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
14449 // CHECK11-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
14450 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
14451 // CHECK11:       omp.body.continue46:
14452 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
14453 // CHECK11:       omp.inner.for.inc47:
14454 // CHECK11-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14455 // CHECK11-NEXT:    [[ADD48:%.*]] = add i64 [[TMP32]], 1
14456 // CHECK11-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14457 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
14458 // CHECK11:       omp.inner.for.end49:
14459 // CHECK11-NEXT:    store i64 400, i64* [[IT]], align 8
14460 // CHECK11-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
14461 // CHECK11-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
14462 // CHECK11-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
14463 // CHECK11-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP34]]
14464 // CHECK11-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
14465 // CHECK11-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
14466 // CHECK11-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
14467 // CHECK11-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
14468 // CHECK11-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
14469 // CHECK11-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
14470 // CHECK11-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP36]]
14471 // CHECK11-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
14472 // CHECK11-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
14473 // CHECK11-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
14474 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
14475 // CHECK11-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
14476 // CHECK11-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
14477 // CHECK11-NEXT:    store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
14478 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
14479 // CHECK11:       omp.inner.for.cond63:
14480 // CHECK11-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
14481 // CHECK11-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
14482 // CHECK11-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
14483 // CHECK11-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
14484 // CHECK11:       omp.inner.for.body65:
14485 // CHECK11-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
14486 // CHECK11-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
14487 // CHECK11-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
14488 // CHECK11-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
14489 // CHECK11-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
14490 // CHECK11-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
14491 // CHECK11-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
14492 // CHECK11-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
14493 // CHECK11-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
14494 // CHECK11-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
14495 // CHECK11-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
14496 // CHECK11-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
14497 // CHECK11-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
14498 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
14499 // CHECK11:       omp.body.continue73:
14500 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
14501 // CHECK11:       omp.inner.for.inc74:
14502 // CHECK11-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
14503 // CHECK11-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
14504 // CHECK11-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
14505 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
14506 // CHECK11:       omp.inner.for.end76:
14507 // CHECK11-NEXT:    store i16 22, i16* [[IT62]], align 2
14508 // CHECK11-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
14509 // CHECK11-NEXT:    store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
14510 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
14511 // CHECK11-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
14512 // CHECK11-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
14513 // CHECK11-NEXT:    store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
14514 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
14515 // CHECK11:       omp.inner.for.cond82:
14516 // CHECK11-NEXT:    [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
14517 // CHECK11-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
14518 // CHECK11-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
14519 // CHECK11-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
14520 // CHECK11:       omp.inner.for.body84:
14521 // CHECK11-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
14522 // CHECK11-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
14523 // CHECK11-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
14524 // CHECK11-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
14525 // CHECK11-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
14526 // CHECK11-NEXT:    [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
14527 // CHECK11-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
14528 // CHECK11-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
14529 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
14530 // CHECK11-NEXT:    [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
14531 // CHECK11-NEXT:    [[CONV89:%.*]] = fpext float [[TMP50]] to double
14532 // CHECK11-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
14533 // CHECK11-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
14534 // CHECK11-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
14535 // CHECK11-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
14536 // CHECK11-NEXT:    [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
14537 // CHECK11-NEXT:    [[CONV93:%.*]] = fpext float [[TMP51]] to double
14538 // CHECK11-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
14539 // CHECK11-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
14540 // CHECK11-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
14541 // CHECK11-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
14542 // CHECK11-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
14543 // CHECK11-NEXT:    [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
14544 // CHECK11-NEXT:    [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
14545 // CHECK11-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
14546 // CHECK11-NEXT:    [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
14547 // CHECK11-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
14548 // CHECK11-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
14549 // CHECK11-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
14550 // CHECK11-NEXT:    [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
14551 // CHECK11-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
14552 // CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
14553 // CHECK11-NEXT:    [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
14554 // CHECK11-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
14555 // CHECK11-NEXT:    store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
14556 // CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
14557 // CHECK11-NEXT:    [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
14558 // CHECK11-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
14559 // CHECK11-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
14560 // CHECK11-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
14561 // CHECK11-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
14562 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
14563 // CHECK11:       omp.body.continue106:
14564 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
14565 // CHECK11:       omp.inner.for.inc107:
14566 // CHECK11-NEXT:    [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
14567 // CHECK11-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
14568 // CHECK11-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
14569 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
14570 // CHECK11:       omp.inner.for.end109:
14571 // CHECK11-NEXT:    store i8 96, i8* [[IT81]], align 1
14572 // CHECK11-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A]], align 4
14573 // CHECK11-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
14574 // CHECK11-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
14575 // CHECK11-NEXT:    ret i32 [[TMP58]]
14576 //
14577 //
14578 // CHECK11-LABEL: define {{[^@]+}}@_Z3bari
14579 // CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
14580 // CHECK11-NEXT:  entry:
14581 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14582 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
14583 // CHECK11-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
14584 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14585 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
14586 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14587 // CHECK11-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
14588 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
14589 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
14590 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14591 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14592 // CHECK11-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
14593 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
14594 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
14595 // CHECK11-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
14596 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14597 // CHECK11-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
14598 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
14599 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
14600 // CHECK11-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14601 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
14602 // CHECK11-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
14603 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
14604 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
14605 // CHECK11-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
14606 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14607 // CHECK11-NEXT:    ret i32 [[TMP8]]
14608 //
14609 //
14610 // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
14611 // CHECK11-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
14612 // CHECK11-NEXT:  entry:
14613 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
14614 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14615 // CHECK11-NEXT:    [[B:%.*]] = alloca i32, align 4
14616 // CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
14617 // CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
14618 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i64, align 4
14619 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
14620 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
14621 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
14622 // CHECK11-NEXT:    [[IT:%.*]] = alloca i64, align 8
14623 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
14624 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14625 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
14626 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14627 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14628 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
14629 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
14630 // CHECK11-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
14631 // CHECK11-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
14632 // CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
14633 // CHECK11-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
14634 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
14635 // CHECK11-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
14636 // CHECK11-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
14637 // CHECK11-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
14638 // CHECK11-NEXT:    store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8
14639 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14640 // CHECK11:       omp.inner.for.cond:
14641 // CHECK11-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
14642 // CHECK11-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
14643 // CHECK11-NEXT:    [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]]
14644 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14645 // CHECK11:       omp.inner.for.body:
14646 // CHECK11-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
14647 // CHECK11-NEXT:    [[MUL:%.*]] = mul i64 [[TMP7]], 400
14648 // CHECK11-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
14649 // CHECK11-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
14650 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
14651 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
14652 // CHECK11-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
14653 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
14654 // CHECK11-NEXT:    store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19
14655 // CHECK11-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
14656 // CHECK11-NEXT:    [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19
14657 // CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
14658 // CHECK11-NEXT:    store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19
14659 // CHECK11-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
14660 // CHECK11-NEXT:    [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
14661 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
14662 // CHECK11-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
14663 // CHECK11-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19
14664 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14665 // CHECK11:       omp.body.continue:
14666 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14667 // CHECK11:       omp.inner.for.inc:
14668 // CHECK11-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
14669 // CHECK11-NEXT:    [[ADD6:%.*]] = add i64 [[TMP11]], 1
14670 // CHECK11-NEXT:    store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
14671 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
14672 // CHECK11:       omp.inner.for.end:
14673 // CHECK11-NEXT:    store i64 400, i64* [[IT]], align 8
14674 // CHECK11-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
14675 // CHECK11-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
14676 // CHECK11-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
14677 // CHECK11-NEXT:    [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
14678 // CHECK11-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP13]] to i32
14679 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B]], align 4
14680 // CHECK11-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]]
14681 // CHECK11-NEXT:    [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
14682 // CHECK11-NEXT:    call void @llvm.stackrestore(i8* [[TMP15]])
14683 // CHECK11-NEXT:    ret i32 [[ADD10]]
14684 //
14685 //
14686 // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici
14687 // CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
14688 // CHECK11-NEXT:  entry:
14689 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14690 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
14691 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
14692 // CHECK11-NEXT:    [[AAA:%.*]] = alloca i8, align 1
14693 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14694 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14695 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14696 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14697 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14698 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
14699 // CHECK11-NEXT:    store i16 0, i16* [[AA]], align 2
14700 // CHECK11-NEXT:    store i8 0, i8* [[AAA]], align 1
14701 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14702 // CHECK11-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
14703 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14704 // CHECK11-NEXT:    ret i32 [[TMP0]]
14705 //
14706 //
14707 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
14708 // CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
14709 // CHECK11-NEXT:  entry:
14710 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14711 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
14712 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
14713 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14714 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i64, align 4
14715 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
14716 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
14717 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
14718 // CHECK11-NEXT:    [[I:%.*]] = alloca i64, align 8
14719 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14720 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
14721 // CHECK11-NEXT:    store i16 0, i16* [[AA]], align 2
14722 // CHECK11-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
14723 // CHECK11-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
14724 // CHECK11-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
14725 // CHECK11-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
14726 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14727 // CHECK11:       omp.inner.for.cond:
14728 // CHECK11-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
14729 // CHECK11-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22
14730 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
14731 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14732 // CHECK11:       omp.inner.for.body:
14733 // CHECK11-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
14734 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
14735 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
14736 // CHECK11-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22
14737 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
14738 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
14739 // CHECK11-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22
14740 // CHECK11-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
14741 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
14742 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
14743 // CHECK11-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
14744 // CHECK11-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22
14745 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
14746 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
14747 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
14748 // CHECK11-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
14749 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14750 // CHECK11:       omp.body.continue:
14751 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14752 // CHECK11:       omp.inner.for.inc:
14753 // CHECK11-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
14754 // CHECK11-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
14755 // CHECK11-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
14756 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
14757 // CHECK11:       omp.inner.for.end:
14758 // CHECK11-NEXT:    store i64 11, i64* [[I]], align 8
14759 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14760 // CHECK11-NEXT:    ret i32 [[TMP8]]
14761 //
14762 //
14763 // CHECK12-LABEL: define {{[^@]+}}@_Z7get_valv
14764 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
14765 // CHECK12-NEXT:  entry:
14766 // CHECK12-NEXT:    ret i64 0
14767 //
14768 //
14769 // CHECK12-LABEL: define {{[^@]+}}@_Z3fooi
14770 // CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
14771 // CHECK12-NEXT:  entry:
14772 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14773 // CHECK12-NEXT:    [[A:%.*]] = alloca i32, align 4
14774 // CHECK12-NEXT:    [[AA:%.*]] = alloca i16, align 2
14775 // CHECK12-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
14776 // CHECK12-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
14777 // CHECK12-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
14778 // CHECK12-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
14779 // CHECK12-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
14780 // CHECK12-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
14781 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14782 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14783 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14784 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14785 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
14786 // CHECK12-NEXT:    [[K:%.*]] = alloca i64, align 8
14787 // CHECK12-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
14788 // CHECK12-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
14789 // CHECK12-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
14790 // CHECK12-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
14791 // CHECK12-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
14792 // CHECK12-NEXT:    [[I7:%.*]] = alloca i32, align 4
14793 // CHECK12-NEXT:    [[K8:%.*]] = alloca i64, align 8
14794 // CHECK12-NEXT:    [[LIN:%.*]] = alloca i32, align 4
14795 // CHECK12-NEXT:    [[_TMP21:%.*]] = alloca i64, align 4
14796 // CHECK12-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
14797 // CHECK12-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
14798 // CHECK12-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
14799 // CHECK12-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
14800 // CHECK12-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
14801 // CHECK12-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
14802 // CHECK12-NEXT:    [[IT:%.*]] = alloca i64, align 8
14803 // CHECK12-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
14804 // CHECK12-NEXT:    [[A29:%.*]] = alloca i32, align 4
14805 // CHECK12-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
14806 // CHECK12-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
14807 // CHECK12-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
14808 // CHECK12-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
14809 // CHECK12-NEXT:    [[IT62:%.*]] = alloca i16, align 2
14810 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
14811 // CHECK12-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
14812 // CHECK12-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
14813 // CHECK12-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
14814 // CHECK12-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
14815 // CHECK12-NEXT:    [[IT81:%.*]] = alloca i8, align 1
14816 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14817 // CHECK12-NEXT:    store i32 0, i32* [[A]], align 4
14818 // CHECK12-NEXT:    store i16 0, i16* [[AA]], align 2
14819 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14820 // CHECK12-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
14821 // CHECK12-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
14822 // CHECK12-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
14823 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
14824 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14825 // CHECK12-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
14826 // CHECK12-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
14827 // CHECK12-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
14828 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14829 // CHECK12-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
14830 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14831 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
14832 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14833 // CHECK12:       omp.inner.for.cond:
14834 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
14835 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
14836 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
14837 // CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14838 // CHECK12:       omp.inner.for.body:
14839 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
14840 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
14841 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
14842 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
14843 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14844 // CHECK12:       omp.body.continue:
14845 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14846 // CHECK12:       omp.inner.for.inc:
14847 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
14848 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
14849 // CHECK12-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
14850 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
14851 // CHECK12:       omp.inner.for.end:
14852 // CHECK12-NEXT:    store i32 33, i32* [[I]], align 4
14853 // CHECK12-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
14854 // CHECK12-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
14855 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
14856 // CHECK12-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
14857 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
14858 // CHECK12-NEXT:    store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
14859 // CHECK12-NEXT:    [[TMP10:%.*]] = load i64, i64* [[K]], align 8
14860 // CHECK12-NEXT:    store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
14861 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
14862 // CHECK12:       omp.inner.for.cond9:
14863 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
14864 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
14865 // CHECK12-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
14866 // CHECK12-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
14867 // CHECK12:       omp.inner.for.body11:
14868 // CHECK12-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
14869 // CHECK12-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
14870 // CHECK12-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
14871 // CHECK12-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
14872 // CHECK12-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
14873 // CHECK12-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
14874 // CHECK12-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
14875 // CHECK12-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
14876 // CHECK12-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
14877 // CHECK12-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
14878 // CHECK12-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
14879 // CHECK12-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
14880 // CHECK12-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
14881 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
14882 // CHECK12:       omp.body.continue16:
14883 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
14884 // CHECK12:       omp.inner.for.inc17:
14885 // CHECK12-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
14886 // CHECK12-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
14887 // CHECK12-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
14888 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
14889 // CHECK12:       omp.inner.for.end19:
14890 // CHECK12-NEXT:    store i32 1, i32* [[I7]], align 4
14891 // CHECK12-NEXT:    [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
14892 // CHECK12-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
14893 // CHECK12-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
14894 // CHECK12-NEXT:    store i32 12, i32* [[LIN]], align 4
14895 // CHECK12-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
14896 // CHECK12-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
14897 // CHECK12-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
14898 // CHECK12-NEXT:    store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
14899 // CHECK12-NEXT:    [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
14900 // CHECK12-NEXT:    store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
14901 // CHECK12-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
14902 // CHECK12-NEXT:    store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
14903 // CHECK12-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
14904 // CHECK12-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
14905 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
14906 // CHECK12:       omp.inner.for.cond30:
14907 // CHECK12-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14908 // CHECK12-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
14909 // CHECK12-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
14910 // CHECK12-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
14911 // CHECK12:       omp.inner.for.body32:
14912 // CHECK12-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14913 // CHECK12-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP24]], 400
14914 // CHECK12-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
14915 // CHECK12-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
14916 // CHECK12-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
14917 // CHECK12-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
14918 // CHECK12-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14919 // CHECK12-NEXT:    [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
14920 // CHECK12-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
14921 // CHECK12-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
14922 // CHECK12-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
14923 // CHECK12-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
14924 // CHECK12-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
14925 // CHECK12-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
14926 // CHECK12-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14927 // CHECK12-NEXT:    [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
14928 // CHECK12-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
14929 // CHECK12-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
14930 // CHECK12-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
14931 // CHECK12-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
14932 // CHECK12-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
14933 // CHECK12-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
14934 // CHECK12-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
14935 // CHECK12-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
14936 // CHECK12-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
14937 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
14938 // CHECK12:       omp.body.continue46:
14939 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
14940 // CHECK12:       omp.inner.for.inc47:
14941 // CHECK12-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14942 // CHECK12-NEXT:    [[ADD48:%.*]] = add i64 [[TMP32]], 1
14943 // CHECK12-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
14944 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
14945 // CHECK12:       omp.inner.for.end49:
14946 // CHECK12-NEXT:    store i64 400, i64* [[IT]], align 8
14947 // CHECK12-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
14948 // CHECK12-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
14949 // CHECK12-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
14950 // CHECK12-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP34]]
14951 // CHECK12-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
14952 // CHECK12-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
14953 // CHECK12-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
14954 // CHECK12-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
14955 // CHECK12-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
14956 // CHECK12-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
14957 // CHECK12-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP36]]
14958 // CHECK12-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
14959 // CHECK12-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
14960 // CHECK12-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
14961 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
14962 // CHECK12-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
14963 // CHECK12-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
14964 // CHECK12-NEXT:    store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
14965 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
14966 // CHECK12:       omp.inner.for.cond63:
14967 // CHECK12-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
14968 // CHECK12-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
14969 // CHECK12-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
14970 // CHECK12-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
14971 // CHECK12:       omp.inner.for.body65:
14972 // CHECK12-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
14973 // CHECK12-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
14974 // CHECK12-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
14975 // CHECK12-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
14976 // CHECK12-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
14977 // CHECK12-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
14978 // CHECK12-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
14979 // CHECK12-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
14980 // CHECK12-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
14981 // CHECK12-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
14982 // CHECK12-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
14983 // CHECK12-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
14984 // CHECK12-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
14985 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
14986 // CHECK12:       omp.body.continue73:
14987 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
14988 // CHECK12:       omp.inner.for.inc74:
14989 // CHECK12-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
14990 // CHECK12-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
14991 // CHECK12-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
14992 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
14993 // CHECK12:       omp.inner.for.end76:
14994 // CHECK12-NEXT:    store i16 22, i16* [[IT62]], align 2
14995 // CHECK12-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
14996 // CHECK12-NEXT:    store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
14997 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
14998 // CHECK12-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
14999 // CHECK12-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
15000 // CHECK12-NEXT:    store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
15001 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
15002 // CHECK12:       omp.inner.for.cond82:
15003 // CHECK12-NEXT:    [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
15004 // CHECK12-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
15005 // CHECK12-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
15006 // CHECK12-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
15007 // CHECK12:       omp.inner.for.body84:
15008 // CHECK12-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
15009 // CHECK12-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
15010 // CHECK12-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
15011 // CHECK12-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
15012 // CHECK12-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
15013 // CHECK12-NEXT:    [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
15014 // CHECK12-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
15015 // CHECK12-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
15016 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
15017 // CHECK12-NEXT:    [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
15018 // CHECK12-NEXT:    [[CONV89:%.*]] = fpext float [[TMP50]] to double
15019 // CHECK12-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
15020 // CHECK12-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
15021 // CHECK12-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
15022 // CHECK12-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
15023 // CHECK12-NEXT:    [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
15024 // CHECK12-NEXT:    [[CONV93:%.*]] = fpext float [[TMP51]] to double
15025 // CHECK12-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
15026 // CHECK12-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
15027 // CHECK12-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
15028 // CHECK12-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
15029 // CHECK12-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
15030 // CHECK12-NEXT:    [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
15031 // CHECK12-NEXT:    [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
15032 // CHECK12-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
15033 // CHECK12-NEXT:    [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
15034 // CHECK12-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
15035 // CHECK12-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
15036 // CHECK12-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
15037 // CHECK12-NEXT:    [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
15038 // CHECK12-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
15039 // CHECK12-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
15040 // CHECK12-NEXT:    [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
15041 // CHECK12-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
15042 // CHECK12-NEXT:    store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
15043 // CHECK12-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
15044 // CHECK12-NEXT:    [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
15045 // CHECK12-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
15046 // CHECK12-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
15047 // CHECK12-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
15048 // CHECK12-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
15049 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
15050 // CHECK12:       omp.body.continue106:
15051 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
15052 // CHECK12:       omp.inner.for.inc107:
15053 // CHECK12-NEXT:    [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
15054 // CHECK12-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
15055 // CHECK12-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
15056 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
15057 // CHECK12:       omp.inner.for.end109:
15058 // CHECK12-NEXT:    store i8 96, i8* [[IT81]], align 1
15059 // CHECK12-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A]], align 4
15060 // CHECK12-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
15061 // CHECK12-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
15062 // CHECK12-NEXT:    ret i32 [[TMP58]]
15063 //
15064 //
15065 // CHECK12-LABEL: define {{[^@]+}}@_Z3bari
15066 // CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
15067 // CHECK12-NEXT:  entry:
15068 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15069 // CHECK12-NEXT:    [[A:%.*]] = alloca i32, align 4
15070 // CHECK12-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
15071 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15072 // CHECK12-NEXT:    store i32 0, i32* [[A]], align 4
15073 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15074 // CHECK12-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
15075 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
15076 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
15077 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
15078 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
15079 // CHECK12-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
15080 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
15081 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
15082 // CHECK12-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
15083 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
15084 // CHECK12-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
15085 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
15086 // CHECK12-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
15087 // CHECK12-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
15088 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
15089 // CHECK12-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
15090 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
15091 // CHECK12-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
15092 // CHECK12-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
15093 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15094 // CHECK12-NEXT:    ret i32 [[TMP8]]
15095 //
15096 //
15097 // CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
15098 // CHECK12-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
15099 // CHECK12-NEXT:  entry:
15100 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
15101 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15102 // CHECK12-NEXT:    [[B:%.*]] = alloca i32, align 4
15103 // CHECK12-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
15104 // CHECK12-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
15105 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i64, align 4
15106 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
15107 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
15108 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
15109 // CHECK12-NEXT:    [[IT:%.*]] = alloca i64, align 8
15110 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
15111 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15112 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
15113 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15114 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
15115 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
15116 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
15117 // CHECK12-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
15118 // CHECK12-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
15119 // CHECK12-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
15120 // CHECK12-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
15121 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
15122 // CHECK12-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
15123 // CHECK12-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
15124 // CHECK12-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
15125 // CHECK12-NEXT:    store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8
15126 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15127 // CHECK12:       omp.inner.for.cond:
15128 // CHECK12-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
15129 // CHECK12-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
15130 // CHECK12-NEXT:    [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]]
15131 // CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15132 // CHECK12:       omp.inner.for.body:
15133 // CHECK12-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
15134 // CHECK12-NEXT:    [[MUL:%.*]] = mul i64 [[TMP7]], 400
15135 // CHECK12-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
15136 // CHECK12-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
15137 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
15138 // CHECK12-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
15139 // CHECK12-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
15140 // CHECK12-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
15141 // CHECK12-NEXT:    store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19
15142 // CHECK12-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
15143 // CHECK12-NEXT:    [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19
15144 // CHECK12-NEXT:    [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
15145 // CHECK12-NEXT:    store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19
15146 // CHECK12-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
15147 // CHECK12-NEXT:    [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
15148 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
15149 // CHECK12-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
15150 // CHECK12-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19
15151 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15152 // CHECK12:       omp.body.continue:
15153 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15154 // CHECK12:       omp.inner.for.inc:
15155 // CHECK12-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
15156 // CHECK12-NEXT:    [[ADD6:%.*]] = add i64 [[TMP11]], 1
15157 // CHECK12-NEXT:    store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
15158 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
15159 // CHECK12:       omp.inner.for.end:
15160 // CHECK12-NEXT:    store i64 400, i64* [[IT]], align 8
15161 // CHECK12-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
15162 // CHECK12-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
15163 // CHECK12-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
15164 // CHECK12-NEXT:    [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
15165 // CHECK12-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP13]] to i32
15166 // CHECK12-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B]], align 4
15167 // CHECK12-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]]
15168 // CHECK12-NEXT:    [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
15169 // CHECK12-NEXT:    call void @llvm.stackrestore(i8* [[TMP15]])
15170 // CHECK12-NEXT:    ret i32 [[ADD10]]
15171 //
15172 //
15173 // CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici
15174 // CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
15175 // CHECK12-NEXT:  entry:
15176 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15177 // CHECK12-NEXT:    [[A:%.*]] = alloca i32, align 4
15178 // CHECK12-NEXT:    [[AA:%.*]] = alloca i16, align 2
15179 // CHECK12-NEXT:    [[AAA:%.*]] = alloca i8, align 1
15180 // CHECK12-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15181 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15182 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15183 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15184 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15185 // CHECK12-NEXT:    store i32 0, i32* [[A]], align 4
15186 // CHECK12-NEXT:    store i16 0, i16* [[AA]], align 2
15187 // CHECK12-NEXT:    store i8 0, i8* [[AAA]], align 1
15188 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15189 // CHECK12-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
15190 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
15191 // CHECK12-NEXT:    ret i32 [[TMP0]]
15192 //
15193 //
15194 // CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
15195 // CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
15196 // CHECK12-NEXT:  entry:
15197 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15198 // CHECK12-NEXT:    [[A:%.*]] = alloca i32, align 4
15199 // CHECK12-NEXT:    [[AA:%.*]] = alloca i16, align 2
15200 // CHECK12-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15201 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i64, align 4
15202 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
15203 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
15204 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
15205 // CHECK12-NEXT:    [[I:%.*]] = alloca i64, align 8
15206 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15207 // CHECK12-NEXT:    store i32 0, i32* [[A]], align 4
15208 // CHECK12-NEXT:    store i16 0, i16* [[AA]], align 2
15209 // CHECK12-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
15210 // CHECK12-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
15211 // CHECK12-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
15212 // CHECK12-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
15213 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15214 // CHECK12:       omp.inner.for.cond:
15215 // CHECK12-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
15216 // CHECK12-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22
15217 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
15218 // CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15219 // CHECK12:       omp.inner.for.body:
15220 // CHECK12-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
15221 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
15222 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
15223 // CHECK12-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22
15224 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
15225 // CHECK12-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
15226 // CHECK12-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22
15227 // CHECK12-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
15228 // CHECK12-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
15229 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
15230 // CHECK12-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
15231 // CHECK12-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22
15232 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
15233 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
15234 // CHECK12-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
15235 // CHECK12-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
15236 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15237 // CHECK12:       omp.body.continue:
15238 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15239 // CHECK12:       omp.inner.for.inc:
15240 // CHECK12-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
15241 // CHECK12-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
15242 // CHECK12-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
15243 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
15244 // CHECK12:       omp.inner.for.end:
15245 // CHECK12-NEXT:    store i64 11, i64* [[I]], align 8
15246 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15247 // CHECK12-NEXT:    ret i32 [[TMP8]]
15248 //
15249 //
15250 // CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv
15251 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] {
15252 // CHECK13-NEXT:  entry:
15253 // CHECK13-NEXT:    ret i64 0
15254 //
15255 //
15256 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi
15257 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
15258 // CHECK13-NEXT:  entry:
15259 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15260 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
15261 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
15262 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
15263 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
15264 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
15265 // CHECK13-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
15266 // CHECK13-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
15267 // CHECK13-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
15268 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15269 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15270 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15271 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15272 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
15273 // CHECK13-NEXT:    [[K:%.*]] = alloca i64, align 8
15274 // CHECK13-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
15275 // CHECK13-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
15276 // CHECK13-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
15277 // CHECK13-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
15278 // CHECK13-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
15279 // CHECK13-NEXT:    [[I7:%.*]] = alloca i32, align 4
15280 // CHECK13-NEXT:    [[K8:%.*]] = alloca i64, align 8
15281 // CHECK13-NEXT:    [[LIN:%.*]] = alloca i32, align 4
15282 // CHECK13-NEXT:    [[_TMP21:%.*]] = alloca i64, align 8
15283 // CHECK13-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
15284 // CHECK13-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
15285 // CHECK13-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
15286 // CHECK13-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
15287 // CHECK13-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
15288 // CHECK13-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
15289 // CHECK13-NEXT:    [[IT:%.*]] = alloca i64, align 8
15290 // CHECK13-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
15291 // CHECK13-NEXT:    [[A29:%.*]] = alloca i32, align 4
15292 // CHECK13-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
15293 // CHECK13-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
15294 // CHECK13-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
15295 // CHECK13-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
15296 // CHECK13-NEXT:    [[IT62:%.*]] = alloca i16, align 2
15297 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
15298 // CHECK13-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
15299 // CHECK13-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
15300 // CHECK13-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
15301 // CHECK13-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
15302 // CHECK13-NEXT:    [[IT81:%.*]] = alloca i8, align 1
15303 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15304 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
15305 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
15306 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15307 // CHECK13-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
15308 // CHECK13-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
15309 // CHECK13-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
15310 // CHECK13-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
15311 // CHECK13-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
15312 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
15313 // CHECK13-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
15314 // CHECK13-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
15315 // CHECK13-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
15316 // CHECK13-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
15317 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15318 // CHECK13-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
15319 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15320 // CHECK13-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
15321 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15322 // CHECK13:       omp.inner.for.cond:
15323 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15324 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
15325 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
15326 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15327 // CHECK13:       omp.inner.for.body:
15328 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15329 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
15330 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
15331 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
15332 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15333 // CHECK13:       omp.body.continue:
15334 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15335 // CHECK13:       omp.inner.for.inc:
15336 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15337 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
15338 // CHECK13-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15339 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
15340 // CHECK13:       omp.inner.for.end:
15341 // CHECK13-NEXT:    store i32 33, i32* [[I]], align 4
15342 // CHECK13-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
15343 // CHECK13-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
15344 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
15345 // CHECK13-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
15346 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
15347 // CHECK13-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
15348 // CHECK13-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K]], align 8
15349 // CHECK13-NEXT:    store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
15350 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
15351 // CHECK13:       omp.inner.for.cond9:
15352 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
15353 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
15354 // CHECK13-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
15355 // CHECK13-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
15356 // CHECK13:       omp.inner.for.body11:
15357 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
15358 // CHECK13-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
15359 // CHECK13-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
15360 // CHECK13-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
15361 // CHECK13-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
15362 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
15363 // CHECK13-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
15364 // CHECK13-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
15365 // CHECK13-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
15366 // CHECK13-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
15367 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
15368 // CHECK13-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
15369 // CHECK13-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
15370 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
15371 // CHECK13:       omp.body.continue16:
15372 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
15373 // CHECK13:       omp.inner.for.inc17:
15374 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
15375 // CHECK13-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
15376 // CHECK13-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
15377 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
15378 // CHECK13:       omp.inner.for.end19:
15379 // CHECK13-NEXT:    store i32 1, i32* [[I7]], align 4
15380 // CHECK13-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
15381 // CHECK13-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
15382 // CHECK13-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
15383 // CHECK13-NEXT:    store i32 12, i32* [[LIN]], align 4
15384 // CHECK13-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
15385 // CHECK13-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
15386 // CHECK13-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
15387 // CHECK13-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
15388 // CHECK13-NEXT:    [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
15389 // CHECK13-NEXT:    store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
15390 // CHECK13-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A]], align 4
15391 // CHECK13-NEXT:    store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
15392 // CHECK13-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
15393 // CHECK13-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
15394 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
15395 // CHECK13:       omp.inner.for.cond30:
15396 // CHECK13-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15397 // CHECK13-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
15398 // CHECK13-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
15399 // CHECK13-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
15400 // CHECK13:       omp.inner.for.body32:
15401 // CHECK13-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15402 // CHECK13-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP26]], 400
15403 // CHECK13-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
15404 // CHECK13-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
15405 // CHECK13-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
15406 // CHECK13-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
15407 // CHECK13-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15408 // CHECK13-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
15409 // CHECK13-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
15410 // CHECK13-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
15411 // CHECK13-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
15412 // CHECK13-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
15413 // CHECK13-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
15414 // CHECK13-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
15415 // CHECK13-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15416 // CHECK13-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
15417 // CHECK13-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
15418 // CHECK13-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
15419 // CHECK13-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
15420 // CHECK13-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
15421 // CHECK13-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
15422 // CHECK13-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
15423 // CHECK13-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
15424 // CHECK13-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
15425 // CHECK13-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
15426 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
15427 // CHECK13:       omp.body.continue46:
15428 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
15429 // CHECK13:       omp.inner.for.inc47:
15430 // CHECK13-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15431 // CHECK13-NEXT:    [[ADD48:%.*]] = add i64 [[TMP34]], 1
15432 // CHECK13-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15433 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
15434 // CHECK13:       omp.inner.for.end49:
15435 // CHECK13-NEXT:    store i64 400, i64* [[IT]], align 8
15436 // CHECK13-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
15437 // CHECK13-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
15438 // CHECK13-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
15439 // CHECK13-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP36]]
15440 // CHECK13-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
15441 // CHECK13-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
15442 // CHECK13-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
15443 // CHECK13-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
15444 // CHECK13-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
15445 // CHECK13-NEXT:    [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
15446 // CHECK13-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP38]]
15447 // CHECK13-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
15448 // CHECK13-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
15449 // CHECK13-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
15450 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
15451 // CHECK13-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
15452 // CHECK13-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
15453 // CHECK13-NEXT:    store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
15454 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
15455 // CHECK13:       omp.inner.for.cond63:
15456 // CHECK13-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
15457 // CHECK13-NEXT:    [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
15458 // CHECK13-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
15459 // CHECK13-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
15460 // CHECK13:       omp.inner.for.body65:
15461 // CHECK13-NEXT:    [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
15462 // CHECK13-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
15463 // CHECK13-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
15464 // CHECK13-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
15465 // CHECK13-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
15466 // CHECK13-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
15467 // CHECK13-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
15468 // CHECK13-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
15469 // CHECK13-NEXT:    [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
15470 // CHECK13-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
15471 // CHECK13-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
15472 // CHECK13-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
15473 // CHECK13-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
15474 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
15475 // CHECK13:       omp.body.continue73:
15476 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
15477 // CHECK13:       omp.inner.for.inc74:
15478 // CHECK13-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
15479 // CHECK13-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
15480 // CHECK13-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
15481 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
15482 // CHECK13:       omp.inner.for.end76:
15483 // CHECK13-NEXT:    store i16 22, i16* [[IT62]], align 2
15484 // CHECK13-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
15485 // CHECK13-NEXT:    store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
15486 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
15487 // CHECK13-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
15488 // CHECK13-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
15489 // CHECK13-NEXT:    store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
15490 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
15491 // CHECK13:       omp.inner.for.cond82:
15492 // CHECK13-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
15493 // CHECK13-NEXT:    [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
15494 // CHECK13-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
15495 // CHECK13-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
15496 // CHECK13:       omp.inner.for.body84:
15497 // CHECK13-NEXT:    [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
15498 // CHECK13-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
15499 // CHECK13-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
15500 // CHECK13-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
15501 // CHECK13-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
15502 // CHECK13-NEXT:    [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
15503 // CHECK13-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
15504 // CHECK13-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
15505 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
15506 // CHECK13-NEXT:    [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
15507 // CHECK13-NEXT:    [[CONV89:%.*]] = fpext float [[TMP52]] to double
15508 // CHECK13-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
15509 // CHECK13-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
15510 // CHECK13-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
15511 // CHECK13-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
15512 // CHECK13-NEXT:    [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
15513 // CHECK13-NEXT:    [[CONV93:%.*]] = fpext float [[TMP53]] to double
15514 // CHECK13-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
15515 // CHECK13-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
15516 // CHECK13-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
15517 // CHECK13-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
15518 // CHECK13-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
15519 // CHECK13-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
15520 // CHECK13-NEXT:    [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
15521 // CHECK13-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
15522 // CHECK13-NEXT:    [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
15523 // CHECK13-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
15524 // CHECK13-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
15525 // CHECK13-NEXT:    [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
15526 // CHECK13-NEXT:    [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
15527 // CHECK13-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
15528 // CHECK13-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
15529 // CHECK13-NEXT:    [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
15530 // CHECK13-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
15531 // CHECK13-NEXT:    store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
15532 // CHECK13-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
15533 // CHECK13-NEXT:    [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
15534 // CHECK13-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
15535 // CHECK13-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
15536 // CHECK13-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
15537 // CHECK13-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
15538 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
15539 // CHECK13:       omp.body.continue106:
15540 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
15541 // CHECK13:       omp.inner.for.inc107:
15542 // CHECK13-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
15543 // CHECK13-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
15544 // CHECK13-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
15545 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
15546 // CHECK13:       omp.inner.for.end109:
15547 // CHECK13-NEXT:    store i8 96, i8* [[IT81]], align 1
15548 // CHECK13-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
15549 // CHECK13-NEXT:    [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
15550 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP61]])
15551 // CHECK13-NEXT:    ret i32 [[TMP60]]
15552 //
15553 //
15554 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari
15555 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
15556 // CHECK13-NEXT:  entry:
15557 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15558 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
15559 // CHECK13-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
15560 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15561 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
15562 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15563 // CHECK13-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
15564 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
15565 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
15566 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
15567 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
15568 // CHECK13-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
15569 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
15570 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
15571 // CHECK13-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
15572 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
15573 // CHECK13-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
15574 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
15575 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
15576 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
15577 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
15578 // CHECK13-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
15579 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
15580 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
15581 // CHECK13-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
15582 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15583 // CHECK13-NEXT:    ret i32 [[TMP8]]
15584 //
15585 //
15586 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
15587 // CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
15588 // CHECK13-NEXT:  entry:
15589 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
15590 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15591 // CHECK13-NEXT:    [[B:%.*]] = alloca i32, align 4
15592 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
15593 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
15594 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
15595 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i64, align 8
15596 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
15597 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
15598 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
15599 // CHECK13-NEXT:    [[IT:%.*]] = alloca i64, align 8
15600 // CHECK13-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
15601 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15602 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
15603 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15604 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
15605 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
15606 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
15607 // CHECK13-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
15608 // CHECK13-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
15609 // CHECK13-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
15610 // CHECK13-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
15611 // CHECK13-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
15612 // CHECK13-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
15613 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
15614 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
15615 // CHECK13-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
15616 // CHECK13-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
15617 // CHECK13-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
15618 // CHECK13-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
15619 // CHECK13-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
15620 // CHECK13-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
15621 // CHECK13-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15622 // CHECK13-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
15623 // CHECK13-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
15624 // CHECK13:       omp_if.then:
15625 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15626 // CHECK13:       omp.inner.for.cond:
15627 // CHECK13-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
15628 // CHECK13-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
15629 // CHECK13-NEXT:    [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]]
15630 // CHECK13-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15631 // CHECK13:       omp.inner.for.body:
15632 // CHECK13-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
15633 // CHECK13-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 400
15634 // CHECK13-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
15635 // CHECK13-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
15636 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
15637 // CHECK13-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
15638 // CHECK13-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
15639 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
15640 // CHECK13-NEXT:    store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18
15641 // CHECK13-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
15642 // CHECK13-NEXT:    [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
15643 // CHECK13-NEXT:    [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
15644 // CHECK13-NEXT:    store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
15645 // CHECK13-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
15646 // CHECK13-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
15647 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
15648 // CHECK13-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
15649 // CHECK13-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
15650 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15651 // CHECK13:       omp.body.continue:
15652 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15653 // CHECK13:       omp.inner.for.inc:
15654 // CHECK13-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
15655 // CHECK13-NEXT:    [[ADD7:%.*]] = add i64 [[TMP14]], 1
15656 // CHECK13-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
15657 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
15658 // CHECK13:       omp.inner.for.end:
15659 // CHECK13-NEXT:    br label [[OMP_IF_END:%.*]]
15660 // CHECK13:       omp_if.else:
15661 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND8:%.*]]
15662 // CHECK13:       omp.inner.for.cond8:
15663 // CHECK13-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
15664 // CHECK13-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
15665 // CHECK13-NEXT:    [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]]
15666 // CHECK13-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
15667 // CHECK13:       omp.inner.for.body10:
15668 // CHECK13-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
15669 // CHECK13-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP17]], 400
15670 // CHECK13-NEXT:    [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
15671 // CHECK13-NEXT:    store i64 [[SUB12]], i64* [[IT]], align 8
15672 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[B]], align 4
15673 // CHECK13-NEXT:    [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double
15674 // CHECK13-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
15675 // CHECK13-NEXT:    [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
15676 // CHECK13-NEXT:    store double [[ADD14]], double* [[A15]], align 8
15677 // CHECK13-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
15678 // CHECK13-NEXT:    [[TMP19:%.*]] = load double, double* [[A16]], align 8
15679 // CHECK13-NEXT:    [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00
15680 // CHECK13-NEXT:    store double [[INC17]], double* [[A16]], align 8
15681 // CHECK13-NEXT:    [[CONV18:%.*]] = fptosi double [[INC17]] to i16
15682 // CHECK13-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
15683 // CHECK13-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
15684 // CHECK13-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1
15685 // CHECK13-NEXT:    store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
15686 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE21:%.*]]
15687 // CHECK13:       omp.body.continue21:
15688 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC22:%.*]]
15689 // CHECK13:       omp.inner.for.inc22:
15690 // CHECK13-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
15691 // CHECK13-NEXT:    [[ADD23:%.*]] = add i64 [[TMP21]], 1
15692 // CHECK13-NEXT:    store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
15693 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]]
15694 // CHECK13:       omp.inner.for.end24:
15695 // CHECK13-NEXT:    br label [[OMP_IF_END]]
15696 // CHECK13:       omp_if.end:
15697 // CHECK13-NEXT:    store i64 400, i64* [[IT]], align 8
15698 // CHECK13-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
15699 // CHECK13-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
15700 // CHECK13-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1
15701 // CHECK13-NEXT:    [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
15702 // CHECK13-NEXT:    [[CONV27:%.*]] = sext i16 [[TMP23]] to i32
15703 // CHECK13-NEXT:    [[TMP24:%.*]] = load i32, i32* [[B]], align 4
15704 // CHECK13-NEXT:    [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]]
15705 // CHECK13-NEXT:    [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
15706 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP25]])
15707 // CHECK13-NEXT:    ret i32 [[ADD28]]
15708 //
15709 //
15710 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
15711 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
15712 // CHECK13-NEXT:  entry:
15713 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15714 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
15715 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
15716 // CHECK13-NEXT:    [[AAA:%.*]] = alloca i8, align 1
15717 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15718 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15719 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15720 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15721 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15722 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
15723 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
15724 // CHECK13-NEXT:    store i8 0, i8* [[AAA]], align 1
15725 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15726 // CHECK13-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
15727 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
15728 // CHECK13-NEXT:    ret i32 [[TMP0]]
15729 //
15730 //
15731 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
15732 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
15733 // CHECK13-NEXT:  entry:
15734 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15735 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
15736 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
15737 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15738 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i64, align 8
15739 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
15740 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
15741 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
15742 // CHECK13-NEXT:    [[I:%.*]] = alloca i64, align 8
15743 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15744 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
15745 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
15746 // CHECK13-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
15747 // CHECK13-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
15748 // CHECK13-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
15749 // CHECK13-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
15750 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15751 // CHECK13:       omp.inner.for.cond:
15752 // CHECK13-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
15753 // CHECK13-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24
15754 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
15755 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15756 // CHECK13:       omp.inner.for.body:
15757 // CHECK13-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
15758 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
15759 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
15760 // CHECK13-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24
15761 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
15762 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
15763 // CHECK13-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
15764 // CHECK13-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
15765 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
15766 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
15767 // CHECK13-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
15768 // CHECK13-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
15769 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
15770 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
15771 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
15772 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
15773 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15774 // CHECK13:       omp.body.continue:
15775 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15776 // CHECK13:       omp.inner.for.inc:
15777 // CHECK13-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
15778 // CHECK13-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
15779 // CHECK13-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
15780 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
15781 // CHECK13:       omp.inner.for.end:
15782 // CHECK13-NEXT:    store i64 11, i64* [[I]], align 8
15783 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15784 // CHECK13-NEXT:    ret i32 [[TMP8]]
15785 //
15786 //
15787 // CHECK14-LABEL: define {{[^@]+}}@_Z7get_valv
15788 // CHECK14-SAME: () #[[ATTR0:[0-9]+]] {
15789 // CHECK14-NEXT:  entry:
15790 // CHECK14-NEXT:    ret i64 0
15791 //
15792 //
15793 // CHECK14-LABEL: define {{[^@]+}}@_Z3fooi
15794 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
15795 // CHECK14-NEXT:  entry:
15796 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15797 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
15798 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
15799 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
15800 // CHECK14-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
15801 // CHECK14-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
15802 // CHECK14-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
15803 // CHECK14-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
15804 // CHECK14-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
15805 // CHECK14-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15806 // CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15807 // CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15808 // CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15809 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
15810 // CHECK14-NEXT:    [[K:%.*]] = alloca i64, align 8
15811 // CHECK14-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
15812 // CHECK14-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
15813 // CHECK14-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
15814 // CHECK14-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
15815 // CHECK14-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
15816 // CHECK14-NEXT:    [[I7:%.*]] = alloca i32, align 4
15817 // CHECK14-NEXT:    [[K8:%.*]] = alloca i64, align 8
15818 // CHECK14-NEXT:    [[LIN:%.*]] = alloca i32, align 4
15819 // CHECK14-NEXT:    [[_TMP21:%.*]] = alloca i64, align 8
15820 // CHECK14-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
15821 // CHECK14-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
15822 // CHECK14-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
15823 // CHECK14-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
15824 // CHECK14-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
15825 // CHECK14-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
15826 // CHECK14-NEXT:    [[IT:%.*]] = alloca i64, align 8
15827 // CHECK14-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
15828 // CHECK14-NEXT:    [[A29:%.*]] = alloca i32, align 4
15829 // CHECK14-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
15830 // CHECK14-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
15831 // CHECK14-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
15832 // CHECK14-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
15833 // CHECK14-NEXT:    [[IT62:%.*]] = alloca i16, align 2
15834 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
15835 // CHECK14-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
15836 // CHECK14-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
15837 // CHECK14-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
15838 // CHECK14-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
15839 // CHECK14-NEXT:    [[IT81:%.*]] = alloca i8, align 1
15840 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15841 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
15842 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
15843 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15844 // CHECK14-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
15845 // CHECK14-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
15846 // CHECK14-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
15847 // CHECK14-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
15848 // CHECK14-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
15849 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
15850 // CHECK14-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
15851 // CHECK14-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
15852 // CHECK14-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
15853 // CHECK14-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
15854 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15855 // CHECK14-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
15856 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15857 // CHECK14-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
15858 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15859 // CHECK14:       omp.inner.for.cond:
15860 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15861 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
15862 // CHECK14-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
15863 // CHECK14-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15864 // CHECK14:       omp.inner.for.body:
15865 // CHECK14-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15866 // CHECK14-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
15867 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
15868 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
15869 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15870 // CHECK14:       omp.body.continue:
15871 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15872 // CHECK14:       omp.inner.for.inc:
15873 // CHECK14-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15874 // CHECK14-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
15875 // CHECK14-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15876 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
15877 // CHECK14:       omp.inner.for.end:
15878 // CHECK14-NEXT:    store i32 33, i32* [[I]], align 4
15879 // CHECK14-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
15880 // CHECK14-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
15881 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
15882 // CHECK14-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
15883 // CHECK14-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
15884 // CHECK14-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
15885 // CHECK14-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K]], align 8
15886 // CHECK14-NEXT:    store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
15887 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
15888 // CHECK14:       omp.inner.for.cond9:
15889 // CHECK14-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
15890 // CHECK14-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
15891 // CHECK14-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
15892 // CHECK14-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
15893 // CHECK14:       omp.inner.for.body11:
15894 // CHECK14-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
15895 // CHECK14-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
15896 // CHECK14-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
15897 // CHECK14-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
15898 // CHECK14-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
15899 // CHECK14-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
15900 // CHECK14-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
15901 // CHECK14-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
15902 // CHECK14-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
15903 // CHECK14-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
15904 // CHECK14-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
15905 // CHECK14-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
15906 // CHECK14-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
15907 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
15908 // CHECK14:       omp.body.continue16:
15909 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
15910 // CHECK14:       omp.inner.for.inc17:
15911 // CHECK14-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
15912 // CHECK14-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
15913 // CHECK14-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
15914 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
15915 // CHECK14:       omp.inner.for.end19:
15916 // CHECK14-NEXT:    store i32 1, i32* [[I7]], align 4
15917 // CHECK14-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
15918 // CHECK14-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
15919 // CHECK14-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
15920 // CHECK14-NEXT:    store i32 12, i32* [[LIN]], align 4
15921 // CHECK14-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
15922 // CHECK14-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
15923 // CHECK14-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
15924 // CHECK14-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
15925 // CHECK14-NEXT:    [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
15926 // CHECK14-NEXT:    store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
15927 // CHECK14-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A]], align 4
15928 // CHECK14-NEXT:    store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
15929 // CHECK14-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
15930 // CHECK14-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
15931 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
15932 // CHECK14:       omp.inner.for.cond30:
15933 // CHECK14-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15934 // CHECK14-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
15935 // CHECK14-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
15936 // CHECK14-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
15937 // CHECK14:       omp.inner.for.body32:
15938 // CHECK14-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15939 // CHECK14-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP26]], 400
15940 // CHECK14-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
15941 // CHECK14-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
15942 // CHECK14-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
15943 // CHECK14-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
15944 // CHECK14-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15945 // CHECK14-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
15946 // CHECK14-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
15947 // CHECK14-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
15948 // CHECK14-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
15949 // CHECK14-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
15950 // CHECK14-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
15951 // CHECK14-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
15952 // CHECK14-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15953 // CHECK14-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
15954 // CHECK14-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
15955 // CHECK14-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
15956 // CHECK14-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
15957 // CHECK14-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
15958 // CHECK14-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
15959 // CHECK14-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
15960 // CHECK14-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
15961 // CHECK14-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
15962 // CHECK14-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
15963 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
15964 // CHECK14:       omp.body.continue46:
15965 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
15966 // CHECK14:       omp.inner.for.inc47:
15967 // CHECK14-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15968 // CHECK14-NEXT:    [[ADD48:%.*]] = add i64 [[TMP34]], 1
15969 // CHECK14-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
15970 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
15971 // CHECK14:       omp.inner.for.end49:
15972 // CHECK14-NEXT:    store i64 400, i64* [[IT]], align 8
15973 // CHECK14-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
15974 // CHECK14-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
15975 // CHECK14-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
15976 // CHECK14-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP36]]
15977 // CHECK14-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
15978 // CHECK14-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
15979 // CHECK14-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
15980 // CHECK14-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
15981 // CHECK14-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
15982 // CHECK14-NEXT:    [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
15983 // CHECK14-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP38]]
15984 // CHECK14-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
15985 // CHECK14-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
15986 // CHECK14-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
15987 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
15988 // CHECK14-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
15989 // CHECK14-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
15990 // CHECK14-NEXT:    store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
15991 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
15992 // CHECK14:       omp.inner.for.cond63:
15993 // CHECK14-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
15994 // CHECK14-NEXT:    [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
15995 // CHECK14-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
15996 // CHECK14-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
15997 // CHECK14:       omp.inner.for.body65:
15998 // CHECK14-NEXT:    [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
15999 // CHECK14-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
16000 // CHECK14-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
16001 // CHECK14-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
16002 // CHECK14-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
16003 // CHECK14-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
16004 // CHECK14-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
16005 // CHECK14-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
16006 // CHECK14-NEXT:    [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
16007 // CHECK14-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
16008 // CHECK14-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
16009 // CHECK14-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
16010 // CHECK14-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
16011 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
16012 // CHECK14:       omp.body.continue73:
16013 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
16014 // CHECK14:       omp.inner.for.inc74:
16015 // CHECK14-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
16016 // CHECK14-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
16017 // CHECK14-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
16018 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
16019 // CHECK14:       omp.inner.for.end76:
16020 // CHECK14-NEXT:    store i16 22, i16* [[IT62]], align 2
16021 // CHECK14-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
16022 // CHECK14-NEXT:    store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
16023 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
16024 // CHECK14-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
16025 // CHECK14-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
16026 // CHECK14-NEXT:    store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
16027 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
16028 // CHECK14:       omp.inner.for.cond82:
16029 // CHECK14-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
16030 // CHECK14-NEXT:    [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
16031 // CHECK14-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
16032 // CHECK14-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
16033 // CHECK14:       omp.inner.for.body84:
16034 // CHECK14-NEXT:    [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
16035 // CHECK14-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
16036 // CHECK14-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
16037 // CHECK14-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
16038 // CHECK14-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
16039 // CHECK14-NEXT:    [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
16040 // CHECK14-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
16041 // CHECK14-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
16042 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
16043 // CHECK14-NEXT:    [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
16044 // CHECK14-NEXT:    [[CONV89:%.*]] = fpext float [[TMP52]] to double
16045 // CHECK14-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
16046 // CHECK14-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
16047 // CHECK14-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
16048 // CHECK14-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
16049 // CHECK14-NEXT:    [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
16050 // CHECK14-NEXT:    [[CONV93:%.*]] = fpext float [[TMP53]] to double
16051 // CHECK14-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
16052 // CHECK14-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
16053 // CHECK14-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
16054 // CHECK14-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
16055 // CHECK14-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
16056 // CHECK14-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
16057 // CHECK14-NEXT:    [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
16058 // CHECK14-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
16059 // CHECK14-NEXT:    [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
16060 // CHECK14-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
16061 // CHECK14-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
16062 // CHECK14-NEXT:    [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
16063 // CHECK14-NEXT:    [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
16064 // CHECK14-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
16065 // CHECK14-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
16066 // CHECK14-NEXT:    [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
16067 // CHECK14-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
16068 // CHECK14-NEXT:    store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
16069 // CHECK14-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
16070 // CHECK14-NEXT:    [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
16071 // CHECK14-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
16072 // CHECK14-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
16073 // CHECK14-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
16074 // CHECK14-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
16075 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
16076 // CHECK14:       omp.body.continue106:
16077 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
16078 // CHECK14:       omp.inner.for.inc107:
16079 // CHECK14-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
16080 // CHECK14-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
16081 // CHECK14-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
16082 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
16083 // CHECK14:       omp.inner.for.end109:
16084 // CHECK14-NEXT:    store i8 96, i8* [[IT81]], align 1
16085 // CHECK14-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
16086 // CHECK14-NEXT:    [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
16087 // CHECK14-NEXT:    call void @llvm.stackrestore(i8* [[TMP61]])
16088 // CHECK14-NEXT:    ret i32 [[TMP60]]
16089 //
16090 //
16091 // CHECK14-LABEL: define {{[^@]+}}@_Z3bari
16092 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
16093 // CHECK14-NEXT:  entry:
16094 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16095 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
16096 // CHECK14-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
16097 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16098 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
16099 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16100 // CHECK14-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
16101 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
16102 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
16103 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
16104 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
16105 // CHECK14-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
16106 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
16107 // CHECK14-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
16108 // CHECK14-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
16109 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
16110 // CHECK14-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
16111 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
16112 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
16113 // CHECK14-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
16114 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
16115 // CHECK14-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
16116 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
16117 // CHECK14-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
16118 // CHECK14-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
16119 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
16120 // CHECK14-NEXT:    ret i32 [[TMP8]]
16121 //
16122 //
16123 // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
16124 // CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
16125 // CHECK14-NEXT:  entry:
16126 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
16127 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16128 // CHECK14-NEXT:    [[B:%.*]] = alloca i32, align 4
16129 // CHECK14-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
16130 // CHECK14-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
16131 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
16132 // CHECK14-NEXT:    [[TMP:%.*]] = alloca i64, align 8
16133 // CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
16134 // CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
16135 // CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
16136 // CHECK14-NEXT:    [[IT:%.*]] = alloca i64, align 8
16137 // CHECK14-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
16138 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16139 // CHECK14-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
16140 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16141 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
16142 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
16143 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
16144 // CHECK14-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
16145 // CHECK14-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
16146 // CHECK14-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
16147 // CHECK14-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
16148 // CHECK14-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
16149 // CHECK14-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
16150 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
16151 // CHECK14-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
16152 // CHECK14-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
16153 // CHECK14-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
16154 // CHECK14-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
16155 // CHECK14-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
16156 // CHECK14-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
16157 // CHECK14-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
16158 // CHECK14-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16159 // CHECK14-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
16160 // CHECK14-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
16161 // CHECK14:       omp_if.then:
16162 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16163 // CHECK14:       omp.inner.for.cond:
16164 // CHECK14-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
16165 // CHECK14-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
16166 // CHECK14-NEXT:    [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]]
16167 // CHECK14-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16168 // CHECK14:       omp.inner.for.body:
16169 // CHECK14-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
16170 // CHECK14-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 400
16171 // CHECK14-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
16172 // CHECK14-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
16173 // CHECK14-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
16174 // CHECK14-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
16175 // CHECK14-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
16176 // CHECK14-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
16177 // CHECK14-NEXT:    store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18
16178 // CHECK14-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
16179 // CHECK14-NEXT:    [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
16180 // CHECK14-NEXT:    [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
16181 // CHECK14-NEXT:    store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
16182 // CHECK14-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
16183 // CHECK14-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
16184 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
16185 // CHECK14-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
16186 // CHECK14-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
16187 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16188 // CHECK14:       omp.body.continue:
16189 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16190 // CHECK14:       omp.inner.for.inc:
16191 // CHECK14-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
16192 // CHECK14-NEXT:    [[ADD7:%.*]] = add i64 [[TMP14]], 1
16193 // CHECK14-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
16194 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
16195 // CHECK14:       omp.inner.for.end:
16196 // CHECK14-NEXT:    br label [[OMP_IF_END:%.*]]
16197 // CHECK14:       omp_if.else:
16198 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND8:%.*]]
16199 // CHECK14:       omp.inner.for.cond8:
16200 // CHECK14-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16201 // CHECK14-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
16202 // CHECK14-NEXT:    [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]]
16203 // CHECK14-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
16204 // CHECK14:       omp.inner.for.body10:
16205 // CHECK14-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16206 // CHECK14-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP17]], 400
16207 // CHECK14-NEXT:    [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
16208 // CHECK14-NEXT:    store i64 [[SUB12]], i64* [[IT]], align 8
16209 // CHECK14-NEXT:    [[TMP18:%.*]] = load i32, i32* [[B]], align 4
16210 // CHECK14-NEXT:    [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double
16211 // CHECK14-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
16212 // CHECK14-NEXT:    [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
16213 // CHECK14-NEXT:    store double [[ADD14]], double* [[A15]], align 8
16214 // CHECK14-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
16215 // CHECK14-NEXT:    [[TMP19:%.*]] = load double, double* [[A16]], align 8
16216 // CHECK14-NEXT:    [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00
16217 // CHECK14-NEXT:    store double [[INC17]], double* [[A16]], align 8
16218 // CHECK14-NEXT:    [[CONV18:%.*]] = fptosi double [[INC17]] to i16
16219 // CHECK14-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
16220 // CHECK14-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
16221 // CHECK14-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1
16222 // CHECK14-NEXT:    store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
16223 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE21:%.*]]
16224 // CHECK14:       omp.body.continue21:
16225 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC22:%.*]]
16226 // CHECK14:       omp.inner.for.inc22:
16227 // CHECK14-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16228 // CHECK14-NEXT:    [[ADD23:%.*]] = add i64 [[TMP21]], 1
16229 // CHECK14-NEXT:    store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
16230 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]]
16231 // CHECK14:       omp.inner.for.end24:
16232 // CHECK14-NEXT:    br label [[OMP_IF_END]]
16233 // CHECK14:       omp_if.end:
16234 // CHECK14-NEXT:    store i64 400, i64* [[IT]], align 8
16235 // CHECK14-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
16236 // CHECK14-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
16237 // CHECK14-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1
16238 // CHECK14-NEXT:    [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
16239 // CHECK14-NEXT:    [[CONV27:%.*]] = sext i16 [[TMP23]] to i32
16240 // CHECK14-NEXT:    [[TMP24:%.*]] = load i32, i32* [[B]], align 4
16241 // CHECK14-NEXT:    [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]]
16242 // CHECK14-NEXT:    [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
16243 // CHECK14-NEXT:    call void @llvm.stackrestore(i8* [[TMP25]])
16244 // CHECK14-NEXT:    ret i32 [[ADD28]]
16245 //
16246 //
16247 // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici
16248 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
16249 // CHECK14-NEXT:  entry:
16250 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16251 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
16252 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
16253 // CHECK14-NEXT:    [[AAA:%.*]] = alloca i8, align 1
16254 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
16255 // CHECK14-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16256 // CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16257 // CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16258 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16259 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
16260 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
16261 // CHECK14-NEXT:    store i8 0, i8* [[AAA]], align 1
16262 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16263 // CHECK14-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
16264 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
16265 // CHECK14-NEXT:    ret i32 [[TMP0]]
16266 //
16267 //
16268 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
16269 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
16270 // CHECK14-NEXT:  entry:
16271 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16272 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
16273 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
16274 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
16275 // CHECK14-NEXT:    [[TMP:%.*]] = alloca i64, align 8
16276 // CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
16277 // CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
16278 // CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
16279 // CHECK14-NEXT:    [[I:%.*]] = alloca i64, align 8
16280 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16281 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
16282 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
16283 // CHECK14-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
16284 // CHECK14-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
16285 // CHECK14-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
16286 // CHECK14-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
16287 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16288 // CHECK14:       omp.inner.for.cond:
16289 // CHECK14-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
16290 // CHECK14-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24
16291 // CHECK14-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
16292 // CHECK14-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16293 // CHECK14:       omp.inner.for.body:
16294 // CHECK14-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
16295 // CHECK14-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
16296 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
16297 // CHECK14-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24
16298 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
16299 // CHECK14-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
16300 // CHECK14-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
16301 // CHECK14-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
16302 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
16303 // CHECK14-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
16304 // CHECK14-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
16305 // CHECK14-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
16306 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
16307 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
16308 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
16309 // CHECK14-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
16310 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16311 // CHECK14:       omp.body.continue:
16312 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16313 // CHECK14:       omp.inner.for.inc:
16314 // CHECK14-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
16315 // CHECK14-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
16316 // CHECK14-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
16317 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
16318 // CHECK14:       omp.inner.for.end:
16319 // CHECK14-NEXT:    store i64 11, i64* [[I]], align 8
16320 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
16321 // CHECK14-NEXT:    ret i32 [[TMP8]]
16322 //
16323 //
16324 // CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv
16325 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] {
16326 // CHECK15-NEXT:  entry:
16327 // CHECK15-NEXT:    ret i64 0
16328 //
16329 //
16330 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi
16331 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
16332 // CHECK15-NEXT:  entry:
16333 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16334 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
16335 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
16336 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
16337 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
16338 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
16339 // CHECK15-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
16340 // CHECK15-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
16341 // CHECK15-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
16342 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16343 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16344 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16345 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16346 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
16347 // CHECK15-NEXT:    [[K:%.*]] = alloca i64, align 8
16348 // CHECK15-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
16349 // CHECK15-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
16350 // CHECK15-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
16351 // CHECK15-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
16352 // CHECK15-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
16353 // CHECK15-NEXT:    [[I7:%.*]] = alloca i32, align 4
16354 // CHECK15-NEXT:    [[K8:%.*]] = alloca i64, align 8
16355 // CHECK15-NEXT:    [[LIN:%.*]] = alloca i32, align 4
16356 // CHECK15-NEXT:    [[_TMP21:%.*]] = alloca i64, align 4
16357 // CHECK15-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
16358 // CHECK15-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
16359 // CHECK15-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
16360 // CHECK15-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
16361 // CHECK15-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
16362 // CHECK15-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
16363 // CHECK15-NEXT:    [[IT:%.*]] = alloca i64, align 8
16364 // CHECK15-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
16365 // CHECK15-NEXT:    [[A29:%.*]] = alloca i32, align 4
16366 // CHECK15-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
16367 // CHECK15-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
16368 // CHECK15-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
16369 // CHECK15-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
16370 // CHECK15-NEXT:    [[IT62:%.*]] = alloca i16, align 2
16371 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
16372 // CHECK15-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
16373 // CHECK15-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
16374 // CHECK15-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
16375 // CHECK15-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
16376 // CHECK15-NEXT:    [[IT81:%.*]] = alloca i8, align 1
16377 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16378 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
16379 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
16380 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16381 // CHECK15-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
16382 // CHECK15-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
16383 // CHECK15-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
16384 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
16385 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
16386 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
16387 // CHECK15-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
16388 // CHECK15-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
16389 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16390 // CHECK15-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
16391 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16392 // CHECK15-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
16393 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16394 // CHECK15:       omp.inner.for.cond:
16395 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16396 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
16397 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
16398 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16399 // CHECK15:       omp.inner.for.body:
16400 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16401 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
16402 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
16403 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
16404 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16405 // CHECK15:       omp.body.continue:
16406 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16407 // CHECK15:       omp.inner.for.inc:
16408 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16409 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
16410 // CHECK15-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16411 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
16412 // CHECK15:       omp.inner.for.end:
16413 // CHECK15-NEXT:    store i32 33, i32* [[I]], align 4
16414 // CHECK15-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
16415 // CHECK15-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
16416 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
16417 // CHECK15-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
16418 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
16419 // CHECK15-NEXT:    store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
16420 // CHECK15-NEXT:    [[TMP10:%.*]] = load i64, i64* [[K]], align 8
16421 // CHECK15-NEXT:    store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
16422 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
16423 // CHECK15:       omp.inner.for.cond9:
16424 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
16425 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
16426 // CHECK15-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
16427 // CHECK15-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
16428 // CHECK15:       omp.inner.for.body11:
16429 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
16430 // CHECK15-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
16431 // CHECK15-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
16432 // CHECK15-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
16433 // CHECK15-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
16434 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
16435 // CHECK15-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
16436 // CHECK15-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
16437 // CHECK15-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
16438 // CHECK15-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
16439 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
16440 // CHECK15-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
16441 // CHECK15-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
16442 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
16443 // CHECK15:       omp.body.continue16:
16444 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
16445 // CHECK15:       omp.inner.for.inc17:
16446 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
16447 // CHECK15-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
16448 // CHECK15-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
16449 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
16450 // CHECK15:       omp.inner.for.end19:
16451 // CHECK15-NEXT:    store i32 1, i32* [[I7]], align 4
16452 // CHECK15-NEXT:    [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
16453 // CHECK15-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
16454 // CHECK15-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
16455 // CHECK15-NEXT:    store i32 12, i32* [[LIN]], align 4
16456 // CHECK15-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
16457 // CHECK15-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
16458 // CHECK15-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
16459 // CHECK15-NEXT:    store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
16460 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
16461 // CHECK15-NEXT:    store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
16462 // CHECK15-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
16463 // CHECK15-NEXT:    store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
16464 // CHECK15-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
16465 // CHECK15-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
16466 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
16467 // CHECK15:       omp.inner.for.cond30:
16468 // CHECK15-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
16469 // CHECK15-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
16470 // CHECK15-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
16471 // CHECK15-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
16472 // CHECK15:       omp.inner.for.body32:
16473 // CHECK15-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
16474 // CHECK15-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP24]], 400
16475 // CHECK15-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
16476 // CHECK15-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
16477 // CHECK15-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
16478 // CHECK15-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
16479 // CHECK15-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
16480 // CHECK15-NEXT:    [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
16481 // CHECK15-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
16482 // CHECK15-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
16483 // CHECK15-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
16484 // CHECK15-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
16485 // CHECK15-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
16486 // CHECK15-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
16487 // CHECK15-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
16488 // CHECK15-NEXT:    [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
16489 // CHECK15-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
16490 // CHECK15-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
16491 // CHECK15-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
16492 // CHECK15-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
16493 // CHECK15-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
16494 // CHECK15-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
16495 // CHECK15-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
16496 // CHECK15-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
16497 // CHECK15-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
16498 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
16499 // CHECK15:       omp.body.continue46:
16500 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
16501 // CHECK15:       omp.inner.for.inc47:
16502 // CHECK15-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
16503 // CHECK15-NEXT:    [[ADD48:%.*]] = add i64 [[TMP32]], 1
16504 // CHECK15-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
16505 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
16506 // CHECK15:       omp.inner.for.end49:
16507 // CHECK15-NEXT:    store i64 400, i64* [[IT]], align 8
16508 // CHECK15-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
16509 // CHECK15-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
16510 // CHECK15-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
16511 // CHECK15-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP34]]
16512 // CHECK15-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
16513 // CHECK15-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
16514 // CHECK15-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
16515 // CHECK15-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
16516 // CHECK15-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
16517 // CHECK15-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
16518 // CHECK15-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP36]]
16519 // CHECK15-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
16520 // CHECK15-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
16521 // CHECK15-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
16522 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
16523 // CHECK15-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
16524 // CHECK15-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
16525 // CHECK15-NEXT:    store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
16526 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
16527 // CHECK15:       omp.inner.for.cond63:
16528 // CHECK15-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
16529 // CHECK15-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
16530 // CHECK15-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
16531 // CHECK15-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
16532 // CHECK15:       omp.inner.for.body65:
16533 // CHECK15-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
16534 // CHECK15-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
16535 // CHECK15-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
16536 // CHECK15-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
16537 // CHECK15-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
16538 // CHECK15-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
16539 // CHECK15-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
16540 // CHECK15-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
16541 // CHECK15-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
16542 // CHECK15-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
16543 // CHECK15-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
16544 // CHECK15-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
16545 // CHECK15-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
16546 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
16547 // CHECK15:       omp.body.continue73:
16548 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
16549 // CHECK15:       omp.inner.for.inc74:
16550 // CHECK15-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
16551 // CHECK15-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
16552 // CHECK15-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
16553 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
16554 // CHECK15:       omp.inner.for.end76:
16555 // CHECK15-NEXT:    store i16 22, i16* [[IT62]], align 2
16556 // CHECK15-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
16557 // CHECK15-NEXT:    store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
16558 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
16559 // CHECK15-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
16560 // CHECK15-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
16561 // CHECK15-NEXT:    store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
16562 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
16563 // CHECK15:       omp.inner.for.cond82:
16564 // CHECK15-NEXT:    [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
16565 // CHECK15-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
16566 // CHECK15-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
16567 // CHECK15-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
16568 // CHECK15:       omp.inner.for.body84:
16569 // CHECK15-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
16570 // CHECK15-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
16571 // CHECK15-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
16572 // CHECK15-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
16573 // CHECK15-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
16574 // CHECK15-NEXT:    [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
16575 // CHECK15-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
16576 // CHECK15-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
16577 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
16578 // CHECK15-NEXT:    [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
16579 // CHECK15-NEXT:    [[CONV89:%.*]] = fpext float [[TMP50]] to double
16580 // CHECK15-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
16581 // CHECK15-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
16582 // CHECK15-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
16583 // CHECK15-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
16584 // CHECK15-NEXT:    [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
16585 // CHECK15-NEXT:    [[CONV93:%.*]] = fpext float [[TMP51]] to double
16586 // CHECK15-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
16587 // CHECK15-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
16588 // CHECK15-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
16589 // CHECK15-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
16590 // CHECK15-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
16591 // CHECK15-NEXT:    [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
16592 // CHECK15-NEXT:    [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
16593 // CHECK15-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
16594 // CHECK15-NEXT:    [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
16595 // CHECK15-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
16596 // CHECK15-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
16597 // CHECK15-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
16598 // CHECK15-NEXT:    [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
16599 // CHECK15-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
16600 // CHECK15-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
16601 // CHECK15-NEXT:    [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
16602 // CHECK15-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
16603 // CHECK15-NEXT:    store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
16604 // CHECK15-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
16605 // CHECK15-NEXT:    [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
16606 // CHECK15-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
16607 // CHECK15-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
16608 // CHECK15-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
16609 // CHECK15-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
16610 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
16611 // CHECK15:       omp.body.continue106:
16612 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
16613 // CHECK15:       omp.inner.for.inc107:
16614 // CHECK15-NEXT:    [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
16615 // CHECK15-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
16616 // CHECK15-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
16617 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
16618 // CHECK15:       omp.inner.for.end109:
16619 // CHECK15-NEXT:    store i8 96, i8* [[IT81]], align 1
16620 // CHECK15-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A]], align 4
16621 // CHECK15-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
16622 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
16623 // CHECK15-NEXT:    ret i32 [[TMP58]]
16624 //
16625 //
16626 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari
16627 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
16628 // CHECK15-NEXT:  entry:
16629 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16630 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
16631 // CHECK15-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
16632 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16633 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
16634 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16635 // CHECK15-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
16636 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
16637 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
16638 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
16639 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
16640 // CHECK15-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
16641 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
16642 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
16643 // CHECK15-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
16644 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
16645 // CHECK15-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
16646 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
16647 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
16648 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
16649 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
16650 // CHECK15-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
16651 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
16652 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
16653 // CHECK15-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
16654 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
16655 // CHECK15-NEXT:    ret i32 [[TMP8]]
16656 //
16657 //
16658 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
16659 // CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
16660 // CHECK15-NEXT:  entry:
16661 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
16662 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16663 // CHECK15-NEXT:    [[B:%.*]] = alloca i32, align 4
16664 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
16665 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
16666 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
16667 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i64, align 4
16668 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
16669 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
16670 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
16671 // CHECK15-NEXT:    [[IT:%.*]] = alloca i64, align 8
16672 // CHECK15-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
16673 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16674 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
16675 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16676 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
16677 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
16678 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
16679 // CHECK15-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
16680 // CHECK15-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
16681 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
16682 // CHECK15-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
16683 // CHECK15-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
16684 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
16685 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
16686 // CHECK15-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
16687 // CHECK15-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
16688 // CHECK15-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
16689 // CHECK15-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
16690 // CHECK15-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
16691 // CHECK15-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
16692 // CHECK15-NEXT:    [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16693 // CHECK15-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
16694 // CHECK15-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
16695 // CHECK15:       omp_if.then:
16696 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16697 // CHECK15:       omp.inner.for.cond:
16698 // CHECK15-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
16699 // CHECK15-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
16700 // CHECK15-NEXT:    [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
16701 // CHECK15-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16702 // CHECK15:       omp.inner.for.body:
16703 // CHECK15-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
16704 // CHECK15-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
16705 // CHECK15-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
16706 // CHECK15-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
16707 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
16708 // CHECK15-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
16709 // CHECK15-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
16710 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
16711 // CHECK15-NEXT:    store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19
16712 // CHECK15-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
16713 // CHECK15-NEXT:    [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
16714 // CHECK15-NEXT:    [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
16715 // CHECK15-NEXT:    store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
16716 // CHECK15-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
16717 // CHECK15-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
16718 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
16719 // CHECK15-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
16720 // CHECK15-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
16721 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16722 // CHECK15:       omp.body.continue:
16723 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16724 // CHECK15:       omp.inner.for.inc:
16725 // CHECK15-NEXT:    [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
16726 // CHECK15-NEXT:    [[ADD7:%.*]] = add i64 [[TMP13]], 1
16727 // CHECK15-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
16728 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
16729 // CHECK15:       omp.inner.for.end:
16730 // CHECK15-NEXT:    br label [[OMP_IF_END:%.*]]
16731 // CHECK15:       omp_if.else:
16732 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND8:%.*]]
16733 // CHECK15:       omp.inner.for.cond8:
16734 // CHECK15-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16735 // CHECK15-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
16736 // CHECK15-NEXT:    [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]]
16737 // CHECK15-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
16738 // CHECK15:       omp.inner.for.body10:
16739 // CHECK15-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16740 // CHECK15-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP16]], 400
16741 // CHECK15-NEXT:    [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
16742 // CHECK15-NEXT:    store i64 [[SUB12]], i64* [[IT]], align 8
16743 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[B]], align 4
16744 // CHECK15-NEXT:    [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double
16745 // CHECK15-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
16746 // CHECK15-NEXT:    [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
16747 // CHECK15-NEXT:    store double [[ADD14]], double* [[A15]], align 4
16748 // CHECK15-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
16749 // CHECK15-NEXT:    [[TMP18:%.*]] = load double, double* [[A16]], align 4
16750 // CHECK15-NEXT:    [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00
16751 // CHECK15-NEXT:    store double [[INC17]], double* [[A16]], align 4
16752 // CHECK15-NEXT:    [[CONV18:%.*]] = fptosi double [[INC17]] to i16
16753 // CHECK15-NEXT:    [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
16754 // CHECK15-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
16755 // CHECK15-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1
16756 // CHECK15-NEXT:    store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
16757 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE21:%.*]]
16758 // CHECK15:       omp.body.continue21:
16759 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC22:%.*]]
16760 // CHECK15:       omp.inner.for.inc22:
16761 // CHECK15-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
16762 // CHECK15-NEXT:    [[ADD23:%.*]] = add i64 [[TMP20]], 1
16763 // CHECK15-NEXT:    store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
16764 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]]
16765 // CHECK15:       omp.inner.for.end24:
16766 // CHECK15-NEXT:    br label [[OMP_IF_END]]
16767 // CHECK15:       omp_if.end:
16768 // CHECK15-NEXT:    store i64 400, i64* [[IT]], align 8
16769 // CHECK15-NEXT:    [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
16770 // CHECK15-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
16771 // CHECK15-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
16772 // CHECK15-NEXT:    [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
16773 // CHECK15-NEXT:    [[CONV27:%.*]] = sext i16 [[TMP22]] to i32
16774 // CHECK15-NEXT:    [[TMP23:%.*]] = load i32, i32* [[B]], align 4
16775 // CHECK15-NEXT:    [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]]
16776 // CHECK15-NEXT:    [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
16777 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP24]])
16778 // CHECK15-NEXT:    ret i32 [[ADD28]]
16779 //
16780 //
16781 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
16782 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
16783 // CHECK15-NEXT:  entry:
16784 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16785 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
16786 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
16787 // CHECK15-NEXT:    [[AAA:%.*]] = alloca i8, align 1
16788 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
16789 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16790 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16791 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16792 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16793 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
16794 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
16795 // CHECK15-NEXT:    store i8 0, i8* [[AAA]], align 1
16796 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16797 // CHECK15-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
16798 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
16799 // CHECK15-NEXT:    ret i32 [[TMP0]]
16800 //
16801 //
16802 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
16803 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
16804 // CHECK15-NEXT:  entry:
16805 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16806 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
16807 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
16808 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
16809 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i64, align 4
16810 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
16811 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
16812 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
16813 // CHECK15-NEXT:    [[I:%.*]] = alloca i64, align 8
16814 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16815 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
16816 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
16817 // CHECK15-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
16818 // CHECK15-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
16819 // CHECK15-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
16820 // CHECK15-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
16821 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16822 // CHECK15:       omp.inner.for.cond:
16823 // CHECK15-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
16824 // CHECK15-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25
16825 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
16826 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16827 // CHECK15:       omp.inner.for.body:
16828 // CHECK15-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
16829 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
16830 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
16831 // CHECK15-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25
16832 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
16833 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
16834 // CHECK15-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
16835 // CHECK15-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
16836 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
16837 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
16838 // CHECK15-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
16839 // CHECK15-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
16840 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
16841 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
16842 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
16843 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
16844 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16845 // CHECK15:       omp.body.continue:
16846 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16847 // CHECK15:       omp.inner.for.inc:
16848 // CHECK15-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
16849 // CHECK15-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
16850 // CHECK15-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
16851 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
16852 // CHECK15:       omp.inner.for.end:
16853 // CHECK15-NEXT:    store i64 11, i64* [[I]], align 8
16854 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
16855 // CHECK15-NEXT:    ret i32 [[TMP8]]
16856 //
16857 //
16858 // CHECK16-LABEL: define {{[^@]+}}@_Z7get_valv
16859 // CHECK16-SAME: () #[[ATTR0:[0-9]+]] {
16860 // CHECK16-NEXT:  entry:
16861 // CHECK16-NEXT:    ret i64 0
16862 //
16863 //
16864 // CHECK16-LABEL: define {{[^@]+}}@_Z3fooi
16865 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
16866 // CHECK16-NEXT:  entry:
16867 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16868 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
16869 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
16870 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
16871 // CHECK16-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
16872 // CHECK16-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
16873 // CHECK16-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
16874 // CHECK16-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
16875 // CHECK16-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
16876 // CHECK16-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16877 // CHECK16-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16878 // CHECK16-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16879 // CHECK16-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16880 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
16881 // CHECK16-NEXT:    [[K:%.*]] = alloca i64, align 8
16882 // CHECK16-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
16883 // CHECK16-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
16884 // CHECK16-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
16885 // CHECK16-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
16886 // CHECK16-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
16887 // CHECK16-NEXT:    [[I7:%.*]] = alloca i32, align 4
16888 // CHECK16-NEXT:    [[K8:%.*]] = alloca i64, align 8
16889 // CHECK16-NEXT:    [[LIN:%.*]] = alloca i32, align 4
16890 // CHECK16-NEXT:    [[_TMP21:%.*]] = alloca i64, align 4
16891 // CHECK16-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
16892 // CHECK16-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
16893 // CHECK16-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
16894 // CHECK16-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
16895 // CHECK16-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
16896 // CHECK16-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
16897 // CHECK16-NEXT:    [[IT:%.*]] = alloca i64, align 8
16898 // CHECK16-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
16899 // CHECK16-NEXT:    [[A29:%.*]] = alloca i32, align 4
16900 // CHECK16-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
16901 // CHECK16-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
16902 // CHECK16-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
16903 // CHECK16-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
16904 // CHECK16-NEXT:    [[IT62:%.*]] = alloca i16, align 2
16905 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
16906 // CHECK16-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
16907 // CHECK16-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
16908 // CHECK16-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
16909 // CHECK16-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
16910 // CHECK16-NEXT:    [[IT81:%.*]] = alloca i8, align 1
16911 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16912 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
16913 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
16914 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16915 // CHECK16-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
16916 // CHECK16-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
16917 // CHECK16-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
16918 // CHECK16-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
16919 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
16920 // CHECK16-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
16921 // CHECK16-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
16922 // CHECK16-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
16923 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16924 // CHECK16-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
16925 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16926 // CHECK16-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
16927 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16928 // CHECK16:       omp.inner.for.cond:
16929 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16930 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
16931 // CHECK16-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
16932 // CHECK16-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16933 // CHECK16:       omp.inner.for.body:
16934 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16935 // CHECK16-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
16936 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
16937 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
16938 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16939 // CHECK16:       omp.body.continue:
16940 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16941 // CHECK16:       omp.inner.for.inc:
16942 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16943 // CHECK16-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
16944 // CHECK16-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16945 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
16946 // CHECK16:       omp.inner.for.end:
16947 // CHECK16-NEXT:    store i32 33, i32* [[I]], align 4
16948 // CHECK16-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
16949 // CHECK16-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
16950 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
16951 // CHECK16-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
16952 // CHECK16-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
16953 // CHECK16-NEXT:    store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
16954 // CHECK16-NEXT:    [[TMP10:%.*]] = load i64, i64* [[K]], align 8
16955 // CHECK16-NEXT:    store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
16956 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
16957 // CHECK16:       omp.inner.for.cond9:
16958 // CHECK16-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
16959 // CHECK16-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
16960 // CHECK16-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
16961 // CHECK16-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
16962 // CHECK16:       omp.inner.for.body11:
16963 // CHECK16-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
16964 // CHECK16-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
16965 // CHECK16-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
16966 // CHECK16-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
16967 // CHECK16-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
16968 // CHECK16-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
16969 // CHECK16-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
16970 // CHECK16-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
16971 // CHECK16-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
16972 // CHECK16-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
16973 // CHECK16-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
16974 // CHECK16-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
16975 // CHECK16-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
16976 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
16977 // CHECK16:       omp.body.continue16:
16978 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
16979 // CHECK16:       omp.inner.for.inc17:
16980 // CHECK16-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
16981 // CHECK16-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
16982 // CHECK16-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
16983 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
16984 // CHECK16:       omp.inner.for.end19:
16985 // CHECK16-NEXT:    store i32 1, i32* [[I7]], align 4
16986 // CHECK16-NEXT:    [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
16987 // CHECK16-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
16988 // CHECK16-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
16989 // CHECK16-NEXT:    store i32 12, i32* [[LIN]], align 4
16990 // CHECK16-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
16991 // CHECK16-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
16992 // CHECK16-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
16993 // CHECK16-NEXT:    store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
16994 // CHECK16-NEXT:    [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
16995 // CHECK16-NEXT:    store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
16996 // CHECK16-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
16997 // CHECK16-NEXT:    store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
16998 // CHECK16-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
16999 // CHECK16-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
17000 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
17001 // CHECK16:       omp.inner.for.cond30:
17002 // CHECK16-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
17003 // CHECK16-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
17004 // CHECK16-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
17005 // CHECK16-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
17006 // CHECK16:       omp.inner.for.body32:
17007 // CHECK16-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
17008 // CHECK16-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP24]], 400
17009 // CHECK16-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
17010 // CHECK16-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
17011 // CHECK16-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
17012 // CHECK16-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
17013 // CHECK16-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
17014 // CHECK16-NEXT:    [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
17015 // CHECK16-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
17016 // CHECK16-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
17017 // CHECK16-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
17018 // CHECK16-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
17019 // CHECK16-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
17020 // CHECK16-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
17021 // CHECK16-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
17022 // CHECK16-NEXT:    [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
17023 // CHECK16-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
17024 // CHECK16-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
17025 // CHECK16-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
17026 // CHECK16-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
17027 // CHECK16-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
17028 // CHECK16-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
17029 // CHECK16-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
17030 // CHECK16-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
17031 // CHECK16-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
17032 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
17033 // CHECK16:       omp.body.continue46:
17034 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
17035 // CHECK16:       omp.inner.for.inc47:
17036 // CHECK16-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
17037 // CHECK16-NEXT:    [[ADD48:%.*]] = add i64 [[TMP32]], 1
17038 // CHECK16-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
17039 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
17040 // CHECK16:       omp.inner.for.end49:
17041 // CHECK16-NEXT:    store i64 400, i64* [[IT]], align 8
17042 // CHECK16-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
17043 // CHECK16-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
17044 // CHECK16-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
17045 // CHECK16-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP34]]
17046 // CHECK16-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
17047 // CHECK16-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
17048 // CHECK16-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
17049 // CHECK16-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
17050 // CHECK16-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
17051 // CHECK16-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
17052 // CHECK16-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP36]]
17053 // CHECK16-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
17054 // CHECK16-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
17055 // CHECK16-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
17056 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
17057 // CHECK16-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
17058 // CHECK16-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
17059 // CHECK16-NEXT:    store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
17060 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
17061 // CHECK16:       omp.inner.for.cond63:
17062 // CHECK16-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
17063 // CHECK16-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
17064 // CHECK16-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
17065 // CHECK16-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
17066 // CHECK16:       omp.inner.for.body65:
17067 // CHECK16-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
17068 // CHECK16-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
17069 // CHECK16-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
17070 // CHECK16-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
17071 // CHECK16-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
17072 // CHECK16-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
17073 // CHECK16-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
17074 // CHECK16-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
17075 // CHECK16-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
17076 // CHECK16-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
17077 // CHECK16-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
17078 // CHECK16-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
17079 // CHECK16-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
17080 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
17081 // CHECK16:       omp.body.continue73:
17082 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
17083 // CHECK16:       omp.inner.for.inc74:
17084 // CHECK16-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
17085 // CHECK16-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
17086 // CHECK16-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
17087 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
17088 // CHECK16:       omp.inner.for.end76:
17089 // CHECK16-NEXT:    store i16 22, i16* [[IT62]], align 2
17090 // CHECK16-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
17091 // CHECK16-NEXT:    store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
17092 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
17093 // CHECK16-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
17094 // CHECK16-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
17095 // CHECK16-NEXT:    store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
17096 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
17097 // CHECK16:       omp.inner.for.cond82:
17098 // CHECK16-NEXT:    [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
17099 // CHECK16-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
17100 // CHECK16-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
17101 // CHECK16-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
17102 // CHECK16:       omp.inner.for.body84:
17103 // CHECK16-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
17104 // CHECK16-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
17105 // CHECK16-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
17106 // CHECK16-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
17107 // CHECK16-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
17108 // CHECK16-NEXT:    [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
17109 // CHECK16-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
17110 // CHECK16-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
17111 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
17112 // CHECK16-NEXT:    [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
17113 // CHECK16-NEXT:    [[CONV89:%.*]] = fpext float [[TMP50]] to double
17114 // CHECK16-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
17115 // CHECK16-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
17116 // CHECK16-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
17117 // CHECK16-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
17118 // CHECK16-NEXT:    [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
17119 // CHECK16-NEXT:    [[CONV93:%.*]] = fpext float [[TMP51]] to double
17120 // CHECK16-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
17121 // CHECK16-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
17122 // CHECK16-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
17123 // CHECK16-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
17124 // CHECK16-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
17125 // CHECK16-NEXT:    [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
17126 // CHECK16-NEXT:    [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
17127 // CHECK16-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
17128 // CHECK16-NEXT:    [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
17129 // CHECK16-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
17130 // CHECK16-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
17131 // CHECK16-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
17132 // CHECK16-NEXT:    [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
17133 // CHECK16-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
17134 // CHECK16-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
17135 // CHECK16-NEXT:    [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
17136 // CHECK16-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
17137 // CHECK16-NEXT:    store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
17138 // CHECK16-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
17139 // CHECK16-NEXT:    [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
17140 // CHECK16-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
17141 // CHECK16-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
17142 // CHECK16-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
17143 // CHECK16-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
17144 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
17145 // CHECK16:       omp.body.continue106:
17146 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
17147 // CHECK16:       omp.inner.for.inc107:
17148 // CHECK16-NEXT:    [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
17149 // CHECK16-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
17150 // CHECK16-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
17151 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
17152 // CHECK16:       omp.inner.for.end109:
17153 // CHECK16-NEXT:    store i8 96, i8* [[IT81]], align 1
17154 // CHECK16-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A]], align 4
17155 // CHECK16-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
17156 // CHECK16-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
17157 // CHECK16-NEXT:    ret i32 [[TMP58]]
17158 //
17159 //
17160 // CHECK16-LABEL: define {{[^@]+}}@_Z3bari
17161 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
17162 // CHECK16-NEXT:  entry:
17163 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17164 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
17165 // CHECK16-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
17166 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17167 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
17168 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17169 // CHECK16-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
17170 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
17171 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
17172 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
17173 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
17174 // CHECK16-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
17175 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
17176 // CHECK16-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
17177 // CHECK16-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
17178 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
17179 // CHECK16-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
17180 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
17181 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
17182 // CHECK16-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
17183 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
17184 // CHECK16-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
17185 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
17186 // CHECK16-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
17187 // CHECK16-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
17188 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
17189 // CHECK16-NEXT:    ret i32 [[TMP8]]
17190 //
17191 //
17192 // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
17193 // CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
17194 // CHECK16-NEXT:  entry:
17195 // CHECK16-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
17196 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17197 // CHECK16-NEXT:    [[B:%.*]] = alloca i32, align 4
17198 // CHECK16-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
17199 // CHECK16-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
17200 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
17201 // CHECK16-NEXT:    [[TMP:%.*]] = alloca i64, align 4
17202 // CHECK16-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
17203 // CHECK16-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
17204 // CHECK16-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
17205 // CHECK16-NEXT:    [[IT:%.*]] = alloca i64, align 8
17206 // CHECK16-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
17207 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17208 // CHECK16-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
17209 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17210 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
17211 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
17212 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
17213 // CHECK16-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
17214 // CHECK16-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
17215 // CHECK16-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
17216 // CHECK16-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
17217 // CHECK16-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
17218 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
17219 // CHECK16-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
17220 // CHECK16-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
17221 // CHECK16-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
17222 // CHECK16-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
17223 // CHECK16-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
17224 // CHECK16-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
17225 // CHECK16-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
17226 // CHECK16-NEXT:    [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17227 // CHECK16-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
17228 // CHECK16-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17229 // CHECK16:       omp_if.then:
17230 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17231 // CHECK16:       omp.inner.for.cond:
17232 // CHECK16-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
17233 // CHECK16-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
17234 // CHECK16-NEXT:    [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
17235 // CHECK16-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17236 // CHECK16:       omp.inner.for.body:
17237 // CHECK16-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
17238 // CHECK16-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
17239 // CHECK16-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
17240 // CHECK16-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
17241 // CHECK16-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
17242 // CHECK16-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
17243 // CHECK16-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
17244 // CHECK16-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
17245 // CHECK16-NEXT:    store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19
17246 // CHECK16-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
17247 // CHECK16-NEXT:    [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
17248 // CHECK16-NEXT:    [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
17249 // CHECK16-NEXT:    store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
17250 // CHECK16-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
17251 // CHECK16-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
17252 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
17253 // CHECK16-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
17254 // CHECK16-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
17255 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17256 // CHECK16:       omp.body.continue:
17257 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17258 // CHECK16:       omp.inner.for.inc:
17259 // CHECK16-NEXT:    [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
17260 // CHECK16-NEXT:    [[ADD7:%.*]] = add i64 [[TMP13]], 1
17261 // CHECK16-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
17262 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
17263 // CHECK16:       omp.inner.for.end:
17264 // CHECK16-NEXT:    br label [[OMP_IF_END:%.*]]
17265 // CHECK16:       omp_if.else:
17266 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND8:%.*]]
17267 // CHECK16:       omp.inner.for.cond8:
17268 // CHECK16-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
17269 // CHECK16-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
17270 // CHECK16-NEXT:    [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]]
17271 // CHECK16-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
17272 // CHECK16:       omp.inner.for.body10:
17273 // CHECK16-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
17274 // CHECK16-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP16]], 400
17275 // CHECK16-NEXT:    [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
17276 // CHECK16-NEXT:    store i64 [[SUB12]], i64* [[IT]], align 8
17277 // CHECK16-NEXT:    [[TMP17:%.*]] = load i32, i32* [[B]], align 4
17278 // CHECK16-NEXT:    [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double
17279 // CHECK16-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
17280 // CHECK16-NEXT:    [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
17281 // CHECK16-NEXT:    store double [[ADD14]], double* [[A15]], align 4
17282 // CHECK16-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
17283 // CHECK16-NEXT:    [[TMP18:%.*]] = load double, double* [[A16]], align 4
17284 // CHECK16-NEXT:    [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00
17285 // CHECK16-NEXT:    store double [[INC17]], double* [[A16]], align 4
17286 // CHECK16-NEXT:    [[CONV18:%.*]] = fptosi double [[INC17]] to i16
17287 // CHECK16-NEXT:    [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
17288 // CHECK16-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
17289 // CHECK16-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1
17290 // CHECK16-NEXT:    store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
17291 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE21:%.*]]
17292 // CHECK16:       omp.body.continue21:
17293 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC22:%.*]]
17294 // CHECK16:       omp.inner.for.inc22:
17295 // CHECK16-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
17296 // CHECK16-NEXT:    [[ADD23:%.*]] = add i64 [[TMP20]], 1
17297 // CHECK16-NEXT:    store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
17298 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]]
17299 // CHECK16:       omp.inner.for.end24:
17300 // CHECK16-NEXT:    br label [[OMP_IF_END]]
17301 // CHECK16:       omp_if.end:
17302 // CHECK16-NEXT:    store i64 400, i64* [[IT]], align 8
17303 // CHECK16-NEXT:    [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
17304 // CHECK16-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
17305 // CHECK16-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
17306 // CHECK16-NEXT:    [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
17307 // CHECK16-NEXT:    [[CONV27:%.*]] = sext i16 [[TMP22]] to i32
17308 // CHECK16-NEXT:    [[TMP23:%.*]] = load i32, i32* [[B]], align 4
17309 // CHECK16-NEXT:    [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]]
17310 // CHECK16-NEXT:    [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
17311 // CHECK16-NEXT:    call void @llvm.stackrestore(i8* [[TMP24]])
17312 // CHECK16-NEXT:    ret i32 [[ADD28]]
17313 //
17314 //
17315 // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici
17316 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
17317 // CHECK16-NEXT:  entry:
17318 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17319 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
17320 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
17321 // CHECK16-NEXT:    [[AAA:%.*]] = alloca i8, align 1
17322 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
17323 // CHECK16-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17324 // CHECK16-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17325 // CHECK16-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17326 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17327 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
17328 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
17329 // CHECK16-NEXT:    store i8 0, i8* [[AAA]], align 1
17330 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17331 // CHECK16-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
17332 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
17333 // CHECK16-NEXT:    ret i32 [[TMP0]]
17334 //
17335 //
17336 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
17337 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
17338 // CHECK16-NEXT:  entry:
17339 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17340 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
17341 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
17342 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
17343 // CHECK16-NEXT:    [[TMP:%.*]] = alloca i64, align 4
17344 // CHECK16-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
17345 // CHECK16-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
17346 // CHECK16-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
17347 // CHECK16-NEXT:    [[I:%.*]] = alloca i64, align 8
17348 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17349 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
17350 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
17351 // CHECK16-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
17352 // CHECK16-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
17353 // CHECK16-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
17354 // CHECK16-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
17355 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17356 // CHECK16:       omp.inner.for.cond:
17357 // CHECK16-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
17358 // CHECK16-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25
17359 // CHECK16-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
17360 // CHECK16-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17361 // CHECK16:       omp.inner.for.body:
17362 // CHECK16-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
17363 // CHECK16-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
17364 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
17365 // CHECK16-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25
17366 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
17367 // CHECK16-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
17368 // CHECK16-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
17369 // CHECK16-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
17370 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
17371 // CHECK16-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
17372 // CHECK16-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
17373 // CHECK16-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
17374 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
17375 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
17376 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
17377 // CHECK16-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
17378 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17379 // CHECK16:       omp.body.continue:
17380 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17381 // CHECK16:       omp.inner.for.inc:
17382 // CHECK16-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
17383 // CHECK16-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
17384 // CHECK16-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
17385 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
17386 // CHECK16:       omp.inner.for.end:
17387 // CHECK16-NEXT:    store i64 11, i64* [[I]], align 8
17388 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
17389 // CHECK16-NEXT:    ret i32 [[TMP8]]
17390 //
17391 //
17392 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
17393 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
17394 // CHECK17-NEXT:  entry:
17395 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
17396 // CHECK17-NEXT:    ret void
17397 //
17398 //
17399 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
17400 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
17401 // CHECK17-NEXT:  entry:
17402 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
17403 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
17404 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17405 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17406 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17407 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17408 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
17409 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17410 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
17411 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
17412 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
17413 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17414 // CHECK17-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
17415 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
17416 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17417 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
17418 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
17419 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
17420 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17421 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
17422 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17423 // CHECK17:       cond.true:
17424 // CHECK17-NEXT:    br label [[COND_END:%.*]]
17425 // CHECK17:       cond.false:
17426 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17427 // CHECK17-NEXT:    br label [[COND_END]]
17428 // CHECK17:       cond.end:
17429 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
17430 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
17431 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17432 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
17433 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17434 // CHECK17:       omp.inner.for.cond:
17435 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17436 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
17437 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
17438 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17439 // CHECK17:       omp.inner.for.body:
17440 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17441 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
17442 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
17443 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
17444 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17445 // CHECK17:       omp.body.continue:
17446 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17447 // CHECK17:       omp.inner.for.inc:
17448 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17449 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
17450 // CHECK17-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17451 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
17452 // CHECK17:       omp.inner.for.end:
17453 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
17454 // CHECK17:       omp.loop.exit:
17455 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
17456 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
17457 // CHECK17-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
17458 // CHECK17-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
17459 // CHECK17:       .omp.final.then:
17460 // CHECK17-NEXT:    store i32 33, i32* [[I]], align 4
17461 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
17462 // CHECK17:       .omp.final.done:
17463 // CHECK17-NEXT:    ret void
17464 //
17465 //
17466 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
17467 // CHECK17-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
17468 // CHECK17-NEXT:  entry:
17469 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
17470 // CHECK17-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
17471 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
17472 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
17473 // CHECK17-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
17474 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
17475 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
17476 // CHECK17-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
17477 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
17478 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
17479 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
17480 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
17481 // CHECK17-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
17482 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
17483 // CHECK17-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
17484 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
17485 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
17486 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
17487 // CHECK17-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
17488 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
17489 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
17490 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
17491 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
17492 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
17493 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
17494 // CHECK17-NEXT:    ret void
17495 //
17496 //
17497 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
17498 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
17499 // CHECK17-NEXT:  entry:
17500 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
17501 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
17502 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
17503 // CHECK17-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
17504 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
17505 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
17506 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i64, align 8
17507 // CHECK17-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
17508 // CHECK17-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
17509 // CHECK17-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
17510 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
17511 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
17512 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
17513 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17514 // CHECK17-NEXT:    [[IT:%.*]] = alloca i64, align 8
17515 // CHECK17-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
17516 // CHECK17-NEXT:    [[A5:%.*]] = alloca i32, align 4
17517 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
17518 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
17519 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
17520 // CHECK17-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
17521 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
17522 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
17523 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
17524 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
17525 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
17526 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
17527 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
17528 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
17529 // CHECK17-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
17530 // CHECK17-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
17531 // CHECK17-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
17532 // CHECK17-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
17533 // CHECK17-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
17534 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17535 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
17536 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
17537 // CHECK17-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
17538 // CHECK17-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
17539 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
17540 // CHECK17-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
17541 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17542 // CHECK17:       cond.true:
17543 // CHECK17-NEXT:    br label [[COND_END:%.*]]
17544 // CHECK17:       cond.false:
17545 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
17546 // CHECK17-NEXT:    br label [[COND_END]]
17547 // CHECK17:       cond.end:
17548 // CHECK17-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
17549 // CHECK17-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
17550 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
17551 // CHECK17-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
17552 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17553 // CHECK17:       omp.inner.for.cond:
17554 // CHECK17-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
17555 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17
17556 // CHECK17-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
17557 // CHECK17-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17558 // CHECK17:       omp.inner.for.body:
17559 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
17560 // CHECK17-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
17561 // CHECK17-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
17562 // CHECK17-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17
17563 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17
17564 // CHECK17-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
17565 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
17566 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
17567 // CHECK17-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
17568 // CHECK17-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
17569 // CHECK17-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
17570 // CHECK17-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17
17571 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
17572 // CHECK17-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
17573 // CHECK17-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
17574 // CHECK17-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
17575 // CHECK17-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
17576 // CHECK17-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
17577 // CHECK17-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
17578 // CHECK17-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
17579 // CHECK17-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
17580 // CHECK17-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
17581 // CHECK17-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
17582 // CHECK17-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
17583 // CHECK17-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
17584 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17585 // CHECK17:       omp.body.continue:
17586 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17587 // CHECK17:       omp.inner.for.inc:
17588 // CHECK17-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
17589 // CHECK17-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
17590 // CHECK17-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
17591 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
17592 // CHECK17:       omp.inner.for.end:
17593 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
17594 // CHECK17:       omp.loop.exit:
17595 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
17596 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
17597 // CHECK17-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
17598 // CHECK17-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
17599 // CHECK17:       .omp.final.then:
17600 // CHECK17-NEXT:    store i64 400, i64* [[IT]], align 8
17601 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
17602 // CHECK17:       .omp.final.done:
17603 // CHECK17-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
17604 // CHECK17-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
17605 // CHECK17-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
17606 // CHECK17:       .omp.linear.pu:
17607 // CHECK17-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
17608 // CHECK17-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
17609 // CHECK17-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
17610 // CHECK17-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP23]]
17611 // CHECK17-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
17612 // CHECK17-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
17613 // CHECK17-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
17614 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
17615 // CHECK17-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
17616 // CHECK17-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
17617 // CHECK17-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP25]]
17618 // CHECK17-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
17619 // CHECK17-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
17620 // CHECK17-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
17621 // CHECK17-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
17622 // CHECK17:       .omp.linear.pu.done:
17623 // CHECK17-NEXT:    ret void
17624 //
17625 //
17626 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv
17627 // CHECK17-SAME: () #[[ATTR3:[0-9]+]] {
17628 // CHECK17-NEXT:  entry:
17629 // CHECK17-NEXT:    ret i64 0
17630 //
17631 //
17632 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
17633 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
17634 // CHECK17-NEXT:  entry:
17635 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
17636 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
17637 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
17638 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
17639 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
17640 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
17641 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
17642 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
17643 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
17644 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
17645 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
17646 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
17647 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
17648 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
17649 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
17650 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
17651 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
17652 // CHECK17-NEXT:    ret void
17653 //
17654 //
17655 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
17656 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
17657 // CHECK17-NEXT:  entry:
17658 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
17659 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
17660 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
17661 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
17662 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17663 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i16, align 2
17664 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17665 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17666 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
17667 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17668 // CHECK17-NEXT:    [[IT:%.*]] = alloca i16, align 2
17669 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
17670 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
17671 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
17672 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
17673 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
17674 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
17675 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17676 // CHECK17-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
17677 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
17678 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17679 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
17680 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
17681 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
17682 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17683 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
17684 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17685 // CHECK17:       cond.true:
17686 // CHECK17-NEXT:    br label [[COND_END:%.*]]
17687 // CHECK17:       cond.false:
17688 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17689 // CHECK17-NEXT:    br label [[COND_END]]
17690 // CHECK17:       cond.end:
17691 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
17692 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
17693 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17694 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
17695 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17696 // CHECK17:       omp.inner.for.cond:
17697 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
17698 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
17699 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
17700 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17701 // CHECK17:       omp.inner.for.body:
17702 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
17703 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
17704 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
17705 // CHECK17-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
17706 // CHECK17-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
17707 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
17708 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
17709 // CHECK17-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
17710 // CHECK17-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
17711 // CHECK17-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
17712 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
17713 // CHECK17-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
17714 // CHECK17-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
17715 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17716 // CHECK17:       omp.body.continue:
17717 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17718 // CHECK17:       omp.inner.for.inc:
17719 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
17720 // CHECK17-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
17721 // CHECK17-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
17722 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
17723 // CHECK17:       omp.inner.for.end:
17724 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
17725 // CHECK17:       omp.loop.exit:
17726 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
17727 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
17728 // CHECK17-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
17729 // CHECK17-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
17730 // CHECK17:       .omp.final.then:
17731 // CHECK17-NEXT:    store i16 22, i16* [[IT]], align 2
17732 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
17733 // CHECK17:       .omp.final.done:
17734 // CHECK17-NEXT:    ret void
17735 //
17736 //
17737 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
17738 // CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
17739 // CHECK17-NEXT:  entry:
17740 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
17741 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
17742 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
17743 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
17744 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
17745 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
17746 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
17747 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
17748 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
17749 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
17750 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
17751 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
17752 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
17753 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
17754 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
17755 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
17756 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
17757 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
17758 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
17759 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
17760 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
17761 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
17762 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
17763 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
17764 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
17765 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
17766 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
17767 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
17768 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
17769 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
17770 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
17771 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
17772 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
17773 // CHECK17-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
17774 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
17775 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
17776 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
17777 // CHECK17-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
17778 // CHECK17-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
17779 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
17780 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
17781 // CHECK17-NEXT:    ret void
17782 //
17783 //
17784 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
17785 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
17786 // CHECK17-NEXT:  entry:
17787 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
17788 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
17789 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
17790 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
17791 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
17792 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
17793 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
17794 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
17795 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
17796 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
17797 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
17798 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
17799 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17800 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i8, align 1
17801 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17802 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17803 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
17804 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17805 // CHECK17-NEXT:    [[IT:%.*]] = alloca i8, align 1
17806 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
17807 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
17808 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
17809 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
17810 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
17811 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
17812 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
17813 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
17814 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
17815 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
17816 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
17817 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
17818 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
17819 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
17820 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
17821 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
17822 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
17823 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
17824 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
17825 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
17826 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
17827 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
17828 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17829 // CHECK17-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
17830 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
17831 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17832 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
17833 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
17834 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
17835 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
17836 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
17837 // CHECK17:       omp.dispatch.cond:
17838 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17839 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
17840 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17841 // CHECK17:       cond.true:
17842 // CHECK17-NEXT:    br label [[COND_END:%.*]]
17843 // CHECK17:       cond.false:
17844 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17845 // CHECK17-NEXT:    br label [[COND_END]]
17846 // CHECK17:       cond.end:
17847 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
17848 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
17849 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17850 // CHECK17-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
17851 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17852 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17853 // CHECK17-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
17854 // CHECK17-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
17855 // CHECK17:       omp.dispatch.body:
17856 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17857 // CHECK17:       omp.inner.for.cond:
17858 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
17859 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
17860 // CHECK17-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
17861 // CHECK17-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17862 // CHECK17:       omp.inner.for.body:
17863 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
17864 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
17865 // CHECK17-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
17866 // CHECK17-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
17867 // CHECK17-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
17868 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
17869 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
17870 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
17871 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
17872 // CHECK17-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
17873 // CHECK17-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
17874 // CHECK17-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
17875 // CHECK17-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
17876 // CHECK17-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
17877 // CHECK17-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
17878 // CHECK17-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
17879 // CHECK17-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
17880 // CHECK17-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
17881 // CHECK17-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
17882 // CHECK17-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
17883 // CHECK17-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
17884 // CHECK17-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
17885 // CHECK17-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
17886 // CHECK17-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
17887 // CHECK17-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
17888 // CHECK17-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
17889 // CHECK17-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
17890 // CHECK17-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
17891 // CHECK17-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
17892 // CHECK17-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
17893 // CHECK17-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
17894 // CHECK17-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
17895 // CHECK17-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23
17896 // CHECK17-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
17897 // CHECK17-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23
17898 // CHECK17-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
17899 // CHECK17-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23
17900 // CHECK17-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
17901 // CHECK17-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
17902 // CHECK17-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
17903 // CHECK17-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23
17904 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17905 // CHECK17:       omp.body.continue:
17906 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17907 // CHECK17:       omp.inner.for.inc:
17908 // CHECK17-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
17909 // CHECK17-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
17910 // CHECK17-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
17911 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
17912 // CHECK17:       omp.inner.for.end:
17913 // CHECK17-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
17914 // CHECK17:       omp.dispatch.inc:
17915 // CHECK17-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17916 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
17917 // CHECK17-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
17918 // CHECK17-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
17919 // CHECK17-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17920 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
17921 // CHECK17-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
17922 // CHECK17-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
17923 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND]]
17924 // CHECK17:       omp.dispatch.end:
17925 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
17926 // CHECK17-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
17927 // CHECK17-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
17928 // CHECK17-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
17929 // CHECK17:       .omp.final.then:
17930 // CHECK17-NEXT:    store i8 96, i8* [[IT]], align 1
17931 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
17932 // CHECK17:       .omp.final.done:
17933 // CHECK17-NEXT:    ret void
17934 //
17935 //
17936 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
17937 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
17938 // CHECK17-NEXT:  entry:
17939 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
17940 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
17941 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
17942 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
17943 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
17944 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
17945 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
17946 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
17947 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
17948 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
17949 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
17950 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
17951 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
17952 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
17953 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
17954 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
17955 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
17956 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
17957 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
17958 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
17959 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
17960 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
17961 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
17962 // CHECK17-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
17963 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
17964 // CHECK17-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
17965 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
17966 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
17967 // CHECK17-NEXT:    ret void
17968 //
17969 //
17970 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
17971 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
17972 // CHECK17-NEXT:  entry:
17973 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
17974 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
17975 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
17976 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
17977 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
17978 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
17979 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17980 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17981 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
17982 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
17983 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
17984 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
17985 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
17986 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
17987 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
17988 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
17989 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
17990 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
17991 // CHECK17-NEXT:    ret void
17992 //
17993 //
17994 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
17995 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
17996 // CHECK17-NEXT:  entry:
17997 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
17998 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
17999 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
18000 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
18001 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
18002 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
18003 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
18004 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
18005 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
18006 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
18007 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
18008 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
18009 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
18010 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
18011 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
18012 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
18013 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
18014 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
18015 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
18016 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
18017 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
18018 // CHECK17-NEXT:    ret void
18019 //
18020 //
18021 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5
18022 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
18023 // CHECK17-NEXT:  entry:
18024 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18025 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18026 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
18027 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
18028 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
18029 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
18030 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
18031 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
18032 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i64, align 8
18033 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
18034 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
18035 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
18036 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18037 // CHECK17-NEXT:    [[IT:%.*]] = alloca i64, align 8
18038 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18039 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18040 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
18041 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
18042 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
18043 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
18044 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
18045 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
18046 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
18047 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
18048 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
18049 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
18050 // CHECK17-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
18051 // CHECK17-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
18052 // CHECK17-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
18053 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18054 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18055 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
18056 // CHECK17-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
18057 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18058 // CHECK17-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
18059 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18060 // CHECK17:       cond.true:
18061 // CHECK17-NEXT:    br label [[COND_END:%.*]]
18062 // CHECK17:       cond.false:
18063 // CHECK17-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18064 // CHECK17-NEXT:    br label [[COND_END]]
18065 // CHECK17:       cond.end:
18066 // CHECK17-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
18067 // CHECK17-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
18068 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
18069 // CHECK17-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
18070 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18071 // CHECK17:       omp.inner.for.cond:
18072 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
18073 // CHECK17-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
18074 // CHECK17-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
18075 // CHECK17-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18076 // CHECK17:       omp.inner.for.body:
18077 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
18078 // CHECK17-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
18079 // CHECK17-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
18080 // CHECK17-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
18081 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
18082 // CHECK17-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
18083 // CHECK17-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
18084 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
18085 // CHECK17-NEXT:    store double [[ADD]], double* [[A]], align 8, !llvm.access.group !26
18086 // CHECK17-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
18087 // CHECK17-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !26
18088 // CHECK17-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
18089 // CHECK17-NEXT:    store double [[INC]], double* [[A5]], align 8, !llvm.access.group !26
18090 // CHECK17-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
18091 // CHECK17-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
18092 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
18093 // CHECK17-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
18094 // CHECK17-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !26
18095 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18096 // CHECK17:       omp.body.continue:
18097 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18098 // CHECK17:       omp.inner.for.inc:
18099 // CHECK17-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
18100 // CHECK17-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
18101 // CHECK17-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
18102 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
18103 // CHECK17:       omp.inner.for.end:
18104 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18105 // CHECK17:       omp.loop.exit:
18106 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
18107 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18108 // CHECK17-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
18109 // CHECK17-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18110 // CHECK17:       .omp.final.then:
18111 // CHECK17-NEXT:    store i64 400, i64* [[IT]], align 8
18112 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18113 // CHECK17:       .omp.final.done:
18114 // CHECK17-NEXT:    ret void
18115 //
18116 //
18117 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
18118 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
18119 // CHECK17-NEXT:  entry:
18120 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18121 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18122 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
18123 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
18124 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
18125 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18126 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18127 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
18128 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18129 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18130 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
18131 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
18132 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
18133 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
18134 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
18135 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
18136 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
18137 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
18138 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
18139 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
18140 // CHECK17-NEXT:    ret void
18141 //
18142 //
18143 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6
18144 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
18145 // CHECK17-NEXT:  entry:
18146 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18147 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18148 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18149 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18150 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
18151 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
18152 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i64, align 8
18153 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
18154 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
18155 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
18156 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18157 // CHECK17-NEXT:    [[I:%.*]] = alloca i64, align 8
18158 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18159 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18160 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18161 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18162 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
18163 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18164 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18165 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
18166 // CHECK17-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
18167 // CHECK17-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
18168 // CHECK17-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
18169 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18170 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18171 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
18172 // CHECK17-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
18173 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18174 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
18175 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18176 // CHECK17:       cond.true:
18177 // CHECK17-NEXT:    br label [[COND_END:%.*]]
18178 // CHECK17:       cond.false:
18179 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18180 // CHECK17-NEXT:    br label [[COND_END]]
18181 // CHECK17:       cond.end:
18182 // CHECK17-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
18183 // CHECK17-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
18184 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
18185 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
18186 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18187 // CHECK17:       omp.inner.for.cond:
18188 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
18189 // CHECK17-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
18190 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
18191 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18192 // CHECK17:       omp.inner.for.body:
18193 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
18194 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
18195 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
18196 // CHECK17-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29
18197 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !29
18198 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
18199 // CHECK17-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !29
18200 // CHECK17-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !29
18201 // CHECK17-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
18202 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
18203 // CHECK17-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
18204 // CHECK17-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !29
18205 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
18206 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
18207 // CHECK17-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
18208 // CHECK17-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
18209 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18210 // CHECK17:       omp.body.continue:
18211 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18212 // CHECK17:       omp.inner.for.inc:
18213 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
18214 // CHECK17-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
18215 // CHECK17-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
18216 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
18217 // CHECK17:       omp.inner.for.end:
18218 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18219 // CHECK17:       omp.loop.exit:
18220 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
18221 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18222 // CHECK17-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
18223 // CHECK17-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18224 // CHECK17:       .omp.final.then:
18225 // CHECK17-NEXT:    store i64 11, i64* [[I]], align 8
18226 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18227 // CHECK17:       .omp.final.done:
18228 // CHECK17-NEXT:    ret void
18229 //
18230 //
18231 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
18232 // CHECK18-SAME: () #[[ATTR0:[0-9]+]] {
18233 // CHECK18-NEXT:  entry:
18234 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
18235 // CHECK18-NEXT:    ret void
18236 //
18237 //
18238 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
18239 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
18240 // CHECK18-NEXT:  entry:
18241 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18242 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18243 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18244 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18245 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18246 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18247 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18248 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18249 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
18250 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18251 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18252 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18253 // CHECK18-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
18254 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18255 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18256 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18257 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
18258 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18259 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18260 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
18261 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18262 // CHECK18:       cond.true:
18263 // CHECK18-NEXT:    br label [[COND_END:%.*]]
18264 // CHECK18:       cond.false:
18265 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18266 // CHECK18-NEXT:    br label [[COND_END]]
18267 // CHECK18:       cond.end:
18268 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
18269 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18270 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18271 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
18272 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18273 // CHECK18:       omp.inner.for.cond:
18274 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
18275 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
18276 // CHECK18-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
18277 // CHECK18-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18278 // CHECK18:       omp.inner.for.body:
18279 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
18280 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
18281 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
18282 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
18283 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18284 // CHECK18:       omp.body.continue:
18285 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18286 // CHECK18:       omp.inner.for.inc:
18287 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
18288 // CHECK18-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
18289 // CHECK18-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
18290 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
18291 // CHECK18:       omp.inner.for.end:
18292 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18293 // CHECK18:       omp.loop.exit:
18294 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
18295 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18296 // CHECK18-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
18297 // CHECK18-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18298 // CHECK18:       .omp.final.then:
18299 // CHECK18-NEXT:    store i32 33, i32* [[I]], align 4
18300 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18301 // CHECK18:       .omp.final.done:
18302 // CHECK18-NEXT:    ret void
18303 //
18304 //
18305 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
18306 // CHECK18-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
18307 // CHECK18-NEXT:  entry:
18308 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18309 // CHECK18-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
18310 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18311 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
18312 // CHECK18-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
18313 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
18314 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18315 // CHECK18-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
18316 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18317 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18318 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
18319 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18320 // CHECK18-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
18321 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
18322 // CHECK18-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
18323 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
18324 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
18325 // CHECK18-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
18326 // CHECK18-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
18327 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
18328 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
18329 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
18330 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
18331 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
18332 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
18333 // CHECK18-NEXT:    ret void
18334 //
18335 //
18336 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
18337 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
18338 // CHECK18-NEXT:  entry:
18339 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18340 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18341 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18342 // CHECK18-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
18343 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18344 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
18345 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i64, align 8
18346 // CHECK18-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
18347 // CHECK18-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
18348 // CHECK18-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
18349 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
18350 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
18351 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
18352 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18353 // CHECK18-NEXT:    [[IT:%.*]] = alloca i64, align 8
18354 // CHECK18-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
18355 // CHECK18-NEXT:    [[A5:%.*]] = alloca i32, align 4
18356 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18357 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18358 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18359 // CHECK18-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
18360 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18361 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18362 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
18363 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18364 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
18365 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
18366 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
18367 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
18368 // CHECK18-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
18369 // CHECK18-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
18370 // CHECK18-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
18371 // CHECK18-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
18372 // CHECK18-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
18373 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18374 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18375 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
18376 // CHECK18-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
18377 // CHECK18-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
18378 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18379 // CHECK18-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
18380 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18381 // CHECK18:       cond.true:
18382 // CHECK18-NEXT:    br label [[COND_END:%.*]]
18383 // CHECK18:       cond.false:
18384 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18385 // CHECK18-NEXT:    br label [[COND_END]]
18386 // CHECK18:       cond.end:
18387 // CHECK18-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
18388 // CHECK18-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
18389 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
18390 // CHECK18-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
18391 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18392 // CHECK18:       omp.inner.for.cond:
18393 // CHECK18-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
18394 // CHECK18-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17
18395 // CHECK18-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
18396 // CHECK18-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18397 // CHECK18:       omp.inner.for.body:
18398 // CHECK18-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
18399 // CHECK18-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
18400 // CHECK18-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
18401 // CHECK18-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17
18402 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17
18403 // CHECK18-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
18404 // CHECK18-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
18405 // CHECK18-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
18406 // CHECK18-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
18407 // CHECK18-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
18408 // CHECK18-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
18409 // CHECK18-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17
18410 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
18411 // CHECK18-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
18412 // CHECK18-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
18413 // CHECK18-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
18414 // CHECK18-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
18415 // CHECK18-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
18416 // CHECK18-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
18417 // CHECK18-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
18418 // CHECK18-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
18419 // CHECK18-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
18420 // CHECK18-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
18421 // CHECK18-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
18422 // CHECK18-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
18423 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18424 // CHECK18:       omp.body.continue:
18425 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18426 // CHECK18:       omp.inner.for.inc:
18427 // CHECK18-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
18428 // CHECK18-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
18429 // CHECK18-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
18430 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
18431 // CHECK18:       omp.inner.for.end:
18432 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18433 // CHECK18:       omp.loop.exit:
18434 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
18435 // CHECK18-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18436 // CHECK18-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
18437 // CHECK18-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18438 // CHECK18:       .omp.final.then:
18439 // CHECK18-NEXT:    store i64 400, i64* [[IT]], align 8
18440 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18441 // CHECK18:       .omp.final.done:
18442 // CHECK18-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18443 // CHECK18-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
18444 // CHECK18-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
18445 // CHECK18:       .omp.linear.pu:
18446 // CHECK18-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
18447 // CHECK18-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
18448 // CHECK18-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
18449 // CHECK18-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP23]]
18450 // CHECK18-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
18451 // CHECK18-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
18452 // CHECK18-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
18453 // CHECK18-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
18454 // CHECK18-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
18455 // CHECK18-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
18456 // CHECK18-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP25]]
18457 // CHECK18-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
18458 // CHECK18-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
18459 // CHECK18-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
18460 // CHECK18-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
18461 // CHECK18:       .omp.linear.pu.done:
18462 // CHECK18-NEXT:    ret void
18463 //
18464 //
18465 // CHECK18-LABEL: define {{[^@]+}}@_Z7get_valv
18466 // CHECK18-SAME: () #[[ATTR3:[0-9]+]] {
18467 // CHECK18-NEXT:  entry:
18468 // CHECK18-NEXT:    ret i64 0
18469 //
18470 //
18471 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
18472 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
18473 // CHECK18-NEXT:  entry:
18474 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18475 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18476 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
18477 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
18478 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18479 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18480 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18481 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18482 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
18483 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
18484 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
18485 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
18486 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
18487 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
18488 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
18489 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
18490 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
18491 // CHECK18-NEXT:    ret void
18492 //
18493 //
18494 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
18495 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
18496 // CHECK18-NEXT:  entry:
18497 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18498 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18499 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18500 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18501 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18502 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i16, align 2
18503 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18504 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18505 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18506 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18507 // CHECK18-NEXT:    [[IT:%.*]] = alloca i16, align 2
18508 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18509 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18510 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18511 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18512 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18513 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18514 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18515 // CHECK18-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
18516 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18517 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18518 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18519 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
18520 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18521 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18522 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
18523 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18524 // CHECK18:       cond.true:
18525 // CHECK18-NEXT:    br label [[COND_END:%.*]]
18526 // CHECK18:       cond.false:
18527 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18528 // CHECK18-NEXT:    br label [[COND_END]]
18529 // CHECK18:       cond.end:
18530 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
18531 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18532 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18533 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
18534 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18535 // CHECK18:       omp.inner.for.cond:
18536 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
18537 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
18538 // CHECK18-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
18539 // CHECK18-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18540 // CHECK18:       omp.inner.for.body:
18541 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
18542 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
18543 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
18544 // CHECK18-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
18545 // CHECK18-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
18546 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
18547 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
18548 // CHECK18-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
18549 // CHECK18-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
18550 // CHECK18-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
18551 // CHECK18-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
18552 // CHECK18-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
18553 // CHECK18-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
18554 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18555 // CHECK18:       omp.body.continue:
18556 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18557 // CHECK18:       omp.inner.for.inc:
18558 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
18559 // CHECK18-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
18560 // CHECK18-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
18561 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
18562 // CHECK18:       omp.inner.for.end:
18563 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18564 // CHECK18:       omp.loop.exit:
18565 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
18566 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18567 // CHECK18-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
18568 // CHECK18-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18569 // CHECK18:       .omp.final.then:
18570 // CHECK18-NEXT:    store i16 22, i16* [[IT]], align 2
18571 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18572 // CHECK18:       .omp.final.done:
18573 // CHECK18-NEXT:    ret void
18574 //
18575 //
18576 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
18577 // CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
18578 // CHECK18-NEXT:  entry:
18579 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18580 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
18581 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
18582 // CHECK18-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
18583 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
18584 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
18585 // CHECK18-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
18586 // CHECK18-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
18587 // CHECK18-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
18588 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
18589 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
18590 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
18591 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18592 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
18593 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
18594 // CHECK18-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
18595 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
18596 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
18597 // CHECK18-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
18598 // CHECK18-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
18599 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
18600 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
18601 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18602 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
18603 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
18604 // CHECK18-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
18605 // CHECK18-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
18606 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
18607 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
18608 // CHECK18-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
18609 // CHECK18-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
18610 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
18611 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
18612 // CHECK18-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
18613 // CHECK18-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
18614 // CHECK18-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
18615 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
18616 // CHECK18-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
18617 // CHECK18-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
18618 // CHECK18-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
18619 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
18620 // CHECK18-NEXT:    ret void
18621 //
18622 //
18623 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
18624 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
18625 // CHECK18-NEXT:  entry:
18626 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18627 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18628 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18629 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
18630 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
18631 // CHECK18-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
18632 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
18633 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
18634 // CHECK18-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
18635 // CHECK18-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
18636 // CHECK18-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
18637 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
18638 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18639 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i8, align 1
18640 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18641 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18642 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18643 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18644 // CHECK18-NEXT:    [[IT:%.*]] = alloca i8, align 1
18645 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18646 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18647 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18648 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
18649 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
18650 // CHECK18-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
18651 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
18652 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
18653 // CHECK18-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
18654 // CHECK18-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
18655 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
18656 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
18657 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18658 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
18659 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
18660 // CHECK18-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
18661 // CHECK18-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
18662 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
18663 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
18664 // CHECK18-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
18665 // CHECK18-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
18666 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
18667 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18668 // CHECK18-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
18669 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18670 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18671 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
18672 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18673 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
18674 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
18675 // CHECK18-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
18676 // CHECK18:       omp.dispatch.cond:
18677 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18678 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
18679 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18680 // CHECK18:       cond.true:
18681 // CHECK18-NEXT:    br label [[COND_END:%.*]]
18682 // CHECK18:       cond.false:
18683 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18684 // CHECK18-NEXT:    br label [[COND_END]]
18685 // CHECK18:       cond.end:
18686 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
18687 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18688 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18689 // CHECK18-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
18690 // CHECK18-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18691 // CHECK18-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18692 // CHECK18-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
18693 // CHECK18-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
18694 // CHECK18:       omp.dispatch.body:
18695 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18696 // CHECK18:       omp.inner.for.cond:
18697 // CHECK18-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
18698 // CHECK18-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
18699 // CHECK18-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
18700 // CHECK18-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18701 // CHECK18:       omp.inner.for.body:
18702 // CHECK18-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
18703 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
18704 // CHECK18-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
18705 // CHECK18-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
18706 // CHECK18-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
18707 // CHECK18-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
18708 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
18709 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
18710 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
18711 // CHECK18-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
18712 // CHECK18-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
18713 // CHECK18-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
18714 // CHECK18-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
18715 // CHECK18-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
18716 // CHECK18-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
18717 // CHECK18-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
18718 // CHECK18-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
18719 // CHECK18-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
18720 // CHECK18-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
18721 // CHECK18-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
18722 // CHECK18-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
18723 // CHECK18-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
18724 // CHECK18-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
18725 // CHECK18-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
18726 // CHECK18-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
18727 // CHECK18-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
18728 // CHECK18-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
18729 // CHECK18-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
18730 // CHECK18-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
18731 // CHECK18-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
18732 // CHECK18-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
18733 // CHECK18-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
18734 // CHECK18-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23
18735 // CHECK18-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
18736 // CHECK18-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23
18737 // CHECK18-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
18738 // CHECK18-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23
18739 // CHECK18-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
18740 // CHECK18-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
18741 // CHECK18-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
18742 // CHECK18-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23
18743 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18744 // CHECK18:       omp.body.continue:
18745 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18746 // CHECK18:       omp.inner.for.inc:
18747 // CHECK18-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
18748 // CHECK18-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
18749 // CHECK18-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
18750 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
18751 // CHECK18:       omp.inner.for.end:
18752 // CHECK18-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
18753 // CHECK18:       omp.dispatch.inc:
18754 // CHECK18-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18755 // CHECK18-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
18756 // CHECK18-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
18757 // CHECK18-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
18758 // CHECK18-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18759 // CHECK18-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
18760 // CHECK18-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
18761 // CHECK18-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
18762 // CHECK18-NEXT:    br label [[OMP_DISPATCH_COND]]
18763 // CHECK18:       omp.dispatch.end:
18764 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
18765 // CHECK18-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18766 // CHECK18-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
18767 // CHECK18-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18768 // CHECK18:       .omp.final.then:
18769 // CHECK18-NEXT:    store i8 96, i8* [[IT]], align 1
18770 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18771 // CHECK18:       .omp.final.done:
18772 // CHECK18-NEXT:    ret void
18773 //
18774 //
18775 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
18776 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
18777 // CHECK18-NEXT:  entry:
18778 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18779 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18780 // CHECK18-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
18781 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
18782 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
18783 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
18784 // CHECK18-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
18785 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18786 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18787 // CHECK18-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
18788 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
18789 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18790 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18791 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
18792 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
18793 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
18794 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
18795 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
18796 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
18797 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
18798 // CHECK18-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
18799 // CHECK18-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
18800 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
18801 // CHECK18-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
18802 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
18803 // CHECK18-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
18804 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
18805 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
18806 // CHECK18-NEXT:    ret void
18807 //
18808 //
18809 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
18810 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
18811 // CHECK18-NEXT:  entry:
18812 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18813 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18814 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18815 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18816 // CHECK18-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
18817 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
18818 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18819 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18820 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18821 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18822 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18823 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18824 // CHECK18-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
18825 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
18826 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18827 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18828 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
18829 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
18830 // CHECK18-NEXT:    ret void
18831 //
18832 //
18833 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
18834 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
18835 // CHECK18-NEXT:  entry:
18836 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
18837 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
18838 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
18839 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
18840 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
18841 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
18842 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
18843 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
18844 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
18845 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
18846 // CHECK18-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
18847 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
18848 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
18849 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
18850 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
18851 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
18852 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
18853 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
18854 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
18855 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
18856 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
18857 // CHECK18-NEXT:    ret void
18858 //
18859 //
18860 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5
18861 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
18862 // CHECK18-NEXT:  entry:
18863 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18864 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18865 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
18866 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
18867 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
18868 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
18869 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
18870 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
18871 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i64, align 8
18872 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
18873 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
18874 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
18875 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18876 // CHECK18-NEXT:    [[IT:%.*]] = alloca i64, align 8
18877 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18878 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18879 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
18880 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
18881 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
18882 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
18883 // CHECK18-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
18884 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
18885 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
18886 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
18887 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
18888 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
18889 // CHECK18-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
18890 // CHECK18-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
18891 // CHECK18-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
18892 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18893 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18894 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
18895 // CHECK18-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
18896 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18897 // CHECK18-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
18898 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18899 // CHECK18:       cond.true:
18900 // CHECK18-NEXT:    br label [[COND_END:%.*]]
18901 // CHECK18:       cond.false:
18902 // CHECK18-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
18903 // CHECK18-NEXT:    br label [[COND_END]]
18904 // CHECK18:       cond.end:
18905 // CHECK18-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
18906 // CHECK18-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
18907 // CHECK18-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
18908 // CHECK18-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
18909 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18910 // CHECK18:       omp.inner.for.cond:
18911 // CHECK18-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
18912 // CHECK18-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
18913 // CHECK18-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
18914 // CHECK18-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18915 // CHECK18:       omp.inner.for.body:
18916 // CHECK18-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
18917 // CHECK18-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
18918 // CHECK18-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
18919 // CHECK18-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
18920 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
18921 // CHECK18-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
18922 // CHECK18-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
18923 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
18924 // CHECK18-NEXT:    store double [[ADD]], double* [[A]], align 8, !llvm.access.group !26
18925 // CHECK18-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
18926 // CHECK18-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !26
18927 // CHECK18-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
18928 // CHECK18-NEXT:    store double [[INC]], double* [[A5]], align 8, !llvm.access.group !26
18929 // CHECK18-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
18930 // CHECK18-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
18931 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
18932 // CHECK18-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
18933 // CHECK18-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !26
18934 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18935 // CHECK18:       omp.body.continue:
18936 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18937 // CHECK18:       omp.inner.for.inc:
18938 // CHECK18-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
18939 // CHECK18-NEXT:    [[ADD8:%.*]] = add i64 [[TMP15]], 1
18940 // CHECK18-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
18941 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
18942 // CHECK18:       omp.inner.for.end:
18943 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18944 // CHECK18:       omp.loop.exit:
18945 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
18946 // CHECK18-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18947 // CHECK18-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
18948 // CHECK18-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18949 // CHECK18:       .omp.final.then:
18950 // CHECK18-NEXT:    store i64 400, i64* [[IT]], align 8
18951 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18952 // CHECK18:       .omp.final.done:
18953 // CHECK18-NEXT:    ret void
18954 //
18955 //
18956 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
18957 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
18958 // CHECK18-NEXT:  entry:
18959 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18960 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18961 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
18962 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
18963 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
18964 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18965 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18966 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
18967 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18968 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18969 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
18970 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
18971 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
18972 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
18973 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
18974 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
18975 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
18976 // CHECK18-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
18977 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
18978 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
18979 // CHECK18-NEXT:    ret void
18980 //
18981 //
18982 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6
18983 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
18984 // CHECK18-NEXT:  entry:
18985 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18986 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18987 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18988 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18989 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
18990 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
18991 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i64, align 8
18992 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
18993 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
18994 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
18995 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18996 // CHECK18-NEXT:    [[I:%.*]] = alloca i64, align 8
18997 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18998 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18999 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
19000 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19001 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
19002 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
19003 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19004 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
19005 // CHECK18-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
19006 // CHECK18-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
19007 // CHECK18-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
19008 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19009 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19010 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
19011 // CHECK18-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
19012 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19013 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
19014 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19015 // CHECK18:       cond.true:
19016 // CHECK18-NEXT:    br label [[COND_END:%.*]]
19017 // CHECK18:       cond.false:
19018 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19019 // CHECK18-NEXT:    br label [[COND_END]]
19020 // CHECK18:       cond.end:
19021 // CHECK18-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
19022 // CHECK18-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
19023 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
19024 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
19025 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19026 // CHECK18:       omp.inner.for.cond:
19027 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
19028 // CHECK18-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29
19029 // CHECK18-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
19030 // CHECK18-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19031 // CHECK18:       omp.inner.for.body:
19032 // CHECK18-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
19033 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
19034 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
19035 // CHECK18-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29
19036 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !29
19037 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
19038 // CHECK18-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !29
19039 // CHECK18-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !29
19040 // CHECK18-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
19041 // CHECK18-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
19042 // CHECK18-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
19043 // CHECK18-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !29
19044 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
19045 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
19046 // CHECK18-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
19047 // CHECK18-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !29
19048 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19049 // CHECK18:       omp.body.continue:
19050 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19051 // CHECK18:       omp.inner.for.inc:
19052 // CHECK18-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
19053 // CHECK18-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
19054 // CHECK18-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29
19055 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
19056 // CHECK18:       omp.inner.for.end:
19057 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19058 // CHECK18:       omp.loop.exit:
19059 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
19060 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19061 // CHECK18-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
19062 // CHECK18-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19063 // CHECK18:       .omp.final.then:
19064 // CHECK18-NEXT:    store i64 11, i64* [[I]], align 8
19065 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19066 // CHECK18:       .omp.final.done:
19067 // CHECK18-NEXT:    ret void
19068 //
19069 //
19070 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
19071 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] {
19072 // CHECK19-NEXT:  entry:
19073 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
19074 // CHECK19-NEXT:    ret void
19075 //
19076 //
19077 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
19078 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
19079 // CHECK19-NEXT:  entry:
19080 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19081 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19082 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19083 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19084 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19085 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19086 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19087 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19088 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
19089 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19090 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19091 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19092 // CHECK19-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
19093 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19094 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19095 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19096 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
19097 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19098 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19099 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
19100 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19101 // CHECK19:       cond.true:
19102 // CHECK19-NEXT:    br label [[COND_END:%.*]]
19103 // CHECK19:       cond.false:
19104 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19105 // CHECK19-NEXT:    br label [[COND_END]]
19106 // CHECK19:       cond.end:
19107 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
19108 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19109 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19110 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
19111 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19112 // CHECK19:       omp.inner.for.cond:
19113 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
19114 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
19115 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
19116 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19117 // CHECK19:       omp.inner.for.body:
19118 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
19119 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
19120 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
19121 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
19122 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19123 // CHECK19:       omp.body.continue:
19124 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19125 // CHECK19:       omp.inner.for.inc:
19126 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
19127 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
19128 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
19129 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
19130 // CHECK19:       omp.inner.for.end:
19131 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19132 // CHECK19:       omp.loop.exit:
19133 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
19134 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19135 // CHECK19-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
19136 // CHECK19-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19137 // CHECK19:       .omp.final.then:
19138 // CHECK19-NEXT:    store i32 33, i32* [[I]], align 4
19139 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19140 // CHECK19:       .omp.final.done:
19141 // CHECK19-NEXT:    ret void
19142 //
19143 //
19144 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
19145 // CHECK19-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
19146 // CHECK19-NEXT:  entry:
19147 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19148 // CHECK19-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
19149 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19150 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19151 // CHECK19-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
19152 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19153 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19154 // CHECK19-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
19155 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19156 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19157 // CHECK19-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
19158 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19159 // CHECK19-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
19160 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19161 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
19162 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
19163 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
19164 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
19165 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
19166 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
19167 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
19168 // CHECK19-NEXT:    ret void
19169 //
19170 //
19171 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
19172 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
19173 // CHECK19-NEXT:  entry:
19174 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19175 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19176 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19177 // CHECK19-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
19178 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19179 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
19180 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i64, align 4
19181 // CHECK19-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
19182 // CHECK19-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
19183 // CHECK19-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
19184 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
19185 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
19186 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
19187 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19188 // CHECK19-NEXT:    [[IT:%.*]] = alloca i64, align 8
19189 // CHECK19-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
19190 // CHECK19-NEXT:    [[A3:%.*]] = alloca i32, align 4
19191 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19192 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19193 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19194 // CHECK19-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
19195 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19196 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19197 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
19198 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
19199 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
19200 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
19201 // CHECK19-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
19202 // CHECK19-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
19203 // CHECK19-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
19204 // CHECK19-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
19205 // CHECK19-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
19206 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19207 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19208 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
19209 // CHECK19-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
19210 // CHECK19-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
19211 // CHECK19-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19212 // CHECK19-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
19213 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19214 // CHECK19:       cond.true:
19215 // CHECK19-NEXT:    br label [[COND_END:%.*]]
19216 // CHECK19:       cond.false:
19217 // CHECK19-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19218 // CHECK19-NEXT:    br label [[COND_END]]
19219 // CHECK19:       cond.end:
19220 // CHECK19-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
19221 // CHECK19-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
19222 // CHECK19-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
19223 // CHECK19-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
19224 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19225 // CHECK19:       omp.inner.for.cond:
19226 // CHECK19-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
19227 // CHECK19-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
19228 // CHECK19-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
19229 // CHECK19-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19230 // CHECK19:       omp.inner.for.body:
19231 // CHECK19-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
19232 // CHECK19-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
19233 // CHECK19-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
19234 // CHECK19-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
19235 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18
19236 // CHECK19-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
19237 // CHECK19-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
19238 // CHECK19-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
19239 // CHECK19-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
19240 // CHECK19-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
19241 // CHECK19-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
19242 // CHECK19-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18
19243 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
19244 // CHECK19-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
19245 // CHECK19-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
19246 // CHECK19-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
19247 // CHECK19-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
19248 // CHECK19-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
19249 // CHECK19-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
19250 // CHECK19-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
19251 // CHECK19-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
19252 // CHECK19-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
19253 // CHECK19-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
19254 // CHECK19-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
19255 // CHECK19-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
19256 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19257 // CHECK19:       omp.body.continue:
19258 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19259 // CHECK19:       omp.inner.for.inc:
19260 // CHECK19-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
19261 // CHECK19-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
19262 // CHECK19-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
19263 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
19264 // CHECK19:       omp.inner.for.end:
19265 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19266 // CHECK19:       omp.loop.exit:
19267 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
19268 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19269 // CHECK19-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
19270 // CHECK19-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19271 // CHECK19:       .omp.final.then:
19272 // CHECK19-NEXT:    store i64 400, i64* [[IT]], align 8
19273 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19274 // CHECK19:       .omp.final.done:
19275 // CHECK19-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19276 // CHECK19-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
19277 // CHECK19-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
19278 // CHECK19:       .omp.linear.pu:
19279 // CHECK19-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
19280 // CHECK19-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
19281 // CHECK19-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
19282 // CHECK19-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP23]]
19283 // CHECK19-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
19284 // CHECK19-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
19285 // CHECK19-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
19286 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
19287 // CHECK19-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
19288 // CHECK19-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
19289 // CHECK19-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP25]]
19290 // CHECK19-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
19291 // CHECK19-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
19292 // CHECK19-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
19293 // CHECK19-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
19294 // CHECK19:       .omp.linear.pu.done:
19295 // CHECK19-NEXT:    ret void
19296 //
19297 //
19298 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv
19299 // CHECK19-SAME: () #[[ATTR3:[0-9]+]] {
19300 // CHECK19-NEXT:  entry:
19301 // CHECK19-NEXT:    ret i64 0
19302 //
19303 //
19304 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
19305 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
19306 // CHECK19-NEXT:  entry:
19307 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19308 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19309 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19310 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19311 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19312 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19313 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19314 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
19315 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
19316 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
19317 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
19318 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19319 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
19320 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19321 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
19322 // CHECK19-NEXT:    ret void
19323 //
19324 //
19325 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
19326 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
19327 // CHECK19-NEXT:  entry:
19328 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19329 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19330 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19331 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19332 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19333 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i16, align 2
19334 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19335 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19336 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19337 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19338 // CHECK19-NEXT:    [[IT:%.*]] = alloca i16, align 2
19339 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19340 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19341 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19342 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19343 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19344 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19345 // CHECK19-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
19346 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19347 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19348 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19349 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
19350 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19351 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19352 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
19353 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19354 // CHECK19:       cond.true:
19355 // CHECK19-NEXT:    br label [[COND_END:%.*]]
19356 // CHECK19:       cond.false:
19357 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19358 // CHECK19-NEXT:    br label [[COND_END]]
19359 // CHECK19:       cond.end:
19360 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
19361 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19362 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19363 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
19364 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19365 // CHECK19:       omp.inner.for.cond:
19366 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
19367 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
19368 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
19369 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19370 // CHECK19:       omp.inner.for.body:
19371 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
19372 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
19373 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
19374 // CHECK19-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
19375 // CHECK19-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
19376 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
19377 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
19378 // CHECK19-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
19379 // CHECK19-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
19380 // CHECK19-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
19381 // CHECK19-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
19382 // CHECK19-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
19383 // CHECK19-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
19384 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19385 // CHECK19:       omp.body.continue:
19386 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19387 // CHECK19:       omp.inner.for.inc:
19388 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
19389 // CHECK19-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
19390 // CHECK19-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
19391 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
19392 // CHECK19:       omp.inner.for.end:
19393 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19394 // CHECK19:       omp.loop.exit:
19395 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
19396 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19397 // CHECK19-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
19398 // CHECK19-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19399 // CHECK19:       .omp.final.then:
19400 // CHECK19-NEXT:    store i16 22, i16* [[IT]], align 2
19401 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19402 // CHECK19:       .omp.final.done:
19403 // CHECK19-NEXT:    ret void
19404 //
19405 //
19406 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
19407 // CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
19408 // CHECK19-NEXT:  entry:
19409 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19410 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
19411 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
19412 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
19413 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
19414 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
19415 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
19416 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
19417 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
19418 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
19419 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19420 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
19421 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19422 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
19423 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
19424 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
19425 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
19426 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
19427 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
19428 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
19429 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
19430 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
19431 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
19432 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
19433 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
19434 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
19435 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
19436 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
19437 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
19438 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
19439 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
19440 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
19441 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
19442 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
19443 // CHECK19-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
19444 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
19445 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
19446 // CHECK19-NEXT:    ret void
19447 //
19448 //
19449 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
19450 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
19451 // CHECK19-NEXT:  entry:
19452 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19453 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19454 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19455 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
19456 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
19457 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
19458 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
19459 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
19460 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
19461 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
19462 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
19463 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
19464 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19465 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i8, align 1
19466 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19467 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19468 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19469 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19470 // CHECK19-NEXT:    [[IT:%.*]] = alloca i8, align 1
19471 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19472 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19473 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19474 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
19475 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
19476 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
19477 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
19478 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
19479 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
19480 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
19481 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
19482 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
19483 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
19484 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
19485 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
19486 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
19487 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
19488 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
19489 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
19490 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
19491 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19492 // CHECK19-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
19493 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19494 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19495 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
19496 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19497 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
19498 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
19499 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
19500 // CHECK19:       omp.dispatch.cond:
19501 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19502 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
19503 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19504 // CHECK19:       cond.true:
19505 // CHECK19-NEXT:    br label [[COND_END:%.*]]
19506 // CHECK19:       cond.false:
19507 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19508 // CHECK19-NEXT:    br label [[COND_END]]
19509 // CHECK19:       cond.end:
19510 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
19511 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19512 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19513 // CHECK19-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
19514 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19515 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19516 // CHECK19-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
19517 // CHECK19-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
19518 // CHECK19:       omp.dispatch.body:
19519 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19520 // CHECK19:       omp.inner.for.cond:
19521 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
19522 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
19523 // CHECK19-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
19524 // CHECK19-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19525 // CHECK19:       omp.inner.for.body:
19526 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
19527 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
19528 // CHECK19-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
19529 // CHECK19-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
19530 // CHECK19-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24
19531 // CHECK19-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24
19532 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
19533 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24
19534 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
19535 // CHECK19-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
19536 // CHECK19-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
19537 // CHECK19-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
19538 // CHECK19-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
19539 // CHECK19-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
19540 // CHECK19-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
19541 // CHECK19-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
19542 // CHECK19-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
19543 // CHECK19-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
19544 // CHECK19-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
19545 // CHECK19-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
19546 // CHECK19-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
19547 // CHECK19-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
19548 // CHECK19-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
19549 // CHECK19-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
19550 // CHECK19-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
19551 // CHECK19-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
19552 // CHECK19-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
19553 // CHECK19-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
19554 // CHECK19-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
19555 // CHECK19-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
19556 // CHECK19-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
19557 // CHECK19-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
19558 // CHECK19-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24
19559 // CHECK19-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
19560 // CHECK19-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24
19561 // CHECK19-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
19562 // CHECK19-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24
19563 // CHECK19-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
19564 // CHECK19-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
19565 // CHECK19-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
19566 // CHECK19-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24
19567 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19568 // CHECK19:       omp.body.continue:
19569 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19570 // CHECK19:       omp.inner.for.inc:
19571 // CHECK19-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
19572 // CHECK19-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
19573 // CHECK19-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
19574 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
19575 // CHECK19:       omp.inner.for.end:
19576 // CHECK19-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
19577 // CHECK19:       omp.dispatch.inc:
19578 // CHECK19-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19579 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
19580 // CHECK19-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
19581 // CHECK19-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
19582 // CHECK19-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19583 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
19584 // CHECK19-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
19585 // CHECK19-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
19586 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND]]
19587 // CHECK19:       omp.dispatch.end:
19588 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
19589 // CHECK19-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19590 // CHECK19-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
19591 // CHECK19-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19592 // CHECK19:       .omp.final.then:
19593 // CHECK19-NEXT:    store i8 96, i8* [[IT]], align 1
19594 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19595 // CHECK19:       .omp.final.done:
19596 // CHECK19-NEXT:    ret void
19597 //
19598 //
19599 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
19600 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
19601 // CHECK19-NEXT:  entry:
19602 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19603 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19604 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
19605 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19606 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19607 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19608 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
19609 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19610 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19611 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
19612 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19613 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19614 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
19615 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19616 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
19617 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
19618 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
19619 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
19620 // CHECK19-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19621 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
19622 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19623 // CHECK19-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
19624 // CHECK19-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
19625 // CHECK19-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
19626 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
19627 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
19628 // CHECK19-NEXT:    ret void
19629 //
19630 //
19631 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
19632 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
19633 // CHECK19-NEXT:  entry:
19634 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19635 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19636 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19637 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19638 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
19639 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19640 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19641 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19642 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19643 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19644 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19645 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19646 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
19647 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19648 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19649 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
19650 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19651 // CHECK19-NEXT:    ret void
19652 //
19653 //
19654 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
19655 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
19656 // CHECK19-NEXT:  entry:
19657 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
19658 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
19659 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
19660 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
19661 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
19662 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
19663 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
19664 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
19665 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
19666 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
19667 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
19668 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
19669 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
19670 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
19671 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
19672 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
19673 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
19674 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
19675 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
19676 // CHECK19-NEXT:    ret void
19677 //
19678 //
19679 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5
19680 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
19681 // CHECK19-NEXT:  entry:
19682 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19683 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19684 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
19685 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
19686 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
19687 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
19688 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
19689 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
19690 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i64, align 4
19691 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
19692 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
19693 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
19694 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19695 // CHECK19-NEXT:    [[IT:%.*]] = alloca i64, align 8
19696 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19697 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19698 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
19699 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
19700 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
19701 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
19702 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
19703 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
19704 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
19705 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
19706 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
19707 // CHECK19-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
19708 // CHECK19-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
19709 // CHECK19-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
19710 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19711 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19712 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
19713 // CHECK19-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
19714 // CHECK19-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19715 // CHECK19-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
19716 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19717 // CHECK19:       cond.true:
19718 // CHECK19-NEXT:    br label [[COND_END:%.*]]
19719 // CHECK19:       cond.false:
19720 // CHECK19-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19721 // CHECK19-NEXT:    br label [[COND_END]]
19722 // CHECK19:       cond.end:
19723 // CHECK19-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
19724 // CHECK19-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
19725 // CHECK19-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
19726 // CHECK19-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
19727 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19728 // CHECK19:       omp.inner.for.cond:
19729 // CHECK19-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
19730 // CHECK19-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27
19731 // CHECK19-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
19732 // CHECK19-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19733 // CHECK19:       omp.inner.for.body:
19734 // CHECK19-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
19735 // CHECK19-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
19736 // CHECK19-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
19737 // CHECK19-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27
19738 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27
19739 // CHECK19-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
19740 // CHECK19-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
19741 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
19742 // CHECK19-NEXT:    store double [[ADD]], double* [[A]], align 4, !llvm.access.group !27
19743 // CHECK19-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
19744 // CHECK19-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !27
19745 // CHECK19-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
19746 // CHECK19-NEXT:    store double [[INC]], double* [[A4]], align 4, !llvm.access.group !27
19747 // CHECK19-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
19748 // CHECK19-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
19749 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
19750 // CHECK19-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
19751 // CHECK19-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !27
19752 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19753 // CHECK19:       omp.body.continue:
19754 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19755 // CHECK19:       omp.inner.for.inc:
19756 // CHECK19-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
19757 // CHECK19-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
19758 // CHECK19-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
19759 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
19760 // CHECK19:       omp.inner.for.end:
19761 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19762 // CHECK19:       omp.loop.exit:
19763 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
19764 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19765 // CHECK19-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
19766 // CHECK19-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19767 // CHECK19:       .omp.final.then:
19768 // CHECK19-NEXT:    store i64 400, i64* [[IT]], align 8
19769 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19770 // CHECK19:       .omp.final.done:
19771 // CHECK19-NEXT:    ret void
19772 //
19773 //
19774 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
19775 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
19776 // CHECK19-NEXT:  entry:
19777 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19778 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19779 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19780 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19781 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19782 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19783 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19784 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19785 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19786 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19787 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
19788 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
19789 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
19790 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
19791 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19792 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
19793 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19794 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
19795 // CHECK19-NEXT:    ret void
19796 //
19797 //
19798 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6
19799 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
19800 // CHECK19-NEXT:  entry:
19801 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19802 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19803 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19804 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19805 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19806 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
19807 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i64, align 4
19808 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
19809 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
19810 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
19811 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19812 // CHECK19-NEXT:    [[I:%.*]] = alloca i64, align 8
19813 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19814 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19815 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19816 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19817 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19818 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19819 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19820 // CHECK19-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
19821 // CHECK19-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
19822 // CHECK19-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
19823 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19824 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19825 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
19826 // CHECK19-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
19827 // CHECK19-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19828 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
19829 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19830 // CHECK19:       cond.true:
19831 // CHECK19-NEXT:    br label [[COND_END:%.*]]
19832 // CHECK19:       cond.false:
19833 // CHECK19-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
19834 // CHECK19-NEXT:    br label [[COND_END]]
19835 // CHECK19:       cond.end:
19836 // CHECK19-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
19837 // CHECK19-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
19838 // CHECK19-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
19839 // CHECK19-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
19840 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19841 // CHECK19:       omp.inner.for.cond:
19842 // CHECK19-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
19843 // CHECK19-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
19844 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
19845 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19846 // CHECK19:       omp.inner.for.body:
19847 // CHECK19-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
19848 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
19849 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
19850 // CHECK19-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !30
19851 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30
19852 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
19853 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30
19854 // CHECK19-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
19855 // CHECK19-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
19856 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
19857 // CHECK19-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
19858 // CHECK19-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !30
19859 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
19860 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
19861 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
19862 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
19863 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19864 // CHECK19:       omp.body.continue:
19865 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19866 // CHECK19:       omp.inner.for.inc:
19867 // CHECK19-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
19868 // CHECK19-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
19869 // CHECK19-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
19870 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
19871 // CHECK19:       omp.inner.for.end:
19872 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19873 // CHECK19:       omp.loop.exit:
19874 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
19875 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19876 // CHECK19-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
19877 // CHECK19-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19878 // CHECK19:       .omp.final.then:
19879 // CHECK19-NEXT:    store i64 11, i64* [[I]], align 8
19880 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19881 // CHECK19:       .omp.final.done:
19882 // CHECK19-NEXT:    ret void
19883 //
19884 //
19885 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
19886 // CHECK20-SAME: () #[[ATTR0:[0-9]+]] {
19887 // CHECK20-NEXT:  entry:
19888 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
19889 // CHECK20-NEXT:    ret void
19890 //
19891 //
19892 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
19893 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
19894 // CHECK20-NEXT:  entry:
19895 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19896 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19897 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19898 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19899 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19900 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19901 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19902 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19903 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
19904 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19905 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19906 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19907 // CHECK20-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
19908 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19909 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19910 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19911 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
19912 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19913 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19914 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
19915 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19916 // CHECK20:       cond.true:
19917 // CHECK20-NEXT:    br label [[COND_END:%.*]]
19918 // CHECK20:       cond.false:
19919 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19920 // CHECK20-NEXT:    br label [[COND_END]]
19921 // CHECK20:       cond.end:
19922 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
19923 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19924 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19925 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
19926 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19927 // CHECK20:       omp.inner.for.cond:
19928 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
19929 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
19930 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
19931 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19932 // CHECK20:       omp.inner.for.body:
19933 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
19934 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
19935 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
19936 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
19937 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19938 // CHECK20:       omp.body.continue:
19939 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19940 // CHECK20:       omp.inner.for.inc:
19941 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
19942 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
19943 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
19944 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
19945 // CHECK20:       omp.inner.for.end:
19946 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19947 // CHECK20:       omp.loop.exit:
19948 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
19949 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19950 // CHECK20-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
19951 // CHECK20-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19952 // CHECK20:       .omp.final.then:
19953 // CHECK20-NEXT:    store i32 33, i32* [[I]], align 4
19954 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19955 // CHECK20:       .omp.final.done:
19956 // CHECK20-NEXT:    ret void
19957 //
19958 //
19959 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
19960 // CHECK20-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
19961 // CHECK20-NEXT:  entry:
19962 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19963 // CHECK20-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
19964 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19965 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19966 // CHECK20-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
19967 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19968 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19969 // CHECK20-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
19970 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19971 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19972 // CHECK20-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
19973 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19974 // CHECK20-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
19975 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19976 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
19977 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
19978 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
19979 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
19980 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
19981 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
19982 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
19983 // CHECK20-NEXT:    ret void
19984 //
19985 //
19986 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1
19987 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
19988 // CHECK20-NEXT:  entry:
19989 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19990 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19991 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19992 // CHECK20-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
19993 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19994 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
19995 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i64, align 4
19996 // CHECK20-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
19997 // CHECK20-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
19998 // CHECK20-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
19999 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
20000 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
20001 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
20002 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20003 // CHECK20-NEXT:    [[IT:%.*]] = alloca i64, align 8
20004 // CHECK20-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
20005 // CHECK20-NEXT:    [[A3:%.*]] = alloca i32, align 4
20006 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20007 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20008 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20009 // CHECK20-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
20010 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20011 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20012 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
20013 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
20014 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
20015 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
20016 // CHECK20-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
20017 // CHECK20-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
20018 // CHECK20-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
20019 // CHECK20-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
20020 // CHECK20-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
20021 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20022 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20023 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
20024 // CHECK20-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
20025 // CHECK20-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
20026 // CHECK20-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
20027 // CHECK20-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
20028 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20029 // CHECK20:       cond.true:
20030 // CHECK20-NEXT:    br label [[COND_END:%.*]]
20031 // CHECK20:       cond.false:
20032 // CHECK20-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
20033 // CHECK20-NEXT:    br label [[COND_END]]
20034 // CHECK20:       cond.end:
20035 // CHECK20-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
20036 // CHECK20-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
20037 // CHECK20-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
20038 // CHECK20-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
20039 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20040 // CHECK20:       omp.inner.for.cond:
20041 // CHECK20-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
20042 // CHECK20-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
20043 // CHECK20-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
20044 // CHECK20-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20045 // CHECK20:       omp.inner.for.body:
20046 // CHECK20-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
20047 // CHECK20-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
20048 // CHECK20-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
20049 // CHECK20-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
20050 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18
20051 // CHECK20-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
20052 // CHECK20-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
20053 // CHECK20-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
20054 // CHECK20-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
20055 // CHECK20-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
20056 // CHECK20-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
20057 // CHECK20-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18
20058 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
20059 // CHECK20-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
20060 // CHECK20-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
20061 // CHECK20-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
20062 // CHECK20-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
20063 // CHECK20-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
20064 // CHECK20-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
20065 // CHECK20-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
20066 // CHECK20-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
20067 // CHECK20-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
20068 // CHECK20-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
20069 // CHECK20-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
20070 // CHECK20-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
20071 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20072 // CHECK20:       omp.body.continue:
20073 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20074 // CHECK20:       omp.inner.for.inc:
20075 // CHECK20-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
20076 // CHECK20-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
20077 // CHECK20-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
20078 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
20079 // CHECK20:       omp.inner.for.end:
20080 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20081 // CHECK20:       omp.loop.exit:
20082 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
20083 // CHECK20-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20084 // CHECK20-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
20085 // CHECK20-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20086 // CHECK20:       .omp.final.then:
20087 // CHECK20-NEXT:    store i64 400, i64* [[IT]], align 8
20088 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20089 // CHECK20:       .omp.final.done:
20090 // CHECK20-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20091 // CHECK20-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
20092 // CHECK20-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
20093 // CHECK20:       .omp.linear.pu:
20094 // CHECK20-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
20095 // CHECK20-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
20096 // CHECK20-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
20097 // CHECK20-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP23]]
20098 // CHECK20-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
20099 // CHECK20-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
20100 // CHECK20-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
20101 // CHECK20-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
20102 // CHECK20-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
20103 // CHECK20-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
20104 // CHECK20-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP25]]
20105 // CHECK20-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
20106 // CHECK20-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
20107 // CHECK20-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
20108 // CHECK20-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
20109 // CHECK20:       .omp.linear.pu.done:
20110 // CHECK20-NEXT:    ret void
20111 //
20112 //
20113 // CHECK20-LABEL: define {{[^@]+}}@_Z7get_valv
20114 // CHECK20-SAME: () #[[ATTR3:[0-9]+]] {
20115 // CHECK20-NEXT:  entry:
20116 // CHECK20-NEXT:    ret i64 0
20117 //
20118 //
20119 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
20120 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
20121 // CHECK20-NEXT:  entry:
20122 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20123 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20124 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
20125 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
20126 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20127 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20128 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20129 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
20130 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
20131 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
20132 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
20133 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
20134 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
20135 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
20136 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
20137 // CHECK20-NEXT:    ret void
20138 //
20139 //
20140 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
20141 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
20142 // CHECK20-NEXT:  entry:
20143 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20144 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20145 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20146 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20147 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20148 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i16, align 2
20149 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20150 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20151 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20152 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20153 // CHECK20-NEXT:    [[IT:%.*]] = alloca i16, align 2
20154 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20155 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20156 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20157 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20158 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20159 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20160 // CHECK20-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
20161 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20162 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20163 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20164 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
20165 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20166 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20167 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
20168 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20169 // CHECK20:       cond.true:
20170 // CHECK20-NEXT:    br label [[COND_END:%.*]]
20171 // CHECK20:       cond.false:
20172 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20173 // CHECK20-NEXT:    br label [[COND_END]]
20174 // CHECK20:       cond.end:
20175 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
20176 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20177 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20178 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
20179 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20180 // CHECK20:       omp.inner.for.cond:
20181 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
20182 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
20183 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
20184 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20185 // CHECK20:       omp.inner.for.body:
20186 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
20187 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
20188 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
20189 // CHECK20-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
20190 // CHECK20-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
20191 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
20192 // CHECK20-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
20193 // CHECK20-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
20194 // CHECK20-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
20195 // CHECK20-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
20196 // CHECK20-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
20197 // CHECK20-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
20198 // CHECK20-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
20199 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20200 // CHECK20:       omp.body.continue:
20201 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20202 // CHECK20:       omp.inner.for.inc:
20203 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
20204 // CHECK20-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
20205 // CHECK20-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
20206 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
20207 // CHECK20:       omp.inner.for.end:
20208 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20209 // CHECK20:       omp.loop.exit:
20210 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
20211 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20212 // CHECK20-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
20213 // CHECK20-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20214 // CHECK20:       .omp.final.then:
20215 // CHECK20-NEXT:    store i16 22, i16* [[IT]], align 2
20216 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20217 // CHECK20:       .omp.final.done:
20218 // CHECK20-NEXT:    ret void
20219 //
20220 //
20221 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
20222 // CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
20223 // CHECK20-NEXT:  entry:
20224 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20225 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
20226 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
20227 // CHECK20-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
20228 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
20229 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
20230 // CHECK20-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
20231 // CHECK20-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
20232 // CHECK20-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
20233 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
20234 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
20235 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
20236 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20237 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
20238 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
20239 // CHECK20-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
20240 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
20241 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
20242 // CHECK20-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
20243 // CHECK20-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
20244 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
20245 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
20246 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
20247 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
20248 // CHECK20-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
20249 // CHECK20-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
20250 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
20251 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
20252 // CHECK20-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
20253 // CHECK20-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
20254 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
20255 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
20256 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
20257 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
20258 // CHECK20-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
20259 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
20260 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
20261 // CHECK20-NEXT:    ret void
20262 //
20263 //
20264 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3
20265 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
20266 // CHECK20-NEXT:  entry:
20267 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20268 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20269 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20270 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
20271 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
20272 // CHECK20-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
20273 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
20274 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
20275 // CHECK20-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
20276 // CHECK20-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
20277 // CHECK20-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
20278 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
20279 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20280 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i8, align 1
20281 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20282 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20283 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20284 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20285 // CHECK20-NEXT:    [[IT:%.*]] = alloca i8, align 1
20286 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20287 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20288 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20289 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
20290 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
20291 // CHECK20-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
20292 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
20293 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
20294 // CHECK20-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
20295 // CHECK20-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
20296 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
20297 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
20298 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
20299 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
20300 // CHECK20-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
20301 // CHECK20-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
20302 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
20303 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
20304 // CHECK20-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
20305 // CHECK20-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
20306 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20307 // CHECK20-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
20308 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20309 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20310 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
20311 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20312 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
20313 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
20314 // CHECK20-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
20315 // CHECK20:       omp.dispatch.cond:
20316 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20317 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
20318 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20319 // CHECK20:       cond.true:
20320 // CHECK20-NEXT:    br label [[COND_END:%.*]]
20321 // CHECK20:       cond.false:
20322 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20323 // CHECK20-NEXT:    br label [[COND_END]]
20324 // CHECK20:       cond.end:
20325 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
20326 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20327 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20328 // CHECK20-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
20329 // CHECK20-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
20330 // CHECK20-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20331 // CHECK20-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
20332 // CHECK20-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
20333 // CHECK20:       omp.dispatch.body:
20334 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20335 // CHECK20:       omp.inner.for.cond:
20336 // CHECK20-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
20337 // CHECK20-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
20338 // CHECK20-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
20339 // CHECK20-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20340 // CHECK20:       omp.inner.for.body:
20341 // CHECK20-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
20342 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
20343 // CHECK20-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
20344 // CHECK20-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
20345 // CHECK20-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24
20346 // CHECK20-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24
20347 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
20348 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24
20349 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
20350 // CHECK20-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
20351 // CHECK20-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
20352 // CHECK20-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
20353 // CHECK20-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
20354 // CHECK20-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
20355 // CHECK20-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
20356 // CHECK20-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
20357 // CHECK20-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
20358 // CHECK20-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
20359 // CHECK20-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
20360 // CHECK20-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
20361 // CHECK20-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
20362 // CHECK20-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
20363 // CHECK20-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
20364 // CHECK20-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
20365 // CHECK20-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
20366 // CHECK20-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
20367 // CHECK20-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
20368 // CHECK20-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
20369 // CHECK20-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
20370 // CHECK20-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
20371 // CHECK20-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
20372 // CHECK20-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
20373 // CHECK20-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24
20374 // CHECK20-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
20375 // CHECK20-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24
20376 // CHECK20-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
20377 // CHECK20-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24
20378 // CHECK20-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
20379 // CHECK20-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
20380 // CHECK20-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
20381 // CHECK20-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24
20382 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20383 // CHECK20:       omp.body.continue:
20384 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20385 // CHECK20:       omp.inner.for.inc:
20386 // CHECK20-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
20387 // CHECK20-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
20388 // CHECK20-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
20389 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
20390 // CHECK20:       omp.inner.for.end:
20391 // CHECK20-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
20392 // CHECK20:       omp.dispatch.inc:
20393 // CHECK20-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20394 // CHECK20-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
20395 // CHECK20-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
20396 // CHECK20-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
20397 // CHECK20-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20398 // CHECK20-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
20399 // CHECK20-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
20400 // CHECK20-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
20401 // CHECK20-NEXT:    br label [[OMP_DISPATCH_COND]]
20402 // CHECK20:       omp.dispatch.end:
20403 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
20404 // CHECK20-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20405 // CHECK20-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
20406 // CHECK20-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20407 // CHECK20:       .omp.final.then:
20408 // CHECK20-NEXT:    store i8 96, i8* [[IT]], align 1
20409 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20410 // CHECK20:       .omp.final.done:
20411 // CHECK20-NEXT:    ret void
20412 //
20413 //
20414 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
20415 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
20416 // CHECK20-NEXT:  entry:
20417 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20418 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20419 // CHECK20-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
20420 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
20421 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
20422 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
20423 // CHECK20-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
20424 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20425 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20426 // CHECK20-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
20427 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
20428 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20429 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
20430 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
20431 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
20432 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
20433 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
20434 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
20435 // CHECK20-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
20436 // CHECK20-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
20437 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
20438 // CHECK20-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
20439 // CHECK20-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
20440 // CHECK20-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
20441 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
20442 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
20443 // CHECK20-NEXT:    ret void
20444 //
20445 //
20446 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
20447 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
20448 // CHECK20-NEXT:  entry:
20449 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20450 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20451 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20452 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20453 // CHECK20-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
20454 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
20455 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20456 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20457 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20458 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20459 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20460 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20461 // CHECK20-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
20462 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
20463 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20464 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
20465 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
20466 // CHECK20-NEXT:    ret void
20467 //
20468 //
20469 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
20470 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
20471 // CHECK20-NEXT:  entry:
20472 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
20473 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
20474 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
20475 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
20476 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
20477 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
20478 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
20479 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
20480 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
20481 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
20482 // CHECK20-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
20483 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
20484 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
20485 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
20486 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
20487 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
20488 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
20489 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
20490 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
20491 // CHECK20-NEXT:    ret void
20492 //
20493 //
20494 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5
20495 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
20496 // CHECK20-NEXT:  entry:
20497 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20498 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20499 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
20500 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
20501 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
20502 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
20503 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
20504 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
20505 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i64, align 4
20506 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
20507 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
20508 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
20509 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20510 // CHECK20-NEXT:    [[IT:%.*]] = alloca i64, align 8
20511 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20512 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20513 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
20514 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
20515 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
20516 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
20517 // CHECK20-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
20518 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
20519 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
20520 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
20521 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
20522 // CHECK20-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
20523 // CHECK20-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
20524 // CHECK20-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
20525 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20526 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20527 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
20528 // CHECK20-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
20529 // CHECK20-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
20530 // CHECK20-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
20531 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20532 // CHECK20:       cond.true:
20533 // CHECK20-NEXT:    br label [[COND_END:%.*]]
20534 // CHECK20:       cond.false:
20535 // CHECK20-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
20536 // CHECK20-NEXT:    br label [[COND_END]]
20537 // CHECK20:       cond.end:
20538 // CHECK20-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
20539 // CHECK20-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
20540 // CHECK20-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
20541 // CHECK20-NEXT:    store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
20542 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20543 // CHECK20:       omp.inner.for.cond:
20544 // CHECK20-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
20545 // CHECK20-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27
20546 // CHECK20-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
20547 // CHECK20-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20548 // CHECK20:       omp.inner.for.body:
20549 // CHECK20-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
20550 // CHECK20-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
20551 // CHECK20-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
20552 // CHECK20-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27
20553 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27
20554 // CHECK20-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
20555 // CHECK20-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
20556 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
20557 // CHECK20-NEXT:    store double [[ADD]], double* [[A]], align 4, !llvm.access.group !27
20558 // CHECK20-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
20559 // CHECK20-NEXT:    [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !27
20560 // CHECK20-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
20561 // CHECK20-NEXT:    store double [[INC]], double* [[A4]], align 4, !llvm.access.group !27
20562 // CHECK20-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
20563 // CHECK20-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
20564 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
20565 // CHECK20-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
20566 // CHECK20-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !27
20567 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20568 // CHECK20:       omp.body.continue:
20569 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20570 // CHECK20:       omp.inner.for.inc:
20571 // CHECK20-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
20572 // CHECK20-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
20573 // CHECK20-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
20574 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
20575 // CHECK20:       omp.inner.for.end:
20576 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20577 // CHECK20:       omp.loop.exit:
20578 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
20579 // CHECK20-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20580 // CHECK20-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
20581 // CHECK20-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20582 // CHECK20:       .omp.final.then:
20583 // CHECK20-NEXT:    store i64 400, i64* [[IT]], align 8
20584 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20585 // CHECK20:       .omp.final.done:
20586 // CHECK20-NEXT:    ret void
20587 //
20588 //
20589 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
20590 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
20591 // CHECK20-NEXT:  entry:
20592 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20593 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20594 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
20595 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
20596 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
20597 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20598 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20599 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
20600 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20601 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
20602 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
20603 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
20604 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
20605 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
20606 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
20607 // CHECK20-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
20608 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
20609 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
20610 // CHECK20-NEXT:    ret void
20611 //
20612 //
20613 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6
20614 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
20615 // CHECK20-NEXT:  entry:
20616 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20617 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20618 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20619 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20620 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
20621 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
20622 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i64, align 4
20623 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
20624 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
20625 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
20626 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20627 // CHECK20-NEXT:    [[I:%.*]] = alloca i64, align 8
20628 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20629 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20630 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20631 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20632 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
20633 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20634 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
20635 // CHECK20-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
20636 // CHECK20-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
20637 // CHECK20-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
20638 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20639 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20640 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
20641 // CHECK20-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
20642 // CHECK20-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
20643 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
20644 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20645 // CHECK20:       cond.true:
20646 // CHECK20-NEXT:    br label [[COND_END:%.*]]
20647 // CHECK20:       cond.false:
20648 // CHECK20-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
20649 // CHECK20-NEXT:    br label [[COND_END]]
20650 // CHECK20:       cond.end:
20651 // CHECK20-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
20652 // CHECK20-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
20653 // CHECK20-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
20654 // CHECK20-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
20655 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20656 // CHECK20:       omp.inner.for.cond:
20657 // CHECK20-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
20658 // CHECK20-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30
20659 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
20660 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20661 // CHECK20:       omp.inner.for.body:
20662 // CHECK20-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
20663 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
20664 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
20665 // CHECK20-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !30
20666 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30
20667 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
20668 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30
20669 // CHECK20-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !30
20670 // CHECK20-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
20671 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
20672 // CHECK20-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
20673 // CHECK20-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !30
20674 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
20675 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
20676 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
20677 // CHECK20-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !30
20678 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20679 // CHECK20:       omp.body.continue:
20680 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20681 // CHECK20:       omp.inner.for.inc:
20682 // CHECK20-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
20683 // CHECK20-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
20684 // CHECK20-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30
20685 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
20686 // CHECK20:       omp.inner.for.end:
20687 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20688 // CHECK20:       omp.loop.exit:
20689 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
20690 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20691 // CHECK20-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
20692 // CHECK20-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20693 // CHECK20:       .omp.final.then:
20694 // CHECK20-NEXT:    store i64 11, i64* [[I]], align 8
20695 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20696 // CHECK20:       .omp.final.done:
20697 // CHECK20-NEXT:    ret void
20698 //
20699 //
20700 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
20701 // CHECK21-SAME: () #[[ATTR0:[0-9]+]] {
20702 // CHECK21-NEXT:  entry:
20703 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
20704 // CHECK21-NEXT:    ret void
20705 //
20706 //
20707 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined.
20708 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
20709 // CHECK21-NEXT:  entry:
20710 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
20711 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
20712 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20713 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20714 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20715 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20716 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20717 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20718 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
20719 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
20720 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
20721 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20722 // CHECK21-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
20723 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20724 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20725 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
20726 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
20727 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20728 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20729 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
20730 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20731 // CHECK21:       cond.true:
20732 // CHECK21-NEXT:    br label [[COND_END:%.*]]
20733 // CHECK21:       cond.false:
20734 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20735 // CHECK21-NEXT:    br label [[COND_END]]
20736 // CHECK21:       cond.end:
20737 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
20738 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20739 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20740 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
20741 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20742 // CHECK21:       omp.inner.for.cond:
20743 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
20744 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
20745 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
20746 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20747 // CHECK21:       omp.inner.for.body:
20748 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
20749 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
20750 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
20751 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
20752 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20753 // CHECK21:       omp.body.continue:
20754 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20755 // CHECK21:       omp.inner.for.inc:
20756 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
20757 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
20758 // CHECK21-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
20759 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
20760 // CHECK21:       omp.inner.for.end:
20761 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20762 // CHECK21:       omp.loop.exit:
20763 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
20764 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20765 // CHECK21-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
20766 // CHECK21-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20767 // CHECK21:       .omp.final.then:
20768 // CHECK21-NEXT:    store i32 33, i32* [[I]], align 4
20769 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20770 // CHECK21:       .omp.final.done:
20771 // CHECK21-NEXT:    ret void
20772 //
20773 //
20774 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
20775 // CHECK21-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
20776 // CHECK21-NEXT:  entry:
20777 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
20778 // CHECK21-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
20779 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
20780 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
20781 // CHECK21-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
20782 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
20783 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
20784 // CHECK21-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
20785 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
20786 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
20787 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
20788 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
20789 // CHECK21-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
20790 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
20791 // CHECK21-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
20792 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
20793 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
20794 // CHECK21-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
20795 // CHECK21-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
20796 // CHECK21-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
20797 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
20798 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
20799 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
20800 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
20801 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
20802 // CHECK21-NEXT:    ret void
20803 //
20804 //
20805 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1
20806 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
20807 // CHECK21-NEXT:  entry:
20808 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
20809 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
20810 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
20811 // CHECK21-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
20812 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
20813 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
20814 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i64, align 8
20815 // CHECK21-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
20816 // CHECK21-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
20817 // CHECK21-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
20818 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
20819 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
20820 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
20821 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20822 // CHECK21-NEXT:    [[IT:%.*]] = alloca i64, align 8
20823 // CHECK21-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
20824 // CHECK21-NEXT:    [[A5:%.*]] = alloca i32, align 4
20825 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
20826 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
20827 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
20828 // CHECK21-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
20829 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
20830 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
20831 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
20832 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
20833 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
20834 // CHECK21-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
20835 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
20836 // CHECK21-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
20837 // CHECK21-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
20838 // CHECK21-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
20839 // CHECK21-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
20840 // CHECK21-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
20841 // CHECK21-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
20842 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20843 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
20844 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
20845 // CHECK21-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
20846 // CHECK21-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
20847 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
20848 // CHECK21-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
20849 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20850 // CHECK21:       cond.true:
20851 // CHECK21-NEXT:    br label [[COND_END:%.*]]
20852 // CHECK21:       cond.false:
20853 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
20854 // CHECK21-NEXT:    br label [[COND_END]]
20855 // CHECK21:       cond.end:
20856 // CHECK21-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
20857 // CHECK21-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
20858 // CHECK21-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
20859 // CHECK21-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
20860 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20861 // CHECK21:       omp.inner.for.cond:
20862 // CHECK21-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
20863 // CHECK21-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17
20864 // CHECK21-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
20865 // CHECK21-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20866 // CHECK21:       omp.inner.for.body:
20867 // CHECK21-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
20868 // CHECK21-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
20869 // CHECK21-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
20870 // CHECK21-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17
20871 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17
20872 // CHECK21-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
20873 // CHECK21-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
20874 // CHECK21-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
20875 // CHECK21-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
20876 // CHECK21-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
20877 // CHECK21-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
20878 // CHECK21-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17
20879 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
20880 // CHECK21-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
20881 // CHECK21-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
20882 // CHECK21-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
20883 // CHECK21-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
20884 // CHECK21-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
20885 // CHECK21-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
20886 // CHECK21-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
20887 // CHECK21-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
20888 // CHECK21-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
20889 // CHECK21-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
20890 // CHECK21-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
20891 // CHECK21-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
20892 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20893 // CHECK21:       omp.body.continue:
20894 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20895 // CHECK21:       omp.inner.for.inc:
20896 // CHECK21-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
20897 // CHECK21-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
20898 // CHECK21-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
20899 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
20900 // CHECK21:       omp.inner.for.end:
20901 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20902 // CHECK21:       omp.loop.exit:
20903 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
20904 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20905 // CHECK21-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
20906 // CHECK21-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20907 // CHECK21:       .omp.final.then:
20908 // CHECK21-NEXT:    store i64 400, i64* [[IT]], align 8
20909 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20910 // CHECK21:       .omp.final.done:
20911 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20912 // CHECK21-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
20913 // CHECK21-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
20914 // CHECK21:       .omp.linear.pu:
20915 // CHECK21-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
20916 // CHECK21-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
20917 // CHECK21-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
20918 // CHECK21-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP23]]
20919 // CHECK21-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
20920 // CHECK21-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
20921 // CHECK21-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
20922 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
20923 // CHECK21-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
20924 // CHECK21-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
20925 // CHECK21-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP25]]
20926 // CHECK21-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
20927 // CHECK21-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
20928 // CHECK21-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
20929 // CHECK21-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
20930 // CHECK21:       .omp.linear.pu.done:
20931 // CHECK21-NEXT:    ret void
20932 //
20933 //
20934 // CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv
20935 // CHECK21-SAME: () #[[ATTR3:[0-9]+]] {
20936 // CHECK21-NEXT:  entry:
20937 // CHECK21-NEXT:    ret i64 0
20938 //
20939 //
20940 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
20941 // CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
20942 // CHECK21-NEXT:  entry:
20943 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
20944 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
20945 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
20946 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
20947 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
20948 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
20949 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
20950 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
20951 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
20952 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
20953 // CHECK21-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
20954 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
20955 // CHECK21-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
20956 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
20957 // CHECK21-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
20958 // CHECK21-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
20959 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
20960 // CHECK21-NEXT:    ret void
20961 //
20962 //
20963 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2
20964 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
20965 // CHECK21-NEXT:  entry:
20966 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
20967 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
20968 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
20969 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
20970 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20971 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i16, align 2
20972 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20973 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20974 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20975 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20976 // CHECK21-NEXT:    [[IT:%.*]] = alloca i16, align 2
20977 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
20978 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
20979 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
20980 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
20981 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
20982 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
20983 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20984 // CHECK21-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
20985 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20986 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20987 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
20988 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
20989 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20990 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20991 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
20992 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20993 // CHECK21:       cond.true:
20994 // CHECK21-NEXT:    br label [[COND_END:%.*]]
20995 // CHECK21:       cond.false:
20996 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20997 // CHECK21-NEXT:    br label [[COND_END]]
20998 // CHECK21:       cond.end:
20999 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21000 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21001 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21002 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21003 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21004 // CHECK21:       omp.inner.for.cond:
21005 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
21006 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
21007 // CHECK21-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21008 // CHECK21-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21009 // CHECK21:       omp.inner.for.body:
21010 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
21011 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
21012 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
21013 // CHECK21-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
21014 // CHECK21-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
21015 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
21016 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
21017 // CHECK21-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
21018 // CHECK21-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
21019 // CHECK21-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
21020 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
21021 // CHECK21-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
21022 // CHECK21-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
21023 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21024 // CHECK21:       omp.body.continue:
21025 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21026 // CHECK21:       omp.inner.for.inc:
21027 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
21028 // CHECK21-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
21029 // CHECK21-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
21030 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
21031 // CHECK21:       omp.inner.for.end:
21032 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21033 // CHECK21:       omp.loop.exit:
21034 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21035 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21036 // CHECK21-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
21037 // CHECK21-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21038 // CHECK21:       .omp.final.then:
21039 // CHECK21-NEXT:    store i16 22, i16* [[IT]], align 2
21040 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21041 // CHECK21:       .omp.final.done:
21042 // CHECK21-NEXT:    ret void
21043 //
21044 //
21045 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
21046 // CHECK21-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
21047 // CHECK21-NEXT:  entry:
21048 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21049 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
21050 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21051 // CHECK21-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
21052 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
21053 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21054 // CHECK21-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
21055 // CHECK21-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
21056 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
21057 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21058 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21059 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
21060 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21061 // CHECK21-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
21062 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21063 // CHECK21-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
21064 // CHECK21-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
21065 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21066 // CHECK21-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
21067 // CHECK21-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
21068 // CHECK21-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
21069 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21070 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21071 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
21072 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
21073 // CHECK21-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
21074 // CHECK21-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
21075 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
21076 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
21077 // CHECK21-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
21078 // CHECK21-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
21079 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
21080 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
21081 // CHECK21-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21082 // CHECK21-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
21083 // CHECK21-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
21084 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
21085 // CHECK21-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
21086 // CHECK21-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
21087 // CHECK21-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
21088 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
21089 // CHECK21-NEXT:    ret void
21090 //
21091 //
21092 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3
21093 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
21094 // CHECK21-NEXT:  entry:
21095 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21096 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21097 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21098 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
21099 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21100 // CHECK21-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
21101 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
21102 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21103 // CHECK21-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
21104 // CHECK21-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
21105 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
21106 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21107 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21108 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i8, align 1
21109 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21110 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21111 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21112 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21113 // CHECK21-NEXT:    [[IT:%.*]] = alloca i8, align 1
21114 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21115 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21116 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21117 // CHECK21-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
21118 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21119 // CHECK21-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
21120 // CHECK21-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
21121 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21122 // CHECK21-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
21123 // CHECK21-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
21124 // CHECK21-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
21125 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21126 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21127 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
21128 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
21129 // CHECK21-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
21130 // CHECK21-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
21131 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
21132 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
21133 // CHECK21-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
21134 // CHECK21-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
21135 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
21136 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21137 // CHECK21-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
21138 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21139 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21140 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
21141 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21142 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
21143 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
21144 // CHECK21-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
21145 // CHECK21:       omp.dispatch.cond:
21146 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21147 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
21148 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21149 // CHECK21:       cond.true:
21150 // CHECK21-NEXT:    br label [[COND_END:%.*]]
21151 // CHECK21:       cond.false:
21152 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21153 // CHECK21-NEXT:    br label [[COND_END]]
21154 // CHECK21:       cond.end:
21155 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
21156 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21157 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21158 // CHECK21-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
21159 // CHECK21-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21160 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21161 // CHECK21-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
21162 // CHECK21-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
21163 // CHECK21:       omp.dispatch.body:
21164 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21165 // CHECK21:       omp.inner.for.cond:
21166 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
21167 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
21168 // CHECK21-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
21169 // CHECK21-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21170 // CHECK21:       omp.inner.for.body:
21171 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
21172 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
21173 // CHECK21-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
21174 // CHECK21-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
21175 // CHECK21-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
21176 // CHECK21-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
21177 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
21178 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
21179 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
21180 // CHECK21-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
21181 // CHECK21-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
21182 // CHECK21-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
21183 // CHECK21-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
21184 // CHECK21-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
21185 // CHECK21-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
21186 // CHECK21-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
21187 // CHECK21-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
21188 // CHECK21-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
21189 // CHECK21-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
21190 // CHECK21-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
21191 // CHECK21-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
21192 // CHECK21-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
21193 // CHECK21-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
21194 // CHECK21-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
21195 // CHECK21-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
21196 // CHECK21-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
21197 // CHECK21-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
21198 // CHECK21-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
21199 // CHECK21-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
21200 // CHECK21-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
21201 // CHECK21-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
21202 // CHECK21-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
21203 // CHECK21-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23
21204 // CHECK21-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
21205 // CHECK21-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23
21206 // CHECK21-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
21207 // CHECK21-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23
21208 // CHECK21-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
21209 // CHECK21-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
21210 // CHECK21-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
21211 // CHECK21-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23
21212 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21213 // CHECK21:       omp.body.continue:
21214 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21215 // CHECK21:       omp.inner.for.inc:
21216 // CHECK21-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
21217 // CHECK21-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
21218 // CHECK21-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
21219 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
21220 // CHECK21:       omp.inner.for.end:
21221 // CHECK21-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
21222 // CHECK21:       omp.dispatch.inc:
21223 // CHECK21-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21224 // CHECK21-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
21225 // CHECK21-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
21226 // CHECK21-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
21227 // CHECK21-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21228 // CHECK21-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
21229 // CHECK21-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
21230 // CHECK21-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
21231 // CHECK21-NEXT:    br label [[OMP_DISPATCH_COND]]
21232 // CHECK21:       omp.dispatch.end:
21233 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
21234 // CHECK21-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21235 // CHECK21-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
21236 // CHECK21-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21237 // CHECK21:       .omp.final.then:
21238 // CHECK21-NEXT:    store i8 96, i8* [[IT]], align 1
21239 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21240 // CHECK21:       .omp.final.done:
21241 // CHECK21-NEXT:    ret void
21242 //
21243 //
21244 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
21245 // CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21246 // CHECK21-NEXT:  entry:
21247 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21248 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21249 // CHECK21-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
21250 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
21251 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21252 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21253 // CHECK21-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
21254 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21255 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21256 // CHECK21-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
21257 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
21258 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21259 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21260 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
21261 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
21262 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
21263 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21264 // CHECK21-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
21265 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
21266 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
21267 // CHECK21-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21268 // CHECK21-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
21269 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21270 // CHECK21-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
21271 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
21272 // CHECK21-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
21273 // CHECK21-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
21274 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
21275 // CHECK21-NEXT:    ret void
21276 //
21277 //
21278 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4
21279 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
21280 // CHECK21-NEXT:  entry:
21281 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21282 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21283 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21284 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21285 // CHECK21-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
21286 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
21287 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21288 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21289 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21290 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21291 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21292 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21293 // CHECK21-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
21294 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
21295 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21296 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21297 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
21298 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
21299 // CHECK21-NEXT:    ret void
21300 //
21301 //
21302 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
21303 // CHECK21-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
21304 // CHECK21-NEXT:  entry:
21305 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
21306 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
21307 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21308 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21309 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
21310 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21311 // CHECK21-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
21312 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
21313 // CHECK21-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
21314 // CHECK21-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
21315 // CHECK21-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
21316 // CHECK21-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
21317 // CHECK21-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
21318 // CHECK21-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
21319 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21320 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21321 // CHECK21-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
21322 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21323 // CHECK21-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
21324 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
21325 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
21326 // CHECK21-NEXT:    [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
21327 // CHECK21-NEXT:    [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
21328 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
21329 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
21330 // CHECK21-NEXT:    [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
21331 // CHECK21-NEXT:    store i32 [[TMP5]], i32* [[CONV4]], align 4
21332 // CHECK21-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
21333 // CHECK21-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
21334 // CHECK21-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
21335 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
21336 // CHECK21-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
21337 // CHECK21-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
21338 // CHECK21-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
21339 // CHECK21-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
21340 // CHECK21-NEXT:    [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
21341 // CHECK21-NEXT:    br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
21342 // CHECK21:       omp_if.then:
21343 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
21344 // CHECK21-NEXT:    br label [[OMP_IF_END:%.*]]
21345 // CHECK21:       omp_if.else:
21346 // CHECK21-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
21347 // CHECK21-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
21348 // CHECK21-NEXT:    call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]]
21349 // CHECK21-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
21350 // CHECK21-NEXT:    br label [[OMP_IF_END]]
21351 // CHECK21:       omp_if.end:
21352 // CHECK21-NEXT:    ret void
21353 //
21354 //
21355 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5
21356 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
21357 // CHECK21-NEXT:  entry:
21358 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21359 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21360 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
21361 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
21362 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21363 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21364 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
21365 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21366 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
21367 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i64, align 8
21368 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
21369 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
21370 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
21371 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21372 // CHECK21-NEXT:    [[IT:%.*]] = alloca i64, align 8
21373 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21374 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21375 // CHECK21-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
21376 // CHECK21-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
21377 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21378 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21379 // CHECK21-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
21380 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21381 // CHECK21-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
21382 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
21383 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
21384 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
21385 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
21386 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
21387 // CHECK21-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
21388 // CHECK21-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
21389 // CHECK21-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
21390 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21391 // CHECK21-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
21392 // CHECK21-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
21393 // CHECK21-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
21394 // CHECK21:       omp_if.then:
21395 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21396 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
21397 // CHECK21-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
21398 // CHECK21-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21399 // CHECK21-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
21400 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21401 // CHECK21:       cond.true:
21402 // CHECK21-NEXT:    br label [[COND_END:%.*]]
21403 // CHECK21:       cond.false:
21404 // CHECK21-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21405 // CHECK21-NEXT:    br label [[COND_END]]
21406 // CHECK21:       cond.end:
21407 // CHECK21-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
21408 // CHECK21-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
21409 // CHECK21-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
21410 // CHECK21-NEXT:    store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
21411 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21412 // CHECK21:       omp.inner.for.cond:
21413 // CHECK21-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
21414 // CHECK21-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
21415 // CHECK21-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
21416 // CHECK21-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21417 // CHECK21:       omp.inner.for.body:
21418 // CHECK21-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
21419 // CHECK21-NEXT:    [[MUL:%.*]] = mul i64 [[TMP12]], 400
21420 // CHECK21-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
21421 // CHECK21-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
21422 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
21423 // CHECK21-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
21424 // CHECK21-NEXT:    [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
21425 // CHECK21-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
21426 // CHECK21-NEXT:    store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group !26
21427 // CHECK21-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
21428 // CHECK21-NEXT:    [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
21429 // CHECK21-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
21430 // CHECK21-NEXT:    store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
21431 // CHECK21-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
21432 // CHECK21-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
21433 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
21434 // CHECK21-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
21435 // CHECK21-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !26
21436 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21437 // CHECK21:       omp.body.continue:
21438 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21439 // CHECK21:       omp.inner.for.inc:
21440 // CHECK21-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
21441 // CHECK21-NEXT:    [[ADD9:%.*]] = add i64 [[TMP16]], 1
21442 // CHECK21-NEXT:    store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
21443 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
21444 // CHECK21:       omp.inner.for.end:
21445 // CHECK21-NEXT:    br label [[OMP_IF_END:%.*]]
21446 // CHECK21:       omp_if.else:
21447 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21448 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
21449 // CHECK21-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
21450 // CHECK21-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21451 // CHECK21-NEXT:    [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3
21452 // CHECK21-NEXT:    br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
21453 // CHECK21:       cond.true11:
21454 // CHECK21-NEXT:    br label [[COND_END13:%.*]]
21455 // CHECK21:       cond.false12:
21456 // CHECK21-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21457 // CHECK21-NEXT:    br label [[COND_END13]]
21458 // CHECK21:       cond.end13:
21459 // CHECK21-NEXT:    [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ]
21460 // CHECK21-NEXT:    store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8
21461 // CHECK21-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
21462 // CHECK21-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
21463 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND15:%.*]]
21464 // CHECK21:       omp.inner.for.cond15:
21465 // CHECK21-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21466 // CHECK21-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21467 // CHECK21-NEXT:    [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
21468 // CHECK21-NEXT:    br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
21469 // CHECK21:       omp.inner.for.body17:
21470 // CHECK21-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21471 // CHECK21-NEXT:    [[MUL18:%.*]] = mul i64 [[TMP24]], 400
21472 // CHECK21-NEXT:    [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
21473 // CHECK21-NEXT:    store i64 [[SUB19]], i64* [[IT]], align 8
21474 // CHECK21-NEXT:    [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
21475 // CHECK21-NEXT:    [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
21476 // CHECK21-NEXT:    [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
21477 // CHECK21-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
21478 // CHECK21-NEXT:    store double [[ADD21]], double* [[A22]], align 8
21479 // CHECK21-NEXT:    [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
21480 // CHECK21-NEXT:    [[TMP26:%.*]] = load double, double* [[A23]], align 8
21481 // CHECK21-NEXT:    [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
21482 // CHECK21-NEXT:    store double [[INC24]], double* [[A23]], align 8
21483 // CHECK21-NEXT:    [[CONV25:%.*]] = fptosi double [[INC24]] to i16
21484 // CHECK21-NEXT:    [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]]
21485 // CHECK21-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]]
21486 // CHECK21-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
21487 // CHECK21-NEXT:    store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2
21488 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE28:%.*]]
21489 // CHECK21:       omp.body.continue28:
21490 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC29:%.*]]
21491 // CHECK21:       omp.inner.for.inc29:
21492 // CHECK21-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
21493 // CHECK21-NEXT:    [[ADD30:%.*]] = add i64 [[TMP28]], 1
21494 // CHECK21-NEXT:    store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8
21495 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP30:![0-9]+]]
21496 // CHECK21:       omp.inner.for.end31:
21497 // CHECK21-NEXT:    br label [[OMP_IF_END]]
21498 // CHECK21:       omp_if.end:
21499 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21500 // CHECK21:       omp.loop.exit:
21501 // CHECK21-NEXT:    [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21502 // CHECK21-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
21503 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
21504 // CHECK21-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21505 // CHECK21-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
21506 // CHECK21-NEXT:    br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21507 // CHECK21:       .omp.final.then:
21508 // CHECK21-NEXT:    store i64 400, i64* [[IT]], align 8
21509 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21510 // CHECK21:       .omp.final.done:
21511 // CHECK21-NEXT:    ret void
21512 //
21513 //
21514 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
21515 // CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21516 // CHECK21-NEXT:  entry:
21517 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21518 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21519 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
21520 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21521 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21522 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21523 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21524 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
21525 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21526 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21527 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
21528 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
21529 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21530 // CHECK21-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
21531 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
21532 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
21533 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21534 // CHECK21-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
21535 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21536 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
21537 // CHECK21-NEXT:    ret void
21538 //
21539 //
21540 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6
21541 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
21542 // CHECK21-NEXT:  entry:
21543 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21544 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21545 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21546 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21547 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
21548 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
21549 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i64, align 8
21550 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
21551 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
21552 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
21553 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21554 // CHECK21-NEXT:    [[I:%.*]] = alloca i64, align 8
21555 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21556 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21557 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21558 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21559 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
21560 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21561 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21562 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
21563 // CHECK21-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
21564 // CHECK21-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
21565 // CHECK21-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
21566 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21567 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21568 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
21569 // CHECK21-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
21570 // CHECK21-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21571 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
21572 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21573 // CHECK21:       cond.true:
21574 // CHECK21-NEXT:    br label [[COND_END:%.*]]
21575 // CHECK21:       cond.false:
21576 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21577 // CHECK21-NEXT:    br label [[COND_END]]
21578 // CHECK21:       cond.end:
21579 // CHECK21-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
21580 // CHECK21-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
21581 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
21582 // CHECK21-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
21583 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21584 // CHECK21:       omp.inner.for.cond:
21585 // CHECK21-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
21586 // CHECK21-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !32
21587 // CHECK21-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
21588 // CHECK21-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21589 // CHECK21:       omp.inner.for.body:
21590 // CHECK21-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
21591 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
21592 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
21593 // CHECK21-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32
21594 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
21595 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
21596 // CHECK21-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32
21597 // CHECK21-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
21598 // CHECK21-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
21599 // CHECK21-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
21600 // CHECK21-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
21601 // CHECK21-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32
21602 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
21603 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
21604 // CHECK21-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
21605 // CHECK21-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
21606 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21607 // CHECK21:       omp.body.continue:
21608 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21609 // CHECK21:       omp.inner.for.inc:
21610 // CHECK21-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
21611 // CHECK21-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
21612 // CHECK21-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
21613 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
21614 // CHECK21:       omp.inner.for.end:
21615 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21616 // CHECK21:       omp.loop.exit:
21617 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
21618 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21619 // CHECK21-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
21620 // CHECK21-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21621 // CHECK21:       .omp.final.then:
21622 // CHECK21-NEXT:    store i64 11, i64* [[I]], align 8
21623 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21624 // CHECK21:       .omp.final.done:
21625 // CHECK21-NEXT:    ret void
21626 //
21627 //
21628 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
21629 // CHECK22-SAME: () #[[ATTR0:[0-9]+]] {
21630 // CHECK22-NEXT:  entry:
21631 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
21632 // CHECK22-NEXT:    ret void
21633 //
21634 //
21635 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined.
21636 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
21637 // CHECK22-NEXT:  entry:
21638 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21639 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21640 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21641 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21642 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21643 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21644 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21645 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21646 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
21647 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21648 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21649 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21650 // CHECK22-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
21651 // CHECK22-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21652 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21653 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21654 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21655 // CHECK22-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21656 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21657 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
21658 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21659 // CHECK22:       cond.true:
21660 // CHECK22-NEXT:    br label [[COND_END:%.*]]
21661 // CHECK22:       cond.false:
21662 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21663 // CHECK22-NEXT:    br label [[COND_END]]
21664 // CHECK22:       cond.end:
21665 // CHECK22-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21666 // CHECK22-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21667 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21668 // CHECK22-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21669 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21670 // CHECK22:       omp.inner.for.cond:
21671 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
21672 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
21673 // CHECK22-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21674 // CHECK22-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21675 // CHECK22:       omp.inner.for.body:
21676 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
21677 // CHECK22-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
21678 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
21679 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
21680 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21681 // CHECK22:       omp.body.continue:
21682 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21683 // CHECK22:       omp.inner.for.inc:
21684 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
21685 // CHECK22-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
21686 // CHECK22-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
21687 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
21688 // CHECK22:       omp.inner.for.end:
21689 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21690 // CHECK22:       omp.loop.exit:
21691 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21692 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21693 // CHECK22-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
21694 // CHECK22-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21695 // CHECK22:       .omp.final.then:
21696 // CHECK22-NEXT:    store i32 33, i32* [[I]], align 4
21697 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21698 // CHECK22:       .omp.final.done:
21699 // CHECK22-NEXT:    ret void
21700 //
21701 //
21702 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
21703 // CHECK22-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
21704 // CHECK22-NEXT:  entry:
21705 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21706 // CHECK22-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
21707 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21708 // CHECK22-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21709 // CHECK22-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
21710 // CHECK22-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21711 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21712 // CHECK22-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
21713 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21714 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21715 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
21716 // CHECK22-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21717 // CHECK22-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
21718 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21719 // CHECK22-NEXT:    store i16 [[TMP0]], i16* [[CONV3]], align 2
21720 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21721 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8
21722 // CHECK22-NEXT:    [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
21723 // CHECK22-NEXT:    store i32 [[TMP2]], i32* [[CONV4]], align 4
21724 // CHECK22-NEXT:    [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
21725 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 8
21726 // CHECK22-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21727 // CHECK22-NEXT:    store i32 [[TMP4]], i32* [[CONV5]], align 4
21728 // CHECK22-NEXT:    [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
21729 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
21730 // CHECK22-NEXT:    ret void
21731 //
21732 //
21733 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1
21734 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
21735 // CHECK22-NEXT:  entry:
21736 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21737 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21738 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21739 // CHECK22-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
21740 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21741 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
21742 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i64, align 8
21743 // CHECK22-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
21744 // CHECK22-NEXT:    [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
21745 // CHECK22-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
21746 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
21747 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
21748 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
21749 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21750 // CHECK22-NEXT:    [[IT:%.*]] = alloca i64, align 8
21751 // CHECK22-NEXT:    [[LIN4:%.*]] = alloca i32, align 4
21752 // CHECK22-NEXT:    [[A5:%.*]] = alloca i32, align 4
21753 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21754 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21755 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21756 // CHECK22-NEXT:    store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
21757 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21758 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21759 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
21760 // CHECK22-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21761 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 8
21762 // CHECK22-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
21763 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8
21764 // CHECK22-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
21765 // CHECK22-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
21766 // CHECK22-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
21767 // CHECK22-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
21768 // CHECK22-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
21769 // CHECK22-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
21770 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21771 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21772 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
21773 // CHECK22-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
21774 // CHECK22-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
21775 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21776 // CHECK22-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
21777 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21778 // CHECK22:       cond.true:
21779 // CHECK22-NEXT:    br label [[COND_END:%.*]]
21780 // CHECK22:       cond.false:
21781 // CHECK22-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
21782 // CHECK22-NEXT:    br label [[COND_END]]
21783 // CHECK22:       cond.end:
21784 // CHECK22-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
21785 // CHECK22-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
21786 // CHECK22-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
21787 // CHECK22-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
21788 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21789 // CHECK22:       omp.inner.for.cond:
21790 // CHECK22-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
21791 // CHECK22-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17
21792 // CHECK22-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
21793 // CHECK22-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21794 // CHECK22:       omp.inner.for.body:
21795 // CHECK22-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
21796 // CHECK22-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
21797 // CHECK22-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
21798 // CHECK22-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17
21799 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17
21800 // CHECK22-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
21801 // CHECK22-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
21802 // CHECK22-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
21803 // CHECK22-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
21804 // CHECK22-NEXT:    [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
21805 // CHECK22-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
21806 // CHECK22-NEXT:    store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17
21807 // CHECK22-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17
21808 // CHECK22-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
21809 // CHECK22-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
21810 // CHECK22-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17
21811 // CHECK22-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
21812 // CHECK22-NEXT:    [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
21813 // CHECK22-NEXT:    [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
21814 // CHECK22-NEXT:    store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17
21815 // CHECK22-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 8, !llvm.access.group !17
21816 // CHECK22-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
21817 // CHECK22-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
21818 // CHECK22-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
21819 // CHECK22-NEXT:    store i16 [[CONV16]], i16* [[CONV]], align 8, !llvm.access.group !17
21820 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21821 // CHECK22:       omp.body.continue:
21822 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21823 // CHECK22:       omp.inner.for.inc:
21824 // CHECK22-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
21825 // CHECK22-NEXT:    [[ADD17:%.*]] = add i64 [[TMP17]], 1
21826 // CHECK22-NEXT:    store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17
21827 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
21828 // CHECK22:       omp.inner.for.end:
21829 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21830 // CHECK22:       omp.loop.exit:
21831 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
21832 // CHECK22-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21833 // CHECK22-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
21834 // CHECK22-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21835 // CHECK22:       .omp.final.then:
21836 // CHECK22-NEXT:    store i64 400, i64* [[IT]], align 8
21837 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21838 // CHECK22:       .omp.final.done:
21839 // CHECK22-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21840 // CHECK22-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
21841 // CHECK22-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
21842 // CHECK22:       .omp.linear.pu:
21843 // CHECK22-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
21844 // CHECK22-NEXT:    [[CONV18:%.*]] = sext i32 [[TMP22]] to i64
21845 // CHECK22-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
21846 // CHECK22-NEXT:    [[MUL19:%.*]] = mul i64 4, [[TMP23]]
21847 // CHECK22-NEXT:    [[ADD20:%.*]] = add i64 [[CONV18]], [[MUL19]]
21848 // CHECK22-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD20]] to i32
21849 // CHECK22-NEXT:    store i32 [[CONV21]], i32* [[CONV1]], align 8
21850 // CHECK22-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
21851 // CHECK22-NEXT:    [[CONV22:%.*]] = sext i32 [[TMP24]] to i64
21852 // CHECK22-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
21853 // CHECK22-NEXT:    [[MUL23:%.*]] = mul i64 4, [[TMP25]]
21854 // CHECK22-NEXT:    [[ADD24:%.*]] = add i64 [[CONV22]], [[MUL23]]
21855 // CHECK22-NEXT:    [[CONV25:%.*]] = trunc i64 [[ADD24]] to i32
21856 // CHECK22-NEXT:    store i32 [[CONV25]], i32* [[CONV2]], align 8
21857 // CHECK22-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
21858 // CHECK22:       .omp.linear.pu.done:
21859 // CHECK22-NEXT:    ret void
21860 //
21861 //
21862 // CHECK22-LABEL: define {{[^@]+}}@_Z7get_valv
21863 // CHECK22-SAME: () #[[ATTR3:[0-9]+]] {
21864 // CHECK22-NEXT:  entry:
21865 // CHECK22-NEXT:    ret i64 0
21866 //
21867 //
21868 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
21869 // CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
21870 // CHECK22-NEXT:  entry:
21871 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21872 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21873 // CHECK22-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21874 // CHECK22-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21875 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21876 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21877 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21878 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21879 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
21880 // CHECK22-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21881 // CHECK22-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
21882 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
21883 // CHECK22-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
21884 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21885 // CHECK22-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
21886 // CHECK22-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21887 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
21888 // CHECK22-NEXT:    ret void
21889 //
21890 //
21891 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2
21892 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] {
21893 // CHECK22-NEXT:  entry:
21894 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21895 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21896 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21897 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21898 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21899 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i16, align 2
21900 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21901 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21902 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21903 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21904 // CHECK22-NEXT:    [[IT:%.*]] = alloca i16, align 2
21905 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21906 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21907 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21908 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21909 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21910 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21911 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21912 // CHECK22-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
21913 // CHECK22-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21914 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21915 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21916 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21917 // CHECK22-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21918 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21919 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
21920 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21921 // CHECK22:       cond.true:
21922 // CHECK22-NEXT:    br label [[COND_END:%.*]]
21923 // CHECK22:       cond.false:
21924 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21925 // CHECK22-NEXT:    br label [[COND_END]]
21926 // CHECK22:       cond.end:
21927 // CHECK22-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21928 // CHECK22-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21929 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21930 // CHECK22-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21931 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21932 // CHECK22:       omp.inner.for.cond:
21933 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
21934 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
21935 // CHECK22-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21936 // CHECK22-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21937 // CHECK22:       omp.inner.for.body:
21938 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
21939 // CHECK22-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
21940 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
21941 // CHECK22-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
21942 // CHECK22-NEXT:    store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20
21943 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !20
21944 // CHECK22-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
21945 // CHECK22-NEXT:    store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !20
21946 // CHECK22-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !20
21947 // CHECK22-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
21948 // CHECK22-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
21949 // CHECK22-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
21950 // CHECK22-NEXT:    store i16 [[CONV7]], i16* [[CONV1]], align 8, !llvm.access.group !20
21951 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21952 // CHECK22:       omp.body.continue:
21953 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21954 // CHECK22:       omp.inner.for.inc:
21955 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
21956 // CHECK22-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
21957 // CHECK22-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
21958 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
21959 // CHECK22:       omp.inner.for.end:
21960 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21961 // CHECK22:       omp.loop.exit:
21962 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21963 // CHECK22-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21964 // CHECK22-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
21965 // CHECK22-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21966 // CHECK22:       .omp.final.then:
21967 // CHECK22-NEXT:    store i16 22, i16* [[IT]], align 2
21968 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21969 // CHECK22:       .omp.final.done:
21970 // CHECK22-NEXT:    ret void
21971 //
21972 //
21973 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
21974 // CHECK22-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
21975 // CHECK22-NEXT:  entry:
21976 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21977 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
21978 // CHECK22-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21979 // CHECK22-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
21980 // CHECK22-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
21981 // CHECK22-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21982 // CHECK22-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
21983 // CHECK22-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
21984 // CHECK22-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
21985 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21986 // CHECK22-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21987 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
21988 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21989 // CHECK22-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
21990 // CHECK22-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21991 // CHECK22-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
21992 // CHECK22-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
21993 // CHECK22-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21994 // CHECK22-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
21995 // CHECK22-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
21996 // CHECK22-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
21997 // CHECK22-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21998 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21999 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
22000 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22001 // CHECK22-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
22002 // CHECK22-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
22003 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22004 // CHECK22-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
22005 // CHECK22-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
22006 // CHECK22-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
22007 // CHECK22-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
22008 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
22009 // CHECK22-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22010 // CHECK22-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
22011 // CHECK22-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
22012 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
22013 // CHECK22-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
22014 // CHECK22-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
22015 // CHECK22-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
22016 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
22017 // CHECK22-NEXT:    ret void
22018 //
22019 //
22020 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3
22021 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
22022 // CHECK22-NEXT:  entry:
22023 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22024 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22025 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22026 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
22027 // CHECK22-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22028 // CHECK22-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
22029 // CHECK22-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
22030 // CHECK22-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22031 // CHECK22-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
22032 // CHECK22-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
22033 // CHECK22-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
22034 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22035 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22036 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i8, align 1
22037 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22038 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22039 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22040 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22041 // CHECK22-NEXT:    [[IT:%.*]] = alloca i8, align 1
22042 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22043 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22044 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22045 // CHECK22-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
22046 // CHECK22-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22047 // CHECK22-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
22048 // CHECK22-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
22049 // CHECK22-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22050 // CHECK22-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
22051 // CHECK22-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
22052 // CHECK22-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
22053 // CHECK22-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22054 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22055 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
22056 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22057 // CHECK22-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
22058 // CHECK22-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
22059 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22060 // CHECK22-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
22061 // CHECK22-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
22062 // CHECK22-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
22063 // CHECK22-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
22064 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22065 // CHECK22-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
22066 // CHECK22-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22067 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22068 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
22069 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22070 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
22071 // CHECK22-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
22072 // CHECK22-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
22073 // CHECK22:       omp.dispatch.cond:
22074 // CHECK22-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22075 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
22076 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22077 // CHECK22:       cond.true:
22078 // CHECK22-NEXT:    br label [[COND_END:%.*]]
22079 // CHECK22:       cond.false:
22080 // CHECK22-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22081 // CHECK22-NEXT:    br label [[COND_END]]
22082 // CHECK22:       cond.end:
22083 // CHECK22-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
22084 // CHECK22-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22085 // CHECK22-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22086 // CHECK22-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
22087 // CHECK22-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22088 // CHECK22-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22089 // CHECK22-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
22090 // CHECK22-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
22091 // CHECK22:       omp.dispatch.body:
22092 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22093 // CHECK22:       omp.inner.for.cond:
22094 // CHECK22-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
22095 // CHECK22-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
22096 // CHECK22-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
22097 // CHECK22-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22098 // CHECK22:       omp.inner.for.body:
22099 // CHECK22-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
22100 // CHECK22-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
22101 // CHECK22-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
22102 // CHECK22-NEXT:    [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
22103 // CHECK22-NEXT:    store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23
22104 // CHECK22-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !23
22105 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
22106 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8, !llvm.access.group !23
22107 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
22108 // CHECK22-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23
22109 // CHECK22-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
22110 // CHECK22-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
22111 // CHECK22-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
22112 // CHECK22-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
22113 // CHECK22-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
22114 // CHECK22-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
22115 // CHECK22-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
22116 // CHECK22-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
22117 // CHECK22-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
22118 // CHECK22-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23
22119 // CHECK22-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
22120 // CHECK22-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
22121 // CHECK22-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
22122 // CHECK22-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
22123 // CHECK22-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23
22124 // CHECK22-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
22125 // CHECK22-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
22126 // CHECK22-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
22127 // CHECK22-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
22128 // CHECK22-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
22129 // CHECK22-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23
22130 // CHECK22-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
22131 // CHECK22-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23
22132 // CHECK22-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
22133 // CHECK22-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23
22134 // CHECK22-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
22135 // CHECK22-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23
22136 // CHECK22-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
22137 // CHECK22-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
22138 // CHECK22-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
22139 // CHECK22-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23
22140 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22141 // CHECK22:       omp.body.continue:
22142 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22143 // CHECK22:       omp.inner.for.inc:
22144 // CHECK22-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
22145 // CHECK22-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
22146 // CHECK22-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
22147 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
22148 // CHECK22:       omp.inner.for.end:
22149 // CHECK22-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
22150 // CHECK22:       omp.dispatch.inc:
22151 // CHECK22-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22152 // CHECK22-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
22153 // CHECK22-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
22154 // CHECK22-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
22155 // CHECK22-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22156 // CHECK22-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
22157 // CHECK22-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
22158 // CHECK22-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
22159 // CHECK22-NEXT:    br label [[OMP_DISPATCH_COND]]
22160 // CHECK22:       omp.dispatch.end:
22161 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
22162 // CHECK22-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22163 // CHECK22-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
22164 // CHECK22-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22165 // CHECK22:       .omp.final.then:
22166 // CHECK22-NEXT:    store i8 96, i8* [[IT]], align 1
22167 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22168 // CHECK22:       .omp.final.done:
22169 // CHECK22-NEXT:    ret void
22170 //
22171 //
22172 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
22173 // CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22174 // CHECK22-NEXT:  entry:
22175 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22176 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22177 // CHECK22-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
22178 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22179 // CHECK22-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22180 // CHECK22-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22181 // CHECK22-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
22182 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22183 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22184 // CHECK22-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
22185 // CHECK22-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22186 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22187 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22188 // CHECK22-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
22189 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22190 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
22191 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22192 // CHECK22-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
22193 // CHECK22-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
22194 // CHECK22-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
22195 // CHECK22-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22196 // CHECK22-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
22197 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22198 // CHECK22-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
22199 // CHECK22-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
22200 // CHECK22-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
22201 // CHECK22-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
22202 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
22203 // CHECK22-NEXT:    ret void
22204 //
22205 //
22206 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4
22207 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
22208 // CHECK22-NEXT:  entry:
22209 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22210 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22211 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22212 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22213 // CHECK22-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
22214 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22215 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22216 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22217 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22218 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22219 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22220 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22221 // CHECK22-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
22222 // CHECK22-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22223 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22224 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22225 // CHECK22-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
22226 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22227 // CHECK22-NEXT:    ret void
22228 //
22229 //
22230 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
22231 // CHECK22-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
22232 // CHECK22-NEXT:  entry:
22233 // CHECK22-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
22234 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
22235 // CHECK22-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22236 // CHECK22-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22237 // CHECK22-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
22238 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22239 // CHECK22-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
22240 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
22241 // CHECK22-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
22242 // CHECK22-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
22243 // CHECK22-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
22244 // CHECK22-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
22245 // CHECK22-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
22246 // CHECK22-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
22247 // CHECK22-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22248 // CHECK22-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22249 // CHECK22-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
22250 // CHECK22-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22251 // CHECK22-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
22252 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
22253 // CHECK22-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22254 // CHECK22-NEXT:    [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22255 // CHECK22-NEXT:    [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8
22256 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
22257 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[CONV]], align 8
22258 // CHECK22-NEXT:    [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
22259 // CHECK22-NEXT:    store i32 [[TMP5]], i32* [[CONV4]], align 4
22260 // CHECK22-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
22261 // CHECK22-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
22262 // CHECK22-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
22263 // CHECK22-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
22264 // CHECK22-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
22265 // CHECK22-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
22266 // CHECK22-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
22267 // CHECK22-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 8
22268 // CHECK22-NEXT:    [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1
22269 // CHECK22-NEXT:    br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
22270 // CHECK22:       omp_if.then:
22271 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]])
22272 // CHECK22-NEXT:    br label [[OMP_IF_END:%.*]]
22273 // CHECK22:       omp_if.else:
22274 // CHECK22-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
22275 // CHECK22-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
22276 // CHECK22-NEXT:    call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]]
22277 // CHECK22-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
22278 // CHECK22-NEXT:    br label [[OMP_IF_END]]
22279 // CHECK22:       omp_if.end:
22280 // CHECK22-NEXT:    ret void
22281 //
22282 //
22283 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..5
22284 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
22285 // CHECK22-NEXT:  entry:
22286 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22287 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22288 // CHECK22-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
22289 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
22290 // CHECK22-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22291 // CHECK22-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22292 // CHECK22-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
22293 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22294 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
22295 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i64, align 8
22296 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
22297 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
22298 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
22299 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22300 // CHECK22-NEXT:    [[IT:%.*]] = alloca i64, align 8
22301 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22302 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22303 // CHECK22-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
22304 // CHECK22-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
22305 // CHECK22-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22306 // CHECK22-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22307 // CHECK22-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
22308 // CHECK22-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22309 // CHECK22-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
22310 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
22311 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22312 // CHECK22-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22313 // CHECK22-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
22314 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
22315 // CHECK22-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
22316 // CHECK22-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
22317 // CHECK22-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
22318 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22319 // CHECK22-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 8
22320 // CHECK22-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
22321 // CHECK22-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
22322 // CHECK22:       omp_if.then:
22323 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22324 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
22325 // CHECK22-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
22326 // CHECK22-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22327 // CHECK22-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
22328 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22329 // CHECK22:       cond.true:
22330 // CHECK22-NEXT:    br label [[COND_END:%.*]]
22331 // CHECK22:       cond.false:
22332 // CHECK22-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22333 // CHECK22-NEXT:    br label [[COND_END]]
22334 // CHECK22:       cond.end:
22335 // CHECK22-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
22336 // CHECK22-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
22337 // CHECK22-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
22338 // CHECK22-NEXT:    store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
22339 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22340 // CHECK22:       omp.inner.for.cond:
22341 // CHECK22-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
22342 // CHECK22-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26
22343 // CHECK22-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
22344 // CHECK22-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22345 // CHECK22:       omp.inner.for.body:
22346 // CHECK22-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
22347 // CHECK22-NEXT:    [[MUL:%.*]] = mul i64 [[TMP12]], 400
22348 // CHECK22-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
22349 // CHECK22-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26
22350 // CHECK22-NEXT:    [[TMP13:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !26
22351 // CHECK22-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
22352 // CHECK22-NEXT:    [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00
22353 // CHECK22-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
22354 // CHECK22-NEXT:    store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group !26
22355 // CHECK22-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
22356 // CHECK22-NEXT:    [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
22357 // CHECK22-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
22358 // CHECK22-NEXT:    store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26
22359 // CHECK22-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
22360 // CHECK22-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
22361 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
22362 // CHECK22-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
22363 // CHECK22-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !26
22364 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22365 // CHECK22:       omp.body.continue:
22366 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22367 // CHECK22:       omp.inner.for.inc:
22368 // CHECK22-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
22369 // CHECK22-NEXT:    [[ADD9:%.*]] = add i64 [[TMP16]], 1
22370 // CHECK22-NEXT:    store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26
22371 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
22372 // CHECK22:       omp.inner.for.end:
22373 // CHECK22-NEXT:    br label [[OMP_IF_END:%.*]]
22374 // CHECK22:       omp_if.else:
22375 // CHECK22-NEXT:    [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22376 // CHECK22-NEXT:    [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
22377 // CHECK22-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
22378 // CHECK22-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22379 // CHECK22-NEXT:    [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3
22380 // CHECK22-NEXT:    br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
22381 // CHECK22:       cond.true11:
22382 // CHECK22-NEXT:    br label [[COND_END13:%.*]]
22383 // CHECK22:       cond.false12:
22384 // CHECK22-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22385 // CHECK22-NEXT:    br label [[COND_END13]]
22386 // CHECK22:       cond.end13:
22387 // CHECK22-NEXT:    [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ]
22388 // CHECK22-NEXT:    store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8
22389 // CHECK22-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
22390 // CHECK22-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
22391 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND15:%.*]]
22392 // CHECK22:       omp.inner.for.cond15:
22393 // CHECK22-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22394 // CHECK22-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22395 // CHECK22-NEXT:    [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
22396 // CHECK22-NEXT:    br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]]
22397 // CHECK22:       omp.inner.for.body17:
22398 // CHECK22-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22399 // CHECK22-NEXT:    [[MUL18:%.*]] = mul i64 [[TMP24]], 400
22400 // CHECK22-NEXT:    [[SUB19:%.*]] = sub i64 2000, [[MUL18]]
22401 // CHECK22-NEXT:    store i64 [[SUB19]], i64* [[IT]], align 8
22402 // CHECK22-NEXT:    [[TMP25:%.*]] = load i32, i32* [[CONV]], align 8
22403 // CHECK22-NEXT:    [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double
22404 // CHECK22-NEXT:    [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00
22405 // CHECK22-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
22406 // CHECK22-NEXT:    store double [[ADD21]], double* [[A22]], align 8
22407 // CHECK22-NEXT:    [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
22408 // CHECK22-NEXT:    [[TMP26:%.*]] = load double, double* [[A23]], align 8
22409 // CHECK22-NEXT:    [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00
22410 // CHECK22-NEXT:    store double [[INC24]], double* [[A23]], align 8
22411 // CHECK22-NEXT:    [[CONV25:%.*]] = fptosi double [[INC24]] to i16
22412 // CHECK22-NEXT:    [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]]
22413 // CHECK22-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]]
22414 // CHECK22-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
22415 // CHECK22-NEXT:    store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2
22416 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE28:%.*]]
22417 // CHECK22:       omp.body.continue28:
22418 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC29:%.*]]
22419 // CHECK22:       omp.inner.for.inc29:
22420 // CHECK22-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
22421 // CHECK22-NEXT:    [[ADD30:%.*]] = add i64 [[TMP28]], 1
22422 // CHECK22-NEXT:    store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8
22423 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP30:![0-9]+]]
22424 // CHECK22:       omp.inner.for.end31:
22425 // CHECK22-NEXT:    br label [[OMP_IF_END]]
22426 // CHECK22:       omp_if.end:
22427 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22428 // CHECK22:       omp.loop.exit:
22429 // CHECK22-NEXT:    [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22430 // CHECK22-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
22431 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
22432 // CHECK22-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22433 // CHECK22-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
22434 // CHECK22-NEXT:    br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22435 // CHECK22:       .omp.final.then:
22436 // CHECK22-NEXT:    store i64 400, i64* [[IT]], align 8
22437 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22438 // CHECK22:       .omp.final.done:
22439 // CHECK22-NEXT:    ret void
22440 //
22441 //
22442 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
22443 // CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22444 // CHECK22-NEXT:  entry:
22445 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22446 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22447 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22448 // CHECK22-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22449 // CHECK22-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22450 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22451 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22452 // CHECK22-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22453 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22454 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22455 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22456 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
22457 // CHECK22-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22458 // CHECK22-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
22459 // CHECK22-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
22460 // CHECK22-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
22461 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22462 // CHECK22-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
22463 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22464 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
22465 // CHECK22-NEXT:    ret void
22466 //
22467 //
22468 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6
22469 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
22470 // CHECK22-NEXT:  entry:
22471 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22472 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22473 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22474 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22475 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22476 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
22477 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i64, align 8
22478 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
22479 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
22480 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
22481 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22482 // CHECK22-NEXT:    [[I:%.*]] = alloca i64, align 8
22483 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22484 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22485 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22486 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22487 // CHECK22-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22488 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22489 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22490 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22491 // CHECK22-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
22492 // CHECK22-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
22493 // CHECK22-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
22494 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22495 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22496 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
22497 // CHECK22-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
22498 // CHECK22-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22499 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
22500 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22501 // CHECK22:       cond.true:
22502 // CHECK22-NEXT:    br label [[COND_END:%.*]]
22503 // CHECK22:       cond.false:
22504 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22505 // CHECK22-NEXT:    br label [[COND_END]]
22506 // CHECK22:       cond.end:
22507 // CHECK22-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
22508 // CHECK22-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
22509 // CHECK22-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
22510 // CHECK22-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
22511 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22512 // CHECK22:       omp.inner.for.cond:
22513 // CHECK22-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
22514 // CHECK22-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !32
22515 // CHECK22-NEXT:    [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
22516 // CHECK22-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22517 // CHECK22:       omp.inner.for.body:
22518 // CHECK22-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
22519 // CHECK22-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
22520 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
22521 // CHECK22-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32
22522 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !32
22523 // CHECK22-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
22524 // CHECK22-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8, !llvm.access.group !32
22525 // CHECK22-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8, !llvm.access.group !32
22526 // CHECK22-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
22527 // CHECK22-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
22528 // CHECK22-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
22529 // CHECK22-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8, !llvm.access.group !32
22530 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
22531 // CHECK22-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
22532 // CHECK22-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
22533 // CHECK22-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !32
22534 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22535 // CHECK22:       omp.body.continue:
22536 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22537 // CHECK22:       omp.inner.for.inc:
22538 // CHECK22-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
22539 // CHECK22-NEXT:    [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
22540 // CHECK22-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32
22541 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
22542 // CHECK22:       omp.inner.for.end:
22543 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22544 // CHECK22:       omp.loop.exit:
22545 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
22546 // CHECK22-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22547 // CHECK22-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
22548 // CHECK22-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22549 // CHECK22:       .omp.final.then:
22550 // CHECK22-NEXT:    store i64 11, i64* [[I]], align 8
22551 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22552 // CHECK22:       .omp.final.done:
22553 // CHECK22-NEXT:    ret void
22554 //
22555 //
22556 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
22557 // CHECK23-SAME: () #[[ATTR0:[0-9]+]] {
22558 // CHECK23-NEXT:  entry:
22559 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
22560 // CHECK23-NEXT:    ret void
22561 //
22562 //
22563 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined.
22564 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
22565 // CHECK23-NEXT:  entry:
22566 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
22567 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
22568 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22569 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22570 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22571 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22572 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22573 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22574 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
22575 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
22576 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
22577 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22578 // CHECK23-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
22579 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22580 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22581 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
22582 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22583 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22584 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22585 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
22586 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22587 // CHECK23:       cond.true:
22588 // CHECK23-NEXT:    br label [[COND_END:%.*]]
22589 // CHECK23:       cond.false:
22590 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22591 // CHECK23-NEXT:    br label [[COND_END]]
22592 // CHECK23:       cond.end:
22593 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22594 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22595 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22596 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22597 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22598 // CHECK23:       omp.inner.for.cond:
22599 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
22600 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
22601 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22602 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22603 // CHECK23:       omp.inner.for.body:
22604 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
22605 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
22606 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
22607 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
22608 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22609 // CHECK23:       omp.body.continue:
22610 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22611 // CHECK23:       omp.inner.for.inc:
22612 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
22613 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
22614 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
22615 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
22616 // CHECK23:       omp.inner.for.end:
22617 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22618 // CHECK23:       omp.loop.exit:
22619 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22620 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22621 // CHECK23-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
22622 // CHECK23-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22623 // CHECK23:       .omp.final.then:
22624 // CHECK23-NEXT:    store i32 33, i32* [[I]], align 4
22625 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22626 // CHECK23:       .omp.final.done:
22627 // CHECK23-NEXT:    ret void
22628 //
22629 //
22630 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
22631 // CHECK23-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
22632 // CHECK23-NEXT:  entry:
22633 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
22634 // CHECK23-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
22635 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22636 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
22637 // CHECK23-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
22638 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
22639 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
22640 // CHECK23-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
22641 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22642 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
22643 // CHECK23-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
22644 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
22645 // CHECK23-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
22646 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
22647 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
22648 // CHECK23-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
22649 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
22650 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
22651 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
22652 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
22653 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
22654 // CHECK23-NEXT:    ret void
22655 //
22656 //
22657 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1
22658 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
22659 // CHECK23-NEXT:  entry:
22660 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
22661 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
22662 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
22663 // CHECK23-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
22664 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22665 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
22666 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i64, align 4
22667 // CHECK23-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
22668 // CHECK23-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
22669 // CHECK23-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
22670 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
22671 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
22672 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
22673 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22674 // CHECK23-NEXT:    [[IT:%.*]] = alloca i64, align 8
22675 // CHECK23-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
22676 // CHECK23-NEXT:    [[A3:%.*]] = alloca i32, align 4
22677 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
22678 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
22679 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
22680 // CHECK23-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
22681 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22682 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
22683 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
22684 // CHECK23-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
22685 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
22686 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
22687 // CHECK23-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
22688 // CHECK23-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
22689 // CHECK23-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
22690 // CHECK23-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
22691 // CHECK23-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
22692 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22693 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
22694 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
22695 // CHECK23-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
22696 // CHECK23-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
22697 // CHECK23-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22698 // CHECK23-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
22699 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22700 // CHECK23:       cond.true:
22701 // CHECK23-NEXT:    br label [[COND_END:%.*]]
22702 // CHECK23:       cond.false:
22703 // CHECK23-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
22704 // CHECK23-NEXT:    br label [[COND_END]]
22705 // CHECK23:       cond.end:
22706 // CHECK23-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
22707 // CHECK23-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
22708 // CHECK23-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
22709 // CHECK23-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
22710 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22711 // CHECK23:       omp.inner.for.cond:
22712 // CHECK23-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
22713 // CHECK23-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
22714 // CHECK23-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
22715 // CHECK23-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22716 // CHECK23:       omp.inner.for.body:
22717 // CHECK23-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
22718 // CHECK23-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
22719 // CHECK23-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
22720 // CHECK23-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
22721 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18
22722 // CHECK23-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
22723 // CHECK23-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
22724 // CHECK23-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
22725 // CHECK23-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
22726 // CHECK23-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
22727 // CHECK23-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
22728 // CHECK23-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18
22729 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
22730 // CHECK23-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
22731 // CHECK23-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
22732 // CHECK23-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
22733 // CHECK23-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
22734 // CHECK23-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
22735 // CHECK23-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
22736 // CHECK23-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
22737 // CHECK23-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
22738 // CHECK23-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
22739 // CHECK23-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
22740 // CHECK23-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
22741 // CHECK23-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
22742 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22743 // CHECK23:       omp.body.continue:
22744 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22745 // CHECK23:       omp.inner.for.inc:
22746 // CHECK23-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
22747 // CHECK23-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
22748 // CHECK23-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
22749 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
22750 // CHECK23:       omp.inner.for.end:
22751 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22752 // CHECK23:       omp.loop.exit:
22753 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
22754 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22755 // CHECK23-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
22756 // CHECK23-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22757 // CHECK23:       .omp.final.then:
22758 // CHECK23-NEXT:    store i64 400, i64* [[IT]], align 8
22759 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22760 // CHECK23:       .omp.final.done:
22761 // CHECK23-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22762 // CHECK23-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
22763 // CHECK23-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
22764 // CHECK23:       .omp.linear.pu:
22765 // CHECK23-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
22766 // CHECK23-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
22767 // CHECK23-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
22768 // CHECK23-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP23]]
22769 // CHECK23-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
22770 // CHECK23-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
22771 // CHECK23-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
22772 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
22773 // CHECK23-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
22774 // CHECK23-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
22775 // CHECK23-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP25]]
22776 // CHECK23-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
22777 // CHECK23-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
22778 // CHECK23-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
22779 // CHECK23-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
22780 // CHECK23:       .omp.linear.pu.done:
22781 // CHECK23-NEXT:    ret void
22782 //
22783 //
22784 // CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv
22785 // CHECK23-SAME: () #[[ATTR3:[0-9]+]] {
22786 // CHECK23-NEXT:  entry:
22787 // CHECK23-NEXT:    ret i64 0
22788 //
22789 //
22790 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
22791 // CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
22792 // CHECK23-NEXT:  entry:
22793 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22794 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
22795 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
22796 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
22797 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22798 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
22799 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
22800 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
22801 // CHECK23-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
22802 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
22803 // CHECK23-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
22804 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
22805 // CHECK23-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
22806 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
22807 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
22808 // CHECK23-NEXT:    ret void
22809 //
22810 //
22811 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2
22812 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
22813 // CHECK23-NEXT:  entry:
22814 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
22815 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
22816 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22817 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
22818 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22819 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i16, align 2
22820 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22821 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22822 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22823 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22824 // CHECK23-NEXT:    [[IT:%.*]] = alloca i16, align 2
22825 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
22826 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
22827 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22828 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
22829 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
22830 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22831 // CHECK23-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
22832 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22833 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22834 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
22835 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22836 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22837 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22838 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
22839 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22840 // CHECK23:       cond.true:
22841 // CHECK23-NEXT:    br label [[COND_END:%.*]]
22842 // CHECK23:       cond.false:
22843 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22844 // CHECK23-NEXT:    br label [[COND_END]]
22845 // CHECK23:       cond.end:
22846 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22847 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22848 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22849 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22850 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22851 // CHECK23:       omp.inner.for.cond:
22852 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
22853 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
22854 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22855 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22856 // CHECK23:       omp.inner.for.body:
22857 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
22858 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
22859 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
22860 // CHECK23-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
22861 // CHECK23-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
22862 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
22863 // CHECK23-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
22864 // CHECK23-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
22865 // CHECK23-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
22866 // CHECK23-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
22867 // CHECK23-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
22868 // CHECK23-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
22869 // CHECK23-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
22870 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22871 // CHECK23:       omp.body.continue:
22872 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22873 // CHECK23:       omp.inner.for.inc:
22874 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
22875 // CHECK23-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
22876 // CHECK23-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
22877 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
22878 // CHECK23:       omp.inner.for.end:
22879 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22880 // CHECK23:       omp.loop.exit:
22881 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22882 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22883 // CHECK23-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
22884 // CHECK23-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22885 // CHECK23:       .omp.final.then:
22886 // CHECK23-NEXT:    store i16 22, i16* [[IT]], align 2
22887 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22888 // CHECK23:       .omp.final.done:
22889 // CHECK23-NEXT:    ret void
22890 //
22891 //
22892 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
22893 // CHECK23-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
22894 // CHECK23-NEXT:  entry:
22895 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22896 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
22897 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
22898 // CHECK23-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
22899 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
22900 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
22901 // CHECK23-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
22902 // CHECK23-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
22903 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
22904 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
22905 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
22906 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
22907 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22908 // CHECK23-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
22909 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
22910 // CHECK23-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
22911 // CHECK23-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
22912 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
22913 // CHECK23-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
22914 // CHECK23-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
22915 // CHECK23-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
22916 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
22917 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
22918 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
22919 // CHECK23-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
22920 // CHECK23-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
22921 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
22922 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
22923 // CHECK23-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
22924 // CHECK23-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
22925 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
22926 // CHECK23-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
22927 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
22928 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
22929 // CHECK23-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
22930 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
22931 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
22932 // CHECK23-NEXT:    ret void
22933 //
22934 //
22935 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3
22936 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
22937 // CHECK23-NEXT:  entry:
22938 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
22939 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
22940 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
22941 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
22942 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
22943 // CHECK23-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
22944 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
22945 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
22946 // CHECK23-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
22947 // CHECK23-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
22948 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
22949 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
22950 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22951 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i8, align 1
22952 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22953 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22954 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22955 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22956 // CHECK23-NEXT:    [[IT:%.*]] = alloca i8, align 1
22957 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
22958 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
22959 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
22960 // CHECK23-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
22961 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
22962 // CHECK23-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
22963 // CHECK23-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
22964 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
22965 // CHECK23-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
22966 // CHECK23-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
22967 // CHECK23-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
22968 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
22969 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
22970 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
22971 // CHECK23-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
22972 // CHECK23-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
22973 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
22974 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
22975 // CHECK23-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
22976 // CHECK23-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
22977 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22978 // CHECK23-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
22979 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22980 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22981 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
22982 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
22983 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
22984 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
22985 // CHECK23-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
22986 // CHECK23:       omp.dispatch.cond:
22987 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22988 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
22989 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22990 // CHECK23:       cond.true:
22991 // CHECK23-NEXT:    br label [[COND_END:%.*]]
22992 // CHECK23:       cond.false:
22993 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22994 // CHECK23-NEXT:    br label [[COND_END]]
22995 // CHECK23:       cond.end:
22996 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
22997 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22998 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22999 // CHECK23-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
23000 // CHECK23-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23001 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23002 // CHECK23-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
23003 // CHECK23-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
23004 // CHECK23:       omp.dispatch.body:
23005 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23006 // CHECK23:       omp.inner.for.cond:
23007 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23008 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
23009 // CHECK23-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
23010 // CHECK23-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23011 // CHECK23:       omp.inner.for.body:
23012 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23013 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
23014 // CHECK23-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
23015 // CHECK23-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
23016 // CHECK23-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24
23017 // CHECK23-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24
23018 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
23019 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24
23020 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
23021 // CHECK23-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
23022 // CHECK23-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
23023 // CHECK23-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
23024 // CHECK23-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
23025 // CHECK23-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
23026 // CHECK23-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
23027 // CHECK23-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
23028 // CHECK23-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
23029 // CHECK23-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
23030 // CHECK23-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
23031 // CHECK23-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
23032 // CHECK23-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
23033 // CHECK23-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
23034 // CHECK23-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
23035 // CHECK23-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
23036 // CHECK23-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
23037 // CHECK23-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
23038 // CHECK23-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
23039 // CHECK23-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
23040 // CHECK23-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
23041 // CHECK23-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
23042 // CHECK23-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
23043 // CHECK23-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
23044 // CHECK23-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24
23045 // CHECK23-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
23046 // CHECK23-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24
23047 // CHECK23-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
23048 // CHECK23-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24
23049 // CHECK23-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
23050 // CHECK23-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
23051 // CHECK23-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
23052 // CHECK23-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24
23053 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23054 // CHECK23:       omp.body.continue:
23055 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23056 // CHECK23:       omp.inner.for.inc:
23057 // CHECK23-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23058 // CHECK23-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
23059 // CHECK23-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23060 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
23061 // CHECK23:       omp.inner.for.end:
23062 // CHECK23-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
23063 // CHECK23:       omp.dispatch.inc:
23064 // CHECK23-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23065 // CHECK23-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
23066 // CHECK23-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
23067 // CHECK23-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
23068 // CHECK23-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23069 // CHECK23-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
23070 // CHECK23-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
23071 // CHECK23-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
23072 // CHECK23-NEXT:    br label [[OMP_DISPATCH_COND]]
23073 // CHECK23:       omp.dispatch.end:
23074 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
23075 // CHECK23-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23076 // CHECK23-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
23077 // CHECK23-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23078 // CHECK23:       .omp.final.then:
23079 // CHECK23-NEXT:    store i8 96, i8* [[IT]], align 1
23080 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23081 // CHECK23:       .omp.final.done:
23082 // CHECK23-NEXT:    ret void
23083 //
23084 //
23085 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
23086 // CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23087 // CHECK23-NEXT:  entry:
23088 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23089 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23090 // CHECK23-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
23091 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23092 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23093 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23094 // CHECK23-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
23095 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23096 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23097 // CHECK23-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
23098 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23099 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23100 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
23101 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23102 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
23103 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
23104 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
23105 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
23106 // CHECK23-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23107 // CHECK23-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
23108 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23109 // CHECK23-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
23110 // CHECK23-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
23111 // CHECK23-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
23112 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
23113 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
23114 // CHECK23-NEXT:    ret void
23115 //
23116 //
23117 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4
23118 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
23119 // CHECK23-NEXT:  entry:
23120 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23121 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23122 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23123 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23124 // CHECK23-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
23125 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23126 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23127 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23128 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23129 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23130 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23131 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23132 // CHECK23-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
23133 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23134 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23135 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
23136 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23137 // CHECK23-NEXT:    ret void
23138 //
23139 //
23140 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
23141 // CHECK23-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
23142 // CHECK23-NEXT:  entry:
23143 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
23144 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
23145 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23146 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23147 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
23148 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23149 // CHECK23-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
23150 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
23151 // CHECK23-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
23152 // CHECK23-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
23153 // CHECK23-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
23154 // CHECK23-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
23155 // CHECK23-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
23156 // CHECK23-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
23157 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23158 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23159 // CHECK23-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
23160 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23161 // CHECK23-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
23162 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23163 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23164 // CHECK23-NEXT:    [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
23165 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
23166 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
23167 // CHECK23-NEXT:    store i32 [[TMP5]], i32* [[B_CASTED]], align 4
23168 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
23169 // CHECK23-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
23170 // CHECK23-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
23171 // CHECK23-NEXT:    [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
23172 // CHECK23-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
23173 // CHECK23-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
23174 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
23175 // CHECK23-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
23176 // CHECK23-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
23177 // CHECK23-NEXT:    br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
23178 // CHECK23:       omp_if.then:
23179 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
23180 // CHECK23-NEXT:    br label [[OMP_IF_END:%.*]]
23181 // CHECK23:       omp_if.else:
23182 // CHECK23-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
23183 // CHECK23-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
23184 // CHECK23-NEXT:    call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]]
23185 // CHECK23-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
23186 // CHECK23-NEXT:    br label [[OMP_IF_END]]
23187 // CHECK23:       omp_if.end:
23188 // CHECK23-NEXT:    ret void
23189 //
23190 //
23191 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5
23192 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
23193 // CHECK23-NEXT:  entry:
23194 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23195 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23196 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
23197 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
23198 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23199 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23200 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
23201 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23202 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
23203 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i64, align 4
23204 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
23205 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
23206 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
23207 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23208 // CHECK23-NEXT:    [[IT:%.*]] = alloca i64, align 8
23209 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23210 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23211 // CHECK23-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
23212 // CHECK23-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
23213 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23214 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23215 // CHECK23-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
23216 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23217 // CHECK23-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
23218 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23219 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23220 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
23221 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
23222 // CHECK23-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
23223 // CHECK23-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
23224 // CHECK23-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
23225 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23226 // CHECK23-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
23227 // CHECK23-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
23228 // CHECK23-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
23229 // CHECK23:       omp_if.then:
23230 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23231 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
23232 // CHECK23-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
23233 // CHECK23-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23234 // CHECK23-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
23235 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23236 // CHECK23:       cond.true:
23237 // CHECK23-NEXT:    br label [[COND_END:%.*]]
23238 // CHECK23:       cond.false:
23239 // CHECK23-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23240 // CHECK23-NEXT:    br label [[COND_END]]
23241 // CHECK23:       cond.end:
23242 // CHECK23-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
23243 // CHECK23-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
23244 // CHECK23-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
23245 // CHECK23-NEXT:    store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
23246 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23247 // CHECK23:       omp.inner.for.cond:
23248 // CHECK23-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
23249 // CHECK23-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27
23250 // CHECK23-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
23251 // CHECK23-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23252 // CHECK23:       omp.inner.for.body:
23253 // CHECK23-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
23254 // CHECK23-NEXT:    [[MUL:%.*]] = mul i64 [[TMP12]], 400
23255 // CHECK23-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
23256 // CHECK23-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27
23257 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27
23258 // CHECK23-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
23259 // CHECK23-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
23260 // CHECK23-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
23261 // CHECK23-NEXT:    store double [[ADD]], double* [[A]], align 4, !nontemporal !28, !llvm.access.group !27
23262 // CHECK23-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
23263 // CHECK23-NEXT:    [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27
23264 // CHECK23-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
23265 // CHECK23-NEXT:    store double [[INC]], double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27
23266 // CHECK23-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
23267 // CHECK23-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
23268 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
23269 // CHECK23-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
23270 // CHECK23-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !27
23271 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23272 // CHECK23:       omp.body.continue:
23273 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23274 // CHECK23:       omp.inner.for.inc:
23275 // CHECK23-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
23276 // CHECK23-NEXT:    [[ADD8:%.*]] = add i64 [[TMP16]], 1
23277 // CHECK23-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
23278 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
23279 // CHECK23:       omp.inner.for.end:
23280 // CHECK23-NEXT:    br label [[OMP_IF_END:%.*]]
23281 // CHECK23:       omp_if.else:
23282 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23283 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
23284 // CHECK23-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
23285 // CHECK23-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23286 // CHECK23-NEXT:    [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3
23287 // CHECK23-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
23288 // CHECK23:       cond.true10:
23289 // CHECK23-NEXT:    br label [[COND_END12:%.*]]
23290 // CHECK23:       cond.false11:
23291 // CHECK23-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23292 // CHECK23-NEXT:    br label [[COND_END12]]
23293 // CHECK23:       cond.end12:
23294 // CHECK23-NEXT:    [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ]
23295 // CHECK23-NEXT:    store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8
23296 // CHECK23-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
23297 // CHECK23-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
23298 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND14:%.*]]
23299 // CHECK23:       omp.inner.for.cond14:
23300 // CHECK23-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23301 // CHECK23-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23302 // CHECK23-NEXT:    [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
23303 // CHECK23-NEXT:    br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]]
23304 // CHECK23:       omp.inner.for.body16:
23305 // CHECK23-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23306 // CHECK23-NEXT:    [[MUL17:%.*]] = mul i64 [[TMP24]], 400
23307 // CHECK23-NEXT:    [[SUB18:%.*]] = sub i64 2000, [[MUL17]]
23308 // CHECK23-NEXT:    store i64 [[SUB18]], i64* [[IT]], align 8
23309 // CHECK23-NEXT:    [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4
23310 // CHECK23-NEXT:    [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double
23311 // CHECK23-NEXT:    [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00
23312 // CHECK23-NEXT:    [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
23313 // CHECK23-NEXT:    store double [[ADD20]], double* [[A21]], align 4
23314 // CHECK23-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
23315 // CHECK23-NEXT:    [[TMP26:%.*]] = load double, double* [[A22]], align 4
23316 // CHECK23-NEXT:    [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00
23317 // CHECK23-NEXT:    store double [[INC23]], double* [[A22]], align 4
23318 // CHECK23-NEXT:    [[CONV24:%.*]] = fptosi double [[INC23]] to i16
23319 // CHECK23-NEXT:    [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]]
23320 // CHECK23-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]]
23321 // CHECK23-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
23322 // CHECK23-NEXT:    store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2
23323 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE27:%.*]]
23324 // CHECK23:       omp.body.continue27:
23325 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC28:%.*]]
23326 // CHECK23:       omp.inner.for.inc28:
23327 // CHECK23-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
23328 // CHECK23-NEXT:    [[ADD29:%.*]] = add i64 [[TMP28]], 1
23329 // CHECK23-NEXT:    store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8
23330 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP31:![0-9]+]]
23331 // CHECK23:       omp.inner.for.end30:
23332 // CHECK23-NEXT:    br label [[OMP_IF_END]]
23333 // CHECK23:       omp_if.end:
23334 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23335 // CHECK23:       omp.loop.exit:
23336 // CHECK23-NEXT:    [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23337 // CHECK23-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
23338 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
23339 // CHECK23-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23340 // CHECK23-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
23341 // CHECK23-NEXT:    br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23342 // CHECK23:       .omp.final.then:
23343 // CHECK23-NEXT:    store i64 400, i64* [[IT]], align 8
23344 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23345 // CHECK23:       .omp.final.done:
23346 // CHECK23-NEXT:    ret void
23347 //
23348 //
23349 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
23350 // CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23351 // CHECK23-NEXT:  entry:
23352 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23353 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23354 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23355 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23356 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23357 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23358 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23359 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23360 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23361 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23362 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
23363 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
23364 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
23365 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
23366 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23367 // CHECK23-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
23368 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23369 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
23370 // CHECK23-NEXT:    ret void
23371 //
23372 //
23373 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6
23374 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
23375 // CHECK23-NEXT:  entry:
23376 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23377 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23378 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23379 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23380 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23381 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
23382 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i64, align 4
23383 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
23384 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
23385 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
23386 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23387 // CHECK23-NEXT:    [[I:%.*]] = alloca i64, align 8
23388 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23389 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23390 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23391 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23392 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23393 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23394 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23395 // CHECK23-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
23396 // CHECK23-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
23397 // CHECK23-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
23398 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23399 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23400 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
23401 // CHECK23-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
23402 // CHECK23-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23403 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
23404 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23405 // CHECK23:       cond.true:
23406 // CHECK23-NEXT:    br label [[COND_END:%.*]]
23407 // CHECK23:       cond.false:
23408 // CHECK23-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23409 // CHECK23-NEXT:    br label [[COND_END]]
23410 // CHECK23:       cond.end:
23411 // CHECK23-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
23412 // CHECK23-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
23413 // CHECK23-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
23414 // CHECK23-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
23415 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23416 // CHECK23:       omp.inner.for.cond:
23417 // CHECK23-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
23418 // CHECK23-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !33
23419 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
23420 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23421 // CHECK23:       omp.inner.for.body:
23422 // CHECK23-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
23423 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
23424 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
23425 // CHECK23-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !33
23426 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
23427 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
23428 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
23429 // CHECK23-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
23430 // CHECK23-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
23431 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
23432 // CHECK23-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
23433 // CHECK23-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33
23434 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
23435 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
23436 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
23437 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
23438 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23439 // CHECK23:       omp.body.continue:
23440 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23441 // CHECK23:       omp.inner.for.inc:
23442 // CHECK23-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
23443 // CHECK23-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
23444 // CHECK23-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
23445 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
23446 // CHECK23:       omp.inner.for.end:
23447 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23448 // CHECK23:       omp.loop.exit:
23449 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
23450 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23451 // CHECK23-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
23452 // CHECK23-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23453 // CHECK23:       .omp.final.then:
23454 // CHECK23-NEXT:    store i64 11, i64* [[I]], align 8
23455 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23456 // CHECK23:       .omp.final.done:
23457 // CHECK23-NEXT:    ret void
23458 //
23459 //
23460 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
23461 // CHECK24-SAME: () #[[ATTR0:[0-9]+]] {
23462 // CHECK24-NEXT:  entry:
23463 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
23464 // CHECK24-NEXT:    ret void
23465 //
23466 //
23467 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined.
23468 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
23469 // CHECK24-NEXT:  entry:
23470 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23471 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23472 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23473 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23474 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23475 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23476 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23477 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23478 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
23479 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23480 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23481 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23482 // CHECK24-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
23483 // CHECK24-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23484 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23485 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23486 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23487 // CHECK24-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23488 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23489 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
23490 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23491 // CHECK24:       cond.true:
23492 // CHECK24-NEXT:    br label [[COND_END:%.*]]
23493 // CHECK24:       cond.false:
23494 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23495 // CHECK24-NEXT:    br label [[COND_END]]
23496 // CHECK24:       cond.end:
23497 // CHECK24-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23498 // CHECK24-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23499 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23500 // CHECK24-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23501 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23502 // CHECK24:       omp.inner.for.cond:
23503 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23504 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
23505 // CHECK24-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23506 // CHECK24-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23507 // CHECK24:       omp.inner.for.body:
23508 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23509 // CHECK24-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
23510 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
23511 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
23512 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23513 // CHECK24:       omp.body.continue:
23514 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23515 // CHECK24:       omp.inner.for.inc:
23516 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23517 // CHECK24-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
23518 // CHECK24-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23519 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
23520 // CHECK24:       omp.inner.for.end:
23521 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23522 // CHECK24:       omp.loop.exit:
23523 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23524 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23525 // CHECK24-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
23526 // CHECK24-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23527 // CHECK24:       .omp.final.then:
23528 // CHECK24-NEXT:    store i32 33, i32* [[I]], align 4
23529 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23530 // CHECK24:       .omp.final.done:
23531 // CHECK24-NEXT:    ret void
23532 //
23533 //
23534 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108
23535 // CHECK24-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
23536 // CHECK24-NEXT:  entry:
23537 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23538 // CHECK24-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
23539 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23540 // CHECK24-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23541 // CHECK24-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
23542 // CHECK24-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23543 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23544 // CHECK24-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
23545 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23546 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23547 // CHECK24-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
23548 // CHECK24-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23549 // CHECK24-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
23550 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23551 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
23552 // CHECK24-NEXT:    store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
23553 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
23554 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
23555 // CHECK24-NEXT:    store i32 [[TMP4]], i32* [[A_CASTED]], align 4
23556 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
23557 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
23558 // CHECK24-NEXT:    ret void
23559 //
23560 //
23561 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1
23562 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
23563 // CHECK24-NEXT:  entry:
23564 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23565 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23566 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23567 // CHECK24-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
23568 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23569 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
23570 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i64, align 4
23571 // CHECK24-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
23572 // CHECK24-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
23573 // CHECK24-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
23574 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
23575 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
23576 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
23577 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23578 // CHECK24-NEXT:    [[IT:%.*]] = alloca i64, align 8
23579 // CHECK24-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
23580 // CHECK24-NEXT:    [[A3:%.*]] = alloca i32, align 4
23581 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23582 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23583 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23584 // CHECK24-NEXT:    store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
23585 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23586 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23587 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
23588 // CHECK24-NEXT:    store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
23589 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
23590 // CHECK24-NEXT:    store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
23591 // CHECK24-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
23592 // CHECK24-NEXT:    store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
23593 // CHECK24-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
23594 // CHECK24-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
23595 // CHECK24-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
23596 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23597 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23598 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
23599 // CHECK24-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
23600 // CHECK24-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
23601 // CHECK24-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23602 // CHECK24-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
23603 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23604 // CHECK24:       cond.true:
23605 // CHECK24-NEXT:    br label [[COND_END:%.*]]
23606 // CHECK24:       cond.false:
23607 // CHECK24-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
23608 // CHECK24-NEXT:    br label [[COND_END]]
23609 // CHECK24:       cond.end:
23610 // CHECK24-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
23611 // CHECK24-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
23612 // CHECK24-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
23613 // CHECK24-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
23614 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23615 // CHECK24:       omp.inner.for.cond:
23616 // CHECK24-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
23617 // CHECK24-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
23618 // CHECK24-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
23619 // CHECK24-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23620 // CHECK24:       omp.inner.for.body:
23621 // CHECK24-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
23622 // CHECK24-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
23623 // CHECK24-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
23624 // CHECK24-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
23625 // CHECK24-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18
23626 // CHECK24-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
23627 // CHECK24-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
23628 // CHECK24-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
23629 // CHECK24-NEXT:    [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
23630 // CHECK24-NEXT:    [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
23631 // CHECK24-NEXT:    [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
23632 // CHECK24-NEXT:    store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18
23633 // CHECK24-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18
23634 // CHECK24-NEXT:    [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
23635 // CHECK24-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
23636 // CHECK24-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18
23637 // CHECK24-NEXT:    [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
23638 // CHECK24-NEXT:    [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
23639 // CHECK24-NEXT:    [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
23640 // CHECK24-NEXT:    store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18
23641 // CHECK24-NEXT:    [[TMP16:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !18
23642 // CHECK24-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
23643 // CHECK24-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
23644 // CHECK24-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
23645 // CHECK24-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4, !llvm.access.group !18
23646 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23647 // CHECK24:       omp.body.continue:
23648 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23649 // CHECK24:       omp.inner.for.inc:
23650 // CHECK24-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
23651 // CHECK24-NEXT:    [[ADD15:%.*]] = add i64 [[TMP17]], 1
23652 // CHECK24-NEXT:    store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
23653 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
23654 // CHECK24:       omp.inner.for.end:
23655 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23656 // CHECK24:       omp.loop.exit:
23657 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
23658 // CHECK24-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23659 // CHECK24-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
23660 // CHECK24-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23661 // CHECK24:       .omp.final.then:
23662 // CHECK24-NEXT:    store i64 400, i64* [[IT]], align 8
23663 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23664 // CHECK24:       .omp.final.done:
23665 // CHECK24-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23666 // CHECK24-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
23667 // CHECK24-NEXT:    br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
23668 // CHECK24:       .omp.linear.pu:
23669 // CHECK24-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
23670 // CHECK24-NEXT:    [[CONV16:%.*]] = sext i32 [[TMP22]] to i64
23671 // CHECK24-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
23672 // CHECK24-NEXT:    [[MUL17:%.*]] = mul i64 4, [[TMP23]]
23673 // CHECK24-NEXT:    [[ADD18:%.*]] = add i64 [[CONV16]], [[MUL17]]
23674 // CHECK24-NEXT:    [[CONV19:%.*]] = trunc i64 [[ADD18]] to i32
23675 // CHECK24-NEXT:    store i32 [[CONV19]], i32* [[LIN_ADDR]], align 4
23676 // CHECK24-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
23677 // CHECK24-NEXT:    [[CONV20:%.*]] = sext i32 [[TMP24]] to i64
23678 // CHECK24-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
23679 // CHECK24-NEXT:    [[MUL21:%.*]] = mul i64 4, [[TMP25]]
23680 // CHECK24-NEXT:    [[ADD22:%.*]] = add i64 [[CONV20]], [[MUL21]]
23681 // CHECK24-NEXT:    [[CONV23:%.*]] = trunc i64 [[ADD22]] to i32
23682 // CHECK24-NEXT:    store i32 [[CONV23]], i32* [[A_ADDR]], align 4
23683 // CHECK24-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
23684 // CHECK24:       .omp.linear.pu.done:
23685 // CHECK24-NEXT:    ret void
23686 //
23687 //
23688 // CHECK24-LABEL: define {{[^@]+}}@_Z7get_valv
23689 // CHECK24-SAME: () #[[ATTR3:[0-9]+]] {
23690 // CHECK24-NEXT:  entry:
23691 // CHECK24-NEXT:    ret i64 0
23692 //
23693 //
23694 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116
23695 // CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
23696 // CHECK24-NEXT:  entry:
23697 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23698 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23699 // CHECK24-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23700 // CHECK24-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23701 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23702 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23703 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23704 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
23705 // CHECK24-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
23706 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
23707 // CHECK24-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
23708 // CHECK24-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23709 // CHECK24-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
23710 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23711 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
23712 // CHECK24-NEXT:    ret void
23713 //
23714 //
23715 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2
23716 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] {
23717 // CHECK24-NEXT:  entry:
23718 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23719 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23720 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23721 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23722 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23723 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i16, align 2
23724 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23725 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23726 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23727 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23728 // CHECK24-NEXT:    [[IT:%.*]] = alloca i16, align 2
23729 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23730 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23731 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23732 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23733 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23734 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23735 // CHECK24-NEXT:    store i32 3, i32* [[DOTOMP_UB]], align 4
23736 // CHECK24-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23737 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23738 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23739 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23740 // CHECK24-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23741 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23742 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
23743 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23744 // CHECK24:       cond.true:
23745 // CHECK24-NEXT:    br label [[COND_END:%.*]]
23746 // CHECK24:       cond.false:
23747 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23748 // CHECK24-NEXT:    br label [[COND_END]]
23749 // CHECK24:       cond.end:
23750 // CHECK24-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23751 // CHECK24-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23752 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23753 // CHECK24-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23754 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23755 // CHECK24:       omp.inner.for.cond:
23756 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
23757 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
23758 // CHECK24-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23759 // CHECK24-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23760 // CHECK24:       omp.inner.for.body:
23761 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
23762 // CHECK24-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
23763 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
23764 // CHECK24-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
23765 // CHECK24-NEXT:    store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21
23766 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21
23767 // CHECK24-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
23768 // CHECK24-NEXT:    store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21
23769 // CHECK24-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !21
23770 // CHECK24-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
23771 // CHECK24-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
23772 // CHECK24-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
23773 // CHECK24-NEXT:    store i16 [[CONV6]], i16* [[CONV]], align 4, !llvm.access.group !21
23774 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23775 // CHECK24:       omp.body.continue:
23776 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23777 // CHECK24:       omp.inner.for.inc:
23778 // CHECK24-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
23779 // CHECK24-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
23780 // CHECK24-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
23781 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
23782 // CHECK24:       omp.inner.for.end:
23783 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23784 // CHECK24:       omp.loop.exit:
23785 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23786 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23787 // CHECK24-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
23788 // CHECK24-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23789 // CHECK24:       .omp.final.then:
23790 // CHECK24-NEXT:    store i16 22, i16* [[IT]], align 2
23791 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23792 // CHECK24:       .omp.final.done:
23793 // CHECK24-NEXT:    ret void
23794 //
23795 //
23796 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140
23797 // CHECK24-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
23798 // CHECK24-NEXT:  entry:
23799 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23800 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
23801 // CHECK24-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23802 // CHECK24-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
23803 // CHECK24-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
23804 // CHECK24-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23805 // CHECK24-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
23806 // CHECK24-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
23807 // CHECK24-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
23808 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23809 // CHECK24-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23810 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
23811 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23812 // CHECK24-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
23813 // CHECK24-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23814 // CHECK24-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
23815 // CHECK24-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
23816 // CHECK24-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23817 // CHECK24-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
23818 // CHECK24-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
23819 // CHECK24-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
23820 // CHECK24-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23821 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
23822 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23823 // CHECK24-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
23824 // CHECK24-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
23825 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23826 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
23827 // CHECK24-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
23828 // CHECK24-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
23829 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
23830 // CHECK24-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
23831 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
23832 // CHECK24-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23833 // CHECK24-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
23834 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
23835 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
23836 // CHECK24-NEXT:    ret void
23837 //
23838 //
23839 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3
23840 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
23841 // CHECK24-NEXT:  entry:
23842 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23843 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23844 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23845 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
23846 // CHECK24-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23847 // CHECK24-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
23848 // CHECK24-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
23849 // CHECK24-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23850 // CHECK24-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
23851 // CHECK24-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
23852 // CHECK24-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
23853 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23854 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23855 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i8, align 1
23856 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23857 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23858 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23859 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23860 // CHECK24-NEXT:    [[IT:%.*]] = alloca i8, align 1
23861 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23862 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23863 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23864 // CHECK24-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
23865 // CHECK24-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23866 // CHECK24-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
23867 // CHECK24-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
23868 // CHECK24-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23869 // CHECK24-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
23870 // CHECK24-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
23871 // CHECK24-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
23872 // CHECK24-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23873 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
23874 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23875 // CHECK24-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
23876 // CHECK24-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
23877 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23878 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
23879 // CHECK24-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
23880 // CHECK24-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
23881 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23882 // CHECK24-NEXT:    store i32 25, i32* [[DOTOMP_UB]], align 4
23883 // CHECK24-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23884 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23885 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23886 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23887 // CHECK24-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
23888 // CHECK24-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
23889 // CHECK24-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
23890 // CHECK24:       omp.dispatch.cond:
23891 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23892 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
23893 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23894 // CHECK24:       cond.true:
23895 // CHECK24-NEXT:    br label [[COND_END:%.*]]
23896 // CHECK24:       cond.false:
23897 // CHECK24-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23898 // CHECK24-NEXT:    br label [[COND_END]]
23899 // CHECK24:       cond.end:
23900 // CHECK24-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
23901 // CHECK24-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23902 // CHECK24-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23903 // CHECK24-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
23904 // CHECK24-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23905 // CHECK24-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23906 // CHECK24-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
23907 // CHECK24-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
23908 // CHECK24:       omp.dispatch.body:
23909 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23910 // CHECK24:       omp.inner.for.cond:
23911 // CHECK24-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23912 // CHECK24-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
23913 // CHECK24-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
23914 // CHECK24-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23915 // CHECK24:       omp.inner.for.body:
23916 // CHECK24-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23917 // CHECK24-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
23918 // CHECK24-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
23919 // CHECK24-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
23920 // CHECK24-NEXT:    store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24
23921 // CHECK24-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24
23922 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
23923 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24
23924 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
23925 // CHECK24-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
23926 // CHECK24-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
23927 // CHECK24-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
23928 // CHECK24-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
23929 // CHECK24-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
23930 // CHECK24-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
23931 // CHECK24-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
23932 // CHECK24-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
23933 // CHECK24-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
23934 // CHECK24-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
23935 // CHECK24-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
23936 // CHECK24-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
23937 // CHECK24-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
23938 // CHECK24-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
23939 // CHECK24-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
23940 // CHECK24-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
23941 // CHECK24-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
23942 // CHECK24-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
23943 // CHECK24-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
23944 // CHECK24-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
23945 // CHECK24-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
23946 // CHECK24-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
23947 // CHECK24-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
23948 // CHECK24-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24
23949 // CHECK24-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
23950 // CHECK24-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24
23951 // CHECK24-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
23952 // CHECK24-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24
23953 // CHECK24-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
23954 // CHECK24-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
23955 // CHECK24-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
23956 // CHECK24-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24
23957 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23958 // CHECK24:       omp.body.continue:
23959 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23960 // CHECK24:       omp.inner.for.inc:
23961 // CHECK24-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23962 // CHECK24-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
23963 // CHECK24-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23964 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
23965 // CHECK24:       omp.inner.for.end:
23966 // CHECK24-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
23967 // CHECK24:       omp.dispatch.inc:
23968 // CHECK24-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23969 // CHECK24-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
23970 // CHECK24-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
23971 // CHECK24-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
23972 // CHECK24-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23973 // CHECK24-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
23974 // CHECK24-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
23975 // CHECK24-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
23976 // CHECK24-NEXT:    br label [[OMP_DISPATCH_COND]]
23977 // CHECK24:       omp.dispatch.end:
23978 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
23979 // CHECK24-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23980 // CHECK24-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
23981 // CHECK24-NEXT:    br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23982 // CHECK24:       .omp.final.then:
23983 // CHECK24-NEXT:    store i8 96, i8* [[IT]], align 1
23984 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23985 // CHECK24:       .omp.final.done:
23986 // CHECK24-NEXT:    ret void
23987 //
23988 //
23989 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195
23990 // CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23991 // CHECK24-NEXT:  entry:
23992 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23993 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23994 // CHECK24-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
23995 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23996 // CHECK24-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23997 // CHECK24-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23998 // CHECK24-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
23999 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24000 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24001 // CHECK24-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
24002 // CHECK24-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24003 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24004 // CHECK24-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
24005 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24006 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
24007 // CHECK24-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
24008 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
24009 // CHECK24-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
24010 // CHECK24-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24011 // CHECK24-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
24012 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24013 // CHECK24-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
24014 // CHECK24-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
24015 // CHECK24-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
24016 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
24017 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
24018 // CHECK24-NEXT:    ret void
24019 //
24020 //
24021 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4
24022 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
24023 // CHECK24-NEXT:  entry:
24024 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24025 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24026 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24027 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24028 // CHECK24-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
24029 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24030 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24031 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24032 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24033 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24034 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24035 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24036 // CHECK24-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
24037 // CHECK24-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24038 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24039 // CHECK24-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
24040 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24041 // CHECK24-NEXT:    ret void
24042 //
24043 //
24044 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214
24045 // CHECK24-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
24046 // CHECK24-NEXT:  entry:
24047 // CHECK24-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
24048 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
24049 // CHECK24-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
24050 // CHECK24-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
24051 // CHECK24-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
24052 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
24053 // CHECK24-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
24054 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
24055 // CHECK24-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
24056 // CHECK24-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
24057 // CHECK24-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
24058 // CHECK24-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
24059 // CHECK24-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
24060 // CHECK24-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
24061 // CHECK24-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
24062 // CHECK24-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
24063 // CHECK24-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
24064 // CHECK24-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24065 // CHECK24-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
24066 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
24067 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
24068 // CHECK24-NEXT:    [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4
24069 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
24070 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4
24071 // CHECK24-NEXT:    store i32 [[TMP5]], i32* [[B_CASTED]], align 4
24072 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
24073 // CHECK24-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV]], align 4
24074 // CHECK24-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
24075 // CHECK24-NEXT:    [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
24076 // CHECK24-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
24077 // CHECK24-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
24078 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
24079 // CHECK24-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV]], align 4
24080 // CHECK24-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1
24081 // CHECK24-NEXT:    br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
24082 // CHECK24:       omp_if.then:
24083 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]])
24084 // CHECK24-NEXT:    br label [[OMP_IF_END:%.*]]
24085 // CHECK24:       omp_if.else:
24086 // CHECK24-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
24087 // CHECK24-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
24088 // CHECK24-NEXT:    call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]]
24089 // CHECK24-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
24090 // CHECK24-NEXT:    br label [[OMP_IF_END]]
24091 // CHECK24:       omp_if.end:
24092 // CHECK24-NEXT:    ret void
24093 //
24094 //
24095 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..5
24096 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
24097 // CHECK24-NEXT:  entry:
24098 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24099 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24100 // CHECK24-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
24101 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
24102 // CHECK24-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
24103 // CHECK24-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
24104 // CHECK24-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
24105 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
24106 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
24107 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i64, align 4
24108 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
24109 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
24110 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
24111 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24112 // CHECK24-NEXT:    [[IT:%.*]] = alloca i64, align 8
24113 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24114 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24115 // CHECK24-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
24116 // CHECK24-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
24117 // CHECK24-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
24118 // CHECK24-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
24119 // CHECK24-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
24120 // CHECK24-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24121 // CHECK24-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
24122 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
24123 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
24124 // CHECK24-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
24125 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
24126 // CHECK24-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
24127 // CHECK24-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
24128 // CHECK24-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
24129 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24130 // CHECK24-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
24131 // CHECK24-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
24132 // CHECK24-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
24133 // CHECK24:       omp_if.then:
24134 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24135 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
24136 // CHECK24-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
24137 // CHECK24-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
24138 // CHECK24-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3
24139 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24140 // CHECK24:       cond.true:
24141 // CHECK24-NEXT:    br label [[COND_END:%.*]]
24142 // CHECK24:       cond.false:
24143 // CHECK24-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
24144 // CHECK24-NEXT:    br label [[COND_END]]
24145 // CHECK24:       cond.end:
24146 // CHECK24-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
24147 // CHECK24-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
24148 // CHECK24-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
24149 // CHECK24-NEXT:    store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8
24150 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24151 // CHECK24:       omp.inner.for.cond:
24152 // CHECK24-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
24153 // CHECK24-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27
24154 // CHECK24-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
24155 // CHECK24-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24156 // CHECK24:       omp.inner.for.body:
24157 // CHECK24-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
24158 // CHECK24-NEXT:    [[MUL:%.*]] = mul i64 [[TMP12]], 400
24159 // CHECK24-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
24160 // CHECK24-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27
24161 // CHECK24-NEXT:    [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27
24162 // CHECK24-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
24163 // CHECK24-NEXT:    [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
24164 // CHECK24-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
24165 // CHECK24-NEXT:    store double [[ADD]], double* [[A]], align 4, !nontemporal !28, !llvm.access.group !27
24166 // CHECK24-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
24167 // CHECK24-NEXT:    [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27
24168 // CHECK24-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
24169 // CHECK24-NEXT:    store double [[INC]], double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27
24170 // CHECK24-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
24171 // CHECK24-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
24172 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
24173 // CHECK24-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
24174 // CHECK24-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !27
24175 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24176 // CHECK24:       omp.body.continue:
24177 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24178 // CHECK24:       omp.inner.for.inc:
24179 // CHECK24-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
24180 // CHECK24-NEXT:    [[ADD8:%.*]] = add i64 [[TMP16]], 1
24181 // CHECK24-NEXT:    store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27
24182 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
24183 // CHECK24:       omp.inner.for.end:
24184 // CHECK24-NEXT:    br label [[OMP_IF_END:%.*]]
24185 // CHECK24:       omp_if.else:
24186 // CHECK24-NEXT:    [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24187 // CHECK24-NEXT:    [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
24188 // CHECK24-NEXT:    call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
24189 // CHECK24-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
24190 // CHECK24-NEXT:    [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3
24191 // CHECK24-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
24192 // CHECK24:       cond.true10:
24193 // CHECK24-NEXT:    br label [[COND_END12:%.*]]
24194 // CHECK24:       cond.false11:
24195 // CHECK24-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
24196 // CHECK24-NEXT:    br label [[COND_END12]]
24197 // CHECK24:       cond.end12:
24198 // CHECK24-NEXT:    [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ]
24199 // CHECK24-NEXT:    store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8
24200 // CHECK24-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
24201 // CHECK24-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8
24202 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND14:%.*]]
24203 // CHECK24:       omp.inner.for.cond14:
24204 // CHECK24-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
24205 // CHECK24-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
24206 // CHECK24-NEXT:    [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
24207 // CHECK24-NEXT:    br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]]
24208 // CHECK24:       omp.inner.for.body16:
24209 // CHECK24-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
24210 // CHECK24-NEXT:    [[MUL17:%.*]] = mul i64 [[TMP24]], 400
24211 // CHECK24-NEXT:    [[SUB18:%.*]] = sub i64 2000, [[MUL17]]
24212 // CHECK24-NEXT:    store i64 [[SUB18]], i64* [[IT]], align 8
24213 // CHECK24-NEXT:    [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4
24214 // CHECK24-NEXT:    [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double
24215 // CHECK24-NEXT:    [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00
24216 // CHECK24-NEXT:    [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
24217 // CHECK24-NEXT:    store double [[ADD20]], double* [[A21]], align 4
24218 // CHECK24-NEXT:    [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
24219 // CHECK24-NEXT:    [[TMP26:%.*]] = load double, double* [[A22]], align 4
24220 // CHECK24-NEXT:    [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00
24221 // CHECK24-NEXT:    store double [[INC23]], double* [[A22]], align 4
24222 // CHECK24-NEXT:    [[CONV24:%.*]] = fptosi double [[INC23]] to i16
24223 // CHECK24-NEXT:    [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]]
24224 // CHECK24-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]]
24225 // CHECK24-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
24226 // CHECK24-NEXT:    store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2
24227 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE27:%.*]]
24228 // CHECK24:       omp.body.continue27:
24229 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC28:%.*]]
24230 // CHECK24:       omp.inner.for.inc28:
24231 // CHECK24-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
24232 // CHECK24-NEXT:    [[ADD29:%.*]] = add i64 [[TMP28]], 1
24233 // CHECK24-NEXT:    store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8
24234 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP31:![0-9]+]]
24235 // CHECK24:       omp.inner.for.end30:
24236 // CHECK24-NEXT:    br label [[OMP_IF_END]]
24237 // CHECK24:       omp_if.end:
24238 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24239 // CHECK24:       omp.loop.exit:
24240 // CHECK24-NEXT:    [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24241 // CHECK24-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4
24242 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]])
24243 // CHECK24-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
24244 // CHECK24-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
24245 // CHECK24-NEXT:    br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
24246 // CHECK24:       .omp.final.then:
24247 // CHECK24-NEXT:    store i64 400, i64* [[IT]], align 8
24248 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
24249 // CHECK24:       .omp.final.done:
24250 // CHECK24-NEXT:    ret void
24251 //
24252 //
24253 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178
24254 // CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
24255 // CHECK24-NEXT:  entry:
24256 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24257 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24258 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24259 // CHECK24-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
24260 // CHECK24-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24261 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24262 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24263 // CHECK24-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24264 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24265 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24266 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
24267 // CHECK24-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
24268 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
24269 // CHECK24-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
24270 // CHECK24-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24271 // CHECK24-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
24272 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24273 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
24274 // CHECK24-NEXT:    ret void
24275 //
24276 //
24277 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6
24278 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
24279 // CHECK24-NEXT:  entry:
24280 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24281 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24282 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24283 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24284 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24285 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
24286 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i64, align 4
24287 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
24288 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
24289 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
24290 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24291 // CHECK24-NEXT:    [[I:%.*]] = alloca i64, align 8
24292 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24293 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24294 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24295 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24296 // CHECK24-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24297 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24298 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24299 // CHECK24-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
24300 // CHECK24-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
24301 // CHECK24-NEXT:    store i64 1, i64* [[DOTOMP_STRIDE]], align 8
24302 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24303 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24304 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
24305 // CHECK24-NEXT:    call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
24306 // CHECK24-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
24307 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
24308 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24309 // CHECK24:       cond.true:
24310 // CHECK24-NEXT:    br label [[COND_END:%.*]]
24311 // CHECK24:       cond.false:
24312 // CHECK24-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
24313 // CHECK24-NEXT:    br label [[COND_END]]
24314 // CHECK24:       cond.end:
24315 // CHECK24-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
24316 // CHECK24-NEXT:    store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
24317 // CHECK24-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
24318 // CHECK24-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
24319 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24320 // CHECK24:       omp.inner.for.cond:
24321 // CHECK24-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
24322 // CHECK24-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !33
24323 // CHECK24-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
24324 // CHECK24-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24325 // CHECK24:       omp.inner.for.body:
24326 // CHECK24-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
24327 // CHECK24-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
24328 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
24329 // CHECK24-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !33
24330 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
24331 // CHECK24-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
24332 // CHECK24-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
24333 // CHECK24-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4, !llvm.access.group !33
24334 // CHECK24-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
24335 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
24336 // CHECK24-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
24337 // CHECK24-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4, !llvm.access.group !33
24338 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
24339 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
24340 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
24341 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
24342 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24343 // CHECK24:       omp.body.continue:
24344 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24345 // CHECK24:       omp.inner.for.inc:
24346 // CHECK24-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
24347 // CHECK24-NEXT:    [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
24348 // CHECK24-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33
24349 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
24350 // CHECK24:       omp.inner.for.end:
24351 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24352 // CHECK24:       omp.loop.exit:
24353 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
24354 // CHECK24-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
24355 // CHECK24-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
24356 // CHECK24-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
24357 // CHECK24:       .omp.final.then:
24358 // CHECK24-NEXT:    store i64 11, i64* [[I]], align 8
24359 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
24360 // CHECK24:       .omp.final.done:
24361 // CHECK24-NEXT:    ret void
24362 //
24363 //
24364 // CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv
24365 // CHECK25-SAME: () #[[ATTR0:[0-9]+]] {
24366 // CHECK25-NEXT:  entry:
24367 // CHECK25-NEXT:    ret i64 0
24368 //
24369 //
24370 // CHECK25-LABEL: define {{[^@]+}}@_Z3fooi
24371 // CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24372 // CHECK25-NEXT:  entry:
24373 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24374 // CHECK25-NEXT:    [[A:%.*]] = alloca i32, align 4
24375 // CHECK25-NEXT:    [[AA:%.*]] = alloca i16, align 2
24376 // CHECK25-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
24377 // CHECK25-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
24378 // CHECK25-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
24379 // CHECK25-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
24380 // CHECK25-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
24381 // CHECK25-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
24382 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24383 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24384 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24385 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24386 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
24387 // CHECK25-NEXT:    [[K:%.*]] = alloca i64, align 8
24388 // CHECK25-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
24389 // CHECK25-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
24390 // CHECK25-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
24391 // CHECK25-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
24392 // CHECK25-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
24393 // CHECK25-NEXT:    [[I7:%.*]] = alloca i32, align 4
24394 // CHECK25-NEXT:    [[K8:%.*]] = alloca i64, align 8
24395 // CHECK25-NEXT:    [[LIN:%.*]] = alloca i32, align 4
24396 // CHECK25-NEXT:    [[_TMP21:%.*]] = alloca i64, align 8
24397 // CHECK25-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
24398 // CHECK25-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
24399 // CHECK25-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
24400 // CHECK25-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
24401 // CHECK25-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
24402 // CHECK25-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
24403 // CHECK25-NEXT:    [[IT:%.*]] = alloca i64, align 8
24404 // CHECK25-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
24405 // CHECK25-NEXT:    [[A29:%.*]] = alloca i32, align 4
24406 // CHECK25-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
24407 // CHECK25-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
24408 // CHECK25-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
24409 // CHECK25-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
24410 // CHECK25-NEXT:    [[IT62:%.*]] = alloca i16, align 2
24411 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
24412 // CHECK25-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
24413 // CHECK25-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
24414 // CHECK25-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
24415 // CHECK25-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
24416 // CHECK25-NEXT:    [[IT81:%.*]] = alloca i8, align 1
24417 // CHECK25-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24418 // CHECK25-NEXT:    store i32 0, i32* [[A]], align 4
24419 // CHECK25-NEXT:    store i16 0, i16* [[AA]], align 2
24420 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24421 // CHECK25-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
24422 // CHECK25-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
24423 // CHECK25-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
24424 // CHECK25-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
24425 // CHECK25-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
24426 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
24427 // CHECK25-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
24428 // CHECK25-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
24429 // CHECK25-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
24430 // CHECK25-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
24431 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24432 // CHECK25-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
24433 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24434 // CHECK25-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
24435 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24436 // CHECK25:       omp.inner.for.cond:
24437 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
24438 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
24439 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
24440 // CHECK25-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24441 // CHECK25:       omp.inner.for.body:
24442 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
24443 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
24444 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
24445 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
24446 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24447 // CHECK25:       omp.body.continue:
24448 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24449 // CHECK25:       omp.inner.for.inc:
24450 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
24451 // CHECK25-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
24452 // CHECK25-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
24453 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
24454 // CHECK25:       omp.inner.for.end:
24455 // CHECK25-NEXT:    store i32 33, i32* [[I]], align 4
24456 // CHECK25-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
24457 // CHECK25-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
24458 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
24459 // CHECK25-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
24460 // CHECK25-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
24461 // CHECK25-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
24462 // CHECK25-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K]], align 8
24463 // CHECK25-NEXT:    store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
24464 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
24465 // CHECK25:       omp.inner.for.cond9:
24466 // CHECK25-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
24467 // CHECK25-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
24468 // CHECK25-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
24469 // CHECK25-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
24470 // CHECK25:       omp.inner.for.body11:
24471 // CHECK25-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
24472 // CHECK25-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
24473 // CHECK25-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
24474 // CHECK25-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
24475 // CHECK25-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
24476 // CHECK25-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
24477 // CHECK25-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
24478 // CHECK25-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
24479 // CHECK25-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
24480 // CHECK25-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
24481 // CHECK25-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
24482 // CHECK25-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
24483 // CHECK25-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
24484 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
24485 // CHECK25:       omp.body.continue16:
24486 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
24487 // CHECK25:       omp.inner.for.inc17:
24488 // CHECK25-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
24489 // CHECK25-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
24490 // CHECK25-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
24491 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
24492 // CHECK25:       omp.inner.for.end19:
24493 // CHECK25-NEXT:    store i32 1, i32* [[I7]], align 4
24494 // CHECK25-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
24495 // CHECK25-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
24496 // CHECK25-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
24497 // CHECK25-NEXT:    store i32 12, i32* [[LIN]], align 4
24498 // CHECK25-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
24499 // CHECK25-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
24500 // CHECK25-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
24501 // CHECK25-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
24502 // CHECK25-NEXT:    [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
24503 // CHECK25-NEXT:    store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
24504 // CHECK25-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A]], align 4
24505 // CHECK25-NEXT:    store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
24506 // CHECK25-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
24507 // CHECK25-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
24508 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
24509 // CHECK25:       omp.inner.for.cond30:
24510 // CHECK25-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
24511 // CHECK25-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
24512 // CHECK25-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
24513 // CHECK25-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
24514 // CHECK25:       omp.inner.for.body32:
24515 // CHECK25-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
24516 // CHECK25-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP26]], 400
24517 // CHECK25-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
24518 // CHECK25-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
24519 // CHECK25-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
24520 // CHECK25-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
24521 // CHECK25-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
24522 // CHECK25-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
24523 // CHECK25-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
24524 // CHECK25-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
24525 // CHECK25-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
24526 // CHECK25-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
24527 // CHECK25-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
24528 // CHECK25-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
24529 // CHECK25-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
24530 // CHECK25-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
24531 // CHECK25-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
24532 // CHECK25-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
24533 // CHECK25-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
24534 // CHECK25-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
24535 // CHECK25-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
24536 // CHECK25-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
24537 // CHECK25-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
24538 // CHECK25-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
24539 // CHECK25-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
24540 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
24541 // CHECK25:       omp.body.continue46:
24542 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
24543 // CHECK25:       omp.inner.for.inc47:
24544 // CHECK25-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
24545 // CHECK25-NEXT:    [[ADD48:%.*]] = add i64 [[TMP34]], 1
24546 // CHECK25-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
24547 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
24548 // CHECK25:       omp.inner.for.end49:
24549 // CHECK25-NEXT:    store i64 400, i64* [[IT]], align 8
24550 // CHECK25-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
24551 // CHECK25-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
24552 // CHECK25-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
24553 // CHECK25-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP36]]
24554 // CHECK25-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
24555 // CHECK25-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
24556 // CHECK25-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
24557 // CHECK25-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
24558 // CHECK25-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
24559 // CHECK25-NEXT:    [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
24560 // CHECK25-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP38]]
24561 // CHECK25-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
24562 // CHECK25-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
24563 // CHECK25-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
24564 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
24565 // CHECK25-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
24566 // CHECK25-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
24567 // CHECK25-NEXT:    store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
24568 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
24569 // CHECK25:       omp.inner.for.cond63:
24570 // CHECK25-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
24571 // CHECK25-NEXT:    [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
24572 // CHECK25-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
24573 // CHECK25-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
24574 // CHECK25:       omp.inner.for.body65:
24575 // CHECK25-NEXT:    [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
24576 // CHECK25-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
24577 // CHECK25-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
24578 // CHECK25-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
24579 // CHECK25-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
24580 // CHECK25-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
24581 // CHECK25-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
24582 // CHECK25-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
24583 // CHECK25-NEXT:    [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
24584 // CHECK25-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
24585 // CHECK25-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
24586 // CHECK25-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
24587 // CHECK25-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
24588 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
24589 // CHECK25:       omp.body.continue73:
24590 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
24591 // CHECK25:       omp.inner.for.inc74:
24592 // CHECK25-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
24593 // CHECK25-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
24594 // CHECK25-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
24595 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
24596 // CHECK25:       omp.inner.for.end76:
24597 // CHECK25-NEXT:    store i16 22, i16* [[IT62]], align 2
24598 // CHECK25-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
24599 // CHECK25-NEXT:    store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
24600 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
24601 // CHECK25-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
24602 // CHECK25-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
24603 // CHECK25-NEXT:    store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
24604 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
24605 // CHECK25:       omp.inner.for.cond82:
24606 // CHECK25-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
24607 // CHECK25-NEXT:    [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
24608 // CHECK25-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
24609 // CHECK25-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
24610 // CHECK25:       omp.inner.for.body84:
24611 // CHECK25-NEXT:    [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
24612 // CHECK25-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
24613 // CHECK25-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
24614 // CHECK25-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
24615 // CHECK25-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
24616 // CHECK25-NEXT:    [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
24617 // CHECK25-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
24618 // CHECK25-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
24619 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
24620 // CHECK25-NEXT:    [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
24621 // CHECK25-NEXT:    [[CONV89:%.*]] = fpext float [[TMP52]] to double
24622 // CHECK25-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
24623 // CHECK25-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
24624 // CHECK25-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
24625 // CHECK25-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
24626 // CHECK25-NEXT:    [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
24627 // CHECK25-NEXT:    [[CONV93:%.*]] = fpext float [[TMP53]] to double
24628 // CHECK25-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
24629 // CHECK25-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
24630 // CHECK25-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
24631 // CHECK25-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
24632 // CHECK25-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
24633 // CHECK25-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
24634 // CHECK25-NEXT:    [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
24635 // CHECK25-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
24636 // CHECK25-NEXT:    [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
24637 // CHECK25-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
24638 // CHECK25-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
24639 // CHECK25-NEXT:    [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
24640 // CHECK25-NEXT:    [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
24641 // CHECK25-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
24642 // CHECK25-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
24643 // CHECK25-NEXT:    [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
24644 // CHECK25-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
24645 // CHECK25-NEXT:    store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
24646 // CHECK25-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
24647 // CHECK25-NEXT:    [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
24648 // CHECK25-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
24649 // CHECK25-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
24650 // CHECK25-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
24651 // CHECK25-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
24652 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
24653 // CHECK25:       omp.body.continue106:
24654 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
24655 // CHECK25:       omp.inner.for.inc107:
24656 // CHECK25-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
24657 // CHECK25-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
24658 // CHECK25-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
24659 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
24660 // CHECK25:       omp.inner.for.end109:
24661 // CHECK25-NEXT:    store i8 96, i8* [[IT81]], align 1
24662 // CHECK25-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
24663 // CHECK25-NEXT:    [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
24664 // CHECK25-NEXT:    call void @llvm.stackrestore(i8* [[TMP61]])
24665 // CHECK25-NEXT:    ret i32 [[TMP60]]
24666 //
24667 //
24668 // CHECK25-LABEL: define {{[^@]+}}@_Z3bari
24669 // CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24670 // CHECK25-NEXT:  entry:
24671 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24672 // CHECK25-NEXT:    [[A:%.*]] = alloca i32, align 4
24673 // CHECK25-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
24674 // CHECK25-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24675 // CHECK25-NEXT:    store i32 0, i32* [[A]], align 4
24676 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24677 // CHECK25-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
24678 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
24679 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
24680 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
24681 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
24682 // CHECK25-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
24683 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
24684 // CHECK25-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
24685 // CHECK25-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
24686 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
24687 // CHECK25-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
24688 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
24689 // CHECK25-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
24690 // CHECK25-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
24691 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
24692 // CHECK25-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
24693 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
24694 // CHECK25-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
24695 // CHECK25-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
24696 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
24697 // CHECK25-NEXT:    ret i32 [[TMP8]]
24698 //
24699 //
24700 // CHECK25-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
24701 // CHECK25-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
24702 // CHECK25-NEXT:  entry:
24703 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
24704 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24705 // CHECK25-NEXT:    [[B:%.*]] = alloca i32, align 4
24706 // CHECK25-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
24707 // CHECK25-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
24708 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i64, align 8
24709 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
24710 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
24711 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
24712 // CHECK25-NEXT:    [[IT:%.*]] = alloca i64, align 8
24713 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
24714 // CHECK25-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24715 // CHECK25-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
24716 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24717 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
24718 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
24719 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
24720 // CHECK25-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
24721 // CHECK25-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
24722 // CHECK25-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
24723 // CHECK25-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
24724 // CHECK25-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
24725 // CHECK25-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
24726 // CHECK25-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
24727 // CHECK25-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
24728 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
24729 // CHECK25-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
24730 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24731 // CHECK25:       omp.inner.for.cond:
24732 // CHECK25-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
24733 // CHECK25-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
24734 // CHECK25-NEXT:    [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]]
24735 // CHECK25-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24736 // CHECK25:       omp.inner.for.body:
24737 // CHECK25-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
24738 // CHECK25-NEXT:    [[MUL:%.*]] = mul i64 [[TMP8]], 400
24739 // CHECK25-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
24740 // CHECK25-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
24741 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
24742 // CHECK25-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
24743 // CHECK25-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
24744 // CHECK25-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
24745 // CHECK25-NEXT:    store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18
24746 // CHECK25-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
24747 // CHECK25-NEXT:    [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18
24748 // CHECK25-NEXT:    [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
24749 // CHECK25-NEXT:    store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18
24750 // CHECK25-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
24751 // CHECK25-NEXT:    [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
24752 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
24753 // CHECK25-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
24754 // CHECK25-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18
24755 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24756 // CHECK25:       omp.body.continue:
24757 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24758 // CHECK25:       omp.inner.for.inc:
24759 // CHECK25-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
24760 // CHECK25-NEXT:    [[ADD6:%.*]] = add i64 [[TMP12]], 1
24761 // CHECK25-NEXT:    store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
24762 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
24763 // CHECK25:       omp.inner.for.end:
24764 // CHECK25-NEXT:    store i64 400, i64* [[IT]], align 8
24765 // CHECK25-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
24766 // CHECK25-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
24767 // CHECK25-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
24768 // CHECK25-NEXT:    [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
24769 // CHECK25-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP14]] to i32
24770 // CHECK25-NEXT:    [[TMP15:%.*]] = load i32, i32* [[B]], align 4
24771 // CHECK25-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]]
24772 // CHECK25-NEXT:    [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
24773 // CHECK25-NEXT:    call void @llvm.stackrestore(i8* [[TMP16]])
24774 // CHECK25-NEXT:    ret i32 [[ADD10]]
24775 //
24776 //
24777 // CHECK25-LABEL: define {{[^@]+}}@_ZL7fstatici
24778 // CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24779 // CHECK25-NEXT:  entry:
24780 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24781 // CHECK25-NEXT:    [[A:%.*]] = alloca i32, align 4
24782 // CHECK25-NEXT:    [[AA:%.*]] = alloca i16, align 2
24783 // CHECK25-NEXT:    [[AAA:%.*]] = alloca i8, align 1
24784 // CHECK25-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
24785 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24786 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24787 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24788 // CHECK25-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24789 // CHECK25-NEXT:    store i32 0, i32* [[A]], align 4
24790 // CHECK25-NEXT:    store i16 0, i16* [[AA]], align 2
24791 // CHECK25-NEXT:    store i8 0, i8* [[AAA]], align 1
24792 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24793 // CHECK25-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
24794 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
24795 // CHECK25-NEXT:    ret i32 [[TMP0]]
24796 //
24797 //
24798 // CHECK25-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
24799 // CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
24800 // CHECK25-NEXT:  entry:
24801 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24802 // CHECK25-NEXT:    [[A:%.*]] = alloca i32, align 4
24803 // CHECK25-NEXT:    [[AA:%.*]] = alloca i16, align 2
24804 // CHECK25-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
24805 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i64, align 8
24806 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
24807 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
24808 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
24809 // CHECK25-NEXT:    [[I:%.*]] = alloca i64, align 8
24810 // CHECK25-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24811 // CHECK25-NEXT:    store i32 0, i32* [[A]], align 4
24812 // CHECK25-NEXT:    store i16 0, i16* [[AA]], align 2
24813 // CHECK25-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
24814 // CHECK25-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
24815 // CHECK25-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
24816 // CHECK25-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
24817 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24818 // CHECK25:       omp.inner.for.cond:
24819 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
24820 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21
24821 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
24822 // CHECK25-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24823 // CHECK25:       omp.inner.for.body:
24824 // CHECK25-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
24825 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
24826 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
24827 // CHECK25-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21
24828 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
24829 // CHECK25-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
24830 // CHECK25-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21
24831 // CHECK25-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
24832 // CHECK25-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
24833 // CHECK25-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
24834 // CHECK25-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
24835 // CHECK25-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21
24836 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
24837 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
24838 // CHECK25-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
24839 // CHECK25-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
24840 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24841 // CHECK25:       omp.body.continue:
24842 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24843 // CHECK25:       omp.inner.for.inc:
24844 // CHECK25-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
24845 // CHECK25-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
24846 // CHECK25-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
24847 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
24848 // CHECK25:       omp.inner.for.end:
24849 // CHECK25-NEXT:    store i64 11, i64* [[I]], align 8
24850 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
24851 // CHECK25-NEXT:    ret i32 [[TMP8]]
24852 //
24853 //
24854 // CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv
24855 // CHECK26-SAME: () #[[ATTR0:[0-9]+]] {
24856 // CHECK26-NEXT:  entry:
24857 // CHECK26-NEXT:    ret i64 0
24858 //
24859 //
24860 // CHECK26-LABEL: define {{[^@]+}}@_Z3fooi
24861 // CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24862 // CHECK26-NEXT:  entry:
24863 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24864 // CHECK26-NEXT:    [[A:%.*]] = alloca i32, align 4
24865 // CHECK26-NEXT:    [[AA:%.*]] = alloca i16, align 2
24866 // CHECK26-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
24867 // CHECK26-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
24868 // CHECK26-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
24869 // CHECK26-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
24870 // CHECK26-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
24871 // CHECK26-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
24872 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24873 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24874 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24875 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24876 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
24877 // CHECK26-NEXT:    [[K:%.*]] = alloca i64, align 8
24878 // CHECK26-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
24879 // CHECK26-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
24880 // CHECK26-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
24881 // CHECK26-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
24882 // CHECK26-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
24883 // CHECK26-NEXT:    [[I7:%.*]] = alloca i32, align 4
24884 // CHECK26-NEXT:    [[K8:%.*]] = alloca i64, align 8
24885 // CHECK26-NEXT:    [[LIN:%.*]] = alloca i32, align 4
24886 // CHECK26-NEXT:    [[_TMP21:%.*]] = alloca i64, align 8
24887 // CHECK26-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
24888 // CHECK26-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
24889 // CHECK26-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
24890 // CHECK26-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
24891 // CHECK26-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
24892 // CHECK26-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
24893 // CHECK26-NEXT:    [[IT:%.*]] = alloca i64, align 8
24894 // CHECK26-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
24895 // CHECK26-NEXT:    [[A29:%.*]] = alloca i32, align 4
24896 // CHECK26-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
24897 // CHECK26-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
24898 // CHECK26-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
24899 // CHECK26-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
24900 // CHECK26-NEXT:    [[IT62:%.*]] = alloca i16, align 2
24901 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
24902 // CHECK26-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
24903 // CHECK26-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
24904 // CHECK26-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
24905 // CHECK26-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
24906 // CHECK26-NEXT:    [[IT81:%.*]] = alloca i8, align 1
24907 // CHECK26-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24908 // CHECK26-NEXT:    store i32 0, i32* [[A]], align 4
24909 // CHECK26-NEXT:    store i16 0, i16* [[AA]], align 2
24910 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24911 // CHECK26-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
24912 // CHECK26-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
24913 // CHECK26-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
24914 // CHECK26-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
24915 // CHECK26-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
24916 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
24917 // CHECK26-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
24918 // CHECK26-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
24919 // CHECK26-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
24920 // CHECK26-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
24921 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24922 // CHECK26-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
24923 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24924 // CHECK26-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
24925 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24926 // CHECK26:       omp.inner.for.cond:
24927 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
24928 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
24929 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
24930 // CHECK26-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24931 // CHECK26:       omp.inner.for.body:
24932 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
24933 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
24934 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
24935 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
24936 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24937 // CHECK26:       omp.body.continue:
24938 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24939 // CHECK26:       omp.inner.for.inc:
24940 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
24941 // CHECK26-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
24942 // CHECK26-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
24943 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
24944 // CHECK26:       omp.inner.for.end:
24945 // CHECK26-NEXT:    store i32 33, i32* [[I]], align 4
24946 // CHECK26-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
24947 // CHECK26-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
24948 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
24949 // CHECK26-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
24950 // CHECK26-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
24951 // CHECK26-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
24952 // CHECK26-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K]], align 8
24953 // CHECK26-NEXT:    store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
24954 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
24955 // CHECK26:       omp.inner.for.cond9:
24956 // CHECK26-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
24957 // CHECK26-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
24958 // CHECK26-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
24959 // CHECK26-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
24960 // CHECK26:       omp.inner.for.body11:
24961 // CHECK26-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
24962 // CHECK26-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
24963 // CHECK26-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
24964 // CHECK26-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
24965 // CHECK26-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
24966 // CHECK26-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
24967 // CHECK26-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
24968 // CHECK26-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
24969 // CHECK26-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
24970 // CHECK26-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
24971 // CHECK26-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
24972 // CHECK26-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
24973 // CHECK26-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
24974 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
24975 // CHECK26:       omp.body.continue16:
24976 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
24977 // CHECK26:       omp.inner.for.inc17:
24978 // CHECK26-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
24979 // CHECK26-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
24980 // CHECK26-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
24981 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
24982 // CHECK26:       omp.inner.for.end19:
24983 // CHECK26-NEXT:    store i32 1, i32* [[I7]], align 4
24984 // CHECK26-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
24985 // CHECK26-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
24986 // CHECK26-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
24987 // CHECK26-NEXT:    store i32 12, i32* [[LIN]], align 4
24988 // CHECK26-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
24989 // CHECK26-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
24990 // CHECK26-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
24991 // CHECK26-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
24992 // CHECK26-NEXT:    [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
24993 // CHECK26-NEXT:    store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
24994 // CHECK26-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A]], align 4
24995 // CHECK26-NEXT:    store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
24996 // CHECK26-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
24997 // CHECK26-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
24998 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
24999 // CHECK26:       omp.inner.for.cond30:
25000 // CHECK26-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
25001 // CHECK26-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
25002 // CHECK26-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
25003 // CHECK26-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
25004 // CHECK26:       omp.inner.for.body32:
25005 // CHECK26-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
25006 // CHECK26-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP26]], 400
25007 // CHECK26-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
25008 // CHECK26-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
25009 // CHECK26-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
25010 // CHECK26-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
25011 // CHECK26-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
25012 // CHECK26-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
25013 // CHECK26-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
25014 // CHECK26-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
25015 // CHECK26-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
25016 // CHECK26-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
25017 // CHECK26-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
25018 // CHECK26-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
25019 // CHECK26-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
25020 // CHECK26-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
25021 // CHECK26-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
25022 // CHECK26-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
25023 // CHECK26-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
25024 // CHECK26-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
25025 // CHECK26-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
25026 // CHECK26-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
25027 // CHECK26-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
25028 // CHECK26-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
25029 // CHECK26-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
25030 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
25031 // CHECK26:       omp.body.continue46:
25032 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
25033 // CHECK26:       omp.inner.for.inc47:
25034 // CHECK26-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
25035 // CHECK26-NEXT:    [[ADD48:%.*]] = add i64 [[TMP34]], 1
25036 // CHECK26-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
25037 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
25038 // CHECK26:       omp.inner.for.end49:
25039 // CHECK26-NEXT:    store i64 400, i64* [[IT]], align 8
25040 // CHECK26-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
25041 // CHECK26-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
25042 // CHECK26-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
25043 // CHECK26-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP36]]
25044 // CHECK26-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
25045 // CHECK26-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
25046 // CHECK26-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
25047 // CHECK26-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
25048 // CHECK26-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
25049 // CHECK26-NEXT:    [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
25050 // CHECK26-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP38]]
25051 // CHECK26-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
25052 // CHECK26-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
25053 // CHECK26-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
25054 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
25055 // CHECK26-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
25056 // CHECK26-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
25057 // CHECK26-NEXT:    store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
25058 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
25059 // CHECK26:       omp.inner.for.cond63:
25060 // CHECK26-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
25061 // CHECK26-NEXT:    [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
25062 // CHECK26-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
25063 // CHECK26-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
25064 // CHECK26:       omp.inner.for.body65:
25065 // CHECK26-NEXT:    [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
25066 // CHECK26-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
25067 // CHECK26-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
25068 // CHECK26-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
25069 // CHECK26-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
25070 // CHECK26-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
25071 // CHECK26-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
25072 // CHECK26-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
25073 // CHECK26-NEXT:    [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
25074 // CHECK26-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
25075 // CHECK26-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
25076 // CHECK26-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
25077 // CHECK26-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
25078 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
25079 // CHECK26:       omp.body.continue73:
25080 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
25081 // CHECK26:       omp.inner.for.inc74:
25082 // CHECK26-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
25083 // CHECK26-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
25084 // CHECK26-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
25085 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
25086 // CHECK26:       omp.inner.for.end76:
25087 // CHECK26-NEXT:    store i16 22, i16* [[IT62]], align 2
25088 // CHECK26-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
25089 // CHECK26-NEXT:    store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
25090 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
25091 // CHECK26-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
25092 // CHECK26-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
25093 // CHECK26-NEXT:    store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
25094 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
25095 // CHECK26:       omp.inner.for.cond82:
25096 // CHECK26-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
25097 // CHECK26-NEXT:    [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
25098 // CHECK26-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
25099 // CHECK26-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
25100 // CHECK26:       omp.inner.for.body84:
25101 // CHECK26-NEXT:    [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
25102 // CHECK26-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
25103 // CHECK26-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
25104 // CHECK26-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
25105 // CHECK26-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
25106 // CHECK26-NEXT:    [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
25107 // CHECK26-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
25108 // CHECK26-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
25109 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
25110 // CHECK26-NEXT:    [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
25111 // CHECK26-NEXT:    [[CONV89:%.*]] = fpext float [[TMP52]] to double
25112 // CHECK26-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
25113 // CHECK26-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
25114 // CHECK26-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
25115 // CHECK26-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
25116 // CHECK26-NEXT:    [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
25117 // CHECK26-NEXT:    [[CONV93:%.*]] = fpext float [[TMP53]] to double
25118 // CHECK26-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
25119 // CHECK26-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
25120 // CHECK26-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
25121 // CHECK26-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
25122 // CHECK26-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
25123 // CHECK26-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
25124 // CHECK26-NEXT:    [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
25125 // CHECK26-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
25126 // CHECK26-NEXT:    [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
25127 // CHECK26-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
25128 // CHECK26-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
25129 // CHECK26-NEXT:    [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
25130 // CHECK26-NEXT:    [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
25131 // CHECK26-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
25132 // CHECK26-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
25133 // CHECK26-NEXT:    [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
25134 // CHECK26-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
25135 // CHECK26-NEXT:    store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
25136 // CHECK26-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
25137 // CHECK26-NEXT:    [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
25138 // CHECK26-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
25139 // CHECK26-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
25140 // CHECK26-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
25141 // CHECK26-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
25142 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
25143 // CHECK26:       omp.body.continue106:
25144 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
25145 // CHECK26:       omp.inner.for.inc107:
25146 // CHECK26-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
25147 // CHECK26-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
25148 // CHECK26-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
25149 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
25150 // CHECK26:       omp.inner.for.end109:
25151 // CHECK26-NEXT:    store i8 96, i8* [[IT81]], align 1
25152 // CHECK26-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
25153 // CHECK26-NEXT:    [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
25154 // CHECK26-NEXT:    call void @llvm.stackrestore(i8* [[TMP61]])
25155 // CHECK26-NEXT:    ret i32 [[TMP60]]
25156 //
25157 //
25158 // CHECK26-LABEL: define {{[^@]+}}@_Z3bari
25159 // CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
25160 // CHECK26-NEXT:  entry:
25161 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25162 // CHECK26-NEXT:    [[A:%.*]] = alloca i32, align 4
25163 // CHECK26-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
25164 // CHECK26-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25165 // CHECK26-NEXT:    store i32 0, i32* [[A]], align 4
25166 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25167 // CHECK26-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
25168 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25169 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
25170 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25171 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25172 // CHECK26-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
25173 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
25174 // CHECK26-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
25175 // CHECK26-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
25176 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
25177 // CHECK26-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
25178 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25179 // CHECK26-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
25180 // CHECK26-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
25181 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
25182 // CHECK26-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
25183 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25184 // CHECK26-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
25185 // CHECK26-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
25186 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25187 // CHECK26-NEXT:    ret i32 [[TMP8]]
25188 //
25189 //
25190 // CHECK26-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
25191 // CHECK26-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
25192 // CHECK26-NEXT:  entry:
25193 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
25194 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25195 // CHECK26-NEXT:    [[B:%.*]] = alloca i32, align 4
25196 // CHECK26-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
25197 // CHECK26-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
25198 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i64, align 8
25199 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
25200 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
25201 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
25202 // CHECK26-NEXT:    [[IT:%.*]] = alloca i64, align 8
25203 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
25204 // CHECK26-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25205 // CHECK26-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
25206 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25207 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
25208 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
25209 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
25210 // CHECK26-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
25211 // CHECK26-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
25212 // CHECK26-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
25213 // CHECK26-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
25214 // CHECK26-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
25215 // CHECK26-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
25216 // CHECK26-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
25217 // CHECK26-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
25218 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
25219 // CHECK26-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
25220 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25221 // CHECK26:       omp.inner.for.cond:
25222 // CHECK26-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
25223 // CHECK26-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
25224 // CHECK26-NEXT:    [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]]
25225 // CHECK26-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25226 // CHECK26:       omp.inner.for.body:
25227 // CHECK26-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
25228 // CHECK26-NEXT:    [[MUL:%.*]] = mul i64 [[TMP8]], 400
25229 // CHECK26-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
25230 // CHECK26-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
25231 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
25232 // CHECK26-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
25233 // CHECK26-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
25234 // CHECK26-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
25235 // CHECK26-NEXT:    store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18
25236 // CHECK26-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
25237 // CHECK26-NEXT:    [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18
25238 // CHECK26-NEXT:    [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
25239 // CHECK26-NEXT:    store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18
25240 // CHECK26-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
25241 // CHECK26-NEXT:    [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
25242 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
25243 // CHECK26-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
25244 // CHECK26-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18
25245 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25246 // CHECK26:       omp.body.continue:
25247 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25248 // CHECK26:       omp.inner.for.inc:
25249 // CHECK26-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
25250 // CHECK26-NEXT:    [[ADD6:%.*]] = add i64 [[TMP12]], 1
25251 // CHECK26-NEXT:    store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
25252 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
25253 // CHECK26:       omp.inner.for.end:
25254 // CHECK26-NEXT:    store i64 400, i64* [[IT]], align 8
25255 // CHECK26-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
25256 // CHECK26-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
25257 // CHECK26-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
25258 // CHECK26-NEXT:    [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
25259 // CHECK26-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP14]] to i32
25260 // CHECK26-NEXT:    [[TMP15:%.*]] = load i32, i32* [[B]], align 4
25261 // CHECK26-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]]
25262 // CHECK26-NEXT:    [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
25263 // CHECK26-NEXT:    call void @llvm.stackrestore(i8* [[TMP16]])
25264 // CHECK26-NEXT:    ret i32 [[ADD10]]
25265 //
25266 //
25267 // CHECK26-LABEL: define {{[^@]+}}@_ZL7fstatici
25268 // CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
25269 // CHECK26-NEXT:  entry:
25270 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25271 // CHECK26-NEXT:    [[A:%.*]] = alloca i32, align 4
25272 // CHECK26-NEXT:    [[AA:%.*]] = alloca i16, align 2
25273 // CHECK26-NEXT:    [[AAA:%.*]] = alloca i8, align 1
25274 // CHECK26-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25275 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
25276 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
25277 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
25278 // CHECK26-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25279 // CHECK26-NEXT:    store i32 0, i32* [[A]], align 4
25280 // CHECK26-NEXT:    store i16 0, i16* [[AA]], align 2
25281 // CHECK26-NEXT:    store i8 0, i8* [[AAA]], align 1
25282 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
25283 // CHECK26-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
25284 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
25285 // CHECK26-NEXT:    ret i32 [[TMP0]]
25286 //
25287 //
25288 // CHECK26-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
25289 // CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
25290 // CHECK26-NEXT:  entry:
25291 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25292 // CHECK26-NEXT:    [[A:%.*]] = alloca i32, align 4
25293 // CHECK26-NEXT:    [[AA:%.*]] = alloca i16, align 2
25294 // CHECK26-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25295 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i64, align 8
25296 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
25297 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
25298 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
25299 // CHECK26-NEXT:    [[I:%.*]] = alloca i64, align 8
25300 // CHECK26-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25301 // CHECK26-NEXT:    store i32 0, i32* [[A]], align 4
25302 // CHECK26-NEXT:    store i16 0, i16* [[AA]], align 2
25303 // CHECK26-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
25304 // CHECK26-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
25305 // CHECK26-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
25306 // CHECK26-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
25307 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25308 // CHECK26:       omp.inner.for.cond:
25309 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
25310 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21
25311 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
25312 // CHECK26-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25313 // CHECK26:       omp.inner.for.body:
25314 // CHECK26-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
25315 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
25316 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
25317 // CHECK26-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21
25318 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
25319 // CHECK26-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
25320 // CHECK26-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21
25321 // CHECK26-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
25322 // CHECK26-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
25323 // CHECK26-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
25324 // CHECK26-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
25325 // CHECK26-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21
25326 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
25327 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
25328 // CHECK26-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
25329 // CHECK26-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
25330 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25331 // CHECK26:       omp.body.continue:
25332 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25333 // CHECK26:       omp.inner.for.inc:
25334 // CHECK26-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
25335 // CHECK26-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
25336 // CHECK26-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21
25337 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
25338 // CHECK26:       omp.inner.for.end:
25339 // CHECK26-NEXT:    store i64 11, i64* [[I]], align 8
25340 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25341 // CHECK26-NEXT:    ret i32 [[TMP8]]
25342 //
25343 //
25344 // CHECK27-LABEL: define {{[^@]+}}@_Z7get_valv
25345 // CHECK27-SAME: () #[[ATTR0:[0-9]+]] {
25346 // CHECK27-NEXT:  entry:
25347 // CHECK27-NEXT:    ret i64 0
25348 //
25349 //
25350 // CHECK27-LABEL: define {{[^@]+}}@_Z3fooi
25351 // CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
25352 // CHECK27-NEXT:  entry:
25353 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25354 // CHECK27-NEXT:    [[A:%.*]] = alloca i32, align 4
25355 // CHECK27-NEXT:    [[AA:%.*]] = alloca i16, align 2
25356 // CHECK27-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
25357 // CHECK27-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
25358 // CHECK27-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
25359 // CHECK27-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
25360 // CHECK27-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
25361 // CHECK27-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
25362 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
25363 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
25364 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
25365 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
25366 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
25367 // CHECK27-NEXT:    [[K:%.*]] = alloca i64, align 8
25368 // CHECK27-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
25369 // CHECK27-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
25370 // CHECK27-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
25371 // CHECK27-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
25372 // CHECK27-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
25373 // CHECK27-NEXT:    [[I7:%.*]] = alloca i32, align 4
25374 // CHECK27-NEXT:    [[K8:%.*]] = alloca i64, align 8
25375 // CHECK27-NEXT:    [[LIN:%.*]] = alloca i32, align 4
25376 // CHECK27-NEXT:    [[_TMP21:%.*]] = alloca i64, align 4
25377 // CHECK27-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
25378 // CHECK27-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
25379 // CHECK27-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
25380 // CHECK27-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
25381 // CHECK27-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
25382 // CHECK27-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
25383 // CHECK27-NEXT:    [[IT:%.*]] = alloca i64, align 8
25384 // CHECK27-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
25385 // CHECK27-NEXT:    [[A29:%.*]] = alloca i32, align 4
25386 // CHECK27-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
25387 // CHECK27-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
25388 // CHECK27-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
25389 // CHECK27-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
25390 // CHECK27-NEXT:    [[IT62:%.*]] = alloca i16, align 2
25391 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
25392 // CHECK27-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
25393 // CHECK27-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
25394 // CHECK27-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
25395 // CHECK27-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
25396 // CHECK27-NEXT:    [[IT81:%.*]] = alloca i8, align 1
25397 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25398 // CHECK27-NEXT:    store i32 0, i32* [[A]], align 4
25399 // CHECK27-NEXT:    store i16 0, i16* [[AA]], align 2
25400 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25401 // CHECK27-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
25402 // CHECK27-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
25403 // CHECK27-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
25404 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
25405 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25406 // CHECK27-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
25407 // CHECK27-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
25408 // CHECK27-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
25409 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
25410 // CHECK27-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
25411 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
25412 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
25413 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25414 // CHECK27:       omp.inner.for.cond:
25415 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
25416 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
25417 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
25418 // CHECK27-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25419 // CHECK27:       omp.inner.for.body:
25420 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
25421 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
25422 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
25423 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
25424 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25425 // CHECK27:       omp.body.continue:
25426 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25427 // CHECK27:       omp.inner.for.inc:
25428 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
25429 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
25430 // CHECK27-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
25431 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
25432 // CHECK27:       omp.inner.for.end:
25433 // CHECK27-NEXT:    store i32 33, i32* [[I]], align 4
25434 // CHECK27-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
25435 // CHECK27-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
25436 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
25437 // CHECK27-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
25438 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
25439 // CHECK27-NEXT:    store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
25440 // CHECK27-NEXT:    [[TMP10:%.*]] = load i64, i64* [[K]], align 8
25441 // CHECK27-NEXT:    store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
25442 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
25443 // CHECK27:       omp.inner.for.cond9:
25444 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
25445 // CHECK27-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
25446 // CHECK27-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
25447 // CHECK27-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
25448 // CHECK27:       omp.inner.for.body11:
25449 // CHECK27-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
25450 // CHECK27-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
25451 // CHECK27-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
25452 // CHECK27-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
25453 // CHECK27-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
25454 // CHECK27-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
25455 // CHECK27-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
25456 // CHECK27-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
25457 // CHECK27-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
25458 // CHECK27-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
25459 // CHECK27-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
25460 // CHECK27-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
25461 // CHECK27-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
25462 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
25463 // CHECK27:       omp.body.continue16:
25464 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
25465 // CHECK27:       omp.inner.for.inc17:
25466 // CHECK27-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
25467 // CHECK27-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
25468 // CHECK27-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
25469 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
25470 // CHECK27:       omp.inner.for.end19:
25471 // CHECK27-NEXT:    store i32 1, i32* [[I7]], align 4
25472 // CHECK27-NEXT:    [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
25473 // CHECK27-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
25474 // CHECK27-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
25475 // CHECK27-NEXT:    store i32 12, i32* [[LIN]], align 4
25476 // CHECK27-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
25477 // CHECK27-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
25478 // CHECK27-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
25479 // CHECK27-NEXT:    store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
25480 // CHECK27-NEXT:    [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
25481 // CHECK27-NEXT:    store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
25482 // CHECK27-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
25483 // CHECK27-NEXT:    store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
25484 // CHECK27-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
25485 // CHECK27-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
25486 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
25487 // CHECK27:       omp.inner.for.cond30:
25488 // CHECK27-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
25489 // CHECK27-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
25490 // CHECK27-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
25491 // CHECK27-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
25492 // CHECK27:       omp.inner.for.body32:
25493 // CHECK27-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
25494 // CHECK27-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP24]], 400
25495 // CHECK27-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
25496 // CHECK27-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
25497 // CHECK27-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
25498 // CHECK27-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
25499 // CHECK27-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
25500 // CHECK27-NEXT:    [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
25501 // CHECK27-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
25502 // CHECK27-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
25503 // CHECK27-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
25504 // CHECK27-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
25505 // CHECK27-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
25506 // CHECK27-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
25507 // CHECK27-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
25508 // CHECK27-NEXT:    [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
25509 // CHECK27-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
25510 // CHECK27-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
25511 // CHECK27-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
25512 // CHECK27-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
25513 // CHECK27-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
25514 // CHECK27-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
25515 // CHECK27-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
25516 // CHECK27-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
25517 // CHECK27-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
25518 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
25519 // CHECK27:       omp.body.continue46:
25520 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
25521 // CHECK27:       omp.inner.for.inc47:
25522 // CHECK27-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
25523 // CHECK27-NEXT:    [[ADD48:%.*]] = add i64 [[TMP32]], 1
25524 // CHECK27-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
25525 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
25526 // CHECK27:       omp.inner.for.end49:
25527 // CHECK27-NEXT:    store i64 400, i64* [[IT]], align 8
25528 // CHECK27-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
25529 // CHECK27-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
25530 // CHECK27-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
25531 // CHECK27-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP34]]
25532 // CHECK27-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
25533 // CHECK27-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
25534 // CHECK27-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
25535 // CHECK27-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
25536 // CHECK27-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
25537 // CHECK27-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
25538 // CHECK27-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP36]]
25539 // CHECK27-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
25540 // CHECK27-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
25541 // CHECK27-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
25542 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
25543 // CHECK27-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
25544 // CHECK27-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
25545 // CHECK27-NEXT:    store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
25546 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
25547 // CHECK27:       omp.inner.for.cond63:
25548 // CHECK27-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
25549 // CHECK27-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
25550 // CHECK27-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
25551 // CHECK27-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
25552 // CHECK27:       omp.inner.for.body65:
25553 // CHECK27-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
25554 // CHECK27-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
25555 // CHECK27-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
25556 // CHECK27-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
25557 // CHECK27-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
25558 // CHECK27-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
25559 // CHECK27-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
25560 // CHECK27-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
25561 // CHECK27-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
25562 // CHECK27-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
25563 // CHECK27-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
25564 // CHECK27-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
25565 // CHECK27-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
25566 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
25567 // CHECK27:       omp.body.continue73:
25568 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
25569 // CHECK27:       omp.inner.for.inc74:
25570 // CHECK27-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
25571 // CHECK27-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
25572 // CHECK27-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
25573 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
25574 // CHECK27:       omp.inner.for.end76:
25575 // CHECK27-NEXT:    store i16 22, i16* [[IT62]], align 2
25576 // CHECK27-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
25577 // CHECK27-NEXT:    store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
25578 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
25579 // CHECK27-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
25580 // CHECK27-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
25581 // CHECK27-NEXT:    store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
25582 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
25583 // CHECK27:       omp.inner.for.cond82:
25584 // CHECK27-NEXT:    [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
25585 // CHECK27-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
25586 // CHECK27-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
25587 // CHECK27-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
25588 // CHECK27:       omp.inner.for.body84:
25589 // CHECK27-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
25590 // CHECK27-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
25591 // CHECK27-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
25592 // CHECK27-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
25593 // CHECK27-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
25594 // CHECK27-NEXT:    [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
25595 // CHECK27-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
25596 // CHECK27-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
25597 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
25598 // CHECK27-NEXT:    [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
25599 // CHECK27-NEXT:    [[CONV89:%.*]] = fpext float [[TMP50]] to double
25600 // CHECK27-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
25601 // CHECK27-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
25602 // CHECK27-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
25603 // CHECK27-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
25604 // CHECK27-NEXT:    [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
25605 // CHECK27-NEXT:    [[CONV93:%.*]] = fpext float [[TMP51]] to double
25606 // CHECK27-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
25607 // CHECK27-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
25608 // CHECK27-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
25609 // CHECK27-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
25610 // CHECK27-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
25611 // CHECK27-NEXT:    [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
25612 // CHECK27-NEXT:    [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
25613 // CHECK27-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
25614 // CHECK27-NEXT:    [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
25615 // CHECK27-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
25616 // CHECK27-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
25617 // CHECK27-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
25618 // CHECK27-NEXT:    [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
25619 // CHECK27-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
25620 // CHECK27-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
25621 // CHECK27-NEXT:    [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
25622 // CHECK27-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
25623 // CHECK27-NEXT:    store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
25624 // CHECK27-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
25625 // CHECK27-NEXT:    [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
25626 // CHECK27-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
25627 // CHECK27-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
25628 // CHECK27-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
25629 // CHECK27-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
25630 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
25631 // CHECK27:       omp.body.continue106:
25632 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
25633 // CHECK27:       omp.inner.for.inc107:
25634 // CHECK27-NEXT:    [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
25635 // CHECK27-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
25636 // CHECK27-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
25637 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
25638 // CHECK27:       omp.inner.for.end109:
25639 // CHECK27-NEXT:    store i8 96, i8* [[IT81]], align 1
25640 // CHECK27-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A]], align 4
25641 // CHECK27-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
25642 // CHECK27-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
25643 // CHECK27-NEXT:    ret i32 [[TMP58]]
25644 //
25645 //
25646 // CHECK27-LABEL: define {{[^@]+}}@_Z3bari
25647 // CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
25648 // CHECK27-NEXT:  entry:
25649 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25650 // CHECK27-NEXT:    [[A:%.*]] = alloca i32, align 4
25651 // CHECK27-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
25652 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25653 // CHECK27-NEXT:    store i32 0, i32* [[A]], align 4
25654 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25655 // CHECK27-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
25656 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25657 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
25658 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25659 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25660 // CHECK27-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
25661 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
25662 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
25663 // CHECK27-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
25664 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
25665 // CHECK27-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
25666 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25667 // CHECK27-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
25668 // CHECK27-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
25669 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
25670 // CHECK27-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
25671 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25672 // CHECK27-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
25673 // CHECK27-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
25674 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25675 // CHECK27-NEXT:    ret i32 [[TMP8]]
25676 //
25677 //
25678 // CHECK27-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
25679 // CHECK27-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
25680 // CHECK27-NEXT:  entry:
25681 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
25682 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25683 // CHECK27-NEXT:    [[B:%.*]] = alloca i32, align 4
25684 // CHECK27-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
25685 // CHECK27-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
25686 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i64, align 4
25687 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
25688 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
25689 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
25690 // CHECK27-NEXT:    [[IT:%.*]] = alloca i64, align 8
25691 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
25692 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25693 // CHECK27-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
25694 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25695 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
25696 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
25697 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
25698 // CHECK27-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
25699 // CHECK27-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
25700 // CHECK27-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
25701 // CHECK27-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
25702 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
25703 // CHECK27-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
25704 // CHECK27-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
25705 // CHECK27-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
25706 // CHECK27-NEXT:    store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8
25707 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25708 // CHECK27:       omp.inner.for.cond:
25709 // CHECK27-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
25710 // CHECK27-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
25711 // CHECK27-NEXT:    [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]]
25712 // CHECK27-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25713 // CHECK27:       omp.inner.for.body:
25714 // CHECK27-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
25715 // CHECK27-NEXT:    [[MUL:%.*]] = mul i64 [[TMP7]], 400
25716 // CHECK27-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
25717 // CHECK27-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
25718 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
25719 // CHECK27-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
25720 // CHECK27-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
25721 // CHECK27-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
25722 // CHECK27-NEXT:    store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19
25723 // CHECK27-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
25724 // CHECK27-NEXT:    [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19
25725 // CHECK27-NEXT:    [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
25726 // CHECK27-NEXT:    store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19
25727 // CHECK27-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
25728 // CHECK27-NEXT:    [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
25729 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
25730 // CHECK27-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
25731 // CHECK27-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19
25732 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25733 // CHECK27:       omp.body.continue:
25734 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25735 // CHECK27:       omp.inner.for.inc:
25736 // CHECK27-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
25737 // CHECK27-NEXT:    [[ADD6:%.*]] = add i64 [[TMP11]], 1
25738 // CHECK27-NEXT:    store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
25739 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
25740 // CHECK27:       omp.inner.for.end:
25741 // CHECK27-NEXT:    store i64 400, i64* [[IT]], align 8
25742 // CHECK27-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
25743 // CHECK27-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
25744 // CHECK27-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
25745 // CHECK27-NEXT:    [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
25746 // CHECK27-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP13]] to i32
25747 // CHECK27-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B]], align 4
25748 // CHECK27-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]]
25749 // CHECK27-NEXT:    [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
25750 // CHECK27-NEXT:    call void @llvm.stackrestore(i8* [[TMP15]])
25751 // CHECK27-NEXT:    ret i32 [[ADD10]]
25752 //
25753 //
25754 // CHECK27-LABEL: define {{[^@]+}}@_ZL7fstatici
25755 // CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
25756 // CHECK27-NEXT:  entry:
25757 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25758 // CHECK27-NEXT:    [[A:%.*]] = alloca i32, align 4
25759 // CHECK27-NEXT:    [[AA:%.*]] = alloca i16, align 2
25760 // CHECK27-NEXT:    [[AAA:%.*]] = alloca i8, align 1
25761 // CHECK27-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25762 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
25763 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
25764 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
25765 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25766 // CHECK27-NEXT:    store i32 0, i32* [[A]], align 4
25767 // CHECK27-NEXT:    store i16 0, i16* [[AA]], align 2
25768 // CHECK27-NEXT:    store i8 0, i8* [[AAA]], align 1
25769 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
25770 // CHECK27-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
25771 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
25772 // CHECK27-NEXT:    ret i32 [[TMP0]]
25773 //
25774 //
25775 // CHECK27-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
25776 // CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
25777 // CHECK27-NEXT:  entry:
25778 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25779 // CHECK27-NEXT:    [[A:%.*]] = alloca i32, align 4
25780 // CHECK27-NEXT:    [[AA:%.*]] = alloca i16, align 2
25781 // CHECK27-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25782 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i64, align 4
25783 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
25784 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
25785 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
25786 // CHECK27-NEXT:    [[I:%.*]] = alloca i64, align 8
25787 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25788 // CHECK27-NEXT:    store i32 0, i32* [[A]], align 4
25789 // CHECK27-NEXT:    store i16 0, i16* [[AA]], align 2
25790 // CHECK27-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
25791 // CHECK27-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
25792 // CHECK27-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
25793 // CHECK27-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
25794 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25795 // CHECK27:       omp.inner.for.cond:
25796 // CHECK27-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
25797 // CHECK27-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22
25798 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
25799 // CHECK27-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25800 // CHECK27:       omp.inner.for.body:
25801 // CHECK27-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
25802 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
25803 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
25804 // CHECK27-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22
25805 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
25806 // CHECK27-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
25807 // CHECK27-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22
25808 // CHECK27-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
25809 // CHECK27-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
25810 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
25811 // CHECK27-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
25812 // CHECK27-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22
25813 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
25814 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
25815 // CHECK27-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
25816 // CHECK27-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
25817 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25818 // CHECK27:       omp.body.continue:
25819 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25820 // CHECK27:       omp.inner.for.inc:
25821 // CHECK27-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
25822 // CHECK27-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
25823 // CHECK27-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
25824 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
25825 // CHECK27:       omp.inner.for.end:
25826 // CHECK27-NEXT:    store i64 11, i64* [[I]], align 8
25827 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25828 // CHECK27-NEXT:    ret i32 [[TMP8]]
25829 //
25830 //
25831 // CHECK28-LABEL: define {{[^@]+}}@_Z7get_valv
25832 // CHECK28-SAME: () #[[ATTR0:[0-9]+]] {
25833 // CHECK28-NEXT:  entry:
25834 // CHECK28-NEXT:    ret i64 0
25835 //
25836 //
25837 // CHECK28-LABEL: define {{[^@]+}}@_Z3fooi
25838 // CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
25839 // CHECK28-NEXT:  entry:
25840 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25841 // CHECK28-NEXT:    [[A:%.*]] = alloca i32, align 4
25842 // CHECK28-NEXT:    [[AA:%.*]] = alloca i16, align 2
25843 // CHECK28-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
25844 // CHECK28-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
25845 // CHECK28-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
25846 // CHECK28-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
25847 // CHECK28-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
25848 // CHECK28-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
25849 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
25850 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
25851 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
25852 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
25853 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
25854 // CHECK28-NEXT:    [[K:%.*]] = alloca i64, align 8
25855 // CHECK28-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
25856 // CHECK28-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
25857 // CHECK28-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
25858 // CHECK28-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
25859 // CHECK28-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
25860 // CHECK28-NEXT:    [[I7:%.*]] = alloca i32, align 4
25861 // CHECK28-NEXT:    [[K8:%.*]] = alloca i64, align 8
25862 // CHECK28-NEXT:    [[LIN:%.*]] = alloca i32, align 4
25863 // CHECK28-NEXT:    [[_TMP21:%.*]] = alloca i64, align 4
25864 // CHECK28-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
25865 // CHECK28-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
25866 // CHECK28-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
25867 // CHECK28-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
25868 // CHECK28-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
25869 // CHECK28-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
25870 // CHECK28-NEXT:    [[IT:%.*]] = alloca i64, align 8
25871 // CHECK28-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
25872 // CHECK28-NEXT:    [[A29:%.*]] = alloca i32, align 4
25873 // CHECK28-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
25874 // CHECK28-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
25875 // CHECK28-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
25876 // CHECK28-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
25877 // CHECK28-NEXT:    [[IT62:%.*]] = alloca i16, align 2
25878 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
25879 // CHECK28-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
25880 // CHECK28-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
25881 // CHECK28-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
25882 // CHECK28-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
25883 // CHECK28-NEXT:    [[IT81:%.*]] = alloca i8, align 1
25884 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25885 // CHECK28-NEXT:    store i32 0, i32* [[A]], align 4
25886 // CHECK28-NEXT:    store i16 0, i16* [[AA]], align 2
25887 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25888 // CHECK28-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
25889 // CHECK28-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
25890 // CHECK28-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
25891 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
25892 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25893 // CHECK28-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
25894 // CHECK28-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
25895 // CHECK28-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
25896 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
25897 // CHECK28-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
25898 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
25899 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
25900 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25901 // CHECK28:       omp.inner.for.cond:
25902 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
25903 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
25904 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
25905 // CHECK28-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25906 // CHECK28:       omp.inner.for.body:
25907 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
25908 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
25909 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
25910 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
25911 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25912 // CHECK28:       omp.body.continue:
25913 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25914 // CHECK28:       omp.inner.for.inc:
25915 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
25916 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
25917 // CHECK28-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
25918 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
25919 // CHECK28:       omp.inner.for.end:
25920 // CHECK28-NEXT:    store i32 33, i32* [[I]], align 4
25921 // CHECK28-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
25922 // CHECK28-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
25923 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
25924 // CHECK28-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
25925 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
25926 // CHECK28-NEXT:    store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
25927 // CHECK28-NEXT:    [[TMP10:%.*]] = load i64, i64* [[K]], align 8
25928 // CHECK28-NEXT:    store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
25929 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
25930 // CHECK28:       omp.inner.for.cond9:
25931 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
25932 // CHECK28-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
25933 // CHECK28-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
25934 // CHECK28-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
25935 // CHECK28:       omp.inner.for.body11:
25936 // CHECK28-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
25937 // CHECK28-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
25938 // CHECK28-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
25939 // CHECK28-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
25940 // CHECK28-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
25941 // CHECK28-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
25942 // CHECK28-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
25943 // CHECK28-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
25944 // CHECK28-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
25945 // CHECK28-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
25946 // CHECK28-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
25947 // CHECK28-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
25948 // CHECK28-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
25949 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
25950 // CHECK28:       omp.body.continue16:
25951 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
25952 // CHECK28:       omp.inner.for.inc17:
25953 // CHECK28-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
25954 // CHECK28-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
25955 // CHECK28-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
25956 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
25957 // CHECK28:       omp.inner.for.end19:
25958 // CHECK28-NEXT:    store i32 1, i32* [[I7]], align 4
25959 // CHECK28-NEXT:    [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
25960 // CHECK28-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
25961 // CHECK28-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
25962 // CHECK28-NEXT:    store i32 12, i32* [[LIN]], align 4
25963 // CHECK28-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
25964 // CHECK28-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
25965 // CHECK28-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
25966 // CHECK28-NEXT:    store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
25967 // CHECK28-NEXT:    [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
25968 // CHECK28-NEXT:    store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
25969 // CHECK28-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
25970 // CHECK28-NEXT:    store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
25971 // CHECK28-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
25972 // CHECK28-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
25973 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
25974 // CHECK28:       omp.inner.for.cond30:
25975 // CHECK28-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
25976 // CHECK28-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
25977 // CHECK28-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
25978 // CHECK28-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
25979 // CHECK28:       omp.inner.for.body32:
25980 // CHECK28-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
25981 // CHECK28-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP24]], 400
25982 // CHECK28-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
25983 // CHECK28-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
25984 // CHECK28-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
25985 // CHECK28-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
25986 // CHECK28-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
25987 // CHECK28-NEXT:    [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
25988 // CHECK28-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
25989 // CHECK28-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
25990 // CHECK28-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
25991 // CHECK28-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
25992 // CHECK28-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
25993 // CHECK28-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
25994 // CHECK28-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
25995 // CHECK28-NEXT:    [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
25996 // CHECK28-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
25997 // CHECK28-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
25998 // CHECK28-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
25999 // CHECK28-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
26000 // CHECK28-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
26001 // CHECK28-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
26002 // CHECK28-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
26003 // CHECK28-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
26004 // CHECK28-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
26005 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
26006 // CHECK28:       omp.body.continue46:
26007 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
26008 // CHECK28:       omp.inner.for.inc47:
26009 // CHECK28-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
26010 // CHECK28-NEXT:    [[ADD48:%.*]] = add i64 [[TMP32]], 1
26011 // CHECK28-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
26012 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
26013 // CHECK28:       omp.inner.for.end49:
26014 // CHECK28-NEXT:    store i64 400, i64* [[IT]], align 8
26015 // CHECK28-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
26016 // CHECK28-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
26017 // CHECK28-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
26018 // CHECK28-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP34]]
26019 // CHECK28-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
26020 // CHECK28-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
26021 // CHECK28-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
26022 // CHECK28-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
26023 // CHECK28-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
26024 // CHECK28-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
26025 // CHECK28-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP36]]
26026 // CHECK28-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
26027 // CHECK28-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
26028 // CHECK28-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
26029 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
26030 // CHECK28-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
26031 // CHECK28-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
26032 // CHECK28-NEXT:    store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
26033 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
26034 // CHECK28:       omp.inner.for.cond63:
26035 // CHECK28-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
26036 // CHECK28-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
26037 // CHECK28-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
26038 // CHECK28-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
26039 // CHECK28:       omp.inner.for.body65:
26040 // CHECK28-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
26041 // CHECK28-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
26042 // CHECK28-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
26043 // CHECK28-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
26044 // CHECK28-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
26045 // CHECK28-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
26046 // CHECK28-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
26047 // CHECK28-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
26048 // CHECK28-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
26049 // CHECK28-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
26050 // CHECK28-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
26051 // CHECK28-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
26052 // CHECK28-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
26053 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
26054 // CHECK28:       omp.body.continue73:
26055 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
26056 // CHECK28:       omp.inner.for.inc74:
26057 // CHECK28-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
26058 // CHECK28-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
26059 // CHECK28-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
26060 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
26061 // CHECK28:       omp.inner.for.end76:
26062 // CHECK28-NEXT:    store i16 22, i16* [[IT62]], align 2
26063 // CHECK28-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
26064 // CHECK28-NEXT:    store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
26065 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
26066 // CHECK28-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
26067 // CHECK28-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
26068 // CHECK28-NEXT:    store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
26069 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
26070 // CHECK28:       omp.inner.for.cond82:
26071 // CHECK28-NEXT:    [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
26072 // CHECK28-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
26073 // CHECK28-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
26074 // CHECK28-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
26075 // CHECK28:       omp.inner.for.body84:
26076 // CHECK28-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
26077 // CHECK28-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
26078 // CHECK28-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
26079 // CHECK28-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
26080 // CHECK28-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
26081 // CHECK28-NEXT:    [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
26082 // CHECK28-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
26083 // CHECK28-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
26084 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
26085 // CHECK28-NEXT:    [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
26086 // CHECK28-NEXT:    [[CONV89:%.*]] = fpext float [[TMP50]] to double
26087 // CHECK28-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
26088 // CHECK28-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
26089 // CHECK28-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
26090 // CHECK28-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
26091 // CHECK28-NEXT:    [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
26092 // CHECK28-NEXT:    [[CONV93:%.*]] = fpext float [[TMP51]] to double
26093 // CHECK28-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
26094 // CHECK28-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
26095 // CHECK28-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
26096 // CHECK28-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
26097 // CHECK28-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
26098 // CHECK28-NEXT:    [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
26099 // CHECK28-NEXT:    [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
26100 // CHECK28-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
26101 // CHECK28-NEXT:    [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
26102 // CHECK28-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
26103 // CHECK28-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
26104 // CHECK28-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
26105 // CHECK28-NEXT:    [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
26106 // CHECK28-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
26107 // CHECK28-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
26108 // CHECK28-NEXT:    [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
26109 // CHECK28-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
26110 // CHECK28-NEXT:    store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
26111 // CHECK28-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
26112 // CHECK28-NEXT:    [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
26113 // CHECK28-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
26114 // CHECK28-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
26115 // CHECK28-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
26116 // CHECK28-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
26117 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
26118 // CHECK28:       omp.body.continue106:
26119 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
26120 // CHECK28:       omp.inner.for.inc107:
26121 // CHECK28-NEXT:    [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
26122 // CHECK28-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
26123 // CHECK28-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
26124 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
26125 // CHECK28:       omp.inner.for.end109:
26126 // CHECK28-NEXT:    store i8 96, i8* [[IT81]], align 1
26127 // CHECK28-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A]], align 4
26128 // CHECK28-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
26129 // CHECK28-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
26130 // CHECK28-NEXT:    ret i32 [[TMP58]]
26131 //
26132 //
26133 // CHECK28-LABEL: define {{[^@]+}}@_Z3bari
26134 // CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
26135 // CHECK28-NEXT:  entry:
26136 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26137 // CHECK28-NEXT:    [[A:%.*]] = alloca i32, align 4
26138 // CHECK28-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
26139 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26140 // CHECK28-NEXT:    store i32 0, i32* [[A]], align 4
26141 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26142 // CHECK28-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
26143 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
26144 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
26145 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
26146 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
26147 // CHECK28-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
26148 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
26149 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
26150 // CHECK28-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
26151 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
26152 // CHECK28-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
26153 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
26154 // CHECK28-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
26155 // CHECK28-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
26156 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
26157 // CHECK28-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
26158 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
26159 // CHECK28-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
26160 // CHECK28-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
26161 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
26162 // CHECK28-NEXT:    ret i32 [[TMP8]]
26163 //
26164 //
26165 // CHECK28-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
26166 // CHECK28-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
26167 // CHECK28-NEXT:  entry:
26168 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
26169 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26170 // CHECK28-NEXT:    [[B:%.*]] = alloca i32, align 4
26171 // CHECK28-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
26172 // CHECK28-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
26173 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i64, align 4
26174 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
26175 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
26176 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
26177 // CHECK28-NEXT:    [[IT:%.*]] = alloca i64, align 8
26178 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
26179 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26180 // CHECK28-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
26181 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26182 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
26183 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
26184 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
26185 // CHECK28-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
26186 // CHECK28-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
26187 // CHECK28-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
26188 // CHECK28-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
26189 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
26190 // CHECK28-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
26191 // CHECK28-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
26192 // CHECK28-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
26193 // CHECK28-NEXT:    store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8
26194 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26195 // CHECK28:       omp.inner.for.cond:
26196 // CHECK28-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
26197 // CHECK28-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
26198 // CHECK28-NEXT:    [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]]
26199 // CHECK28-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26200 // CHECK28:       omp.inner.for.body:
26201 // CHECK28-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
26202 // CHECK28-NEXT:    [[MUL:%.*]] = mul i64 [[TMP7]], 400
26203 // CHECK28-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
26204 // CHECK28-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
26205 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
26206 // CHECK28-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
26207 // CHECK28-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
26208 // CHECK28-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
26209 // CHECK28-NEXT:    store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19
26210 // CHECK28-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
26211 // CHECK28-NEXT:    [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19
26212 // CHECK28-NEXT:    [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
26213 // CHECK28-NEXT:    store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19
26214 // CHECK28-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
26215 // CHECK28-NEXT:    [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
26216 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
26217 // CHECK28-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
26218 // CHECK28-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19
26219 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26220 // CHECK28:       omp.body.continue:
26221 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26222 // CHECK28:       omp.inner.for.inc:
26223 // CHECK28-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
26224 // CHECK28-NEXT:    [[ADD6:%.*]] = add i64 [[TMP11]], 1
26225 // CHECK28-NEXT:    store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
26226 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
26227 // CHECK28:       omp.inner.for.end:
26228 // CHECK28-NEXT:    store i64 400, i64* [[IT]], align 8
26229 // CHECK28-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
26230 // CHECK28-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
26231 // CHECK28-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
26232 // CHECK28-NEXT:    [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
26233 // CHECK28-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP13]] to i32
26234 // CHECK28-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B]], align 4
26235 // CHECK28-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]]
26236 // CHECK28-NEXT:    [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
26237 // CHECK28-NEXT:    call void @llvm.stackrestore(i8* [[TMP15]])
26238 // CHECK28-NEXT:    ret i32 [[ADD10]]
26239 //
26240 //
26241 // CHECK28-LABEL: define {{[^@]+}}@_ZL7fstatici
26242 // CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
26243 // CHECK28-NEXT:  entry:
26244 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26245 // CHECK28-NEXT:    [[A:%.*]] = alloca i32, align 4
26246 // CHECK28-NEXT:    [[AA:%.*]] = alloca i16, align 2
26247 // CHECK28-NEXT:    [[AAA:%.*]] = alloca i8, align 1
26248 // CHECK28-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
26249 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26250 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26251 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26252 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26253 // CHECK28-NEXT:    store i32 0, i32* [[A]], align 4
26254 // CHECK28-NEXT:    store i16 0, i16* [[AA]], align 2
26255 // CHECK28-NEXT:    store i8 0, i8* [[AAA]], align 1
26256 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26257 // CHECK28-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
26258 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
26259 // CHECK28-NEXT:    ret i32 [[TMP0]]
26260 //
26261 //
26262 // CHECK28-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
26263 // CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
26264 // CHECK28-NEXT:  entry:
26265 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26266 // CHECK28-NEXT:    [[A:%.*]] = alloca i32, align 4
26267 // CHECK28-NEXT:    [[AA:%.*]] = alloca i16, align 2
26268 // CHECK28-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
26269 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i64, align 4
26270 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
26271 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
26272 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
26273 // CHECK28-NEXT:    [[I:%.*]] = alloca i64, align 8
26274 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26275 // CHECK28-NEXT:    store i32 0, i32* [[A]], align 4
26276 // CHECK28-NEXT:    store i16 0, i16* [[AA]], align 2
26277 // CHECK28-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
26278 // CHECK28-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
26279 // CHECK28-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
26280 // CHECK28-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
26281 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26282 // CHECK28:       omp.inner.for.cond:
26283 // CHECK28-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
26284 // CHECK28-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22
26285 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
26286 // CHECK28-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26287 // CHECK28:       omp.inner.for.body:
26288 // CHECK28-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
26289 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
26290 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
26291 // CHECK28-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22
26292 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
26293 // CHECK28-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
26294 // CHECK28-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22
26295 // CHECK28-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
26296 // CHECK28-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
26297 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
26298 // CHECK28-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
26299 // CHECK28-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22
26300 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
26301 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
26302 // CHECK28-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
26303 // CHECK28-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
26304 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26305 // CHECK28:       omp.body.continue:
26306 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26307 // CHECK28:       omp.inner.for.inc:
26308 // CHECK28-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
26309 // CHECK28-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
26310 // CHECK28-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22
26311 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
26312 // CHECK28:       omp.inner.for.end:
26313 // CHECK28-NEXT:    store i64 11, i64* [[I]], align 8
26314 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
26315 // CHECK28-NEXT:    ret i32 [[TMP8]]
26316 //
26317 //
26318 // CHECK29-LABEL: define {{[^@]+}}@_Z7get_valv
26319 // CHECK29-SAME: () #[[ATTR0:[0-9]+]] {
26320 // CHECK29-NEXT:  entry:
26321 // CHECK29-NEXT:    ret i64 0
26322 //
26323 //
26324 // CHECK29-LABEL: define {{[^@]+}}@_Z3fooi
26325 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
26326 // CHECK29-NEXT:  entry:
26327 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26328 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
26329 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
26330 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
26331 // CHECK29-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
26332 // CHECK29-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
26333 // CHECK29-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
26334 // CHECK29-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
26335 // CHECK29-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
26336 // CHECK29-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26337 // CHECK29-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26338 // CHECK29-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26339 // CHECK29-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
26340 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
26341 // CHECK29-NEXT:    [[K:%.*]] = alloca i64, align 8
26342 // CHECK29-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
26343 // CHECK29-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
26344 // CHECK29-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
26345 // CHECK29-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
26346 // CHECK29-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
26347 // CHECK29-NEXT:    [[I7:%.*]] = alloca i32, align 4
26348 // CHECK29-NEXT:    [[K8:%.*]] = alloca i64, align 8
26349 // CHECK29-NEXT:    [[LIN:%.*]] = alloca i32, align 4
26350 // CHECK29-NEXT:    [[_TMP21:%.*]] = alloca i64, align 8
26351 // CHECK29-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
26352 // CHECK29-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
26353 // CHECK29-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
26354 // CHECK29-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
26355 // CHECK29-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
26356 // CHECK29-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
26357 // CHECK29-NEXT:    [[IT:%.*]] = alloca i64, align 8
26358 // CHECK29-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
26359 // CHECK29-NEXT:    [[A29:%.*]] = alloca i32, align 4
26360 // CHECK29-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
26361 // CHECK29-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
26362 // CHECK29-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
26363 // CHECK29-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
26364 // CHECK29-NEXT:    [[IT62:%.*]] = alloca i16, align 2
26365 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
26366 // CHECK29-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
26367 // CHECK29-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
26368 // CHECK29-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
26369 // CHECK29-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
26370 // CHECK29-NEXT:    [[IT81:%.*]] = alloca i8, align 1
26371 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26372 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
26373 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
26374 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26375 // CHECK29-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
26376 // CHECK29-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
26377 // CHECK29-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
26378 // CHECK29-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
26379 // CHECK29-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
26380 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
26381 // CHECK29-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
26382 // CHECK29-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
26383 // CHECK29-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
26384 // CHECK29-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
26385 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26386 // CHECK29-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
26387 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
26388 // CHECK29-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
26389 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26390 // CHECK29:       omp.inner.for.cond:
26391 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26392 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
26393 // CHECK29-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
26394 // CHECK29-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26395 // CHECK29:       omp.inner.for.body:
26396 // CHECK29-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26397 // CHECK29-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
26398 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
26399 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
26400 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26401 // CHECK29:       omp.body.continue:
26402 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26403 // CHECK29:       omp.inner.for.inc:
26404 // CHECK29-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26405 // CHECK29-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
26406 // CHECK29-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26407 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
26408 // CHECK29:       omp.inner.for.end:
26409 // CHECK29-NEXT:    store i32 33, i32* [[I]], align 4
26410 // CHECK29-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
26411 // CHECK29-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
26412 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
26413 // CHECK29-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
26414 // CHECK29-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
26415 // CHECK29-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
26416 // CHECK29-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K]], align 8
26417 // CHECK29-NEXT:    store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
26418 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
26419 // CHECK29:       omp.inner.for.cond9:
26420 // CHECK29-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
26421 // CHECK29-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
26422 // CHECK29-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
26423 // CHECK29-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
26424 // CHECK29:       omp.inner.for.body11:
26425 // CHECK29-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
26426 // CHECK29-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
26427 // CHECK29-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
26428 // CHECK29-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
26429 // CHECK29-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
26430 // CHECK29-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
26431 // CHECK29-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
26432 // CHECK29-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
26433 // CHECK29-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
26434 // CHECK29-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
26435 // CHECK29-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
26436 // CHECK29-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
26437 // CHECK29-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
26438 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
26439 // CHECK29:       omp.body.continue16:
26440 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
26441 // CHECK29:       omp.inner.for.inc17:
26442 // CHECK29-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
26443 // CHECK29-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
26444 // CHECK29-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
26445 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
26446 // CHECK29:       omp.inner.for.end19:
26447 // CHECK29-NEXT:    store i32 1, i32* [[I7]], align 4
26448 // CHECK29-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
26449 // CHECK29-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
26450 // CHECK29-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
26451 // CHECK29-NEXT:    store i32 12, i32* [[LIN]], align 4
26452 // CHECK29-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
26453 // CHECK29-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
26454 // CHECK29-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
26455 // CHECK29-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
26456 // CHECK29-NEXT:    [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
26457 // CHECK29-NEXT:    store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
26458 // CHECK29-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A]], align 4
26459 // CHECK29-NEXT:    store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
26460 // CHECK29-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
26461 // CHECK29-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
26462 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
26463 // CHECK29:       omp.inner.for.cond30:
26464 // CHECK29-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
26465 // CHECK29-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
26466 // CHECK29-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
26467 // CHECK29-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
26468 // CHECK29:       omp.inner.for.body32:
26469 // CHECK29-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
26470 // CHECK29-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP26]], 400
26471 // CHECK29-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
26472 // CHECK29-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
26473 // CHECK29-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
26474 // CHECK29-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
26475 // CHECK29-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
26476 // CHECK29-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
26477 // CHECK29-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
26478 // CHECK29-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
26479 // CHECK29-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
26480 // CHECK29-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
26481 // CHECK29-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
26482 // CHECK29-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
26483 // CHECK29-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
26484 // CHECK29-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
26485 // CHECK29-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
26486 // CHECK29-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
26487 // CHECK29-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
26488 // CHECK29-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
26489 // CHECK29-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
26490 // CHECK29-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
26491 // CHECK29-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
26492 // CHECK29-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
26493 // CHECK29-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
26494 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
26495 // CHECK29:       omp.body.continue46:
26496 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
26497 // CHECK29:       omp.inner.for.inc47:
26498 // CHECK29-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
26499 // CHECK29-NEXT:    [[ADD48:%.*]] = add i64 [[TMP34]], 1
26500 // CHECK29-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
26501 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
26502 // CHECK29:       omp.inner.for.end49:
26503 // CHECK29-NEXT:    store i64 400, i64* [[IT]], align 8
26504 // CHECK29-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
26505 // CHECK29-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
26506 // CHECK29-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
26507 // CHECK29-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP36]]
26508 // CHECK29-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
26509 // CHECK29-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
26510 // CHECK29-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
26511 // CHECK29-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
26512 // CHECK29-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
26513 // CHECK29-NEXT:    [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
26514 // CHECK29-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP38]]
26515 // CHECK29-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
26516 // CHECK29-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
26517 // CHECK29-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
26518 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
26519 // CHECK29-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
26520 // CHECK29-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
26521 // CHECK29-NEXT:    store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
26522 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
26523 // CHECK29:       omp.inner.for.cond63:
26524 // CHECK29-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
26525 // CHECK29-NEXT:    [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
26526 // CHECK29-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
26527 // CHECK29-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
26528 // CHECK29:       omp.inner.for.body65:
26529 // CHECK29-NEXT:    [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
26530 // CHECK29-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
26531 // CHECK29-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
26532 // CHECK29-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
26533 // CHECK29-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
26534 // CHECK29-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
26535 // CHECK29-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
26536 // CHECK29-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
26537 // CHECK29-NEXT:    [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
26538 // CHECK29-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
26539 // CHECK29-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
26540 // CHECK29-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
26541 // CHECK29-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
26542 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
26543 // CHECK29:       omp.body.continue73:
26544 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
26545 // CHECK29:       omp.inner.for.inc74:
26546 // CHECK29-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
26547 // CHECK29-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
26548 // CHECK29-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
26549 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
26550 // CHECK29:       omp.inner.for.end76:
26551 // CHECK29-NEXT:    store i16 22, i16* [[IT62]], align 2
26552 // CHECK29-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
26553 // CHECK29-NEXT:    store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
26554 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
26555 // CHECK29-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
26556 // CHECK29-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
26557 // CHECK29-NEXT:    store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
26558 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
26559 // CHECK29:       omp.inner.for.cond82:
26560 // CHECK29-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
26561 // CHECK29-NEXT:    [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
26562 // CHECK29-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
26563 // CHECK29-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
26564 // CHECK29:       omp.inner.for.body84:
26565 // CHECK29-NEXT:    [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
26566 // CHECK29-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
26567 // CHECK29-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
26568 // CHECK29-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
26569 // CHECK29-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
26570 // CHECK29-NEXT:    [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
26571 // CHECK29-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
26572 // CHECK29-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
26573 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
26574 // CHECK29-NEXT:    [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
26575 // CHECK29-NEXT:    [[CONV89:%.*]] = fpext float [[TMP52]] to double
26576 // CHECK29-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
26577 // CHECK29-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
26578 // CHECK29-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
26579 // CHECK29-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
26580 // CHECK29-NEXT:    [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
26581 // CHECK29-NEXT:    [[CONV93:%.*]] = fpext float [[TMP53]] to double
26582 // CHECK29-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
26583 // CHECK29-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
26584 // CHECK29-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
26585 // CHECK29-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
26586 // CHECK29-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
26587 // CHECK29-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
26588 // CHECK29-NEXT:    [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
26589 // CHECK29-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
26590 // CHECK29-NEXT:    [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
26591 // CHECK29-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
26592 // CHECK29-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
26593 // CHECK29-NEXT:    [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
26594 // CHECK29-NEXT:    [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
26595 // CHECK29-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
26596 // CHECK29-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
26597 // CHECK29-NEXT:    [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
26598 // CHECK29-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
26599 // CHECK29-NEXT:    store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
26600 // CHECK29-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
26601 // CHECK29-NEXT:    [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
26602 // CHECK29-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
26603 // CHECK29-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
26604 // CHECK29-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
26605 // CHECK29-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
26606 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
26607 // CHECK29:       omp.body.continue106:
26608 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
26609 // CHECK29:       omp.inner.for.inc107:
26610 // CHECK29-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
26611 // CHECK29-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
26612 // CHECK29-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
26613 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
26614 // CHECK29:       omp.inner.for.end109:
26615 // CHECK29-NEXT:    store i8 96, i8* [[IT81]], align 1
26616 // CHECK29-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
26617 // CHECK29-NEXT:    [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
26618 // CHECK29-NEXT:    call void @llvm.stackrestore(i8* [[TMP61]])
26619 // CHECK29-NEXT:    ret i32 [[TMP60]]
26620 //
26621 //
26622 // CHECK29-LABEL: define {{[^@]+}}@_Z3bari
26623 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
26624 // CHECK29-NEXT:  entry:
26625 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26626 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
26627 // CHECK29-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
26628 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26629 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
26630 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26631 // CHECK29-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
26632 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
26633 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
26634 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
26635 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
26636 // CHECK29-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
26637 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
26638 // CHECK29-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
26639 // CHECK29-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
26640 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
26641 // CHECK29-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
26642 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
26643 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
26644 // CHECK29-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
26645 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
26646 // CHECK29-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
26647 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
26648 // CHECK29-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
26649 // CHECK29-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
26650 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
26651 // CHECK29-NEXT:    ret i32 [[TMP8]]
26652 //
26653 //
26654 // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
26655 // CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
26656 // CHECK29-NEXT:  entry:
26657 // CHECK29-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
26658 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26659 // CHECK29-NEXT:    [[B:%.*]] = alloca i32, align 4
26660 // CHECK29-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
26661 // CHECK29-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
26662 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
26663 // CHECK29-NEXT:    [[TMP:%.*]] = alloca i64, align 8
26664 // CHECK29-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
26665 // CHECK29-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
26666 // CHECK29-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
26667 // CHECK29-NEXT:    [[IT:%.*]] = alloca i64, align 8
26668 // CHECK29-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
26669 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26670 // CHECK29-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
26671 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26672 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
26673 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
26674 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
26675 // CHECK29-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
26676 // CHECK29-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
26677 // CHECK29-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
26678 // CHECK29-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
26679 // CHECK29-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
26680 // CHECK29-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
26681 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
26682 // CHECK29-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
26683 // CHECK29-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
26684 // CHECK29-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
26685 // CHECK29-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
26686 // CHECK29-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
26687 // CHECK29-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
26688 // CHECK29-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
26689 // CHECK29-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
26690 // CHECK29-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
26691 // CHECK29-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
26692 // CHECK29:       omp_if.then:
26693 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26694 // CHECK29:       omp.inner.for.cond:
26695 // CHECK29-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
26696 // CHECK29-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
26697 // CHECK29-NEXT:    [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]]
26698 // CHECK29-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26699 // CHECK29:       omp.inner.for.body:
26700 // CHECK29-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
26701 // CHECK29-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 400
26702 // CHECK29-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
26703 // CHECK29-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
26704 // CHECK29-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
26705 // CHECK29-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
26706 // CHECK29-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
26707 // CHECK29-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
26708 // CHECK29-NEXT:    store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18
26709 // CHECK29-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
26710 // CHECK29-NEXT:    [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
26711 // CHECK29-NEXT:    [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
26712 // CHECK29-NEXT:    store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
26713 // CHECK29-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
26714 // CHECK29-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
26715 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
26716 // CHECK29-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
26717 // CHECK29-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
26718 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26719 // CHECK29:       omp.body.continue:
26720 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26721 // CHECK29:       omp.inner.for.inc:
26722 // CHECK29-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
26723 // CHECK29-NEXT:    [[ADD7:%.*]] = add i64 [[TMP14]], 1
26724 // CHECK29-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
26725 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
26726 // CHECK29:       omp.inner.for.end:
26727 // CHECK29-NEXT:    br label [[OMP_IF_END:%.*]]
26728 // CHECK29:       omp_if.else:
26729 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND8:%.*]]
26730 // CHECK29:       omp.inner.for.cond8:
26731 // CHECK29-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
26732 // CHECK29-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
26733 // CHECK29-NEXT:    [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]]
26734 // CHECK29-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
26735 // CHECK29:       omp.inner.for.body10:
26736 // CHECK29-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
26737 // CHECK29-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP17]], 400
26738 // CHECK29-NEXT:    [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
26739 // CHECK29-NEXT:    store i64 [[SUB12]], i64* [[IT]], align 8
26740 // CHECK29-NEXT:    [[TMP18:%.*]] = load i32, i32* [[B]], align 4
26741 // CHECK29-NEXT:    [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double
26742 // CHECK29-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
26743 // CHECK29-NEXT:    [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
26744 // CHECK29-NEXT:    store double [[ADD14]], double* [[A15]], align 8
26745 // CHECK29-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
26746 // CHECK29-NEXT:    [[TMP19:%.*]] = load double, double* [[A16]], align 8
26747 // CHECK29-NEXT:    [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00
26748 // CHECK29-NEXT:    store double [[INC17]], double* [[A16]], align 8
26749 // CHECK29-NEXT:    [[CONV18:%.*]] = fptosi double [[INC17]] to i16
26750 // CHECK29-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
26751 // CHECK29-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
26752 // CHECK29-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1
26753 // CHECK29-NEXT:    store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
26754 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE21:%.*]]
26755 // CHECK29:       omp.body.continue21:
26756 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC22:%.*]]
26757 // CHECK29:       omp.inner.for.inc22:
26758 // CHECK29-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
26759 // CHECK29-NEXT:    [[ADD23:%.*]] = add i64 [[TMP21]], 1
26760 // CHECK29-NEXT:    store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
26761 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]]
26762 // CHECK29:       omp.inner.for.end24:
26763 // CHECK29-NEXT:    br label [[OMP_IF_END]]
26764 // CHECK29:       omp_if.end:
26765 // CHECK29-NEXT:    store i64 400, i64* [[IT]], align 8
26766 // CHECK29-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
26767 // CHECK29-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
26768 // CHECK29-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1
26769 // CHECK29-NEXT:    [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
26770 // CHECK29-NEXT:    [[CONV27:%.*]] = sext i16 [[TMP23]] to i32
26771 // CHECK29-NEXT:    [[TMP24:%.*]] = load i32, i32* [[B]], align 4
26772 // CHECK29-NEXT:    [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]]
26773 // CHECK29-NEXT:    [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
26774 // CHECK29-NEXT:    call void @llvm.stackrestore(i8* [[TMP25]])
26775 // CHECK29-NEXT:    ret i32 [[ADD28]]
26776 //
26777 //
26778 // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici
26779 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
26780 // CHECK29-NEXT:  entry:
26781 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26782 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
26783 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
26784 // CHECK29-NEXT:    [[AAA:%.*]] = alloca i8, align 1
26785 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
26786 // CHECK29-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26787 // CHECK29-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26788 // CHECK29-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26789 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26790 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
26791 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
26792 // CHECK29-NEXT:    store i8 0, i8* [[AAA]], align 1
26793 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26794 // CHECK29-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
26795 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
26796 // CHECK29-NEXT:    ret i32 [[TMP0]]
26797 //
26798 //
26799 // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
26800 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
26801 // CHECK29-NEXT:  entry:
26802 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26803 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
26804 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
26805 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
26806 // CHECK29-NEXT:    [[TMP:%.*]] = alloca i64, align 8
26807 // CHECK29-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
26808 // CHECK29-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
26809 // CHECK29-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
26810 // CHECK29-NEXT:    [[I:%.*]] = alloca i64, align 8
26811 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26812 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
26813 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
26814 // CHECK29-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
26815 // CHECK29-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
26816 // CHECK29-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
26817 // CHECK29-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
26818 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26819 // CHECK29:       omp.inner.for.cond:
26820 // CHECK29-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
26821 // CHECK29-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24
26822 // CHECK29-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
26823 // CHECK29-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26824 // CHECK29:       omp.inner.for.body:
26825 // CHECK29-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
26826 // CHECK29-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
26827 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
26828 // CHECK29-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24
26829 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
26830 // CHECK29-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
26831 // CHECK29-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
26832 // CHECK29-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
26833 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
26834 // CHECK29-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
26835 // CHECK29-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
26836 // CHECK29-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
26837 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
26838 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
26839 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
26840 // CHECK29-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
26841 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26842 // CHECK29:       omp.body.continue:
26843 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26844 // CHECK29:       omp.inner.for.inc:
26845 // CHECK29-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
26846 // CHECK29-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
26847 // CHECK29-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
26848 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
26849 // CHECK29:       omp.inner.for.end:
26850 // CHECK29-NEXT:    store i64 11, i64* [[I]], align 8
26851 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
26852 // CHECK29-NEXT:    ret i32 [[TMP8]]
26853 //
26854 //
26855 // CHECK30-LABEL: define {{[^@]+}}@_Z7get_valv
26856 // CHECK30-SAME: () #[[ATTR0:[0-9]+]] {
26857 // CHECK30-NEXT:  entry:
26858 // CHECK30-NEXT:    ret i64 0
26859 //
26860 //
26861 // CHECK30-LABEL: define {{[^@]+}}@_Z3fooi
26862 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
26863 // CHECK30-NEXT:  entry:
26864 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26865 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
26866 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
26867 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
26868 // CHECK30-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
26869 // CHECK30-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
26870 // CHECK30-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
26871 // CHECK30-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
26872 // CHECK30-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
26873 // CHECK30-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26874 // CHECK30-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26875 // CHECK30-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26876 // CHECK30-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
26877 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
26878 // CHECK30-NEXT:    [[K:%.*]] = alloca i64, align 8
26879 // CHECK30-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
26880 // CHECK30-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
26881 // CHECK30-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
26882 // CHECK30-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
26883 // CHECK30-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
26884 // CHECK30-NEXT:    [[I7:%.*]] = alloca i32, align 4
26885 // CHECK30-NEXT:    [[K8:%.*]] = alloca i64, align 8
26886 // CHECK30-NEXT:    [[LIN:%.*]] = alloca i32, align 4
26887 // CHECK30-NEXT:    [[_TMP21:%.*]] = alloca i64, align 8
26888 // CHECK30-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
26889 // CHECK30-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
26890 // CHECK30-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
26891 // CHECK30-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
26892 // CHECK30-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
26893 // CHECK30-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
26894 // CHECK30-NEXT:    [[IT:%.*]] = alloca i64, align 8
26895 // CHECK30-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
26896 // CHECK30-NEXT:    [[A29:%.*]] = alloca i32, align 4
26897 // CHECK30-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
26898 // CHECK30-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
26899 // CHECK30-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
26900 // CHECK30-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
26901 // CHECK30-NEXT:    [[IT62:%.*]] = alloca i16, align 2
26902 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
26903 // CHECK30-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
26904 // CHECK30-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
26905 // CHECK30-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
26906 // CHECK30-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
26907 // CHECK30-NEXT:    [[IT81:%.*]] = alloca i8, align 1
26908 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26909 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
26910 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
26911 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26912 // CHECK30-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
26913 // CHECK30-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
26914 // CHECK30-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
26915 // CHECK30-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
26916 // CHECK30-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
26917 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
26918 // CHECK30-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
26919 // CHECK30-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
26920 // CHECK30-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
26921 // CHECK30-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
26922 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26923 // CHECK30-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
26924 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
26925 // CHECK30-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
26926 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26927 // CHECK30:       omp.inner.for.cond:
26928 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26929 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
26930 // CHECK30-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
26931 // CHECK30-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26932 // CHECK30:       omp.inner.for.body:
26933 // CHECK30-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26934 // CHECK30-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5
26935 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
26936 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
26937 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26938 // CHECK30:       omp.body.continue:
26939 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26940 // CHECK30:       omp.inner.for.inc:
26941 // CHECK30-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26942 // CHECK30-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
26943 // CHECK30-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26944 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
26945 // CHECK30:       omp.inner.for.end:
26946 // CHECK30-NEXT:    store i32 33, i32* [[I]], align 4
26947 // CHECK30-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
26948 // CHECK30-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
26949 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
26950 // CHECK30-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
26951 // CHECK30-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
26952 // CHECK30-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4
26953 // CHECK30-NEXT:    [[TMP12:%.*]] = load i64, i64* [[K]], align 8
26954 // CHECK30-NEXT:    store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8
26955 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
26956 // CHECK30:       omp.inner.for.cond9:
26957 // CHECK30-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
26958 // CHECK30-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6
26959 // CHECK30-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
26960 // CHECK30-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
26961 // CHECK30:       omp.inner.for.body11:
26962 // CHECK30-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
26963 // CHECK30-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1
26964 // CHECK30-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
26965 // CHECK30-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6
26966 // CHECK30-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6
26967 // CHECK30-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
26968 // CHECK30-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3
26969 // CHECK30-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
26970 // CHECK30-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]]
26971 // CHECK30-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6
26972 // CHECK30-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6
26973 // CHECK30-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
26974 // CHECK30-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6
26975 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
26976 // CHECK30:       omp.body.continue16:
26977 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
26978 // CHECK30:       omp.inner.for.inc17:
26979 // CHECK30-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
26980 // CHECK30-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
26981 // CHECK30-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6
26982 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]]
26983 // CHECK30:       omp.inner.for.end19:
26984 // CHECK30-NEXT:    store i32 1, i32* [[I7]], align 4
26985 // CHECK30-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
26986 // CHECK30-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP20]], 27
26987 // CHECK30-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
26988 // CHECK30-NEXT:    store i32 12, i32* [[LIN]], align 4
26989 // CHECK30-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
26990 // CHECK30-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
26991 // CHECK30-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
26992 // CHECK30-NEXT:    store i64 [[TMP21]], i64* [[DOTOMP_IV24]], align 8
26993 // CHECK30-NEXT:    [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4
26994 // CHECK30-NEXT:    store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4
26995 // CHECK30-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A]], align 4
26996 // CHECK30-NEXT:    store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4
26997 // CHECK30-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
26998 // CHECK30-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
26999 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
27000 // CHECK30:       omp.inner.for.cond30:
27001 // CHECK30-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
27002 // CHECK30-NEXT:    [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !9
27003 // CHECK30-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]]
27004 // CHECK30-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
27005 // CHECK30:       omp.inner.for.body32:
27006 // CHECK30-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
27007 // CHECK30-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP26]], 400
27008 // CHECK30-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
27009 // CHECK30-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !9
27010 // CHECK30-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9
27011 // CHECK30-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP27]] to i64
27012 // CHECK30-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
27013 // CHECK30-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
27014 // CHECK30-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP28]], [[TMP29]]
27015 // CHECK30-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
27016 // CHECK30-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
27017 // CHECK30-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !9
27018 // CHECK30-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !9
27019 // CHECK30-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP30]] to i64
27020 // CHECK30-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
27021 // CHECK30-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9
27022 // CHECK30-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP31]], [[TMP32]]
27023 // CHECK30-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
27024 // CHECK30-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
27025 // CHECK30-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !9
27026 // CHECK30-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
27027 // CHECK30-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP33]] to i32
27028 // CHECK30-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
27029 // CHECK30-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
27030 // CHECK30-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !9
27031 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
27032 // CHECK30:       omp.body.continue46:
27033 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
27034 // CHECK30:       omp.inner.for.inc47:
27035 // CHECK30-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
27036 // CHECK30-NEXT:    [[ADD48:%.*]] = add i64 [[TMP34]], 1
27037 // CHECK30-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !9
27038 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP10:![0-9]+]]
27039 // CHECK30:       omp.inner.for.end49:
27040 // CHECK30-NEXT:    store i64 400, i64* [[IT]], align 8
27041 // CHECK30-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
27042 // CHECK30-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP35]] to i64
27043 // CHECK30-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
27044 // CHECK30-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP36]]
27045 // CHECK30-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
27046 // CHECK30-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
27047 // CHECK30-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
27048 // CHECK30-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
27049 // CHECK30-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP37]] to i64
27050 // CHECK30-NEXT:    [[TMP38:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
27051 // CHECK30-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP38]]
27052 // CHECK30-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
27053 // CHECK30-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
27054 // CHECK30-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
27055 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
27056 // CHECK30-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
27057 // CHECK30-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
27058 // CHECK30-NEXT:    store i32 [[TMP39]], i32* [[DOTOMP_IV61]], align 4
27059 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
27060 // CHECK30:       omp.inner.for.cond63:
27061 // CHECK30-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
27062 // CHECK30-NEXT:    [[TMP41:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !12
27063 // CHECK30-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP40]], [[TMP41]]
27064 // CHECK30-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
27065 // CHECK30:       omp.inner.for.body65:
27066 // CHECK30-NEXT:    [[TMP42:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
27067 // CHECK30-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP42]], 4
27068 // CHECK30-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
27069 // CHECK30-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
27070 // CHECK30-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !12
27071 // CHECK30-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
27072 // CHECK30-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP43]], 1
27073 // CHECK30-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !12
27074 // CHECK30-NEXT:    [[TMP44:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
27075 // CHECK30-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP44]] to i32
27076 // CHECK30-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
27077 // CHECK30-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
27078 // CHECK30-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !12
27079 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
27080 // CHECK30:       omp.body.continue73:
27081 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
27082 // CHECK30:       omp.inner.for.inc74:
27083 // CHECK30-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
27084 // CHECK30-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP45]], 1
27085 // CHECK30-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !12
27086 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
27087 // CHECK30:       omp.inner.for.end76:
27088 // CHECK30-NEXT:    store i16 22, i16* [[IT62]], align 2
27089 // CHECK30-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
27090 // CHECK30-NEXT:    store i32 [[TMP46]], i32* [[DOTCAPTURE_EXPR_]], align 4
27091 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
27092 // CHECK30-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
27093 // CHECK30-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
27094 // CHECK30-NEXT:    store i32 [[TMP47]], i32* [[DOTOMP_IV80]], align 4
27095 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
27096 // CHECK30:       omp.inner.for.cond82:
27097 // CHECK30-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
27098 // CHECK30-NEXT:    [[TMP49:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !15
27099 // CHECK30-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP48]], [[TMP49]]
27100 // CHECK30-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
27101 // CHECK30:       omp.inner.for.body84:
27102 // CHECK30-NEXT:    [[TMP50:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
27103 // CHECK30-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP50]], 1
27104 // CHECK30-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
27105 // CHECK30-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
27106 // CHECK30-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !15
27107 // CHECK30-NEXT:    [[TMP51:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
27108 // CHECK30-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP51]], 1
27109 // CHECK30-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !15
27110 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
27111 // CHECK30-NEXT:    [[TMP52:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
27112 // CHECK30-NEXT:    [[CONV89:%.*]] = fpext float [[TMP52]] to double
27113 // CHECK30-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
27114 // CHECK30-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
27115 // CHECK30-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
27116 // CHECK30-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
27117 // CHECK30-NEXT:    [[TMP53:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
27118 // CHECK30-NEXT:    [[CONV93:%.*]] = fpext float [[TMP53]] to double
27119 // CHECK30-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
27120 // CHECK30-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
27121 // CHECK30-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !15
27122 // CHECK30-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
27123 // CHECK30-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i64 0, i64 2
27124 // CHECK30-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
27125 // CHECK30-NEXT:    [[ADD98:%.*]] = fadd double [[TMP54]], 1.000000e+00
27126 // CHECK30-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !15
27127 // CHECK30-NEXT:    [[TMP55:%.*]] = mul nsw i64 1, [[TMP4]]
27128 // CHECK30-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP55]]
27129 // CHECK30-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i64 3
27130 // CHECK30-NEXT:    [[TMP56:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
27131 // CHECK30-NEXT:    [[ADD101:%.*]] = fadd double [[TMP56]], 1.000000e+00
27132 // CHECK30-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !15
27133 // CHECK30-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
27134 // CHECK30-NEXT:    [[TMP57:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
27135 // CHECK30-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP57]], 1
27136 // CHECK30-NEXT:    store i64 [[ADD102]], i64* [[X]], align 8, !llvm.access.group !15
27137 // CHECK30-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
27138 // CHECK30-NEXT:    [[TMP58:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
27139 // CHECK30-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP58]] to i32
27140 // CHECK30-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
27141 // CHECK30-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
27142 // CHECK30-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 8, !llvm.access.group !15
27143 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
27144 // CHECK30:       omp.body.continue106:
27145 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
27146 // CHECK30:       omp.inner.for.inc107:
27147 // CHECK30-NEXT:    [[TMP59:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
27148 // CHECK30-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP59]], 1
27149 // CHECK30-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !15
27150 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP16:![0-9]+]]
27151 // CHECK30:       omp.inner.for.end109:
27152 // CHECK30-NEXT:    store i8 96, i8* [[IT81]], align 1
27153 // CHECK30-NEXT:    [[TMP60:%.*]] = load i32, i32* [[A]], align 4
27154 // CHECK30-NEXT:    [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
27155 // CHECK30-NEXT:    call void @llvm.stackrestore(i8* [[TMP61]])
27156 // CHECK30-NEXT:    ret i32 [[TMP60]]
27157 //
27158 //
27159 // CHECK30-LABEL: define {{[^@]+}}@_Z3bari
27160 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
27161 // CHECK30-NEXT:  entry:
27162 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27163 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
27164 // CHECK30-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
27165 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27166 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
27167 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27168 // CHECK30-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
27169 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
27170 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
27171 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
27172 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
27173 // CHECK30-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
27174 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
27175 // CHECK30-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
27176 // CHECK30-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
27177 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
27178 // CHECK30-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
27179 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
27180 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
27181 // CHECK30-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
27182 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
27183 // CHECK30-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
27184 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
27185 // CHECK30-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
27186 // CHECK30-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
27187 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
27188 // CHECK30-NEXT:    ret i32 [[TMP8]]
27189 //
27190 //
27191 // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
27192 // CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
27193 // CHECK30-NEXT:  entry:
27194 // CHECK30-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
27195 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27196 // CHECK30-NEXT:    [[B:%.*]] = alloca i32, align 4
27197 // CHECK30-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
27198 // CHECK30-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
27199 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
27200 // CHECK30-NEXT:    [[TMP:%.*]] = alloca i64, align 8
27201 // CHECK30-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
27202 // CHECK30-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
27203 // CHECK30-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
27204 // CHECK30-NEXT:    [[IT:%.*]] = alloca i64, align 8
27205 // CHECK30-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
27206 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27207 // CHECK30-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
27208 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27209 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
27210 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
27211 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
27212 // CHECK30-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
27213 // CHECK30-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
27214 // CHECK30-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
27215 // CHECK30-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
27216 // CHECK30-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
27217 // CHECK30-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
27218 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
27219 // CHECK30-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
27220 // CHECK30-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
27221 // CHECK30-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
27222 // CHECK30-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
27223 // CHECK30-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
27224 // CHECK30-NEXT:    [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
27225 // CHECK30-NEXT:    store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
27226 // CHECK30-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
27227 // CHECK30-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
27228 // CHECK30-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
27229 // CHECK30:       omp_if.then:
27230 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27231 // CHECK30:       omp.inner.for.cond:
27232 // CHECK30-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
27233 // CHECK30-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18
27234 // CHECK30-NEXT:    [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]]
27235 // CHECK30-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27236 // CHECK30:       omp.inner.for.body:
27237 // CHECK30-NEXT:    [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
27238 // CHECK30-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 400
27239 // CHECK30-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
27240 // CHECK30-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18
27241 // CHECK30-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
27242 // CHECK30-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
27243 // CHECK30-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
27244 // CHECK30-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
27245 // CHECK30-NEXT:    store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18
27246 // CHECK30-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
27247 // CHECK30-NEXT:    [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
27248 // CHECK30-NEXT:    [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
27249 // CHECK30-NEXT:    store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18
27250 // CHECK30-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
27251 // CHECK30-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
27252 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
27253 // CHECK30-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
27254 // CHECK30-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
27255 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27256 // CHECK30:       omp.body.continue:
27257 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27258 // CHECK30:       omp.inner.for.inc:
27259 // CHECK30-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
27260 // CHECK30-NEXT:    [[ADD7:%.*]] = add i64 [[TMP14]], 1
27261 // CHECK30-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18
27262 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
27263 // CHECK30:       omp.inner.for.end:
27264 // CHECK30-NEXT:    br label [[OMP_IF_END:%.*]]
27265 // CHECK30:       omp_if.else:
27266 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND8:%.*]]
27267 // CHECK30:       omp.inner.for.cond8:
27268 // CHECK30-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
27269 // CHECK30-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
27270 // CHECK30-NEXT:    [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]]
27271 // CHECK30-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
27272 // CHECK30:       omp.inner.for.body10:
27273 // CHECK30-NEXT:    [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
27274 // CHECK30-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP17]], 400
27275 // CHECK30-NEXT:    [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
27276 // CHECK30-NEXT:    store i64 [[SUB12]], i64* [[IT]], align 8
27277 // CHECK30-NEXT:    [[TMP18:%.*]] = load i32, i32* [[B]], align 4
27278 // CHECK30-NEXT:    [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double
27279 // CHECK30-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
27280 // CHECK30-NEXT:    [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
27281 // CHECK30-NEXT:    store double [[ADD14]], double* [[A15]], align 8
27282 // CHECK30-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
27283 // CHECK30-NEXT:    [[TMP19:%.*]] = load double, double* [[A16]], align 8
27284 // CHECK30-NEXT:    [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00
27285 // CHECK30-NEXT:    store double [[INC17]], double* [[A16]], align 8
27286 // CHECK30-NEXT:    [[CONV18:%.*]] = fptosi double [[INC17]] to i16
27287 // CHECK30-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
27288 // CHECK30-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
27289 // CHECK30-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1
27290 // CHECK30-NEXT:    store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
27291 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE21:%.*]]
27292 // CHECK30:       omp.body.continue21:
27293 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC22:%.*]]
27294 // CHECK30:       omp.inner.for.inc22:
27295 // CHECK30-NEXT:    [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
27296 // CHECK30-NEXT:    [[ADD23:%.*]] = add i64 [[TMP21]], 1
27297 // CHECK30-NEXT:    store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
27298 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]]
27299 // CHECK30:       omp.inner.for.end24:
27300 // CHECK30-NEXT:    br label [[OMP_IF_END]]
27301 // CHECK30:       omp_if.end:
27302 // CHECK30-NEXT:    store i64 400, i64* [[IT]], align 8
27303 // CHECK30-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
27304 // CHECK30-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
27305 // CHECK30-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1
27306 // CHECK30-NEXT:    [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
27307 // CHECK30-NEXT:    [[CONV27:%.*]] = sext i16 [[TMP23]] to i32
27308 // CHECK30-NEXT:    [[TMP24:%.*]] = load i32, i32* [[B]], align 4
27309 // CHECK30-NEXT:    [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]]
27310 // CHECK30-NEXT:    [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
27311 // CHECK30-NEXT:    call void @llvm.stackrestore(i8* [[TMP25]])
27312 // CHECK30-NEXT:    ret i32 [[ADD28]]
27313 //
27314 //
27315 // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici
27316 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
27317 // CHECK30-NEXT:  entry:
27318 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27319 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
27320 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
27321 // CHECK30-NEXT:    [[AAA:%.*]] = alloca i8, align 1
27322 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
27323 // CHECK30-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27324 // CHECK30-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27325 // CHECK30-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27326 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27327 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
27328 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
27329 // CHECK30-NEXT:    store i8 0, i8* [[AAA]], align 1
27330 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27331 // CHECK30-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
27332 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
27333 // CHECK30-NEXT:    ret i32 [[TMP0]]
27334 //
27335 //
27336 // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
27337 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
27338 // CHECK30-NEXT:  entry:
27339 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27340 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
27341 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
27342 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
27343 // CHECK30-NEXT:    [[TMP:%.*]] = alloca i64, align 8
27344 // CHECK30-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
27345 // CHECK30-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
27346 // CHECK30-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
27347 // CHECK30-NEXT:    [[I:%.*]] = alloca i64, align 8
27348 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27349 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
27350 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
27351 // CHECK30-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
27352 // CHECK30-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
27353 // CHECK30-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
27354 // CHECK30-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
27355 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27356 // CHECK30:       omp.inner.for.cond:
27357 // CHECK30-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
27358 // CHECK30-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24
27359 // CHECK30-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
27360 // CHECK30-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27361 // CHECK30:       omp.inner.for.body:
27362 // CHECK30-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
27363 // CHECK30-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
27364 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
27365 // CHECK30-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24
27366 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
27367 // CHECK30-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
27368 // CHECK30-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
27369 // CHECK30-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
27370 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
27371 // CHECK30-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
27372 // CHECK30-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
27373 // CHECK30-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
27374 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
27375 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
27376 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
27377 // CHECK30-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
27378 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27379 // CHECK30:       omp.body.continue:
27380 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27381 // CHECK30:       omp.inner.for.inc:
27382 // CHECK30-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
27383 // CHECK30-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
27384 // CHECK30-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24
27385 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
27386 // CHECK30:       omp.inner.for.end:
27387 // CHECK30-NEXT:    store i64 11, i64* [[I]], align 8
27388 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
27389 // CHECK30-NEXT:    ret i32 [[TMP8]]
27390 //
27391 //
27392 // CHECK31-LABEL: define {{[^@]+}}@_Z7get_valv
27393 // CHECK31-SAME: () #[[ATTR0:[0-9]+]] {
27394 // CHECK31-NEXT:  entry:
27395 // CHECK31-NEXT:    ret i64 0
27396 //
27397 //
27398 // CHECK31-LABEL: define {{[^@]+}}@_Z3fooi
27399 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
27400 // CHECK31-NEXT:  entry:
27401 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27402 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
27403 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
27404 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
27405 // CHECK31-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
27406 // CHECK31-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
27407 // CHECK31-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
27408 // CHECK31-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
27409 // CHECK31-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
27410 // CHECK31-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27411 // CHECK31-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27412 // CHECK31-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27413 // CHECK31-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
27414 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
27415 // CHECK31-NEXT:    [[K:%.*]] = alloca i64, align 8
27416 // CHECK31-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
27417 // CHECK31-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
27418 // CHECK31-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
27419 // CHECK31-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
27420 // CHECK31-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
27421 // CHECK31-NEXT:    [[I7:%.*]] = alloca i32, align 4
27422 // CHECK31-NEXT:    [[K8:%.*]] = alloca i64, align 8
27423 // CHECK31-NEXT:    [[LIN:%.*]] = alloca i32, align 4
27424 // CHECK31-NEXT:    [[_TMP21:%.*]] = alloca i64, align 4
27425 // CHECK31-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
27426 // CHECK31-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
27427 // CHECK31-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
27428 // CHECK31-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
27429 // CHECK31-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
27430 // CHECK31-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
27431 // CHECK31-NEXT:    [[IT:%.*]] = alloca i64, align 8
27432 // CHECK31-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
27433 // CHECK31-NEXT:    [[A29:%.*]] = alloca i32, align 4
27434 // CHECK31-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
27435 // CHECK31-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
27436 // CHECK31-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
27437 // CHECK31-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
27438 // CHECK31-NEXT:    [[IT62:%.*]] = alloca i16, align 2
27439 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
27440 // CHECK31-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
27441 // CHECK31-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
27442 // CHECK31-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
27443 // CHECK31-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
27444 // CHECK31-NEXT:    [[IT81:%.*]] = alloca i8, align 1
27445 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27446 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
27447 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
27448 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27449 // CHECK31-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
27450 // CHECK31-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
27451 // CHECK31-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
27452 // CHECK31-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
27453 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
27454 // CHECK31-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
27455 // CHECK31-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
27456 // CHECK31-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
27457 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27458 // CHECK31-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
27459 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
27460 // CHECK31-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
27461 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27462 // CHECK31:       omp.inner.for.cond:
27463 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
27464 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
27465 // CHECK31-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
27466 // CHECK31-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27467 // CHECK31:       omp.inner.for.body:
27468 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
27469 // CHECK31-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
27470 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
27471 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
27472 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27473 // CHECK31:       omp.body.continue:
27474 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27475 // CHECK31:       omp.inner.for.inc:
27476 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
27477 // CHECK31-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
27478 // CHECK31-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
27479 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
27480 // CHECK31:       omp.inner.for.end:
27481 // CHECK31-NEXT:    store i32 33, i32* [[I]], align 4
27482 // CHECK31-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
27483 // CHECK31-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
27484 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
27485 // CHECK31-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
27486 // CHECK31-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
27487 // CHECK31-NEXT:    store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
27488 // CHECK31-NEXT:    [[TMP10:%.*]] = load i64, i64* [[K]], align 8
27489 // CHECK31-NEXT:    store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
27490 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
27491 // CHECK31:       omp.inner.for.cond9:
27492 // CHECK31-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
27493 // CHECK31-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
27494 // CHECK31-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
27495 // CHECK31-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
27496 // CHECK31:       omp.inner.for.body11:
27497 // CHECK31-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
27498 // CHECK31-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
27499 // CHECK31-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
27500 // CHECK31-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
27501 // CHECK31-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
27502 // CHECK31-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
27503 // CHECK31-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
27504 // CHECK31-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
27505 // CHECK31-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
27506 // CHECK31-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
27507 // CHECK31-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
27508 // CHECK31-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
27509 // CHECK31-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
27510 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
27511 // CHECK31:       omp.body.continue16:
27512 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
27513 // CHECK31:       omp.inner.for.inc17:
27514 // CHECK31-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
27515 // CHECK31-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
27516 // CHECK31-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
27517 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
27518 // CHECK31:       omp.inner.for.end19:
27519 // CHECK31-NEXT:    store i32 1, i32* [[I7]], align 4
27520 // CHECK31-NEXT:    [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
27521 // CHECK31-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
27522 // CHECK31-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
27523 // CHECK31-NEXT:    store i32 12, i32* [[LIN]], align 4
27524 // CHECK31-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
27525 // CHECK31-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
27526 // CHECK31-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
27527 // CHECK31-NEXT:    store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
27528 // CHECK31-NEXT:    [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
27529 // CHECK31-NEXT:    store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
27530 // CHECK31-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
27531 // CHECK31-NEXT:    store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
27532 // CHECK31-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
27533 // CHECK31-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
27534 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
27535 // CHECK31:       omp.inner.for.cond30:
27536 // CHECK31-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
27537 // CHECK31-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
27538 // CHECK31-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
27539 // CHECK31-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
27540 // CHECK31:       omp.inner.for.body32:
27541 // CHECK31-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
27542 // CHECK31-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP24]], 400
27543 // CHECK31-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
27544 // CHECK31-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
27545 // CHECK31-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
27546 // CHECK31-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
27547 // CHECK31-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
27548 // CHECK31-NEXT:    [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
27549 // CHECK31-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
27550 // CHECK31-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
27551 // CHECK31-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
27552 // CHECK31-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
27553 // CHECK31-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
27554 // CHECK31-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
27555 // CHECK31-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
27556 // CHECK31-NEXT:    [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
27557 // CHECK31-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
27558 // CHECK31-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
27559 // CHECK31-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
27560 // CHECK31-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
27561 // CHECK31-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
27562 // CHECK31-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
27563 // CHECK31-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
27564 // CHECK31-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
27565 // CHECK31-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
27566 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
27567 // CHECK31:       omp.body.continue46:
27568 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
27569 // CHECK31:       omp.inner.for.inc47:
27570 // CHECK31-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
27571 // CHECK31-NEXT:    [[ADD48:%.*]] = add i64 [[TMP32]], 1
27572 // CHECK31-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
27573 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
27574 // CHECK31:       omp.inner.for.end49:
27575 // CHECK31-NEXT:    store i64 400, i64* [[IT]], align 8
27576 // CHECK31-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
27577 // CHECK31-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
27578 // CHECK31-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
27579 // CHECK31-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP34]]
27580 // CHECK31-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
27581 // CHECK31-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
27582 // CHECK31-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
27583 // CHECK31-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
27584 // CHECK31-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
27585 // CHECK31-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
27586 // CHECK31-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP36]]
27587 // CHECK31-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
27588 // CHECK31-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
27589 // CHECK31-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
27590 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
27591 // CHECK31-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
27592 // CHECK31-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
27593 // CHECK31-NEXT:    store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
27594 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
27595 // CHECK31:       omp.inner.for.cond63:
27596 // CHECK31-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
27597 // CHECK31-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
27598 // CHECK31-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
27599 // CHECK31-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
27600 // CHECK31:       omp.inner.for.body65:
27601 // CHECK31-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
27602 // CHECK31-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
27603 // CHECK31-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
27604 // CHECK31-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
27605 // CHECK31-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
27606 // CHECK31-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
27607 // CHECK31-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
27608 // CHECK31-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
27609 // CHECK31-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
27610 // CHECK31-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
27611 // CHECK31-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
27612 // CHECK31-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
27613 // CHECK31-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
27614 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
27615 // CHECK31:       omp.body.continue73:
27616 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
27617 // CHECK31:       omp.inner.for.inc74:
27618 // CHECK31-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
27619 // CHECK31-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
27620 // CHECK31-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
27621 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
27622 // CHECK31:       omp.inner.for.end76:
27623 // CHECK31-NEXT:    store i16 22, i16* [[IT62]], align 2
27624 // CHECK31-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
27625 // CHECK31-NEXT:    store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
27626 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
27627 // CHECK31-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
27628 // CHECK31-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
27629 // CHECK31-NEXT:    store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
27630 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
27631 // CHECK31:       omp.inner.for.cond82:
27632 // CHECK31-NEXT:    [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
27633 // CHECK31-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
27634 // CHECK31-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
27635 // CHECK31-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
27636 // CHECK31:       omp.inner.for.body84:
27637 // CHECK31-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
27638 // CHECK31-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
27639 // CHECK31-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
27640 // CHECK31-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
27641 // CHECK31-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
27642 // CHECK31-NEXT:    [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
27643 // CHECK31-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
27644 // CHECK31-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
27645 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
27646 // CHECK31-NEXT:    [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
27647 // CHECK31-NEXT:    [[CONV89:%.*]] = fpext float [[TMP50]] to double
27648 // CHECK31-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
27649 // CHECK31-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
27650 // CHECK31-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
27651 // CHECK31-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
27652 // CHECK31-NEXT:    [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
27653 // CHECK31-NEXT:    [[CONV93:%.*]] = fpext float [[TMP51]] to double
27654 // CHECK31-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
27655 // CHECK31-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
27656 // CHECK31-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
27657 // CHECK31-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
27658 // CHECK31-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
27659 // CHECK31-NEXT:    [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
27660 // CHECK31-NEXT:    [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
27661 // CHECK31-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
27662 // CHECK31-NEXT:    [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
27663 // CHECK31-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
27664 // CHECK31-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
27665 // CHECK31-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
27666 // CHECK31-NEXT:    [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
27667 // CHECK31-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
27668 // CHECK31-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
27669 // CHECK31-NEXT:    [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
27670 // CHECK31-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
27671 // CHECK31-NEXT:    store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
27672 // CHECK31-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
27673 // CHECK31-NEXT:    [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
27674 // CHECK31-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
27675 // CHECK31-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
27676 // CHECK31-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
27677 // CHECK31-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
27678 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
27679 // CHECK31:       omp.body.continue106:
27680 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
27681 // CHECK31:       omp.inner.for.inc107:
27682 // CHECK31-NEXT:    [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
27683 // CHECK31-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
27684 // CHECK31-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
27685 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
27686 // CHECK31:       omp.inner.for.end109:
27687 // CHECK31-NEXT:    store i8 96, i8* [[IT81]], align 1
27688 // CHECK31-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A]], align 4
27689 // CHECK31-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
27690 // CHECK31-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
27691 // CHECK31-NEXT:    ret i32 [[TMP58]]
27692 //
27693 //
27694 // CHECK31-LABEL: define {{[^@]+}}@_Z3bari
27695 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
27696 // CHECK31-NEXT:  entry:
27697 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27698 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
27699 // CHECK31-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
27700 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27701 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
27702 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27703 // CHECK31-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
27704 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
27705 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
27706 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
27707 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
27708 // CHECK31-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
27709 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
27710 // CHECK31-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
27711 // CHECK31-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
27712 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
27713 // CHECK31-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
27714 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
27715 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
27716 // CHECK31-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
27717 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
27718 // CHECK31-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
27719 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
27720 // CHECK31-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
27721 // CHECK31-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
27722 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
27723 // CHECK31-NEXT:    ret i32 [[TMP8]]
27724 //
27725 //
27726 // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
27727 // CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
27728 // CHECK31-NEXT:  entry:
27729 // CHECK31-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
27730 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27731 // CHECK31-NEXT:    [[B:%.*]] = alloca i32, align 4
27732 // CHECK31-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
27733 // CHECK31-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
27734 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
27735 // CHECK31-NEXT:    [[TMP:%.*]] = alloca i64, align 4
27736 // CHECK31-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
27737 // CHECK31-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
27738 // CHECK31-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
27739 // CHECK31-NEXT:    [[IT:%.*]] = alloca i64, align 8
27740 // CHECK31-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
27741 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27742 // CHECK31-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
27743 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27744 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
27745 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
27746 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
27747 // CHECK31-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
27748 // CHECK31-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
27749 // CHECK31-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
27750 // CHECK31-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
27751 // CHECK31-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
27752 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
27753 // CHECK31-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
27754 // CHECK31-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
27755 // CHECK31-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
27756 // CHECK31-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
27757 // CHECK31-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
27758 // CHECK31-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
27759 // CHECK31-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
27760 // CHECK31-NEXT:    [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
27761 // CHECK31-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
27762 // CHECK31-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
27763 // CHECK31:       omp_if.then:
27764 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27765 // CHECK31:       omp.inner.for.cond:
27766 // CHECK31-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
27767 // CHECK31-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
27768 // CHECK31-NEXT:    [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
27769 // CHECK31-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27770 // CHECK31:       omp.inner.for.body:
27771 // CHECK31-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
27772 // CHECK31-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
27773 // CHECK31-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
27774 // CHECK31-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
27775 // CHECK31-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
27776 // CHECK31-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
27777 // CHECK31-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
27778 // CHECK31-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
27779 // CHECK31-NEXT:    store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19
27780 // CHECK31-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
27781 // CHECK31-NEXT:    [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
27782 // CHECK31-NEXT:    [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
27783 // CHECK31-NEXT:    store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
27784 // CHECK31-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
27785 // CHECK31-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
27786 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
27787 // CHECK31-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
27788 // CHECK31-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
27789 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27790 // CHECK31:       omp.body.continue:
27791 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27792 // CHECK31:       omp.inner.for.inc:
27793 // CHECK31-NEXT:    [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
27794 // CHECK31-NEXT:    [[ADD7:%.*]] = add i64 [[TMP13]], 1
27795 // CHECK31-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
27796 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
27797 // CHECK31:       omp.inner.for.end:
27798 // CHECK31-NEXT:    br label [[OMP_IF_END:%.*]]
27799 // CHECK31:       omp_if.else:
27800 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND8:%.*]]
27801 // CHECK31:       omp.inner.for.cond8:
27802 // CHECK31-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
27803 // CHECK31-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
27804 // CHECK31-NEXT:    [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]]
27805 // CHECK31-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
27806 // CHECK31:       omp.inner.for.body10:
27807 // CHECK31-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
27808 // CHECK31-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP16]], 400
27809 // CHECK31-NEXT:    [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
27810 // CHECK31-NEXT:    store i64 [[SUB12]], i64* [[IT]], align 8
27811 // CHECK31-NEXT:    [[TMP17:%.*]] = load i32, i32* [[B]], align 4
27812 // CHECK31-NEXT:    [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double
27813 // CHECK31-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
27814 // CHECK31-NEXT:    [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
27815 // CHECK31-NEXT:    store double [[ADD14]], double* [[A15]], align 4
27816 // CHECK31-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
27817 // CHECK31-NEXT:    [[TMP18:%.*]] = load double, double* [[A16]], align 4
27818 // CHECK31-NEXT:    [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00
27819 // CHECK31-NEXT:    store double [[INC17]], double* [[A16]], align 4
27820 // CHECK31-NEXT:    [[CONV18:%.*]] = fptosi double [[INC17]] to i16
27821 // CHECK31-NEXT:    [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
27822 // CHECK31-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
27823 // CHECK31-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1
27824 // CHECK31-NEXT:    store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
27825 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE21:%.*]]
27826 // CHECK31:       omp.body.continue21:
27827 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC22:%.*]]
27828 // CHECK31:       omp.inner.for.inc22:
27829 // CHECK31-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
27830 // CHECK31-NEXT:    [[ADD23:%.*]] = add i64 [[TMP20]], 1
27831 // CHECK31-NEXT:    store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
27832 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]]
27833 // CHECK31:       omp.inner.for.end24:
27834 // CHECK31-NEXT:    br label [[OMP_IF_END]]
27835 // CHECK31:       omp_if.end:
27836 // CHECK31-NEXT:    store i64 400, i64* [[IT]], align 8
27837 // CHECK31-NEXT:    [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
27838 // CHECK31-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
27839 // CHECK31-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
27840 // CHECK31-NEXT:    [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
27841 // CHECK31-NEXT:    [[CONV27:%.*]] = sext i16 [[TMP22]] to i32
27842 // CHECK31-NEXT:    [[TMP23:%.*]] = load i32, i32* [[B]], align 4
27843 // CHECK31-NEXT:    [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]]
27844 // CHECK31-NEXT:    [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
27845 // CHECK31-NEXT:    call void @llvm.stackrestore(i8* [[TMP24]])
27846 // CHECK31-NEXT:    ret i32 [[ADD28]]
27847 //
27848 //
27849 // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici
27850 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
27851 // CHECK31-NEXT:  entry:
27852 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27853 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
27854 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
27855 // CHECK31-NEXT:    [[AAA:%.*]] = alloca i8, align 1
27856 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
27857 // CHECK31-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27858 // CHECK31-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27859 // CHECK31-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27860 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27861 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
27862 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
27863 // CHECK31-NEXT:    store i8 0, i8* [[AAA]], align 1
27864 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27865 // CHECK31-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
27866 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
27867 // CHECK31-NEXT:    ret i32 [[TMP0]]
27868 //
27869 //
27870 // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
27871 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
27872 // CHECK31-NEXT:  entry:
27873 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27874 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
27875 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
27876 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
27877 // CHECK31-NEXT:    [[TMP:%.*]] = alloca i64, align 4
27878 // CHECK31-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
27879 // CHECK31-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
27880 // CHECK31-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
27881 // CHECK31-NEXT:    [[I:%.*]] = alloca i64, align 8
27882 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27883 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
27884 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
27885 // CHECK31-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
27886 // CHECK31-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
27887 // CHECK31-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
27888 // CHECK31-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
27889 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27890 // CHECK31:       omp.inner.for.cond:
27891 // CHECK31-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
27892 // CHECK31-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25
27893 // CHECK31-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
27894 // CHECK31-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27895 // CHECK31:       omp.inner.for.body:
27896 // CHECK31-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
27897 // CHECK31-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
27898 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
27899 // CHECK31-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25
27900 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
27901 // CHECK31-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
27902 // CHECK31-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
27903 // CHECK31-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
27904 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
27905 // CHECK31-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
27906 // CHECK31-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
27907 // CHECK31-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
27908 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
27909 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
27910 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
27911 // CHECK31-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
27912 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27913 // CHECK31:       omp.body.continue:
27914 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27915 // CHECK31:       omp.inner.for.inc:
27916 // CHECK31-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
27917 // CHECK31-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
27918 // CHECK31-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
27919 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
27920 // CHECK31:       omp.inner.for.end:
27921 // CHECK31-NEXT:    store i64 11, i64* [[I]], align 8
27922 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
27923 // CHECK31-NEXT:    ret i32 [[TMP8]]
27924 //
27925 //
27926 // CHECK32-LABEL: define {{[^@]+}}@_Z7get_valv
27927 // CHECK32-SAME: () #[[ATTR0:[0-9]+]] {
27928 // CHECK32-NEXT:  entry:
27929 // CHECK32-NEXT:    ret i64 0
27930 //
27931 //
27932 // CHECK32-LABEL: define {{[^@]+}}@_Z3fooi
27933 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
27934 // CHECK32-NEXT:  entry:
27935 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27936 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
27937 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
27938 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
27939 // CHECK32-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
27940 // CHECK32-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
27941 // CHECK32-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
27942 // CHECK32-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
27943 // CHECK32-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
27944 // CHECK32-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27945 // CHECK32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27946 // CHECK32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27947 // CHECK32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
27948 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
27949 // CHECK32-NEXT:    [[K:%.*]] = alloca i64, align 8
27950 // CHECK32-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
27951 // CHECK32-NEXT:    [[DOTOMP_LB4:%.*]] = alloca i32, align 4
27952 // CHECK32-NEXT:    [[DOTOMP_UB5:%.*]] = alloca i32, align 4
27953 // CHECK32-NEXT:    [[DOTOMP_IV6:%.*]] = alloca i32, align 4
27954 // CHECK32-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
27955 // CHECK32-NEXT:    [[I7:%.*]] = alloca i32, align 4
27956 // CHECK32-NEXT:    [[K8:%.*]] = alloca i64, align 8
27957 // CHECK32-NEXT:    [[LIN:%.*]] = alloca i32, align 4
27958 // CHECK32-NEXT:    [[_TMP21:%.*]] = alloca i64, align 4
27959 // CHECK32-NEXT:    [[DOTOMP_LB22:%.*]] = alloca i64, align 8
27960 // CHECK32-NEXT:    [[DOTOMP_UB23:%.*]] = alloca i64, align 8
27961 // CHECK32-NEXT:    [[DOTOMP_IV24:%.*]] = alloca i64, align 8
27962 // CHECK32-NEXT:    [[DOTLINEAR_START25:%.*]] = alloca i32, align 4
27963 // CHECK32-NEXT:    [[DOTLINEAR_START26:%.*]] = alloca i32, align 4
27964 // CHECK32-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
27965 // CHECK32-NEXT:    [[IT:%.*]] = alloca i64, align 8
27966 // CHECK32-NEXT:    [[LIN28:%.*]] = alloca i32, align 4
27967 // CHECK32-NEXT:    [[A29:%.*]] = alloca i32, align 4
27968 // CHECK32-NEXT:    [[_TMP58:%.*]] = alloca i16, align 2
27969 // CHECK32-NEXT:    [[DOTOMP_LB59:%.*]] = alloca i32, align 4
27970 // CHECK32-NEXT:    [[DOTOMP_UB60:%.*]] = alloca i32, align 4
27971 // CHECK32-NEXT:    [[DOTOMP_IV61:%.*]] = alloca i32, align 4
27972 // CHECK32-NEXT:    [[IT62:%.*]] = alloca i16, align 2
27973 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
27974 // CHECK32-NEXT:    [[_TMP77:%.*]] = alloca i8, align 1
27975 // CHECK32-NEXT:    [[DOTOMP_LB78:%.*]] = alloca i32, align 4
27976 // CHECK32-NEXT:    [[DOTOMP_UB79:%.*]] = alloca i32, align 4
27977 // CHECK32-NEXT:    [[DOTOMP_IV80:%.*]] = alloca i32, align 4
27978 // CHECK32-NEXT:    [[IT81:%.*]] = alloca i8, align 1
27979 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27980 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
27981 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
27982 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27983 // CHECK32-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
27984 // CHECK32-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
27985 // CHECK32-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
27986 // CHECK32-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
27987 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
27988 // CHECK32-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
27989 // CHECK32-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
27990 // CHECK32-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
27991 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27992 // CHECK32-NEXT:    store i32 5, i32* [[DOTOMP_UB]], align 4
27993 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
27994 // CHECK32-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
27995 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27996 // CHECK32:       omp.inner.for.cond:
27997 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
27998 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
27999 // CHECK32-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
28000 // CHECK32-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28001 // CHECK32:       omp.inner.for.body:
28002 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
28003 // CHECK32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
28004 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
28005 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
28006 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28007 // CHECK32:       omp.body.continue:
28008 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28009 // CHECK32:       omp.inner.for.inc:
28010 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
28011 // CHECK32-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
28012 // CHECK32-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
28013 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
28014 // CHECK32:       omp.inner.for.end:
28015 // CHECK32-NEXT:    store i32 33, i32* [[I]], align 4
28016 // CHECK32-NEXT:    [[CALL:%.*]] = call i64 @_Z7get_valv()
28017 // CHECK32-NEXT:    store i64 [[CALL]], i64* [[K]], align 8
28018 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB4]], align 4
28019 // CHECK32-NEXT:    store i32 8, i32* [[DOTOMP_UB5]], align 4
28020 // CHECK32-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4
28021 // CHECK32-NEXT:    store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4
28022 // CHECK32-NEXT:    [[TMP10:%.*]] = load i64, i64* [[K]], align 8
28023 // CHECK32-NEXT:    store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8
28024 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
28025 // CHECK32:       omp.inner.for.cond9:
28026 // CHECK32-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
28027 // CHECK32-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7
28028 // CHECK32-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
28029 // CHECK32-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
28030 // CHECK32:       omp.inner.for.body11:
28031 // CHECK32-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
28032 // CHECK32-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1
28033 // CHECK32-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL12]]
28034 // CHECK32-NEXT:    store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7
28035 // CHECK32-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7
28036 // CHECK32-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
28037 // CHECK32-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3
28038 // CHECK32-NEXT:    [[CONV:%.*]] = sext i32 [[MUL13]] to i64
28039 // CHECK32-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]]
28040 // CHECK32-NEXT:    store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7
28041 // CHECK32-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7
28042 // CHECK32-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
28043 // CHECK32-NEXT:    store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7
28044 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
28045 // CHECK32:       omp.body.continue16:
28046 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
28047 // CHECK32:       omp.inner.for.inc17:
28048 // CHECK32-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
28049 // CHECK32-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
28050 // CHECK32-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7
28051 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]]
28052 // CHECK32:       omp.inner.for.end19:
28053 // CHECK32-NEXT:    store i32 1, i32* [[I7]], align 4
28054 // CHECK32-NEXT:    [[TMP18:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8
28055 // CHECK32-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP18]], 27
28056 // CHECK32-NEXT:    store i64 [[ADD20]], i64* [[K]], align 8
28057 // CHECK32-NEXT:    store i32 12, i32* [[LIN]], align 4
28058 // CHECK32-NEXT:    store i64 0, i64* [[DOTOMP_LB22]], align 8
28059 // CHECK32-NEXT:    store i64 3, i64* [[DOTOMP_UB23]], align 8
28060 // CHECK32-NEXT:    [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB22]], align 8
28061 // CHECK32-NEXT:    store i64 [[TMP19]], i64* [[DOTOMP_IV24]], align 8
28062 // CHECK32-NEXT:    [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4
28063 // CHECK32-NEXT:    store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4
28064 // CHECK32-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
28065 // CHECK32-NEXT:    store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4
28066 // CHECK32-NEXT:    [[CALL27:%.*]] = call i64 @_Z7get_valv()
28067 // CHECK32-NEXT:    store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8
28068 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
28069 // CHECK32:       omp.inner.for.cond30:
28070 // CHECK32-NEXT:    [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
28071 // CHECK32-NEXT:    [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB23]], align 8, !llvm.access.group !10
28072 // CHECK32-NEXT:    [[CMP31:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]]
28073 // CHECK32-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END49:%.*]]
28074 // CHECK32:       omp.inner.for.body32:
28075 // CHECK32-NEXT:    [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
28076 // CHECK32-NEXT:    [[MUL33:%.*]] = mul i64 [[TMP24]], 400
28077 // CHECK32-NEXT:    [[SUB34:%.*]] = sub i64 2000, [[MUL33]]
28078 // CHECK32-NEXT:    store i64 [[SUB34]], i64* [[IT]], align 8, !llvm.access.group !10
28079 // CHECK32-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10
28080 // CHECK32-NEXT:    [[CONV35:%.*]] = sext i32 [[TMP25]] to i64
28081 // CHECK32-NEXT:    [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
28082 // CHECK32-NEXT:    [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
28083 // CHECK32-NEXT:    [[MUL36:%.*]] = mul i64 [[TMP26]], [[TMP27]]
28084 // CHECK32-NEXT:    [[ADD37:%.*]] = add i64 [[CONV35]], [[MUL36]]
28085 // CHECK32-NEXT:    [[CONV38:%.*]] = trunc i64 [[ADD37]] to i32
28086 // CHECK32-NEXT:    store i32 [[CONV38]], i32* [[LIN28]], align 4, !llvm.access.group !10
28087 // CHECK32-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4, !llvm.access.group !10
28088 // CHECK32-NEXT:    [[CONV39:%.*]] = sext i32 [[TMP28]] to i64
28089 // CHECK32-NEXT:    [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
28090 // CHECK32-NEXT:    [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10
28091 // CHECK32-NEXT:    [[MUL40:%.*]] = mul i64 [[TMP29]], [[TMP30]]
28092 // CHECK32-NEXT:    [[ADD41:%.*]] = add i64 [[CONV39]], [[MUL40]]
28093 // CHECK32-NEXT:    [[CONV42:%.*]] = trunc i64 [[ADD41]] to i32
28094 // CHECK32-NEXT:    store i32 [[CONV42]], i32* [[A29]], align 4, !llvm.access.group !10
28095 // CHECK32-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
28096 // CHECK32-NEXT:    [[CONV43:%.*]] = sext i16 [[TMP31]] to i32
28097 // CHECK32-NEXT:    [[ADD44:%.*]] = add nsw i32 [[CONV43]], 1
28098 // CHECK32-NEXT:    [[CONV45:%.*]] = trunc i32 [[ADD44]] to i16
28099 // CHECK32-NEXT:    store i16 [[CONV45]], i16* [[AA]], align 2, !llvm.access.group !10
28100 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE46:%.*]]
28101 // CHECK32:       omp.body.continue46:
28102 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC47:%.*]]
28103 // CHECK32:       omp.inner.for.inc47:
28104 // CHECK32-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
28105 // CHECK32-NEXT:    [[ADD48:%.*]] = add i64 [[TMP32]], 1
28106 // CHECK32-NEXT:    store i64 [[ADD48]], i64* [[DOTOMP_IV24]], align 8, !llvm.access.group !10
28107 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP11:![0-9]+]]
28108 // CHECK32:       omp.inner.for.end49:
28109 // CHECK32-NEXT:    store i64 400, i64* [[IT]], align 8
28110 // CHECK32-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4
28111 // CHECK32-NEXT:    [[CONV50:%.*]] = sext i32 [[TMP33]] to i64
28112 // CHECK32-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
28113 // CHECK32-NEXT:    [[MUL51:%.*]] = mul i64 4, [[TMP34]]
28114 // CHECK32-NEXT:    [[ADD52:%.*]] = add i64 [[CONV50]], [[MUL51]]
28115 // CHECK32-NEXT:    [[CONV53:%.*]] = trunc i64 [[ADD52]] to i32
28116 // CHECK32-NEXT:    store i32 [[CONV53]], i32* [[LIN]], align 4
28117 // CHECK32-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTLINEAR_START26]], align 4
28118 // CHECK32-NEXT:    [[CONV54:%.*]] = sext i32 [[TMP35]] to i64
28119 // CHECK32-NEXT:    [[TMP36:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
28120 // CHECK32-NEXT:    [[MUL55:%.*]] = mul i64 4, [[TMP36]]
28121 // CHECK32-NEXT:    [[ADD56:%.*]] = add i64 [[CONV54]], [[MUL55]]
28122 // CHECK32-NEXT:    [[CONV57:%.*]] = trunc i64 [[ADD56]] to i32
28123 // CHECK32-NEXT:    store i32 [[CONV57]], i32* [[A]], align 4
28124 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB59]], align 4
28125 // CHECK32-NEXT:    store i32 3, i32* [[DOTOMP_UB60]], align 4
28126 // CHECK32-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB59]], align 4
28127 // CHECK32-NEXT:    store i32 [[TMP37]], i32* [[DOTOMP_IV61]], align 4
28128 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND63:%.*]]
28129 // CHECK32:       omp.inner.for.cond63:
28130 // CHECK32-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
28131 // CHECK32-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB60]], align 4, !llvm.access.group !13
28132 // CHECK32-NEXT:    [[CMP64:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]]
28133 // CHECK32-NEXT:    br i1 [[CMP64]], label [[OMP_INNER_FOR_BODY65:%.*]], label [[OMP_INNER_FOR_END76:%.*]]
28134 // CHECK32:       omp.inner.for.body65:
28135 // CHECK32-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
28136 // CHECK32-NEXT:    [[MUL66:%.*]] = mul nsw i32 [[TMP40]], 4
28137 // CHECK32-NEXT:    [[ADD67:%.*]] = add nsw i32 6, [[MUL66]]
28138 // CHECK32-NEXT:    [[CONV68:%.*]] = trunc i32 [[ADD67]] to i16
28139 // CHECK32-NEXT:    store i16 [[CONV68]], i16* [[IT62]], align 2, !llvm.access.group !13
28140 // CHECK32-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
28141 // CHECK32-NEXT:    [[ADD69:%.*]] = add nsw i32 [[TMP41]], 1
28142 // CHECK32-NEXT:    store i32 [[ADD69]], i32* [[A]], align 4, !llvm.access.group !13
28143 // CHECK32-NEXT:    [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
28144 // CHECK32-NEXT:    [[CONV70:%.*]] = sext i16 [[TMP42]] to i32
28145 // CHECK32-NEXT:    [[ADD71:%.*]] = add nsw i32 [[CONV70]], 1
28146 // CHECK32-NEXT:    [[CONV72:%.*]] = trunc i32 [[ADD71]] to i16
28147 // CHECK32-NEXT:    store i16 [[CONV72]], i16* [[AA]], align 2, !llvm.access.group !13
28148 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE73:%.*]]
28149 // CHECK32:       omp.body.continue73:
28150 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC74:%.*]]
28151 // CHECK32:       omp.inner.for.inc74:
28152 // CHECK32-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
28153 // CHECK32-NEXT:    [[ADD75:%.*]] = add nsw i32 [[TMP43]], 1
28154 // CHECK32-NEXT:    store i32 [[ADD75]], i32* [[DOTOMP_IV61]], align 4, !llvm.access.group !13
28155 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND63]], !llvm.loop [[LOOP14:![0-9]+]]
28156 // CHECK32:       omp.inner.for.end76:
28157 // CHECK32-NEXT:    store i16 22, i16* [[IT62]], align 2
28158 // CHECK32-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
28159 // CHECK32-NEXT:    store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4
28160 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB78]], align 4
28161 // CHECK32-NEXT:    store i32 25, i32* [[DOTOMP_UB79]], align 4
28162 // CHECK32-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB78]], align 4
28163 // CHECK32-NEXT:    store i32 [[TMP45]], i32* [[DOTOMP_IV80]], align 4
28164 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND82:%.*]]
28165 // CHECK32:       omp.inner.for.cond82:
28166 // CHECK32-NEXT:    [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
28167 // CHECK32-NEXT:    [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB79]], align 4, !llvm.access.group !16
28168 // CHECK32-NEXT:    [[CMP83:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]]
28169 // CHECK32-NEXT:    br i1 [[CMP83]], label [[OMP_INNER_FOR_BODY84:%.*]], label [[OMP_INNER_FOR_END109:%.*]]
28170 // CHECK32:       omp.inner.for.body84:
28171 // CHECK32-NEXT:    [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
28172 // CHECK32-NEXT:    [[MUL85:%.*]] = mul nsw i32 [[TMP48]], 1
28173 // CHECK32-NEXT:    [[SUB86:%.*]] = sub nsw i32 122, [[MUL85]]
28174 // CHECK32-NEXT:    [[CONV87:%.*]] = trunc i32 [[SUB86]] to i8
28175 // CHECK32-NEXT:    store i8 [[CONV87]], i8* [[IT81]], align 1, !llvm.access.group !16
28176 // CHECK32-NEXT:    [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
28177 // CHECK32-NEXT:    [[ADD88:%.*]] = add nsw i32 [[TMP49]], 1
28178 // CHECK32-NEXT:    store i32 [[ADD88]], i32* [[A]], align 4, !llvm.access.group !16
28179 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
28180 // CHECK32-NEXT:    [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
28181 // CHECK32-NEXT:    [[CONV89:%.*]] = fpext float [[TMP50]] to double
28182 // CHECK32-NEXT:    [[ADD90:%.*]] = fadd double [[CONV89]], 1.000000e+00
28183 // CHECK32-NEXT:    [[CONV91:%.*]] = fptrunc double [[ADD90]] to float
28184 // CHECK32-NEXT:    store float [[CONV91]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
28185 // CHECK32-NEXT:    [[ARRAYIDX92:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
28186 // CHECK32-NEXT:    [[TMP51:%.*]] = load float, float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
28187 // CHECK32-NEXT:    [[CONV93:%.*]] = fpext float [[TMP51]] to double
28188 // CHECK32-NEXT:    [[ADD94:%.*]] = fadd double [[CONV93]], 1.000000e+00
28189 // CHECK32-NEXT:    [[CONV95:%.*]] = fptrunc double [[ADD94]] to float
28190 // CHECK32-NEXT:    store float [[CONV95]], float* [[ARRAYIDX92]], align 4, !llvm.access.group !16
28191 // CHECK32-NEXT:    [[ARRAYIDX96:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
28192 // CHECK32-NEXT:    [[ARRAYIDX97:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX96]], i32 0, i32 2
28193 // CHECK32-NEXT:    [[TMP52:%.*]] = load double, double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
28194 // CHECK32-NEXT:    [[ADD98:%.*]] = fadd double [[TMP52]], 1.000000e+00
28195 // CHECK32-NEXT:    store double [[ADD98]], double* [[ARRAYIDX97]], align 8, !llvm.access.group !16
28196 // CHECK32-NEXT:    [[TMP53:%.*]] = mul nsw i32 1, [[TMP2]]
28197 // CHECK32-NEXT:    [[ARRAYIDX99:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP53]]
28198 // CHECK32-NEXT:    [[ARRAYIDX100:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX99]], i32 3
28199 // CHECK32-NEXT:    [[TMP54:%.*]] = load double, double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
28200 // CHECK32-NEXT:    [[ADD101:%.*]] = fadd double [[TMP54]], 1.000000e+00
28201 // CHECK32-NEXT:    store double [[ADD101]], double* [[ARRAYIDX100]], align 8, !llvm.access.group !16
28202 // CHECK32-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
28203 // CHECK32-NEXT:    [[TMP55:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
28204 // CHECK32-NEXT:    [[ADD102:%.*]] = add nsw i64 [[TMP55]], 1
28205 // CHECK32-NEXT:    store i64 [[ADD102]], i64* [[X]], align 4, !llvm.access.group !16
28206 // CHECK32-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
28207 // CHECK32-NEXT:    [[TMP56:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
28208 // CHECK32-NEXT:    [[CONV103:%.*]] = sext i8 [[TMP56]] to i32
28209 // CHECK32-NEXT:    [[ADD104:%.*]] = add nsw i32 [[CONV103]], 1
28210 // CHECK32-NEXT:    [[CONV105:%.*]] = trunc i32 [[ADD104]] to i8
28211 // CHECK32-NEXT:    store i8 [[CONV105]], i8* [[Y]], align 4, !llvm.access.group !16
28212 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE106:%.*]]
28213 // CHECK32:       omp.body.continue106:
28214 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC107:%.*]]
28215 // CHECK32:       omp.inner.for.inc107:
28216 // CHECK32-NEXT:    [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
28217 // CHECK32-NEXT:    [[ADD108:%.*]] = add nsw i32 [[TMP57]], 1
28218 // CHECK32-NEXT:    store i32 [[ADD108]], i32* [[DOTOMP_IV80]], align 4, !llvm.access.group !16
28219 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND82]], !llvm.loop [[LOOP17:![0-9]+]]
28220 // CHECK32:       omp.inner.for.end109:
28221 // CHECK32-NEXT:    store i8 96, i8* [[IT81]], align 1
28222 // CHECK32-NEXT:    [[TMP58:%.*]] = load i32, i32* [[A]], align 4
28223 // CHECK32-NEXT:    [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
28224 // CHECK32-NEXT:    call void @llvm.stackrestore(i8* [[TMP59]])
28225 // CHECK32-NEXT:    ret i32 [[TMP58]]
28226 //
28227 //
28228 // CHECK32-LABEL: define {{[^@]+}}@_Z3bari
28229 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
28230 // CHECK32-NEXT:  entry:
28231 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28232 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
28233 // CHECK32-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
28234 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28235 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
28236 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
28237 // CHECK32-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
28238 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
28239 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
28240 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
28241 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
28242 // CHECK32-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
28243 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
28244 // CHECK32-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
28245 // CHECK32-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
28246 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
28247 // CHECK32-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
28248 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
28249 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
28250 // CHECK32-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
28251 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
28252 // CHECK32-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
28253 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
28254 // CHECK32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
28255 // CHECK32-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
28256 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
28257 // CHECK32-NEXT:    ret i32 [[TMP8]]
28258 //
28259 //
28260 // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
28261 // CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
28262 // CHECK32-NEXT:  entry:
28263 // CHECK32-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
28264 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28265 // CHECK32-NEXT:    [[B:%.*]] = alloca i32, align 4
28266 // CHECK32-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
28267 // CHECK32-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
28268 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
28269 // CHECK32-NEXT:    [[TMP:%.*]] = alloca i64, align 4
28270 // CHECK32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
28271 // CHECK32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
28272 // CHECK32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
28273 // CHECK32-NEXT:    [[IT:%.*]] = alloca i64, align 8
28274 // CHECK32-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
28275 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28276 // CHECK32-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
28277 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
28278 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
28279 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
28280 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
28281 // CHECK32-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
28282 // CHECK32-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
28283 // CHECK32-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
28284 // CHECK32-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
28285 // CHECK32-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
28286 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
28287 // CHECK32-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
28288 // CHECK32-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
28289 // CHECK32-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
28290 // CHECK32-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
28291 // CHECK32-NEXT:    store i64 3, i64* [[DOTOMP_UB]], align 8
28292 // CHECK32-NEXT:    [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
28293 // CHECK32-NEXT:    store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
28294 // CHECK32-NEXT:    [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
28295 // CHECK32-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
28296 // CHECK32-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
28297 // CHECK32:       omp_if.then:
28298 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
28299 // CHECK32:       omp.inner.for.cond:
28300 // CHECK32-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
28301 // CHECK32-NEXT:    [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19
28302 // CHECK32-NEXT:    [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
28303 // CHECK32-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28304 // CHECK32:       omp.inner.for.body:
28305 // CHECK32-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
28306 // CHECK32-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
28307 // CHECK32-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
28308 // CHECK32-NEXT:    store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19
28309 // CHECK32-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
28310 // CHECK32-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
28311 // CHECK32-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
28312 // CHECK32-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
28313 // CHECK32-NEXT:    store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19
28314 // CHECK32-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
28315 // CHECK32-NEXT:    [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
28316 // CHECK32-NEXT:    [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
28317 // CHECK32-NEXT:    store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19
28318 // CHECK32-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
28319 // CHECK32-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
28320 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
28321 // CHECK32-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
28322 // CHECK32-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
28323 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28324 // CHECK32:       omp.body.continue:
28325 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28326 // CHECK32:       omp.inner.for.inc:
28327 // CHECK32-NEXT:    [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
28328 // CHECK32-NEXT:    [[ADD7:%.*]] = add i64 [[TMP13]], 1
28329 // CHECK32-NEXT:    store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19
28330 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
28331 // CHECK32:       omp.inner.for.end:
28332 // CHECK32-NEXT:    br label [[OMP_IF_END:%.*]]
28333 // CHECK32:       omp_if.else:
28334 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND8:%.*]]
28335 // CHECK32:       omp.inner.for.cond8:
28336 // CHECK32-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
28337 // CHECK32-NEXT:    [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
28338 // CHECK32-NEXT:    [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]]
28339 // CHECK32-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]]
28340 // CHECK32:       omp.inner.for.body10:
28341 // CHECK32-NEXT:    [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
28342 // CHECK32-NEXT:    [[MUL11:%.*]] = mul i64 [[TMP16]], 400
28343 // CHECK32-NEXT:    [[SUB12:%.*]] = sub i64 2000, [[MUL11]]
28344 // CHECK32-NEXT:    store i64 [[SUB12]], i64* [[IT]], align 8
28345 // CHECK32-NEXT:    [[TMP17:%.*]] = load i32, i32* [[B]], align 4
28346 // CHECK32-NEXT:    [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double
28347 // CHECK32-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00
28348 // CHECK32-NEXT:    [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
28349 // CHECK32-NEXT:    store double [[ADD14]], double* [[A15]], align 4
28350 // CHECK32-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
28351 // CHECK32-NEXT:    [[TMP18:%.*]] = load double, double* [[A16]], align 4
28352 // CHECK32-NEXT:    [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00
28353 // CHECK32-NEXT:    store double [[INC17]], double* [[A16]], align 4
28354 // CHECK32-NEXT:    [[CONV18:%.*]] = fptosi double [[INC17]] to i16
28355 // CHECK32-NEXT:    [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
28356 // CHECK32-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
28357 // CHECK32-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1
28358 // CHECK32-NEXT:    store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2
28359 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE21:%.*]]
28360 // CHECK32:       omp.body.continue21:
28361 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC22:%.*]]
28362 // CHECK32:       omp.inner.for.inc22:
28363 // CHECK32-NEXT:    [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
28364 // CHECK32-NEXT:    [[ADD23:%.*]] = add i64 [[TMP20]], 1
28365 // CHECK32-NEXT:    store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8
28366 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]]
28367 // CHECK32:       omp.inner.for.end24:
28368 // CHECK32-NEXT:    br label [[OMP_IF_END]]
28369 // CHECK32:       omp_if.end:
28370 // CHECK32-NEXT:    store i64 400, i64* [[IT]], align 8
28371 // CHECK32-NEXT:    [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
28372 // CHECK32-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
28373 // CHECK32-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1
28374 // CHECK32-NEXT:    [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2
28375 // CHECK32-NEXT:    [[CONV27:%.*]] = sext i16 [[TMP22]] to i32
28376 // CHECK32-NEXT:    [[TMP23:%.*]] = load i32, i32* [[B]], align 4
28377 // CHECK32-NEXT:    [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]]
28378 // CHECK32-NEXT:    [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
28379 // CHECK32-NEXT:    call void @llvm.stackrestore(i8* [[TMP24]])
28380 // CHECK32-NEXT:    ret i32 [[ADD28]]
28381 //
28382 //
28383 // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici
28384 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
28385 // CHECK32-NEXT:  entry:
28386 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28387 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
28388 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
28389 // CHECK32-NEXT:    [[AAA:%.*]] = alloca i8, align 1
28390 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
28391 // CHECK32-NEXT:    [[TMP:%.*]] = alloca i32, align 4
28392 // CHECK32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
28393 // CHECK32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
28394 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28395 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
28396 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
28397 // CHECK32-NEXT:    store i8 0, i8* [[AAA]], align 1
28398 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
28399 // CHECK32-NEXT:    store i32 429496720, i32* [[DOTOMP_UB]], align 4
28400 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
28401 // CHECK32-NEXT:    ret i32 [[TMP0]]
28402 //
28403 //
28404 // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
28405 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
28406 // CHECK32-NEXT:  entry:
28407 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28408 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
28409 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
28410 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
28411 // CHECK32-NEXT:    [[TMP:%.*]] = alloca i64, align 4
28412 // CHECK32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
28413 // CHECK32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
28414 // CHECK32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
28415 // CHECK32-NEXT:    [[I:%.*]] = alloca i64, align 8
28416 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28417 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
28418 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
28419 // CHECK32-NEXT:    store i64 0, i64* [[DOTOMP_LB]], align 8
28420 // CHECK32-NEXT:    store i64 6, i64* [[DOTOMP_UB]], align 8
28421 // CHECK32-NEXT:    [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
28422 // CHECK32-NEXT:    store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8
28423 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
28424 // CHECK32:       omp.inner.for.cond:
28425 // CHECK32-NEXT:    [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
28426 // CHECK32-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25
28427 // CHECK32-NEXT:    [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]]
28428 // CHECK32-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28429 // CHECK32:       omp.inner.for.body:
28430 // CHECK32-NEXT:    [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
28431 // CHECK32-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3
28432 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
28433 // CHECK32-NEXT:    store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25
28434 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
28435 // CHECK32-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
28436 // CHECK32-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
28437 // CHECK32-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
28438 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
28439 // CHECK32-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
28440 // CHECK32-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
28441 // CHECK32-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
28442 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
28443 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
28444 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
28445 // CHECK32-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
28446 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28447 // CHECK32:       omp.body.continue:
28448 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28449 // CHECK32:       omp.inner.for.inc:
28450 // CHECK32-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
28451 // CHECK32-NEXT:    [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1
28452 // CHECK32-NEXT:    store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25
28453 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
28454 // CHECK32:       omp.inner.for.end:
28455 // CHECK32-NEXT:    store i64 11, i64* [[I]], align 8
28456 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
28457 // CHECK32-NEXT:    ret i32 [[TMP8]]
28458 //
28459