1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
5 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
8
9 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6
12 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8
15
16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
17 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
19 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
20 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
22
23 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
24 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
25 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
26 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
27 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
28 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
29
30 // expected-no-diagnostics
31 #ifndef HEADER
32 #define HEADER
33
34 template <class T>
35 struct S {
36 T f;
SS37 S(T a) : f(a) {}
SS38 S() : f() {}
operator TS39 operator T() { return T(); }
~SS40 ~S() {}
41 };
42
43 template <typename T>
tmain()44 T tmain() {
45 S<T> test;
46 T t_var = T();
47 T vec[] = {1, 2};
48 S<T> s_arr[] = {1, 2};
49 S<T> &var = test;
50 #pragma omp target teams distribute parallel for lastprivate(t_var, vec, s_arr, s_arr, var, var)
51 for (int i = 0; i < 2; ++i) {
52 vec[i] = t_var;
53 s_arr[i] = var;
54 }
55 return T();
56 }
57
main()58 int main() {
59 static int svar;
60 volatile double g;
61 volatile double &g1 = g;
62
63 #ifdef LAMBDA
64 [&]() {
65 static float sfvar;
66
67 #pragma omp target teams distribute parallel for lastprivate(g, g1, svar, sfvar)
68 for (int i = 0; i < 2; ++i) {
69 // skip gbl and bound tid
70 // loop variables
71
72
73
74 g1 = 1;
75 svar = 3;
76 sfvar = 4.0;
77
78
79
80 // skip tid and prev variables
81 // loop variables
82
83
84
85
86
87
88
89 [&]() {
90 g = 2;
91 g1 = 2;
92 svar = 4;
93 sfvar = 8.0;
94
95 }();
96 }
97 }();
98 return 0;
99 #else
100 S<float> test;
101 int t_var = 0;
102 int vec[] = {1, 2};
103 S<float> s_arr[] = {1, 2};
104 S<float> &var = test;
105
106 #pragma omp target teams distribute parallel for lastprivate(t_var, vec, s_arr, s_arr, var, var, svar)
107 for (int i = 0; i < 2; ++i) {
108 vec[i] = t_var;
109 s_arr[i] = var;
110 }
111 int i;
112
113 return tmain<int>();
114 #endif
115 }
116
117
118 // skip loop variables
119
120 // copy from parameters to local address variables
121
122 // prepare lastprivate targets
123
124 // the distribute loop
125
126 // lastprivates
127
128
129
130 // gbl and bound tid vars, prev lb and ub vars
131
132 // skip loop variables
133
134 // copy from parameters to local address variables
135
136 // prepare lastprivate targets
137
138 // the distribute loop
139 // skip body: code generation routine is same as distribute parallel for lastprivate
140
141 // lastprivates
142
143
144 // template tmain
145
146
147 // skip alloca of global_tid and bound_tid
148 // skip loop variables
149
150 // copy from parameters to local address variables
151
152 // prepare lastprivate targets
153
154
155 // lastprivates
156
157
158 // skip alloca of global_tid and bound_tid, and prev lb and ub vars
159
160 // skip loop variables
161
162 // copy from parameters to local address variables
163
164 // prepare lastprivate targets
165
166 // skip body: code generation routine is same as distribute parallel for lastprivate
167
168 // lastprivates
169
170
171 #endif
172 // CHECK1-LABEL: define {{[^@]+}}@main
173 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
174 // CHECK1-NEXT: entry:
175 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
176 // CHECK1-NEXT: [[G:%.*]] = alloca double, align 8
177 // CHECK1-NEXT: [[G1:%.*]] = alloca double*, align 8
178 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
179 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
180 // CHECK1-NEXT: store double* [[G]], double** [[G1]], align 8
181 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
182 // CHECK1-NEXT: store double* [[G]], double** [[TMP0]], align 8
183 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
184 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8
185 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8
186 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]])
187 // CHECK1-NEXT: ret i32 0
188 //
189 //
190 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
191 // CHECK1-SAME: (i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2:[0-9]+]] {
192 // CHECK1-NEXT: entry:
193 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
194 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
195 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
196 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
197 // CHECK1-NEXT: [[TMP:%.*]] = alloca double*, align 8
198 // CHECK1-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
199 // CHECK1-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
200 // CHECK1-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8
201 // CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
202 // CHECK1-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
203 // CHECK1-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
204 // CHECK1-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8
205 // CHECK1-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
206 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to double*
207 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
208 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
209 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
210 // CHECK1-NEXT: store double* [[CONV]], double** [[TMP]], align 8
211 // CHECK1-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8
212 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8
213 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
214 // CHECK1-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
215 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
216 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
217 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
218 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
219 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
220 // CHECK1-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 8
221 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
222 // CHECK1-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
223 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
224 // CHECK1-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8
225 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double*
226 // CHECK1-NEXT: store double [[TMP7]], double* [[CONV7]], align 8
227 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8
228 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
229 // CHECK1-NEXT: ret void
230 //
231 //
232 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
233 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] {
234 // CHECK1-NEXT: entry:
235 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
236 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
237 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
238 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
239 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
240 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
241 // CHECK1-NEXT: [[TMP:%.*]] = alloca double*, align 8
242 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
243 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
244 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
245 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
246 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
247 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
248 // CHECK1-NEXT: [[G5:%.*]] = alloca double, align 8
249 // CHECK1-NEXT: [[G16:%.*]] = alloca double, align 8
250 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca double*, align 8
251 // CHECK1-NEXT: [[SVAR8:%.*]] = alloca i32, align 4
252 // CHECK1-NEXT: [[SFVAR9:%.*]] = alloca float, align 4
253 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
254 // CHECK1-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
255 // CHECK1-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
256 // CHECK1-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8
257 // CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
258 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
259 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
260 // CHECK1-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
261 // CHECK1-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
262 // CHECK1-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8
263 // CHECK1-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
264 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to double*
265 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
266 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
267 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
268 // CHECK1-NEXT: store double* [[CONV]], double** [[TMP]], align 8
269 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
270 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
271 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
272 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
273 // CHECK1-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8
274 // CHECK1-NEXT: store double* [[G16]], double** [[_TMP7]], align 8
275 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
276 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
277 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
278 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
279 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
280 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
281 // CHECK1: cond.true:
282 // CHECK1-NEXT: br label [[COND_END:%.*]]
283 // CHECK1: cond.false:
284 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
285 // CHECK1-NEXT: br label [[COND_END]]
286 // CHECK1: cond.end:
287 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
288 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
289 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
290 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
291 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
292 // CHECK1: omp.inner.for.cond:
293 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
294 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
295 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
296 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
297 // CHECK1: omp.inner.for.body:
298 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
299 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
300 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
301 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
302 // CHECK1-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP7]], align 8
303 // CHECK1-NEXT: [[TMP13:%.*]] = load volatile double, double* [[TMP12]], align 8
304 // CHECK1-NEXT: [[CONV11:%.*]] = bitcast i64* [[G1_CASTED]] to double*
305 // CHECK1-NEXT: store double [[TMP13]], double* [[CONV11]], align 8
306 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[G1_CASTED]], align 8
307 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[SVAR8]], align 4
308 // CHECK1-NEXT: [[CONV12:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
309 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[CONV12]], align 4
310 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
311 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[SFVAR9]], align 4
312 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
313 // CHECK1-NEXT: store float [[TMP17]], float* [[CONV13]], align 4
314 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
315 // CHECK1-NEXT: [[TMP19:%.*]] = load double, double* [[G5]], align 8
316 // CHECK1-NEXT: [[CONV14:%.*]] = bitcast i64* [[G_CASTED]] to double*
317 // CHECK1-NEXT: store double [[TMP19]], double* [[CONV14]], align 8
318 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[G_CASTED]], align 8
319 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]])
320 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
321 // CHECK1: omp.inner.for.inc:
322 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
323 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
324 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
325 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
326 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
327 // CHECK1: omp.inner.for.end:
328 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
329 // CHECK1: omp.loop.exit:
330 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
331 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
332 // CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
333 // CHECK1-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
334 // CHECK1: .omp.lastprivate.then:
335 // CHECK1-NEXT: [[TMP25:%.*]] = load double, double* [[G5]], align 8
336 // CHECK1-NEXT: store volatile double [[TMP25]], double* [[CONV3]], align 8
337 // CHECK1-NEXT: [[TMP26:%.*]] = load double*, double** [[_TMP7]], align 8
338 // CHECK1-NEXT: [[TMP27:%.*]] = load double, double* [[TMP26]], align 8
339 // CHECK1-NEXT: store volatile double [[TMP27]], double* [[TMP0]], align 8
340 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[SVAR8]], align 4
341 // CHECK1-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 8
342 // CHECK1-NEXT: [[TMP29:%.*]] = load float, float* [[SFVAR9]], align 4
343 // CHECK1-NEXT: store float [[TMP29]], float* [[CONV2]], align 8
344 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
345 // CHECK1: .omp.lastprivate.done:
346 // CHECK1-NEXT: ret void
347 //
348 //
349 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
350 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] {
351 // CHECK1-NEXT: entry:
352 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
353 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
354 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
355 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
356 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
357 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
358 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
359 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
360 // CHECK1-NEXT: [[TMP:%.*]] = alloca double*, align 8
361 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
362 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
363 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
364 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
365 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
366 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
367 // CHECK1-NEXT: [[G7:%.*]] = alloca double, align 8
368 // CHECK1-NEXT: [[G18:%.*]] = alloca double, align 8
369 // CHECK1-NEXT: [[_TMP9:%.*]] = alloca double*, align 8
370 // CHECK1-NEXT: [[SVAR10:%.*]] = alloca i32, align 4
371 // CHECK1-NEXT: [[SFVAR11:%.*]] = alloca float, align 4
372 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
373 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
374 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
375 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
376 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
377 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
378 // CHECK1-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
379 // CHECK1-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
380 // CHECK1-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8
381 // CHECK1-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
382 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to double*
383 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
384 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
385 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
386 // CHECK1-NEXT: store double* [[CONV]], double** [[TMP]], align 8
387 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
388 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
389 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
390 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP0]] to i32
391 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
392 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP1]] to i32
393 // CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
394 // CHECK1-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
395 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
396 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
397 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8
398 // CHECK1-NEXT: store double* [[G18]], double** [[_TMP9]], align 8
399 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
400 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
401 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
402 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
403 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
404 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
405 // CHECK1: cond.true:
406 // CHECK1-NEXT: br label [[COND_END:%.*]]
407 // CHECK1: cond.false:
408 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
409 // CHECK1-NEXT: br label [[COND_END]]
410 // CHECK1: cond.end:
411 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
412 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
413 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
414 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
415 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
416 // CHECK1: omp.inner.for.cond:
417 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
418 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
419 // CHECK1-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
420 // CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
421 // CHECK1: omp.inner.for.body:
422 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
423 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
424 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
425 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
426 // CHECK1-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP9]], align 8
427 // CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP11]], align 8
428 // CHECK1-NEXT: store i32 3, i32* [[SVAR10]], align 4
429 // CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR11]], align 4
430 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
431 // CHECK1-NEXT: store double* [[G7]], double** [[TMP12]], align 8
432 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
433 // CHECK1-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP9]], align 8
434 // CHECK1-NEXT: store double* [[TMP14]], double** [[TMP13]], align 8
435 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
436 // CHECK1-NEXT: store i32* [[SVAR10]], i32** [[TMP15]], align 8
437 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
438 // CHECK1-NEXT: store float* [[SFVAR11]], float** [[TMP16]], align 8
439 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])
440 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
441 // CHECK1: omp.body.continue:
442 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
443 // CHECK1: omp.inner.for.inc:
444 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
445 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], 1
446 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
447 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
448 // CHECK1: omp.inner.for.end:
449 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
450 // CHECK1: omp.loop.exit:
451 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
452 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
453 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
454 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
455 // CHECK1: .omp.lastprivate.then:
456 // CHECK1-NEXT: [[TMP20:%.*]] = load double, double* [[G7]], align 8
457 // CHECK1-NEXT: store volatile double [[TMP20]], double* [[CONV3]], align 8
458 // CHECK1-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP9]], align 8
459 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
460 // CHECK1-NEXT: store volatile double [[TMP22]], double* [[TMP2]], align 8
461 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR10]], align 4
462 // CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 8
463 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR11]], align 4
464 // CHECK1-NEXT: store float [[TMP24]], float* [[CONV2]], align 8
465 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
466 // CHECK1: .omp.lastprivate.done:
467 // CHECK1-NEXT: ret void
468 //
469 //
470 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
471 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
472 // CHECK1-NEXT: entry:
473 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
474 // CHECK1-NEXT: ret void
475 //
476 //
477 // CHECK2-LABEL: define {{[^@]+}}@main
478 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
479 // CHECK2-NEXT: entry:
480 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
481 // CHECK2-NEXT: [[G:%.*]] = alloca double, align 8
482 // CHECK2-NEXT: [[G1:%.*]] = alloca double*, align 8
483 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
484 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
485 // CHECK2-NEXT: store double* [[G]], double** [[G1]], align 8
486 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
487 // CHECK2-NEXT: store double* [[G]], double** [[TMP0]], align 8
488 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
489 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8
490 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8
491 // CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]])
492 // CHECK2-NEXT: ret i32 0
493 //
494 //
495 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
496 // CHECK2-SAME: (i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2:[0-9]+]] {
497 // CHECK2-NEXT: entry:
498 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
499 // CHECK2-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
500 // CHECK2-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
501 // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
502 // CHECK2-NEXT: [[TMP:%.*]] = alloca double*, align 8
503 // CHECK2-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
504 // CHECK2-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
505 // CHECK2-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8
506 // CHECK2-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
507 // CHECK2-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
508 // CHECK2-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
509 // CHECK2-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8
510 // CHECK2-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
511 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to double*
512 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
513 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
514 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
515 // CHECK2-NEXT: store double* [[CONV]], double** [[TMP]], align 8
516 // CHECK2-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8
517 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile double, double* [[TMP0]], align 8
518 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to double*
519 // CHECK2-NEXT: store double [[TMP1]], double* [[CONV4]], align 8
520 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[G1_CASTED]], align 8
521 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
522 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
523 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4
524 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
525 // CHECK2-NEXT: [[TMP5:%.*]] = load float, float* [[CONV2]], align 8
526 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
527 // CHECK2-NEXT: store float [[TMP5]], float* [[CONV6]], align 4
528 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
529 // CHECK2-NEXT: [[TMP7:%.*]] = load double, double* [[CONV3]], align 8
530 // CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[G_CASTED]] to double*
531 // CHECK2-NEXT: store double [[TMP7]], double* [[CONV7]], align 8
532 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[G_CASTED]], align 8
533 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
534 // CHECK2-NEXT: ret void
535 //
536 //
537 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
538 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] {
539 // CHECK2-NEXT: entry:
540 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
541 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
542 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
543 // CHECK2-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
544 // CHECK2-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
545 // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
546 // CHECK2-NEXT: [[TMP:%.*]] = alloca double*, align 8
547 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
548 // CHECK2-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
549 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
550 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
551 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
552 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
553 // CHECK2-NEXT: [[G5:%.*]] = alloca double, align 8
554 // CHECK2-NEXT: [[G16:%.*]] = alloca double, align 8
555 // CHECK2-NEXT: [[_TMP7:%.*]] = alloca double*, align 8
556 // CHECK2-NEXT: [[SVAR8:%.*]] = alloca i32, align 4
557 // CHECK2-NEXT: [[SFVAR9:%.*]] = alloca float, align 4
558 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
559 // CHECK2-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
560 // CHECK2-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
561 // CHECK2-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8
562 // CHECK2-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
563 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
564 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
565 // CHECK2-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
566 // CHECK2-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
567 // CHECK2-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8
568 // CHECK2-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
569 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to double*
570 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
571 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
572 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
573 // CHECK2-NEXT: store double* [[CONV]], double** [[TMP]], align 8
574 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
575 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
576 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
577 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
578 // CHECK2-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8
579 // CHECK2-NEXT: store double* [[G16]], double** [[_TMP7]], align 8
580 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
581 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
582 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
583 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
584 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
585 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
586 // CHECK2: cond.true:
587 // CHECK2-NEXT: br label [[COND_END:%.*]]
588 // CHECK2: cond.false:
589 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
590 // CHECK2-NEXT: br label [[COND_END]]
591 // CHECK2: cond.end:
592 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
593 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
594 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
595 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
596 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
597 // CHECK2: omp.inner.for.cond:
598 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
599 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
600 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
601 // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
602 // CHECK2: omp.inner.for.body:
603 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
604 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
605 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
606 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
607 // CHECK2-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP7]], align 8
608 // CHECK2-NEXT: [[TMP13:%.*]] = load volatile double, double* [[TMP12]], align 8
609 // CHECK2-NEXT: [[CONV11:%.*]] = bitcast i64* [[G1_CASTED]] to double*
610 // CHECK2-NEXT: store double [[TMP13]], double* [[CONV11]], align 8
611 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[G1_CASTED]], align 8
612 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[SVAR8]], align 4
613 // CHECK2-NEXT: [[CONV12:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
614 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[CONV12]], align 4
615 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
616 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[SFVAR9]], align 4
617 // CHECK2-NEXT: [[CONV13:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float*
618 // CHECK2-NEXT: store float [[TMP17]], float* [[CONV13]], align 4
619 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8
620 // CHECK2-NEXT: [[TMP19:%.*]] = load double, double* [[G5]], align 8
621 // CHECK2-NEXT: [[CONV14:%.*]] = bitcast i64* [[G_CASTED]] to double*
622 // CHECK2-NEXT: store double [[TMP19]], double* [[CONV14]], align 8
623 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[G_CASTED]], align 8
624 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]])
625 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
626 // CHECK2: omp.inner.for.inc:
627 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
628 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
629 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
630 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
631 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
632 // CHECK2: omp.inner.for.end:
633 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
634 // CHECK2: omp.loop.exit:
635 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
636 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
637 // CHECK2-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
638 // CHECK2-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
639 // CHECK2: .omp.lastprivate.then:
640 // CHECK2-NEXT: [[TMP25:%.*]] = load double, double* [[G5]], align 8
641 // CHECK2-NEXT: store volatile double [[TMP25]], double* [[CONV3]], align 8
642 // CHECK2-NEXT: [[TMP26:%.*]] = load double*, double** [[_TMP7]], align 8
643 // CHECK2-NEXT: [[TMP27:%.*]] = load double, double* [[TMP26]], align 8
644 // CHECK2-NEXT: store volatile double [[TMP27]], double* [[TMP0]], align 8
645 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[SVAR8]], align 4
646 // CHECK2-NEXT: store i32 [[TMP28]], i32* [[CONV1]], align 8
647 // CHECK2-NEXT: [[TMP29:%.*]] = load float, float* [[SFVAR9]], align 4
648 // CHECK2-NEXT: store float [[TMP29]], float* [[CONV2]], align 8
649 // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
650 // CHECK2: .omp.lastprivate.done:
651 // CHECK2-NEXT: ret void
652 //
653 //
654 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
655 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] {
656 // CHECK2-NEXT: entry:
657 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
658 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
659 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
660 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
661 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
662 // CHECK2-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
663 // CHECK2-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
664 // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
665 // CHECK2-NEXT: [[TMP:%.*]] = alloca double*, align 8
666 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
667 // CHECK2-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
668 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
669 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
670 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
671 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
672 // CHECK2-NEXT: [[G7:%.*]] = alloca double, align 8
673 // CHECK2-NEXT: [[G18:%.*]] = alloca double, align 8
674 // CHECK2-NEXT: [[_TMP9:%.*]] = alloca double*, align 8
675 // CHECK2-NEXT: [[SVAR10:%.*]] = alloca i32, align 4
676 // CHECK2-NEXT: [[SFVAR11:%.*]] = alloca float, align 4
677 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
678 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
679 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
680 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
681 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
682 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
683 // CHECK2-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
684 // CHECK2-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
685 // CHECK2-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8
686 // CHECK2-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
687 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to double*
688 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
689 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float*
690 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_ADDR]] to double*
691 // CHECK2-NEXT: store double* [[CONV]], double** [[TMP]], align 8
692 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
693 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
694 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
695 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP0]] to i32
696 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
697 // CHECK2-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP1]] to i32
698 // CHECK2-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
699 // CHECK2-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
700 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
701 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
702 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 8
703 // CHECK2-NEXT: store double* [[G18]], double** [[_TMP9]], align 8
704 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
705 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
706 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
707 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
708 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
709 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
710 // CHECK2: cond.true:
711 // CHECK2-NEXT: br label [[COND_END:%.*]]
712 // CHECK2: cond.false:
713 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
714 // CHECK2-NEXT: br label [[COND_END]]
715 // CHECK2: cond.end:
716 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
717 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
718 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
719 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
720 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
721 // CHECK2: omp.inner.for.cond:
722 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
723 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
724 // CHECK2-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
725 // CHECK2-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
726 // CHECK2: omp.inner.for.body:
727 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
728 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
729 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
730 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
731 // CHECK2-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP9]], align 8
732 // CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP11]], align 8
733 // CHECK2-NEXT: store i32 3, i32* [[SVAR10]], align 4
734 // CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR11]], align 4
735 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
736 // CHECK2-NEXT: store double* [[G7]], double** [[TMP12]], align 8
737 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
738 // CHECK2-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP9]], align 8
739 // CHECK2-NEXT: store double* [[TMP14]], double** [[TMP13]], align 8
740 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
741 // CHECK2-NEXT: store i32* [[SVAR10]], i32** [[TMP15]], align 8
742 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
743 // CHECK2-NEXT: store float* [[SFVAR11]], float** [[TMP16]], align 8
744 // CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]])
745 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
746 // CHECK2: omp.body.continue:
747 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
748 // CHECK2: omp.inner.for.inc:
749 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
750 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], 1
751 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
752 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
753 // CHECK2: omp.inner.for.end:
754 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
755 // CHECK2: omp.loop.exit:
756 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
757 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
758 // CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
759 // CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
760 // CHECK2: .omp.lastprivate.then:
761 // CHECK2-NEXT: [[TMP20:%.*]] = load double, double* [[G7]], align 8
762 // CHECK2-NEXT: store volatile double [[TMP20]], double* [[CONV3]], align 8
763 // CHECK2-NEXT: [[TMP21:%.*]] = load double*, double** [[_TMP9]], align 8
764 // CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[TMP21]], align 8
765 // CHECK2-NEXT: store volatile double [[TMP22]], double* [[TMP2]], align 8
766 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR10]], align 4
767 // CHECK2-NEXT: store i32 [[TMP23]], i32* [[CONV1]], align 8
768 // CHECK2-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR11]], align 4
769 // CHECK2-NEXT: store float [[TMP24]], float* [[CONV2]], align 8
770 // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
771 // CHECK2: .omp.lastprivate.done:
772 // CHECK2-NEXT: ret void
773 //
774 //
775 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
776 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
777 // CHECK2-NEXT: entry:
778 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
779 // CHECK2-NEXT: ret void
780 //
781 //
782 // CHECK3-LABEL: define {{[^@]+}}@main
783 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
784 // CHECK3-NEXT: entry:
785 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
786 // CHECK3-NEXT: [[G:%.*]] = alloca double, align 8
787 // CHECK3-NEXT: [[G1:%.*]] = alloca double*, align 4
788 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
789 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
790 // CHECK3-NEXT: store double* [[G]], double** [[G1]], align 4
791 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
792 // CHECK3-NEXT: store double* [[G]], double** [[TMP0]], align 4
793 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
794 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4
795 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4
796 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]])
797 // CHECK3-NEXT: ret i32 0
798 //
799 //
800 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
801 // CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] {
802 // CHECK3-NEXT: entry:
803 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4
804 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
805 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
806 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4
807 // CHECK3-NEXT: [[TMP:%.*]] = alloca double*, align 4
808 // CHECK3-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
809 // CHECK3-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4
810 // CHECK3-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4
811 // CHECK3-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
812 // CHECK3-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4
813 // CHECK3-NEXT: store double* [[G]], double** [[G_ADDR]], align 4
814 // CHECK3-NEXT: [[TMP0:%.*]] = load double*, double** [[G1_ADDR]], align 4
815 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float*
816 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[G_ADDR]], align 4
817 // CHECK3-NEXT: store double* [[TMP0]], double** [[TMP]], align 4
818 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 4
819 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SVAR_ADDR]], align 4
820 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[SVAR_CASTED]], align 4
821 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
822 // CHECK3-NEXT: [[TMP5:%.*]] = load float, float* [[CONV]], align 4
823 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[SFVAR_CASTED]] to float*
824 // CHECK3-NEXT: store float [[TMP5]], float* [[CONV1]], align 4
825 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4
826 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, double*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), double* [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], double* [[TMP1]])
827 // CHECK3-NEXT: ret void
828 //
829 //
830 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
831 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] {
832 // CHECK3-NEXT: entry:
833 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
834 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
835 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4
836 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
837 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
838 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4
839 // CHECK3-NEXT: [[TMP:%.*]] = alloca double*, align 4
840 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
841 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
842 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
843 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
844 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
845 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
846 // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8
847 // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8
848 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca double*, align 4
849 // CHECK3-NEXT: [[SVAR5:%.*]] = alloca i32, align 4
850 // CHECK3-NEXT: [[SFVAR6:%.*]] = alloca float, align 4
851 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
852 // CHECK3-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
853 // CHECK3-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4
854 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
855 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
856 // CHECK3-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4
857 // CHECK3-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
858 // CHECK3-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4
859 // CHECK3-NEXT: store double* [[G]], double** [[G_ADDR]], align 4
860 // CHECK3-NEXT: [[TMP0:%.*]] = load double*, double** [[G1_ADDR]], align 4
861 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float*
862 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[G_ADDR]], align 4
863 // CHECK3-NEXT: store double* [[TMP0]], double** [[TMP]], align 4
864 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
865 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
866 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
867 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
868 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 4
869 // CHECK3-NEXT: store double* [[G13]], double** [[_TMP4]], align 4
870 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
871 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
872 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
873 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
874 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
875 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
876 // CHECK3: cond.true:
877 // CHECK3-NEXT: br label [[COND_END:%.*]]
878 // CHECK3: cond.false:
879 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
880 // CHECK3-NEXT: br label [[COND_END]]
881 // CHECK3: cond.end:
882 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
883 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
884 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
885 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
886 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
887 // CHECK3: omp.inner.for.cond:
888 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
889 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
890 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
891 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
892 // CHECK3: omp.inner.for.body:
893 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
894 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
895 // CHECK3-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP4]], align 4
896 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[SVAR5]], align 4
897 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[SVAR_CASTED]], align 4
898 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
899 // CHECK3-NEXT: [[TMP15:%.*]] = load float, float* [[SFVAR6]], align 4
900 // CHECK3-NEXT: [[CONV8:%.*]] = bitcast i32* [[SFVAR_CASTED]] to float*
901 // CHECK3-NEXT: store float [[TMP15]], float* [[CONV8]], align 4
902 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4
903 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, double*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP10]], i32 [[TMP11]], double* [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], double* [[G2]])
904 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
905 // CHECK3: omp.inner.for.inc:
906 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
907 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
908 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
909 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
910 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
911 // CHECK3: omp.inner.for.end:
912 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
913 // CHECK3: omp.loop.exit:
914 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
915 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
916 // CHECK3-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
917 // CHECK3-NEXT: br i1 [[TMP20]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
918 // CHECK3: .omp.lastprivate.then:
919 // CHECK3-NEXT: [[TMP21:%.*]] = load double, double* [[G2]], align 8
920 // CHECK3-NEXT: store volatile double [[TMP21]], double* [[TMP1]], align 8
921 // CHECK3-NEXT: [[TMP22:%.*]] = load double*, double** [[_TMP4]], align 4
922 // CHECK3-NEXT: [[TMP23:%.*]] = load double, double* [[TMP22]], align 4
923 // CHECK3-NEXT: store volatile double [[TMP23]], double* [[TMP2]], align 4
924 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[SVAR5]], align 4
925 // CHECK3-NEXT: store i32 [[TMP24]], i32* [[SVAR_ADDR]], align 4
926 // CHECK3-NEXT: [[TMP25:%.*]] = load float, float* [[SFVAR6]], align 4
927 // CHECK3-NEXT: store float [[TMP25]], float* [[CONV]], align 4
928 // CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
929 // CHECK3: .omp.lastprivate.done:
930 // CHECK3-NEXT: ret void
931 //
932 //
933 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
934 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] {
935 // CHECK3-NEXT: entry:
936 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
937 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
938 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
939 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
940 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4
941 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
942 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
943 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4
944 // CHECK3-NEXT: [[TMP:%.*]] = alloca double*, align 4
945 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
946 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
947 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
948 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
949 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
950 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
951 // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8
952 // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8
953 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca double*, align 4
954 // CHECK3-NEXT: [[SVAR5:%.*]] = alloca i32, align 4
955 // CHECK3-NEXT: [[SFVAR6:%.*]] = alloca float, align 4
956 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
957 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4
958 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
959 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
960 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
961 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
962 // CHECK3-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4
963 // CHECK3-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
964 // CHECK3-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4
965 // CHECK3-NEXT: store double* [[G]], double** [[G_ADDR]], align 4
966 // CHECK3-NEXT: [[TMP0:%.*]] = load double*, double** [[G1_ADDR]], align 4
967 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float*
968 // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[G_ADDR]], align 4
969 // CHECK3-NEXT: store double* [[TMP0]], double** [[TMP]], align 4
970 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
971 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
972 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
973 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
974 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_LB]], align 4
975 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_UB]], align 4
976 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
977 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
978 // CHECK3-NEXT: [[TMP4:%.*]] = load double*, double** [[TMP]], align 4
979 // CHECK3-NEXT: store double* [[G13]], double** [[_TMP4]], align 4
980 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
981 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
982 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
983 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
984 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
985 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
986 // CHECK3: cond.true:
987 // CHECK3-NEXT: br label [[COND_END:%.*]]
988 // CHECK3: cond.false:
989 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
990 // CHECK3-NEXT: br label [[COND_END]]
991 // CHECK3: cond.end:
992 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
993 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
994 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
995 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
996 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
997 // CHECK3: omp.inner.for.cond:
998 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
999 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1000 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
1001 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1002 // CHECK3: omp.inner.for.body:
1003 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1004 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
1005 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1006 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1007 // CHECK3-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4
1008 // CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4
1009 // CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4
1010 // CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4
1011 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
1012 // CHECK3-NEXT: store double* [[G2]], double** [[TMP14]], align 4
1013 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
1014 // CHECK3-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4
1015 // CHECK3-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4
1016 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
1017 // CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4
1018 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
1019 // CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4
1020 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])
1021 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1022 // CHECK3: omp.body.continue:
1023 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1024 // CHECK3: omp.inner.for.inc:
1025 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1026 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
1027 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
1028 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
1029 // CHECK3: omp.inner.for.end:
1030 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1031 // CHECK3: omp.loop.exit:
1032 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
1033 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1034 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
1035 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1036 // CHECK3: .omp.lastprivate.then:
1037 // CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[G2]], align 8
1038 // CHECK3-NEXT: store volatile double [[TMP22]], double* [[TMP1]], align 8
1039 // CHECK3-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP4]], align 4
1040 // CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[TMP23]], align 4
1041 // CHECK3-NEXT: store volatile double [[TMP24]], double* [[TMP4]], align 4
1042 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[SVAR5]], align 4
1043 // CHECK3-NEXT: store i32 [[TMP25]], i32* [[SVAR_ADDR]], align 4
1044 // CHECK3-NEXT: [[TMP26:%.*]] = load float, float* [[SFVAR6]], align 4
1045 // CHECK3-NEXT: store float [[TMP26]], float* [[CONV]], align 4
1046 // CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1047 // CHECK3: .omp.lastprivate.done:
1048 // CHECK3-NEXT: ret void
1049 //
1050 //
1051 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1052 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
1053 // CHECK3-NEXT: entry:
1054 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
1055 // CHECK3-NEXT: ret void
1056 //
1057 //
1058 // CHECK4-LABEL: define {{[^@]+}}@main
1059 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
1060 // CHECK4-NEXT: entry:
1061 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1062 // CHECK4-NEXT: [[G:%.*]] = alloca double, align 8
1063 // CHECK4-NEXT: [[G1:%.*]] = alloca double*, align 4
1064 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
1065 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
1066 // CHECK4-NEXT: store double* [[G]], double** [[G1]], align 4
1067 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0
1068 // CHECK4-NEXT: store double* [[G]], double** [[TMP0]], align 4
1069 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1
1070 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4
1071 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4
1072 // CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]])
1073 // CHECK4-NEXT: ret i32 0
1074 //
1075 //
1076 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
1077 // CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] {
1078 // CHECK4-NEXT: entry:
1079 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4
1080 // CHECK4-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
1081 // CHECK4-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
1082 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4
1083 // CHECK4-NEXT: [[TMP:%.*]] = alloca double*, align 4
1084 // CHECK4-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
1085 // CHECK4-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4
1086 // CHECK4-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4
1087 // CHECK4-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
1088 // CHECK4-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4
1089 // CHECK4-NEXT: store double* [[G]], double** [[G_ADDR]], align 4
1090 // CHECK4-NEXT: [[TMP0:%.*]] = load double*, double** [[G1_ADDR]], align 4
1091 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float*
1092 // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[G_ADDR]], align 4
1093 // CHECK4-NEXT: store double* [[TMP0]], double** [[TMP]], align 4
1094 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 4
1095 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SVAR_ADDR]], align 4
1096 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[SVAR_CASTED]], align 4
1097 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
1098 // CHECK4-NEXT: [[TMP5:%.*]] = load float, float* [[CONV]], align 4
1099 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[SFVAR_CASTED]] to float*
1100 // CHECK4-NEXT: store float [[TMP5]], float* [[CONV1]], align 4
1101 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4
1102 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, double*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), double* [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], double* [[TMP1]])
1103 // CHECK4-NEXT: ret void
1104 //
1105 //
1106 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
1107 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] {
1108 // CHECK4-NEXT: entry:
1109 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1110 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1111 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4
1112 // CHECK4-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
1113 // CHECK4-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
1114 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4
1115 // CHECK4-NEXT: [[TMP:%.*]] = alloca double*, align 4
1116 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1117 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1118 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1119 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1120 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1121 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1122 // CHECK4-NEXT: [[G2:%.*]] = alloca double, align 8
1123 // CHECK4-NEXT: [[G13:%.*]] = alloca double, align 8
1124 // CHECK4-NEXT: [[_TMP4:%.*]] = alloca double*, align 4
1125 // CHECK4-NEXT: [[SVAR5:%.*]] = alloca i32, align 4
1126 // CHECK4-NEXT: [[SFVAR6:%.*]] = alloca float, align 4
1127 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
1128 // CHECK4-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
1129 // CHECK4-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4
1130 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1131 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1132 // CHECK4-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4
1133 // CHECK4-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
1134 // CHECK4-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4
1135 // CHECK4-NEXT: store double* [[G]], double** [[G_ADDR]], align 4
1136 // CHECK4-NEXT: [[TMP0:%.*]] = load double*, double** [[G1_ADDR]], align 4
1137 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float*
1138 // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[G_ADDR]], align 4
1139 // CHECK4-NEXT: store double* [[TMP0]], double** [[TMP]], align 4
1140 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1141 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1142 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1143 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1144 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[TMP]], align 4
1145 // CHECK4-NEXT: store double* [[G13]], double** [[_TMP4]], align 4
1146 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1147 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
1148 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1149 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1150 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
1151 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1152 // CHECK4: cond.true:
1153 // CHECK4-NEXT: br label [[COND_END:%.*]]
1154 // CHECK4: cond.false:
1155 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1156 // CHECK4-NEXT: br label [[COND_END]]
1157 // CHECK4: cond.end:
1158 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
1159 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1160 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1161 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
1162 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1163 // CHECK4: omp.inner.for.cond:
1164 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1165 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1166 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
1167 // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1168 // CHECK4: omp.inner.for.body:
1169 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1170 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1171 // CHECK4-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP4]], align 4
1172 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[SVAR5]], align 4
1173 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[SVAR_CASTED]], align 4
1174 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
1175 // CHECK4-NEXT: [[TMP15:%.*]] = load float, float* [[SFVAR6]], align 4
1176 // CHECK4-NEXT: [[CONV8:%.*]] = bitcast i32* [[SFVAR_CASTED]] to float*
1177 // CHECK4-NEXT: store float [[TMP15]], float* [[CONV8]], align 4
1178 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4
1179 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, double*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP10]], i32 [[TMP11]], double* [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], double* [[G2]])
1180 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1181 // CHECK4: omp.inner.for.inc:
1182 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1183 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1184 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
1185 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1186 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
1187 // CHECK4: omp.inner.for.end:
1188 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1189 // CHECK4: omp.loop.exit:
1190 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
1191 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1192 // CHECK4-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
1193 // CHECK4-NEXT: br i1 [[TMP20]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1194 // CHECK4: .omp.lastprivate.then:
1195 // CHECK4-NEXT: [[TMP21:%.*]] = load double, double* [[G2]], align 8
1196 // CHECK4-NEXT: store volatile double [[TMP21]], double* [[TMP1]], align 8
1197 // CHECK4-NEXT: [[TMP22:%.*]] = load double*, double** [[_TMP4]], align 4
1198 // CHECK4-NEXT: [[TMP23:%.*]] = load double, double* [[TMP22]], align 4
1199 // CHECK4-NEXT: store volatile double [[TMP23]], double* [[TMP2]], align 4
1200 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[SVAR5]], align 4
1201 // CHECK4-NEXT: store i32 [[TMP24]], i32* [[SVAR_ADDR]], align 4
1202 // CHECK4-NEXT: [[TMP25:%.*]] = load float, float* [[SFVAR6]], align 4
1203 // CHECK4-NEXT: store float [[TMP25]], float* [[CONV]], align 4
1204 // CHECK4-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1205 // CHECK4: .omp.lastprivate.done:
1206 // CHECK4-NEXT: ret void
1207 //
1208 //
1209 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
1210 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] {
1211 // CHECK4-NEXT: entry:
1212 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1213 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1214 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1215 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1216 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4
1217 // CHECK4-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
1218 // CHECK4-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
1219 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4
1220 // CHECK4-NEXT: [[TMP:%.*]] = alloca double*, align 4
1221 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1222 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1223 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1224 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1225 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1226 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1227 // CHECK4-NEXT: [[G2:%.*]] = alloca double, align 8
1228 // CHECK4-NEXT: [[G13:%.*]] = alloca double, align 8
1229 // CHECK4-NEXT: [[_TMP4:%.*]] = alloca double*, align 4
1230 // CHECK4-NEXT: [[SVAR5:%.*]] = alloca i32, align 4
1231 // CHECK4-NEXT: [[SFVAR6:%.*]] = alloca float, align 4
1232 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
1233 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4
1234 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1235 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1236 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1237 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1238 // CHECK4-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4
1239 // CHECK4-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
1240 // CHECK4-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4
1241 // CHECK4-NEXT: store double* [[G]], double** [[G_ADDR]], align 4
1242 // CHECK4-NEXT: [[TMP0:%.*]] = load double*, double** [[G1_ADDR]], align 4
1243 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float*
1244 // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[G_ADDR]], align 4
1245 // CHECK4-NEXT: store double* [[TMP0]], double** [[TMP]], align 4
1246 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1247 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1248 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1249 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1250 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_LB]], align 4
1251 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_UB]], align 4
1252 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1253 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1254 // CHECK4-NEXT: [[TMP4:%.*]] = load double*, double** [[TMP]], align 4
1255 // CHECK4-NEXT: store double* [[G13]], double** [[_TMP4]], align 4
1256 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1257 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
1258 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1259 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1260 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
1261 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1262 // CHECK4: cond.true:
1263 // CHECK4-NEXT: br label [[COND_END:%.*]]
1264 // CHECK4: cond.false:
1265 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1266 // CHECK4-NEXT: br label [[COND_END]]
1267 // CHECK4: cond.end:
1268 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
1269 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1270 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1271 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
1272 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1273 // CHECK4: omp.inner.for.cond:
1274 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1275 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1276 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
1277 // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1278 // CHECK4: omp.inner.for.body:
1279 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1280 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
1281 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1282 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1283 // CHECK4-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4
1284 // CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4
1285 // CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4
1286 // CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4
1287 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
1288 // CHECK4-NEXT: store double* [[G2]], double** [[TMP14]], align 4
1289 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
1290 // CHECK4-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4
1291 // CHECK4-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4
1292 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
1293 // CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4
1294 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3
1295 // CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4
1296 // CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]])
1297 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1298 // CHECK4: omp.body.continue:
1299 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1300 // CHECK4: omp.inner.for.inc:
1301 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1302 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
1303 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
1304 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
1305 // CHECK4: omp.inner.for.end:
1306 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1307 // CHECK4: omp.loop.exit:
1308 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
1309 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1310 // CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
1311 // CHECK4-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1312 // CHECK4: .omp.lastprivate.then:
1313 // CHECK4-NEXT: [[TMP22:%.*]] = load double, double* [[G2]], align 8
1314 // CHECK4-NEXT: store volatile double [[TMP22]], double* [[TMP1]], align 8
1315 // CHECK4-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP4]], align 4
1316 // CHECK4-NEXT: [[TMP24:%.*]] = load double, double* [[TMP23]], align 4
1317 // CHECK4-NEXT: store volatile double [[TMP24]], double* [[TMP4]], align 4
1318 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[SVAR5]], align 4
1319 // CHECK4-NEXT: store i32 [[TMP25]], i32* [[SVAR_ADDR]], align 4
1320 // CHECK4-NEXT: [[TMP26:%.*]] = load float, float* [[SFVAR6]], align 4
1321 // CHECK4-NEXT: store float [[TMP26]], float* [[CONV]], align 4
1322 // CHECK4-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1323 // CHECK4: .omp.lastprivate.done:
1324 // CHECK4-NEXT: ret void
1325 //
1326 //
1327 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1328 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] {
1329 // CHECK4-NEXT: entry:
1330 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
1331 // CHECK4-NEXT: ret void
1332 //
1333 //
1334 // CHECK5-LABEL: define {{[^@]+}}@main
1335 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1336 // CHECK5-NEXT: entry:
1337 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1338 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8
1339 // CHECK5-NEXT: [[G1:%.*]] = alloca double*, align 8
1340 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1341 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1342 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1343 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1344 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8
1345 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
1346 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1347 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
1348 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1349 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1350 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1351 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1352 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1353 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1354 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8
1355 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
1356 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
1357 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1358 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false)
1359 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
1360 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00)
1361 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
1362 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)
1363 // CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8
1364 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8
1365 // CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8
1366 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
1367 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1368 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
1369 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1370 // CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
1371 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4
1372 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
1373 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4
1374 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
1375 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1376 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
1377 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8
1378 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1379 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
1380 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 8
1381 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1382 // CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8
1383 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1384 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1385 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
1386 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1387 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1388 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
1389 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1390 // CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8
1391 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1392 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]**
1393 // CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8
1394 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1395 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]**
1396 // CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8
1397 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1398 // CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8
1399 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1400 // CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S**
1401 // CHECK5-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 8
1402 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1403 // CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S**
1404 // CHECK5-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 8
1405 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1406 // CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8
1407 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1408 // CHECK5-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
1409 // CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP28]], align 8
1410 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1411 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
1412 // CHECK5-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8
1413 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1414 // CHECK5-NEXT: store i8* null, i8** [[TMP31]], align 8
1415 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1416 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1417 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
1418 // CHECK5-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1419 // CHECK5-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
1420 // CHECK5-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1421 // CHECK5: omp_offload.failed:
1422 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]]
1423 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
1424 // CHECK5: omp_offload.cont:
1425 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
1426 // CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
1427 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1428 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1429 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1430 // CHECK5: arraydestroy.body:
1431 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1432 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1433 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1434 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1435 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
1436 // CHECK5: arraydestroy.done3:
1437 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1438 // CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4
1439 // CHECK5-NEXT: ret i32 [[TMP37]]
1440 //
1441 //
1442 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1443 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1444 // CHECK5-NEXT: entry:
1445 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1446 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1447 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1448 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1449 // CHECK5-NEXT: ret void
1450 //
1451 //
1452 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1453 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1454 // CHECK5-NEXT: entry:
1455 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1456 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1457 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1458 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1459 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1460 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1461 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1462 // CHECK5-NEXT: ret void
1463 //
1464 //
1465 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
1466 // CHECK5-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
1467 // CHECK5-NEXT: entry:
1468 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1469 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1470 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1471 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1472 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
1473 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
1474 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1475 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
1476 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1477 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1478 // CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1479 // CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1480 // CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
1481 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1482 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1483 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1484 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1485 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
1486 // CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
1487 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1488 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1489 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
1490 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1491 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
1492 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
1493 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
1494 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
1495 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
1496 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
1497 // CHECK5-NEXT: ret void
1498 //
1499 //
1500 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
1501 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] {
1502 // CHECK5-NEXT: entry:
1503 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1504 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1505 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1506 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1507 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1508 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1509 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
1510 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
1511 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1512 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1513 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1514 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1515 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1516 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1517 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4
1518 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
1519 // CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
1520 // CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1521 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8
1522 // CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4
1523 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1524 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1525 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
1526 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1527 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1528 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1529 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1530 // CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1531 // CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1532 // CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
1533 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1534 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1535 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1536 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1537 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
1538 // CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
1539 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1540 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1541 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1542 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1543 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
1544 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1545 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1546 // CHECK5: arrayctor.loop:
1547 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1548 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1549 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
1550 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1551 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1552 // CHECK5: arrayctor.cont:
1553 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
1554 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]])
1555 // CHECK5-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8
1556 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1557 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1558 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1559 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1560 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
1561 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1562 // CHECK5: cond.true:
1563 // CHECK5-NEXT: br label [[COND_END:%.*]]
1564 // CHECK5: cond.false:
1565 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1566 // CHECK5-NEXT: br label [[COND_END]]
1567 // CHECK5: cond.end:
1568 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1569 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1570 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1571 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
1572 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1573 // CHECK5: omp.inner.for.cond:
1574 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1575 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1576 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1577 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1578 // CHECK5: omp.inner.for.cond.cleanup:
1579 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1580 // CHECK5: omp.inner.for.body:
1581 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1582 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
1583 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1584 // CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
1585 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4
1586 // CHECK5-NEXT: [[CONV10:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1587 // CHECK5-NEXT: store i32 [[TMP15]], i32* [[CONV10]], align 4
1588 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1589 // CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
1590 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[SVAR8]], align 4
1591 // CHECK5-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
1592 // CHECK5-NEXT: store i32 [[TMP18]], i32* [[CONV11]], align 4
1593 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
1594 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC4]], i64 [[TMP16]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP17]], i64 [[TMP19]])
1595 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1596 // CHECK5: omp.inner.for.inc:
1597 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1598 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1599 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
1600 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1601 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1602 // CHECK5: omp.inner.for.end:
1603 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1604 // CHECK5: omp.loop.exit:
1605 // CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1606 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
1607 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
1608 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1609 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
1610 // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1611 // CHECK5: .omp.lastprivate.then:
1612 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4
1613 // CHECK5-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 8
1614 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1615 // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
1616 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
1617 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
1618 // CHECK5-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
1619 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2
1620 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]]
1621 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1622 // CHECK5: omp.arraycpy.body:
1623 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1624 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1625 // CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
1626 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
1627 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false)
1628 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1629 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1630 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]]
1631 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]]
1632 // CHECK5: omp.arraycpy.done13:
1633 // CHECK5-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
1634 // CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
1635 // CHECK5-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8*
1636 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false)
1637 // CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4
1638 // CHECK5-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 8
1639 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1640 // CHECK5: .omp.lastprivate.done:
1641 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
1642 // CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
1643 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
1644 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1645 // CHECK5: arraydestroy.body:
1646 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1647 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1648 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1649 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
1650 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
1651 // CHECK5: arraydestroy.done15:
1652 // CHECK5-NEXT: ret void
1653 //
1654 //
1655 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1
1656 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] {
1657 // CHECK5-NEXT: entry:
1658 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1659 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1660 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1661 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1662 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1663 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1664 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1665 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1666 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
1667 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
1668 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1669 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1670 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1671 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1672 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1673 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1674 // CHECK5-NEXT: [[T_VAR5:%.*]] = alloca i32, align 4
1675 // CHECK5-NEXT: [[VEC6:%.*]] = alloca [2 x i32], align 4
1676 // CHECK5-NEXT: [[S_ARR7:%.*]] = alloca [2 x %struct.S], align 4
1677 // CHECK5-NEXT: [[VAR8:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1678 // CHECK5-NEXT: [[_TMP9:%.*]] = alloca %struct.S*, align 8
1679 // CHECK5-NEXT: [[SVAR10:%.*]] = alloca i32, align 4
1680 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1681 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1682 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1683 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1684 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1685 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1686 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1687 // CHECK5-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1688 // CHECK5-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1689 // CHECK5-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
1690 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1691 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1692 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1693 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1694 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
1695 // CHECK5-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
1696 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1697 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1698 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1699 // CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP3]] to i32
1700 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1701 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP4]] to i32
1702 // CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4
1703 // CHECK5-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4
1704 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1705 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1706 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0
1707 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1708 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1709 // CHECK5: arrayctor.loop:
1710 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1711 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1712 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
1713 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1714 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1715 // CHECK5: arrayctor.cont:
1716 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
1717 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]])
1718 // CHECK5-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8
1719 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1720 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
1721 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1722 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1723 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
1724 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1725 // CHECK5: cond.true:
1726 // CHECK5-NEXT: br label [[COND_END:%.*]]
1727 // CHECK5: cond.false:
1728 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1729 // CHECK5-NEXT: br label [[COND_END]]
1730 // CHECK5: cond.end:
1731 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
1732 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1733 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1734 // CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
1735 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1736 // CHECK5: omp.inner.for.cond:
1737 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1738 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1739 // CHECK5-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
1740 // CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1741 // CHECK5: omp.inner.for.cond.cleanup:
1742 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1743 // CHECK5: omp.inner.for.body:
1744 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1745 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
1746 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1747 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1748 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR5]], align 4
1749 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
1750 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
1751 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC6]], i64 0, i64 [[IDXPROM]]
1752 // CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
1753 // CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
1754 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
1755 // CHECK5-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP17]] to i64
1756 // CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i64 0, i64 [[IDXPROM12]]
1757 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX13]] to i8*
1758 // CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8*
1759 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
1760 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1761 // CHECK5: omp.body.continue:
1762 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1763 // CHECK5: omp.inner.for.inc:
1764 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1765 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP20]], 1
1766 // CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4
1767 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1768 // CHECK5: omp.inner.for.end:
1769 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1770 // CHECK5: omp.loop.exit:
1771 // CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1772 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
1773 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
1774 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1775 // CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
1776 // CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1777 // CHECK5: .omp.lastprivate.then:
1778 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR5]], align 4
1779 // CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
1780 // CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1781 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
1782 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
1783 // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
1784 // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S*
1785 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
1786 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP29]]
1787 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1788 // CHECK5: omp.arraycpy.body:
1789 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1790 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1791 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
1792 // CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
1793 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false)
1794 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1795 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1796 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
1797 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]]
1798 // CHECK5: omp.arraycpy.done16:
1799 // CHECK5-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
1800 // CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8*
1801 // CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
1802 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
1803 // CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR10]], align 4
1804 // CHECK5-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8
1805 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1806 // CHECK5: .omp.lastprivate.done:
1807 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
1808 // CHECK5-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0
1809 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2
1810 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1811 // CHECK5: arraydestroy.body:
1812 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1813 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1814 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1815 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN17]]
1816 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY]]
1817 // CHECK5: arraydestroy.done18:
1818 // CHECK5-NEXT: ret void
1819 //
1820 //
1821 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1822 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1823 // CHECK5-NEXT: entry:
1824 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1825 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1826 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1827 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1828 // CHECK5-NEXT: ret void
1829 //
1830 //
1831 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1832 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
1833 // CHECK5-NEXT: entry:
1834 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1835 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1836 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1837 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1838 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1839 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
1840 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1841 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1842 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1843 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1844 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1845 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1846 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1847 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
1848 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1849 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1850 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1851 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
1852 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1853 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
1854 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
1855 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
1856 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
1857 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
1858 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1859 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
1860 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1861 // CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1862 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1863 // CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
1864 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8
1865 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1866 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
1867 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8
1868 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1869 // CHECK5-NEXT: store i8* null, i8** [[TMP9]], align 8
1870 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1871 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1872 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
1873 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1874 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1875 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
1876 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1877 // CHECK5-NEXT: store i8* null, i8** [[TMP14]], align 8
1878 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1879 // CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
1880 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8
1881 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1882 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
1883 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
1884 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1885 // CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8
1886 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1887 // CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
1888 // CHECK5-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8
1889 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1890 // CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
1891 // CHECK5-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8
1892 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1893 // CHECK5-NEXT: store i8* null, i8** [[TMP24]], align 8
1894 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1895 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1896 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
1897 // CHECK5-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1898 // CHECK5-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
1899 // CHECK5-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1900 // CHECK5: omp_offload.failed:
1901 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]]
1902 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
1903 // CHECK5: omp_offload.cont:
1904 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
1905 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1906 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1907 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1908 // CHECK5: arraydestroy.body:
1909 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1910 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1911 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1912 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1913 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1914 // CHECK5: arraydestroy.done2:
1915 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1916 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4
1917 // CHECK5-NEXT: ret i32 [[TMP30]]
1918 //
1919 //
1920 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1921 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1922 // CHECK5-NEXT: entry:
1923 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1924 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1925 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1926 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1927 // CHECK5-NEXT: store float 0.000000e+00, float* [[F]], align 4
1928 // CHECK5-NEXT: ret void
1929 //
1930 //
1931 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1932 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1933 // CHECK5-NEXT: entry:
1934 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1935 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1936 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1937 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1938 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1939 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1940 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1941 // CHECK5-NEXT: store float [[TMP0]], float* [[F]], align 4
1942 // CHECK5-NEXT: ret void
1943 //
1944 //
1945 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1946 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1947 // CHECK5-NEXT: entry:
1948 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1949 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1950 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1951 // CHECK5-NEXT: ret void
1952 //
1953 //
1954 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1955 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1956 // CHECK5-NEXT: entry:
1957 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1958 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1959 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1960 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1961 // CHECK5-NEXT: ret void
1962 //
1963 //
1964 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1965 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1966 // CHECK5-NEXT: entry:
1967 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1968 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1969 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1970 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1971 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1972 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1973 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
1974 // CHECK5-NEXT: ret void
1975 //
1976 //
1977 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50
1978 // CHECK5-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1979 // CHECK5-NEXT: entry:
1980 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1981 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1982 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1983 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1984 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1985 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1986 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1987 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1988 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1989 // CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1990 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1991 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1992 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1993 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1994 // CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1995 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1996 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1997 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
1998 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1999 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
2000 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
2001 // CHECK5-NEXT: ret void
2002 //
2003 //
2004 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
2005 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2006 // CHECK5-NEXT: entry:
2007 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2008 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2009 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
2010 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
2011 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
2012 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
2013 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
2014 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2015 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2016 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2017 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2018 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2019 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2020 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2021 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2022 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2023 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2024 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
2025 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2026 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
2027 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2028 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2029 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2030 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
2031 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2032 // CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
2033 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2034 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
2035 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2036 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
2037 // CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
2038 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2039 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2040 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2041 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2042 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2043 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2044 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2045 // CHECK5: arrayctor.loop:
2046 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2047 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2048 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
2049 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2050 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2051 // CHECK5: arrayctor.cont:
2052 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
2053 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
2054 // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
2055 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2056 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2057 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2058 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2059 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
2060 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2061 // CHECK5: cond.true:
2062 // CHECK5-NEXT: br label [[COND_END:%.*]]
2063 // CHECK5: cond.false:
2064 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2065 // CHECK5-NEXT: br label [[COND_END]]
2066 // CHECK5: cond.end:
2067 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2068 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2069 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2070 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
2071 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2072 // CHECK5: omp.inner.for.cond:
2073 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2074 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2075 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2076 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2077 // CHECK5: omp.inner.for.cond.cleanup:
2078 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2079 // CHECK5: omp.inner.for.body:
2080 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2081 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
2082 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2083 // CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
2084 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4
2085 // CHECK5-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
2086 // CHECK5-NEXT: store i32 [[TMP15]], i32* [[CONV8]], align 4
2087 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
2088 // CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8
2089 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC3]], i64 [[TMP16]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP17]])
2090 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2091 // CHECK5: omp.inner.for.inc:
2092 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2093 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2094 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
2095 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2096 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
2097 // CHECK5: omp.inner.for.end:
2098 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2099 // CHECK5: omp.loop.exit:
2100 // CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2101 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4
2102 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
2103 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2104 // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
2105 // CHECK5-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2106 // CHECK5: .omp.lastprivate.then:
2107 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4
2108 // CHECK5-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 8
2109 // CHECK5-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2110 // CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
2111 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false)
2112 // CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
2113 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
2114 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2
2115 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]]
2116 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2117 // CHECK5: omp.arraycpy.body:
2118 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2119 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2120 // CHECK5-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
2121 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
2122 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false)
2123 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2124 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2125 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]]
2126 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]]
2127 // CHECK5: omp.arraycpy.done10:
2128 // CHECK5-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8
2129 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8*
2130 // CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8*
2131 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false)
2132 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2133 // CHECK5: .omp.lastprivate.done:
2134 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2135 // CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2136 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2
2137 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2138 // CHECK5: arraydestroy.body:
2139 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2140 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2141 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2142 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
2143 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
2144 // CHECK5: arraydestroy.done12:
2145 // CHECK5-NEXT: ret void
2146 //
2147 //
2148 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
2149 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2150 // CHECK5-NEXT: entry:
2151 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2152 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2153 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2154 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2155 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
2156 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
2157 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
2158 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
2159 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
2160 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2161 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2162 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2163 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2164 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2165 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2166 // CHECK5-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4
2167 // CHECK5-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4
2168 // CHECK5-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4
2169 // CHECK5-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2170 // CHECK5-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8
2171 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2172 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2173 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2174 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2175 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2176 // CHECK5-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2177 // CHECK5-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
2178 // CHECK5-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2179 // CHECK5-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
2180 // CHECK5-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2181 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
2182 // CHECK5-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2183 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
2184 // CHECK5-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
2185 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2186 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2187 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2188 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
2189 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2190 // CHECK5-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
2191 // CHECK5-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
2192 // CHECK5-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
2193 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2194 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2195 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0
2196 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2197 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2198 // CHECK5: arrayctor.loop:
2199 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2200 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2201 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
2202 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2203 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2204 // CHECK5: arrayctor.cont:
2205 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
2206 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]])
2207 // CHECK5-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8
2208 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2209 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
2210 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2211 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2212 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
2213 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2214 // CHECK5: cond.true:
2215 // CHECK5-NEXT: br label [[COND_END:%.*]]
2216 // CHECK5: cond.false:
2217 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2218 // CHECK5-NEXT: br label [[COND_END]]
2219 // CHECK5: cond.end:
2220 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
2221 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2222 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2223 // CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
2224 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2225 // CHECK5: omp.inner.for.cond:
2226 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2227 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2228 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
2229 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2230 // CHECK5: omp.inner.for.cond.cleanup:
2231 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2232 // CHECK5: omp.inner.for.body:
2233 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2234 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
2235 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2236 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2237 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR4]], align 4
2238 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
2239 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
2240 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
2241 // CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
2242 // CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8
2243 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
2244 // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64
2245 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i64 0, i64 [[IDXPROM10]]
2246 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8*
2247 // CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8*
2248 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
2249 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2250 // CHECK5: omp.body.continue:
2251 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2252 // CHECK5: omp.inner.for.inc:
2253 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2254 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1
2255 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
2256 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
2257 // CHECK5: omp.inner.for.end:
2258 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2259 // CHECK5: omp.loop.exit:
2260 // CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2261 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
2262 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
2263 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2264 // CHECK5-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
2265 // CHECK5-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2266 // CHECK5: .omp.lastprivate.then:
2267 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR4]], align 4
2268 // CHECK5-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
2269 // CHECK5-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2270 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
2271 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
2272 // CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
2273 // CHECK5-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0*
2274 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2
2275 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP29]]
2276 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2277 // CHECK5: omp.arraycpy.body:
2278 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2279 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2280 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
2281 // CHECK5-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
2282 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false)
2283 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2284 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2285 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
2286 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]]
2287 // CHECK5: omp.arraycpy.done14:
2288 // CHECK5-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8
2289 // CHECK5-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8*
2290 // CHECK5-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8*
2291 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
2292 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2293 // CHECK5: .omp.lastprivate.done:
2294 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
2295 // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0
2296 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN15]], i64 2
2297 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2298 // CHECK5: arraydestroy.body:
2299 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2300 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2301 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2302 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
2303 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
2304 // CHECK5: arraydestroy.done16:
2305 // CHECK5-NEXT: ret void
2306 //
2307 //
2308 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2309 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2310 // CHECK5-NEXT: entry:
2311 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2312 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2313 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2314 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2315 // CHECK5-NEXT: ret void
2316 //
2317 //
2318 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2319 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2320 // CHECK5-NEXT: entry:
2321 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2322 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2323 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2324 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2325 // CHECK5-NEXT: store i32 0, i32* [[F]], align 4
2326 // CHECK5-NEXT: ret void
2327 //
2328 //
2329 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2330 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2331 // CHECK5-NEXT: entry:
2332 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2333 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2334 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2335 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2336 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2337 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2338 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2339 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2340 // CHECK5-NEXT: ret void
2341 //
2342 //
2343 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2344 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2345 // CHECK5-NEXT: entry:
2346 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2347 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2348 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2349 // CHECK5-NEXT: ret void
2350 //
2351 //
2352 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2353 // CHECK5-SAME: () #[[ATTR6:[0-9]+]] {
2354 // CHECK5-NEXT: entry:
2355 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
2356 // CHECK5-NEXT: ret void
2357 //
2358 //
2359 // CHECK6-LABEL: define {{[^@]+}}@main
2360 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
2361 // CHECK6-NEXT: entry:
2362 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2363 // CHECK6-NEXT: [[G:%.*]] = alloca double, align 8
2364 // CHECK6-NEXT: [[G1:%.*]] = alloca double*, align 8
2365 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2366 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2367 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2368 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2369 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8
2370 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
2371 // CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
2372 // CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
2373 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
2374 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
2375 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
2376 // CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
2377 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
2378 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
2379 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8
2380 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
2381 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4
2382 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2383 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false)
2384 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
2385 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00)
2386 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
2387 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)
2388 // CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8
2389 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8
2390 // CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8
2391 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
2392 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
2393 // CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
2394 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
2395 // CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
2396 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4
2397 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
2398 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4
2399 // CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
2400 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2401 // CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
2402 // CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8
2403 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2404 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
2405 // CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 8
2406 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2407 // CHECK6-NEXT: store i8* null, i8** [[TMP11]], align 8
2408 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2409 // CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
2410 // CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
2411 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2412 // CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
2413 // CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
2414 // CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2415 // CHECK6-NEXT: store i8* null, i8** [[TMP16]], align 8
2416 // CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2417 // CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]**
2418 // CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8
2419 // CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2420 // CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]**
2421 // CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8
2422 // CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2423 // CHECK6-NEXT: store i8* null, i8** [[TMP21]], align 8
2424 // CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2425 // CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S**
2426 // CHECK6-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 8
2427 // CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2428 // CHECK6-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S**
2429 // CHECK6-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 8
2430 // CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2431 // CHECK6-NEXT: store i8* null, i8** [[TMP26]], align 8
2432 // CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2433 // CHECK6-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
2434 // CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP28]], align 8
2435 // CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2436 // CHECK6-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
2437 // CHECK6-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8
2438 // CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
2439 // CHECK6-NEXT: store i8* null, i8** [[TMP31]], align 8
2440 // CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2441 // CHECK6-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2442 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
2443 // CHECK6-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2444 // CHECK6-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
2445 // CHECK6-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2446 // CHECK6: omp_offload.failed:
2447 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]]
2448 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
2449 // CHECK6: omp_offload.cont:
2450 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
2451 // CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
2452 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2453 // CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
2454 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2455 // CHECK6: arraydestroy.body:
2456 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2457 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2458 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2459 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2460 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
2461 // CHECK6: arraydestroy.done3:
2462 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2463 // CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4
2464 // CHECK6-NEXT: ret i32 [[TMP37]]
2465 //
2466 //
2467 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2468 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2469 // CHECK6-NEXT: entry:
2470 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2471 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2472 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2473 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2474 // CHECK6-NEXT: ret void
2475 //
2476 //
2477 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2478 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2479 // CHECK6-NEXT: entry:
2480 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2481 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2482 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2483 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2484 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2485 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2486 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2487 // CHECK6-NEXT: ret void
2488 //
2489 //
2490 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
2491 // CHECK6-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
2492 // CHECK6-NEXT: entry:
2493 // CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
2494 // CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
2495 // CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
2496 // CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
2497 // CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
2498 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
2499 // CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
2500 // CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
2501 // CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2502 // CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
2503 // CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
2504 // CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
2505 // CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
2506 // CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2507 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
2508 // CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
2509 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
2510 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
2511 // CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
2512 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
2513 // CHECK6-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
2514 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
2515 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
2516 // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
2517 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8
2518 // CHECK6-NEXT: [[CONV3:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
2519 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[CONV3]], align 4
2520 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
2521 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i64 [[TMP7]])
2522 // CHECK6-NEXT: ret void
2523 //
2524 //
2525 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
2526 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] {
2527 // CHECK6-NEXT: entry:
2528 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2529 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2530 // CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
2531 // CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
2532 // CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
2533 // CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
2534 // CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
2535 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
2536 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2537 // CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
2538 // CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2539 // CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2540 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2541 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2542 // CHECK6-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4
2543 // CHECK6-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
2544 // CHECK6-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
2545 // CHECK6-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2546 // CHECK6-NEXT: [[_TMP7:%.*]] = alloca %struct.S*, align 8
2547 // CHECK6-NEXT: [[SVAR8:%.*]] = alloca i32, align 4
2548 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
2549 // CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
2550 // CHECK6-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
2551 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2552 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2553 // CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2554 // CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
2555 // CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
2556 // CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
2557 // CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
2558 // CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2559 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
2560 // CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
2561 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
2562 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
2563 // CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
2564 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2565 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2566 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2567 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2568 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
2569 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
2570 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2571 // CHECK6: arrayctor.loop:
2572 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2573 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2574 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
2575 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2576 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2577 // CHECK6: arrayctor.cont:
2578 // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
2579 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]])
2580 // CHECK6-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8
2581 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2582 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2583 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2584 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2585 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
2586 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2587 // CHECK6: cond.true:
2588 // CHECK6-NEXT: br label [[COND_END:%.*]]
2589 // CHECK6: cond.false:
2590 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2591 // CHECK6-NEXT: br label [[COND_END]]
2592 // CHECK6: cond.end:
2593 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2594 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2595 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2596 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
2597 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2598 // CHECK6: omp.inner.for.cond:
2599 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2600 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2601 // CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2602 // CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2603 // CHECK6: omp.inner.for.cond.cleanup:
2604 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2605 // CHECK6: omp.inner.for.body:
2606 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2607 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
2608 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2609 // CHECK6-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
2610 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4
2611 // CHECK6-NEXT: [[CONV10:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
2612 // CHECK6-NEXT: store i32 [[TMP15]], i32* [[CONV10]], align 4
2613 // CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
2614 // CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
2615 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[SVAR8]], align 4
2616 // CHECK6-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32*
2617 // CHECK6-NEXT: store i32 [[TMP18]], i32* [[CONV11]], align 4
2618 // CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8
2619 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC4]], i64 [[TMP16]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP17]], i64 [[TMP19]])
2620 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2621 // CHECK6: omp.inner.for.inc:
2622 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2623 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2624 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
2625 // CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2626 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]
2627 // CHECK6: omp.inner.for.end:
2628 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2629 // CHECK6: omp.loop.exit:
2630 // CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2631 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
2632 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
2633 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2634 // CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
2635 // CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2636 // CHECK6: .omp.lastprivate.then:
2637 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4
2638 // CHECK6-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 8
2639 // CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2640 // CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
2641 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 8, i1 false)
2642 // CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
2643 // CHECK6-NEXT: [[TMP29:%.*]] = bitcast [2 x %struct.S]* [[S_ARR5]] to %struct.S*
2644 // CHECK6-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2
2645 // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN12]], [[TMP30]]
2646 // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2647 // CHECK6: omp.arraycpy.body:
2648 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2649 // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2650 // CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
2651 // CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
2652 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false)
2653 // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2654 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2655 // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP30]]
2656 // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]]
2657 // CHECK6: omp.arraycpy.done13:
2658 // CHECK6-NEXT: [[TMP33:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8
2659 // CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
2660 // CHECK6-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP33]] to i8*
2661 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false)
2662 // CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[SVAR8]], align 4
2663 // CHECK6-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 8
2664 // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2665 // CHECK6: .omp.lastprivate.done:
2666 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
2667 // CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
2668 // CHECK6-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
2669 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2670 // CHECK6: arraydestroy.body:
2671 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2672 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2673 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2674 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
2675 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
2676 // CHECK6: arraydestroy.done15:
2677 // CHECK6-NEXT: ret void
2678 //
2679 //
2680 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1
2681 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] {
2682 // CHECK6-NEXT: entry:
2683 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2684 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2685 // CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2686 // CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2687 // CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
2688 // CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
2689 // CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
2690 // CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
2691 // CHECK6-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
2692 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8
2693 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2694 // CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
2695 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2696 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2697 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2698 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2699 // CHECK6-NEXT: [[T_VAR5:%.*]] = alloca i32, align 4
2700 // CHECK6-NEXT: [[VEC6:%.*]] = alloca [2 x i32], align 4
2701 // CHECK6-NEXT: [[S_ARR7:%.*]] = alloca [2 x %struct.S], align 4
2702 // CHECK6-NEXT: [[VAR8:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2703 // CHECK6-NEXT: [[_TMP9:%.*]] = alloca %struct.S*, align 8
2704 // CHECK6-NEXT: [[SVAR10:%.*]] = alloca i32, align 4
2705 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
2706 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2707 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2708 // CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2709 // CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2710 // CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2711 // CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
2712 // CHECK6-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
2713 // CHECK6-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
2714 // CHECK6-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8
2715 // CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2716 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
2717 // CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
2718 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
2719 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32*
2720 // CHECK6-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8
2721 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2722 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2723 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2724 // CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP3]] to i32
2725 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2726 // CHECK6-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP4]] to i32
2727 // CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4
2728 // CHECK6-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4
2729 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2730 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2731 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0
2732 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
2733 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2734 // CHECK6: arrayctor.loop:
2735 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2736 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2737 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
2738 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2739 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2740 // CHECK6: arrayctor.cont:
2741 // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8
2742 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]])
2743 // CHECK6-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8
2744 // CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2745 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
2746 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2747 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2748 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
2749 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2750 // CHECK6: cond.true:
2751 // CHECK6-NEXT: br label [[COND_END:%.*]]
2752 // CHECK6: cond.false:
2753 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2754 // CHECK6-NEXT: br label [[COND_END]]
2755 // CHECK6: cond.end:
2756 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
2757 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2758 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2759 // CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
2760 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2761 // CHECK6: omp.inner.for.cond:
2762 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2763 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2764 // CHECK6-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
2765 // CHECK6-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2766 // CHECK6: omp.inner.for.cond.cleanup:
2767 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2768 // CHECK6: omp.inner.for.body:
2769 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2770 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
2771 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2772 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2773 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR5]], align 4
2774 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
2775 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
2776 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC6]], i64 0, i64 [[IDXPROM]]
2777 // CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
2778 // CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
2779 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
2780 // CHECK6-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP17]] to i64
2781 // CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i64 0, i64 [[IDXPROM12]]
2782 // CHECK6-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX13]] to i8*
2783 // CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8*
2784 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
2785 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2786 // CHECK6: omp.body.continue:
2787 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2788 // CHECK6: omp.inner.for.inc:
2789 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2790 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP20]], 1
2791 // CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4
2792 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]
2793 // CHECK6: omp.inner.for.end:
2794 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2795 // CHECK6: omp.loop.exit:
2796 // CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2797 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
2798 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
2799 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2800 // CHECK6-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
2801 // CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2802 // CHECK6: .omp.lastprivate.then:
2803 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR5]], align 4
2804 // CHECK6-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
2805 // CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2806 // CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC6]] to i8*
2807 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
2808 // CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
2809 // CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR7]] to %struct.S*
2810 // CHECK6-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2
2811 // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN15]], [[TMP29]]
2812 // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE16:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2813 // CHECK6: omp.arraycpy.body:
2814 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2815 // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN15]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2816 // CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
2817 // CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
2818 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false)
2819 // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2820 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2821 // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
2822 // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_BODY]]
2823 // CHECK6: omp.arraycpy.done16:
2824 // CHECK6-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8
2825 // CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8*
2826 // CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
2827 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
2828 // CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR10]], align 4
2829 // CHECK6-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8
2830 // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2831 // CHECK6: .omp.lastprivate.done:
2832 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]]
2833 // CHECK6-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0
2834 // CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2
2835 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2836 // CHECK6: arraydestroy.body:
2837 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2838 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2839 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2840 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN17]]
2841 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY]]
2842 // CHECK6: arraydestroy.done18:
2843 // CHECK6-NEXT: ret void
2844 //
2845 //
2846 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2847 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2848 // CHECK6-NEXT: entry:
2849 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2850 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2851 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2852 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2853 // CHECK6-NEXT: ret void
2854 //
2855 //
2856 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2857 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat {
2858 // CHECK6-NEXT: entry:
2859 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2860 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2861 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2862 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2863 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2864 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
2865 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
2866 // CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
2867 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
2868 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
2869 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
2870 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2871 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2872 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4
2873 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2874 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
2875 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
2876 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
2877 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
2878 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
2879 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
2880 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
2881 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
2882 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
2883 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
2884 // CHECK6-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
2885 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
2886 // CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
2887 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2888 // CHECK6-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
2889 // CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8
2890 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2891 // CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
2892 // CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8
2893 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2894 // CHECK6-NEXT: store i8* null, i8** [[TMP9]], align 8
2895 // CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2896 // CHECK6-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
2897 // CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
2898 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2899 // CHECK6-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
2900 // CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
2901 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2902 // CHECK6-NEXT: store i8* null, i8** [[TMP14]], align 8
2903 // CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2904 // CHECK6-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
2905 // CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8
2906 // CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2907 // CHECK6-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
2908 // CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
2909 // CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2910 // CHECK6-NEXT: store i8* null, i8** [[TMP19]], align 8
2911 // CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2912 // CHECK6-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
2913 // CHECK6-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8
2914 // CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2915 // CHECK6-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
2916 // CHECK6-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8
2917 // CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2918 // CHECK6-NEXT: store i8* null, i8** [[TMP24]], align 8
2919 // CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2920 // CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2921 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
2922 // CHECK6-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2923 // CHECK6-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2924 // CHECK6-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2925 // CHECK6: omp_offload.failed:
2926 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]]
2927 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
2928 // CHECK6: omp_offload.cont:
2929 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
2930 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2931 // CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2932 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2933 // CHECK6: arraydestroy.body:
2934 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2935 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2936 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2937 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2938 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
2939 // CHECK6: arraydestroy.done2:
2940 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2941 // CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4
2942 // CHECK6-NEXT: ret i32 [[TMP30]]
2943 //
2944 //
2945 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2946 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2947 // CHECK6-NEXT: entry:
2948 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2949 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2950 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2951 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2952 // CHECK6-NEXT: store float 0.000000e+00, float* [[F]], align 4
2953 // CHECK6-NEXT: ret void
2954 //
2955 //
2956 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2957 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2958 // CHECK6-NEXT: entry:
2959 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2960 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2961 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2962 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2963 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2964 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2965 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2966 // CHECK6-NEXT: store float [[TMP0]], float* [[F]], align 4
2967 // CHECK6-NEXT: ret void
2968 //
2969 //
2970 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2971 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2972 // CHECK6-NEXT: entry:
2973 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2974 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2975 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2976 // CHECK6-NEXT: ret void
2977 //
2978 //
2979 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2980 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2981 // CHECK6-NEXT: entry:
2982 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2983 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2984 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2985 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2986 // CHECK6-NEXT: ret void
2987 //
2988 //
2989 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2990 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2991 // CHECK6-NEXT: entry:
2992 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2993 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2994 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2995 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2996 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2997 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2998 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
2999 // CHECK6-NEXT: ret void
3000 //
3001 //
3002 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50
3003 // CHECK6-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
3004 // CHECK6-NEXT: entry:
3005 // CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
3006 // CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
3007 // CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
3008 // CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
3009 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
3010 // CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
3011 // CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
3012 // CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
3013 // CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3014 // CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
3015 // CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
3016 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
3017 // CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3018 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
3019 // CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
3020 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
3021 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
3022 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
3023 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
3024 // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
3025 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
3026 // CHECK6-NEXT: ret void
3027 //
3028 //
3029 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2
3030 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
3031 // CHECK6-NEXT: entry:
3032 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3033 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3034 // CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
3035 // CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
3036 // CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
3037 // CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
3038 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
3039 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3040 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3041 // CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3042 // CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3043 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3044 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3045 // CHECK6-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
3046 // CHECK6-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
3047 // CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
3048 // CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3049 // CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
3050 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
3051 // CHECK6-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
3052 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3053 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3054 // CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
3055 // CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
3056 // CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3057 // CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
3058 // CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
3059 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
3060 // CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3061 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
3062 // CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
3063 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3064 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
3065 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3066 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3067 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3068 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
3069 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3070 // CHECK6: arrayctor.loop:
3071 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3072 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3073 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
3074 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3075 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3076 // CHECK6: arrayctor.cont:
3077 // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
3078 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
3079 // CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
3080 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3081 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3082 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3083 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3084 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
3085 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3086 // CHECK6: cond.true:
3087 // CHECK6-NEXT: br label [[COND_END:%.*]]
3088 // CHECK6: cond.false:
3089 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3090 // CHECK6-NEXT: br label [[COND_END]]
3091 // CHECK6: cond.end:
3092 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3093 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3094 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3095 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
3096 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3097 // CHECK6: omp.inner.for.cond:
3098 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3099 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3100 // CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3101 // CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3102 // CHECK6: omp.inner.for.cond.cleanup:
3103 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3104 // CHECK6: omp.inner.for.body:
3105 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3106 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
3107 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3108 // CHECK6-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
3109 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4
3110 // CHECK6-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
3111 // CHECK6-NEXT: store i32 [[TMP15]], i32* [[CONV8]], align 4
3112 // CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
3113 // CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8
3114 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC3]], i64 [[TMP16]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP17]])
3115 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3116 // CHECK6: omp.inner.for.inc:
3117 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3118 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3119 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
3120 // CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3121 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]
3122 // CHECK6: omp.inner.for.end:
3123 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3124 // CHECK6: omp.loop.exit:
3125 // CHECK6-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3126 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4
3127 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
3128 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3129 // CHECK6-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
3130 // CHECK6-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
3131 // CHECK6: .omp.lastprivate.then:
3132 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4
3133 // CHECK6-NEXT: store i32 [[TMP24]], i32* [[CONV]], align 8
3134 // CHECK6-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3135 // CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
3136 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 8, i1 false)
3137 // CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
3138 // CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
3139 // CHECK6-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2
3140 // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN9]], [[TMP28]]
3141 // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3142 // CHECK6: omp.arraycpy.body:
3143 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3144 // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3145 // CHECK6-NEXT: [[TMP29:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
3146 // CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
3147 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false)
3148 // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3149 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3150 // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]]
3151 // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]]
3152 // CHECK6: omp.arraycpy.done10:
3153 // CHECK6-NEXT: [[TMP31:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8
3154 // CHECK6-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8*
3155 // CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP31]] to i8*
3156 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false)
3157 // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
3158 // CHECK6: .omp.lastprivate.done:
3159 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
3160 // CHECK6-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3161 // CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2
3162 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3163 // CHECK6: arraydestroy.body:
3164 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3165 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3166 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
3167 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
3168 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
3169 // CHECK6: arraydestroy.done12:
3170 // CHECK6-NEXT: ret void
3171 //
3172 //
3173 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3
3174 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
3175 // CHECK6-NEXT: entry:
3176 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3177 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3178 // CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
3179 // CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
3180 // CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
3181 // CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
3182 // CHECK6-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
3183 // CHECK6-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
3184 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
3185 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3186 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3187 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3188 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3189 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3190 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3191 // CHECK6-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4
3192 // CHECK6-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4
3193 // CHECK6-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4
3194 // CHECK6-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3195 // CHECK6-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8
3196 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
3197 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3198 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3199 // CHECK6-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
3200 // CHECK6-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
3201 // CHECK6-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
3202 // CHECK6-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
3203 // CHECK6-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3204 // CHECK6-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
3205 // CHECK6-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
3206 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
3207 // CHECK6-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3208 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
3209 // CHECK6-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
3210 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3211 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3212 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
3213 // CHECK6-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
3214 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
3215 // CHECK6-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
3216 // CHECK6-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
3217 // CHECK6-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
3218 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3219 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3220 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0
3221 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
3222 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3223 // CHECK6: arrayctor.loop:
3224 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3225 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3226 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
3227 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3228 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3229 // CHECK6: arrayctor.cont:
3230 // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
3231 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]])
3232 // CHECK6-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8
3233 // CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3234 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
3235 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3236 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3237 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
3238 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3239 // CHECK6: cond.true:
3240 // CHECK6-NEXT: br label [[COND_END:%.*]]
3241 // CHECK6: cond.false:
3242 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3243 // CHECK6-NEXT: br label [[COND_END]]
3244 // CHECK6: cond.end:
3245 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
3246 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3247 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3248 // CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
3249 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3250 // CHECK6: omp.inner.for.cond:
3251 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3252 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3253 // CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
3254 // CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3255 // CHECK6: omp.inner.for.cond.cleanup:
3256 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3257 // CHECK6: omp.inner.for.body:
3258 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3259 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
3260 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3261 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3262 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR4]], align 4
3263 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
3264 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
3265 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]]
3266 // CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
3267 // CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8
3268 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
3269 // CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64
3270 // CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i64 0, i64 [[IDXPROM10]]
3271 // CHECK6-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8*
3272 // CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8*
3273 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false)
3274 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3275 // CHECK6: omp.body.continue:
3276 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3277 // CHECK6: omp.inner.for.inc:
3278 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3279 // CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1
3280 // CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
3281 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]
3282 // CHECK6: omp.inner.for.end:
3283 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3284 // CHECK6: omp.loop.exit:
3285 // CHECK6-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3286 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
3287 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
3288 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3289 // CHECK6-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
3290 // CHECK6-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
3291 // CHECK6: .omp.lastprivate.then:
3292 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR4]], align 4
3293 // CHECK6-NEXT: store i32 [[TMP25]], i32* [[CONV]], align 8
3294 // CHECK6-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3295 // CHECK6-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC5]] to i8*
3296 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 8, i1 false)
3297 // CHECK6-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
3298 // CHECK6-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR6]] to %struct.S.0*
3299 // CHECK6-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2
3300 // CHECK6-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN13]], [[TMP29]]
3301 // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3302 // CHECK6: omp.arraycpy.body:
3303 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3304 // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3305 // CHECK6-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
3306 // CHECK6-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
3307 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i64 4, i1 false)
3308 // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3309 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3310 // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
3311 // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]]
3312 // CHECK6: omp.arraycpy.done14:
3313 // CHECK6-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8
3314 // CHECK6-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8*
3315 // CHECK6-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8*
3316 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false)
3317 // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
3318 // CHECK6: .omp.lastprivate.done:
3319 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]]
3320 // CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0
3321 // CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN15]], i64 2
3322 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3323 // CHECK6: arraydestroy.body:
3324 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3325 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3326 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
3327 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
3328 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
3329 // CHECK6: arraydestroy.done16:
3330 // CHECK6-NEXT: ret void
3331 //
3332 //
3333 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3334 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3335 // CHECK6-NEXT: entry:
3336 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3337 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3338 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3339 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
3340 // CHECK6-NEXT: ret void
3341 //
3342 //
3343 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3344 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3345 // CHECK6-NEXT: entry:
3346 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3347 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3348 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3349 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3350 // CHECK6-NEXT: store i32 0, i32* [[F]], align 4
3351 // CHECK6-NEXT: ret void
3352 //
3353 //
3354 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3355 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3356 // CHECK6-NEXT: entry:
3357 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3358 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3359 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3360 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3361 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3362 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3363 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3364 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3365 // CHECK6-NEXT: ret void
3366 //
3367 //
3368 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3369 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3370 // CHECK6-NEXT: entry:
3371 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3372 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3373 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3374 // CHECK6-NEXT: ret void
3375 //
3376 //
3377 // CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3378 // CHECK6-SAME: () #[[ATTR6:[0-9]+]] {
3379 // CHECK6-NEXT: entry:
3380 // CHECK6-NEXT: call void @__tgt_register_requires(i64 1)
3381 // CHECK6-NEXT: ret void
3382 //
3383 //
3384 // CHECK7-LABEL: define {{[^@]+}}@main
3385 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
3386 // CHECK7-NEXT: entry:
3387 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3388 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8
3389 // CHECK7-NEXT: [[G1:%.*]] = alloca double*, align 4
3390 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3391 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3392 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3393 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
3394 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4
3395 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
3396 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3397 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
3398 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
3399 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
3400 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
3401 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3402 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
3403 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
3404 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4
3405 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
3406 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
3407 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3408 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false)
3409 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3410 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00)
3411 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1
3412 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)
3413 // CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4
3414 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4
3415 // CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4
3416 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
3417 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
3418 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3419 // CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
3420 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4
3421 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4
3422 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
3423 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3424 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
3425 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4
3426 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3427 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
3428 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 4
3429 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3430 // CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4
3431 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3432 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
3433 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
3434 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3435 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
3436 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
3437 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3438 // CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4
3439 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3440 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]**
3441 // CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4
3442 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3443 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]**
3444 // CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4
3445 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3446 // CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4
3447 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3448 // CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S**
3449 // CHECK7-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 4
3450 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3451 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S**
3452 // CHECK7-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 4
3453 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3454 // CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4
3455 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3456 // CHECK7-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
3457 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP28]], align 4
3458 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3459 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
3460 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4
3461 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3462 // CHECK7-NEXT: store i8* null, i8** [[TMP31]], align 4
3463 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3464 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3465 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
3466 // CHECK7-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3467 // CHECK7-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
3468 // CHECK7-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3469 // CHECK7: omp_offload.failed:
3470 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]]
3471 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
3472 // CHECK7: omp_offload.cont:
3473 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
3474 // CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
3475 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3476 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
3477 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3478 // CHECK7: arraydestroy.body:
3479 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3480 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3481 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
3482 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
3483 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
3484 // CHECK7: arraydestroy.done2:
3485 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
3486 // CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4
3487 // CHECK7-NEXT: ret i32 [[TMP37]]
3488 //
3489 //
3490 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3491 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3492 // CHECK7-NEXT: entry:
3493 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3494 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3495 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3496 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3497 // CHECK7-NEXT: ret void
3498 //
3499 //
3500 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3501 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3502 // CHECK7-NEXT: entry:
3503 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3504 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3505 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3506 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3507 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3508 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3509 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3510 // CHECK7-NEXT: ret void
3511 //
3512 //
3513 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
3514 // CHECK7-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
3515 // CHECK7-NEXT: entry:
3516 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3517 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3518 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
3519 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
3520 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
3521 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
3522 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3523 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
3524 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3525 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3526 // CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3527 // CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
3528 // CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
3529 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3530 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3531 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
3532 // CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4
3533 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3534 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
3535 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3536 // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
3537 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_ADDR]], align 4
3538 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[SVAR_CASTED]], align 4
3539 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
3540 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i32 [[TMP7]])
3541 // CHECK7-NEXT: ret void
3542 //
3543 //
3544 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined.
3545 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] {
3546 // CHECK7-NEXT: entry:
3547 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3548 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3549 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3550 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3551 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
3552 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
3553 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
3554 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
3555 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3556 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3557 // CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3558 // CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3559 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3560 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3561 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
3562 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
3563 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
3564 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3565 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4
3566 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4
3567 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
3568 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3569 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
3570 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3571 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3572 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3573 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3574 // CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3575 // CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
3576 // CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
3577 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3578 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3579 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
3580 // CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4
3581 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3582 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
3583 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3584 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3585 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
3586 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
3587 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3588 // CHECK7: arrayctor.loop:
3589 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3590 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3591 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
3592 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3593 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3594 // CHECK7: arrayctor.cont:
3595 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
3596 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]])
3597 // CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4
3598 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3599 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3600 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3601 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3602 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
3603 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3604 // CHECK7: cond.true:
3605 // CHECK7-NEXT: br label [[COND_END:%.*]]
3606 // CHECK7: cond.false:
3607 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3608 // CHECK7-NEXT: br label [[COND_END]]
3609 // CHECK7: cond.end:
3610 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3611 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3612 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3613 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
3614 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3615 // CHECK7: omp.inner.for.cond:
3616 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3617 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3618 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3619 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3620 // CHECK7: omp.inner.for.cond.cleanup:
3621 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3622 // CHECK7: omp.inner.for.body:
3623 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3624 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3625 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4
3626 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4
3627 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3628 // CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
3629 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[SVAR7]], align 4
3630 // CHECK7-NEXT: store i32 [[TMP16]], i32* [[SVAR_CASTED]], align 4
3631 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
3632 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32 [[TMP17]])
3633 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3634 // CHECK7: omp.inner.for.inc:
3635 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3636 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3637 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
3638 // CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3639 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
3640 // CHECK7: omp.inner.for.end:
3641 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3642 // CHECK7: omp.loop.exit:
3643 // CHECK7-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3644 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4
3645 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
3646 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3647 // CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
3648 // CHECK7-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
3649 // CHECK7: .omp.lastprivate.then:
3650 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4
3651 // CHECK7-NEXT: store i32 [[TMP24]], i32* [[T_VAR_ADDR]], align 4
3652 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3653 // CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
3654 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 8, i1 false)
3655 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
3656 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S*
3657 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2
3658 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP28]]
3659 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3660 // CHECK7: omp.arraycpy.body:
3661 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3662 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3663 // CHECK7-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
3664 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
3665 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false)
3666 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3667 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3668 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]]
3669 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]]
3670 // CHECK7: omp.arraycpy.done10:
3671 // CHECK7-NEXT: [[TMP31:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
3672 // CHECK7-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
3673 // CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP31]] to i8*
3674 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false)
3675 // CHECK7-NEXT: [[TMP34:%.*]] = load i32, i32* [[SVAR7]], align 4
3676 // CHECK7-NEXT: store i32 [[TMP34]], i32* [[SVAR_ADDR]], align 4
3677 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
3678 // CHECK7: .omp.lastprivate.done:
3679 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
3680 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
3681 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2
3682 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3683 // CHECK7: arraydestroy.body:
3684 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3685 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3686 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
3687 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
3688 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
3689 // CHECK7: arraydestroy.done12:
3690 // CHECK7-NEXT: ret void
3691 //
3692 //
3693 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1
3694 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] {
3695 // CHECK7-NEXT: entry:
3696 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3697 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3698 // CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3699 // CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3700 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3701 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3702 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
3703 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
3704 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
3705 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
3706 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3707 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3708 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3709 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3710 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3711 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3712 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
3713 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
3714 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
3715 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3716 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4
3717 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4
3718 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
3719 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3720 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3721 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3722 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3723 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3724 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3725 // CHECK7-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3726 // CHECK7-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
3727 // CHECK7-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
3728 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3729 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3730 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
3731 // CHECK7-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4
3732 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3733 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3734 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3735 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3736 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
3737 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
3738 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3739 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3740 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
3741 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
3742 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3743 // CHECK7: arrayctor.loop:
3744 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3745 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3746 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
3747 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3748 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3749 // CHECK7: arrayctor.cont:
3750 // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
3751 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]])
3752 // CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4
3753 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3754 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
3755 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3756 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3757 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
3758 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3759 // CHECK7: cond.true:
3760 // CHECK7-NEXT: br label [[COND_END:%.*]]
3761 // CHECK7: cond.false:
3762 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3763 // CHECK7-NEXT: br label [[COND_END]]
3764 // CHECK7: cond.end:
3765 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
3766 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3767 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3768 // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
3769 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3770 // CHECK7: omp.inner.for.cond:
3771 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3772 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3773 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
3774 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3775 // CHECK7: omp.inner.for.cond.cleanup:
3776 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3777 // CHECK7: omp.inner.for.body:
3778 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3779 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
3780 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3781 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3782 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4
3783 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
3784 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]]
3785 // CHECK7-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
3786 // CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
3787 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
3788 // CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]]
3789 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
3790 // CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8*
3791 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)
3792 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3793 // CHECK7: omp.body.continue:
3794 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3795 // CHECK7: omp.inner.for.inc:
3796 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3797 // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
3798 // CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
3799 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
3800 // CHECK7: omp.inner.for.end:
3801 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3802 // CHECK7: omp.loop.exit:
3803 // CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3804 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
3805 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
3806 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3807 // CHECK7-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
3808 // CHECK7-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
3809 // CHECK7: .omp.lastprivate.then:
3810 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4
3811 // CHECK7-NEXT: store i32 [[TMP25]], i32* [[T_VAR_ADDR]], align 4
3812 // CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3813 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
3814 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false)
3815 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
3816 // CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S*
3817 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2
3818 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP29]]
3819 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3820 // CHECK7: omp.arraycpy.body:
3821 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3822 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3823 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
3824 // CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
3825 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false)
3826 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3827 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3828 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
3829 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]]
3830 // CHECK7: omp.arraycpy.done12:
3831 // CHECK7-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
3832 // CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8*
3833 // CHECK7-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
3834 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false)
3835 // CHECK7-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4
3836 // CHECK7-NEXT: store i32 [[TMP35]], i32* [[SVAR_ADDR]], align 4
3837 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
3838 // CHECK7: .omp.lastprivate.done:
3839 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
3840 // CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
3841 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2
3842 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3843 // CHECK7: arraydestroy.body:
3844 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3845 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3846 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
3847 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
3848 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
3849 // CHECK7: arraydestroy.done14:
3850 // CHECK7-NEXT: ret void
3851 //
3852 //
3853 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3854 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3855 // CHECK7-NEXT: entry:
3856 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3857 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3858 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3859 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
3860 // CHECK7-NEXT: ret void
3861 //
3862 //
3863 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3864 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
3865 // CHECK7-NEXT: entry:
3866 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3867 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3868 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3869 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3870 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3871 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
3872 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
3873 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3874 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
3875 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
3876 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
3877 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3878 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3879 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
3880 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3881 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
3882 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3883 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
3884 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
3885 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
3886 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
3887 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
3888 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
3889 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
3890 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
3891 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3892 // CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3893 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3894 // CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
3895 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4
3896 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3897 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
3898 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4
3899 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3900 // CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 4
3901 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3902 // CHECK7-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
3903 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
3904 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3905 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
3906 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
3907 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3908 // CHECK7-NEXT: store i8* null, i8** [[TMP14]], align 4
3909 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3910 // CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
3911 // CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4
3912 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3913 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
3914 // CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
3915 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3916 // CHECK7-NEXT: store i8* null, i8** [[TMP19]], align 4
3917 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3918 // CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
3919 // CHECK7-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4
3920 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3921 // CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
3922 // CHECK7-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4
3923 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3924 // CHECK7-NEXT: store i8* null, i8** [[TMP24]], align 4
3925 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3926 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3927 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
3928 // CHECK7-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3929 // CHECK7-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3930 // CHECK7-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3931 // CHECK7: omp_offload.failed:
3932 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]]
3933 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
3934 // CHECK7: omp_offload.cont:
3935 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
3936 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3937 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3938 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3939 // CHECK7: arraydestroy.body:
3940 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3941 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3942 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
3943 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
3944 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
3945 // CHECK7: arraydestroy.done2:
3946 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
3947 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4
3948 // CHECK7-NEXT: ret i32 [[TMP30]]
3949 //
3950 //
3951 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3952 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3953 // CHECK7-NEXT: entry:
3954 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3955 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3956 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3957 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3958 // CHECK7-NEXT: store float 0.000000e+00, float* [[F]], align 4
3959 // CHECK7-NEXT: ret void
3960 //
3961 //
3962 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3963 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3964 // CHECK7-NEXT: entry:
3965 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3966 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3967 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3968 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3969 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3970 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3971 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3972 // CHECK7-NEXT: store float [[TMP0]], float* [[F]], align 4
3973 // CHECK7-NEXT: ret void
3974 //
3975 //
3976 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3977 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3978 // CHECK7-NEXT: entry:
3979 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3980 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3981 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3982 // CHECK7-NEXT: ret void
3983 //
3984 //
3985 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3986 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3987 // CHECK7-NEXT: entry:
3988 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3989 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3990 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3991 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3992 // CHECK7-NEXT: ret void
3993 //
3994 //
3995 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3996 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3997 // CHECK7-NEXT: entry:
3998 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3999 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4000 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4001 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4002 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4003 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4004 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
4005 // CHECK7-NEXT: ret void
4006 //
4007 //
4008 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50
4009 // CHECK7-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
4010 // CHECK7-NEXT: entry:
4011 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4012 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4013 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4014 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4015 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4016 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4017 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4018 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4019 // CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4020 // CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4021 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4022 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4023 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4024 // CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4025 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
4026 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
4027 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4028 // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4029 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
4030 // CHECK7-NEXT: ret void
4031 //
4032 //
4033 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2
4034 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
4035 // CHECK7-NEXT: entry:
4036 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4037 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4038 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4039 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4040 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4041 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4042 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4043 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4044 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4045 // CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4046 // CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4047 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4048 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4049 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
4050 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
4051 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
4052 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4053 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
4054 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
4055 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4056 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4057 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4058 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4059 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4060 // CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4061 // CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4062 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4063 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4064 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4065 // CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4066 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
4067 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
4068 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4069 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4070 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
4071 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4072 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
4073 // CHECK7: arrayctor.loop:
4074 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
4075 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
4076 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
4077 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
4078 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
4079 // CHECK7: arrayctor.cont:
4080 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4081 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
4082 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
4083 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4084 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
4085 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4086 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4087 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
4088 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4089 // CHECK7: cond.true:
4090 // CHECK7-NEXT: br label [[COND_END:%.*]]
4091 // CHECK7: cond.false:
4092 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4093 // CHECK7-NEXT: br label [[COND_END]]
4094 // CHECK7: cond.end:
4095 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
4096 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
4097 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4098 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
4099 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4100 // CHECK7: omp.inner.for.cond:
4101 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4102 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4103 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
4104 // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4105 // CHECK7: omp.inner.for.cond.cleanup:
4106 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
4107 // CHECK7: omp.inner.for.body:
4108 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4109 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4110 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4
4111 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4
4112 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4113 // CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
4114 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP15]])
4115 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4116 // CHECK7: omp.inner.for.inc:
4117 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4118 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4119 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
4120 // CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4121 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
4122 // CHECK7: omp.inner.for.end:
4123 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4124 // CHECK7: omp.loop.exit:
4125 // CHECK7-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4126 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
4127 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
4128 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4129 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
4130 // CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
4131 // CHECK7: .omp.lastprivate.then:
4132 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 4
4133 // CHECK7-NEXT: store i32 [[TMP22]], i32* [[T_VAR_ADDR]], align 4
4134 // CHECK7-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4135 // CHECK7-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
4136 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false)
4137 // CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
4138 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
4139 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2
4140 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP26]]
4141 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4142 // CHECK7: omp.arraycpy.body:
4143 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4144 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4145 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
4146 // CHECK7-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
4147 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false)
4148 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4149 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4150 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]]
4151 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]]
4152 // CHECK7: omp.arraycpy.done9:
4153 // CHECK7-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
4154 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8*
4155 // CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8*
4156 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false)
4157 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
4158 // CHECK7: .omp.lastprivate.done:
4159 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
4160 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
4161 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2
4162 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4163 // CHECK7: arraydestroy.body:
4164 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4165 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4166 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
4167 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
4168 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
4169 // CHECK7: arraydestroy.done11:
4170 // CHECK7-NEXT: ret void
4171 //
4172 //
4173 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3
4174 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
4175 // CHECK7-NEXT: entry:
4176 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4177 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4178 // CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
4179 // CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
4180 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4181 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4182 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4183 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4184 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4185 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4186 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4187 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4188 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4189 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4190 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4191 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
4192 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
4193 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
4194 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4195 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
4196 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
4197 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4198 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4199 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4200 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4201 // CHECK7-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4202 // CHECK7-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4203 // CHECK7-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4204 // CHECK7-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4205 // CHECK7-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4206 // CHECK7-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4207 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4208 // CHECK7-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4209 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4210 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4211 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4212 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4213 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
4214 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
4215 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4216 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4217 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
4218 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4219 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
4220 // CHECK7: arrayctor.loop:
4221 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
4222 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
4223 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
4224 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
4225 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
4226 // CHECK7: arrayctor.cont:
4227 // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4228 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
4229 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
4230 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4231 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
4232 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4233 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4234 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
4235 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4236 // CHECK7: cond.true:
4237 // CHECK7-NEXT: br label [[COND_END:%.*]]
4238 // CHECK7: cond.false:
4239 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4240 // CHECK7-NEXT: br label [[COND_END]]
4241 // CHECK7: cond.end:
4242 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
4243 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4244 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4245 // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
4246 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4247 // CHECK7: omp.inner.for.cond:
4248 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4249 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4250 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
4251 // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4252 // CHECK7: omp.inner.for.cond.cleanup:
4253 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
4254 // CHECK7: omp.inner.for.body:
4255 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4256 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
4257 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4258 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4
4259 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4
4260 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
4261 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]]
4262 // CHECK7-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
4263 // CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
4264 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
4265 // CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP17]]
4266 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
4267 // CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8*
4268 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)
4269 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4270 // CHECK7: omp.body.continue:
4271 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4272 // CHECK7: omp.inner.for.inc:
4273 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4274 // CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
4275 // CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
4276 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
4277 // CHECK7: omp.inner.for.end:
4278 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4279 // CHECK7: omp.loop.exit:
4280 // CHECK7-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4281 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
4282 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
4283 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4284 // CHECK7-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
4285 // CHECK7-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
4286 // CHECK7: .omp.lastprivate.then:
4287 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4
4288 // CHECK7-NEXT: store i32 [[TMP25]], i32* [[T_VAR_ADDR]], align 4
4289 // CHECK7-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4290 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
4291 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false)
4292 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
4293 // CHECK7-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
4294 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2
4295 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP29]]
4296 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4297 // CHECK7: omp.arraycpy.body:
4298 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4299 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4300 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
4301 // CHECK7-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
4302 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false)
4303 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4304 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4305 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
4306 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]]
4307 // CHECK7: omp.arraycpy.done11:
4308 // CHECK7-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
4309 // CHECK7-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8*
4310 // CHECK7-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8*
4311 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false)
4312 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
4313 // CHECK7: .omp.lastprivate.done:
4314 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
4315 // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
4316 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2
4317 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4318 // CHECK7: arraydestroy.body:
4319 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4320 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4321 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
4322 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
4323 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
4324 // CHECK7: arraydestroy.done13:
4325 // CHECK7-NEXT: ret void
4326 //
4327 //
4328 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4329 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4330 // CHECK7-NEXT: entry:
4331 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4332 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4333 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4334 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
4335 // CHECK7-NEXT: ret void
4336 //
4337 //
4338 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
4339 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4340 // CHECK7-NEXT: entry:
4341 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4342 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4343 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4344 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4345 // CHECK7-NEXT: store i32 0, i32* [[F]], align 4
4346 // CHECK7-NEXT: ret void
4347 //
4348 //
4349 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
4350 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4351 // CHECK7-NEXT: entry:
4352 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4353 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4354 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4355 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4356 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4357 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4358 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4359 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
4360 // CHECK7-NEXT: ret void
4361 //
4362 //
4363 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
4364 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4365 // CHECK7-NEXT: entry:
4366 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4367 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4368 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4369 // CHECK7-NEXT: ret void
4370 //
4371 //
4372 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4373 // CHECK7-SAME: () #[[ATTR6:[0-9]+]] {
4374 // CHECK7-NEXT: entry:
4375 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1)
4376 // CHECK7-NEXT: ret void
4377 //
4378 //
4379 // CHECK8-LABEL: define {{[^@]+}}@main
4380 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
4381 // CHECK8-NEXT: entry:
4382 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4383 // CHECK8-NEXT: [[G:%.*]] = alloca double, align 8
4384 // CHECK8-NEXT: [[G1:%.*]] = alloca double*, align 4
4385 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
4386 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
4387 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
4388 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
4389 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4
4390 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
4391 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4392 // CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
4393 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
4394 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
4395 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
4396 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4397 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
4398 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
4399 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4
4400 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
4401 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4
4402 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
4403 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false)
4404 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
4405 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00)
4406 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1
4407 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)
4408 // CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4
4409 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4
4410 // CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4
4411 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
4412 // CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
4413 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4414 // CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
4415 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4
4416 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4
4417 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
4418 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4419 // CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
4420 // CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4
4421 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4422 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
4423 // CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP10]], align 4
4424 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4425 // CHECK8-NEXT: store i8* null, i8** [[TMP11]], align 4
4426 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4427 // CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4428 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
4429 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4430 // CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
4431 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
4432 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4433 // CHECK8-NEXT: store i8* null, i8** [[TMP16]], align 4
4434 // CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4435 // CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]**
4436 // CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4
4437 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4438 // CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]**
4439 // CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4
4440 // CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4441 // CHECK8-NEXT: store i8* null, i8** [[TMP21]], align 4
4442 // CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4443 // CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S**
4444 // CHECK8-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP23]], align 4
4445 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4446 // CHECK8-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S**
4447 // CHECK8-NEXT: store %struct.S* [[TMP4]], %struct.S** [[TMP25]], align 4
4448 // CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4449 // CHECK8-NEXT: store i8* null, i8** [[TMP26]], align 4
4450 // CHECK8-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
4451 // CHECK8-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
4452 // CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP28]], align 4
4453 // CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
4454 // CHECK8-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
4455 // CHECK8-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4
4456 // CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
4457 // CHECK8-NEXT: store i8* null, i8** [[TMP31]], align 4
4458 // CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4459 // CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4460 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
4461 // CHECK8-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, i32 5, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4462 // CHECK8-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
4463 // CHECK8-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4464 // CHECK8: omp_offload.failed:
4465 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]]
4466 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
4467 // CHECK8: omp_offload.cont:
4468 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
4469 // CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
4470 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
4471 // CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
4472 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4473 // CHECK8: arraydestroy.body:
4474 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4475 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4476 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
4477 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
4478 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
4479 // CHECK8: arraydestroy.done2:
4480 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
4481 // CHECK8-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4
4482 // CHECK8-NEXT: ret i32 [[TMP37]]
4483 //
4484 //
4485 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4486 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4487 // CHECK8-NEXT: entry:
4488 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4489 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4490 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4491 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4492 // CHECK8-NEXT: ret void
4493 //
4494 //
4495 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4496 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4497 // CHECK8-NEXT: entry:
4498 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4499 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4500 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4501 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4502 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4503 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4504 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4505 // CHECK8-NEXT: ret void
4506 //
4507 //
4508 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
4509 // CHECK8-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
4510 // CHECK8-NEXT: entry:
4511 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4512 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4513 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
4514 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
4515 // CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
4516 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
4517 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4518 // CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
4519 // CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4520 // CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4521 // CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4522 // CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
4523 // CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
4524 // CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4525 // CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4526 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
4527 // CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4
4528 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
4529 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
4530 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4531 // CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
4532 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_ADDR]], align 4
4533 // CHECK8-NEXT: store i32 [[TMP6]], i32* [[SVAR_CASTED]], align 4
4534 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
4535 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP5]], i32 [[TMP7]])
4536 // CHECK8-NEXT: ret void
4537 //
4538 //
4539 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined.
4540 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] {
4541 // CHECK8-NEXT: entry:
4542 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4543 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4544 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4545 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4546 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
4547 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
4548 // CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
4549 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
4550 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4551 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4552 // CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4553 // CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4554 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4555 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4556 // CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
4557 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
4558 // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
4559 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
4560 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4
4561 // CHECK8-NEXT: [[SVAR7:%.*]] = alloca i32, align 4
4562 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
4563 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4564 // CHECK8-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
4565 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4566 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4567 // CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4568 // CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4569 // CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4570 // CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
4571 // CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
4572 // CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4573 // CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4574 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
4575 // CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4
4576 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
4577 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
4578 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4579 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4580 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
4581 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
4582 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
4583 // CHECK8: arrayctor.loop:
4584 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
4585 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
4586 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
4587 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
4588 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
4589 // CHECK8: arrayctor.cont:
4590 // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
4591 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]])
4592 // CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4
4593 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4594 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
4595 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4596 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4597 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
4598 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4599 // CHECK8: cond.true:
4600 // CHECK8-NEXT: br label [[COND_END:%.*]]
4601 // CHECK8: cond.false:
4602 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4603 // CHECK8-NEXT: br label [[COND_END]]
4604 // CHECK8: cond.end:
4605 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
4606 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
4607 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4608 // CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
4609 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4610 // CHECK8: omp.inner.for.cond:
4611 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4612 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4613 // CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
4614 // CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4615 // CHECK8: omp.inner.for.cond.cleanup:
4616 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
4617 // CHECK8: omp.inner.for.body:
4618 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4619 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4620 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4
4621 // CHECK8-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4
4622 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4623 // CHECK8-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
4624 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[SVAR7]], align 4
4625 // CHECK8-NEXT: store i32 [[TMP16]], i32* [[SVAR_CASTED]], align 4
4626 // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4
4627 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32 [[TMP17]])
4628 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4629 // CHECK8: omp.inner.for.inc:
4630 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4631 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4632 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
4633 // CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4634 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]]
4635 // CHECK8: omp.inner.for.end:
4636 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4637 // CHECK8: omp.loop.exit:
4638 // CHECK8-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4639 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4
4640 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]])
4641 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4642 // CHECK8-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
4643 // CHECK8-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
4644 // CHECK8: .omp.lastprivate.then:
4645 // CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR2]], align 4
4646 // CHECK8-NEXT: store i32 [[TMP24]], i32* [[T_VAR_ADDR]], align 4
4647 // CHECK8-NEXT: [[TMP25:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4648 // CHECK8-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
4649 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 8, i1 false)
4650 // CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
4651 // CHECK8-NEXT: [[TMP27:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S*
4652 // CHECK8-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2
4653 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN9]], [[TMP28]]
4654 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4655 // CHECK8: omp.arraycpy.body:
4656 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4657 // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4658 // CHECK8-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
4659 // CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
4660 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false)
4661 // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4662 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4663 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP28]]
4664 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]]
4665 // CHECK8: omp.arraycpy.done10:
4666 // CHECK8-NEXT: [[TMP31:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
4667 // CHECK8-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP3]] to i8*
4668 // CHECK8-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP31]] to i8*
4669 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false)
4670 // CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[SVAR7]], align 4
4671 // CHECK8-NEXT: store i32 [[TMP34]], i32* [[SVAR_ADDR]], align 4
4672 // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
4673 // CHECK8: .omp.lastprivate.done:
4674 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
4675 // CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
4676 // CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2
4677 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4678 // CHECK8: arraydestroy.body:
4679 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4680 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4681 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
4682 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
4683 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
4684 // CHECK8: arraydestroy.done12:
4685 // CHECK8-NEXT: ret void
4686 //
4687 //
4688 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1
4689 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] {
4690 // CHECK8-NEXT: entry:
4691 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4692 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4693 // CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
4694 // CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
4695 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4696 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4697 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
4698 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
4699 // CHECK8-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
4700 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4
4701 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4702 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4703 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4704 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4705 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4706 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4707 // CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
4708 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
4709 // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
4710 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
4711 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S*, align 4
4712 // CHECK8-NEXT: [[SVAR7:%.*]] = alloca i32, align 4
4713 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
4714 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4715 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4716 // CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4717 // CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4718 // CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4719 // CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4720 // CHECK8-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4721 // CHECK8-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
4722 // CHECK8-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4
4723 // CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4724 // CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
4725 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
4726 // CHECK8-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4
4727 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4728 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4729 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4730 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4731 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
4732 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
4733 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4734 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4735 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
4736 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
4737 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
4738 // CHECK8: arrayctor.loop:
4739 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
4740 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
4741 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
4742 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
4743 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
4744 // CHECK8: arrayctor.cont:
4745 // CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4
4746 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]])
4747 // CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4
4748 // CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4749 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
4750 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4751 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4752 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
4753 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4754 // CHECK8: cond.true:
4755 // CHECK8-NEXT: br label [[COND_END:%.*]]
4756 // CHECK8: cond.false:
4757 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4758 // CHECK8-NEXT: br label [[COND_END]]
4759 // CHECK8: cond.end:
4760 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
4761 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4762 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4763 // CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
4764 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4765 // CHECK8: omp.inner.for.cond:
4766 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4767 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4768 // CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
4769 // CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4770 // CHECK8: omp.inner.for.cond.cleanup:
4771 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
4772 // CHECK8: omp.inner.for.body:
4773 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4774 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
4775 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4776 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4
4777 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4
4778 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
4779 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]]
4780 // CHECK8-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
4781 // CHECK8-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
4782 // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
4783 // CHECK8-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]]
4784 // CHECK8-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8*
4785 // CHECK8-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8*
4786 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)
4787 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4788 // CHECK8: omp.body.continue:
4789 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4790 // CHECK8: omp.inner.for.inc:
4791 // CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4792 // CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
4793 // CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
4794 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]]
4795 // CHECK8: omp.inner.for.end:
4796 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4797 // CHECK8: omp.loop.exit:
4798 // CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4799 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
4800 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
4801 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4802 // CHECK8-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
4803 // CHECK8-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
4804 // CHECK8: .omp.lastprivate.then:
4805 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4
4806 // CHECK8-NEXT: store i32 [[TMP25]], i32* [[T_VAR_ADDR]], align 4
4807 // CHECK8-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4808 // CHECK8-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
4809 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false)
4810 // CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP1]], i32 0, i32 0
4811 // CHECK8-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S]* [[S_ARR4]] to %struct.S*
4812 // CHECK8-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2
4813 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN11]], [[TMP29]]
4814 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4815 // CHECK8: omp.arraycpy.body:
4816 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4817 // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4818 // CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
4819 // CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
4820 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false)
4821 // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4822 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4823 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
4824 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]]
4825 // CHECK8: omp.arraycpy.done12:
4826 // CHECK8-NEXT: [[TMP32:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4
4827 // CHECK8-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[TMP5]] to i8*
4828 // CHECK8-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP32]] to i8*
4829 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false)
4830 // CHECK8-NEXT: [[TMP35:%.*]] = load i32, i32* [[SVAR7]], align 4
4831 // CHECK8-NEXT: store i32 [[TMP35]], i32* [[SVAR_ADDR]], align 4
4832 // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
4833 // CHECK8: .omp.lastprivate.done:
4834 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
4835 // CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0
4836 // CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2
4837 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4838 // CHECK8: arraydestroy.body:
4839 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4840 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4841 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
4842 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
4843 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
4844 // CHECK8: arraydestroy.done14:
4845 // CHECK8-NEXT: ret void
4846 //
4847 //
4848 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4849 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4850 // CHECK8-NEXT: entry:
4851 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4852 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4853 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4854 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
4855 // CHECK8-NEXT: ret void
4856 //
4857 //
4858 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
4859 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat {
4860 // CHECK8-NEXT: entry:
4861 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4862 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4863 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
4864 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
4865 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
4866 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
4867 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4868 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4869 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
4870 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
4871 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
4872 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4873 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
4874 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4
4875 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
4876 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
4877 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4878 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
4879 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
4880 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
4881 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
4882 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
4883 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
4884 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
4885 // CHECK8-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
4886 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4887 // CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4888 // CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4889 // CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]**
4890 // CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4
4891 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4892 // CHECK8-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]**
4893 // CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4
4894 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4895 // CHECK8-NEXT: store i8* null, i8** [[TMP9]], align 4
4896 // CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4897 // CHECK8-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
4898 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
4899 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4900 // CHECK8-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4901 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
4902 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4903 // CHECK8-NEXT: store i8* null, i8** [[TMP14]], align 4
4904 // CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4905 // CHECK8-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]**
4906 // CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4
4907 // CHECK8-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4908 // CHECK8-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
4909 // CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
4910 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4911 // CHECK8-NEXT: store i8* null, i8** [[TMP19]], align 4
4912 // CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4913 // CHECK8-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0**
4914 // CHECK8-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4
4915 // CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4916 // CHECK8-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
4917 // CHECK8-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4
4918 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4919 // CHECK8-NEXT: store i8* null, i8** [[TMP24]], align 4
4920 // CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4921 // CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4922 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
4923 // CHECK8-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4924 // CHECK8-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
4925 // CHECK8-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4926 // CHECK8: omp_offload.failed:
4927 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]]
4928 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
4929 // CHECK8: omp_offload.cont:
4930 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
4931 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4932 // CHECK8-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4933 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4934 // CHECK8: arraydestroy.body:
4935 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4936 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4937 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
4938 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
4939 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
4940 // CHECK8: arraydestroy.done2:
4941 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
4942 // CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4
4943 // CHECK8-NEXT: ret i32 [[TMP30]]
4944 //
4945 //
4946 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4947 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4948 // CHECK8-NEXT: entry:
4949 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4950 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4951 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4952 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4953 // CHECK8-NEXT: store float 0.000000e+00, float* [[F]], align 4
4954 // CHECK8-NEXT: ret void
4955 //
4956 //
4957 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4958 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4959 // CHECK8-NEXT: entry:
4960 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4961 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4962 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4963 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4964 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4965 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4966 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4967 // CHECK8-NEXT: store float [[TMP0]], float* [[F]], align 4
4968 // CHECK8-NEXT: ret void
4969 //
4970 //
4971 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4972 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4973 // CHECK8-NEXT: entry:
4974 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4975 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4976 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4977 // CHECK8-NEXT: ret void
4978 //
4979 //
4980 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
4981 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4982 // CHECK8-NEXT: entry:
4983 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4984 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4985 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4986 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
4987 // CHECK8-NEXT: ret void
4988 //
4989 //
4990 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
4991 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4992 // CHECK8-NEXT: entry:
4993 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4994 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4995 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4996 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4997 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4998 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4999 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
5000 // CHECK8-NEXT: ret void
5001 //
5002 //
5003 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50
5004 // CHECK8-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
5005 // CHECK8-NEXT: entry:
5006 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
5007 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
5008 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
5009 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
5010 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
5011 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
5012 // CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
5013 // CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
5014 // CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
5015 // CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
5016 // CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
5017 // CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
5018 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
5019 // CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
5020 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
5021 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
5022 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
5023 // CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
5024 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
5025 // CHECK8-NEXT: ret void
5026 //
5027 //
5028 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2
5029 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
5030 // CHECK8-NEXT: entry:
5031 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5032 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5033 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
5034 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
5035 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
5036 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
5037 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
5038 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5039 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
5040 // CHECK8-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
5041 // CHECK8-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
5042 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5043 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5044 // CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
5045 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
5046 // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
5047 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
5048 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
5049 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
5050 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
5051 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5052 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5053 // CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
5054 // CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
5055 // CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
5056 // CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
5057 // CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
5058 // CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
5059 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
5060 // CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
5061 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
5062 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
5063 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5064 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5065 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
5066 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
5067 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
5068 // CHECK8: arrayctor.loop:
5069 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
5070 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
5071 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
5072 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
5073 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
5074 // CHECK8: arrayctor.cont:
5075 // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
5076 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
5077 // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
5078 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5079 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
5080 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5081 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5082 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
5083 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5084 // CHECK8: cond.true:
5085 // CHECK8-NEXT: br label [[COND_END:%.*]]
5086 // CHECK8: cond.false:
5087 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5088 // CHECK8-NEXT: br label [[COND_END]]
5089 // CHECK8: cond.end:
5090 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5091 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
5092 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5093 // CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
5094 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5095 // CHECK8: omp.inner.for.cond:
5096 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5097 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5098 // CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
5099 // CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
5100 // CHECK8: omp.inner.for.cond.cleanup:
5101 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
5102 // CHECK8: omp.inner.for.body:
5103 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
5104 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5105 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4
5106 // CHECK8-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4
5107 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
5108 // CHECK8-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
5109 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP15]])
5110 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5111 // CHECK8: omp.inner.for.inc:
5112 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5113 // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5114 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
5115 // CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
5116 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]]
5117 // CHECK8: omp.inner.for.end:
5118 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5119 // CHECK8: omp.loop.exit:
5120 // CHECK8-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5121 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
5122 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
5123 // CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5124 // CHECK8-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
5125 // CHECK8-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
5126 // CHECK8: .omp.lastprivate.then:
5127 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 4
5128 // CHECK8-NEXT: store i32 [[TMP22]], i32* [[T_VAR_ADDR]], align 4
5129 // CHECK8-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
5130 // CHECK8-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
5131 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i32 8, i1 false)
5132 // CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
5133 // CHECK8-NEXT: [[TMP25:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
5134 // CHECK8-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2
5135 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN8]], [[TMP26]]
5136 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
5137 // CHECK8: omp.arraycpy.body:
5138 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5139 // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5140 // CHECK8-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
5141 // CHECK8-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
5142 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false)
5143 // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
5144 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
5145 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]]
5146 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]]
5147 // CHECK8: omp.arraycpy.done9:
5148 // CHECK8-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
5149 // CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8*
5150 // CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8*
5151 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false)
5152 // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
5153 // CHECK8: .omp.lastprivate.done:
5154 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
5155 // CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
5156 // CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2
5157 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5158 // CHECK8: arraydestroy.body:
5159 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5160 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
5161 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
5162 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
5163 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
5164 // CHECK8: arraydestroy.done11:
5165 // CHECK8-NEXT: ret void
5166 //
5167 //
5168 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3
5169 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
5170 // CHECK8-NEXT: entry:
5171 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5172 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5173 // CHECK8-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
5174 // CHECK8-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
5175 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
5176 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
5177 // CHECK8-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
5178 // CHECK8-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
5179 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
5180 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5181 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
5182 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5183 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5184 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5185 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5186 // CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
5187 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
5188 // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
5189 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
5190 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
5191 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
5192 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5193 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5194 // CHECK8-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
5195 // CHECK8-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
5196 // CHECK8-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
5197 // CHECK8-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
5198 // CHECK8-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
5199 // CHECK8-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
5200 // CHECK8-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
5201 // CHECK8-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
5202 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
5203 // CHECK8-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
5204 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5205 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
5206 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
5207 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
5208 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
5209 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
5210 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5211 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5212 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
5213 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
5214 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
5215 // CHECK8: arrayctor.loop:
5216 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
5217 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
5218 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
5219 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
5220 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
5221 // CHECK8: arrayctor.cont:
5222 // CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
5223 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
5224 // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
5225 // CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5226 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
5227 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5228 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5229 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
5230 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5231 // CHECK8: cond.true:
5232 // CHECK8-NEXT: br label [[COND_END:%.*]]
5233 // CHECK8: cond.false:
5234 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5235 // CHECK8-NEXT: br label [[COND_END]]
5236 // CHECK8: cond.end:
5237 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
5238 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5239 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5240 // CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4
5241 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5242 // CHECK8: omp.inner.for.cond:
5243 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5244 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5245 // CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
5246 // CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
5247 // CHECK8: omp.inner.for.cond.cleanup:
5248 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
5249 // CHECK8: omp.inner.for.body:
5250 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5251 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
5252 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5253 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4
5254 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4
5255 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
5256 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]]
5257 // CHECK8-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4
5258 // CHECK8-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
5259 // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4
5260 // CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP17]]
5261 // CHECK8-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
5262 // CHECK8-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8*
5263 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false)
5264 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5265 // CHECK8: omp.body.continue:
5266 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5267 // CHECK8: omp.inner.for.inc:
5268 // CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5269 // CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
5270 // CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
5271 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]]
5272 // CHECK8: omp.inner.for.end:
5273 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5274 // CHECK8: omp.loop.exit:
5275 // CHECK8-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5276 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4
5277 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
5278 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5279 // CHECK8-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
5280 // CHECK8-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
5281 // CHECK8: .omp.lastprivate.then:
5282 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR2]], align 4
5283 // CHECK8-NEXT: store i32 [[TMP25]], i32* [[T_VAR_ADDR]], align 4
5284 // CHECK8-NEXT: [[TMP26:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
5285 // CHECK8-NEXT: [[TMP27:%.*]] = bitcast [2 x i32]* [[VEC3]] to i8*
5286 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 8, i1 false)
5287 // CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP1]], i32 0, i32 0
5288 // CHECK8-NEXT: [[TMP28:%.*]] = bitcast [2 x %struct.S.0]* [[S_ARR4]] to %struct.S.0*
5289 // CHECK8-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2
5290 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN10]], [[TMP29]]
5291 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
5292 // CHECK8: omp.arraycpy.body:
5293 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5294 // CHECK8-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
5295 // CHECK8-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8*
5296 // CHECK8-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8*
5297 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false)
5298 // CHECK8-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
5299 // CHECK8-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
5300 // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP29]]
5301 // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]]
5302 // CHECK8: omp.arraycpy.done11:
5303 // CHECK8-NEXT: [[TMP32:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4
5304 // CHECK8-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8*
5305 // CHECK8-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP32]] to i8*
5306 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false)
5307 // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
5308 // CHECK8: .omp.lastprivate.done:
5309 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
5310 // CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
5311 // CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2
5312 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5313 // CHECK8: arraydestroy.body:
5314 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5315 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
5316 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
5317 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
5318 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
5319 // CHECK8: arraydestroy.done13:
5320 // CHECK8-NEXT: ret void
5321 //
5322 //
5323 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
5324 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5325 // CHECK8-NEXT: entry:
5326 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5327 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5328 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5329 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
5330 // CHECK8-NEXT: ret void
5331 //
5332 //
5333 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
5334 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5335 // CHECK8-NEXT: entry:
5336 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5337 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5338 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5339 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
5340 // CHECK8-NEXT: store i32 0, i32* [[F]], align 4
5341 // CHECK8-NEXT: ret void
5342 //
5343 //
5344 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
5345 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5346 // CHECK8-NEXT: entry:
5347 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5348 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5349 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5350 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5351 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5352 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
5353 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5354 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
5355 // CHECK8-NEXT: ret void
5356 //
5357 //
5358 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
5359 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5360 // CHECK8-NEXT: entry:
5361 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5362 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5363 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5364 // CHECK8-NEXT: ret void
5365 //
5366 //
5367 // CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5368 // CHECK8-SAME: () #[[ATTR6:[0-9]+]] {
5369 // CHECK8-NEXT: entry:
5370 // CHECK8-NEXT: call void @__tgt_register_requires(i64 1)
5371 // CHECK8-NEXT: ret void
5372 //
5373 //