1 use crate::ir::types::*;
2 use crate::isa::aarch64::inst::*;
3 use crate::isa::test_utils;
4 use crate::isa::CallConv;
5 use crate::settings;
6
7 use alloc::boxed::Box;
8 use alloc::vec::Vec;
9
10 #[test]
test_aarch64_binemit()11 fn test_aarch64_binemit() {
12 let mut insns = Vec::<(Inst, &str, &str)>::new();
13
14 // N.B.: the architecture is little-endian, so when transcribing the 32-bit
15 // hex instructions from e.g. objdump disassembly, one must swap the bytes
16 // seen below. (E.g., a `ret` is normally written as the u32 `D65F03C0`,
17 // but we write it here as C0035FD6.)
18
19 // Useful helper script to produce the encodings from the text:
20 //
21 // #!/bin/sh
22 // tmp=`mktemp /tmp/XXXXXXXX.o`
23 // aarch64-linux-gnu-as /dev/stdin -o $tmp
24 // aarch64-linux-gnu-objdump -d $tmp
25 // rm -f $tmp
26 //
27 // Then:
28 //
29 // $ echo "mov x1, x2" | aarch64inst.sh
30 insns.push((Inst::Ret, "C0035FD6", "ret"));
31 insns.push((Inst::Nop0, "", "nop-zero-len"));
32 insns.push((Inst::Nop4, "1F2003D5", "nop"));
33 insns.push((
34 Inst::AluRRR {
35 alu_op: ALUOp::Add32,
36 rd: writable_xreg(1),
37 rn: xreg(2),
38 rm: xreg(3),
39 },
40 "4100030B",
41 "add w1, w2, w3",
42 ));
43 insns.push((
44 Inst::AluRRR {
45 alu_op: ALUOp::Add64,
46 rd: writable_xreg(4),
47 rn: xreg(5),
48 rm: xreg(6),
49 },
50 "A400068B",
51 "add x4, x5, x6",
52 ));
53 insns.push((
54 Inst::AluRRR {
55 alu_op: ALUOp::Adc32,
56 rd: writable_xreg(1),
57 rn: xreg(2),
58 rm: xreg(3),
59 },
60 "4100031A",
61 "adc w1, w2, w3",
62 ));
63 insns.push((
64 Inst::AluRRR {
65 alu_op: ALUOp::Adc64,
66 rd: writable_xreg(4),
67 rn: xreg(5),
68 rm: xreg(6),
69 },
70 "A400069A",
71 "adc x4, x5, x6",
72 ));
73 insns.push((
74 Inst::AluRRR {
75 alu_op: ALUOp::AdcS32,
76 rd: writable_xreg(1),
77 rn: xreg(2),
78 rm: xreg(3),
79 },
80 "4100033A",
81 "adcs w1, w2, w3",
82 ));
83 insns.push((
84 Inst::AluRRR {
85 alu_op: ALUOp::AdcS64,
86 rd: writable_xreg(4),
87 rn: xreg(5),
88 rm: xreg(6),
89 },
90 "A40006BA",
91 "adcs x4, x5, x6",
92 ));
93 insns.push((
94 Inst::AluRRR {
95 alu_op: ALUOp::Sub32,
96 rd: writable_xreg(1),
97 rn: xreg(2),
98 rm: xreg(3),
99 },
100 "4100034B",
101 "sub w1, w2, w3",
102 ));
103 insns.push((
104 Inst::AluRRR {
105 alu_op: ALUOp::Sub64,
106 rd: writable_xreg(4),
107 rn: xreg(5),
108 rm: xreg(6),
109 },
110 "A40006CB",
111 "sub x4, x5, x6",
112 ));
113 insns.push((
114 Inst::AluRRR {
115 alu_op: ALUOp::Sbc32,
116 rd: writable_xreg(1),
117 rn: xreg(2),
118 rm: xreg(3),
119 },
120 "4100035A",
121 "sbc w1, w2, w3",
122 ));
123 insns.push((
124 Inst::AluRRR {
125 alu_op: ALUOp::Sbc64,
126 rd: writable_xreg(4),
127 rn: xreg(5),
128 rm: xreg(6),
129 },
130 "A40006DA",
131 "sbc x4, x5, x6",
132 ));
133 insns.push((
134 Inst::AluRRR {
135 alu_op: ALUOp::SbcS32,
136 rd: writable_xreg(1),
137 rn: xreg(2),
138 rm: xreg(3),
139 },
140 "4100037A",
141 "sbcs w1, w2, w3",
142 ));
143 insns.push((
144 Inst::AluRRR {
145 alu_op: ALUOp::SbcS64,
146 rd: writable_xreg(4),
147 rn: xreg(5),
148 rm: xreg(6),
149 },
150 "A40006FA",
151 "sbcs x4, x5, x6",
152 ));
153
154 insns.push((
155 Inst::AluRRR {
156 alu_op: ALUOp::Orr32,
157 rd: writable_xreg(1),
158 rn: xreg(2),
159 rm: xreg(3),
160 },
161 "4100032A",
162 "orr w1, w2, w3",
163 ));
164 insns.push((
165 Inst::AluRRR {
166 alu_op: ALUOp::Orr64,
167 rd: writable_xreg(4),
168 rn: xreg(5),
169 rm: xreg(6),
170 },
171 "A40006AA",
172 "orr x4, x5, x6",
173 ));
174 insns.push((
175 Inst::AluRRR {
176 alu_op: ALUOp::And32,
177 rd: writable_xreg(1),
178 rn: xreg(2),
179 rm: xreg(3),
180 },
181 "4100030A",
182 "and w1, w2, w3",
183 ));
184 insns.push((
185 Inst::AluRRR {
186 alu_op: ALUOp::And64,
187 rd: writable_xreg(4),
188 rn: xreg(5),
189 rm: xreg(6),
190 },
191 "A400068A",
192 "and x4, x5, x6",
193 ));
194 insns.push((
195 Inst::AluRRR {
196 alu_op: ALUOp::AndS32,
197 rd: writable_xreg(1),
198 rn: xreg(2),
199 rm: xreg(3),
200 },
201 "4100036A",
202 "ands w1, w2, w3",
203 ));
204 insns.push((
205 Inst::AluRRR {
206 alu_op: ALUOp::AndS64,
207 rd: writable_xreg(4),
208 rn: xreg(5),
209 rm: xreg(6),
210 },
211 "A40006EA",
212 "ands x4, x5, x6",
213 ));
214 insns.push((
215 Inst::AluRRR {
216 alu_op: ALUOp::SubS32,
217 rd: writable_zero_reg(),
218 rn: xreg(2),
219 rm: xreg(3),
220 },
221 "5F00036B",
222 // TODO: Display as cmp
223 "subs wzr, w2, w3",
224 ));
225 insns.push((
226 Inst::AluRRR {
227 alu_op: ALUOp::SubS32,
228 rd: writable_xreg(1),
229 rn: xreg(2),
230 rm: xreg(3),
231 },
232 "4100036B",
233 "subs w1, w2, w3",
234 ));
235 insns.push((
236 Inst::AluRRR {
237 alu_op: ALUOp::SubS64,
238 rd: writable_xreg(4),
239 rn: xreg(5),
240 rm: xreg(6),
241 },
242 "A40006EB",
243 "subs x4, x5, x6",
244 ));
245 insns.push((
246 Inst::AluRRR {
247 alu_op: ALUOp::AddS32,
248 rd: writable_xreg(1),
249 rn: xreg(2),
250 rm: xreg(3),
251 },
252 "4100032B",
253 "adds w1, w2, w3",
254 ));
255 insns.push((
256 Inst::AluRRR {
257 alu_op: ALUOp::AddS64,
258 rd: writable_xreg(4),
259 rn: xreg(5),
260 rm: xreg(6),
261 },
262 "A40006AB",
263 "adds x4, x5, x6",
264 ));
265 insns.push((
266 Inst::AluRRImm12 {
267 alu_op: ALUOp::AddS64,
268 rd: writable_zero_reg(),
269 rn: xreg(5),
270 imm12: Imm12::maybe_from_u64(1).unwrap(),
271 },
272 "BF0400B1",
273 // TODO: Display as cmn.
274 "adds xzr, x5, #1",
275 ));
276 insns.push((
277 Inst::AluRRR {
278 alu_op: ALUOp::SDiv64,
279 rd: writable_xreg(4),
280 rn: xreg(5),
281 rm: xreg(6),
282 },
283 "A40CC69A",
284 "sdiv x4, x5, x6",
285 ));
286 insns.push((
287 Inst::AluRRR {
288 alu_op: ALUOp::UDiv64,
289 rd: writable_xreg(4),
290 rn: xreg(5),
291 rm: xreg(6),
292 },
293 "A408C69A",
294 "udiv x4, x5, x6",
295 ));
296
297 insns.push((
298 Inst::AluRRR {
299 alu_op: ALUOp::Eor32,
300 rd: writable_xreg(4),
301 rn: xreg(5),
302 rm: xreg(6),
303 },
304 "A400064A",
305 "eor w4, w5, w6",
306 ));
307 insns.push((
308 Inst::AluRRR {
309 alu_op: ALUOp::Eor64,
310 rd: writable_xreg(4),
311 rn: xreg(5),
312 rm: xreg(6),
313 },
314 "A40006CA",
315 "eor x4, x5, x6",
316 ));
317 insns.push((
318 Inst::AluRRR {
319 alu_op: ALUOp::AndNot32,
320 rd: writable_xreg(4),
321 rn: xreg(5),
322 rm: xreg(6),
323 },
324 "A400260A",
325 "bic w4, w5, w6",
326 ));
327 insns.push((
328 Inst::AluRRR {
329 alu_op: ALUOp::AndNot64,
330 rd: writable_xreg(4),
331 rn: xreg(5),
332 rm: xreg(6),
333 },
334 "A400268A",
335 "bic x4, x5, x6",
336 ));
337 insns.push((
338 Inst::AluRRR {
339 alu_op: ALUOp::OrrNot32,
340 rd: writable_xreg(4),
341 rn: xreg(5),
342 rm: xreg(6),
343 },
344 "A400262A",
345 "orn w4, w5, w6",
346 ));
347 insns.push((
348 Inst::AluRRR {
349 alu_op: ALUOp::OrrNot64,
350 rd: writable_xreg(4),
351 rn: xreg(5),
352 rm: xreg(6),
353 },
354 "A40026AA",
355 "orn x4, x5, x6",
356 ));
357 insns.push((
358 Inst::AluRRR {
359 alu_op: ALUOp::EorNot32,
360 rd: writable_xreg(4),
361 rn: xreg(5),
362 rm: xreg(6),
363 },
364 "A400264A",
365 "eon w4, w5, w6",
366 ));
367 insns.push((
368 Inst::AluRRR {
369 alu_op: ALUOp::EorNot64,
370 rd: writable_xreg(4),
371 rn: xreg(5),
372 rm: xreg(6),
373 },
374 "A40026CA",
375 "eon x4, x5, x6",
376 ));
377
378 insns.push((
379 Inst::AluRRR {
380 alu_op: ALUOp::RotR32,
381 rd: writable_xreg(4),
382 rn: xreg(5),
383 rm: xreg(6),
384 },
385 "A42CC61A",
386 "ror w4, w5, w6",
387 ));
388 insns.push((
389 Inst::AluRRR {
390 alu_op: ALUOp::RotR64,
391 rd: writable_xreg(4),
392 rn: xreg(5),
393 rm: xreg(6),
394 },
395 "A42CC69A",
396 "ror x4, x5, x6",
397 ));
398 insns.push((
399 Inst::AluRRR {
400 alu_op: ALUOp::Lsr32,
401 rd: writable_xreg(4),
402 rn: xreg(5),
403 rm: xreg(6),
404 },
405 "A424C61A",
406 "lsr w4, w5, w6",
407 ));
408 insns.push((
409 Inst::AluRRR {
410 alu_op: ALUOp::Lsr64,
411 rd: writable_xreg(4),
412 rn: xreg(5),
413 rm: xreg(6),
414 },
415 "A424C69A",
416 "lsr x4, x5, x6",
417 ));
418 insns.push((
419 Inst::AluRRR {
420 alu_op: ALUOp::Asr32,
421 rd: writable_xreg(4),
422 rn: xreg(5),
423 rm: xreg(6),
424 },
425 "A428C61A",
426 "asr w4, w5, w6",
427 ));
428 insns.push((
429 Inst::AluRRR {
430 alu_op: ALUOp::Asr64,
431 rd: writable_xreg(4),
432 rn: xreg(5),
433 rm: xreg(6),
434 },
435 "A428C69A",
436 "asr x4, x5, x6",
437 ));
438 insns.push((
439 Inst::AluRRR {
440 alu_op: ALUOp::Lsl32,
441 rd: writable_xreg(4),
442 rn: xreg(5),
443 rm: xreg(6),
444 },
445 "A420C61A",
446 "lsl w4, w5, w6",
447 ));
448 insns.push((
449 Inst::AluRRR {
450 alu_op: ALUOp::Lsl64,
451 rd: writable_xreg(4),
452 rn: xreg(5),
453 rm: xreg(6),
454 },
455 "A420C69A",
456 "lsl x4, x5, x6",
457 ));
458
459 insns.push((
460 Inst::AluRRImm12 {
461 alu_op: ALUOp::Add32,
462 rd: writable_xreg(7),
463 rn: xreg(8),
464 imm12: Imm12 {
465 bits: 0x123,
466 shift12: false,
467 },
468 },
469 "078D0411",
470 "add w7, w8, #291",
471 ));
472 insns.push((
473 Inst::AluRRImm12 {
474 alu_op: ALUOp::Add32,
475 rd: writable_xreg(7),
476 rn: xreg(8),
477 imm12: Imm12 {
478 bits: 0x123,
479 shift12: true,
480 },
481 },
482 "078D4411",
483 "add w7, w8, #1191936",
484 ));
485 insns.push((
486 Inst::AluRRImm12 {
487 alu_op: ALUOp::Add64,
488 rd: writable_xreg(7),
489 rn: xreg(8),
490 imm12: Imm12 {
491 bits: 0x123,
492 shift12: false,
493 },
494 },
495 "078D0491",
496 "add x7, x8, #291",
497 ));
498 insns.push((
499 Inst::AluRRImm12 {
500 alu_op: ALUOp::Sub32,
501 rd: writable_xreg(7),
502 rn: xreg(8),
503 imm12: Imm12 {
504 bits: 0x123,
505 shift12: false,
506 },
507 },
508 "078D0451",
509 "sub w7, w8, #291",
510 ));
511 insns.push((
512 Inst::AluRRImm12 {
513 alu_op: ALUOp::Sub64,
514 rd: writable_xreg(7),
515 rn: xreg(8),
516 imm12: Imm12 {
517 bits: 0x123,
518 shift12: false,
519 },
520 },
521 "078D04D1",
522 "sub x7, x8, #291",
523 ));
524 insns.push((
525 Inst::AluRRImm12 {
526 alu_op: ALUOp::SubS32,
527 rd: writable_xreg(7),
528 rn: xreg(8),
529 imm12: Imm12 {
530 bits: 0x123,
531 shift12: false,
532 },
533 },
534 "078D0471",
535 "subs w7, w8, #291",
536 ));
537 insns.push((
538 Inst::AluRRImm12 {
539 alu_op: ALUOp::SubS64,
540 rd: writable_xreg(7),
541 rn: xreg(8),
542 imm12: Imm12 {
543 bits: 0x123,
544 shift12: false,
545 },
546 },
547 "078D04F1",
548 "subs x7, x8, #291",
549 ));
550
551 insns.push((
552 Inst::AluRRRExtend {
553 alu_op: ALUOp::Add32,
554 rd: writable_xreg(7),
555 rn: xreg(8),
556 rm: xreg(9),
557 extendop: ExtendOp::SXTB,
558 },
559 "0781290B",
560 "add w7, w8, w9, SXTB",
561 ));
562
563 insns.push((
564 Inst::AluRRRExtend {
565 alu_op: ALUOp::Add64,
566 rd: writable_xreg(15),
567 rn: xreg(16),
568 rm: xreg(17),
569 extendop: ExtendOp::UXTB,
570 },
571 "0F02318B",
572 "add x15, x16, x17, UXTB",
573 ));
574
575 insns.push((
576 Inst::AluRRRExtend {
577 alu_op: ALUOp::Sub32,
578 rd: writable_xreg(1),
579 rn: xreg(2),
580 rm: xreg(3),
581 extendop: ExtendOp::SXTH,
582 },
583 "41A0234B",
584 "sub w1, w2, w3, SXTH",
585 ));
586
587 insns.push((
588 Inst::AluRRRExtend {
589 alu_op: ALUOp::Sub64,
590 rd: writable_xreg(20),
591 rn: xreg(21),
592 rm: xreg(22),
593 extendop: ExtendOp::UXTW,
594 },
595 "B44236CB",
596 "sub x20, x21, x22, UXTW",
597 ));
598
599 insns.push((
600 Inst::AluRRRShift {
601 alu_op: ALUOp::Add32,
602 rd: writable_xreg(10),
603 rn: xreg(11),
604 rm: xreg(12),
605 shiftop: ShiftOpAndAmt::new(
606 ShiftOp::LSL,
607 ShiftOpShiftImm::maybe_from_shift(20).unwrap(),
608 ),
609 },
610 "6A510C0B",
611 "add w10, w11, w12, LSL 20",
612 ));
613 insns.push((
614 Inst::AluRRRShift {
615 alu_op: ALUOp::Add64,
616 rd: writable_xreg(10),
617 rn: xreg(11),
618 rm: xreg(12),
619 shiftop: ShiftOpAndAmt::new(
620 ShiftOp::ASR,
621 ShiftOpShiftImm::maybe_from_shift(42).unwrap(),
622 ),
623 },
624 "6AA98C8B",
625 "add x10, x11, x12, ASR 42",
626 ));
627 insns.push((
628 Inst::AluRRRShift {
629 alu_op: ALUOp::Sub32,
630 rd: writable_xreg(10),
631 rn: xreg(11),
632 rm: xreg(12),
633 shiftop: ShiftOpAndAmt::new(
634 ShiftOp::LSL,
635 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
636 ),
637 },
638 "6A5D0C4B",
639 "sub w10, w11, w12, LSL 23",
640 ));
641 insns.push((
642 Inst::AluRRRShift {
643 alu_op: ALUOp::Sub64,
644 rd: writable_xreg(10),
645 rn: xreg(11),
646 rm: xreg(12),
647 shiftop: ShiftOpAndAmt::new(
648 ShiftOp::LSL,
649 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
650 ),
651 },
652 "6A5D0CCB",
653 "sub x10, x11, x12, LSL 23",
654 ));
655 insns.push((
656 Inst::AluRRRShift {
657 alu_op: ALUOp::Orr32,
658 rd: writable_xreg(10),
659 rn: xreg(11),
660 rm: xreg(12),
661 shiftop: ShiftOpAndAmt::new(
662 ShiftOp::LSL,
663 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
664 ),
665 },
666 "6A5D0C2A",
667 "orr w10, w11, w12, LSL 23",
668 ));
669 insns.push((
670 Inst::AluRRRShift {
671 alu_op: ALUOp::Orr64,
672 rd: writable_xreg(10),
673 rn: xreg(11),
674 rm: xreg(12),
675 shiftop: ShiftOpAndAmt::new(
676 ShiftOp::LSL,
677 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
678 ),
679 },
680 "6A5D0CAA",
681 "orr x10, x11, x12, LSL 23",
682 ));
683 insns.push((
684 Inst::AluRRRShift {
685 alu_op: ALUOp::And32,
686 rd: writable_xreg(10),
687 rn: xreg(11),
688 rm: xreg(12),
689 shiftop: ShiftOpAndAmt::new(
690 ShiftOp::LSL,
691 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
692 ),
693 },
694 "6A5D0C0A",
695 "and w10, w11, w12, LSL 23",
696 ));
697 insns.push((
698 Inst::AluRRRShift {
699 alu_op: ALUOp::And64,
700 rd: writable_xreg(10),
701 rn: xreg(11),
702 rm: xreg(12),
703 shiftop: ShiftOpAndAmt::new(
704 ShiftOp::LSL,
705 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
706 ),
707 },
708 "6A5D0C8A",
709 "and x10, x11, x12, LSL 23",
710 ));
711 insns.push((
712 Inst::AluRRRShift {
713 alu_op: ALUOp::AndS32,
714 rd: writable_xreg(10),
715 rn: xreg(11),
716 rm: xreg(12),
717 shiftop: ShiftOpAndAmt::new(
718 ShiftOp::LSL,
719 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
720 ),
721 },
722 "6A5D0C6A",
723 "ands w10, w11, w12, LSL 23",
724 ));
725 insns.push((
726 Inst::AluRRRShift {
727 alu_op: ALUOp::AndS64,
728 rd: writable_xreg(10),
729 rn: xreg(11),
730 rm: xreg(12),
731 shiftop: ShiftOpAndAmt::new(
732 ShiftOp::LSL,
733 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
734 ),
735 },
736 "6A5D0CEA",
737 "ands x10, x11, x12, LSL 23",
738 ));
739 insns.push((
740 Inst::AluRRRShift {
741 alu_op: ALUOp::Eor32,
742 rd: writable_xreg(10),
743 rn: xreg(11),
744 rm: xreg(12),
745 shiftop: ShiftOpAndAmt::new(
746 ShiftOp::LSL,
747 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
748 ),
749 },
750 "6A5D0C4A",
751 "eor w10, w11, w12, LSL 23",
752 ));
753 insns.push((
754 Inst::AluRRRShift {
755 alu_op: ALUOp::Eor64,
756 rd: writable_xreg(10),
757 rn: xreg(11),
758 rm: xreg(12),
759 shiftop: ShiftOpAndAmt::new(
760 ShiftOp::LSL,
761 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
762 ),
763 },
764 "6A5D0CCA",
765 "eor x10, x11, x12, LSL 23",
766 ));
767 insns.push((
768 Inst::AluRRRShift {
769 alu_op: ALUOp::OrrNot32,
770 rd: writable_xreg(10),
771 rn: xreg(11),
772 rm: xreg(12),
773 shiftop: ShiftOpAndAmt::new(
774 ShiftOp::LSL,
775 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
776 ),
777 },
778 "6A5D2C2A",
779 "orn w10, w11, w12, LSL 23",
780 ));
781 insns.push((
782 Inst::AluRRRShift {
783 alu_op: ALUOp::OrrNot64,
784 rd: writable_xreg(10),
785 rn: xreg(11),
786 rm: xreg(12),
787 shiftop: ShiftOpAndAmt::new(
788 ShiftOp::LSL,
789 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
790 ),
791 },
792 "6A5D2CAA",
793 "orn x10, x11, x12, LSL 23",
794 ));
795 insns.push((
796 Inst::AluRRRShift {
797 alu_op: ALUOp::AndNot32,
798 rd: writable_xreg(10),
799 rn: xreg(11),
800 rm: xreg(12),
801 shiftop: ShiftOpAndAmt::new(
802 ShiftOp::LSL,
803 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
804 ),
805 },
806 "6A5D2C0A",
807 "bic w10, w11, w12, LSL 23",
808 ));
809 insns.push((
810 Inst::AluRRRShift {
811 alu_op: ALUOp::AndNot64,
812 rd: writable_xreg(10),
813 rn: xreg(11),
814 rm: xreg(12),
815 shiftop: ShiftOpAndAmt::new(
816 ShiftOp::LSL,
817 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
818 ),
819 },
820 "6A5D2C8A",
821 "bic x10, x11, x12, LSL 23",
822 ));
823 insns.push((
824 Inst::AluRRRShift {
825 alu_op: ALUOp::EorNot32,
826 rd: writable_xreg(10),
827 rn: xreg(11),
828 rm: xreg(12),
829 shiftop: ShiftOpAndAmt::new(
830 ShiftOp::LSL,
831 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
832 ),
833 },
834 "6A5D2C4A",
835 "eon w10, w11, w12, LSL 23",
836 ));
837 insns.push((
838 Inst::AluRRRShift {
839 alu_op: ALUOp::EorNot64,
840 rd: writable_xreg(10),
841 rn: xreg(11),
842 rm: xreg(12),
843 shiftop: ShiftOpAndAmt::new(
844 ShiftOp::LSL,
845 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
846 ),
847 },
848 "6A5D2CCA",
849 "eon x10, x11, x12, LSL 23",
850 ));
851 insns.push((
852 Inst::AluRRRShift {
853 alu_op: ALUOp::AddS32,
854 rd: writable_xreg(10),
855 rn: xreg(11),
856 rm: xreg(12),
857 shiftop: ShiftOpAndAmt::new(
858 ShiftOp::LSL,
859 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
860 ),
861 },
862 "6A5D0C2B",
863 "adds w10, w11, w12, LSL 23",
864 ));
865 insns.push((
866 Inst::AluRRRShift {
867 alu_op: ALUOp::AddS64,
868 rd: writable_xreg(10),
869 rn: xreg(11),
870 rm: xreg(12),
871 shiftop: ShiftOpAndAmt::new(
872 ShiftOp::LSL,
873 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
874 ),
875 },
876 "6A5D0CAB",
877 "adds x10, x11, x12, LSL 23",
878 ));
879 insns.push((
880 Inst::AluRRRShift {
881 alu_op: ALUOp::SubS32,
882 rd: writable_xreg(10),
883 rn: xreg(11),
884 rm: xreg(12),
885 shiftop: ShiftOpAndAmt::new(
886 ShiftOp::LSL,
887 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
888 ),
889 },
890 "6A5D0C6B",
891 "subs w10, w11, w12, LSL 23",
892 ));
893 insns.push((
894 Inst::AluRRRShift {
895 alu_op: ALUOp::SubS64,
896 rd: writable_xreg(10),
897 rn: xreg(11),
898 rm: xreg(12),
899 shiftop: ShiftOpAndAmt::new(
900 ShiftOp::LSL,
901 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
902 ),
903 },
904 "6A5D0CEB",
905 "subs x10, x11, x12, LSL 23",
906 ));
907
908 insns.push((
909 Inst::AluRRRExtend {
910 alu_op: ALUOp::SubS64,
911 rd: writable_zero_reg(),
912 rn: stack_reg(),
913 rm: xreg(12),
914 extendop: ExtendOp::UXTX,
915 },
916 "FF632CEB",
917 "subs xzr, sp, x12, UXTX",
918 ));
919
920 insns.push((
921 Inst::AluRRRR {
922 alu_op: ALUOp3::MAdd32,
923 rd: writable_xreg(1),
924 rn: xreg(2),
925 rm: xreg(3),
926 ra: xreg(4),
927 },
928 "4110031B",
929 "madd w1, w2, w3, w4",
930 ));
931 insns.push((
932 Inst::AluRRRR {
933 alu_op: ALUOp3::MAdd64,
934 rd: writable_xreg(1),
935 rn: xreg(2),
936 rm: xreg(3),
937 ra: xreg(4),
938 },
939 "4110039B",
940 "madd x1, x2, x3, x4",
941 ));
942 insns.push((
943 Inst::AluRRRR {
944 alu_op: ALUOp3::MSub32,
945 rd: writable_xreg(1),
946 rn: xreg(2),
947 rm: xreg(3),
948 ra: xreg(4),
949 },
950 "4190031B",
951 "msub w1, w2, w3, w4",
952 ));
953 insns.push((
954 Inst::AluRRRR {
955 alu_op: ALUOp3::MSub64,
956 rd: writable_xreg(1),
957 rn: xreg(2),
958 rm: xreg(3),
959 ra: xreg(4),
960 },
961 "4190039B",
962 "msub x1, x2, x3, x4",
963 ));
964 insns.push((
965 Inst::AluRRR {
966 alu_op: ALUOp::SMulH,
967 rd: writable_xreg(1),
968 rn: xreg(2),
969 rm: xreg(3),
970 },
971 "417C439B",
972 "smulh x1, x2, x3",
973 ));
974 insns.push((
975 Inst::AluRRR {
976 alu_op: ALUOp::UMulH,
977 rd: writable_xreg(1),
978 rn: xreg(2),
979 rm: xreg(3),
980 },
981 "417CC39B",
982 "umulh x1, x2, x3",
983 ));
984
985 insns.push((
986 Inst::AluRRImmShift {
987 alu_op: ALUOp::RotR32,
988 rd: writable_xreg(20),
989 rn: xreg(21),
990 immshift: ImmShift::maybe_from_u64(19).unwrap(),
991 },
992 "B44E9513",
993 "ror w20, w21, #19",
994 ));
995 insns.push((
996 Inst::AluRRImmShift {
997 alu_op: ALUOp::RotR64,
998 rd: writable_xreg(20),
999 rn: xreg(21),
1000 immshift: ImmShift::maybe_from_u64(42).unwrap(),
1001 },
1002 "B4AAD593",
1003 "ror x20, x21, #42",
1004 ));
1005 insns.push((
1006 Inst::AluRRImmShift {
1007 alu_op: ALUOp::Lsr32,
1008 rd: writable_xreg(10),
1009 rn: xreg(11),
1010 immshift: ImmShift::maybe_from_u64(13).unwrap(),
1011 },
1012 "6A7D0D53",
1013 "lsr w10, w11, #13",
1014 ));
1015 insns.push((
1016 Inst::AluRRImmShift {
1017 alu_op: ALUOp::Lsr64,
1018 rd: writable_xreg(10),
1019 rn: xreg(11),
1020 immshift: ImmShift::maybe_from_u64(57).unwrap(),
1021 },
1022 "6AFD79D3",
1023 "lsr x10, x11, #57",
1024 ));
1025 insns.push((
1026 Inst::AluRRImmShift {
1027 alu_op: ALUOp::Asr32,
1028 rd: writable_xreg(4),
1029 rn: xreg(5),
1030 immshift: ImmShift::maybe_from_u64(7).unwrap(),
1031 },
1032 "A47C0713",
1033 "asr w4, w5, #7",
1034 ));
1035 insns.push((
1036 Inst::AluRRImmShift {
1037 alu_op: ALUOp::Asr64,
1038 rd: writable_xreg(4),
1039 rn: xreg(5),
1040 immshift: ImmShift::maybe_from_u64(35).unwrap(),
1041 },
1042 "A4FC6393",
1043 "asr x4, x5, #35",
1044 ));
1045 insns.push((
1046 Inst::AluRRImmShift {
1047 alu_op: ALUOp::Lsl32,
1048 rd: writable_xreg(8),
1049 rn: xreg(9),
1050 immshift: ImmShift::maybe_from_u64(24).unwrap(),
1051 },
1052 "281D0853",
1053 "lsl w8, w9, #24",
1054 ));
1055 insns.push((
1056 Inst::AluRRImmShift {
1057 alu_op: ALUOp::Lsl64,
1058 rd: writable_xreg(8),
1059 rn: xreg(9),
1060 immshift: ImmShift::maybe_from_u64(63).unwrap(),
1061 },
1062 "280141D3",
1063 "lsl x8, x9, #63",
1064 ));
1065 insns.push((
1066 Inst::AluRRImmShift {
1067 alu_op: ALUOp::Lsl32,
1068 rd: writable_xreg(10),
1069 rn: xreg(11),
1070 immshift: ImmShift::maybe_from_u64(0).unwrap(),
1071 },
1072 "6A7D0053",
1073 "lsl w10, w11, #0",
1074 ));
1075 insns.push((
1076 Inst::AluRRImmShift {
1077 alu_op: ALUOp::Lsl64,
1078 rd: writable_xreg(10),
1079 rn: xreg(11),
1080 immshift: ImmShift::maybe_from_u64(0).unwrap(),
1081 },
1082 "6AFD40D3",
1083 "lsl x10, x11, #0",
1084 ));
1085
1086 insns.push((
1087 Inst::AluRRImmLogic {
1088 alu_op: ALUOp::And32,
1089 rd: writable_xreg(21),
1090 rn: xreg(27),
1091 imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
1092 },
1093 "753B0112",
1094 "and w21, w27, #2147500031",
1095 ));
1096 insns.push((
1097 Inst::AluRRImmLogic {
1098 alu_op: ALUOp::And64,
1099 rd: writable_xreg(7),
1100 rn: xreg(6),
1101 imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
1102 },
1103 "C7381592",
1104 "and x7, x6, #288221580125796352",
1105 ));
1106 insns.push((
1107 Inst::AluRRImmLogic {
1108 alu_op: ALUOp::AndS32,
1109 rd: writable_xreg(21),
1110 rn: xreg(27),
1111 imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
1112 },
1113 "753B0172",
1114 "ands w21, w27, #2147500031",
1115 ));
1116 insns.push((
1117 Inst::AluRRImmLogic {
1118 alu_op: ALUOp::AndS64,
1119 rd: writable_xreg(7),
1120 rn: xreg(6),
1121 imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
1122 },
1123 "C73815F2",
1124 "ands x7, x6, #288221580125796352",
1125 ));
1126 insns.push((
1127 Inst::AluRRImmLogic {
1128 alu_op: ALUOp::Orr32,
1129 rd: writable_xreg(1),
1130 rn: xreg(5),
1131 imml: ImmLogic::maybe_from_u64(0x100000, I32).unwrap(),
1132 },
1133 "A1000C32",
1134 "orr w1, w5, #1048576",
1135 ));
1136 insns.push((
1137 Inst::AluRRImmLogic {
1138 alu_op: ALUOp::Orr64,
1139 rd: writable_xreg(4),
1140 rn: xreg(5),
1141 imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
1142 },
1143 "A4C401B2",
1144 "orr x4, x5, #9331882296111890817",
1145 ));
1146 insns.push((
1147 Inst::AluRRImmLogic {
1148 alu_op: ALUOp::Eor32,
1149 rd: writable_xreg(1),
1150 rn: xreg(5),
1151 imml: ImmLogic::maybe_from_u64(0x00007fff, I32).unwrap(),
1152 },
1153 "A1380052",
1154 "eor w1, w5, #32767",
1155 ));
1156 insns.push((
1157 Inst::AluRRImmLogic {
1158 alu_op: ALUOp::Eor64,
1159 rd: writable_xreg(10),
1160 rn: xreg(8),
1161 imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
1162 },
1163 "0AC501D2",
1164 "eor x10, x8, #9331882296111890817",
1165 ));
1166
1167 insns.push((
1168 Inst::BitRR {
1169 op: BitOp::RBit32,
1170 rd: writable_xreg(1),
1171 rn: xreg(10),
1172 },
1173 "4101C05A",
1174 "rbit w1, w10",
1175 ));
1176
1177 insns.push((
1178 Inst::BitRR {
1179 op: BitOp::RBit64,
1180 rd: writable_xreg(1),
1181 rn: xreg(10),
1182 },
1183 "4101C0DA",
1184 "rbit x1, x10",
1185 ));
1186
1187 insns.push((
1188 Inst::BitRR {
1189 op: BitOp::Clz32,
1190 rd: writable_xreg(15),
1191 rn: xreg(3),
1192 },
1193 "6F10C05A",
1194 "clz w15, w3",
1195 ));
1196
1197 insns.push((
1198 Inst::BitRR {
1199 op: BitOp::Clz64,
1200 rd: writable_xreg(15),
1201 rn: xreg(3),
1202 },
1203 "6F10C0DA",
1204 "clz x15, x3",
1205 ));
1206
1207 insns.push((
1208 Inst::BitRR {
1209 op: BitOp::Cls32,
1210 rd: writable_xreg(21),
1211 rn: xreg(16),
1212 },
1213 "1516C05A",
1214 "cls w21, w16",
1215 ));
1216
1217 insns.push((
1218 Inst::BitRR {
1219 op: BitOp::Cls64,
1220 rd: writable_xreg(21),
1221 rn: xreg(16),
1222 },
1223 "1516C0DA",
1224 "cls x21, x16",
1225 ));
1226
1227 insns.push((
1228 Inst::ULoad8 {
1229 rd: writable_xreg(1),
1230 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1231 flags: MemFlags::trusted(),
1232 },
1233 "41004038",
1234 "ldurb w1, [x2]",
1235 ));
1236 insns.push((
1237 Inst::ULoad8 {
1238 rd: writable_xreg(1),
1239 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::zero(I8)),
1240 flags: MemFlags::trusted(),
1241 },
1242 "41004039",
1243 "ldrb w1, [x2]",
1244 ));
1245 insns.push((
1246 Inst::ULoad8 {
1247 rd: writable_xreg(1),
1248 mem: AMode::RegReg(xreg(2), xreg(5)),
1249 flags: MemFlags::trusted(),
1250 },
1251 "41686538",
1252 "ldrb w1, [x2, x5]",
1253 ));
1254 insns.push((
1255 Inst::SLoad8 {
1256 rd: writable_xreg(1),
1257 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1258 flags: MemFlags::trusted(),
1259 },
1260 "41008038",
1261 "ldursb x1, [x2]",
1262 ));
1263 insns.push((
1264 Inst::SLoad8 {
1265 rd: writable_xreg(1),
1266 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(63, I8).unwrap()),
1267 flags: MemFlags::trusted(),
1268 },
1269 "41FC8039",
1270 "ldrsb x1, [x2, #63]",
1271 ));
1272 insns.push((
1273 Inst::SLoad8 {
1274 rd: writable_xreg(1),
1275 mem: AMode::RegReg(xreg(2), xreg(5)),
1276 flags: MemFlags::trusted(),
1277 },
1278 "4168A538",
1279 "ldrsb x1, [x2, x5]",
1280 ));
1281 insns.push((
1282 Inst::ULoad16 {
1283 rd: writable_xreg(1),
1284 mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(5).unwrap()),
1285 flags: MemFlags::trusted(),
1286 },
1287 "41504078",
1288 "ldurh w1, [x2, #5]",
1289 ));
1290 insns.push((
1291 Inst::ULoad16 {
1292 rd: writable_xreg(1),
1293 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(8, I16).unwrap()),
1294 flags: MemFlags::trusted(),
1295 },
1296 "41104079",
1297 "ldrh w1, [x2, #8]",
1298 ));
1299 insns.push((
1300 Inst::ULoad16 {
1301 rd: writable_xreg(1),
1302 mem: AMode::RegScaled(xreg(2), xreg(3), I16),
1303 flags: MemFlags::trusted(),
1304 },
1305 "41786378",
1306 "ldrh w1, [x2, x3, LSL #1]",
1307 ));
1308 insns.push((
1309 Inst::SLoad16 {
1310 rd: writable_xreg(1),
1311 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1312 flags: MemFlags::trusted(),
1313 },
1314 "41008078",
1315 "ldursh x1, [x2]",
1316 ));
1317 insns.push((
1318 Inst::SLoad16 {
1319 rd: writable_xreg(28),
1320 mem: AMode::UnsignedOffset(xreg(20), UImm12Scaled::maybe_from_i64(24, I16).unwrap()),
1321 flags: MemFlags::trusted(),
1322 },
1323 "9C328079",
1324 "ldrsh x28, [x20, #24]",
1325 ));
1326 insns.push((
1327 Inst::SLoad16 {
1328 rd: writable_xreg(28),
1329 mem: AMode::RegScaled(xreg(20), xreg(20), I16),
1330 flags: MemFlags::trusted(),
1331 },
1332 "9C7AB478",
1333 "ldrsh x28, [x20, x20, LSL #1]",
1334 ));
1335 insns.push((
1336 Inst::ULoad32 {
1337 rd: writable_xreg(1),
1338 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1339 flags: MemFlags::trusted(),
1340 },
1341 "410040B8",
1342 "ldur w1, [x2]",
1343 ));
1344 insns.push((
1345 Inst::ULoad32 {
1346 rd: writable_xreg(12),
1347 mem: AMode::UnsignedOffset(xreg(0), UImm12Scaled::maybe_from_i64(204, I32).unwrap()),
1348 flags: MemFlags::trusted(),
1349 },
1350 "0CCC40B9",
1351 "ldr w12, [x0, #204]",
1352 ));
1353 insns.push((
1354 Inst::ULoad32 {
1355 rd: writable_xreg(1),
1356 mem: AMode::RegScaled(xreg(2), xreg(12), I32),
1357 flags: MemFlags::trusted(),
1358 },
1359 "41786CB8",
1360 "ldr w1, [x2, x12, LSL #2]",
1361 ));
1362 insns.push((
1363 Inst::SLoad32 {
1364 rd: writable_xreg(1),
1365 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1366 flags: MemFlags::trusted(),
1367 },
1368 "410080B8",
1369 "ldursw x1, [x2]",
1370 ));
1371 insns.push((
1372 Inst::SLoad32 {
1373 rd: writable_xreg(12),
1374 mem: AMode::UnsignedOffset(xreg(1), UImm12Scaled::maybe_from_i64(16380, I32).unwrap()),
1375 flags: MemFlags::trusted(),
1376 },
1377 "2CFCBFB9",
1378 "ldrsw x12, [x1, #16380]",
1379 ));
1380 insns.push((
1381 Inst::SLoad32 {
1382 rd: writable_xreg(1),
1383 mem: AMode::RegScaled(xreg(5), xreg(1), I32),
1384 flags: MemFlags::trusted(),
1385 },
1386 "A178A1B8",
1387 "ldrsw x1, [x5, x1, LSL #2]",
1388 ));
1389 insns.push((
1390 Inst::ULoad64 {
1391 rd: writable_xreg(1),
1392 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1393 flags: MemFlags::trusted(),
1394 },
1395 "410040F8",
1396 "ldur x1, [x2]",
1397 ));
1398 insns.push((
1399 Inst::ULoad64 {
1400 rd: writable_xreg(1),
1401 mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(-256).unwrap()),
1402 flags: MemFlags::trusted(),
1403 },
1404 "410050F8",
1405 "ldur x1, [x2, #-256]",
1406 ));
1407 insns.push((
1408 Inst::ULoad64 {
1409 rd: writable_xreg(1),
1410 mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(255).unwrap()),
1411 flags: MemFlags::trusted(),
1412 },
1413 "41F04FF8",
1414 "ldur x1, [x2, #255]",
1415 ));
1416 insns.push((
1417 Inst::ULoad64 {
1418 rd: writable_xreg(1),
1419 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(32760, I64).unwrap()),
1420 flags: MemFlags::trusted(),
1421 },
1422 "41FC7FF9",
1423 "ldr x1, [x2, #32760]",
1424 ));
1425 insns.push((
1426 Inst::ULoad64 {
1427 rd: writable_xreg(1),
1428 mem: AMode::RegReg(xreg(2), xreg(3)),
1429 flags: MemFlags::trusted(),
1430 },
1431 "416863F8",
1432 "ldr x1, [x2, x3]",
1433 ));
1434 insns.push((
1435 Inst::ULoad64 {
1436 rd: writable_xreg(1),
1437 mem: AMode::RegScaled(xreg(2), xreg(3), I64),
1438 flags: MemFlags::trusted(),
1439 },
1440 "417863F8",
1441 "ldr x1, [x2, x3, LSL #3]",
1442 ));
1443 insns.push((
1444 Inst::ULoad64 {
1445 rd: writable_xreg(1),
1446 mem: AMode::RegScaledExtended(xreg(2), xreg(3), I64, ExtendOp::SXTW),
1447 flags: MemFlags::trusted(),
1448 },
1449 "41D863F8",
1450 "ldr x1, [x2, w3, SXTW #3]",
1451 ));
1452 insns.push((
1453 Inst::ULoad64 {
1454 rd: writable_xreg(1),
1455 mem: AMode::RegExtended(xreg(2), xreg(3), ExtendOp::SXTW),
1456 flags: MemFlags::trusted(),
1457 },
1458 "41C863F8",
1459 "ldr x1, [x2, w3, SXTW]",
1460 ));
1461 insns.push((
1462 Inst::ULoad64 {
1463 rd: writable_xreg(1),
1464 mem: AMode::Label(MemLabel::PCRel(64)),
1465 flags: MemFlags::trusted(),
1466 },
1467 "01020058",
1468 "ldr x1, pc+64",
1469 ));
1470 insns.push((
1471 Inst::ULoad64 {
1472 rd: writable_xreg(1),
1473 mem: AMode::PreIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
1474 flags: MemFlags::trusted(),
1475 },
1476 "410C41F8",
1477 "ldr x1, [x2, #16]!",
1478 ));
1479 insns.push((
1480 Inst::ULoad64 {
1481 rd: writable_xreg(1),
1482 mem: AMode::PostIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
1483 flags: MemFlags::trusted(),
1484 },
1485 "410441F8",
1486 "ldr x1, [x2], #16",
1487 ));
1488 insns.push((
1489 Inst::ULoad64 {
1490 rd: writable_xreg(1),
1491 mem: AMode::FPOffset(32768, I8),
1492 flags: MemFlags::trusted(),
1493 },
1494 "100090D2B063308B010240F9",
1495 "movz x16, #32768 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
1496 ));
1497 insns.push((
1498 Inst::ULoad64 {
1499 rd: writable_xreg(1),
1500 mem: AMode::FPOffset(-32768, I8),
1501 flags: MemFlags::trusted(),
1502 },
1503 "F0FF8F92B063308B010240F9",
1504 "movn x16, #32767 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
1505 ));
1506 insns.push((
1507 Inst::ULoad64 {
1508 rd: writable_xreg(1),
1509 mem: AMode::FPOffset(1048576, I8), // 2^20
1510 flags: MemFlags::trusted(),
1511 },
1512 "1002A0D2B063308B010240F9",
1513 "movz x16, #16, LSL #16 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
1514 ));
1515 insns.push((
1516 Inst::ULoad64 {
1517 rd: writable_xreg(1),
1518 mem: AMode::FPOffset(1048576 + 1, I8), // 2^20 + 1
1519 flags: MemFlags::trusted(),
1520 },
1521 "300080521002A072B063308B010240F9",
1522 "movz w16, #1 ; movk w16, #16, LSL #16 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
1523 ));
1524
1525 insns.push((
1526 Inst::ULoad64 {
1527 rd: writable_xreg(1),
1528 mem: AMode::RegOffset(xreg(7), 8, I64),
1529 flags: MemFlags::trusted(),
1530 },
1531 "E18040F8",
1532 "ldur x1, [x7, #8]",
1533 ));
1534
1535 insns.push((
1536 Inst::ULoad64 {
1537 rd: writable_xreg(1),
1538 mem: AMode::RegOffset(xreg(7), 1024, I64),
1539 flags: MemFlags::trusted(),
1540 },
1541 "E10042F9",
1542 "ldr x1, [x7, #1024]",
1543 ));
1544
1545 insns.push((
1546 Inst::ULoad64 {
1547 rd: writable_xreg(1),
1548 mem: AMode::RegOffset(xreg(7), 1048576, I64),
1549 flags: MemFlags::trusted(),
1550 },
1551 "1002A0D2F060308B010240F9",
1552 "movz x16, #16, LSL #16 ; add x16, x7, x16, UXTX ; ldr x1, [x16]",
1553 ));
1554
1555 insns.push((
1556 Inst::Store8 {
1557 rd: xreg(1),
1558 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1559 flags: MemFlags::trusted(),
1560 },
1561 "41000038",
1562 "sturb w1, [x2]",
1563 ));
1564 insns.push((
1565 Inst::Store8 {
1566 rd: xreg(1),
1567 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(4095, I8).unwrap()),
1568 flags: MemFlags::trusted(),
1569 },
1570 "41FC3F39",
1571 "strb w1, [x2, #4095]",
1572 ));
1573 insns.push((
1574 Inst::Store16 {
1575 rd: xreg(1),
1576 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1577 flags: MemFlags::trusted(),
1578 },
1579 "41000078",
1580 "sturh w1, [x2]",
1581 ));
1582 insns.push((
1583 Inst::Store16 {
1584 rd: xreg(1),
1585 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(8190, I16).unwrap()),
1586 flags: MemFlags::trusted(),
1587 },
1588 "41FC3F79",
1589 "strh w1, [x2, #8190]",
1590 ));
1591 insns.push((
1592 Inst::Store32 {
1593 rd: xreg(1),
1594 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1595 flags: MemFlags::trusted(),
1596 },
1597 "410000B8",
1598 "stur w1, [x2]",
1599 ));
1600 insns.push((
1601 Inst::Store32 {
1602 rd: xreg(1),
1603 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(16380, I32).unwrap()),
1604 flags: MemFlags::trusted(),
1605 },
1606 "41FC3FB9",
1607 "str w1, [x2, #16380]",
1608 ));
1609 insns.push((
1610 Inst::Store64 {
1611 rd: xreg(1),
1612 mem: AMode::Unscaled(xreg(2), SImm9::zero()),
1613 flags: MemFlags::trusted(),
1614 },
1615 "410000F8",
1616 "stur x1, [x2]",
1617 ));
1618 insns.push((
1619 Inst::Store64 {
1620 rd: xreg(1),
1621 mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(32760, I64).unwrap()),
1622 flags: MemFlags::trusted(),
1623 },
1624 "41FC3FF9",
1625 "str x1, [x2, #32760]",
1626 ));
1627 insns.push((
1628 Inst::Store64 {
1629 rd: xreg(1),
1630 mem: AMode::RegReg(xreg(2), xreg(3)),
1631 flags: MemFlags::trusted(),
1632 },
1633 "416823F8",
1634 "str x1, [x2, x3]",
1635 ));
1636 insns.push((
1637 Inst::Store64 {
1638 rd: xreg(1),
1639 mem: AMode::RegScaled(xreg(2), xreg(3), I64),
1640 flags: MemFlags::trusted(),
1641 },
1642 "417823F8",
1643 "str x1, [x2, x3, LSL #3]",
1644 ));
1645 insns.push((
1646 Inst::Store64 {
1647 rd: xreg(1),
1648 mem: AMode::RegScaledExtended(xreg(2), xreg(3), I64, ExtendOp::UXTW),
1649 flags: MemFlags::trusted(),
1650 },
1651 "415823F8",
1652 "str x1, [x2, w3, UXTW #3]",
1653 ));
1654 insns.push((
1655 Inst::Store64 {
1656 rd: xreg(1),
1657 mem: AMode::RegExtended(xreg(2), xreg(3), ExtendOp::UXTW),
1658 flags: MemFlags::trusted(),
1659 },
1660 "414823F8",
1661 "str x1, [x2, w3, UXTW]",
1662 ));
1663 insns.push((
1664 Inst::Store64 {
1665 rd: xreg(1),
1666 mem: AMode::PreIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
1667 flags: MemFlags::trusted(),
1668 },
1669 "410C01F8",
1670 "str x1, [x2, #16]!",
1671 ));
1672 insns.push((
1673 Inst::Store64 {
1674 rd: xreg(1),
1675 mem: AMode::PostIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
1676 flags: MemFlags::trusted(),
1677 },
1678 "410401F8",
1679 "str x1, [x2], #16",
1680 ));
1681
1682 insns.push((
1683 Inst::StoreP64 {
1684 rt: xreg(8),
1685 rt2: xreg(9),
1686 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::zero(I64)),
1687 flags: MemFlags::trusted(),
1688 },
1689 "482500A9",
1690 "stp x8, x9, [x10]",
1691 ));
1692 insns.push((
1693 Inst::StoreP64 {
1694 rt: xreg(8),
1695 rt2: xreg(9),
1696 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(504, I64).unwrap()),
1697 flags: MemFlags::trusted(),
1698 },
1699 "48A51FA9",
1700 "stp x8, x9, [x10, #504]",
1701 ));
1702 insns.push((
1703 Inst::StoreP64 {
1704 rt: xreg(8),
1705 rt2: xreg(9),
1706 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(-64, I64).unwrap()),
1707 flags: MemFlags::trusted(),
1708 },
1709 "48253CA9",
1710 "stp x8, x9, [x10, #-64]",
1711 ));
1712 insns.push((
1713 Inst::StoreP64 {
1714 rt: xreg(21),
1715 rt2: xreg(28),
1716 mem: PairAMode::SignedOffset(xreg(1), SImm7Scaled::maybe_from_i64(-512, I64).unwrap()),
1717 flags: MemFlags::trusted(),
1718 },
1719 "357020A9",
1720 "stp x21, x28, [x1, #-512]",
1721 ));
1722 insns.push((
1723 Inst::StoreP64 {
1724 rt: xreg(8),
1725 rt2: xreg(9),
1726 mem: PairAMode::PreIndexed(
1727 writable_xreg(10),
1728 SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
1729 ),
1730 flags: MemFlags::trusted(),
1731 },
1732 "4825BCA9",
1733 "stp x8, x9, [x10, #-64]!",
1734 ));
1735 insns.push((
1736 Inst::StoreP64 {
1737 rt: xreg(15),
1738 rt2: xreg(16),
1739 mem: PairAMode::PostIndexed(
1740 writable_xreg(20),
1741 SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
1742 ),
1743 flags: MemFlags::trusted(),
1744 },
1745 "8FC29FA8",
1746 "stp x15, x16, [x20], #504",
1747 ));
1748
1749 insns.push((
1750 Inst::LoadP64 {
1751 rt: writable_xreg(8),
1752 rt2: writable_xreg(9),
1753 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::zero(I64)),
1754 flags: MemFlags::trusted(),
1755 },
1756 "482540A9",
1757 "ldp x8, x9, [x10]",
1758 ));
1759 insns.push((
1760 Inst::LoadP64 {
1761 rt: writable_xreg(8),
1762 rt2: writable_xreg(9),
1763 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(504, I64).unwrap()),
1764 flags: MemFlags::trusted(),
1765 },
1766 "48A55FA9",
1767 "ldp x8, x9, [x10, #504]",
1768 ));
1769 insns.push((
1770 Inst::LoadP64 {
1771 rt: writable_xreg(8),
1772 rt2: writable_xreg(9),
1773 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(-64, I64).unwrap()),
1774 flags: MemFlags::trusted(),
1775 },
1776 "48257CA9",
1777 "ldp x8, x9, [x10, #-64]",
1778 ));
1779 insns.push((
1780 Inst::LoadP64 {
1781 rt: writable_xreg(8),
1782 rt2: writable_xreg(9),
1783 mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(-512, I64).unwrap()),
1784 flags: MemFlags::trusted(),
1785 },
1786 "482560A9",
1787 "ldp x8, x9, [x10, #-512]",
1788 ));
1789 insns.push((
1790 Inst::LoadP64 {
1791 rt: writable_xreg(8),
1792 rt2: writable_xreg(9),
1793 mem: PairAMode::PreIndexed(
1794 writable_xreg(10),
1795 SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
1796 ),
1797 flags: MemFlags::trusted(),
1798 },
1799 "4825FCA9",
1800 "ldp x8, x9, [x10, #-64]!",
1801 ));
1802 insns.push((
1803 Inst::LoadP64 {
1804 rt: writable_xreg(8),
1805 rt2: writable_xreg(25),
1806 mem: PairAMode::PostIndexed(
1807 writable_xreg(12),
1808 SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
1809 ),
1810 flags: MemFlags::trusted(),
1811 },
1812 "88E5DFA8",
1813 "ldp x8, x25, [x12], #504",
1814 ));
1815
1816 insns.push((
1817 Inst::Mov64 {
1818 rd: writable_xreg(8),
1819 rm: xreg(9),
1820 },
1821 "E80309AA",
1822 "mov x8, x9",
1823 ));
1824 insns.push((
1825 Inst::Mov32 {
1826 rd: writable_xreg(8),
1827 rm: xreg(9),
1828 },
1829 "E803092A",
1830 "mov w8, w9",
1831 ));
1832
1833 insns.push((
1834 Inst::MovZ {
1835 rd: writable_xreg(8),
1836 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
1837 size: OperandSize::Size64,
1838 },
1839 "E8FF9FD2",
1840 "movz x8, #65535",
1841 ));
1842 insns.push((
1843 Inst::MovZ {
1844 rd: writable_xreg(8),
1845 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
1846 size: OperandSize::Size64,
1847 },
1848 "E8FFBFD2",
1849 "movz x8, #65535, LSL #16",
1850 ));
1851 insns.push((
1852 Inst::MovZ {
1853 rd: writable_xreg(8),
1854 imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
1855 size: OperandSize::Size64,
1856 },
1857 "E8FFDFD2",
1858 "movz x8, #65535, LSL #32",
1859 ));
1860 insns.push((
1861 Inst::MovZ {
1862 rd: writable_xreg(8),
1863 imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
1864 size: OperandSize::Size64,
1865 },
1866 "E8FFFFD2",
1867 "movz x8, #65535, LSL #48",
1868 ));
1869 insns.push((
1870 Inst::MovZ {
1871 rd: writable_xreg(8),
1872 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
1873 size: OperandSize::Size32,
1874 },
1875 "E8FFBF52",
1876 "movz w8, #65535, LSL #16",
1877 ));
1878
1879 insns.push((
1880 Inst::MovN {
1881 rd: writable_xreg(8),
1882 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
1883 size: OperandSize::Size64,
1884 },
1885 "E8FF9F92",
1886 "movn x8, #65535",
1887 ));
1888 insns.push((
1889 Inst::MovN {
1890 rd: writable_xreg(8),
1891 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
1892 size: OperandSize::Size64,
1893 },
1894 "E8FFBF92",
1895 "movn x8, #65535, LSL #16",
1896 ));
1897 insns.push((
1898 Inst::MovN {
1899 rd: writable_xreg(8),
1900 imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
1901 size: OperandSize::Size64,
1902 },
1903 "E8FFDF92",
1904 "movn x8, #65535, LSL #32",
1905 ));
1906 insns.push((
1907 Inst::MovN {
1908 rd: writable_xreg(8),
1909 imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
1910 size: OperandSize::Size64,
1911 },
1912 "E8FFFF92",
1913 "movn x8, #65535, LSL #48",
1914 ));
1915 insns.push((
1916 Inst::MovN {
1917 rd: writable_xreg(8),
1918 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
1919 size: OperandSize::Size32,
1920 },
1921 "E8FF9F12",
1922 "movn w8, #65535",
1923 ));
1924
1925 insns.push((
1926 Inst::MovK {
1927 rd: writable_xreg(12),
1928 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_0000).unwrap(),
1929 size: OperandSize::Size64,
1930 },
1931 "0C0080F2",
1932 "movk x12, #0",
1933 ));
1934 insns.push((
1935 Inst::MovK {
1936 rd: writable_xreg(19),
1937 imm: MoveWideConst::maybe_with_shift(0x0000, 16).unwrap(),
1938 size: OperandSize::Size64,
1939 },
1940 "1300A0F2",
1941 "movk x19, #0, LSL #16",
1942 ));
1943 insns.push((
1944 Inst::MovK {
1945 rd: writable_xreg(3),
1946 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
1947 size: OperandSize::Size64,
1948 },
1949 "E3FF9FF2",
1950 "movk x3, #65535",
1951 ));
1952 insns.push((
1953 Inst::MovK {
1954 rd: writable_xreg(8),
1955 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
1956 size: OperandSize::Size64,
1957 },
1958 "E8FFBFF2",
1959 "movk x8, #65535, LSL #16",
1960 ));
1961 insns.push((
1962 Inst::MovK {
1963 rd: writable_xreg(8),
1964 imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
1965 size: OperandSize::Size64,
1966 },
1967 "E8FFDFF2",
1968 "movk x8, #65535, LSL #32",
1969 ));
1970 insns.push((
1971 Inst::MovK {
1972 rd: writable_xreg(8),
1973 imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
1974 size: OperandSize::Size64,
1975 },
1976 "E8FFFFF2",
1977 "movk x8, #65535, LSL #48",
1978 ));
1979
1980 insns.push((
1981 Inst::CSel {
1982 rd: writable_xreg(10),
1983 rn: xreg(12),
1984 rm: xreg(14),
1985 cond: Cond::Hs,
1986 },
1987 "8A218E9A",
1988 "csel x10, x12, x14, hs",
1989 ));
1990 insns.push((
1991 Inst::CSet {
1992 rd: writable_xreg(15),
1993 cond: Cond::Ge,
1994 },
1995 "EFB79F9A",
1996 "cset x15, ge",
1997 ));
1998 insns.push((
1999 Inst::CSetm {
2000 rd: writable_xreg(0),
2001 cond: Cond::Eq,
2002 },
2003 "E0139FDA",
2004 "csetm x0, eq",
2005 ));
2006 insns.push((
2007 Inst::CSetm {
2008 rd: writable_xreg(16),
2009 cond: Cond::Vs,
2010 },
2011 "F0739FDA",
2012 "csetm x16, vs",
2013 ));
2014 insns.push((
2015 Inst::CCmpImm {
2016 size: OperandSize::Size64,
2017 rn: xreg(22),
2018 imm: UImm5::maybe_from_u8(5).unwrap(),
2019 nzcv: NZCV::new(false, false, true, true),
2020 cond: Cond::Eq,
2021 },
2022 "C30A45FA",
2023 "ccmp x22, #5, #nzCV, eq",
2024 ));
2025 insns.push((
2026 Inst::CCmpImm {
2027 size: OperandSize::Size32,
2028 rn: xreg(3),
2029 imm: UImm5::maybe_from_u8(30).unwrap(),
2030 nzcv: NZCV::new(true, true, true, true),
2031 cond: Cond::Gt,
2032 },
2033 "6FC85E7A",
2034 "ccmp w3, #30, #NZCV, gt",
2035 ));
2036 insns.push((
2037 Inst::MovToFpu {
2038 rd: writable_vreg(31),
2039 rn: xreg(0),
2040 size: ScalarSize::Size64,
2041 },
2042 "1F00679E",
2043 "fmov d31, x0",
2044 ));
2045 insns.push((
2046 Inst::MovToFpu {
2047 rd: writable_vreg(1),
2048 rn: xreg(28),
2049 size: ScalarSize::Size32,
2050 },
2051 "8103271E",
2052 "fmov s1, w28",
2053 ));
2054 insns.push((
2055 Inst::MovToVec {
2056 rd: writable_vreg(0),
2057 rn: xreg(0),
2058 idx: 7,
2059 size: VectorSize::Size8x8,
2060 },
2061 "001C0F4E",
2062 "mov v0.b[7], w0",
2063 ));
2064 insns.push((
2065 Inst::MovToVec {
2066 rd: writable_vreg(20),
2067 rn: xreg(21),
2068 idx: 0,
2069 size: VectorSize::Size64x2,
2070 },
2071 "B41E084E",
2072 "mov v20.d[0], x21",
2073 ));
2074 insns.push((
2075 Inst::MovFromVec {
2076 rd: writable_xreg(3),
2077 rn: vreg(27),
2078 idx: 14,
2079 size: VectorSize::Size8x16,
2080 },
2081 "633F1D0E",
2082 "umov w3, v27.b[14]",
2083 ));
2084 insns.push((
2085 Inst::MovFromVec {
2086 rd: writable_xreg(24),
2087 rn: vreg(5),
2088 idx: 3,
2089 size: VectorSize::Size16x8,
2090 },
2091 "B83C0E0E",
2092 "umov w24, v5.h[3]",
2093 ));
2094 insns.push((
2095 Inst::MovFromVec {
2096 rd: writable_xreg(12),
2097 rn: vreg(17),
2098 idx: 1,
2099 size: VectorSize::Size32x4,
2100 },
2101 "2C3E0C0E",
2102 "mov w12, v17.s[1]",
2103 ));
2104 insns.push((
2105 Inst::MovFromVec {
2106 rd: writable_xreg(21),
2107 rn: vreg(20),
2108 idx: 0,
2109 size: VectorSize::Size64x2,
2110 },
2111 "953E084E",
2112 "mov x21, v20.d[0]",
2113 ));
2114 insns.push((
2115 Inst::MovFromVecSigned {
2116 rd: writable_xreg(0),
2117 rn: vreg(0),
2118 idx: 15,
2119 size: VectorSize::Size8x16,
2120 scalar_size: OperandSize::Size32,
2121 },
2122 "002C1F0E",
2123 "smov w0, v0.b[15]",
2124 ));
2125 insns.push((
2126 Inst::MovFromVecSigned {
2127 rd: writable_xreg(12),
2128 rn: vreg(13),
2129 idx: 7,
2130 size: VectorSize::Size8x8,
2131 scalar_size: OperandSize::Size64,
2132 },
2133 "AC2D0F4E",
2134 "smov x12, v13.b[7]",
2135 ));
2136 insns.push((
2137 Inst::MovFromVecSigned {
2138 rd: writable_xreg(23),
2139 rn: vreg(31),
2140 idx: 7,
2141 size: VectorSize::Size16x8,
2142 scalar_size: OperandSize::Size32,
2143 },
2144 "F72F1E0E",
2145 "smov w23, v31.h[7]",
2146 ));
2147 insns.push((
2148 Inst::MovFromVecSigned {
2149 rd: writable_xreg(24),
2150 rn: vreg(5),
2151 idx: 1,
2152 size: VectorSize::Size32x2,
2153 scalar_size: OperandSize::Size64,
2154 },
2155 "B82C0C4E",
2156 "smov x24, v5.s[1]",
2157 ));
2158 insns.push((
2159 Inst::MovToNZCV { rn: xreg(13) },
2160 "0D421BD5",
2161 "msr nzcv, x13",
2162 ));
2163 insns.push((
2164 Inst::MovFromNZCV {
2165 rd: writable_xreg(27),
2166 },
2167 "1B423BD5",
2168 "mrs x27, nzcv",
2169 ));
2170 insns.push((
2171 Inst::VecDup {
2172 rd: writable_vreg(25),
2173 rn: xreg(7),
2174 size: VectorSize::Size8x16,
2175 },
2176 "F90C014E",
2177 "dup v25.16b, w7",
2178 ));
2179 insns.push((
2180 Inst::VecDup {
2181 rd: writable_vreg(2),
2182 rn: xreg(23),
2183 size: VectorSize::Size16x8,
2184 },
2185 "E20E024E",
2186 "dup v2.8h, w23",
2187 ));
2188 insns.push((
2189 Inst::VecDup {
2190 rd: writable_vreg(0),
2191 rn: xreg(28),
2192 size: VectorSize::Size32x4,
2193 },
2194 "800F044E",
2195 "dup v0.4s, w28",
2196 ));
2197 insns.push((
2198 Inst::VecDup {
2199 rd: writable_vreg(31),
2200 rn: xreg(5),
2201 size: VectorSize::Size64x2,
2202 },
2203 "BF0C084E",
2204 "dup v31.2d, x5",
2205 ));
2206 insns.push((
2207 Inst::VecDupFromFpu {
2208 rd: writable_vreg(14),
2209 rn: vreg(19),
2210 size: VectorSize::Size32x4,
2211 },
2212 "6E06044E",
2213 "dup v14.4s, v19.s[0]",
2214 ));
2215 insns.push((
2216 Inst::VecDupFromFpu {
2217 rd: writable_vreg(18),
2218 rn: vreg(10),
2219 size: VectorSize::Size64x2,
2220 },
2221 "5205084E",
2222 "dup v18.2d, v10.d[0]",
2223 ));
2224 insns.push((
2225 Inst::VecDupFPImm {
2226 rd: writable_vreg(31),
2227 imm: ASIMDFPModImm::maybe_from_u64(1_f32.to_bits() as u64, ScalarSize::Size32).unwrap(),
2228 size: VectorSize::Size32x2,
2229 },
2230 "1FF6030F",
2231 "fmov v31.2s, #1",
2232 ));
2233 insns.push((
2234 Inst::VecDupFPImm {
2235 rd: writable_vreg(0),
2236 imm: ASIMDFPModImm::maybe_from_u64(2_f64.to_bits(), ScalarSize::Size64).unwrap(),
2237 size: VectorSize::Size64x2,
2238 },
2239 "00F4006F",
2240 "fmov v0.2d, #2",
2241 ));
2242 insns.push((
2243 Inst::VecDupImm {
2244 rd: writable_vreg(31),
2245 imm: ASIMDMovModImm::maybe_from_u64(255, ScalarSize::Size8).unwrap(),
2246 invert: false,
2247 size: VectorSize::Size8x16,
2248 },
2249 "FFE7074F",
2250 "movi v31.16b, #255",
2251 ));
2252 insns.push((
2253 Inst::VecDupImm {
2254 rd: writable_vreg(30),
2255 imm: ASIMDMovModImm::maybe_from_u64(0, ScalarSize::Size16).unwrap(),
2256 invert: false,
2257 size: VectorSize::Size16x8,
2258 },
2259 "1E84004F",
2260 "movi v30.8h, #0",
2261 ));
2262 insns.push((
2263 Inst::VecDupImm {
2264 rd: writable_vreg(0),
2265 imm: ASIMDMovModImm::zero(ScalarSize::Size16),
2266 invert: true,
2267 size: VectorSize::Size16x4,
2268 },
2269 "0084002F",
2270 "mvni v0.4h, #0",
2271 ));
2272 insns.push((
2273 Inst::VecDupImm {
2274 rd: writable_vreg(0),
2275 imm: ASIMDMovModImm::maybe_from_u64(256, ScalarSize::Size16).unwrap(),
2276 invert: false,
2277 size: VectorSize::Size16x8,
2278 },
2279 "20A4004F",
2280 "movi v0.8h, #1, LSL #8",
2281 ));
2282 insns.push((
2283 Inst::VecDupImm {
2284 rd: writable_vreg(8),
2285 imm: ASIMDMovModImm::maybe_from_u64(2228223, ScalarSize::Size32).unwrap(),
2286 invert: false,
2287 size: VectorSize::Size32x4,
2288 },
2289 "28D4014F",
2290 "movi v8.4s, #33, MSL #16",
2291 ));
2292 insns.push((
2293 Inst::VecDupImm {
2294 rd: writable_vreg(16),
2295 imm: ASIMDMovModImm::maybe_from_u64(35071, ScalarSize::Size32).unwrap(),
2296 invert: true,
2297 size: VectorSize::Size32x2,
2298 },
2299 "10C5042F",
2300 "mvni v16.2s, #136, MSL #8",
2301 ));
2302 insns.push((
2303 Inst::VecDupImm {
2304 rd: writable_vreg(1),
2305 imm: ASIMDMovModImm::maybe_from_u64(0, ScalarSize::Size32).unwrap(),
2306 invert: false,
2307 size: VectorSize::Size32x2,
2308 },
2309 "0104000F",
2310 "movi v1.2s, #0",
2311 ));
2312 insns.push((
2313 Inst::VecDupImm {
2314 rd: writable_vreg(24),
2315 imm: ASIMDMovModImm::maybe_from_u64(1107296256, ScalarSize::Size32).unwrap(),
2316 invert: false,
2317 size: VectorSize::Size32x4,
2318 },
2319 "5864024F",
2320 "movi v24.4s, #66, LSL #24",
2321 ));
2322 insns.push((
2323 Inst::VecDupImm {
2324 rd: writable_vreg(8),
2325 imm: ASIMDMovModImm::zero(ScalarSize::Size64),
2326 invert: false,
2327 size: VectorSize::Size64x2,
2328 },
2329 "08E4006F",
2330 "movi v8.2d, #0",
2331 ));
2332 insns.push((
2333 Inst::VecDupImm {
2334 rd: writable_vreg(7),
2335 imm: ASIMDMovModImm::maybe_from_u64(18374687574904995840, ScalarSize::Size64).unwrap(),
2336 invert: false,
2337 size: VectorSize::Size64x2,
2338 },
2339 "87E6046F",
2340 "movi v7.2d, #18374687574904995840",
2341 ));
2342 insns.push((
2343 Inst::VecExtend {
2344 t: VecExtendOp::Sxtl8,
2345 rd: writable_vreg(4),
2346 rn: vreg(27),
2347 high_half: false,
2348 },
2349 "64A7080F",
2350 "sxtl v4.8h, v27.8b",
2351 ));
2352 insns.push((
2353 Inst::VecExtend {
2354 t: VecExtendOp::Sxtl16,
2355 rd: writable_vreg(17),
2356 rn: vreg(19),
2357 high_half: true,
2358 },
2359 "71A6104F",
2360 "sxtl2 v17.4s, v19.8h",
2361 ));
2362 insns.push((
2363 Inst::VecExtend {
2364 t: VecExtendOp::Sxtl32,
2365 rd: writable_vreg(30),
2366 rn: vreg(6),
2367 high_half: false,
2368 },
2369 "DEA4200F",
2370 "sxtl v30.2d, v6.2s",
2371 ));
2372 insns.push((
2373 Inst::VecExtend {
2374 t: VecExtendOp::Uxtl8,
2375 rd: writable_vreg(3),
2376 rn: vreg(29),
2377 high_half: true,
2378 },
2379 "A3A7086F",
2380 "uxtl2 v3.8h, v29.16b",
2381 ));
2382 insns.push((
2383 Inst::VecExtend {
2384 t: VecExtendOp::Uxtl16,
2385 rd: writable_vreg(15),
2386 rn: vreg(12),
2387 high_half: false,
2388 },
2389 "8FA5102F",
2390 "uxtl v15.4s, v12.4h",
2391 ));
2392 insns.push((
2393 Inst::VecExtend {
2394 t: VecExtendOp::Uxtl32,
2395 rd: writable_vreg(28),
2396 rn: vreg(2),
2397 high_half: true,
2398 },
2399 "5CA4206F",
2400 "uxtl2 v28.2d, v2.4s",
2401 ));
2402
2403 insns.push((
2404 Inst::VecMovElement {
2405 rd: writable_vreg(0),
2406 rn: vreg(31),
2407 dest_idx: 7,
2408 src_idx: 7,
2409 size: VectorSize::Size16x8,
2410 },
2411 "E0771E6E",
2412 "mov v0.h[7], v31.h[7]",
2413 ));
2414
2415 insns.push((
2416 Inst::VecMovElement {
2417 rd: writable_vreg(31),
2418 rn: vreg(16),
2419 dest_idx: 1,
2420 src_idx: 0,
2421 size: VectorSize::Size32x2,
2422 },
2423 "1F060C6E",
2424 "mov v31.s[1], v16.s[0]",
2425 ));
2426
2427 insns.push((
2428 Inst::VecRRLong {
2429 op: VecRRLongOp::Fcvtl16,
2430 rd: writable_vreg(0),
2431 rn: vreg(30),
2432 high_half: false,
2433 },
2434 "C07B210E",
2435 "fcvtl v0.4s, v30.4h",
2436 ));
2437
2438 insns.push((
2439 Inst::VecRRLong {
2440 op: VecRRLongOp::Fcvtl32,
2441 rd: writable_vreg(16),
2442 rn: vreg(1),
2443 high_half: true,
2444 },
2445 "3078614E",
2446 "fcvtl2 v16.2d, v1.4s",
2447 ));
2448
2449 insns.push((
2450 Inst::VecRRLong {
2451 op: VecRRLongOp::Shll8,
2452 rd: writable_vreg(12),
2453 rn: vreg(5),
2454 high_half: false,
2455 },
2456 "AC38212E",
2457 "shll v12.8h, v5.8b, #8",
2458 ));
2459
2460 insns.push((
2461 Inst::VecRRLong {
2462 op: VecRRLongOp::Shll16,
2463 rd: writable_vreg(9),
2464 rn: vreg(1),
2465 high_half: true,
2466 },
2467 "2938616E",
2468 "shll2 v9.4s, v1.8h, #16",
2469 ));
2470
2471 insns.push((
2472 Inst::VecRRLong {
2473 op: VecRRLongOp::Shll32,
2474 rd: writable_vreg(1),
2475 rn: vreg(10),
2476 high_half: false,
2477 },
2478 "4139A12E",
2479 "shll v1.2d, v10.2s, #32",
2480 ));
2481
2482 insns.push((
2483 Inst::VecRRNarrow {
2484 op: VecRRNarrowOp::Xtn16,
2485 rd: writable_vreg(25),
2486 rn: vreg(17),
2487 high_half: false,
2488 },
2489 "392A210E",
2490 "xtn v25.8b, v17.8h",
2491 ));
2492
2493 insns.push((
2494 Inst::VecRRNarrow {
2495 op: VecRRNarrowOp::Xtn32,
2496 rd: writable_vreg(3),
2497 rn: vreg(10),
2498 high_half: true,
2499 },
2500 "4329614E",
2501 "xtn2 v3.8h, v10.4s",
2502 ));
2503
2504 insns.push((
2505 Inst::VecRRNarrow {
2506 op: VecRRNarrowOp::Xtn64,
2507 rd: writable_vreg(22),
2508 rn: vreg(8),
2509 high_half: false,
2510 },
2511 "1629A10E",
2512 "xtn v22.2s, v8.2d",
2513 ));
2514
2515 insns.push((
2516 Inst::VecRRNarrow {
2517 op: VecRRNarrowOp::Sqxtn16,
2518 rd: writable_vreg(7),
2519 rn: vreg(22),
2520 high_half: true,
2521 },
2522 "C74A214E",
2523 "sqxtn2 v7.16b, v22.8h",
2524 ));
2525
2526 insns.push((
2527 Inst::VecRRNarrow {
2528 op: VecRRNarrowOp::Sqxtn32,
2529 rd: writable_vreg(31),
2530 rn: vreg(0),
2531 high_half: true,
2532 },
2533 "1F48614E",
2534 "sqxtn2 v31.8h, v0.4s",
2535 ));
2536
2537 insns.push((
2538 Inst::VecRRNarrow {
2539 op: VecRRNarrowOp::Sqxtn64,
2540 rd: writable_vreg(14),
2541 rn: vreg(20),
2542 high_half: false,
2543 },
2544 "8E4AA10E",
2545 "sqxtn v14.2s, v20.2d",
2546 ));
2547
2548 insns.push((
2549 Inst::VecRRNarrow {
2550 op: VecRRNarrowOp::Sqxtun16,
2551 rd: writable_vreg(16),
2552 rn: vreg(23),
2553 high_half: false,
2554 },
2555 "F02A212E",
2556 "sqxtun v16.8b, v23.8h",
2557 ));
2558
2559 insns.push((
2560 Inst::VecRRNarrow {
2561 op: VecRRNarrowOp::Sqxtun32,
2562 rd: writable_vreg(28),
2563 rn: vreg(9),
2564 high_half: true,
2565 },
2566 "3C29616E",
2567 "sqxtun2 v28.8h, v9.4s",
2568 ));
2569
2570 insns.push((
2571 Inst::VecRRNarrow {
2572 op: VecRRNarrowOp::Sqxtun64,
2573 rd: writable_vreg(15),
2574 rn: vreg(15),
2575 high_half: false,
2576 },
2577 "EF29A12E",
2578 "sqxtun v15.2s, v15.2d",
2579 ));
2580
2581 insns.push((
2582 Inst::VecRRNarrow {
2583 op: VecRRNarrowOp::Uqxtn16,
2584 rd: writable_vreg(21),
2585 rn: vreg(4),
2586 high_half: true,
2587 },
2588 "9548216E",
2589 "uqxtn2 v21.16b, v4.8h",
2590 ));
2591
2592 insns.push((
2593 Inst::VecRRNarrow {
2594 op: VecRRNarrowOp::Uqxtn32,
2595 rd: writable_vreg(31),
2596 rn: vreg(31),
2597 high_half: false,
2598 },
2599 "FF4B612E",
2600 "uqxtn v31.4h, v31.4s",
2601 ));
2602
2603 insns.push((
2604 Inst::VecRRNarrow {
2605 op: VecRRNarrowOp::Uqxtn64,
2606 rd: writable_vreg(11),
2607 rn: vreg(12),
2608 high_half: true,
2609 },
2610 "8B49A16E",
2611 "uqxtn2 v11.4s, v12.2d",
2612 ));
2613
2614 insns.push((
2615 Inst::VecRRNarrow {
2616 op: VecRRNarrowOp::Fcvtn32,
2617 rd: writable_vreg(0),
2618 rn: vreg(0),
2619 high_half: false,
2620 },
2621 "0068210E",
2622 "fcvtn v0.4h, v0.4s",
2623 ));
2624
2625 insns.push((
2626 Inst::VecRRNarrow {
2627 op: VecRRNarrowOp::Fcvtn64,
2628 rd: writable_vreg(31),
2629 rn: vreg(30),
2630 high_half: true,
2631 },
2632 "DF6B614E",
2633 "fcvtn2 v31.4s, v30.2d",
2634 ));
2635
2636 insns.push((
2637 Inst::VecRRPair {
2638 op: VecPairOp::Addp,
2639 rd: writable_vreg(0),
2640 rn: vreg(30),
2641 },
2642 "C0BBF15E",
2643 "addp d0, v30.2d",
2644 ));
2645
2646 insns.push((
2647 Inst::VecRRPairLong {
2648 op: VecRRPairLongOp::Uaddlp8,
2649 rd: writable_vreg(0),
2650 rn: vreg(1),
2651 },
2652 "2028206E",
2653 "uaddlp v0.8h, v1.16b",
2654 ));
2655
2656 insns.push((
2657 Inst::VecRRPairLong {
2658 op: VecRRPairLongOp::Saddlp8,
2659 rd: writable_vreg(3),
2660 rn: vreg(11),
2661 },
2662 "6329204E",
2663 "saddlp v3.8h, v11.16b",
2664 ));
2665
2666 insns.push((
2667 Inst::VecRRPairLong {
2668 op: VecRRPairLongOp::Uaddlp16,
2669 rd: writable_vreg(14),
2670 rn: vreg(23),
2671 },
2672 "EE2A606E",
2673 "uaddlp v14.4s, v23.8h",
2674 ));
2675
2676 insns.push((
2677 Inst::VecRRPairLong {
2678 op: VecRRPairLongOp::Saddlp16,
2679 rd: writable_vreg(29),
2680 rn: vreg(0),
2681 },
2682 "1D28604E",
2683 "saddlp v29.4s, v0.8h",
2684 ));
2685
2686 insns.push((
2687 Inst::VecRRR {
2688 alu_op: VecALUOp::Sqadd,
2689 rd: writable_vreg(1),
2690 rn: vreg(2),
2691 rm: vreg(8),
2692 size: VectorSize::Size8x16,
2693 },
2694 "410C284E",
2695 "sqadd v1.16b, v2.16b, v8.16b",
2696 ));
2697
2698 insns.push((
2699 Inst::VecRRR {
2700 alu_op: VecALUOp::Sqadd,
2701 rd: writable_vreg(1),
2702 rn: vreg(12),
2703 rm: vreg(28),
2704 size: VectorSize::Size16x8,
2705 },
2706 "810D7C4E",
2707 "sqadd v1.8h, v12.8h, v28.8h",
2708 ));
2709
2710 insns.push((
2711 Inst::VecRRR {
2712 alu_op: VecALUOp::Sqadd,
2713 rd: writable_vreg(12),
2714 rn: vreg(2),
2715 rm: vreg(6),
2716 size: VectorSize::Size32x4,
2717 },
2718 "4C0CA64E",
2719 "sqadd v12.4s, v2.4s, v6.4s",
2720 ));
2721
2722 insns.push((
2723 Inst::VecRRR {
2724 alu_op: VecALUOp::Sqadd,
2725 rd: writable_vreg(20),
2726 rn: vreg(7),
2727 rm: vreg(13),
2728 size: VectorSize::Size64x2,
2729 },
2730 "F40CED4E",
2731 "sqadd v20.2d, v7.2d, v13.2d",
2732 ));
2733
2734 insns.push((
2735 Inst::VecRRR {
2736 alu_op: VecALUOp::Sqsub,
2737 rd: writable_vreg(1),
2738 rn: vreg(2),
2739 rm: vreg(8),
2740 size: VectorSize::Size8x16,
2741 },
2742 "412C284E",
2743 "sqsub v1.16b, v2.16b, v8.16b",
2744 ));
2745
2746 insns.push((
2747 Inst::VecRRR {
2748 alu_op: VecALUOp::Sqsub,
2749 rd: writable_vreg(1),
2750 rn: vreg(12),
2751 rm: vreg(28),
2752 size: VectorSize::Size16x8,
2753 },
2754 "812D7C4E",
2755 "sqsub v1.8h, v12.8h, v28.8h",
2756 ));
2757
2758 insns.push((
2759 Inst::VecRRR {
2760 alu_op: VecALUOp::Sqsub,
2761 rd: writable_vreg(12),
2762 rn: vreg(2),
2763 rm: vreg(6),
2764 size: VectorSize::Size32x4,
2765 },
2766 "4C2CA64E",
2767 "sqsub v12.4s, v2.4s, v6.4s",
2768 ));
2769
2770 insns.push((
2771 Inst::VecRRR {
2772 alu_op: VecALUOp::Sqsub,
2773 rd: writable_vreg(20),
2774 rn: vreg(7),
2775 rm: vreg(13),
2776 size: VectorSize::Size64x2,
2777 },
2778 "F42CED4E",
2779 "sqsub v20.2d, v7.2d, v13.2d",
2780 ));
2781
2782 insns.push((
2783 Inst::VecRRR {
2784 alu_op: VecALUOp::Uqadd,
2785 rd: writable_vreg(1),
2786 rn: vreg(2),
2787 rm: vreg(8),
2788 size: VectorSize::Size8x16,
2789 },
2790 "410C286E",
2791 "uqadd v1.16b, v2.16b, v8.16b",
2792 ));
2793
2794 insns.push((
2795 Inst::VecRRR {
2796 alu_op: VecALUOp::Uqadd,
2797 rd: writable_vreg(1),
2798 rn: vreg(12),
2799 rm: vreg(28),
2800 size: VectorSize::Size16x8,
2801 },
2802 "810D7C6E",
2803 "uqadd v1.8h, v12.8h, v28.8h",
2804 ));
2805
2806 insns.push((
2807 Inst::VecRRR {
2808 alu_op: VecALUOp::Uqadd,
2809 rd: writable_vreg(12),
2810 rn: vreg(2),
2811 rm: vreg(6),
2812 size: VectorSize::Size32x4,
2813 },
2814 "4C0CA66E",
2815 "uqadd v12.4s, v2.4s, v6.4s",
2816 ));
2817
2818 insns.push((
2819 Inst::VecRRR {
2820 alu_op: VecALUOp::Uqadd,
2821 rd: writable_vreg(20),
2822 rn: vreg(7),
2823 rm: vreg(13),
2824 size: VectorSize::Size64x2,
2825 },
2826 "F40CED6E",
2827 "uqadd v20.2d, v7.2d, v13.2d",
2828 ));
2829
2830 insns.push((
2831 Inst::VecRRR {
2832 alu_op: VecALUOp::Uqsub,
2833 rd: writable_vreg(1),
2834 rn: vreg(2),
2835 rm: vreg(8),
2836 size: VectorSize::Size8x16,
2837 },
2838 "412C286E",
2839 "uqsub v1.16b, v2.16b, v8.16b",
2840 ));
2841
2842 insns.push((
2843 Inst::VecRRR {
2844 alu_op: VecALUOp::Uqsub,
2845 rd: writable_vreg(1),
2846 rn: vreg(12),
2847 rm: vreg(28),
2848 size: VectorSize::Size16x8,
2849 },
2850 "812D7C6E",
2851 "uqsub v1.8h, v12.8h, v28.8h",
2852 ));
2853
2854 insns.push((
2855 Inst::VecRRR {
2856 alu_op: VecALUOp::Uqsub,
2857 rd: writable_vreg(12),
2858 rn: vreg(2),
2859 rm: vreg(6),
2860 size: VectorSize::Size32x4,
2861 },
2862 "4C2CA66E",
2863 "uqsub v12.4s, v2.4s, v6.4s",
2864 ));
2865
2866 insns.push((
2867 Inst::VecRRR {
2868 alu_op: VecALUOp::Uqsub,
2869 rd: writable_vreg(20),
2870 rn: vreg(7),
2871 rm: vreg(13),
2872 size: VectorSize::Size64x2,
2873 },
2874 "F42CED6E",
2875 "uqsub v20.2d, v7.2d, v13.2d",
2876 ));
2877
2878 insns.push((
2879 Inst::VecRRR {
2880 alu_op: VecALUOp::Cmeq,
2881 rd: writable_vreg(3),
2882 rn: vreg(23),
2883 rm: vreg(24),
2884 size: VectorSize::Size8x16,
2885 },
2886 "E38E386E",
2887 "cmeq v3.16b, v23.16b, v24.16b",
2888 ));
2889
2890 insns.push((
2891 Inst::VecRRR {
2892 alu_op: VecALUOp::Cmgt,
2893 rd: writable_vreg(3),
2894 rn: vreg(23),
2895 rm: vreg(24),
2896 size: VectorSize::Size8x16,
2897 },
2898 "E336384E",
2899 "cmgt v3.16b, v23.16b, v24.16b",
2900 ));
2901
2902 insns.push((
2903 Inst::VecRRR {
2904 alu_op: VecALUOp::Cmge,
2905 rd: writable_vreg(23),
2906 rn: vreg(9),
2907 rm: vreg(12),
2908 size: VectorSize::Size8x16,
2909 },
2910 "373D2C4E",
2911 "cmge v23.16b, v9.16b, v12.16b",
2912 ));
2913
2914 insns.push((
2915 Inst::VecRRR {
2916 alu_op: VecALUOp::Cmhi,
2917 rd: writable_vreg(5),
2918 rn: vreg(1),
2919 rm: vreg(1),
2920 size: VectorSize::Size8x16,
2921 },
2922 "2534216E",
2923 "cmhi v5.16b, v1.16b, v1.16b",
2924 ));
2925
2926 insns.push((
2927 Inst::VecRRR {
2928 alu_op: VecALUOp::Cmhs,
2929 rd: writable_vreg(8),
2930 rn: vreg(2),
2931 rm: vreg(15),
2932 size: VectorSize::Size8x16,
2933 },
2934 "483C2F6E",
2935 "cmhs v8.16b, v2.16b, v15.16b",
2936 ));
2937
2938 insns.push((
2939 Inst::VecRRR {
2940 alu_op: VecALUOp::Cmeq,
2941 rd: writable_vreg(3),
2942 rn: vreg(23),
2943 rm: vreg(24),
2944 size: VectorSize::Size16x8,
2945 },
2946 "E38E786E",
2947 "cmeq v3.8h, v23.8h, v24.8h",
2948 ));
2949
2950 insns.push((
2951 Inst::VecRRR {
2952 alu_op: VecALUOp::Cmgt,
2953 rd: writable_vreg(3),
2954 rn: vreg(23),
2955 rm: vreg(24),
2956 size: VectorSize::Size16x8,
2957 },
2958 "E336784E",
2959 "cmgt v3.8h, v23.8h, v24.8h",
2960 ));
2961
2962 insns.push((
2963 Inst::VecRRR {
2964 alu_op: VecALUOp::Cmge,
2965 rd: writable_vreg(23),
2966 rn: vreg(9),
2967 rm: vreg(12),
2968 size: VectorSize::Size16x8,
2969 },
2970 "373D6C4E",
2971 "cmge v23.8h, v9.8h, v12.8h",
2972 ));
2973
2974 insns.push((
2975 Inst::VecRRR {
2976 alu_op: VecALUOp::Cmhi,
2977 rd: writable_vreg(5),
2978 rn: vreg(1),
2979 rm: vreg(1),
2980 size: VectorSize::Size16x8,
2981 },
2982 "2534616E",
2983 "cmhi v5.8h, v1.8h, v1.8h",
2984 ));
2985
2986 insns.push((
2987 Inst::VecRRR {
2988 alu_op: VecALUOp::Cmhs,
2989 rd: writable_vreg(8),
2990 rn: vreg(2),
2991 rm: vreg(15),
2992 size: VectorSize::Size16x8,
2993 },
2994 "483C6F6E",
2995 "cmhs v8.8h, v2.8h, v15.8h",
2996 ));
2997
2998 insns.push((
2999 Inst::VecRRR {
3000 alu_op: VecALUOp::Cmeq,
3001 rd: writable_vreg(3),
3002 rn: vreg(23),
3003 rm: vreg(24),
3004 size: VectorSize::Size32x4,
3005 },
3006 "E38EB86E",
3007 "cmeq v3.4s, v23.4s, v24.4s",
3008 ));
3009
3010 insns.push((
3011 Inst::VecRRR {
3012 alu_op: VecALUOp::Cmgt,
3013 rd: writable_vreg(3),
3014 rn: vreg(23),
3015 rm: vreg(24),
3016 size: VectorSize::Size32x4,
3017 },
3018 "E336B84E",
3019 "cmgt v3.4s, v23.4s, v24.4s",
3020 ));
3021
3022 insns.push((
3023 Inst::VecRRR {
3024 alu_op: VecALUOp::Cmge,
3025 rd: writable_vreg(23),
3026 rn: vreg(9),
3027 rm: vreg(12),
3028 size: VectorSize::Size32x4,
3029 },
3030 "373DAC4E",
3031 "cmge v23.4s, v9.4s, v12.4s",
3032 ));
3033
3034 insns.push((
3035 Inst::VecRRR {
3036 alu_op: VecALUOp::Cmhi,
3037 rd: writable_vreg(5),
3038 rn: vreg(1),
3039 rm: vreg(1),
3040 size: VectorSize::Size32x4,
3041 },
3042 "2534A16E",
3043 "cmhi v5.4s, v1.4s, v1.4s",
3044 ));
3045
3046 insns.push((
3047 Inst::VecRRR {
3048 alu_op: VecALUOp::Cmhs,
3049 rd: writable_vreg(8),
3050 rn: vreg(2),
3051 rm: vreg(15),
3052 size: VectorSize::Size32x4,
3053 },
3054 "483CAF6E",
3055 "cmhs v8.4s, v2.4s, v15.4s",
3056 ));
3057
3058 insns.push((
3059 Inst::VecRRR {
3060 alu_op: VecALUOp::Fcmeq,
3061 rd: writable_vreg(28),
3062 rn: vreg(12),
3063 rm: vreg(4),
3064 size: VectorSize::Size32x2,
3065 },
3066 "9CE5240E",
3067 "fcmeq v28.2s, v12.2s, v4.2s",
3068 ));
3069
3070 insns.push((
3071 Inst::VecRRR {
3072 alu_op: VecALUOp::Fcmgt,
3073 rd: writable_vreg(3),
3074 rn: vreg(16),
3075 rm: vreg(31),
3076 size: VectorSize::Size64x2,
3077 },
3078 "03E6FF6E",
3079 "fcmgt v3.2d, v16.2d, v31.2d",
3080 ));
3081
3082 insns.push((
3083 Inst::VecRRR {
3084 alu_op: VecALUOp::Fcmge,
3085 rd: writable_vreg(18),
3086 rn: vreg(23),
3087 rm: vreg(0),
3088 size: VectorSize::Size64x2,
3089 },
3090 "F2E6606E",
3091 "fcmge v18.2d, v23.2d, v0.2d",
3092 ));
3093
3094 insns.push((
3095 Inst::VecRRR {
3096 alu_op: VecALUOp::And,
3097 rd: writable_vreg(20),
3098 rn: vreg(19),
3099 rm: vreg(18),
3100 size: VectorSize::Size32x4,
3101 },
3102 "741E324E",
3103 "and v20.16b, v19.16b, v18.16b",
3104 ));
3105
3106 insns.push((
3107 Inst::VecRRR {
3108 alu_op: VecALUOp::Bic,
3109 rd: writable_vreg(8),
3110 rn: vreg(11),
3111 rm: vreg(1),
3112 size: VectorSize::Size8x16,
3113 },
3114 "681D614E",
3115 "bic v8.16b, v11.16b, v1.16b",
3116 ));
3117
3118 insns.push((
3119 Inst::VecRRR {
3120 alu_op: VecALUOp::Orr,
3121 rd: writable_vreg(15),
3122 rn: vreg(2),
3123 rm: vreg(12),
3124 size: VectorSize::Size16x8,
3125 },
3126 "4F1CAC4E",
3127 "orr v15.16b, v2.16b, v12.16b",
3128 ));
3129
3130 insns.push((
3131 Inst::VecRRR {
3132 alu_op: VecALUOp::Eor,
3133 rd: writable_vreg(18),
3134 rn: vreg(3),
3135 rm: vreg(22),
3136 size: VectorSize::Size8x16,
3137 },
3138 "721C366E",
3139 "eor v18.16b, v3.16b, v22.16b",
3140 ));
3141
3142 insns.push((
3143 Inst::VecRRR {
3144 alu_op: VecALUOp::Bsl,
3145 rd: writable_vreg(8),
3146 rn: vreg(9),
3147 rm: vreg(1),
3148 size: VectorSize::Size8x16,
3149 },
3150 "281D616E",
3151 "bsl v8.16b, v9.16b, v1.16b",
3152 ));
3153
3154 insns.push((
3155 Inst::VecRRR {
3156 alu_op: VecALUOp::Umaxp,
3157 rd: writable_vreg(8),
3158 rn: vreg(12),
3159 rm: vreg(1),
3160 size: VectorSize::Size8x16,
3161 },
3162 "88A5216E",
3163 "umaxp v8.16b, v12.16b, v1.16b",
3164 ));
3165
3166 insns.push((
3167 Inst::VecRRR {
3168 alu_op: VecALUOp::Umaxp,
3169 rd: writable_vreg(1),
3170 rn: vreg(6),
3171 rm: vreg(1),
3172 size: VectorSize::Size16x8,
3173 },
3174 "C1A4616E",
3175 "umaxp v1.8h, v6.8h, v1.8h",
3176 ));
3177
3178 insns.push((
3179 Inst::VecRRR {
3180 alu_op: VecALUOp::Umaxp,
3181 rd: writable_vreg(1),
3182 rn: vreg(20),
3183 rm: vreg(16),
3184 size: VectorSize::Size32x4,
3185 },
3186 "81A6B06E",
3187 "umaxp v1.4s, v20.4s, v16.4s",
3188 ));
3189
3190 insns.push((
3191 Inst::VecRRR {
3192 alu_op: VecALUOp::Add,
3193 rd: writable_vreg(5),
3194 rn: vreg(1),
3195 rm: vreg(1),
3196 size: VectorSize::Size8x16,
3197 },
3198 "2584214E",
3199 "add v5.16b, v1.16b, v1.16b",
3200 ));
3201
3202 insns.push((
3203 Inst::VecRRR {
3204 alu_op: VecALUOp::Add,
3205 rd: writable_vreg(7),
3206 rn: vreg(13),
3207 rm: vreg(2),
3208 size: VectorSize::Size16x8,
3209 },
3210 "A785624E",
3211 "add v7.8h, v13.8h, v2.8h",
3212 ));
3213
3214 insns.push((
3215 Inst::VecRRR {
3216 alu_op: VecALUOp::Add,
3217 rd: writable_vreg(18),
3218 rn: vreg(9),
3219 rm: vreg(6),
3220 size: VectorSize::Size32x4,
3221 },
3222 "3285A64E",
3223 "add v18.4s, v9.4s, v6.4s",
3224 ));
3225
3226 insns.push((
3227 Inst::VecRRR {
3228 alu_op: VecALUOp::Add,
3229 rd: writable_vreg(1),
3230 rn: vreg(3),
3231 rm: vreg(2),
3232 size: VectorSize::Size64x2,
3233 },
3234 "6184E24E",
3235 "add v1.2d, v3.2d, v2.2d",
3236 ));
3237
3238 insns.push((
3239 Inst::VecRRR {
3240 alu_op: VecALUOp::Sub,
3241 rd: writable_vreg(5),
3242 rn: vreg(1),
3243 rm: vreg(1),
3244 size: VectorSize::Size8x16,
3245 },
3246 "2584216E",
3247 "sub v5.16b, v1.16b, v1.16b",
3248 ));
3249
3250 insns.push((
3251 Inst::VecRRR {
3252 alu_op: VecALUOp::Sub,
3253 rd: writable_vreg(7),
3254 rn: vreg(13),
3255 rm: vreg(2),
3256 size: VectorSize::Size16x8,
3257 },
3258 "A785626E",
3259 "sub v7.8h, v13.8h, v2.8h",
3260 ));
3261
3262 insns.push((
3263 Inst::VecRRR {
3264 alu_op: VecALUOp::Sub,
3265 rd: writable_vreg(18),
3266 rn: vreg(9),
3267 rm: vreg(6),
3268 size: VectorSize::Size32x4,
3269 },
3270 "3285A66E",
3271 "sub v18.4s, v9.4s, v6.4s",
3272 ));
3273
3274 insns.push((
3275 Inst::VecRRR {
3276 alu_op: VecALUOp::Sub,
3277 rd: writable_vreg(18),
3278 rn: vreg(0),
3279 rm: vreg(8),
3280 size: VectorSize::Size64x2,
3281 },
3282 "1284E86E",
3283 "sub v18.2d, v0.2d, v8.2d",
3284 ));
3285
3286 insns.push((
3287 Inst::VecRRR {
3288 alu_op: VecALUOp::Mul,
3289 rd: writable_vreg(25),
3290 rn: vreg(9),
3291 rm: vreg(8),
3292 size: VectorSize::Size8x16,
3293 },
3294 "399D284E",
3295 "mul v25.16b, v9.16b, v8.16b",
3296 ));
3297
3298 insns.push((
3299 Inst::VecRRR {
3300 alu_op: VecALUOp::Mul,
3301 rd: writable_vreg(30),
3302 rn: vreg(30),
3303 rm: vreg(12),
3304 size: VectorSize::Size16x8,
3305 },
3306 "DE9F6C4E",
3307 "mul v30.8h, v30.8h, v12.8h",
3308 ));
3309
3310 insns.push((
3311 Inst::VecRRR {
3312 alu_op: VecALUOp::Mul,
3313 rd: writable_vreg(18),
3314 rn: vreg(18),
3315 rm: vreg(18),
3316 size: VectorSize::Size32x4,
3317 },
3318 "529EB24E",
3319 "mul v18.4s, v18.4s, v18.4s",
3320 ));
3321
3322 insns.push((
3323 Inst::VecRRR {
3324 alu_op: VecALUOp::Ushl,
3325 rd: writable_vreg(18),
3326 rn: vreg(18),
3327 rm: vreg(18),
3328 size: VectorSize::Size8x16,
3329 },
3330 "5246326E",
3331 "ushl v18.16b, v18.16b, v18.16b",
3332 ));
3333
3334 insns.push((
3335 Inst::VecRRR {
3336 alu_op: VecALUOp::Ushl,
3337 rd: writable_vreg(18),
3338 rn: vreg(18),
3339 rm: vreg(18),
3340 size: VectorSize::Size16x8,
3341 },
3342 "5246726E",
3343 "ushl v18.8h, v18.8h, v18.8h",
3344 ));
3345
3346 insns.push((
3347 Inst::VecRRR {
3348 alu_op: VecALUOp::Ushl,
3349 rd: writable_vreg(18),
3350 rn: vreg(1),
3351 rm: vreg(21),
3352 size: VectorSize::Size32x4,
3353 },
3354 "3244B56E",
3355 "ushl v18.4s, v1.4s, v21.4s",
3356 ));
3357
3358 insns.push((
3359 Inst::VecRRR {
3360 alu_op: VecALUOp::Ushl,
3361 rd: writable_vreg(5),
3362 rn: vreg(7),
3363 rm: vreg(19),
3364 size: VectorSize::Size64x2,
3365 },
3366 "E544F36E",
3367 "ushl v5.2d, v7.2d, v19.2d",
3368 ));
3369
3370 insns.push((
3371 Inst::VecRRR {
3372 alu_op: VecALUOp::Sshl,
3373 rd: writable_vreg(18),
3374 rn: vreg(18),
3375 rm: vreg(18),
3376 size: VectorSize::Size8x16,
3377 },
3378 "5246324E",
3379 "sshl v18.16b, v18.16b, v18.16b",
3380 ));
3381
3382 insns.push((
3383 Inst::VecRRR {
3384 alu_op: VecALUOp::Sshl,
3385 rd: writable_vreg(30),
3386 rn: vreg(1),
3387 rm: vreg(29),
3388 size: VectorSize::Size16x8,
3389 },
3390 "3E447D4E",
3391 "sshl v30.8h, v1.8h, v29.8h",
3392 ));
3393
3394 insns.push((
3395 Inst::VecRRR {
3396 alu_op: VecALUOp::Sshl,
3397 rd: writable_vreg(8),
3398 rn: vreg(22),
3399 rm: vreg(21),
3400 size: VectorSize::Size32x4,
3401 },
3402 "C846B54E",
3403 "sshl v8.4s, v22.4s, v21.4s",
3404 ));
3405
3406 insns.push((
3407 Inst::VecRRR {
3408 alu_op: VecALUOp::Sshl,
3409 rd: writable_vreg(8),
3410 rn: vreg(22),
3411 rm: vreg(2),
3412 size: VectorSize::Size64x2,
3413 },
3414 "C846E24E",
3415 "sshl v8.2d, v22.2d, v2.2d",
3416 ));
3417
3418 insns.push((
3419 Inst::VecRRR {
3420 alu_op: VecALUOp::Umin,
3421 rd: writable_vreg(1),
3422 rn: vreg(12),
3423 rm: vreg(3),
3424 size: VectorSize::Size8x16,
3425 },
3426 "816D236E",
3427 "umin v1.16b, v12.16b, v3.16b",
3428 ));
3429
3430 insns.push((
3431 Inst::VecRRR {
3432 alu_op: VecALUOp::Umin,
3433 rd: writable_vreg(30),
3434 rn: vreg(20),
3435 rm: vreg(10),
3436 size: VectorSize::Size16x8,
3437 },
3438 "9E6E6A6E",
3439 "umin v30.8h, v20.8h, v10.8h",
3440 ));
3441
3442 insns.push((
3443 Inst::VecRRR {
3444 alu_op: VecALUOp::Umin,
3445 rd: writable_vreg(8),
3446 rn: vreg(22),
3447 rm: vreg(21),
3448 size: VectorSize::Size32x4,
3449 },
3450 "C86EB56E",
3451 "umin v8.4s, v22.4s, v21.4s",
3452 ));
3453
3454 insns.push((
3455 Inst::VecRRR {
3456 alu_op: VecALUOp::Smin,
3457 rd: writable_vreg(1),
3458 rn: vreg(12),
3459 rm: vreg(3),
3460 size: VectorSize::Size8x16,
3461 },
3462 "816D234E",
3463 "smin v1.16b, v12.16b, v3.16b",
3464 ));
3465
3466 insns.push((
3467 Inst::VecRRR {
3468 alu_op: VecALUOp::Smin,
3469 rd: writable_vreg(30),
3470 rn: vreg(20),
3471 rm: vreg(10),
3472 size: VectorSize::Size16x8,
3473 },
3474 "9E6E6A4E",
3475 "smin v30.8h, v20.8h, v10.8h",
3476 ));
3477
3478 insns.push((
3479 Inst::VecRRR {
3480 alu_op: VecALUOp::Smin,
3481 rd: writable_vreg(8),
3482 rn: vreg(22),
3483 rm: vreg(21),
3484 size: VectorSize::Size32x4,
3485 },
3486 "C86EB54E",
3487 "smin v8.4s, v22.4s, v21.4s",
3488 ));
3489
3490 insns.push((
3491 Inst::VecRRR {
3492 alu_op: VecALUOp::Umax,
3493 rd: writable_vreg(6),
3494 rn: vreg(9),
3495 rm: vreg(8),
3496 size: VectorSize::Size8x8,
3497 },
3498 "2665282E",
3499 "umax v6.8b, v9.8b, v8.8b",
3500 ));
3501
3502 insns.push((
3503 Inst::VecRRR {
3504 alu_op: VecALUOp::Umax,
3505 rd: writable_vreg(11),
3506 rn: vreg(13),
3507 rm: vreg(2),
3508 size: VectorSize::Size16x8,
3509 },
3510 "AB65626E",
3511 "umax v11.8h, v13.8h, v2.8h",
3512 ));
3513
3514 insns.push((
3515 Inst::VecRRR {
3516 alu_op: VecALUOp::Umax,
3517 rd: writable_vreg(8),
3518 rn: vreg(12),
3519 rm: vreg(14),
3520 size: VectorSize::Size32x4,
3521 },
3522 "8865AE6E",
3523 "umax v8.4s, v12.4s, v14.4s",
3524 ));
3525
3526 insns.push((
3527 Inst::VecRRR {
3528 alu_op: VecALUOp::Smax,
3529 rd: writable_vreg(6),
3530 rn: vreg(9),
3531 rm: vreg(8),
3532 size: VectorSize::Size8x16,
3533 },
3534 "2665284E",
3535 "smax v6.16b, v9.16b, v8.16b",
3536 ));
3537
3538 insns.push((
3539 Inst::VecRRR {
3540 alu_op: VecALUOp::Smax,
3541 rd: writable_vreg(11),
3542 rn: vreg(13),
3543 rm: vreg(2),
3544 size: VectorSize::Size16x8,
3545 },
3546 "AB65624E",
3547 "smax v11.8h, v13.8h, v2.8h",
3548 ));
3549
3550 insns.push((
3551 Inst::VecRRR {
3552 alu_op: VecALUOp::Smax,
3553 rd: writable_vreg(8),
3554 rn: vreg(12),
3555 rm: vreg(14),
3556 size: VectorSize::Size32x4,
3557 },
3558 "8865AE4E",
3559 "smax v8.4s, v12.4s, v14.4s",
3560 ));
3561
3562 insns.push((
3563 Inst::VecRRR {
3564 alu_op: VecALUOp::Urhadd,
3565 rd: writable_vreg(8),
3566 rn: vreg(1),
3567 rm: vreg(3),
3568 size: VectorSize::Size8x16,
3569 },
3570 "2814236E",
3571 "urhadd v8.16b, v1.16b, v3.16b",
3572 ));
3573
3574 insns.push((
3575 Inst::VecRRR {
3576 alu_op: VecALUOp::Urhadd,
3577 rd: writable_vreg(2),
3578 rn: vreg(13),
3579 rm: vreg(6),
3580 size: VectorSize::Size16x8,
3581 },
3582 "A215666E",
3583 "urhadd v2.8h, v13.8h, v6.8h",
3584 ));
3585
3586 insns.push((
3587 Inst::VecRRR {
3588 alu_op: VecALUOp::Urhadd,
3589 rd: writable_vreg(8),
3590 rn: vreg(12),
3591 rm: vreg(14),
3592 size: VectorSize::Size32x4,
3593 },
3594 "8815AE6E",
3595 "urhadd v8.4s, v12.4s, v14.4s",
3596 ));
3597
3598 insns.push((
3599 Inst::VecRRR {
3600 alu_op: VecALUOp::Fadd,
3601 rd: writable_vreg(31),
3602 rn: vreg(0),
3603 rm: vreg(16),
3604 size: VectorSize::Size32x4,
3605 },
3606 "1FD4304E",
3607 "fadd v31.4s, v0.4s, v16.4s",
3608 ));
3609
3610 insns.push((
3611 Inst::VecRRR {
3612 alu_op: VecALUOp::Fsub,
3613 rd: writable_vreg(8),
3614 rn: vreg(7),
3615 rm: vreg(15),
3616 size: VectorSize::Size64x2,
3617 },
3618 "E8D4EF4E",
3619 "fsub v8.2d, v7.2d, v15.2d",
3620 ));
3621
3622 insns.push((
3623 Inst::VecRRR {
3624 alu_op: VecALUOp::Fdiv,
3625 rd: writable_vreg(1),
3626 rn: vreg(3),
3627 rm: vreg(4),
3628 size: VectorSize::Size32x4,
3629 },
3630 "61FC246E",
3631 "fdiv v1.4s, v3.4s, v4.4s",
3632 ));
3633
3634 insns.push((
3635 Inst::VecRRR {
3636 alu_op: VecALUOp::Fmax,
3637 rd: writable_vreg(31),
3638 rn: vreg(16),
3639 rm: vreg(0),
3640 size: VectorSize::Size64x2,
3641 },
3642 "1FF6604E",
3643 "fmax v31.2d, v16.2d, v0.2d",
3644 ));
3645
3646 insns.push((
3647 Inst::VecRRR {
3648 alu_op: VecALUOp::Fmin,
3649 rd: writable_vreg(5),
3650 rn: vreg(19),
3651 rm: vreg(26),
3652 size: VectorSize::Size32x4,
3653 },
3654 "65F6BA4E",
3655 "fmin v5.4s, v19.4s, v26.4s",
3656 ));
3657
3658 insns.push((
3659 Inst::VecRRR {
3660 alu_op: VecALUOp::Fmul,
3661 rd: writable_vreg(2),
3662 rn: vreg(0),
3663 rm: vreg(5),
3664 size: VectorSize::Size64x2,
3665 },
3666 "02DC656E",
3667 "fmul v2.2d, v0.2d, v5.2d",
3668 ));
3669
3670 insns.push((
3671 Inst::VecRRR {
3672 alu_op: VecALUOp::Addp,
3673 rd: writable_vreg(16),
3674 rn: vreg(12),
3675 rm: vreg(1),
3676 size: VectorSize::Size8x16,
3677 },
3678 "90BD214E",
3679 "addp v16.16b, v12.16b, v1.16b",
3680 ));
3681
3682 insns.push((
3683 Inst::VecRRR {
3684 alu_op: VecALUOp::Addp,
3685 rd: writable_vreg(8),
3686 rn: vreg(12),
3687 rm: vreg(14),
3688 size: VectorSize::Size32x4,
3689 },
3690 "88BDAE4E",
3691 "addp v8.4s, v12.4s, v14.4s",
3692 ));
3693
3694 insns.push((
3695 Inst::VecRRR {
3696 alu_op: VecALUOp::Zip1,
3697 rd: writable_vreg(16),
3698 rn: vreg(12),
3699 rm: vreg(1),
3700 size: VectorSize::Size8x16,
3701 },
3702 "9039014E",
3703 "zip1 v16.16b, v12.16b, v1.16b",
3704 ));
3705
3706 insns.push((
3707 Inst::VecRRR {
3708 alu_op: VecALUOp::Zip1,
3709 rd: writable_vreg(2),
3710 rn: vreg(13),
3711 rm: vreg(6),
3712 size: VectorSize::Size16x8,
3713 },
3714 "A239464E",
3715 "zip1 v2.8h, v13.8h, v6.8h",
3716 ));
3717
3718 insns.push((
3719 Inst::VecRRR {
3720 alu_op: VecALUOp::Zip1,
3721 rd: writable_vreg(8),
3722 rn: vreg(12),
3723 rm: vreg(14),
3724 size: VectorSize::Size32x4,
3725 },
3726 "88398E4E",
3727 "zip1 v8.4s, v12.4s, v14.4s",
3728 ));
3729
3730 insns.push((
3731 Inst::VecRRR {
3732 alu_op: VecALUOp::Zip1,
3733 rd: writable_vreg(9),
3734 rn: vreg(20),
3735 rm: vreg(17),
3736 size: VectorSize::Size64x2,
3737 },
3738 "893AD14E",
3739 "zip1 v9.2d, v20.2d, v17.2d",
3740 ));
3741
3742 insns.push((
3743 Inst::VecRRRLong {
3744 alu_op: VecRRRLongOp::Smull8,
3745 rd: writable_vreg(16),
3746 rn: vreg(12),
3747 rm: vreg(1),
3748 high_half: false,
3749 },
3750 "90C1210E",
3751 "smull v16.8h, v12.8b, v1.8b",
3752 ));
3753
3754 insns.push((
3755 Inst::VecRRRLong {
3756 alu_op: VecRRRLongOp::Umull8,
3757 rd: writable_vreg(15),
3758 rn: vreg(11),
3759 rm: vreg(2),
3760 high_half: false,
3761 },
3762 "6FC1222E",
3763 "umull v15.8h, v11.8b, v2.8b",
3764 ));
3765
3766 insns.push((
3767 Inst::VecRRRLong {
3768 alu_op: VecRRRLongOp::Umlal8,
3769 rd: writable_vreg(4),
3770 rn: vreg(8),
3771 rm: vreg(16),
3772 high_half: false,
3773 },
3774 "0481302E",
3775 "umlal v4.8h, v8.8b, v16.8b",
3776 ));
3777
3778 insns.push((
3779 Inst::VecRRRLong {
3780 alu_op: VecRRRLongOp::Smull16,
3781 rd: writable_vreg(2),
3782 rn: vreg(13),
3783 rm: vreg(6),
3784 high_half: false,
3785 },
3786 "A2C1660E",
3787 "smull v2.4s, v13.4h, v6.4h",
3788 ));
3789
3790 insns.push((
3791 Inst::VecRRRLong {
3792 alu_op: VecRRRLongOp::Umull16,
3793 rd: writable_vreg(3),
3794 rn: vreg(14),
3795 rm: vreg(7),
3796 high_half: false,
3797 },
3798 "C3C1672E",
3799 "umull v3.4s, v14.4h, v7.4h",
3800 ));
3801
3802 insns.push((
3803 Inst::VecRRRLong {
3804 alu_op: VecRRRLongOp::Umlal16,
3805 rd: writable_vreg(7),
3806 rn: vreg(14),
3807 rm: vreg(21),
3808 high_half: false,
3809 },
3810 "C781752E",
3811 "umlal v7.4s, v14.4h, v21.4h",
3812 ));
3813
3814 insns.push((
3815 Inst::VecRRRLong {
3816 alu_op: VecRRRLongOp::Smull32,
3817 rd: writable_vreg(8),
3818 rn: vreg(12),
3819 rm: vreg(14),
3820 high_half: false,
3821 },
3822 "88C1AE0E",
3823 "smull v8.2d, v12.2s, v14.2s",
3824 ));
3825
3826 insns.push((
3827 Inst::VecRRRLong {
3828 alu_op: VecRRRLongOp::Umull32,
3829 rd: writable_vreg(9),
3830 rn: vreg(5),
3831 rm: vreg(6),
3832 high_half: false,
3833 },
3834 "A9C0A62E",
3835 "umull v9.2d, v5.2s, v6.2s",
3836 ));
3837
3838 insns.push((
3839 Inst::VecRRRLong {
3840 alu_op: VecRRRLongOp::Umlal32,
3841 rd: writable_vreg(9),
3842 rn: vreg(20),
3843 rm: vreg(17),
3844 high_half: false,
3845 },
3846 "8982B12E",
3847 "umlal v9.2d, v20.2s, v17.2s",
3848 ));
3849
3850 insns.push((
3851 Inst::VecRRRLong {
3852 alu_op: VecRRRLongOp::Smull8,
3853 rd: writable_vreg(16),
3854 rn: vreg(12),
3855 rm: vreg(1),
3856 high_half: true,
3857 },
3858 "90C1214E",
3859 "smull2 v16.8h, v12.16b, v1.16b",
3860 ));
3861
3862 insns.push((
3863 Inst::VecRRRLong {
3864 alu_op: VecRRRLongOp::Umull8,
3865 rd: writable_vreg(29),
3866 rn: vreg(22),
3867 rm: vreg(10),
3868 high_half: true,
3869 },
3870 "DDC22A6E",
3871 "umull2 v29.8h, v22.16b, v10.16b",
3872 ));
3873
3874 insns.push((
3875 Inst::VecRRRLong {
3876 alu_op: VecRRRLongOp::Umlal8,
3877 rd: writable_vreg(1),
3878 rn: vreg(5),
3879 rm: vreg(15),
3880 high_half: true,
3881 },
3882 "A1802F6E",
3883 "umlal2 v1.8h, v5.16b, v15.16b",
3884 ));
3885
3886 insns.push((
3887 Inst::VecRRRLong {
3888 alu_op: VecRRRLongOp::Smull16,
3889 rd: writable_vreg(2),
3890 rn: vreg(13),
3891 rm: vreg(6),
3892 high_half: true,
3893 },
3894 "A2C1664E",
3895 "smull2 v2.4s, v13.8h, v6.8h",
3896 ));
3897
3898 insns.push((
3899 Inst::VecRRRLong {
3900 alu_op: VecRRRLongOp::Umull16,
3901 rd: writable_vreg(19),
3902 rn: vreg(18),
3903 rm: vreg(17),
3904 high_half: true,
3905 },
3906 "53C2716E",
3907 "umull2 v19.4s, v18.8h, v17.8h",
3908 ));
3909
3910 insns.push((
3911 Inst::VecRRRLong {
3912 alu_op: VecRRRLongOp::Umlal16,
3913 rd: writable_vreg(11),
3914 rn: vreg(10),
3915 rm: vreg(12),
3916 high_half: true,
3917 },
3918 "4B816C6E",
3919 "umlal2 v11.4s, v10.8h, v12.8h",
3920 ));
3921
3922 insns.push((
3923 Inst::VecRRRLong {
3924 alu_op: VecRRRLongOp::Smull32,
3925 rd: writable_vreg(8),
3926 rn: vreg(12),
3927 rm: vreg(14),
3928 high_half: true,
3929 },
3930 "88C1AE4E",
3931 "smull2 v8.2d, v12.4s, v14.4s",
3932 ));
3933
3934 insns.push((
3935 Inst::VecRRRLong {
3936 alu_op: VecRRRLongOp::Umull32,
3937 rd: writable_vreg(4),
3938 rn: vreg(12),
3939 rm: vreg(16),
3940 high_half: true,
3941 },
3942 "84C1B06E",
3943 "umull2 v4.2d, v12.4s, v16.4s",
3944 ));
3945
3946 insns.push((
3947 Inst::VecRRRLong {
3948 alu_op: VecRRRLongOp::Umlal32,
3949 rd: writable_vreg(10),
3950 rn: vreg(29),
3951 rm: vreg(2),
3952 high_half: true,
3953 },
3954 "AA83A26E",
3955 "umlal2 v10.2d, v29.4s, v2.4s",
3956 ));
3957
3958 insns.push((
3959 Inst::VecRRR {
3960 alu_op: VecALUOp::Sqrdmulh,
3961 rd: writable_vreg(31),
3962 rn: vreg(0),
3963 rm: vreg(31),
3964 size: VectorSize::Size16x8,
3965 },
3966 "1FB47F6E",
3967 "sqrdmulh v31.8h, v0.8h, v31.8h",
3968 ));
3969
3970 insns.push((
3971 Inst::VecRRR {
3972 alu_op: VecALUOp::Sqrdmulh,
3973 rd: writable_vreg(7),
3974 rn: vreg(7),
3975 rm: vreg(23),
3976 size: VectorSize::Size32x2,
3977 },
3978 "E7B4B72E",
3979 "sqrdmulh v7.2s, v7.2s, v23.2s",
3980 ));
3981
3982 insns.push((
3983 Inst::VecMisc {
3984 op: VecMisc2::Not,
3985 rd: writable_vreg(20),
3986 rn: vreg(17),
3987 size: VectorSize::Size8x8,
3988 },
3989 "345A202E",
3990 "mvn v20.8b, v17.8b",
3991 ));
3992
3993 insns.push((
3994 Inst::VecMisc {
3995 op: VecMisc2::Not,
3996 rd: writable_vreg(2),
3997 rn: vreg(1),
3998 size: VectorSize::Size32x4,
3999 },
4000 "2258206E",
4001 "mvn v2.16b, v1.16b",
4002 ));
4003
4004 insns.push((
4005 Inst::VecMisc {
4006 op: VecMisc2::Neg,
4007 rd: writable_vreg(3),
4008 rn: vreg(7),
4009 size: VectorSize::Size8x8,
4010 },
4011 "E3B8202E",
4012 "neg v3.8b, v7.8b",
4013 ));
4014
4015 insns.push((
4016 Inst::VecMisc {
4017 op: VecMisc2::Neg,
4018 rd: writable_vreg(8),
4019 rn: vreg(12),
4020 size: VectorSize::Size8x16,
4021 },
4022 "88B9206E",
4023 "neg v8.16b, v12.16b",
4024 ));
4025
4026 insns.push((
4027 Inst::VecMisc {
4028 op: VecMisc2::Neg,
4029 rd: writable_vreg(0),
4030 rn: vreg(31),
4031 size: VectorSize::Size16x8,
4032 },
4033 "E0BB606E",
4034 "neg v0.8h, v31.8h",
4035 ));
4036
4037 insns.push((
4038 Inst::VecMisc {
4039 op: VecMisc2::Neg,
4040 rd: writable_vreg(2),
4041 rn: vreg(3),
4042 size: VectorSize::Size32x4,
4043 },
4044 "62B8A06E",
4045 "neg v2.4s, v3.4s",
4046 ));
4047
4048 insns.push((
4049 Inst::VecMisc {
4050 op: VecMisc2::Neg,
4051 rd: writable_vreg(10),
4052 rn: vreg(8),
4053 size: VectorSize::Size64x2,
4054 },
4055 "0AB9E06E",
4056 "neg v10.2d, v8.2d",
4057 ));
4058
4059 insns.push((
4060 Inst::VecMisc {
4061 op: VecMisc2::Abs,
4062 rd: writable_vreg(3),
4063 rn: vreg(1),
4064 size: VectorSize::Size8x8,
4065 },
4066 "23B8200E",
4067 "abs v3.8b, v1.8b",
4068 ));
4069
4070 insns.push((
4071 Inst::VecMisc {
4072 op: VecMisc2::Abs,
4073 rd: writable_vreg(1),
4074 rn: vreg(1),
4075 size: VectorSize::Size8x16,
4076 },
4077 "21B8204E",
4078 "abs v1.16b, v1.16b",
4079 ));
4080
4081 insns.push((
4082 Inst::VecMisc {
4083 op: VecMisc2::Abs,
4084 rd: writable_vreg(29),
4085 rn: vreg(28),
4086 size: VectorSize::Size16x8,
4087 },
4088 "9DBB604E",
4089 "abs v29.8h, v28.8h",
4090 ));
4091
4092 insns.push((
4093 Inst::VecMisc {
4094 op: VecMisc2::Abs,
4095 rd: writable_vreg(7),
4096 rn: vreg(8),
4097 size: VectorSize::Size32x4,
4098 },
4099 "07B9A04E",
4100 "abs v7.4s, v8.4s",
4101 ));
4102
4103 insns.push((
4104 Inst::VecMisc {
4105 op: VecMisc2::Abs,
4106 rd: writable_vreg(1),
4107 rn: vreg(10),
4108 size: VectorSize::Size64x2,
4109 },
4110 "41B9E04E",
4111 "abs v1.2d, v10.2d",
4112 ));
4113
4114 insns.push((
4115 Inst::VecMisc {
4116 op: VecMisc2::Fabs,
4117 rd: writable_vreg(15),
4118 rn: vreg(16),
4119 size: VectorSize::Size32x4,
4120 },
4121 "0FFAA04E",
4122 "fabs v15.4s, v16.4s",
4123 ));
4124
4125 insns.push((
4126 Inst::VecMisc {
4127 op: VecMisc2::Fneg,
4128 rd: writable_vreg(31),
4129 rn: vreg(0),
4130 size: VectorSize::Size32x4,
4131 },
4132 "1FF8A06E",
4133 "fneg v31.4s, v0.4s",
4134 ));
4135
4136 insns.push((
4137 Inst::VecMisc {
4138 op: VecMisc2::Fsqrt,
4139 rd: writable_vreg(7),
4140 rn: vreg(18),
4141 size: VectorSize::Size64x2,
4142 },
4143 "47FAE16E",
4144 "fsqrt v7.2d, v18.2d",
4145 ));
4146
4147 insns.push((
4148 Inst::VecMisc {
4149 op: VecMisc2::Rev64,
4150 rd: writable_vreg(1),
4151 rn: vreg(10),
4152 size: VectorSize::Size32x4,
4153 },
4154 "4109A04E",
4155 "rev64 v1.4s, v10.4s",
4156 ));
4157
4158 insns.push((
4159 Inst::VecMisc {
4160 op: VecMisc2::Fcvtzs,
4161 rd: writable_vreg(4),
4162 rn: vreg(22),
4163 size: VectorSize::Size32x4,
4164 },
4165 "C4BAA14E",
4166 "fcvtzs v4.4s, v22.4s",
4167 ));
4168
4169 insns.push((
4170 Inst::VecMisc {
4171 op: VecMisc2::Fcvtzu,
4172 rd: writable_vreg(29),
4173 rn: vreg(15),
4174 size: VectorSize::Size64x2,
4175 },
4176 "FDB9E16E",
4177 "fcvtzu v29.2d, v15.2d",
4178 ));
4179
4180 insns.push((
4181 Inst::VecMisc {
4182 op: VecMisc2::Scvtf,
4183 rd: writable_vreg(20),
4184 rn: vreg(8),
4185 size: VectorSize::Size32x4,
4186 },
4187 "14D9214E",
4188 "scvtf v20.4s, v8.4s",
4189 ));
4190
4191 insns.push((
4192 Inst::VecMisc {
4193 op: VecMisc2::Ucvtf,
4194 rd: writable_vreg(10),
4195 rn: vreg(19),
4196 size: VectorSize::Size64x2,
4197 },
4198 "6ADA616E",
4199 "ucvtf v10.2d, v19.2d",
4200 ));
4201
4202 insns.push((
4203 Inst::VecMisc {
4204 op: VecMisc2::Frintn,
4205 rd: writable_vreg(11),
4206 rn: vreg(18),
4207 size: VectorSize::Size32x4,
4208 },
4209 "4B8A214E",
4210 "frintn v11.4s, v18.4s",
4211 ));
4212
4213 insns.push((
4214 Inst::VecMisc {
4215 op: VecMisc2::Frintn,
4216 rd: writable_vreg(12),
4217 rn: vreg(17),
4218 size: VectorSize::Size64x2,
4219 },
4220 "2C8A614E",
4221 "frintn v12.2d, v17.2d",
4222 ));
4223
4224 insns.push((
4225 Inst::VecMisc {
4226 op: VecMisc2::Frintz,
4227 rd: writable_vreg(11),
4228 rn: vreg(18),
4229 size: VectorSize::Size32x4,
4230 },
4231 "4B9AA14E",
4232 "frintz v11.4s, v18.4s",
4233 ));
4234
4235 insns.push((
4236 Inst::VecMisc {
4237 op: VecMisc2::Frintz,
4238 rd: writable_vreg(12),
4239 rn: vreg(17),
4240 size: VectorSize::Size64x2,
4241 },
4242 "2C9AE14E",
4243 "frintz v12.2d, v17.2d",
4244 ));
4245
4246 insns.push((
4247 Inst::VecMisc {
4248 op: VecMisc2::Frintm,
4249 rd: writable_vreg(11),
4250 rn: vreg(18),
4251 size: VectorSize::Size32x4,
4252 },
4253 "4B9A214E",
4254 "frintm v11.4s, v18.4s",
4255 ));
4256
4257 insns.push((
4258 Inst::VecMisc {
4259 op: VecMisc2::Frintm,
4260 rd: writable_vreg(12),
4261 rn: vreg(17),
4262 size: VectorSize::Size64x2,
4263 },
4264 "2C9A614E",
4265 "frintm v12.2d, v17.2d",
4266 ));
4267
4268 insns.push((
4269 Inst::VecMisc {
4270 op: VecMisc2::Frintp,
4271 rd: writable_vreg(11),
4272 rn: vreg(18),
4273 size: VectorSize::Size32x4,
4274 },
4275 "4B8AA14E",
4276 "frintp v11.4s, v18.4s",
4277 ));
4278
4279 insns.push((
4280 Inst::VecMisc {
4281 op: VecMisc2::Frintp,
4282 rd: writable_vreg(12),
4283 rn: vreg(17),
4284 size: VectorSize::Size64x2,
4285 },
4286 "2C8AE14E",
4287 "frintp v12.2d, v17.2d",
4288 ));
4289
4290 insns.push((
4291 Inst::VecMisc {
4292 op: VecMisc2::Cnt,
4293 rd: writable_vreg(23),
4294 rn: vreg(5),
4295 size: VectorSize::Size8x8,
4296 },
4297 "B758200E",
4298 "cnt v23.8b, v5.8b",
4299 ));
4300
4301 insns.push((
4302 Inst::VecMisc {
4303 op: VecMisc2::Cmeq0,
4304 rd: writable_vreg(12),
4305 rn: vreg(27),
4306 size: VectorSize::Size16x8,
4307 },
4308 "6C9B604E",
4309 "cmeq v12.8h, v27.8h, #0",
4310 ));
4311
4312 insns.push((
4313 Inst::VecLanes {
4314 op: VecLanesOp::Uminv,
4315 rd: writable_vreg(0),
4316 rn: vreg(31),
4317 size: VectorSize::Size8x8,
4318 },
4319 "E0AB312E",
4320 "uminv b0, v31.8b",
4321 ));
4322
4323 insns.push((
4324 Inst::VecLanes {
4325 op: VecLanesOp::Uminv,
4326 rd: writable_vreg(2),
4327 rn: vreg(1),
4328 size: VectorSize::Size8x16,
4329 },
4330 "22A8316E",
4331 "uminv b2, v1.16b",
4332 ));
4333
4334 insns.push((
4335 Inst::VecLanes {
4336 op: VecLanesOp::Uminv,
4337 rd: writable_vreg(3),
4338 rn: vreg(11),
4339 size: VectorSize::Size16x8,
4340 },
4341 "63A9716E",
4342 "uminv h3, v11.8h",
4343 ));
4344
4345 insns.push((
4346 Inst::VecLanes {
4347 op: VecLanesOp::Uminv,
4348 rd: writable_vreg(18),
4349 rn: vreg(4),
4350 size: VectorSize::Size32x4,
4351 },
4352 "92A8B16E",
4353 "uminv s18, v4.4s",
4354 ));
4355
4356 insns.push((
4357 Inst::VecLanes {
4358 op: VecLanesOp::Addv,
4359 rd: writable_vreg(2),
4360 rn: vreg(29),
4361 size: VectorSize::Size8x16,
4362 },
4363 "A2BB314E",
4364 "addv b2, v29.16b",
4365 ));
4366
4367 insns.push((
4368 Inst::VecLanes {
4369 op: VecLanesOp::Addv,
4370 rd: writable_vreg(15),
4371 rn: vreg(7),
4372 size: VectorSize::Size16x4,
4373 },
4374 "EFB8710E",
4375 "addv h15, v7.4h",
4376 ));
4377
4378 insns.push((
4379 Inst::VecLanes {
4380 op: VecLanesOp::Addv,
4381 rd: writable_vreg(3),
4382 rn: vreg(21),
4383 size: VectorSize::Size16x8,
4384 },
4385 "A3BA714E",
4386 "addv h3, v21.8h",
4387 ));
4388
4389 insns.push((
4390 Inst::VecLanes {
4391 op: VecLanesOp::Addv,
4392 rd: writable_vreg(18),
4393 rn: vreg(5),
4394 size: VectorSize::Size32x4,
4395 },
4396 "B2B8B14E",
4397 "addv s18, v5.4s",
4398 ));
4399
4400 insns.push((
4401 Inst::VecShiftImm {
4402 op: VecShiftImmOp::Shl,
4403 rd: writable_vreg(27),
4404 rn: vreg(5),
4405 imm: 7,
4406 size: VectorSize::Size8x16,
4407 },
4408 "BB540F4F",
4409 "shl v27.16b, v5.16b, #7",
4410 ));
4411
4412 insns.push((
4413 Inst::VecShiftImm {
4414 op: VecShiftImmOp::Shl,
4415 rd: writable_vreg(1),
4416 rn: vreg(30),
4417 imm: 0,
4418 size: VectorSize::Size8x16,
4419 },
4420 "C157084F",
4421 "shl v1.16b, v30.16b, #0",
4422 ));
4423
4424 insns.push((
4425 Inst::VecShiftImm {
4426 op: VecShiftImmOp::Sshr,
4427 rd: writable_vreg(26),
4428 rn: vreg(6),
4429 imm: 16,
4430 size: VectorSize::Size16x8,
4431 },
4432 "DA04104F",
4433 "sshr v26.8h, v6.8h, #16",
4434 ));
4435
4436 insns.push((
4437 Inst::VecShiftImm {
4438 op: VecShiftImmOp::Sshr,
4439 rd: writable_vreg(3),
4440 rn: vreg(19),
4441 imm: 1,
4442 size: VectorSize::Size16x8,
4443 },
4444 "63061F4F",
4445 "sshr v3.8h, v19.8h, #1",
4446 ));
4447
4448 insns.push((
4449 Inst::VecShiftImm {
4450 op: VecShiftImmOp::Ushr,
4451 rd: writable_vreg(25),
4452 rn: vreg(6),
4453 imm: 32,
4454 size: VectorSize::Size32x4,
4455 },
4456 "D904206F",
4457 "ushr v25.4s, v6.4s, #32",
4458 ));
4459
4460 insns.push((
4461 Inst::VecShiftImm {
4462 op: VecShiftImmOp::Ushr,
4463 rd: writable_vreg(5),
4464 rn: vreg(21),
4465 imm: 1,
4466 size: VectorSize::Size32x4,
4467 },
4468 "A5063F6F",
4469 "ushr v5.4s, v21.4s, #1",
4470 ));
4471
4472 insns.push((
4473 Inst::VecShiftImm {
4474 op: VecShiftImmOp::Shl,
4475 rd: writable_vreg(22),
4476 rn: vreg(13),
4477 imm: 63,
4478 size: VectorSize::Size64x2,
4479 },
4480 "B6557F4F",
4481 "shl v22.2d, v13.2d, #63",
4482 ));
4483
4484 insns.push((
4485 Inst::VecShiftImm {
4486 op: VecShiftImmOp::Shl,
4487 rd: writable_vreg(23),
4488 rn: vreg(9),
4489 imm: 0,
4490 size: VectorSize::Size64x2,
4491 },
4492 "3755404F",
4493 "shl v23.2d, v9.2d, #0",
4494 ));
4495
4496 insns.push((
4497 Inst::VecExtract {
4498 rd: writable_vreg(1),
4499 rn: vreg(30),
4500 rm: vreg(17),
4501 imm4: 0,
4502 },
4503 "C103116E",
4504 "ext v1.16b, v30.16b, v17.16b, #0",
4505 ));
4506
4507 insns.push((
4508 Inst::VecExtract {
4509 rd: writable_vreg(1),
4510 rn: vreg(30),
4511 rm: vreg(17),
4512 imm4: 8,
4513 },
4514 "C143116E",
4515 "ext v1.16b, v30.16b, v17.16b, #8",
4516 ));
4517
4518 insns.push((
4519 Inst::VecExtract {
4520 rd: writable_vreg(1),
4521 rn: vreg(30),
4522 rm: vreg(17),
4523 imm4: 15,
4524 },
4525 "C17B116E",
4526 "ext v1.16b, v30.16b, v17.16b, #15",
4527 ));
4528
4529 insns.push((
4530 Inst::VecTbl {
4531 rd: writable_vreg(0),
4532 rn: vreg(31),
4533 rm: vreg(16),
4534 is_extension: false,
4535 },
4536 "E003104E",
4537 "tbl v0.16b, { v31.16b }, v16.16b",
4538 ));
4539
4540 insns.push((
4541 Inst::VecTbl {
4542 rd: writable_vreg(4),
4543 rn: vreg(12),
4544 rm: vreg(23),
4545 is_extension: true,
4546 },
4547 "8411174E",
4548 "tbx v4.16b, { v12.16b }, v23.16b",
4549 ));
4550
4551 insns.push((
4552 Inst::VecTbl2 {
4553 rd: writable_vreg(16),
4554 rn: vreg(31),
4555 rn2: vreg(0),
4556 rm: vreg(26),
4557 is_extension: false,
4558 },
4559 "F0231A4E",
4560 "tbl v16.16b, { v31.16b, v0.16b }, v26.16b",
4561 ));
4562
4563 insns.push((
4564 Inst::VecTbl2 {
4565 rd: writable_vreg(3),
4566 rn: vreg(11),
4567 rn2: vreg(12),
4568 rm: vreg(19),
4569 is_extension: true,
4570 },
4571 "6331134E",
4572 "tbx v3.16b, { v11.16b, v12.16b }, v19.16b",
4573 ));
4574
4575 insns.push((
4576 Inst::VecLoadReplicate {
4577 rd: writable_vreg(31),
4578 rn: xreg(0),
4579
4580 size: VectorSize::Size64x2,
4581 },
4582 "1FCC404D",
4583 "ld1r { v31.2d }, [x0]",
4584 ));
4585
4586 insns.push((
4587 Inst::VecLoadReplicate {
4588 rd: writable_vreg(0),
4589 rn: xreg(25),
4590
4591 size: VectorSize::Size8x8,
4592 },
4593 "20C3400D",
4594 "ld1r { v0.8b }, [x25]",
4595 ));
4596
4597 insns.push((
4598 Inst::VecCSel {
4599 rd: writable_vreg(5),
4600 rn: vreg(10),
4601 rm: vreg(19),
4602 cond: Cond::Gt,
4603 },
4604 "6C000054651EB34E02000014451DAA4E",
4605 "vcsel v5.16b, v10.16b, v19.16b, gt (if-then-else diamond)",
4606 ));
4607
4608 insns.push((
4609 Inst::Extend {
4610 rd: writable_xreg(3),
4611 rn: xreg(5),
4612 signed: false,
4613 from_bits: 1,
4614 to_bits: 32,
4615 },
4616 "A3000012",
4617 "and w3, w5, #1",
4618 ));
4619 insns.push((
4620 Inst::Extend {
4621 rd: writable_xreg(3),
4622 rn: xreg(5),
4623 signed: false,
4624 from_bits: 1,
4625 to_bits: 64,
4626 },
4627 "A3000012",
4628 "and w3, w5, #1",
4629 ));
4630 insns.push((
4631 Inst::Extend {
4632 rd: writable_xreg(10),
4633 rn: xreg(21),
4634 signed: true,
4635 from_bits: 1,
4636 to_bits: 32,
4637 },
4638 "AA020013",
4639 "sbfx w10, w21, #0, #1",
4640 ));
4641 insns.push((
4642 Inst::Extend {
4643 rd: writable_xreg(1),
4644 rn: xreg(2),
4645 signed: true,
4646 from_bits: 1,
4647 to_bits: 64,
4648 },
4649 "41004093",
4650 "sbfx x1, x2, #0, #1",
4651 ));
4652 insns.push((
4653 Inst::Extend {
4654 rd: writable_xreg(1),
4655 rn: xreg(2),
4656 signed: false,
4657 from_bits: 8,
4658 to_bits: 32,
4659 },
4660 "411C0053",
4661 "uxtb w1, w2",
4662 ));
4663 insns.push((
4664 Inst::Extend {
4665 rd: writable_xreg(1),
4666 rn: xreg(2),
4667 signed: true,
4668 from_bits: 8,
4669 to_bits: 32,
4670 },
4671 "411C0013",
4672 "sxtb w1, w2",
4673 ));
4674 insns.push((
4675 Inst::Extend {
4676 rd: writable_xreg(1),
4677 rn: xreg(2),
4678 signed: false,
4679 from_bits: 16,
4680 to_bits: 32,
4681 },
4682 "413C0053",
4683 "uxth w1, w2",
4684 ));
4685 insns.push((
4686 Inst::Extend {
4687 rd: writable_xreg(1),
4688 rn: xreg(2),
4689 signed: true,
4690 from_bits: 16,
4691 to_bits: 32,
4692 },
4693 "413C0013",
4694 "sxth w1, w2",
4695 ));
4696 insns.push((
4697 Inst::Extend {
4698 rd: writable_xreg(1),
4699 rn: xreg(2),
4700 signed: false,
4701 from_bits: 8,
4702 to_bits: 64,
4703 },
4704 "411C0053",
4705 "uxtb w1, w2",
4706 ));
4707 insns.push((
4708 Inst::Extend {
4709 rd: writable_xreg(1),
4710 rn: xreg(2),
4711 signed: true,
4712 from_bits: 8,
4713 to_bits: 64,
4714 },
4715 "411C4093",
4716 "sxtb x1, w2",
4717 ));
4718 insns.push((
4719 Inst::Extend {
4720 rd: writable_xreg(1),
4721 rn: xreg(2),
4722 signed: false,
4723 from_bits: 16,
4724 to_bits: 64,
4725 },
4726 "413C0053",
4727 "uxth w1, w2",
4728 ));
4729 insns.push((
4730 Inst::Extend {
4731 rd: writable_xreg(1),
4732 rn: xreg(2),
4733 signed: true,
4734 from_bits: 16,
4735 to_bits: 64,
4736 },
4737 "413C4093",
4738 "sxth x1, w2",
4739 ));
4740 insns.push((
4741 Inst::Extend {
4742 rd: writable_xreg(1),
4743 rn: xreg(2),
4744 signed: false,
4745 from_bits: 32,
4746 to_bits: 64,
4747 },
4748 "E103022A",
4749 "mov w1, w2",
4750 ));
4751 insns.push((
4752 Inst::Extend {
4753 rd: writable_xreg(1),
4754 rn: xreg(2),
4755 signed: true,
4756 from_bits: 32,
4757 to_bits: 64,
4758 },
4759 "417C4093",
4760 "sxtw x1, w2",
4761 ));
4762
4763 insns.push((
4764 Inst::Jump {
4765 dest: BranchTarget::ResolvedOffset(64),
4766 },
4767 "10000014",
4768 "b 64",
4769 ));
4770
4771 insns.push((
4772 Inst::TrapIf {
4773 trap_code: TrapCode::Interrupt,
4774 kind: CondBrKind::NotZero(xreg(8)),
4775 },
4776 "480000B40000A0D4",
4777 "cbz x8, 8 ; udf",
4778 ));
4779 insns.push((
4780 Inst::TrapIf {
4781 trap_code: TrapCode::Interrupt,
4782 kind: CondBrKind::Zero(xreg(8)),
4783 },
4784 "480000B50000A0D4",
4785 "cbnz x8, 8 ; udf",
4786 ));
4787 insns.push((
4788 Inst::TrapIf {
4789 trap_code: TrapCode::Interrupt,
4790 kind: CondBrKind::Cond(Cond::Ne),
4791 },
4792 "400000540000A0D4",
4793 "b.eq 8 ; udf",
4794 ));
4795 insns.push((
4796 Inst::TrapIf {
4797 trap_code: TrapCode::Interrupt,
4798 kind: CondBrKind::Cond(Cond::Eq),
4799 },
4800 "410000540000A0D4",
4801 "b.ne 8 ; udf",
4802 ));
4803 insns.push((
4804 Inst::TrapIf {
4805 trap_code: TrapCode::Interrupt,
4806 kind: CondBrKind::Cond(Cond::Lo),
4807 },
4808 "420000540000A0D4",
4809 "b.hs 8 ; udf",
4810 ));
4811 insns.push((
4812 Inst::TrapIf {
4813 trap_code: TrapCode::Interrupt,
4814 kind: CondBrKind::Cond(Cond::Hs),
4815 },
4816 "430000540000A0D4",
4817 "b.lo 8 ; udf",
4818 ));
4819 insns.push((
4820 Inst::TrapIf {
4821 trap_code: TrapCode::Interrupt,
4822 kind: CondBrKind::Cond(Cond::Pl),
4823 },
4824 "440000540000A0D4",
4825 "b.mi 8 ; udf",
4826 ));
4827 insns.push((
4828 Inst::TrapIf {
4829 trap_code: TrapCode::Interrupt,
4830 kind: CondBrKind::Cond(Cond::Mi),
4831 },
4832 "450000540000A0D4",
4833 "b.pl 8 ; udf",
4834 ));
4835 insns.push((
4836 Inst::TrapIf {
4837 trap_code: TrapCode::Interrupt,
4838 kind: CondBrKind::Cond(Cond::Vc),
4839 },
4840 "460000540000A0D4",
4841 "b.vs 8 ; udf",
4842 ));
4843 insns.push((
4844 Inst::TrapIf {
4845 trap_code: TrapCode::Interrupt,
4846 kind: CondBrKind::Cond(Cond::Vs),
4847 },
4848 "470000540000A0D4",
4849 "b.vc 8 ; udf",
4850 ));
4851 insns.push((
4852 Inst::TrapIf {
4853 trap_code: TrapCode::Interrupt,
4854 kind: CondBrKind::Cond(Cond::Ls),
4855 },
4856 "480000540000A0D4",
4857 "b.hi 8 ; udf",
4858 ));
4859 insns.push((
4860 Inst::TrapIf {
4861 trap_code: TrapCode::Interrupt,
4862 kind: CondBrKind::Cond(Cond::Hi),
4863 },
4864 "490000540000A0D4",
4865 "b.ls 8 ; udf",
4866 ));
4867 insns.push((
4868 Inst::TrapIf {
4869 trap_code: TrapCode::Interrupt,
4870 kind: CondBrKind::Cond(Cond::Lt),
4871 },
4872 "4A0000540000A0D4",
4873 "b.ge 8 ; udf",
4874 ));
4875 insns.push((
4876 Inst::TrapIf {
4877 trap_code: TrapCode::Interrupt,
4878 kind: CondBrKind::Cond(Cond::Ge),
4879 },
4880 "4B0000540000A0D4",
4881 "b.lt 8 ; udf",
4882 ));
4883 insns.push((
4884 Inst::TrapIf {
4885 trap_code: TrapCode::Interrupt,
4886 kind: CondBrKind::Cond(Cond::Le),
4887 },
4888 "4C0000540000A0D4",
4889 "b.gt 8 ; udf",
4890 ));
4891 insns.push((
4892 Inst::TrapIf {
4893 trap_code: TrapCode::Interrupt,
4894 kind: CondBrKind::Cond(Cond::Gt),
4895 },
4896 "4D0000540000A0D4",
4897 "b.le 8 ; udf",
4898 ));
4899 insns.push((
4900 Inst::TrapIf {
4901 trap_code: TrapCode::Interrupt,
4902 kind: CondBrKind::Cond(Cond::Nv),
4903 },
4904 "4E0000540000A0D4",
4905 "b.al 8 ; udf",
4906 ));
4907 insns.push((
4908 Inst::TrapIf {
4909 trap_code: TrapCode::Interrupt,
4910 kind: CondBrKind::Cond(Cond::Al),
4911 },
4912 "4F0000540000A0D4",
4913 "b.nv 8 ; udf",
4914 ));
4915
4916 insns.push((
4917 Inst::CondBr {
4918 taken: BranchTarget::ResolvedOffset(64),
4919 not_taken: BranchTarget::ResolvedOffset(128),
4920 kind: CondBrKind::Cond(Cond::Le),
4921 },
4922 "0D02005420000014",
4923 "b.le 64 ; b 128",
4924 ));
4925
4926 insns.push((
4927 Inst::Call {
4928 info: Box::new(CallInfo {
4929 dest: ExternalName::testcase("test0"),
4930 uses: Vec::new(),
4931 defs: Vec::new(),
4932 opcode: Opcode::Call,
4933 caller_callconv: CallConv::SystemV,
4934 callee_callconv: CallConv::SystemV,
4935 }),
4936 },
4937 "00000094",
4938 "bl 0",
4939 ));
4940
4941 insns.push((
4942 Inst::CallInd {
4943 info: Box::new(CallIndInfo {
4944 rn: xreg(10),
4945 uses: Vec::new(),
4946 defs: Vec::new(),
4947 opcode: Opcode::CallIndirect,
4948 caller_callconv: CallConv::SystemV,
4949 callee_callconv: CallConv::SystemV,
4950 }),
4951 },
4952 "40013FD6",
4953 "blr x10",
4954 ));
4955
4956 insns.push((
4957 Inst::IndirectBr {
4958 rn: xreg(3),
4959 targets: vec![],
4960 },
4961 "60001FD6",
4962 "br x3",
4963 ));
4964
4965 insns.push((Inst::Brk, "000020D4", "brk #0"));
4966
4967 insns.push((
4968 Inst::Adr {
4969 rd: writable_xreg(15),
4970 off: (1 << 20) - 4,
4971 },
4972 "EFFF7F10",
4973 "adr x15, pc+1048572",
4974 ));
4975
4976 insns.push((
4977 Inst::FpuMove64 {
4978 rd: writable_vreg(8),
4979 rn: vreg(4),
4980 },
4981 "8840601E",
4982 "fmov d8, d4",
4983 ));
4984
4985 insns.push((
4986 Inst::FpuMove128 {
4987 rd: writable_vreg(17),
4988 rn: vreg(26),
4989 },
4990 "511FBA4E",
4991 "mov v17.16b, v26.16b",
4992 ));
4993
4994 insns.push((
4995 Inst::FpuMoveFromVec {
4996 rd: writable_vreg(1),
4997 rn: vreg(30),
4998 idx: 2,
4999 size: VectorSize::Size32x4,
5000 },
5001 "C107145E",
5002 "mov s1, v30.s[2]",
5003 ));
5004
5005 insns.push((
5006 Inst::FpuMoveFromVec {
5007 rd: writable_vreg(23),
5008 rn: vreg(11),
5009 idx: 0,
5010 size: VectorSize::Size64x2,
5011 },
5012 "7705085E",
5013 "mov d23, v11.d[0]",
5014 ));
5015
5016 insns.push((
5017 Inst::FpuExtend {
5018 rd: writable_vreg(31),
5019 rn: vreg(0),
5020 size: ScalarSize::Size32,
5021 },
5022 "1F40201E",
5023 "fmov s31, s0",
5024 ));
5025
5026 insns.push((
5027 Inst::FpuRR {
5028 fpu_op: FPUOp1::Abs32,
5029 rd: writable_vreg(15),
5030 rn: vreg(30),
5031 },
5032 "CFC3201E",
5033 "fabs s15, s30",
5034 ));
5035
5036 insns.push((
5037 Inst::FpuRR {
5038 fpu_op: FPUOp1::Abs64,
5039 rd: writable_vreg(15),
5040 rn: vreg(30),
5041 },
5042 "CFC3601E",
5043 "fabs d15, d30",
5044 ));
5045
5046 insns.push((
5047 Inst::FpuRR {
5048 fpu_op: FPUOp1::Neg32,
5049 rd: writable_vreg(15),
5050 rn: vreg(30),
5051 },
5052 "CF43211E",
5053 "fneg s15, s30",
5054 ));
5055
5056 insns.push((
5057 Inst::FpuRR {
5058 fpu_op: FPUOp1::Neg64,
5059 rd: writable_vreg(15),
5060 rn: vreg(30),
5061 },
5062 "CF43611E",
5063 "fneg d15, d30",
5064 ));
5065
5066 insns.push((
5067 Inst::FpuRR {
5068 fpu_op: FPUOp1::Sqrt32,
5069 rd: writable_vreg(15),
5070 rn: vreg(30),
5071 },
5072 "CFC3211E",
5073 "fsqrt s15, s30",
5074 ));
5075
5076 insns.push((
5077 Inst::FpuRR {
5078 fpu_op: FPUOp1::Sqrt64,
5079 rd: writable_vreg(15),
5080 rn: vreg(30),
5081 },
5082 "CFC3611E",
5083 "fsqrt d15, d30",
5084 ));
5085
5086 insns.push((
5087 Inst::FpuRR {
5088 fpu_op: FPUOp1::Cvt32To64,
5089 rd: writable_vreg(15),
5090 rn: vreg(30),
5091 },
5092 "CFC3221E",
5093 "fcvt d15, s30",
5094 ));
5095
5096 insns.push((
5097 Inst::FpuRR {
5098 fpu_op: FPUOp1::Cvt64To32,
5099 rd: writable_vreg(15),
5100 rn: vreg(30),
5101 },
5102 "CF43621E",
5103 "fcvt s15, d30",
5104 ));
5105
5106 insns.push((
5107 Inst::FpuRRR {
5108 fpu_op: FPUOp2::Add32,
5109 rd: writable_vreg(15),
5110 rn: vreg(30),
5111 rm: vreg(31),
5112 },
5113 "CF2B3F1E",
5114 "fadd s15, s30, s31",
5115 ));
5116
5117 insns.push((
5118 Inst::FpuRRR {
5119 fpu_op: FPUOp2::Add64,
5120 rd: writable_vreg(15),
5121 rn: vreg(30),
5122 rm: vreg(31),
5123 },
5124 "CF2B7F1E",
5125 "fadd d15, d30, d31",
5126 ));
5127
5128 insns.push((
5129 Inst::FpuRRR {
5130 fpu_op: FPUOp2::Sub32,
5131 rd: writable_vreg(15),
5132 rn: vreg(30),
5133 rm: vreg(31),
5134 },
5135 "CF3B3F1E",
5136 "fsub s15, s30, s31",
5137 ));
5138
5139 insns.push((
5140 Inst::FpuRRR {
5141 fpu_op: FPUOp2::Sub64,
5142 rd: writable_vreg(15),
5143 rn: vreg(30),
5144 rm: vreg(31),
5145 },
5146 "CF3B7F1E",
5147 "fsub d15, d30, d31",
5148 ));
5149
5150 insns.push((
5151 Inst::FpuRRR {
5152 fpu_op: FPUOp2::Mul32,
5153 rd: writable_vreg(15),
5154 rn: vreg(30),
5155 rm: vreg(31),
5156 },
5157 "CF0B3F1E",
5158 "fmul s15, s30, s31",
5159 ));
5160
5161 insns.push((
5162 Inst::FpuRRR {
5163 fpu_op: FPUOp2::Mul64,
5164 rd: writable_vreg(15),
5165 rn: vreg(30),
5166 rm: vreg(31),
5167 },
5168 "CF0B7F1E",
5169 "fmul d15, d30, d31",
5170 ));
5171
5172 insns.push((
5173 Inst::FpuRRR {
5174 fpu_op: FPUOp2::Div32,
5175 rd: writable_vreg(15),
5176 rn: vreg(30),
5177 rm: vreg(31),
5178 },
5179 "CF1B3F1E",
5180 "fdiv s15, s30, s31",
5181 ));
5182
5183 insns.push((
5184 Inst::FpuRRR {
5185 fpu_op: FPUOp2::Div64,
5186 rd: writable_vreg(15),
5187 rn: vreg(30),
5188 rm: vreg(31),
5189 },
5190 "CF1B7F1E",
5191 "fdiv d15, d30, d31",
5192 ));
5193
5194 insns.push((
5195 Inst::FpuRRR {
5196 fpu_op: FPUOp2::Max32,
5197 rd: writable_vreg(15),
5198 rn: vreg(30),
5199 rm: vreg(31),
5200 },
5201 "CF4B3F1E",
5202 "fmax s15, s30, s31",
5203 ));
5204
5205 insns.push((
5206 Inst::FpuRRR {
5207 fpu_op: FPUOp2::Max64,
5208 rd: writable_vreg(15),
5209 rn: vreg(30),
5210 rm: vreg(31),
5211 },
5212 "CF4B7F1E",
5213 "fmax d15, d30, d31",
5214 ));
5215
5216 insns.push((
5217 Inst::FpuRRR {
5218 fpu_op: FPUOp2::Min32,
5219 rd: writable_vreg(15),
5220 rn: vreg(30),
5221 rm: vreg(31),
5222 },
5223 "CF5B3F1E",
5224 "fmin s15, s30, s31",
5225 ));
5226
5227 insns.push((
5228 Inst::FpuRRR {
5229 fpu_op: FPUOp2::Min64,
5230 rd: writable_vreg(15),
5231 rn: vreg(30),
5232 rm: vreg(31),
5233 },
5234 "CF5B7F1E",
5235 "fmin d15, d30, d31",
5236 ));
5237
5238 insns.push((
5239 Inst::FpuRRR {
5240 fpu_op: FPUOp2::Uqadd64,
5241 rd: writable_vreg(21),
5242 rn: vreg(22),
5243 rm: vreg(23),
5244 },
5245 "D50EF77E",
5246 "uqadd d21, d22, d23",
5247 ));
5248
5249 insns.push((
5250 Inst::FpuRRR {
5251 fpu_op: FPUOp2::Sqadd64,
5252 rd: writable_vreg(21),
5253 rn: vreg(22),
5254 rm: vreg(23),
5255 },
5256 "D50EF75E",
5257 "sqadd d21, d22, d23",
5258 ));
5259
5260 insns.push((
5261 Inst::FpuRRR {
5262 fpu_op: FPUOp2::Uqsub64,
5263 rd: writable_vreg(21),
5264 rn: vreg(22),
5265 rm: vreg(23),
5266 },
5267 "D52EF77E",
5268 "uqsub d21, d22, d23",
5269 ));
5270
5271 insns.push((
5272 Inst::FpuRRR {
5273 fpu_op: FPUOp2::Sqsub64,
5274 rd: writable_vreg(21),
5275 rn: vreg(22),
5276 rm: vreg(23),
5277 },
5278 "D52EF75E",
5279 "sqsub d21, d22, d23",
5280 ));
5281
5282 insns.push((
5283 Inst::FpuRRRR {
5284 fpu_op: FPUOp3::MAdd32,
5285 rd: writable_vreg(15),
5286 rn: vreg(30),
5287 rm: vreg(31),
5288 ra: vreg(1),
5289 },
5290 "CF071F1F",
5291 "fmadd s15, s30, s31, s1",
5292 ));
5293
5294 insns.push((
5295 Inst::FpuRRRR {
5296 fpu_op: FPUOp3::MAdd64,
5297 rd: writable_vreg(15),
5298 rn: vreg(30),
5299 rm: vreg(31),
5300 ra: vreg(1),
5301 },
5302 "CF075F1F",
5303 "fmadd d15, d30, d31, d1",
5304 ));
5305
5306 insns.push((
5307 Inst::FpuRRI {
5308 fpu_op: FPUOpRI::UShr32(FPURightShiftImm::maybe_from_u8(32, 32).unwrap()),
5309 rd: writable_vreg(2),
5310 rn: vreg(5),
5311 },
5312 "A204202F",
5313 "ushr v2.2s, v5.2s, #32",
5314 ));
5315
5316 insns.push((
5317 Inst::FpuRRI {
5318 fpu_op: FPUOpRI::UShr64(FPURightShiftImm::maybe_from_u8(63, 64).unwrap()),
5319 rd: writable_vreg(2),
5320 rn: vreg(5),
5321 },
5322 "A204417F",
5323 "ushr d2, d5, #63",
5324 ));
5325
5326 insns.push((
5327 Inst::FpuRRI {
5328 fpu_op: FPUOpRI::Sli32(FPULeftShiftImm::maybe_from_u8(31, 32).unwrap()),
5329 rd: writable_vreg(4),
5330 rn: vreg(10),
5331 },
5332 "44553F2F",
5333 "sli v4.2s, v10.2s, #31",
5334 ));
5335
5336 insns.push((
5337 Inst::FpuRRI {
5338 fpu_op: FPUOpRI::Sli64(FPULeftShiftImm::maybe_from_u8(63, 64).unwrap()),
5339 rd: writable_vreg(4),
5340 rn: vreg(10),
5341 },
5342 "44557F7F",
5343 "sli d4, d10, #63",
5344 ));
5345
5346 insns.push((
5347 Inst::FpuToInt {
5348 op: FpuToIntOp::F32ToU32,
5349 rd: writable_xreg(1),
5350 rn: vreg(4),
5351 },
5352 "8100391E",
5353 "fcvtzu w1, s4",
5354 ));
5355
5356 insns.push((
5357 Inst::FpuToInt {
5358 op: FpuToIntOp::F32ToU64,
5359 rd: writable_xreg(1),
5360 rn: vreg(4),
5361 },
5362 "8100399E",
5363 "fcvtzu x1, s4",
5364 ));
5365
5366 insns.push((
5367 Inst::FpuToInt {
5368 op: FpuToIntOp::F32ToI32,
5369 rd: writable_xreg(1),
5370 rn: vreg(4),
5371 },
5372 "8100381E",
5373 "fcvtzs w1, s4",
5374 ));
5375
5376 insns.push((
5377 Inst::FpuToInt {
5378 op: FpuToIntOp::F32ToI64,
5379 rd: writable_xreg(1),
5380 rn: vreg(4),
5381 },
5382 "8100389E",
5383 "fcvtzs x1, s4",
5384 ));
5385
5386 insns.push((
5387 Inst::FpuToInt {
5388 op: FpuToIntOp::F64ToU32,
5389 rd: writable_xreg(1),
5390 rn: vreg(4),
5391 },
5392 "8100791E",
5393 "fcvtzu w1, d4",
5394 ));
5395
5396 insns.push((
5397 Inst::FpuToInt {
5398 op: FpuToIntOp::F64ToU64,
5399 rd: writable_xreg(1),
5400 rn: vreg(4),
5401 },
5402 "8100799E",
5403 "fcvtzu x1, d4",
5404 ));
5405
5406 insns.push((
5407 Inst::FpuToInt {
5408 op: FpuToIntOp::F64ToI32,
5409 rd: writable_xreg(1),
5410 rn: vreg(4),
5411 },
5412 "8100781E",
5413 "fcvtzs w1, d4",
5414 ));
5415
5416 insns.push((
5417 Inst::FpuToInt {
5418 op: FpuToIntOp::F64ToI64,
5419 rd: writable_xreg(1),
5420 rn: vreg(4),
5421 },
5422 "8100789E",
5423 "fcvtzs x1, d4",
5424 ));
5425
5426 insns.push((
5427 Inst::IntToFpu {
5428 op: IntToFpuOp::U32ToF32,
5429 rd: writable_vreg(1),
5430 rn: xreg(4),
5431 },
5432 "8100231E",
5433 "ucvtf s1, w4",
5434 ));
5435
5436 insns.push((
5437 Inst::IntToFpu {
5438 op: IntToFpuOp::I32ToF32,
5439 rd: writable_vreg(1),
5440 rn: xreg(4),
5441 },
5442 "8100221E",
5443 "scvtf s1, w4",
5444 ));
5445
5446 insns.push((
5447 Inst::IntToFpu {
5448 op: IntToFpuOp::U32ToF64,
5449 rd: writable_vreg(1),
5450 rn: xreg(4),
5451 },
5452 "8100631E",
5453 "ucvtf d1, w4",
5454 ));
5455
5456 insns.push((
5457 Inst::IntToFpu {
5458 op: IntToFpuOp::I32ToF64,
5459 rd: writable_vreg(1),
5460 rn: xreg(4),
5461 },
5462 "8100621E",
5463 "scvtf d1, w4",
5464 ));
5465
5466 insns.push((
5467 Inst::IntToFpu {
5468 op: IntToFpuOp::U64ToF32,
5469 rd: writable_vreg(1),
5470 rn: xreg(4),
5471 },
5472 "8100239E",
5473 "ucvtf s1, x4",
5474 ));
5475
5476 insns.push((
5477 Inst::IntToFpu {
5478 op: IntToFpuOp::I64ToF32,
5479 rd: writable_vreg(1),
5480 rn: xreg(4),
5481 },
5482 "8100229E",
5483 "scvtf s1, x4",
5484 ));
5485
5486 insns.push((
5487 Inst::IntToFpu {
5488 op: IntToFpuOp::U64ToF64,
5489 rd: writable_vreg(1),
5490 rn: xreg(4),
5491 },
5492 "8100639E",
5493 "ucvtf d1, x4",
5494 ));
5495
5496 insns.push((
5497 Inst::IntToFpu {
5498 op: IntToFpuOp::I64ToF64,
5499 rd: writable_vreg(1),
5500 rn: xreg(4),
5501 },
5502 "8100629E",
5503 "scvtf d1, x4",
5504 ));
5505
5506 insns.push((
5507 Inst::FpuCmp32 {
5508 rn: vreg(23),
5509 rm: vreg(24),
5510 },
5511 "E022381E",
5512 "fcmp s23, s24",
5513 ));
5514
5515 insns.push((
5516 Inst::FpuCmp64 {
5517 rn: vreg(23),
5518 rm: vreg(24),
5519 },
5520 "E022781E",
5521 "fcmp d23, d24",
5522 ));
5523
5524 insns.push((
5525 Inst::FpuLoad32 {
5526 rd: writable_vreg(16),
5527 mem: AMode::RegScaled(xreg(8), xreg(9), F32),
5528 flags: MemFlags::trusted(),
5529 },
5530 "107969BC",
5531 "ldr s16, [x8, x9, LSL #2]",
5532 ));
5533
5534 insns.push((
5535 Inst::FpuLoad64 {
5536 rd: writable_vreg(16),
5537 mem: AMode::RegScaled(xreg(8), xreg(9), F64),
5538 flags: MemFlags::trusted(),
5539 },
5540 "107969FC",
5541 "ldr d16, [x8, x9, LSL #3]",
5542 ));
5543
5544 insns.push((
5545 Inst::FpuLoad128 {
5546 rd: writable_vreg(16),
5547 mem: AMode::RegScaled(xreg(8), xreg(9), I128),
5548 flags: MemFlags::trusted(),
5549 },
5550 "1079E93C",
5551 "ldr q16, [x8, x9, LSL #4]",
5552 ));
5553
5554 insns.push((
5555 Inst::FpuLoad32 {
5556 rd: writable_vreg(16),
5557 mem: AMode::Label(MemLabel::PCRel(8)),
5558 flags: MemFlags::trusted(),
5559 },
5560 "5000001C",
5561 "ldr s16, pc+8",
5562 ));
5563
5564 insns.push((
5565 Inst::FpuLoad64 {
5566 rd: writable_vreg(16),
5567 mem: AMode::Label(MemLabel::PCRel(8)),
5568 flags: MemFlags::trusted(),
5569 },
5570 "5000005C",
5571 "ldr d16, pc+8",
5572 ));
5573
5574 insns.push((
5575 Inst::FpuLoad128 {
5576 rd: writable_vreg(16),
5577 mem: AMode::Label(MemLabel::PCRel(8)),
5578 flags: MemFlags::trusted(),
5579 },
5580 "5000009C",
5581 "ldr q16, pc+8",
5582 ));
5583
5584 insns.push((
5585 Inst::FpuStore32 {
5586 rd: vreg(16),
5587 mem: AMode::RegScaled(xreg(8), xreg(9), F32),
5588 flags: MemFlags::trusted(),
5589 },
5590 "107929BC",
5591 "str s16, [x8, x9, LSL #2]",
5592 ));
5593
5594 insns.push((
5595 Inst::FpuStore64 {
5596 rd: vreg(16),
5597 mem: AMode::RegScaled(xreg(8), xreg(9), F64),
5598 flags: MemFlags::trusted(),
5599 },
5600 "107929FC",
5601 "str d16, [x8, x9, LSL #3]",
5602 ));
5603
5604 insns.push((
5605 Inst::FpuStore128 {
5606 rd: vreg(16),
5607 mem: AMode::RegScaled(xreg(8), xreg(9), I128),
5608 flags: MemFlags::trusted(),
5609 },
5610 "1079A93C",
5611 "str q16, [x8, x9, LSL #4]",
5612 ));
5613
5614 insns.push((
5615 Inst::FpuLoadP64 {
5616 rt: writable_vreg(0),
5617 rt2: writable_vreg(31),
5618 mem: PairAMode::SignedOffset(xreg(0), SImm7Scaled::zero(F64)),
5619 flags: MemFlags::trusted(),
5620 },
5621 "007C406D",
5622 "ldp d0, d31, [x0]",
5623 ));
5624
5625 insns.push((
5626 Inst::FpuLoadP64 {
5627 rt: writable_vreg(19),
5628 rt2: writable_vreg(11),
5629 mem: PairAMode::PreIndexed(
5630 writable_xreg(25),
5631 SImm7Scaled::maybe_from_i64(-512, F64).unwrap(),
5632 ),
5633 flags: MemFlags::trusted(),
5634 },
5635 "332FE06D",
5636 "ldp d19, d11, [x25, #-512]!",
5637 ));
5638
5639 insns.push((
5640 Inst::FpuLoadP64 {
5641 rt: writable_vreg(7),
5642 rt2: writable_vreg(20),
5643 mem: PairAMode::PostIndexed(
5644 writable_stack_reg(),
5645 SImm7Scaled::maybe_from_i64(64, F64).unwrap(),
5646 ),
5647 flags: MemFlags::trusted(),
5648 },
5649 "E753C46C",
5650 "ldp d7, d20, [sp], #64",
5651 ));
5652
5653 insns.push((
5654 Inst::FpuStoreP64 {
5655 rt: vreg(4),
5656 rt2: vreg(26),
5657 mem: PairAMode::SignedOffset(
5658 stack_reg(),
5659 SImm7Scaled::maybe_from_i64(504, F64).unwrap(),
5660 ),
5661 flags: MemFlags::trusted(),
5662 },
5663 "E4EB1F6D",
5664 "stp d4, d26, [sp, #504]",
5665 ));
5666
5667 insns.push((
5668 Inst::FpuStoreP64 {
5669 rt: vreg(16),
5670 rt2: vreg(8),
5671 mem: PairAMode::PreIndexed(
5672 writable_xreg(15),
5673 SImm7Scaled::maybe_from_i64(48, F64).unwrap(),
5674 ),
5675 flags: MemFlags::trusted(),
5676 },
5677 "F021836D",
5678 "stp d16, d8, [x15, #48]!",
5679 ));
5680
5681 insns.push((
5682 Inst::FpuStoreP64 {
5683 rt: vreg(5),
5684 rt2: vreg(6),
5685 mem: PairAMode::PostIndexed(
5686 writable_xreg(28),
5687 SImm7Scaled::maybe_from_i64(-32, F64).unwrap(),
5688 ),
5689 flags: MemFlags::trusted(),
5690 },
5691 "851BBE6C",
5692 "stp d5, d6, [x28], #-32",
5693 ));
5694
5695 insns.push((
5696 Inst::FpuLoadP128 {
5697 rt: writable_vreg(0),
5698 rt2: writable_vreg(17),
5699 mem: PairAMode::SignedOffset(xreg(3), SImm7Scaled::zero(I8X16)),
5700 flags: MemFlags::trusted(),
5701 },
5702 "604440AD",
5703 "ldp q0, q17, [x3]",
5704 ));
5705
5706 insns.push((
5707 Inst::FpuLoadP128 {
5708 rt: writable_vreg(29),
5709 rt2: writable_vreg(9),
5710 mem: PairAMode::PreIndexed(
5711 writable_xreg(16),
5712 SImm7Scaled::maybe_from_i64(-1024, I8X16).unwrap(),
5713 ),
5714 flags: MemFlags::trusted(),
5715 },
5716 "1D26E0AD",
5717 "ldp q29, q9, [x16, #-1024]!",
5718 ));
5719
5720 insns.push((
5721 Inst::FpuLoadP128 {
5722 rt: writable_vreg(10),
5723 rt2: writable_vreg(20),
5724 mem: PairAMode::PostIndexed(
5725 writable_xreg(26),
5726 SImm7Scaled::maybe_from_i64(256, I8X16).unwrap(),
5727 ),
5728 flags: MemFlags::trusted(),
5729 },
5730 "4A53C8AC",
5731 "ldp q10, q20, [x26], #256",
5732 ));
5733
5734 insns.push((
5735 Inst::FpuStoreP128 {
5736 rt: vreg(9),
5737 rt2: vreg(31),
5738 mem: PairAMode::SignedOffset(
5739 stack_reg(),
5740 SImm7Scaled::maybe_from_i64(1008, I8X16).unwrap(),
5741 ),
5742 flags: MemFlags::trusted(),
5743 },
5744 "E9FF1FAD",
5745 "stp q9, q31, [sp, #1008]",
5746 ));
5747
5748 insns.push((
5749 Inst::FpuStoreP128 {
5750 rt: vreg(27),
5751 rt2: vreg(13),
5752 mem: PairAMode::PreIndexed(
5753 writable_stack_reg(),
5754 SImm7Scaled::maybe_from_i64(-192, I8X16).unwrap(),
5755 ),
5756 flags: MemFlags::trusted(),
5757 },
5758 "FB37BAAD",
5759 "stp q27, q13, [sp, #-192]!",
5760 ));
5761
5762 insns.push((
5763 Inst::FpuStoreP128 {
5764 rt: vreg(18),
5765 rt2: vreg(22),
5766 mem: PairAMode::PostIndexed(
5767 writable_xreg(13),
5768 SImm7Scaled::maybe_from_i64(304, I8X16).unwrap(),
5769 ),
5770 flags: MemFlags::trusted(),
5771 },
5772 "B2D989AC",
5773 "stp q18, q22, [x13], #304",
5774 ));
5775
5776 insns.push((
5777 Inst::LoadFpuConst64 {
5778 rd: writable_vreg(16),
5779 const_data: 1.0_f64.to_bits(),
5780 },
5781 "5000005C03000014000000000000F03F",
5782 "ldr d16, pc+8 ; b 12 ; data.f64 1",
5783 ));
5784
5785 insns.push((
5786 Inst::LoadFpuConst128 {
5787 rd: writable_vreg(5),
5788 const_data: 0x0f0e0d0c0b0a09080706050403020100,
5789 },
5790 "4500009C05000014000102030405060708090A0B0C0D0E0F",
5791 "ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100",
5792 ));
5793
5794 insns.push((
5795 Inst::FpuCSel32 {
5796 rd: writable_vreg(1),
5797 rn: vreg(2),
5798 rm: vreg(3),
5799 cond: Cond::Hi,
5800 },
5801 "418C231E",
5802 "fcsel s1, s2, s3, hi",
5803 ));
5804
5805 insns.push((
5806 Inst::FpuCSel64 {
5807 rd: writable_vreg(1),
5808 rn: vreg(2),
5809 rm: vreg(3),
5810 cond: Cond::Eq,
5811 },
5812 "410C631E",
5813 "fcsel d1, d2, d3, eq",
5814 ));
5815
5816 insns.push((
5817 Inst::FpuRound {
5818 rd: writable_vreg(23),
5819 rn: vreg(24),
5820 op: FpuRoundMode::Minus32,
5821 },
5822 "1743251E",
5823 "frintm s23, s24",
5824 ));
5825 insns.push((
5826 Inst::FpuRound {
5827 rd: writable_vreg(23),
5828 rn: vreg(24),
5829 op: FpuRoundMode::Minus64,
5830 },
5831 "1743651E",
5832 "frintm d23, d24",
5833 ));
5834 insns.push((
5835 Inst::FpuRound {
5836 rd: writable_vreg(23),
5837 rn: vreg(24),
5838 op: FpuRoundMode::Plus32,
5839 },
5840 "17C3241E",
5841 "frintp s23, s24",
5842 ));
5843 insns.push((
5844 Inst::FpuRound {
5845 rd: writable_vreg(23),
5846 rn: vreg(24),
5847 op: FpuRoundMode::Plus64,
5848 },
5849 "17C3641E",
5850 "frintp d23, d24",
5851 ));
5852 insns.push((
5853 Inst::FpuRound {
5854 rd: writable_vreg(23),
5855 rn: vreg(24),
5856 op: FpuRoundMode::Zero32,
5857 },
5858 "17C3251E",
5859 "frintz s23, s24",
5860 ));
5861 insns.push((
5862 Inst::FpuRound {
5863 rd: writable_vreg(23),
5864 rn: vreg(24),
5865 op: FpuRoundMode::Zero64,
5866 },
5867 "17C3651E",
5868 "frintz d23, d24",
5869 ));
5870 insns.push((
5871 Inst::FpuRound {
5872 rd: writable_vreg(23),
5873 rn: vreg(24),
5874 op: FpuRoundMode::Nearest32,
5875 },
5876 "1743241E",
5877 "frintn s23, s24",
5878 ));
5879 insns.push((
5880 Inst::FpuRound {
5881 rd: writable_vreg(23),
5882 rn: vreg(24),
5883 op: FpuRoundMode::Nearest64,
5884 },
5885 "1743641E",
5886 "frintn d23, d24",
5887 ));
5888
5889 insns.push((
5890 Inst::AtomicRMW {
5891 ty: I16,
5892 op: inst_common::AtomicRmwOp::Xor,
5893 },
5894 "3BFF5F487C031ACA3CFF1848B8FFFFB5",
5895 "atomically { 16_bits_at_[x25]) Xor= x26 ; x27 = old_value_at_[x25]; x24,x28 = trash }",
5896 ));
5897
5898 insns.push((
5899 Inst::AtomicRMW {
5900 ty: I32,
5901 op: inst_common::AtomicRmwOp::Xchg,
5902 },
5903 "3BFF5F88FC031AAA3CFF1888B8FFFFB5",
5904 "atomically { 32_bits_at_[x25]) Xchg= x26 ; x27 = old_value_at_[x25]; x24,x28 = trash }",
5905 ));
5906 insns.push((
5907 Inst::AtomicCAS {
5908 rs: writable_xreg(28),
5909 rt: xreg(20),
5910 rn: xreg(10),
5911 ty: I8,
5912 },
5913 "54FDFC08",
5914 "casalb w28, w20, [x10]",
5915 ));
5916 insns.push((
5917 Inst::AtomicCAS {
5918 rs: writable_xreg(2),
5919 rt: xreg(19),
5920 rn: xreg(23),
5921 ty: I16,
5922 },
5923 "F3FEE248",
5924 "casalh w2, w19, [x23]",
5925 ));
5926 insns.push((
5927 Inst::AtomicCAS {
5928 rs: writable_xreg(0),
5929 rt: zero_reg(),
5930 rn: stack_reg(),
5931 ty: I32,
5932 },
5933 "FFFFE088",
5934 "casal w0, wzr, [sp]",
5935 ));
5936 insns.push((
5937 Inst::AtomicCAS {
5938 rs: writable_xreg(7),
5939 rt: xreg(15),
5940 rn: xreg(27),
5941 ty: I64,
5942 },
5943 "6FFFE7C8",
5944 "casal x7, x15, [x27]",
5945 ));
5946 insns.push((
5947 Inst::AtomicCASLoop {
5948 ty: I8,
5949 },
5950 "3BFF5F087F033AEB610000543CFF180898FFFFB5",
5951 "atomically { compare-and-swap(8_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }"
5952 ));
5953
5954 insns.push((
5955 Inst::AtomicCASLoop {
5956 ty: I16,
5957 },
5958 "3BFF5F487F233AEB610000543CFF184898FFFFB5",
5959 "atomically { compare-and-swap(16_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }"
5960 ));
5961
5962 insns.push((
5963 Inst::AtomicCASLoop {
5964 ty: I32,
5965 },
5966 "3BFF5F887F031AEB610000543CFF188898FFFFB5",
5967 "atomically { compare-and-swap(32_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }"
5968 ));
5969
5970 insns.push((
5971 Inst::AtomicCASLoop {
5972 ty: I64,
5973 },
5974 "3BFF5FC87F031AEB610000543CFF18C898FFFFB5",
5975 "atomically { compare-and-swap(64_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }"
5976 ));
5977
5978 insns.push((
5979 Inst::LoadAcquire {
5980 access_ty: I8,
5981 rt: writable_xreg(7),
5982 rn: xreg(28),
5983 },
5984 "87FFDF08",
5985 "ldarb w7, [x28]",
5986 ));
5987
5988 insns.push((
5989 Inst::LoadAcquire {
5990 access_ty: I16,
5991 rt: writable_xreg(2),
5992 rn: xreg(3),
5993 },
5994 "62FCDF48",
5995 "ldarh w2, [x3]",
5996 ));
5997
5998 insns.push((
5999 Inst::LoadAcquire {
6000 access_ty: I32,
6001 rt: writable_xreg(15),
6002 rn: xreg(0),
6003 },
6004 "0FFCDF88",
6005 "ldar w15, [x0]",
6006 ));
6007
6008 insns.push((
6009 Inst::LoadAcquire {
6010 access_ty: I64,
6011 rt: writable_xreg(28),
6012 rn: xreg(7),
6013 },
6014 "FCFCDFC8",
6015 "ldar x28, [x7]",
6016 ));
6017
6018 insns.push((
6019 Inst::StoreRelease {
6020 access_ty: I8,
6021 rt: xreg(7),
6022 rn: xreg(28),
6023 },
6024 "87FF9F08",
6025 "stlrb w7, [x28]",
6026 ));
6027
6028 insns.push((
6029 Inst::StoreRelease {
6030 access_ty: I16,
6031 rt: xreg(2),
6032 rn: xreg(3),
6033 },
6034 "62FC9F48",
6035 "stlrh w2, [x3]",
6036 ));
6037
6038 insns.push((
6039 Inst::StoreRelease {
6040 access_ty: I32,
6041 rt: xreg(15),
6042 rn: xreg(0),
6043 },
6044 "0FFC9F88",
6045 "stlr w15, [x0]",
6046 ));
6047
6048 insns.push((
6049 Inst::StoreRelease {
6050 access_ty: I64,
6051 rt: xreg(28),
6052 rn: xreg(7),
6053 },
6054 "FCFC9FC8",
6055 "stlr x28, [x7]",
6056 ));
6057
6058 insns.push((Inst::Fence {}, "BF3B03D5", "dmb ish"));
6059
6060 let flags = settings::Flags::new(settings::builder());
6061 let rru = create_reg_universe(&flags);
6062 let emit_info = EmitInfo::new(flags);
6063 for (insn, expected_encoding, expected_printing) in insns {
6064 println!(
6065 "AArch64: {:?}, {}, {}",
6066 insn, expected_encoding, expected_printing
6067 );
6068
6069 // Check the printed text is as expected.
6070 let actual_printing = insn.show_rru(Some(&rru));
6071 assert_eq!(expected_printing, actual_printing);
6072
6073 let mut sink = test_utils::TestCodeSink::new();
6074 let mut buffer = MachBuffer::new();
6075 insn.emit(&mut buffer, &emit_info, &mut Default::default());
6076 let buffer = buffer.finish();
6077 buffer.emit(&mut sink);
6078 let actual_encoding = &sink.stringify();
6079 assert_eq!(expected_encoding, actual_encoding);
6080 }
6081 }
6082
6083 #[test]
test_cond_invert()6084 fn test_cond_invert() {
6085 for cond in vec![
6086 Cond::Eq,
6087 Cond::Ne,
6088 Cond::Hs,
6089 Cond::Lo,
6090 Cond::Mi,
6091 Cond::Pl,
6092 Cond::Vs,
6093 Cond::Vc,
6094 Cond::Hi,
6095 Cond::Ls,
6096 Cond::Ge,
6097 Cond::Lt,
6098 Cond::Gt,
6099 Cond::Le,
6100 Cond::Al,
6101 Cond::Nv,
6102 ]
6103 .into_iter()
6104 {
6105 assert_eq!(cond.invert().invert(), cond);
6106 }
6107 }
6108