1 /* 2 * This definitions of the PIC10F320 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:22:54 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic10f320.h> 26 27 //============================================================================== 28 29 __at(0x0000) __sfr INDF; 30 31 __at(0x0001) __sfr TMR0; 32 33 __at(0x0002) __sfr PCL; 34 35 __at(0x0003) __sfr STATUS; 36 __at(0x0003) volatile __STATUSbits_t STATUSbits; 37 38 __at(0x0004) __sfr FSR; 39 40 __at(0x0005) __sfr PORTA; 41 __at(0x0005) volatile __PORTAbits_t PORTAbits; 42 43 __at(0x0006) __sfr TRISA; 44 __at(0x0006) volatile __TRISAbits_t TRISAbits; 45 46 __at(0x0007) __sfr LATA; 47 __at(0x0007) volatile __LATAbits_t LATAbits; 48 49 __at(0x0008) __sfr ANSELA; 50 __at(0x0008) volatile __ANSELAbits_t ANSELAbits; 51 52 __at(0x0009) __sfr WPUA; 53 __at(0x0009) volatile __WPUAbits_t WPUAbits; 54 55 __at(0x000A) __sfr PCLATH; 56 __at(0x000A) volatile __PCLATHbits_t PCLATHbits; 57 58 __at(0x000B) __sfr INTCON; 59 __at(0x000B) volatile __INTCONbits_t INTCONbits; 60 61 __at(0x000C) __sfr PIR1; 62 __at(0x000C) volatile __PIR1bits_t PIR1bits; 63 64 __at(0x000D) __sfr PIE1; 65 __at(0x000D) volatile __PIE1bits_t PIE1bits; 66 67 __at(0x000E) __sfr OPTION_REG; 68 __at(0x000E) volatile __OPTION_REGbits_t OPTION_REGbits; 69 70 __at(0x000F) __sfr PCON; 71 __at(0x000F) volatile __PCONbits_t PCONbits; 72 73 __at(0x0010) __sfr OSCCON; 74 __at(0x0010) volatile __OSCCONbits_t OSCCONbits; 75 76 __at(0x0011) __sfr TMR2; 77 78 __at(0x0012) __sfr PR2; 79 80 __at(0x0013) __sfr T2CON; 81 __at(0x0013) volatile __T2CONbits_t T2CONbits; 82 83 __at(0x0014) __sfr PWM1DCL; 84 __at(0x0014) volatile __PWM1DCLbits_t PWM1DCLbits; 85 86 __at(0x0015) __sfr PWM1DCH; 87 __at(0x0015) volatile __PWM1DCHbits_t PWM1DCHbits; 88 89 __at(0x0016) __sfr PWM1CON; 90 __at(0x0016) volatile __PWM1CONbits_t PWM1CONbits; 91 92 __at(0x0016) __sfr PWM1CON0; 93 __at(0x0016) volatile __PWM1CON0bits_t PWM1CON0bits; 94 95 __at(0x0017) __sfr PWM2DCL; 96 __at(0x0017) volatile __PWM2DCLbits_t PWM2DCLbits; 97 98 __at(0x0018) __sfr PWM2DCH; 99 __at(0x0018) volatile __PWM2DCHbits_t PWM2DCHbits; 100 101 __at(0x0019) __sfr PWM2CON; 102 __at(0x0019) volatile __PWM2CONbits_t PWM2CONbits; 103 104 __at(0x0019) __sfr PWM2CON0; 105 __at(0x0019) volatile __PWM2CON0bits_t PWM2CON0bits; 106 107 __at(0x001A) __sfr IOCAP; 108 __at(0x001A) volatile __IOCAPbits_t IOCAPbits; 109 110 __at(0x001B) __sfr IOCAN; 111 __at(0x001B) volatile __IOCANbits_t IOCANbits; 112 113 __at(0x001C) __sfr IOCAF; 114 __at(0x001C) volatile __IOCAFbits_t IOCAFbits; 115 116 __at(0x001D) __sfr FVRCON; 117 __at(0x001D) volatile __FVRCONbits_t FVRCONbits; 118 119 __at(0x001E) __sfr ADRES; 120 121 __at(0x001F) __sfr ADCON; 122 __at(0x001F) volatile __ADCONbits_t ADCONbits; 123 124 __at(0x0020) __sfr PMADR; 125 126 __at(0x0020) __sfr PMADRL; 127 128 __at(0x0021) __sfr PMADRH; 129 __at(0x0021) volatile __PMADRHbits_t PMADRHbits; 130 131 __at(0x0022) __sfr PMDAT; 132 133 __at(0x0022) __sfr PMDATL; 134 135 __at(0x0023) __sfr PMDATH; 136 137 __at(0x0024) __sfr PMCON1; 138 __at(0x0024) volatile __PMCON1bits_t PMCON1bits; 139 140 __at(0x0025) __sfr PMCON2; 141 142 __at(0x0026) __sfr CLKRCON; 143 __at(0x0026) volatile __CLKRCONbits_t CLKRCONbits; 144 145 __at(0x0027) __sfr NCO1ACC; 146 147 __at(0x0027) __sfr NCO1ACCL; 148 __at(0x0027) volatile __NCO1ACCLbits_t NCO1ACCLbits; 149 150 __at(0x0028) __sfr NCO1ACCH; 151 __at(0x0028) volatile __NCO1ACCHbits_t NCO1ACCHbits; 152 153 __at(0x0029) __sfr NCO1ACCU; 154 __at(0x0029) volatile __NCO1ACCUbits_t NCO1ACCUbits; 155 156 __at(0x002A) __sfr NCO1INC; 157 158 __at(0x002A) __sfr NCO1INCL; 159 __at(0x002A) volatile __NCO1INCLbits_t NCO1INCLbits; 160 161 __at(0x002B) __sfr NCO1INCH; 162 __at(0x002B) volatile __NCO1INCHbits_t NCO1INCHbits; 163 164 __at(0x002C) __sfr NCO1INCU; 165 166 __at(0x002D) __sfr NCO1CON; 167 __at(0x002D) volatile __NCO1CONbits_t NCO1CONbits; 168 169 __at(0x002E) __sfr NCO1CLK; 170 __at(0x002E) volatile __NCO1CLKbits_t NCO1CLKbits; 171 172 __at(0x0030) __sfr WDTCON; 173 __at(0x0030) volatile __WDTCONbits_t WDTCONbits; 174 175 __at(0x0031) __sfr CLC1CON; 176 __at(0x0031) volatile __CLC1CONbits_t CLC1CONbits; 177 178 __at(0x0032) __sfr CLC1SEL0; 179 __at(0x0032) volatile __CLC1SEL0bits_t CLC1SEL0bits; 180 181 __at(0x0033) __sfr CLC1SEL1; 182 __at(0x0033) volatile __CLC1SEL1bits_t CLC1SEL1bits; 183 184 __at(0x0034) __sfr CLC1POL; 185 __at(0x0034) volatile __CLC1POLbits_t CLC1POLbits; 186 187 __at(0x0035) __sfr CLC1GLS0; 188 __at(0x0035) volatile __CLC1GLS0bits_t CLC1GLS0bits; 189 190 __at(0x0036) __sfr CLC1GLS1; 191 __at(0x0036) volatile __CLC1GLS1bits_t CLC1GLS1bits; 192 193 __at(0x0037) __sfr CLC1GLS2; 194 __at(0x0037) volatile __CLC1GLS2bits_t CLC1GLS2bits; 195 196 __at(0x0038) __sfr CLC1GLS3; 197 __at(0x0038) volatile __CLC1GLS3bits_t CLC1GLS3bits; 198 199 __at(0x0039) __sfr CWG1CON0; 200 __at(0x0039) volatile __CWG1CON0bits_t CWG1CON0bits; 201 202 __at(0x003A) __sfr CWG1CON1; 203 __at(0x003A) volatile __CWG1CON1bits_t CWG1CON1bits; 204 205 __at(0x003B) __sfr CWG1CON2; 206 __at(0x003B) volatile __CWG1CON2bits_t CWG1CON2bits; 207 208 __at(0x003C) __sfr CWG1DBR; 209 __at(0x003C) volatile __CWG1DBRbits_t CWG1DBRbits; 210 211 __at(0x003D) __sfr CWG1DBF; 212 __at(0x003D) volatile __CWG1DBFbits_t CWG1DBFbits; 213 214 __at(0x003E) __sfr VREGCON; 215 __at(0x003E) volatile __VREGCONbits_t VREGCONbits; 216 217 __at(0x003F) __sfr BORCON; 218 __at(0x003F) volatile __BORCONbits_t BORCONbits; 219