1 /* 2 * This definitions of the PIC16LF1503 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:05 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic16lf1503.h> 26 27 //============================================================================== 28 29 __at(0x0000) __sfr INDF0; 30 31 __at(0x0001) __sfr INDF1; 32 33 __at(0x0002) __sfr PCL; 34 35 __at(0x0003) __sfr STATUS; 36 __at(0x0003) volatile __STATUSbits_t STATUSbits; 37 38 __at(0x0004) __sfr FSR0; 39 40 __at(0x0004) __sfr FSR0L; 41 42 __at(0x0005) __sfr FSR0H; 43 44 __at(0x0006) __sfr FSR1; 45 46 __at(0x0006) __sfr FSR1L; 47 48 __at(0x0007) __sfr FSR1H; 49 50 __at(0x0008) __sfr BSR; 51 __at(0x0008) volatile __BSRbits_t BSRbits; 52 53 __at(0x0009) __sfr WREG; 54 55 __at(0x000A) __sfr PCLATH; 56 57 __at(0x000B) __sfr INTCON; 58 __at(0x000B) volatile __INTCONbits_t INTCONbits; 59 60 __at(0x000C) __sfr PORTA; 61 __at(0x000C) volatile __PORTAbits_t PORTAbits; 62 63 __at(0x000E) __sfr PORTC; 64 __at(0x000E) volatile __PORTCbits_t PORTCbits; 65 66 __at(0x0011) __sfr PIR1; 67 __at(0x0011) volatile __PIR1bits_t PIR1bits; 68 69 __at(0x0012) __sfr PIR2; 70 __at(0x0012) volatile __PIR2bits_t PIR2bits; 71 72 __at(0x0013) __sfr PIR3; 73 __at(0x0013) volatile __PIR3bits_t PIR3bits; 74 75 __at(0x0015) __sfr TMR0; 76 77 __at(0x0016) __sfr TMR1; 78 79 __at(0x0016) __sfr TMR1L; 80 81 __at(0x0017) __sfr TMR1H; 82 83 __at(0x0018) __sfr T1CON; 84 __at(0x0018) volatile __T1CONbits_t T1CONbits; 85 86 __at(0x0019) __sfr T1GCON; 87 __at(0x0019) volatile __T1GCONbits_t T1GCONbits; 88 89 __at(0x001A) __sfr TMR2; 90 91 __at(0x001B) __sfr PR2; 92 93 __at(0x001C) __sfr T2CON; 94 __at(0x001C) volatile __T2CONbits_t T2CONbits; 95 96 __at(0x008C) __sfr TRISA; 97 __at(0x008C) volatile __TRISAbits_t TRISAbits; 98 99 __at(0x008E) __sfr TRISC; 100 __at(0x008E) volatile __TRISCbits_t TRISCbits; 101 102 __at(0x0091) __sfr PIE1; 103 __at(0x0091) volatile __PIE1bits_t PIE1bits; 104 105 __at(0x0092) __sfr PIE2; 106 __at(0x0092) volatile __PIE2bits_t PIE2bits; 107 108 __at(0x0093) __sfr PIE3; 109 __at(0x0093) volatile __PIE3bits_t PIE3bits; 110 111 __at(0x0095) __sfr OPTION_REG; 112 __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits; 113 114 __at(0x0096) __sfr PCON; 115 __at(0x0096) volatile __PCONbits_t PCONbits; 116 117 __at(0x0097) __sfr WDTCON; 118 __at(0x0097) volatile __WDTCONbits_t WDTCONbits; 119 120 __at(0x0099) __sfr OSCCON; 121 __at(0x0099) volatile __OSCCONbits_t OSCCONbits; 122 123 __at(0x009A) __sfr OSCSTAT; 124 __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits; 125 126 __at(0x009B) __sfr ADRES; 127 128 __at(0x009B) __sfr ADRESL; 129 130 __at(0x009C) __sfr ADRESH; 131 132 __at(0x009D) __sfr ADCON0; 133 __at(0x009D) volatile __ADCON0bits_t ADCON0bits; 134 135 __at(0x009E) __sfr ADCON1; 136 __at(0x009E) volatile __ADCON1bits_t ADCON1bits; 137 138 __at(0x009F) __sfr ADCON2; 139 __at(0x009F) volatile __ADCON2bits_t ADCON2bits; 140 141 __at(0x010C) __sfr LATA; 142 __at(0x010C) volatile __LATAbits_t LATAbits; 143 144 __at(0x010E) __sfr LATC; 145 __at(0x010E) volatile __LATCbits_t LATCbits; 146 147 __at(0x0111) __sfr CM1CON0; 148 __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits; 149 150 __at(0x0112) __sfr CM1CON1; 151 __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits; 152 153 __at(0x0113) __sfr CM2CON0; 154 __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits; 155 156 __at(0x0114) __sfr CM2CON1; 157 __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits; 158 159 __at(0x0115) __sfr CMOUT; 160 __at(0x0115) volatile __CMOUTbits_t CMOUTbits; 161 162 __at(0x0116) __sfr BORCON; 163 __at(0x0116) volatile __BORCONbits_t BORCONbits; 164 165 __at(0x0117) __sfr FVRCON; 166 __at(0x0117) volatile __FVRCONbits_t FVRCONbits; 167 168 __at(0x0118) __sfr DACCON0; 169 __at(0x0118) volatile __DACCON0bits_t DACCON0bits; 170 171 __at(0x0119) __sfr DACCON1; 172 __at(0x0119) volatile __DACCON1bits_t DACCON1bits; 173 174 __at(0x011D) __sfr APFCON; 175 __at(0x011D) volatile __APFCONbits_t APFCONbits; 176 177 __at(0x018C) __sfr ANSELA; 178 __at(0x018C) volatile __ANSELAbits_t ANSELAbits; 179 180 __at(0x018E) __sfr ANSELC; 181 __at(0x018E) volatile __ANSELCbits_t ANSELCbits; 182 183 __at(0x0191) __sfr PMADR; 184 185 __at(0x0191) __sfr PMADRL; 186 187 __at(0x0192) __sfr PMADRH; 188 189 __at(0x0193) __sfr PMDAT; 190 191 __at(0x0193) __sfr PMDATL; 192 193 __at(0x0194) __sfr PMDATH; 194 195 __at(0x0195) __sfr PMCON1; 196 __at(0x0195) volatile __PMCON1bits_t PMCON1bits; 197 198 __at(0x0196) __sfr PMCON2; 199 200 __at(0x020C) __sfr WPUA; 201 __at(0x020C) volatile __WPUAbits_t WPUAbits; 202 203 __at(0x0211) __sfr SSP1BUF; 204 205 __at(0x0211) __sfr SSPBUF; 206 207 __at(0x0212) __sfr SSP1ADD; 208 209 __at(0x0212) __sfr SSPADD; 210 211 __at(0x0213) __sfr SSP1MSK; 212 213 __at(0x0213) __sfr SSPMSK; 214 215 __at(0x0214) __sfr SSP1STAT; 216 __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits; 217 218 __at(0x0214) __sfr SSPSTAT; 219 __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits; 220 221 __at(0x0215) __sfr SSP1CON1; 222 __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits; 223 224 __at(0x0215) __sfr SSPCON; 225 __at(0x0215) volatile __SSPCONbits_t SSPCONbits; 226 227 __at(0x0215) __sfr SSPCON1; 228 __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits; 229 230 __at(0x0216) __sfr SSP1CON2; 231 __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits; 232 233 __at(0x0216) __sfr SSPCON2; 234 __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits; 235 236 __at(0x0217) __sfr SSP1CON3; 237 __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits; 238 239 __at(0x0217) __sfr SSPCON3; 240 __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits; 241 242 __at(0x0391) __sfr IOCAP; 243 __at(0x0391) volatile __IOCAPbits_t IOCAPbits; 244 245 __at(0x0392) __sfr IOCAN; 246 __at(0x0392) volatile __IOCANbits_t IOCANbits; 247 248 __at(0x0393) __sfr IOCAF; 249 __at(0x0393) volatile __IOCAFbits_t IOCAFbits; 250 251 __at(0x0498) __sfr NCO1ACC; 252 253 __at(0x0498) __sfr NCO1ACCL; 254 __at(0x0498) volatile __NCO1ACCLbits_t NCO1ACCLbits; 255 256 __at(0x0499) __sfr NCO1ACCH; 257 __at(0x0499) volatile __NCO1ACCHbits_t NCO1ACCHbits; 258 259 __at(0x049A) __sfr NCO1ACCU; 260 __at(0x049A) volatile __NCO1ACCUbits_t NCO1ACCUbits; 261 262 __at(0x049B) __sfr NCO1INC; 263 264 __at(0x049B) __sfr NCO1INCL; 265 __at(0x049B) volatile __NCO1INCLbits_t NCO1INCLbits; 266 267 __at(0x049C) __sfr NCO1INCH; 268 __at(0x049C) volatile __NCO1INCHbits_t NCO1INCHbits; 269 270 __at(0x049D) __sfr NCO1INCU; 271 272 __at(0x049E) __sfr NCO1CON; 273 __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits; 274 275 __at(0x049F) __sfr NCO1CLK; 276 __at(0x049F) volatile __NCO1CLKbits_t NCO1CLKbits; 277 278 __at(0x0611) __sfr PWM1DCL; 279 __at(0x0611) volatile __PWM1DCLbits_t PWM1DCLbits; 280 281 __at(0x0612) __sfr PWM1DCH; 282 __at(0x0612) volatile __PWM1DCHbits_t PWM1DCHbits; 283 284 __at(0x0613) __sfr PWM1CON; 285 __at(0x0613) volatile __PWM1CONbits_t PWM1CONbits; 286 287 __at(0x0613) __sfr PWM1CON0; 288 __at(0x0613) volatile __PWM1CON0bits_t PWM1CON0bits; 289 290 __at(0x0614) __sfr PWM2DCL; 291 __at(0x0614) volatile __PWM2DCLbits_t PWM2DCLbits; 292 293 __at(0x0615) __sfr PWM2DCH; 294 __at(0x0615) volatile __PWM2DCHbits_t PWM2DCHbits; 295 296 __at(0x0616) __sfr PWM2CON; 297 __at(0x0616) volatile __PWM2CONbits_t PWM2CONbits; 298 299 __at(0x0616) __sfr PWM2CON0; 300 __at(0x0616) volatile __PWM2CON0bits_t PWM2CON0bits; 301 302 __at(0x0617) __sfr PWM3DCL; 303 __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits; 304 305 __at(0x0618) __sfr PWM3DCH; 306 __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits; 307 308 __at(0x0619) __sfr PWM3CON; 309 __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits; 310 311 __at(0x0619) __sfr PWM3CON0; 312 __at(0x0619) volatile __PWM3CON0bits_t PWM3CON0bits; 313 314 __at(0x061A) __sfr PWM4DCL; 315 __at(0x061A) volatile __PWM4DCLbits_t PWM4DCLbits; 316 317 __at(0x061B) __sfr PWM4DCH; 318 __at(0x061B) volatile __PWM4DCHbits_t PWM4DCHbits; 319 320 __at(0x061C) __sfr PWM4CON; 321 __at(0x061C) volatile __PWM4CONbits_t PWM4CONbits; 322 323 __at(0x061C) __sfr PWM4CON0; 324 __at(0x061C) volatile __PWM4CON0bits_t PWM4CON0bits; 325 326 __at(0x0691) __sfr CWG1DBR; 327 __at(0x0691) volatile __CWG1DBRbits_t CWG1DBRbits; 328 329 __at(0x0692) __sfr CWG1DBF; 330 __at(0x0692) volatile __CWG1DBFbits_t CWG1DBFbits; 331 332 __at(0x0693) __sfr CWG1CON0; 333 __at(0x0693) volatile __CWG1CON0bits_t CWG1CON0bits; 334 335 __at(0x0694) __sfr CWG1CON1; 336 __at(0x0694) volatile __CWG1CON1bits_t CWG1CON1bits; 337 338 __at(0x0695) __sfr CWG1CON2; 339 __at(0x0695) volatile __CWG1CON2bits_t CWG1CON2bits; 340 341 __at(0x0F0F) __sfr CLCDATA; 342 __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits; 343 344 __at(0x0F10) __sfr CLC1CON; 345 __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits; 346 347 __at(0x0F11) __sfr CLC1POL; 348 __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits; 349 350 __at(0x0F12) __sfr CLC1SEL0; 351 __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits; 352 353 __at(0x0F13) __sfr CLC1SEL1; 354 __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits; 355 356 __at(0x0F14) __sfr CLC1GLS0; 357 __at(0x0F14) volatile __CLC1GLS0bits_t CLC1GLS0bits; 358 359 __at(0x0F15) __sfr CLC1GLS1; 360 __at(0x0F15) volatile __CLC1GLS1bits_t CLC1GLS1bits; 361 362 __at(0x0F16) __sfr CLC1GLS2; 363 __at(0x0F16) volatile __CLC1GLS2bits_t CLC1GLS2bits; 364 365 __at(0x0F17) __sfr CLC1GLS3; 366 __at(0x0F17) volatile __CLC1GLS3bits_t CLC1GLS3bits; 367 368 __at(0x0F18) __sfr CLC2CON; 369 __at(0x0F18) volatile __CLC2CONbits_t CLC2CONbits; 370 371 __at(0x0F19) __sfr CLC2POL; 372 __at(0x0F19) volatile __CLC2POLbits_t CLC2POLbits; 373 374 __at(0x0F1A) __sfr CLC2SEL0; 375 __at(0x0F1A) volatile __CLC2SEL0bits_t CLC2SEL0bits; 376 377 __at(0x0F1B) __sfr CLC2SEL1; 378 __at(0x0F1B) volatile __CLC2SEL1bits_t CLC2SEL1bits; 379 380 __at(0x0F1C) __sfr CLC2GLS0; 381 __at(0x0F1C) volatile __CLC2GLS0bits_t CLC2GLS0bits; 382 383 __at(0x0F1D) __sfr CLC2GLS1; 384 __at(0x0F1D) volatile __CLC2GLS1bits_t CLC2GLS1bits; 385 386 __at(0x0F1E) __sfr CLC2GLS2; 387 __at(0x0F1E) volatile __CLC2GLS2bits_t CLC2GLS2bits; 388 389 __at(0x0F1F) __sfr CLC2GLS3; 390 __at(0x0F1F) volatile __CLC2GLS3bits_t CLC2GLS3bits; 391 392 __at(0x0FE3) __sfr BSR_ICDSHAD; 393 394 __at(0x0FE4) __sfr STATUS_SHAD; 395 __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits; 396 397 __at(0x0FE5) __sfr WREG_SHAD; 398 399 __at(0x0FE6) __sfr BSR_SHAD; 400 401 __at(0x0FE7) __sfr PCLATH_SHAD; 402 403 __at(0x0FE8) __sfr FSR0L_SHAD; 404 405 __at(0x0FE9) __sfr FSR0H_SHAD; 406 407 __at(0x0FEA) __sfr FSR1L_SHAD; 408 409 __at(0x0FEB) __sfr FSR1H_SHAD; 410 411 __at(0x0FED) __sfr STKPTR; 412 413 __at(0x0FEE) __sfr TOSL; 414 415 __at(0x0FEF) __sfr TOSH; 416