1 /* 2 * This definitions of the PIC18F2420 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:43 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic18f2420.h> 26 27 //============================================================================== 28 29 __at(0x0F80) __sfr PORTA; 30 __at(0x0F80) volatile __PORTAbits_t PORTAbits; 31 32 __at(0x0F81) __sfr PORTB; 33 __at(0x0F81) volatile __PORTBbits_t PORTBbits; 34 35 __at(0x0F82) __sfr PORTC; 36 __at(0x0F82) volatile __PORTCbits_t PORTCbits; 37 38 __at(0x0F84) __sfr PORTE; 39 __at(0x0F84) volatile __PORTEbits_t PORTEbits; 40 41 __at(0x0F89) __sfr LATA; 42 __at(0x0F89) volatile __LATAbits_t LATAbits; 43 44 __at(0x0F8A) __sfr LATB; 45 __at(0x0F8A) volatile __LATBbits_t LATBbits; 46 47 __at(0x0F8B) __sfr LATC; 48 __at(0x0F8B) volatile __LATCbits_t LATCbits; 49 50 __at(0x0F92) __sfr DDRA; 51 __at(0x0F92) volatile __DDRAbits_t DDRAbits; 52 53 __at(0x0F92) __sfr TRISA; 54 __at(0x0F92) volatile __TRISAbits_t TRISAbits; 55 56 __at(0x0F93) __sfr DDRB; 57 __at(0x0F93) volatile __DDRBbits_t DDRBbits; 58 59 __at(0x0F93) __sfr TRISB; 60 __at(0x0F93) volatile __TRISBbits_t TRISBbits; 61 62 __at(0x0F94) __sfr DDRC; 63 __at(0x0F94) volatile __DDRCbits_t DDRCbits; 64 65 __at(0x0F94) __sfr TRISC; 66 __at(0x0F94) volatile __TRISCbits_t TRISCbits; 67 68 __at(0x0F9B) __sfr OSCTUNE; 69 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits; 70 71 __at(0x0F9D) __sfr PIE1; 72 __at(0x0F9D) volatile __PIE1bits_t PIE1bits; 73 74 __at(0x0F9E) __sfr PIR1; 75 __at(0x0F9E) volatile __PIR1bits_t PIR1bits; 76 77 __at(0x0F9F) __sfr IPR1; 78 __at(0x0F9F) volatile __IPR1bits_t IPR1bits; 79 80 __at(0x0FA0) __sfr PIE2; 81 __at(0x0FA0) volatile __PIE2bits_t PIE2bits; 82 83 __at(0x0FA1) __sfr PIR2; 84 __at(0x0FA1) volatile __PIR2bits_t PIR2bits; 85 86 __at(0x0FA2) __sfr IPR2; 87 __at(0x0FA2) volatile __IPR2bits_t IPR2bits; 88 89 __at(0x0FA6) __sfr EECON1; 90 __at(0x0FA6) volatile __EECON1bits_t EECON1bits; 91 92 __at(0x0FA7) __sfr EECON2; 93 94 __at(0x0FA8) __sfr EEDATA; 95 96 __at(0x0FA9) __sfr EEADR; 97 98 __at(0x0FAB) __sfr RCSTA; 99 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits; 100 101 __at(0x0FAC) __sfr TXSTA; 102 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits; 103 104 __at(0x0FAD) __sfr TXREG; 105 106 __at(0x0FAE) __sfr RCREG; 107 108 __at(0x0FAF) __sfr SPBRG; 109 110 __at(0x0FB0) __sfr SPBRGH; 111 112 __at(0x0FB1) __sfr T3CON; 113 __at(0x0FB1) volatile __T3CONbits_t T3CONbits; 114 115 __at(0x0FB2) __sfr TMR3; 116 117 __at(0x0FB2) __sfr TMR3L; 118 119 __at(0x0FB3) __sfr TMR3H; 120 121 __at(0x0FB4) __sfr CMCON; 122 __at(0x0FB4) volatile __CMCONbits_t CMCONbits; 123 124 __at(0x0FB5) __sfr CVRCON; 125 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits; 126 127 __at(0x0FB6) __sfr ECCP1AS; 128 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits; 129 130 __at(0x0FB6) __sfr ECCPAS; 131 __at(0x0FB6) volatile __ECCPASbits_t ECCPASbits; 132 133 __at(0x0FB7) __sfr ECCP1DEL; 134 __at(0x0FB7) volatile __ECCP1DELbits_t ECCP1DELbits; 135 136 __at(0x0FB7) __sfr PWM1CON; 137 __at(0x0FB7) volatile __PWM1CONbits_t PWM1CONbits; 138 139 __at(0x0FB8) __sfr BAUDCON; 140 __at(0x0FB8) volatile __BAUDCONbits_t BAUDCONbits; 141 142 __at(0x0FB8) __sfr BAUDCTL; 143 __at(0x0FB8) volatile __BAUDCTLbits_t BAUDCTLbits; 144 145 __at(0x0FBA) __sfr CCP2CON; 146 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits; 147 148 __at(0x0FBB) __sfr CCPR2; 149 150 __at(0x0FBB) __sfr CCPR2L; 151 152 __at(0x0FBC) __sfr CCPR2H; 153 154 __at(0x0FBD) __sfr CCP1CON; 155 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits; 156 157 __at(0x0FBE) __sfr CCPR1; 158 159 __at(0x0FBE) __sfr CCPR1L; 160 161 __at(0x0FBF) __sfr CCPR1H; 162 163 __at(0x0FC0) __sfr ADCON2; 164 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits; 165 166 __at(0x0FC1) __sfr ADCON1; 167 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits; 168 169 __at(0x0FC2) __sfr ADCON0; 170 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits; 171 172 __at(0x0FC3) __sfr ADRES; 173 174 __at(0x0FC3) __sfr ADRESL; 175 176 __at(0x0FC4) __sfr ADRESH; 177 178 __at(0x0FC5) __sfr SSPCON2; 179 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits; 180 181 __at(0x0FC6) __sfr SSPCON1; 182 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits; 183 184 __at(0x0FC7) __sfr SSPSTAT; 185 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits; 186 187 __at(0x0FC8) __sfr SSPADD; 188 189 __at(0x0FC9) __sfr SSPBUF; 190 191 __at(0x0FCA) __sfr T2CON; 192 __at(0x0FCA) volatile __T2CONbits_t T2CONbits; 193 194 __at(0x0FCB) __sfr PR2; 195 196 __at(0x0FCC) __sfr TMR2; 197 198 __at(0x0FCD) __sfr T1CON; 199 __at(0x0FCD) volatile __T1CONbits_t T1CONbits; 200 201 __at(0x0FCE) __sfr TMR1; 202 203 __at(0x0FCE) __sfr TMR1L; 204 205 __at(0x0FCF) __sfr TMR1H; 206 207 __at(0x0FD0) __sfr RCON; 208 __at(0x0FD0) volatile __RCONbits_t RCONbits; 209 210 __at(0x0FD1) __sfr WDTCON; 211 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits; 212 213 __at(0x0FD2) __sfr HLVDCON; 214 __at(0x0FD2) volatile __HLVDCONbits_t HLVDCONbits; 215 216 __at(0x0FD2) __sfr LVDCON; 217 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits; 218 219 __at(0x0FD3) __sfr OSCCON; 220 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits; 221 222 __at(0x0FD5) __sfr T0CON; 223 __at(0x0FD5) volatile __T0CONbits_t T0CONbits; 224 225 __at(0x0FD6) __sfr TMR0; 226 227 __at(0x0FD6) __sfr TMR0L; 228 229 __at(0x0FD7) __sfr TMR0H; 230 231 __at(0x0FD8) __sfr STATUS; 232 __at(0x0FD8) volatile __STATUSbits_t STATUSbits; 233 234 __at(0x0FD9) __sfr FSR2L; 235 236 __at(0x0FDA) __sfr FSR2H; 237 238 __at(0x0FDB) __sfr PLUSW2; 239 240 __at(0x0FDC) __sfr PREINC2; 241 242 __at(0x0FDD) __sfr POSTDEC2; 243 244 __at(0x0FDE) __sfr POSTINC2; 245 246 __at(0x0FDF) __sfr INDF2; 247 248 __at(0x0FE0) __sfr BSR; 249 250 __at(0x0FE1) __sfr FSR1L; 251 252 __at(0x0FE2) __sfr FSR1H; 253 254 __at(0x0FE3) __sfr PLUSW1; 255 256 __at(0x0FE4) __sfr PREINC1; 257 258 __at(0x0FE5) __sfr POSTDEC1; 259 260 __at(0x0FE6) __sfr POSTINC1; 261 262 __at(0x0FE7) __sfr INDF1; 263 264 __at(0x0FE8) __sfr WREG; 265 266 __at(0x0FE9) __sfr FSR0L; 267 268 __at(0x0FEA) __sfr FSR0H; 269 270 __at(0x0FEB) __sfr PLUSW0; 271 272 __at(0x0FEC) __sfr PREINC0; 273 274 __at(0x0FED) __sfr POSTDEC0; 275 276 __at(0x0FEE) __sfr POSTINC0; 277 278 __at(0x0FEF) __sfr INDF0; 279 280 __at(0x0FF0) __sfr INTCON3; 281 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits; 282 283 __at(0x0FF1) __sfr INTCON2; 284 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits; 285 286 __at(0x0FF2) __sfr INTCON; 287 __at(0x0FF2) volatile __INTCONbits_t INTCONbits; 288 289 __at(0x0FF3) __sfr PROD; 290 291 __at(0x0FF3) __sfr PRODL; 292 293 __at(0x0FF4) __sfr PRODH; 294 295 __at(0x0FF5) __sfr TABLAT; 296 297 __at(0x0FF6) __sfr TBLPTR; 298 299 __at(0x0FF6) __sfr TBLPTRL; 300 301 __at(0x0FF7) __sfr TBLPTRH; 302 303 __at(0x0FF8) __sfr TBLPTRU; 304 305 __at(0x0FF9) __sfr PC; 306 307 __at(0x0FF9) __sfr PCL; 308 309 __at(0x0FFA) __sfr PCLATH; 310 311 __at(0x0FFB) __sfr PCLATU; 312 313 __at(0x0FFC) __sfr STKPTR; 314 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits; 315 316 __at(0x0FFD) __sfr TOS; 317 318 __at(0x0FFD) __sfr TOSL; 319 320 __at(0x0FFE) __sfr TOSH; 321 322 __at(0x0FFF) __sfr TOSU; 323