1 /* 2 * This definitions of the PIC18LF27J13 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:55 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic18lf27j13.h> 26 27 //============================================================================== 28 29 __at(0x0EB8) __sfr ADCTRIG; 30 __at(0x0EB8) volatile __ADCTRIGbits_t ADCTRIGbits; 31 32 __at(0x0EB9) __sfr PD0; 33 __at(0x0EB9) volatile __PD0bits_t PD0bits; 34 35 __at(0x0EB9) __sfr PMDIS0; 36 __at(0x0EB9) volatile __PMDIS0bits_t PMDIS0bits; 37 38 __at(0x0EBA) __sfr PD1; 39 __at(0x0EBA) volatile __PD1bits_t PD1bits; 40 41 __at(0x0EBA) __sfr PMDIS1; 42 __at(0x0EBA) volatile __PMDIS1bits_t PMDIS1bits; 43 44 __at(0x0EBB) __sfr PD2; 45 __at(0x0EBB) volatile __PD2bits_t PD2bits; 46 47 __at(0x0EBB) __sfr PMDIS2; 48 __at(0x0EBB) volatile __PMDIS2bits_t PMDIS2bits; 49 50 __at(0x0EBC) __sfr PD3; 51 __at(0x0EBC) volatile __PD3bits_t PD3bits; 52 53 __at(0x0EBC) __sfr PMDIS3; 54 __at(0x0EBC) volatile __PMDIS3bits_t PMDIS3bits; 55 56 __at(0x0EBF) __sfr PPSCON; 57 __at(0x0EBF) volatile __PPSCONbits_t PPSCONbits; 58 59 __at(0x0EC0) __sfr RPOR0; 60 61 __at(0x0EC1) __sfr RPOR1; 62 63 __at(0x0EC2) __sfr RPOR2; 64 65 __at(0x0EC3) __sfr RPOR3; 66 67 __at(0x0EC4) __sfr RPOR4; 68 69 __at(0x0EC5) __sfr RPOR5; 70 71 __at(0x0EC6) __sfr RPOR6; 72 73 __at(0x0EC7) __sfr RPOR7; 74 75 __at(0x0EC8) __sfr RPOR8; 76 77 __at(0x0EC9) __sfr RPOR9; 78 79 __at(0x0ECA) __sfr RPOR10; 80 81 __at(0x0ECB) __sfr RPOR11; 82 83 __at(0x0ECC) __sfr RPOR12; 84 85 __at(0x0ECD) __sfr RPOR13; 86 87 __at(0x0ECE) __sfr RPOR14; 88 89 __at(0x0ECF) __sfr RPOR15; 90 91 __at(0x0ED0) __sfr RPOR16; 92 93 __at(0x0ED1) __sfr RPOR17; 94 95 __at(0x0ED2) __sfr RPOR18; 96 97 __at(0x0EE1) __sfr RPINR1; 98 99 __at(0x0EE2) __sfr RPINR2; 100 101 __at(0x0EE3) __sfr RPINR3; 102 103 __at(0x0EE4) __sfr RPINR4; 104 105 __at(0x0EE6) __sfr RPINR6; 106 107 __at(0x0EE7) __sfr RPINR15; 108 109 __at(0x0EE8) __sfr RPINR7; 110 111 __at(0x0EE9) __sfr RPINR8; 112 113 __at(0x0EEA) __sfr RPINR9; 114 115 __at(0x0EF2) __sfr RPINR12; 116 117 __at(0x0EF3) __sfr RPINR13; 118 119 __at(0x0EF4) __sfr RPINR14; 120 121 __at(0x0EF7) __sfr RPINR16; 122 123 __at(0x0EF8) __sfr RPINR17; 124 125 __at(0x0EFC) __sfr RPINR21; 126 127 __at(0x0EFD) __sfr RPINR22; 128 129 __at(0x0EFE) __sfr RPINR23; 130 131 __at(0x0EFF) __sfr RPINR24; 132 133 __at(0x0F00) __sfr CCP10CON; 134 __at(0x0F00) volatile __CCP10CONbits_t CCP10CONbits; 135 136 __at(0x0F01) __sfr CCPR10L; 137 138 __at(0x0F02) __sfr CCPR10H; 139 140 __at(0x0F03) __sfr CCP9CON; 141 __at(0x0F03) volatile __CCP9CONbits_t CCP9CONbits; 142 143 __at(0x0F04) __sfr CCPR9L; 144 145 __at(0x0F05) __sfr CCPR9H; 146 147 __at(0x0F06) __sfr CCP8CON; 148 __at(0x0F06) volatile __CCP8CONbits_t CCP8CONbits; 149 150 __at(0x0F07) __sfr CCPR8L; 151 152 __at(0x0F08) __sfr CCPR8H; 153 154 __at(0x0F09) __sfr CCP7CON; 155 __at(0x0F09) volatile __CCP7CONbits_t CCP7CONbits; 156 157 __at(0x0F0A) __sfr CCPR7L; 158 159 __at(0x0F0B) __sfr CCPR7H; 160 161 __at(0x0F0C) __sfr CCP6CON; 162 __at(0x0F0C) volatile __CCP6CONbits_t CCP6CONbits; 163 164 __at(0x0F0D) __sfr CCPR6L; 165 166 __at(0x0F0E) __sfr CCPR6H; 167 168 __at(0x0F0F) __sfr CCP5CON; 169 __at(0x0F0F) volatile __CCP5CONbits_t CCP5CONbits; 170 171 __at(0x0F10) __sfr CCPR5L; 172 173 __at(0x0F11) __sfr CCPR5H; 174 175 __at(0x0F12) __sfr CCP4CON; 176 __at(0x0F12) volatile __CCP4CONbits_t CCP4CONbits; 177 178 __at(0x0F13) __sfr CCPR4L; 179 180 __at(0x0F14) __sfr CCPR4H; 181 182 __at(0x0F15) __sfr CCP3CON; 183 __at(0x0F15) volatile __CCP3CONbits_t CCP3CONbits; 184 185 __at(0x0F16) __sfr CCPR3L; 186 187 __at(0x0F17) __sfr CCPR3H; 188 189 __at(0x0F18) __sfr ECCP3DEL; 190 __at(0x0F18) volatile __ECCP3DELbits_t ECCP3DELbits; 191 192 __at(0x0F19) __sfr ECCP3AS; 193 __at(0x0F19) volatile __ECCP3ASbits_t ECCP3ASbits; 194 195 __at(0x0F1A) __sfr PSTR3CON; 196 __at(0x0F1A) volatile __PSTR3CONbits_t PSTR3CONbits; 197 198 __at(0x0F1B) __sfr T8CON; 199 __at(0x0F1B) volatile __T8CONbits_t T8CONbits; 200 201 __at(0x0F1C) __sfr PR8; 202 203 __at(0x0F1D) __sfr TMR8; 204 205 __at(0x0F1E) __sfr T6CON; 206 __at(0x0F1E) volatile __T6CONbits_t T6CONbits; 207 208 __at(0x0F1F) __sfr PR6; 209 210 __at(0x0F20) __sfr TMR6; 211 212 __at(0x0F21) __sfr T5GCON; 213 __at(0x0F21) volatile __T5GCONbits_t T5GCONbits; 214 215 __at(0x0F22) __sfr T5CON; 216 __at(0x0F22) volatile __T5CONbits_t T5CONbits; 217 218 __at(0x0F23) __sfr TMR5L; 219 220 __at(0x0F24) __sfr TMR5H; 221 222 __at(0x0F25) __sfr CM3CON; 223 __at(0x0F25) volatile __CM3CONbits_t CM3CONbits; 224 225 __at(0x0F3A) __sfr RTCVALL; 226 227 __at(0x0F3B) __sfr RTCVALH; 228 229 __at(0x0F3C) __sfr PADCFG1; 230 __at(0x0F3C) volatile __PADCFG1bits_t PADCFG1bits; 231 232 __at(0x0F3D) __sfr REFOCON; 233 __at(0x0F3D) volatile __REFOCONbits_t REFOCONbits; 234 235 __at(0x0F3E) __sfr RTCCAL; 236 __at(0x0F3E) volatile __RTCCALbits_t RTCCALbits; 237 238 __at(0x0F3F) __sfr RTCCFG; 239 __at(0x0F3F) volatile __RTCCFGbits_t RTCCFGbits; 240 241 __at(0x0F40) __sfr ODCON3; 242 __at(0x0F40) volatile __ODCON3bits_t ODCON3bits; 243 244 __at(0x0F41) __sfr ODCON2; 245 __at(0x0F41) volatile __ODCON2bits_t ODCON2bits; 246 247 __at(0x0F42) __sfr ODCON1; 248 __at(0x0F42) volatile __ODCON1bits_t ODCON1bits; 249 250 __at(0x0F44) __sfr ALRMVALL; 251 252 __at(0x0F45) __sfr ALRMVALH; 253 254 __at(0x0F46) __sfr ALRMRPT; 255 __at(0x0F46) volatile __ALRMRPTbits_t ALRMRPTbits; 256 257 __at(0x0F47) __sfr ALRMCFG; 258 __at(0x0F47) volatile __ALRMCFGbits_t ALRMCFGbits; 259 260 __at(0x0F48) __sfr ANCON0; 261 __at(0x0F48) volatile __ANCON0bits_t ANCON0bits; 262 263 __at(0x0F49) __sfr ANCON1; 264 __at(0x0F49) volatile __ANCON1bits_t ANCON1bits; 265 266 __at(0x0F4A) __sfr DSWAKEL; 267 __at(0x0F4A) volatile __DSWAKELbits_t DSWAKELbits; 268 269 __at(0x0F4B) __sfr DSWAKEH; 270 __at(0x0F4B) volatile __DSWAKEHbits_t DSWAKEHbits; 271 272 __at(0x0F4C) __sfr DSCONL; 273 __at(0x0F4C) volatile __DSCONLbits_t DSCONLbits; 274 275 __at(0x0F4D) __sfr DSCONH; 276 __at(0x0F4D) volatile __DSCONHbits_t DSCONHbits; 277 278 __at(0x0F4E) __sfr DSGPR0; 279 280 __at(0x0F4F) __sfr DSGPR1; 281 282 __at(0x0F50) __sfr CCPTMRS2; 283 __at(0x0F50) volatile __CCPTMRS2bits_t CCPTMRS2bits; 284 285 __at(0x0F51) __sfr CCPTMRS1; 286 __at(0x0F51) volatile __CCPTMRS1bits_t CCPTMRS1bits; 287 288 __at(0x0F52) __sfr CCPTMRS0; 289 __at(0x0F52) volatile __CCPTMRS0bits_t CCPTMRS0bits; 290 291 __at(0x0F53) __sfr CVRCON; 292 __at(0x0F53) volatile __CVRCONbits_t CVRCONbits; 293 294 __at(0x0F66) __sfr DMABCH; 295 296 __at(0x0F67) __sfr DMABCL; 297 298 __at(0x0F68) __sfr RXADDRH; 299 300 __at(0x0F69) __sfr RXADDRL; 301 302 __at(0x0F6A) __sfr TXADDRH; 303 304 __at(0x0F6B) __sfr TXADDRL; 305 306 __at(0x0F70) __sfr CMSTAT; 307 __at(0x0F70) volatile __CMSTATbits_t CMSTATbits; 308 309 __at(0x0F70) __sfr CMSTATUS; 310 __at(0x0F70) volatile __CMSTATUSbits_t CMSTATUSbits; 311 312 __at(0x0F71) __sfr SSP2CON2; 313 __at(0x0F71) volatile __SSP2CON2bits_t SSP2CON2bits; 314 315 __at(0x0F72) __sfr SSP2CON1; 316 __at(0x0F72) volatile __SSP2CON1bits_t SSP2CON1bits; 317 318 __at(0x0F73) __sfr SSP2STAT; 319 __at(0x0F73) volatile __SSP2STATbits_t SSP2STATbits; 320 321 __at(0x0F74) __sfr SSP2ADD; 322 323 __at(0x0F74) __sfr SSP2MSK; 324 __at(0x0F74) volatile __SSP2MSKbits_t SSP2MSKbits; 325 326 __at(0x0F75) __sfr SSP2BUF; 327 328 __at(0x0F76) __sfr T4CON; 329 __at(0x0F76) volatile __T4CONbits_t T4CONbits; 330 331 __at(0x0F77) __sfr PR4; 332 333 __at(0x0F78) __sfr TMR4; 334 335 __at(0x0F79) __sfr T3CON; 336 __at(0x0F79) volatile __T3CONbits_t T3CONbits; 337 338 __at(0x0F7A) __sfr TMR3; 339 340 __at(0x0F7A) __sfr TMR3L; 341 342 __at(0x0F7B) __sfr TMR3H; 343 344 __at(0x0F7C) __sfr BAUDCON2; 345 __at(0x0F7C) volatile __BAUDCON2bits_t BAUDCON2bits; 346 347 __at(0x0F7D) __sfr SPBRGH2; 348 349 __at(0x0F7E) __sfr BAUDCON; 350 __at(0x0F7E) volatile __BAUDCONbits_t BAUDCONbits; 351 352 __at(0x0F7E) __sfr BAUDCON1; 353 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits; 354 355 __at(0x0F7E) __sfr BAUDCTL; 356 __at(0x0F7E) volatile __BAUDCTLbits_t BAUDCTLbits; 357 358 __at(0x0F7F) __sfr SPBRGH; 359 360 __at(0x0F7F) __sfr SPBRGH1; 361 362 __at(0x0F80) __sfr PORTA; 363 __at(0x0F80) volatile __PORTAbits_t PORTAbits; 364 365 __at(0x0F81) __sfr PORTB; 366 __at(0x0F81) volatile __PORTBbits_t PORTBbits; 367 368 __at(0x0F82) __sfr PORTC; 369 __at(0x0F82) volatile __PORTCbits_t PORTCbits; 370 371 __at(0x0F85) __sfr HLVDCON; 372 __at(0x0F85) volatile __HLVDCONbits_t HLVDCONbits; 373 374 __at(0x0F86) __sfr DMACON2; 375 __at(0x0F86) volatile __DMACON2bits_t DMACON2bits; 376 377 __at(0x0F87) __sfr OSCCON2; 378 __at(0x0F87) volatile __OSCCON2bits_t OSCCON2bits; 379 380 __at(0x0F88) __sfr DMACON1; 381 __at(0x0F88) volatile __DMACON1bits_t DMACON1bits; 382 383 __at(0x0F89) __sfr LATA; 384 __at(0x0F89) volatile __LATAbits_t LATAbits; 385 386 __at(0x0F8A) __sfr LATB; 387 __at(0x0F8A) volatile __LATBbits_t LATBbits; 388 389 __at(0x0F8B) __sfr LATC; 390 __at(0x0F8B) volatile __LATCbits_t LATCbits; 391 392 __at(0x0F8E) __sfr PIE4; 393 __at(0x0F8E) volatile __PIE4bits_t PIE4bits; 394 395 __at(0x0F8F) __sfr PIR4; 396 __at(0x0F8F) volatile __PIR4bits_t PIR4bits; 397 398 __at(0x0F90) __sfr IPR4; 399 __at(0x0F90) volatile __IPR4bits_t IPR4bits; 400 401 __at(0x0F91) __sfr PIE5; 402 __at(0x0F91) volatile __PIE5bits_t PIE5bits; 403 404 __at(0x0F92) __sfr TRISA; 405 __at(0x0F92) volatile __TRISAbits_t TRISAbits; 406 407 __at(0x0F93) __sfr TRISB; 408 __at(0x0F93) volatile __TRISBbits_t TRISBbits; 409 410 __at(0x0F94) __sfr TRISC; 411 __at(0x0F94) volatile __TRISCbits_t TRISCbits; 412 413 __at(0x0F97) __sfr T3GCON; 414 __at(0x0F97) volatile __T3GCONbits_t T3GCONbits; 415 416 __at(0x0F98) __sfr PIR5; 417 __at(0x0F98) volatile __PIR5bits_t PIR5bits; 418 419 __at(0x0F99) __sfr IPR5; 420 __at(0x0F99) volatile __IPR5bits_t IPR5bits; 421 422 __at(0x0F9A) __sfr T1GCON; 423 __at(0x0F9A) volatile __T1GCONbits_t T1GCONbits; 424 425 __at(0x0F9B) __sfr OSCTUNE; 426 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits; 427 428 __at(0x0F9C) __sfr RCSTA2; 429 __at(0x0F9C) volatile __RCSTA2bits_t RCSTA2bits; 430 431 __at(0x0F9D) __sfr PIE1; 432 __at(0x0F9D) volatile __PIE1bits_t PIE1bits; 433 434 __at(0x0F9E) __sfr PIR1; 435 __at(0x0F9E) volatile __PIR1bits_t PIR1bits; 436 437 __at(0x0F9F) __sfr IPR1; 438 __at(0x0F9F) volatile __IPR1bits_t IPR1bits; 439 440 __at(0x0FA0) __sfr PIE2; 441 __at(0x0FA0) volatile __PIE2bits_t PIE2bits; 442 443 __at(0x0FA1) __sfr PIR2; 444 __at(0x0FA1) volatile __PIR2bits_t PIR2bits; 445 446 __at(0x0FA2) __sfr IPR2; 447 __at(0x0FA2) volatile __IPR2bits_t IPR2bits; 448 449 __at(0x0FA3) __sfr PIE3; 450 __at(0x0FA3) volatile __PIE3bits_t PIE3bits; 451 452 __at(0x0FA4) __sfr PIR3; 453 __at(0x0FA4) volatile __PIR3bits_t PIR3bits; 454 455 __at(0x0FA5) __sfr IPR3; 456 __at(0x0FA5) volatile __IPR3bits_t IPR3bits; 457 458 __at(0x0FA6) __sfr EECON1; 459 __at(0x0FA6) volatile __EECON1bits_t EECON1bits; 460 461 __at(0x0FA7) __sfr EECON2; 462 463 __at(0x0FA8) __sfr TXSTA2; 464 __at(0x0FA8) volatile __TXSTA2bits_t TXSTA2bits; 465 466 __at(0x0FA9) __sfr TXREG2; 467 468 __at(0x0FAA) __sfr RCREG2; 469 470 __at(0x0FAB) __sfr SPBRG2; 471 472 __at(0x0FAC) __sfr RCSTA; 473 __at(0x0FAC) volatile __RCSTAbits_t RCSTAbits; 474 475 __at(0x0FAC) __sfr RCSTA1; 476 __at(0x0FAC) volatile __RCSTA1bits_t RCSTA1bits; 477 478 __at(0x0FAD) __sfr TXSTA; 479 __at(0x0FAD) volatile __TXSTAbits_t TXSTAbits; 480 481 __at(0x0FAD) __sfr TXSTA1; 482 __at(0x0FAD) volatile __TXSTA1bits_t TXSTA1bits; 483 484 __at(0x0FAE) __sfr TXREG; 485 486 __at(0x0FAE) __sfr TXREG1; 487 488 __at(0x0FAF) __sfr RCREG; 489 490 __at(0x0FAF) __sfr RCREG1; 491 492 __at(0x0FB0) __sfr SPBRG; 493 494 __at(0x0FB0) __sfr SPBRG1; 495 496 __at(0x0FB1) __sfr CTMUICON; 497 __at(0x0FB1) volatile __CTMUICONbits_t CTMUICONbits; 498 499 __at(0x0FB2) __sfr CTMUCONL; 500 __at(0x0FB2) volatile __CTMUCONLbits_t CTMUCONLbits; 501 502 __at(0x0FB3) __sfr CTMUCONH; 503 __at(0x0FB3) volatile __CTMUCONHbits_t CTMUCONHbits; 504 505 __at(0x0FB4) __sfr CCP2CON; 506 __at(0x0FB4) volatile __CCP2CONbits_t CCP2CONbits; 507 508 __at(0x0FB4) __sfr ECCP2CON; 509 __at(0x0FB4) volatile __ECCP2CONbits_t ECCP2CONbits; 510 511 __at(0x0FB5) __sfr CCPR2; 512 513 __at(0x0FB5) __sfr CCPR2L; 514 515 __at(0x0FB6) __sfr CCPR2H; 516 517 __at(0x0FB7) __sfr ECCP2DEL; 518 __at(0x0FB7) volatile __ECCP2DELbits_t ECCP2DELbits; 519 520 __at(0x0FB7) __sfr PWM2CON; 521 __at(0x0FB7) volatile __PWM2CONbits_t PWM2CONbits; 522 523 __at(0x0FB8) __sfr ECCP2AS; 524 __at(0x0FB8) volatile __ECCP2ASbits_t ECCP2ASbits; 525 526 __at(0x0FB9) __sfr PSTR2CON; 527 __at(0x0FB9) volatile __PSTR2CONbits_t PSTR2CONbits; 528 529 __at(0x0FBA) __sfr CCP1CON; 530 __at(0x0FBA) volatile __CCP1CONbits_t CCP1CONbits; 531 532 __at(0x0FBA) __sfr ECCP1CON; 533 __at(0x0FBA) volatile __ECCP1CONbits_t ECCP1CONbits; 534 535 __at(0x0FBB) __sfr CCPR1; 536 537 __at(0x0FBB) __sfr CCPR1L; 538 539 __at(0x0FBC) __sfr CCPR1H; 540 541 __at(0x0FBD) __sfr ECCP1DEL; 542 __at(0x0FBD) volatile __ECCP1DELbits_t ECCP1DELbits; 543 544 __at(0x0FBD) __sfr PWM1CON; 545 __at(0x0FBD) volatile __PWM1CONbits_t PWM1CONbits; 546 547 __at(0x0FBE) __sfr ECCP1AS; 548 __at(0x0FBE) volatile __ECCP1ASbits_t ECCP1ASbits; 549 550 __at(0x0FBF) __sfr PSTR1CON; 551 __at(0x0FBF) volatile __PSTR1CONbits_t PSTR1CONbits; 552 553 __at(0x0FC0) __sfr WDTCON; 554 __at(0x0FC0) volatile __WDTCONbits_t WDTCONbits; 555 556 __at(0x0FC1) __sfr ADCON1; 557 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits; 558 559 __at(0x0FC2) __sfr ADCON0; 560 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits; 561 562 __at(0x0FC3) __sfr ADRES; 563 564 __at(0x0FC3) __sfr ADRESL; 565 566 __at(0x0FC4) __sfr ADRESH; 567 568 __at(0x0FC5) __sfr SSP1CON2; 569 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits; 570 571 __at(0x0FC5) __sfr SSPCON2; 572 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits; 573 574 __at(0x0FC6) __sfr SSP1CON1; 575 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits; 576 577 __at(0x0FC6) __sfr SSPCON1; 578 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits; 579 580 __at(0x0FC7) __sfr SSP1STAT; 581 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits; 582 583 __at(0x0FC7) __sfr SSPSTAT; 584 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits; 585 586 __at(0x0FC8) __sfr SSP1ADD; 587 588 __at(0x0FC8) __sfr SSP1MSK; 589 __at(0x0FC8) volatile __SSP1MSKbits_t SSP1MSKbits; 590 591 __at(0x0FC8) __sfr SSPADD; 592 593 __at(0x0FC9) __sfr SSP1BUF; 594 595 __at(0x0FC9) __sfr SSPBUF; 596 597 __at(0x0FCA) __sfr T2CON; 598 __at(0x0FCA) volatile __T2CONbits_t T2CONbits; 599 600 __at(0x0FCB) __sfr PR2; 601 602 __at(0x0FCC) __sfr TMR2; 603 604 __at(0x0FCD) __sfr T1CON; 605 __at(0x0FCD) volatile __T1CONbits_t T1CONbits; 606 607 __at(0x0FCE) __sfr TMR1; 608 609 __at(0x0FCE) __sfr TMR1L; 610 611 __at(0x0FCF) __sfr TMR1H; 612 613 __at(0x0FD0) __sfr RCON; 614 __at(0x0FD0) volatile __RCONbits_t RCONbits; 615 616 __at(0x0FD1) __sfr CM2CON; 617 __at(0x0FD1) volatile __CM2CONbits_t CM2CONbits; 618 619 __at(0x0FD1) __sfr CM2CON1; 620 __at(0x0FD1) volatile __CM2CON1bits_t CM2CON1bits; 621 622 __at(0x0FD2) __sfr CM1CON; 623 __at(0x0FD2) volatile __CM1CONbits_t CM1CONbits; 624 625 __at(0x0FD2) __sfr CM1CON1; 626 __at(0x0FD2) volatile __CM1CON1bits_t CM1CON1bits; 627 628 __at(0x0FD3) __sfr OSCCON; 629 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits; 630 631 __at(0x0FD5) __sfr T0CON; 632 __at(0x0FD5) volatile __T0CONbits_t T0CONbits; 633 634 __at(0x0FD6) __sfr TMR0; 635 636 __at(0x0FD6) __sfr TMR0L; 637 638 __at(0x0FD7) __sfr TMR0H; 639 640 __at(0x0FD8) __sfr STATUS; 641 __at(0x0FD8) volatile __STATUSbits_t STATUSbits; 642 643 __at(0x0FD9) __sfr FSR2L; 644 645 __at(0x0FDA) __sfr FSR2H; 646 647 __at(0x0FDB) __sfr PLUSW2; 648 649 __at(0x0FDC) __sfr PREINC2; 650 651 __at(0x0FDD) __sfr POSTDEC2; 652 653 __at(0x0FDE) __sfr POSTINC2; 654 655 __at(0x0FDF) __sfr INDF2; 656 657 __at(0x0FE0) __sfr BSR; 658 659 __at(0x0FE1) __sfr FSR1L; 660 661 __at(0x0FE2) __sfr FSR1H; 662 663 __at(0x0FE3) __sfr PLUSW1; 664 665 __at(0x0FE4) __sfr PREINC1; 666 667 __at(0x0FE5) __sfr POSTDEC1; 668 669 __at(0x0FE6) __sfr POSTINC1; 670 671 __at(0x0FE7) __sfr INDF1; 672 673 __at(0x0FE8) __sfr WREG; 674 675 __at(0x0FE9) __sfr FSR0L; 676 677 __at(0x0FEA) __sfr FSR0H; 678 679 __at(0x0FEB) __sfr PLUSW0; 680 681 __at(0x0FEC) __sfr PREINC0; 682 683 __at(0x0FED) __sfr POSTDEC0; 684 685 __at(0x0FEE) __sfr POSTINC0; 686 687 __at(0x0FEF) __sfr INDF0; 688 689 __at(0x0FF0) __sfr INTCON3; 690 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits; 691 692 __at(0x0FF1) __sfr INTCON2; 693 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits; 694 695 __at(0x0FF2) __sfr INTCON; 696 __at(0x0FF2) volatile __INTCONbits_t INTCONbits; 697 698 __at(0x0FF3) __sfr PROD; 699 700 __at(0x0FF3) __sfr PRODL; 701 702 __at(0x0FF4) __sfr PRODH; 703 704 __at(0x0FF5) __sfr TABLAT; 705 706 __at(0x0FF6) __sfr TBLPTR; 707 708 __at(0x0FF6) __sfr TBLPTRL; 709 710 __at(0x0FF7) __sfr TBLPTRH; 711 712 __at(0x0FF8) __sfr TBLPTRU; 713 714 __at(0x0FF9) __sfr PC; 715 716 __at(0x0FF9) __sfr PCL; 717 718 __at(0x0FFA) __sfr PCLATH; 719 720 __at(0x0FFB) __sfr PCLATU; 721 722 __at(0x0FFC) __sfr STKPTR; 723 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits; 724 725 __at(0x0FFD) __sfr TOS; 726 727 __at(0x0FFD) __sfr TOSL; 728 729 __at(0x0FFE) __sfr TOSH; 730 731 __at(0x0FFF) __sfr TOSU; 732