1 /* 2 * This definitions of the PIC18LF6310 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:24:05 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic18lf6310.h> 26 27 //============================================================================== 28 29 __at(0x0F6B) __sfr RCSTA2; 30 __at(0x0F6B) volatile __RCSTA2bits_t RCSTA2bits; 31 32 __at(0x0F6C) __sfr TXSTA2; 33 __at(0x0F6C) volatile __TXSTA2bits_t TXSTA2bits; 34 35 __at(0x0F6D) __sfr TXREG2; 36 37 __at(0x0F6E) __sfr RCREG2; 38 39 __at(0x0F6F) __sfr SPBRG2; 40 41 __at(0x0F7E) __sfr BAUDCON1; 42 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits; 43 44 __at(0x0F7E) __sfr BAUDCTL1; 45 __at(0x0F7E) volatile __BAUDCTL1bits_t BAUDCTL1bits; 46 47 __at(0x0F7F) __sfr SPBRGH1; 48 49 __at(0x0F80) __sfr PORTA; 50 __at(0x0F80) volatile __PORTAbits_t PORTAbits; 51 52 __at(0x0F81) __sfr PORTB; 53 __at(0x0F81) volatile __PORTBbits_t PORTBbits; 54 55 __at(0x0F82) __sfr PORTC; 56 __at(0x0F82) volatile __PORTCbits_t PORTCbits; 57 58 __at(0x0F83) __sfr PORTD; 59 __at(0x0F83) volatile __PORTDbits_t PORTDbits; 60 61 __at(0x0F84) __sfr PORTE; 62 __at(0x0F84) volatile __PORTEbits_t PORTEbits; 63 64 __at(0x0F85) __sfr PORTF; 65 __at(0x0F85) volatile __PORTFbits_t PORTFbits; 66 67 __at(0x0F86) __sfr PORTG; 68 __at(0x0F86) volatile __PORTGbits_t PORTGbits; 69 70 __at(0x0F89) __sfr LATA; 71 __at(0x0F89) volatile __LATAbits_t LATAbits; 72 73 __at(0x0F8A) __sfr LATB; 74 __at(0x0F8A) volatile __LATBbits_t LATBbits; 75 76 __at(0x0F8B) __sfr LATC; 77 __at(0x0F8B) volatile __LATCbits_t LATCbits; 78 79 __at(0x0F8C) __sfr LATD; 80 __at(0x0F8C) volatile __LATDbits_t LATDbits; 81 82 __at(0x0F8D) __sfr LATE; 83 __at(0x0F8D) volatile __LATEbits_t LATEbits; 84 85 __at(0x0F8E) __sfr LATF; 86 __at(0x0F8E) volatile __LATFbits_t LATFbits; 87 88 __at(0x0F8F) __sfr LATG; 89 __at(0x0F8F) volatile __LATGbits_t LATGbits; 90 91 __at(0x0F92) __sfr DDRA; 92 __at(0x0F92) volatile __DDRAbits_t DDRAbits; 93 94 __at(0x0F92) __sfr TRISA; 95 __at(0x0F92) volatile __TRISAbits_t TRISAbits; 96 97 __at(0x0F93) __sfr DDRB; 98 __at(0x0F93) volatile __DDRBbits_t DDRBbits; 99 100 __at(0x0F93) __sfr TRISB; 101 __at(0x0F93) volatile __TRISBbits_t TRISBbits; 102 103 __at(0x0F94) __sfr DDRC; 104 __at(0x0F94) volatile __DDRCbits_t DDRCbits; 105 106 __at(0x0F94) __sfr TRISC; 107 __at(0x0F94) volatile __TRISCbits_t TRISCbits; 108 109 __at(0x0F95) __sfr DDRD; 110 __at(0x0F95) volatile __DDRDbits_t DDRDbits; 111 112 __at(0x0F95) __sfr TRISD; 113 __at(0x0F95) volatile __TRISDbits_t TRISDbits; 114 115 __at(0x0F96) __sfr DDRE; 116 __at(0x0F96) volatile __DDREbits_t DDREbits; 117 118 __at(0x0F96) __sfr TRISE; 119 __at(0x0F96) volatile __TRISEbits_t TRISEbits; 120 121 __at(0x0F97) __sfr DDRF; 122 __at(0x0F97) volatile __DDRFbits_t DDRFbits; 123 124 __at(0x0F97) __sfr TRISF; 125 __at(0x0F97) volatile __TRISFbits_t TRISFbits; 126 127 __at(0x0F98) __sfr DDRG; 128 __at(0x0F98) volatile __DDRGbits_t DDRGbits; 129 130 __at(0x0F98) __sfr TRISG; 131 __at(0x0F98) volatile __TRISGbits_t TRISGbits; 132 133 __at(0x0F9B) __sfr OSCTUNE; 134 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits; 135 136 __at(0x0F9D) __sfr PIE1; 137 __at(0x0F9D) volatile __PIE1bits_t PIE1bits; 138 139 __at(0x0F9E) __sfr PIR1; 140 __at(0x0F9E) volatile __PIR1bits_t PIR1bits; 141 142 __at(0x0F9F) __sfr IPR1; 143 __at(0x0F9F) volatile __IPR1bits_t IPR1bits; 144 145 __at(0x0FA0) __sfr PIE2; 146 __at(0x0FA0) volatile __PIE2bits_t PIE2bits; 147 148 __at(0x0FA1) __sfr PIR2; 149 __at(0x0FA1) volatile __PIR2bits_t PIR2bits; 150 151 __at(0x0FA2) __sfr IPR2; 152 __at(0x0FA2) volatile __IPR2bits_t IPR2bits; 153 154 __at(0x0FA3) __sfr PIE3; 155 __at(0x0FA3) volatile __PIE3bits_t PIE3bits; 156 157 __at(0x0FA4) __sfr PIR3; 158 __at(0x0FA4) volatile __PIR3bits_t PIR3bits; 159 160 __at(0x0FA5) __sfr IPR3; 161 __at(0x0FA5) volatile __IPR3bits_t IPR3bits; 162 163 __at(0x0FAB) __sfr RCSTA; 164 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits; 165 166 __at(0x0FAB) __sfr RCSTA1; 167 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits; 168 169 __at(0x0FAC) __sfr TXSTA; 170 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits; 171 172 __at(0x0FAC) __sfr TXSTA1; 173 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits; 174 175 __at(0x0FAD) __sfr TXREG; 176 177 __at(0x0FAD) __sfr TXREG1; 178 179 __at(0x0FAE) __sfr RCREG; 180 181 __at(0x0FAE) __sfr RCREG1; 182 183 __at(0x0FAF) __sfr SPBRG; 184 185 __at(0x0FAF) __sfr SPBRG1; 186 187 __at(0x0FB0) __sfr PSPCON; 188 __at(0x0FB0) volatile __PSPCONbits_t PSPCONbits; 189 190 __at(0x0FB1) __sfr T3CON; 191 __at(0x0FB1) volatile __T3CONbits_t T3CONbits; 192 193 __at(0x0FB2) __sfr TMR3; 194 195 __at(0x0FB2) __sfr TMR3L; 196 197 __at(0x0FB3) __sfr TMR3H; 198 199 __at(0x0FB4) __sfr CMCON; 200 __at(0x0FB4) volatile __CMCONbits_t CMCONbits; 201 202 __at(0x0FB5) __sfr CVRCON; 203 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits; 204 205 __at(0x0FB7) __sfr CCP3CON; 206 __at(0x0FB7) volatile __CCP3CONbits_t CCP3CONbits; 207 208 __at(0x0FB8) __sfr CCPR3; 209 210 __at(0x0FB8) __sfr CCPR3L; 211 212 __at(0x0FB9) __sfr CCPR3H; 213 214 __at(0x0FBA) __sfr CCP2CON; 215 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits; 216 217 __at(0x0FBB) __sfr CCPR2; 218 219 __at(0x0FBB) __sfr CCPR2L; 220 221 __at(0x0FBC) __sfr CCPR2H; 222 223 __at(0x0FBD) __sfr CCP1CON; 224 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits; 225 226 __at(0x0FBE) __sfr CCPR1; 227 228 __at(0x0FBE) __sfr CCPR1L; 229 230 __at(0x0FBF) __sfr CCPR1H; 231 232 __at(0x0FC0) __sfr ADCON2; 233 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits; 234 235 __at(0x0FC1) __sfr ADCON1; 236 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits; 237 238 __at(0x0FC2) __sfr ADCON0; 239 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits; 240 241 __at(0x0FC3) __sfr ADRES; 242 243 __at(0x0FC3) __sfr ADRESL; 244 245 __at(0x0FC4) __sfr ADRESH; 246 247 __at(0x0FC5) __sfr SSPCON2; 248 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits; 249 250 __at(0x0FC6) __sfr SSPCON1; 251 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits; 252 253 __at(0x0FC7) __sfr SSPSTAT; 254 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits; 255 256 __at(0x0FC8) __sfr SSPADD; 257 258 __at(0x0FC9) __sfr SSPBUF; 259 260 __at(0x0FCA) __sfr T2CON; 261 __at(0x0FCA) volatile __T2CONbits_t T2CONbits; 262 263 __at(0x0FCB) __sfr PR2; 264 265 __at(0x0FCC) __sfr TMR2; 266 267 __at(0x0FCD) __sfr T1CON; 268 __at(0x0FCD) volatile __T1CONbits_t T1CONbits; 269 270 __at(0x0FCE) __sfr TMR1; 271 272 __at(0x0FCE) __sfr TMR1L; 273 274 __at(0x0FCF) __sfr TMR1H; 275 276 __at(0x0FD0) __sfr RCON; 277 __at(0x0FD0) volatile __RCONbits_t RCONbits; 278 279 __at(0x0FD1) __sfr WDTCON; 280 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits; 281 282 __at(0x0FD2) __sfr HLVDCON; 283 __at(0x0FD2) volatile __HLVDCONbits_t HLVDCONbits; 284 285 __at(0x0FD2) __sfr LVDCON; 286 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits; 287 288 __at(0x0FD3) __sfr OSCCON; 289 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits; 290 291 __at(0x0FD5) __sfr T0CON; 292 __at(0x0FD5) volatile __T0CONbits_t T0CONbits; 293 294 __at(0x0FD6) __sfr TMR0; 295 296 __at(0x0FD6) __sfr TMR0L; 297 298 __at(0x0FD7) __sfr TMR0H; 299 300 __at(0x0FD8) __sfr STATUS; 301 __at(0x0FD8) volatile __STATUSbits_t STATUSbits; 302 303 __at(0x0FD9) __sfr FSR2L; 304 305 __at(0x0FDA) __sfr FSR2H; 306 307 __at(0x0FDB) __sfr PLUSW2; 308 309 __at(0x0FDC) __sfr PREINC2; 310 311 __at(0x0FDD) __sfr POSTDEC2; 312 313 __at(0x0FDE) __sfr POSTINC2; 314 315 __at(0x0FDF) __sfr INDF2; 316 317 __at(0x0FE0) __sfr BSR; 318 319 __at(0x0FE1) __sfr FSR1L; 320 321 __at(0x0FE2) __sfr FSR1H; 322 323 __at(0x0FE3) __sfr PLUSW1; 324 325 __at(0x0FE4) __sfr PREINC1; 326 327 __at(0x0FE5) __sfr POSTDEC1; 328 329 __at(0x0FE6) __sfr POSTINC1; 330 331 __at(0x0FE7) __sfr INDF1; 332 333 __at(0x0FE8) __sfr WREG; 334 335 __at(0x0FE9) __sfr FSR0L; 336 337 __at(0x0FEA) __sfr FSR0H; 338 339 __at(0x0FEB) __sfr PLUSW0; 340 341 __at(0x0FEC) __sfr PREINC0; 342 343 __at(0x0FED) __sfr POSTDEC0; 344 345 __at(0x0FEE) __sfr POSTINC0; 346 347 __at(0x0FEF) __sfr INDF0; 348 349 __at(0x0FF0) __sfr INTCON3; 350 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits; 351 352 __at(0x0FF1) __sfr INTCON2; 353 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits; 354 355 __at(0x0FF2) __sfr INTCON; 356 __at(0x0FF2) volatile __INTCONbits_t INTCONbits; 357 358 __at(0x0FF3) __sfr PROD; 359 360 __at(0x0FF3) __sfr PRODL; 361 362 __at(0x0FF4) __sfr PRODH; 363 364 __at(0x0FF5) __sfr TABLAT; 365 366 __at(0x0FF6) __sfr TBLPTR; 367 368 __at(0x0FF6) __sfr TBLPTRL; 369 370 __at(0x0FF7) __sfr TBLPTRH; 371 372 __at(0x0FF8) __sfr TBLPTRU; 373 374 __at(0x0FF9) __sfr PC; 375 376 __at(0x0FF9) __sfr PCL; 377 378 __at(0x0FFA) __sfr PCLATH; 379 380 __at(0x0FFB) __sfr PCLATU; 381 382 __at(0x0FFC) __sfr STKPTR; 383 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits; 384 385 __at(0x0FFD) __sfr TOS; 386 387 __at(0x0FFD) __sfr TOSL; 388 389 __at(0x0FFE) __sfr TOSH; 390 391 __at(0x0FFF) __sfr TOSU; 392