1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */
20
21 #include <stdio.h>
22 #include "ansidecl.h"
23 #include "opcode/ppc.h"
24
25 /* This file holds the PowerPC opcode table. The opcode table
26 includes almost all of the extended instruction mnemonics. This
27 permits the disassembler to use them, and simplifies the assembler
28 logic, at the cost of increasing the table size. The table is
29 strictly constant data, so the compiler should be able to put it in
30 the .text section.
31
32 This file also holds the operand table. All knowledge about
33 inserting operands into instructions and vice-versa is kept in this
34 file. */
35
36 /* Local insertion and extraction functions. */
37
38 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
39 static long extract_bat PARAMS ((unsigned long, int *));
40 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
41 static long extract_bba PARAMS ((unsigned long, int *));
42 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
43 static long extract_bd PARAMS ((unsigned long, int *));
44 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
45 static long extract_bdm PARAMS ((unsigned long, int *));
46 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
47 static long extract_bdp PARAMS ((unsigned long, int *));
48 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
49 static long extract_bo PARAMS ((unsigned long, int *));
50 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
51 static long extract_boe PARAMS ((unsigned long, int *));
52 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
53 static long extract_ds PARAMS ((unsigned long, int *));
54 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
55 static long extract_li PARAMS ((unsigned long, int *));
56 static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
57 static long extract_mbe PARAMS ((unsigned long, int *));
58 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
59 static long extract_mb6 PARAMS ((unsigned long, int *));
60 static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
61 static long extract_nb PARAMS ((unsigned long, int *));
62 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
63 static long extract_nsi PARAMS ((unsigned long, int *));
64 static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
65 static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
66 static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
67 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
68 static long extract_rbs PARAMS ((unsigned long, int *));
69 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
70 static long extract_sh6 PARAMS ((unsigned long, int *));
71 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
72 static long extract_spr PARAMS ((unsigned long, int *));
73 static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
74 static long extract_tbr PARAMS ((unsigned long, int *));
75
76 /* The operands table.
77
78 The fields are bits, shift, signed, insert, extract, flags. */
79
80 const struct powerpc_operand powerpc_operands[] =
81 {
82 /* The zero index is used to indicate the end of the list of
83 operands. */
84 #define UNUSED (0)
85 { 0, 0, 0, 0, 0 },
86
87 /* The BA field in an XL form instruction. */
88 #define BA (UNUSED + 1)
89 #define BA_MASK (0x1f << 16)
90 { 5, 16, 0, 0, PPC_OPERAND_CR },
91
92 /* The BA field in an XL form instruction when it must be the same
93 as the BT field in the same instruction. */
94 #define BAT (BA + 1)
95 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
96
97 /* The BB field in an XL form instruction. */
98 #define BB (BAT + 1)
99 #define BB_MASK (0x1f << 11)
100 { 5, 11, 0, 0, PPC_OPERAND_CR },
101
102 /* The BB field in an XL form instruction when it must be the same
103 as the BA field in the same instruction. */
104 #define BBA (BB + 1)
105 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
106
107 /* The BD field in a B form instruction. The lower two bits are
108 forced to zero. */
109 #define BD (BBA + 1)
110 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
111
112 /* The BD field in a B form instruction when absolute addressing is
113 used. */
114 #define BDA (BD + 1)
115 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
116
117 /* The BD field in a B form instruction when the - modifier is used.
118 This sets the y bit of the BO field appropriately. */
119 #define BDM (BDA + 1)
120 { 16, 0, insert_bdm, extract_bdm,
121 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
122
123 /* The BD field in a B form instruction when the - modifier is used
124 and absolute address is used. */
125 #define BDMA (BDM + 1)
126 { 16, 0, insert_bdm, extract_bdm,
127 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
128
129 /* The BD field in a B form instruction when the + modifier is used.
130 This sets the y bit of the BO field appropriately. */
131 #define BDP (BDMA + 1)
132 { 16, 0, insert_bdp, extract_bdp,
133 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
134
135 /* The BD field in a B form instruction when the + modifier is used
136 and absolute addressing is used. */
137 #define BDPA (BDP + 1)
138 { 16, 0, insert_bdp, extract_bdp,
139 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
140
141 /* The BF field in an X or XL form instruction. */
142 #define BF (BDPA + 1)
143 { 3, 23, 0, 0, PPC_OPERAND_CR },
144
145 /* An optional BF field. This is used for comparison instructions,
146 in which an omitted BF field is taken as zero. */
147 #define OBF (BF + 1)
148 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
149
150 /* The BFA field in an X or XL form instruction. */
151 #define BFA (OBF + 1)
152 { 3, 18, 0, 0, PPC_OPERAND_CR },
153
154 /* The BI field in a B form or XL form instruction. */
155 #define BI (BFA + 1)
156 #define BI_MASK (0x1f << 16)
157 { 5, 16, 0, 0, PPC_OPERAND_CR },
158
159 /* The BO field in a B form instruction. Certain values are
160 illegal. */
161 #define BO (BI + 1)
162 #define BO_MASK (0x1f << 21)
163 { 5, 21, insert_bo, extract_bo, 0 },
164
165 /* The BO field in a B form instruction when the + or - modifier is
166 used. This is like the BO field, but it must be even. */
167 #define BOE (BO + 1)
168 { 5, 21, insert_boe, extract_boe, 0 },
169
170 /* The BT field in an X or XL form instruction. */
171 #define BT (BOE + 1)
172 { 5, 21, 0, 0, PPC_OPERAND_CR },
173
174 /* The condition register number portion of the BI field in a B form
175 or XL form instruction. This is used for the extended
176 conditional branch mnemonics, which set the lower two bits of the
177 BI field. This field is optional. */
178 #define CR (BT + 1)
179 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
180
181 /* The D field in a D form instruction. This is a displacement off
182 a register, and implies that the next operand is a register in
183 parentheses. */
184 #define D (CR + 1)
185 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
186
187 /* The DS field in a DS form instruction. This is like D, but the
188 lower two bits are forced to zero. */
189 #define DS (D + 1)
190 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
191
192 /* The FL1 field in a POWER SC form instruction. */
193 #define FL1 (DS + 1)
194 { 4, 12, 0, 0, 0 },
195
196 /* The FL2 field in a POWER SC form instruction. */
197 #define FL2 (FL1 + 1)
198 { 3, 2, 0, 0, 0 },
199
200 /* The FLM field in an XFL form instruction. */
201 #define FLM (FL2 + 1)
202 { 8, 17, 0, 0, 0 },
203
204 /* The FRA field in an X or A form instruction. */
205 #define FRA (FLM + 1)
206 #define FRA_MASK (0x1f << 16)
207 { 5, 16, 0, 0, PPC_OPERAND_FPR },
208
209 /* The FRB field in an X or A form instruction. */
210 #define FRB (FRA + 1)
211 #define FRB_MASK (0x1f << 11)
212 { 5, 11, 0, 0, PPC_OPERAND_FPR },
213
214 /* The FRC field in an A form instruction. */
215 #define FRC (FRB + 1)
216 #define FRC_MASK (0x1f << 6)
217 { 5, 6, 0, 0, PPC_OPERAND_FPR },
218
219 /* The FRS field in an X form instruction or the FRT field in a D, X
220 or A form instruction. */
221 #define FRS (FRC + 1)
222 #define FRT (FRS)
223 { 5, 21, 0, 0, PPC_OPERAND_FPR },
224
225 /* The FXM field in an XFX instruction. */
226 #define FXM (FRS + 1)
227 #define FXM_MASK (0xff << 12)
228 { 8, 12, 0, 0, 0 },
229
230 /* The L field in a D or X form instruction. */
231 #define L (FXM + 1)
232 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
233
234 /* The LEV field in a POWER SC form instruction. */
235 #define LEV (L + 1)
236 { 7, 5, 0, 0, 0 },
237
238 /* The LI field in an I form instruction. The lower two bits are
239 forced to zero. */
240 #define LI (LEV + 1)
241 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
242
243 /* The LI field in an I form instruction when used as an absolute
244 address. */
245 #define LIA (LI + 1)
246 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
247
248 /* The MB field in an M form instruction. */
249 #define MB (LIA + 1)
250 #define MB_MASK (0x1f << 6)
251 { 5, 6, 0, 0, 0 },
252
253 /* The ME field in an M form instruction. */
254 #define ME (MB + 1)
255 #define ME_MASK (0x1f << 1)
256 { 5, 1, 0, 0, 0 },
257
258 /* The MB and ME fields in an M form instruction expressed a single
259 operand which is a bitmask indicating which bits to select. This
260 is a two operand form using PPC_OPERAND_NEXT. See the
261 description in opcode/ppc.h for what this means. */
262 #define MBE (ME + 1)
263 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
264 { 32, 0, insert_mbe, extract_mbe, 0 },
265
266 /* The MB or ME field in an MD or MDS form instruction. The high
267 bit is wrapped to the low end. */
268 #define MB6 (MBE + 2)
269 #define ME6 (MB6)
270 #define MB6_MASK (0x3f << 5)
271 { 6, 5, insert_mb6, extract_mb6, 0 },
272
273 /* The NB field in an X form instruction. The value 32 is stored as
274 0. */
275 #define NB (MB6 + 1)
276 { 6, 11, insert_nb, extract_nb, 0 },
277
278 /* The NSI field in a D form instruction. This is the same as the
279 SI field, only negated. */
280 #define NSI (NB + 1)
281 { 16, 0, insert_nsi, extract_nsi,
282 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
283
284 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
285 #define RA (NSI + 1)
286 #define RA_MASK (0x1f << 16)
287 { 5, 16, 0, 0, PPC_OPERAND_GPR },
288
289 /* The RA field in a D or X form instruction which is an updating
290 load, which means that the RA field may not be zero and may not
291 equal the RT field. */
292 #define RAL (RA + 1)
293 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
294
295 /* The RA field in an lmw instruction, which has special value
296 restrictions. */
297 #define RAM (RAL + 1)
298 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
299
300 /* The RA field in a D or X form instruction which is an updating
301 store or an updating floating point load, which means that the RA
302 field may not be zero. */
303 #define RAS (RAM + 1)
304 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
305
306 /* The RB field in an X, XO, M, or MDS form instruction. */
307 #define RB (RAS + 1)
308 #define RB_MASK (0x1f << 11)
309 { 5, 11, 0, 0, PPC_OPERAND_GPR },
310
311 /* The RB field in an X form instruction when it must be the same as
312 the RS field in the instruction. This is used for extended
313 mnemonics like mr. */
314 #define RBS (RB + 1)
315 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
316
317 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
318 instruction or the RT field in a D, DS, X, XFX or XO form
319 instruction. */
320 #define RS (RBS + 1)
321 #define RT (RS)
322 #define RT_MASK (0x1f << 21)
323 { 5, 21, 0, 0, PPC_OPERAND_GPR },
324
325 /* The SH field in an X or M form instruction. */
326 #define SH (RS + 1)
327 #define SH_MASK (0x1f << 11)
328 { 5, 11, 0, 0, 0 },
329
330 /* The SH field in an MD form instruction. This is split. */
331 #define SH6 (SH + 1)
332 #define SH6_MASK ((0x1f << 11) | (1 << 1))
333 { 6, 1, insert_sh6, extract_sh6, 0 },
334
335 /* The SI field in a D form instruction. */
336 #define SI (SH6 + 1)
337 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
338
339 /* The SI field in a D form instruction when we accept a wide range
340 of positive values. */
341 #define SISIGNOPT (SI + 1)
342 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
343
344 /* The SPR field in an XFX form instruction. This is flipped--the
345 lower 5 bits are stored in the upper 5 and vice- versa. */
346 #define SPR (SISIGNOPT + 1)
347 #define SPR_MASK (0x3ff << 11)
348 { 10, 11, insert_spr, extract_spr, 0 },
349
350 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
351 #define SPRBAT (SPR + 1)
352 #define SPRBAT_MASK (0x3 << 17)
353 { 2, 17, 0, 0, 0 },
354
355 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
356 #define SPRG (SPRBAT + 1)
357 #define SPRG_MASK (0x3 << 16)
358 { 2, 16, 0, 0, 0 },
359
360 /* The SR field in an X form instruction. */
361 #define SR (SPRG + 1)
362 { 4, 16, 0, 0, 0 },
363
364 /* The SV field in a POWER SC form instruction. */
365 #define SV (SR + 1)
366 { 14, 2, 0, 0, 0 },
367
368 /* The TBR field in an XFX form instruction. This is like the SPR
369 field, but it is optional. */
370 #define TBR (SV + 1)
371 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
372
373 /* The TO field in a D or X form instruction. */
374 #define TO (TBR + 1)
375 #define TO_MASK (0x1f << 21)
376 { 5, 21, 0, 0, 0 },
377
378 /* The U field in an X form instruction. */
379 #define U (TO + 1)
380 { 4, 12, 0, 0, 0 },
381
382 /* The UI field in a D form instruction. */
383 #define UI (U + 1)
384 { 16, 0, 0, 0, 0 },
385 };
386
387 /* The functions used to insert and extract complicated operands. */
388
389 /* The BA field in an XL form instruction when it must be the same as
390 the BT field in the same instruction. This operand is marked FAKE.
391 The insertion function just copies the BT field into the BA field,
392 and the extraction function just checks that the fields are the
393 same. */
394
395 /*ARGSUSED*/
396 static unsigned long
insert_bat(insn,value,errmsg)397 insert_bat (insn, value, errmsg)
398 unsigned long insn;
399 long value;
400 const char **errmsg;
401 {
402 return insn | (((insn >> 21) & 0x1f) << 16);
403 }
404
405 static long
extract_bat(insn,invalid)406 extract_bat (insn, invalid)
407 unsigned long insn;
408 int *invalid;
409 {
410 if (invalid != (int *) NULL
411 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
412 *invalid = 1;
413 return 0;
414 }
415
416 /* The BB field in an XL form instruction when it must be the same as
417 the BA field in the same instruction. This operand is marked FAKE.
418 The insertion function just copies the BA field into the BB field,
419 and the extraction function just checks that the fields are the
420 same. */
421
422 /*ARGSUSED*/
423 static unsigned long
insert_bba(insn,value,errmsg)424 insert_bba (insn, value, errmsg)
425 unsigned long insn;
426 long value;
427 const char **errmsg;
428 {
429 return insn | (((insn >> 16) & 0x1f) << 11);
430 }
431
432 static long
extract_bba(insn,invalid)433 extract_bba (insn, invalid)
434 unsigned long insn;
435 int *invalid;
436 {
437 if (invalid != (int *) NULL
438 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
439 *invalid = 1;
440 return 0;
441 }
442
443 /* The BD field in a B form instruction. The lower two bits are
444 forced to zero. */
445
446 /*ARGSUSED*/
447 static unsigned long
insert_bd(insn,value,errmsg)448 insert_bd (insn, value, errmsg)
449 unsigned long insn;
450 long value;
451 const char **errmsg;
452 {
453 return insn | (value & 0xfffc);
454 }
455
456 /*ARGSUSED*/
457 static long
extract_bd(insn,invalid)458 extract_bd (insn, invalid)
459 unsigned long insn;
460 int *invalid;
461 {
462 if ((insn & 0x8000) != 0)
463 return (insn & 0xfffc) - 0x10000;
464 else
465 return insn & 0xfffc;
466 }
467
468 /* The BD field in a B form instruction when the - modifier is used.
469 This modifier means that the branch is not expected to be taken.
470 We must set the y bit of the BO field to 1 if the offset is
471 negative. When extracting, we require that the y bit be 1 and that
472 the offset be positive, since if the y bit is 0 we just want to
473 print the normal form of the instruction. */
474
475 /*ARGSUSED*/
476 static unsigned long
insert_bdm(insn,value,errmsg)477 insert_bdm (insn, value, errmsg)
478 unsigned long insn;
479 long value;
480 const char **errmsg;
481 {
482 if ((value & 0x8000) != 0)
483 insn |= 1 << 21;
484 return insn | (value & 0xfffc);
485 }
486
487 static long
extract_bdm(insn,invalid)488 extract_bdm (insn, invalid)
489 unsigned long insn;
490 int *invalid;
491 {
492 if (invalid != (int *) NULL
493 && ((insn & (1 << 21)) == 0
494 || (insn & (1 << 15)) == 0))
495 *invalid = 1;
496 if ((insn & 0x8000) != 0)
497 return (insn & 0xfffc) - 0x10000;
498 else
499 return insn & 0xfffc;
500 }
501
502 /* The BD field in a B form instruction when the + modifier is used.
503 This is like BDM, above, except that the branch is expected to be
504 taken. */
505
506 /*ARGSUSED*/
507 static unsigned long
insert_bdp(insn,value,errmsg)508 insert_bdp (insn, value, errmsg)
509 unsigned long insn;
510 long value;
511 const char **errmsg;
512 {
513 if ((value & 0x8000) == 0)
514 insn |= 1 << 21;
515 return insn | (value & 0xfffc);
516 }
517
518 static long
extract_bdp(insn,invalid)519 extract_bdp (insn, invalid)
520 unsigned long insn;
521 int *invalid;
522 {
523 if (invalid != (int *) NULL
524 && ((insn & (1 << 21)) == 0
525 || (insn & (1 << 15)) != 0))
526 *invalid = 1;
527 if ((insn & 0x8000) != 0)
528 return (insn & 0xfffc) - 0x10000;
529 else
530 return insn & 0xfffc;
531 }
532
533 /* Check for legal values of a BO field. */
534
535 static int
valid_bo(value)536 valid_bo (value)
537 long value;
538 {
539 /* Certain encodings have bits that are required to be zero. These
540 are (z must be zero, y may be anything):
541 001zy
542 011zy
543 1z00y
544 1z01y
545 1z1zz
546 */
547 switch (value & 0x14)
548 {
549 default:
550 case 0:
551 return 1;
552 case 0x4:
553 return (value & 0x2) == 0;
554 case 0x10:
555 return (value & 0x8) == 0;
556 case 0x14:
557 return value == 0x14;
558 }
559 }
560
561 /* The BO field in a B form instruction. Warn about attempts to set
562 the field to an illegal value. */
563
564 static unsigned long
insert_bo(insn,value,errmsg)565 insert_bo (insn, value, errmsg)
566 unsigned long insn;
567 long value;
568 const char **errmsg;
569 {
570 if (errmsg != (const char **) NULL
571 && ! valid_bo (value))
572 *errmsg = "invalid conditional option";
573 return insn | ((value & 0x1f) << 21);
574 }
575
576 static long
extract_bo(insn,invalid)577 extract_bo (insn, invalid)
578 unsigned long insn;
579 int *invalid;
580 {
581 long value;
582
583 value = (insn >> 21) & 0x1f;
584 if (invalid != (int *) NULL
585 && ! valid_bo (value))
586 *invalid = 1;
587 return value;
588 }
589
590 /* The BO field in a B form instruction when the + or - modifier is
591 used. This is like the BO field, but it must be even. When
592 extracting it, we force it to be even. */
593
594 static unsigned long
insert_boe(insn,value,errmsg)595 insert_boe (insn, value, errmsg)
596 unsigned long insn;
597 long value;
598 const char **errmsg;
599 {
600 if (errmsg != (const char **) NULL)
601 {
602 if (! valid_bo (value))
603 *errmsg = "invalid conditional option";
604 else if ((value & 1) != 0)
605 *errmsg = "attempt to set y bit when using + or - modifier";
606 }
607 return insn | ((value & 0x1f) << 21);
608 }
609
610 static long
extract_boe(insn,invalid)611 extract_boe (insn, invalid)
612 unsigned long insn;
613 int *invalid;
614 {
615 long value;
616
617 value = (insn >> 21) & 0x1f;
618 if (invalid != (int *) NULL
619 && ! valid_bo (value))
620 *invalid = 1;
621 return value & 0x1e;
622 }
623
624 /* The DS field in a DS form instruction. This is like D, but the
625 lower two bits are forced to zero. */
626
627 /*ARGSUSED*/
628 static unsigned long
insert_ds(insn,value,errmsg)629 insert_ds (insn, value, errmsg)
630 unsigned long insn;
631 long value;
632 const char **errmsg;
633 {
634 return insn | (value & 0xfffc);
635 }
636
637 /*ARGSUSED*/
638 static long
extract_ds(insn,invalid)639 extract_ds (insn, invalid)
640 unsigned long insn;
641 int *invalid;
642 {
643 if ((insn & 0x8000) != 0)
644 return (insn & 0xfffc) - 0x10000;
645 else
646 return insn & 0xfffc;
647 }
648
649 /* The LI field in an I form instruction. The lower two bits are
650 forced to zero. */
651
652 /*ARGSUSED*/
653 static unsigned long
insert_li(insn,value,errmsg)654 insert_li (insn, value, errmsg)
655 unsigned long insn;
656 long value;
657 const char **errmsg;
658 {
659 return insn | (value & 0x3fffffc);
660 }
661
662 /*ARGSUSED*/
663 static long
extract_li(insn,invalid)664 extract_li (insn, invalid)
665 unsigned long insn;
666 int *invalid;
667 {
668 if ((insn & 0x2000000) != 0)
669 return (insn & 0x3fffffc) - 0x4000000;
670 else
671 return insn & 0x3fffffc;
672 }
673
674 /* The MB and ME fields in an M form instruction expressed as a single
675 operand which is itself a bitmask. The extraction function always
676 marks it as invalid, since we never want to recognize an
677 instruction which uses a field of this type. */
678
679 static unsigned long
insert_mbe(insn,value,errmsg)680 insert_mbe (insn, value, errmsg)
681 unsigned long insn;
682 long value;
683 const char **errmsg;
684 {
685 unsigned long uval;
686 int mb, me;
687
688 uval = value;
689
690 if (uval == 0)
691 {
692 if (errmsg != (const char **) NULL)
693 *errmsg = "illegal bitmask";
694 return insn;
695 }
696
697 me = 31;
698 while ((uval & 1) == 0)
699 {
700 uval >>= 1;
701 --me;
702 }
703
704 mb = me;
705 uval >>= 1;
706 while ((uval & 1) != 0)
707 {
708 uval >>= 1;
709 --mb;
710 }
711
712 if (uval != 0)
713 {
714 if (errmsg != (const char **) NULL)
715 *errmsg = "illegal bitmask";
716 }
717
718 return insn | (mb << 6) | (me << 1);
719 }
720
721 static long
extract_mbe(insn,invalid)722 extract_mbe (insn, invalid)
723 unsigned long insn;
724 int *invalid;
725 {
726 long ret;
727 int mb, me;
728 int i;
729
730 if (invalid != (int *) NULL)
731 *invalid = 1;
732
733 ret = 0;
734 mb = (insn >> 6) & 0x1f;
735 me = (insn >> 1) & 0x1f;
736 for (i = mb; i < me; i++)
737 ret |= 1 << (31 - i);
738 return ret;
739 }
740
741 /* The MB or ME field in an MD or MDS form instruction. The high bit
742 is wrapped to the low end. */
743
744 /*ARGSUSED*/
745 static unsigned long
insert_mb6(insn,value,errmsg)746 insert_mb6 (insn, value, errmsg)
747 unsigned long insn;
748 long value;
749 const char **errmsg;
750 {
751 return insn | ((value & 0x1f) << 6) | (value & 0x20);
752 }
753
754 /*ARGSUSED*/
755 static long
extract_mb6(insn,invalid)756 extract_mb6 (insn, invalid)
757 unsigned long insn;
758 int *invalid;
759 {
760 return ((insn >> 6) & 0x1f) | (insn & 0x20);
761 }
762
763 /* The NB field in an X form instruction. The value 32 is stored as
764 0. */
765
766 static unsigned long
insert_nb(insn,value,errmsg)767 insert_nb (insn, value, errmsg)
768 unsigned long insn;
769 long value;
770 const char **errmsg;
771 {
772 if (value < 0 || value > 32)
773 *errmsg = "value out of range";
774 if (value == 32)
775 value = 0;
776 return insn | ((value & 0x1f) << 11);
777 }
778
779 /*ARGSUSED*/
780 static long
extract_nb(insn,invalid)781 extract_nb (insn, invalid)
782 unsigned long insn;
783 int *invalid;
784 {
785 long ret;
786
787 ret = (insn >> 11) & 0x1f;
788 if (ret == 0)
789 ret = 32;
790 return ret;
791 }
792
793 /* The NSI field in a D form instruction. This is the same as the SI
794 field, only negated. The extraction function always marks it as
795 invalid, since we never want to recognize an instruction which uses
796 a field of this type. */
797
798 /*ARGSUSED*/
799 static unsigned long
insert_nsi(insn,value,errmsg)800 insert_nsi (insn, value, errmsg)
801 unsigned long insn;
802 long value;
803 const char **errmsg;
804 {
805 return insn | ((- value) & 0xffff);
806 }
807
808 static long
extract_nsi(insn,invalid)809 extract_nsi (insn, invalid)
810 unsigned long insn;
811 int *invalid;
812 {
813 if (invalid != (int *) NULL)
814 *invalid = 1;
815 if ((insn & 0x8000) != 0)
816 return - ((insn & 0xffff) - 0x10000);
817 else
818 return - (insn & 0xffff);
819 }
820
821 /* The RA field in a D or X form instruction which is an updating
822 load, which means that the RA field may not be zero and may not
823 equal the RT field. */
824
825 static unsigned long
insert_ral(insn,value,errmsg)826 insert_ral (insn, value, errmsg)
827 unsigned long insn;
828 long value;
829 const char **errmsg;
830 {
831 if (value == 0
832 || value == ((insn >> 21) & 0x1f))
833 *errmsg = "invalid register operand when updating";
834 return insn | ((value & 0x1f) << 16);
835 }
836
837 /* The RA field in an lmw instruction, which has special value
838 restrictions. */
839
840 static unsigned long
insert_ram(insn,value,errmsg)841 insert_ram (insn, value, errmsg)
842 unsigned long insn;
843 long value;
844 const char **errmsg;
845 {
846 if (value >= ((insn >> 21) & 0x1f))
847 *errmsg = "index register in load range";
848 return insn | ((value & 0x1f) << 16);
849 }
850
851 /* The RA field in a D or X form instruction which is an updating
852 store or an updating floating point load, which means that the RA
853 field may not be zero. */
854
855 static unsigned long
insert_ras(insn,value,errmsg)856 insert_ras (insn, value, errmsg)
857 unsigned long insn;
858 long value;
859 const char **errmsg;
860 {
861 if (value == 0)
862 *errmsg = "invalid register operand when updating";
863 return insn | ((value & 0x1f) << 16);
864 }
865
866 /* The RB field in an X form instruction when it must be the same as
867 the RS field in the instruction. This is used for extended
868 mnemonics like mr. This operand is marked FAKE. The insertion
869 function just copies the BT field into the BA field, and the
870 extraction function just checks that the fields are the same. */
871
872 /*ARGSUSED*/
873 static unsigned long
insert_rbs(insn,value,errmsg)874 insert_rbs (insn, value, errmsg)
875 unsigned long insn;
876 long value;
877 const char **errmsg;
878 {
879 return insn | (((insn >> 21) & 0x1f) << 11);
880 }
881
882 static long
extract_rbs(insn,invalid)883 extract_rbs (insn, invalid)
884 unsigned long insn;
885 int *invalid;
886 {
887 if (invalid != (int *) NULL
888 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
889 *invalid = 1;
890 return 0;
891 }
892
893 /* The SH field in an MD form instruction. This is split. */
894
895 /*ARGSUSED*/
896 static unsigned long
insert_sh6(insn,value,errmsg)897 insert_sh6 (insn, value, errmsg)
898 unsigned long insn;
899 long value;
900 const char **errmsg;
901 {
902 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
903 }
904
905 /*ARGSUSED*/
906 static long
extract_sh6(insn,invalid)907 extract_sh6 (insn, invalid)
908 unsigned long insn;
909 int *invalid;
910 {
911 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
912 }
913
914 /* The SPR field in an XFX form instruction. This is flipped--the
915 lower 5 bits are stored in the upper 5 and vice- versa. */
916
917 static unsigned long
insert_spr(insn,value,errmsg)918 insert_spr (insn, value, errmsg)
919 unsigned long insn;
920 long value;
921 const char **errmsg;
922 {
923 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
924 }
925
926 static long
extract_spr(insn,invalid)927 extract_spr (insn, invalid)
928 unsigned long insn;
929 int *invalid;
930 {
931 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
932 }
933
934 /* The TBR field in an XFX instruction. This is just like SPR, but it
935 is optional. When TBR is omitted, it must be inserted as 268 (the
936 magic number of the TB register). These functions treat 0
937 (indicating an omitted optional operand) as 268. This means that
938 ``mftb 4,0'' is not handled correctly. This does not matter very
939 much, since the architecture manual does not define mftb as
940 accepting any values other than 268 or 269. */
941
942 #define TB (268)
943
944 static unsigned long
insert_tbr(insn,value,errmsg)945 insert_tbr (insn, value, errmsg)
946 unsigned long insn;
947 long value;
948 const char **errmsg;
949 {
950 if (value == 0)
951 value = TB;
952 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
953 }
954
955 static long
extract_tbr(insn,invalid)956 extract_tbr (insn, invalid)
957 unsigned long insn;
958 int *invalid;
959 {
960 long ret;
961
962 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
963 if (ret == TB)
964 ret = 0;
965 return ret;
966 }
967
968 /* Macros used to form opcodes. */
969
970 /* The main opcode. */
971 #define OP(x) (((x) & 0x3f) << 26)
972 #define OP_MASK OP (0x3f)
973
974 /* The main opcode combined with a trap code in the TO field of a D
975 form instruction. Used for extended mnemonics for the trap
976 instructions. */
977 #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
978 #define OPTO_MASK (OP_MASK | TO_MASK)
979
980 /* The main opcode combined with a comparison size bit in the L field
981 of a D form or X form instruction. Used for extended mnemonics for
982 the comparison instructions. */
983 #define OPL(x,l) (OP (x) | (((l) & 1) << 21))
984 #define OPL_MASK OPL (0x3f,1)
985
986 /* An A form instruction. */
987 #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
988 #define A_MASK A (0x3f, 0x1f, 1)
989
990 /* An A_MASK with the FRB field fixed. */
991 #define AFRB_MASK (A_MASK | FRB_MASK)
992
993 /* An A_MASK with the FRC field fixed. */
994 #define AFRC_MASK (A_MASK | FRC_MASK)
995
996 /* An A_MASK with the FRA and FRC fields fixed. */
997 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
998
999 /* A B form instruction. */
1000 #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
1001 #define B_MASK B (0x3f, 1, 1)
1002
1003 /* A B form instruction setting the BO field. */
1004 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
1005 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1006
1007 /* A BBO_MASK with the y bit of the BO field removed. This permits
1008 matching a conditional branch regardless of the setting of the y
1009 bit. */
1010 #define Y_MASK (1 << 21)
1011 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1012
1013 /* A B form instruction setting the BO field and the condition bits of
1014 the BI field. */
1015 #define BBOCB(op, bo, cb, aa, lk) \
1016 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
1017 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1018
1019 /* A BBOCB_MASK with the y bit of the BO field removed. */
1020 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1021
1022 /* A BBOYCB_MASK in which the BI field is fixed. */
1023 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1024
1025 /* The main opcode mask with the RA field clear. */
1026 #define DRA_MASK (OP_MASK | RA_MASK)
1027
1028 /* A DS form instruction. */
1029 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1030 #define DS_MASK DSO (0x3f, 3)
1031
1032 /* An M form instruction. */
1033 #define M(op, rc) (OP (op) | ((rc) & 1))
1034 #define M_MASK M (0x3f, 1)
1035
1036 /* An M form instruction with the ME field specified. */
1037 #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
1038
1039 /* An M_MASK with the MB and ME fields fixed. */
1040 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1041
1042 /* An M_MASK with the SH and ME fields fixed. */
1043 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1044
1045 /* An MD form instruction. */
1046 #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
1047 #define MD_MASK MD (0x3f, 0x7, 1)
1048
1049 /* An MD_MASK with the MB field fixed. */
1050 #define MDMB_MASK (MD_MASK | MB6_MASK)
1051
1052 /* An MD_MASK with the SH field fixed. */
1053 #define MDSH_MASK (MD_MASK | SH6_MASK)
1054
1055 /* An MDS form instruction. */
1056 #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
1057 #define MDS_MASK MDS (0x3f, 0xf, 1)
1058
1059 /* An MDS_MASK with the MB field fixed. */
1060 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1061
1062 /* An SC form instruction. */
1063 #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
1064 #define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
1065
1066 /* An X form instruction. */
1067 #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1068
1069 /* An X form instruction with the RC bit specified. */
1070 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1071
1072 /* The mask for an X form instruction. */
1073 #define X_MASK XRC (0x3f, 0x3ff, 1)
1074
1075 /* An X_MASK with the RA field fixed. */
1076 #define XRA_MASK (X_MASK | RA_MASK)
1077
1078 /* An X_MASK with the RB field fixed. */
1079 #define XRB_MASK (X_MASK | RB_MASK)
1080
1081 /* An X_MASK with the RT field fixed. */
1082 #define XRT_MASK (X_MASK | RT_MASK)
1083
1084 /* An X_MASK with the RA and RB fields fixed. */
1085 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1086
1087 /* An X_MASK with the RT and RA fields fixed. */
1088 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1089
1090 /* An X form comparison instruction. */
1091 #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
1092
1093 /* The mask for an X form comparison instruction. */
1094 #define XCMP_MASK (X_MASK | (1 << 22))
1095
1096 /* The mask for an X form comparison instruction with the L field
1097 fixed. */
1098 #define XCMPL_MASK (XCMP_MASK | (1 << 21))
1099
1100 /* An X form trap instruction with the TO field specified. */
1101 #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1102 #define XTO_MASK (X_MASK | TO_MASK)
1103
1104 /* An XFL form instruction. */
1105 #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1106 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1107
1108 /* An XL form instruction with the LK field set to 0. */
1109 #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1110
1111 /* An XL form instruction which uses the LK field. */
1112 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1113
1114 /* The mask for an XL form instruction. */
1115 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1116
1117 /* An XL form instruction which explicitly sets the BO field. */
1118 #define XLO(op, bo, xop, lk) \
1119 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1120 #define XLO_MASK (XL_MASK | BO_MASK)
1121
1122 /* An XL form instruction which explicitly sets the y bit of the BO
1123 field. */
1124 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1125 #define XLYLK_MASK (XL_MASK | Y_MASK)
1126
1127 /* An XL form instruction which sets the BO field and the condition
1128 bits of the BI field. */
1129 #define XLOCB(op, bo, cb, xop, lk) \
1130 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1131 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1132
1133 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1134 #define XLBB_MASK (XL_MASK | BB_MASK)
1135 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1136 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1137
1138 /* An XL_MASK with the BO and BB fields fixed. */
1139 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1140
1141 /* An XL_MASK with the BO, BI and BB fields fixed. */
1142 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1143
1144 /* An XO form instruction. */
1145 #define XO(op, xop, oe, rc) \
1146 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1147 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1148
1149 /* An XO_MASK with the RB field fixed. */
1150 #define XORB_MASK (XO_MASK | RB_MASK)
1151
1152 /* An XS form instruction. */
1153 #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1154 #define XS_MASK XS (0x3f, 0x1ff, 1)
1155
1156 /* A mask for the FXM version of an XFX form instruction. */
1157 #define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
1158
1159 /* An XFX form instruction with the FXM field filled in. */
1160 #define XFXM(op, xop, fxm) \
1161 (X ((op), (xop)) | (((fxm) & 0xff) << 12))
1162
1163 /* An XFX form instruction with the SPR field filled in. */
1164 #define XSPR(op, xop, spr) \
1165 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1166 #define XSPR_MASK (X_MASK | SPR_MASK)
1167
1168 /* An XFX form instruction with the SPR field filled in except for the
1169 SPRBAT field. */
1170 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1171
1172 /* An XFX form instruction with the SPR field filled in except for the
1173 SPRG field. */
1174 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1175
1176 /* The BO encodings used in extended conditional branch mnemonics. */
1177 #define BODNZF (0x0)
1178 #define BODNZFP (0x1)
1179 #define BODZF (0x2)
1180 #define BODZFP (0x3)
1181 #define BOF (0x4)
1182 #define BOFP (0x5)
1183 #define BODNZT (0x8)
1184 #define BODNZTP (0x9)
1185 #define BODZT (0xa)
1186 #define BODZTP (0xb)
1187 #define BOT (0xc)
1188 #define BOTP (0xd)
1189 #define BODNZ (0x10)
1190 #define BODNZP (0x11)
1191 #define BODZ (0x12)
1192 #define BODZP (0x13)
1193 #define BOU (0x14)
1194
1195 /* The BI condition bit encodings used in extended conditional branch
1196 mnemonics. */
1197 #define CBLT (0)
1198 #define CBGT (1)
1199 #define CBEQ (2)
1200 #define CBSO (3)
1201
1202 /* The TO encodings used in extended trap mnemonics. */
1203 #define TOLGT (0x1)
1204 #define TOLLT (0x2)
1205 #define TOEQ (0x4)
1206 #define TOLGE (0x5)
1207 #define TOLNL (0x5)
1208 #define TOLLE (0x6)
1209 #define TOLNG (0x6)
1210 #define TOGT (0x8)
1211 #define TOGE (0xc)
1212 #define TONL (0xc)
1213 #define TOLT (0x10)
1214 #define TOLE (0x14)
1215 #define TONG (0x14)
1216 #define TONE (0x18)
1217 #define TOU (0x1f)
1218
1219 /* Smaller names for the flags so each entry in the opcodes table will
1220 fit on a single line. */
1221 #undef PPC
1222 #define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1223 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1224 #define PPC32 PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
1225 #define PPC64 PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
1226 #define PPCONLY PPC_OPCODE_PPC
1227 #define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1228 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1229 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1230 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1231 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1232 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1233 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1234 #define MFDEC1 PPC_OPCODE_POWER
1235 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
1236
1237 /* The opcode table.
1238
1239 The format of the opcode table is:
1240
1241 NAME OPCODE MASK FLAGS { OPERANDS }
1242
1243 NAME is the name of the instruction.
1244 OPCODE is the instruction opcode.
1245 MASK is the opcode mask; this is used to tell the disassembler
1246 which bits in the actual opcode must match OPCODE.
1247 FLAGS are flags indicated what processors support the instruction.
1248 OPERANDS is the list of operands.
1249
1250 The disassembler reads the table in order and prints the first
1251 instruction which matches, so this table is sorted to put more
1252 specific instructions before more general instructions. It is also
1253 sorted by major opcode. */
1254
1255 const struct powerpc_opcode powerpc_opcodes[] = {
1256 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1257 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1258 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1259 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1260 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1261 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1262 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1263 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1264 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1265 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1266 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1267 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1268 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1269 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1270 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1271
1272 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1273 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1274 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1275 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1276 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1277 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1278 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1279 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1280 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1281 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1282 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1283 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1284 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1285 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1286 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1287 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1288 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1289 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1290 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1291 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1292 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1293 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1294 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1295 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1296 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1297 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1298 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1299 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1300 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1301 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1302
1303 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
1304 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
1305
1306 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
1307 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
1308
1309 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
1310
1311 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
1312 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
1313 { "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
1314 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
1315
1316 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
1317 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
1318 { "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
1319 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
1320
1321 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
1322 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
1323 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
1324
1325 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
1326 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
1327 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
1328
1329 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
1330 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
1331 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
1332 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
1333 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
1334 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
1335
1336 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
1337 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
1338 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
1339 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
1340 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
1341
1342 { "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1343 { "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1344 { "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BD } },
1345 { "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM, { BD } },
1346 { "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1347 { "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1348 { "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BD } },
1349 { "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM, { BD } },
1350 { "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1351 { "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1352 { "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDA } },
1353 { "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM, { BDA } },
1354 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1355 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1356 { "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDA } },
1357 { "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM, { BDA } },
1358 { "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1359 { "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1360 { "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, COM, { BD } },
1361 { "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1362 { "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1363 { "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, COM, { BD } },
1364 { "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1365 { "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1366 { "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, COM, { BDA } },
1367 { "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1368 { "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1369 { "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, COM, { BDA } },
1370 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1371 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1372 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1373 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1374 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1375 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1376 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1377 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1378 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1379 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1380 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1381 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1382 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1383 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1384 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1385 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1386 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1387 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1388 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1389 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1390 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1391 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1392 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1393 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1394 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1395 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1396 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } },
1397 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1398 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1399 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } },
1400 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1401 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1402 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1403 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1404 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1405 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1406 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1407 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1408 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } },
1409 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1410 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1411 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } },
1412 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1413 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1414 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1415 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1416 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1417 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1418 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1419 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1420 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
1421 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1422 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1423 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
1424 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1425 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1426 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1427 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1428 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1429 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1430 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1431 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1432 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1433 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1434 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1435 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1436 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1437 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1438 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1439 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1440 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1441 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1442 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1443 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1444 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1445 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1446 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1447 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1448 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1449 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1450 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1451 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1452 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1453 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1454 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1455 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1456 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1457 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1458 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1459 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1460 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1461 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1462 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1463 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1464 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1465 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1466 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1467 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1468 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1469 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1470 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1471 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1472 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1473 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1474 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1475 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1476 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1477 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1478 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1479 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1480 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } },
1481 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1482 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1483 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } },
1484 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1485 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1486 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1487 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1488 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1489 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1490 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1491 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1492 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } },
1493 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1494 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1495 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } },
1496 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1497 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1498 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1499 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1500 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1501 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1502 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1503 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1504 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
1505 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1506 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1507 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
1508 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1509 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1510 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1511 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1512 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1513 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1514 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1515 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1516 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1517 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1518 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1519 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1520 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1521 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1522 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1523 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1524 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1525 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1526 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1527 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1528 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1529 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1530 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1531 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1532 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1533 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1534 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1535 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1536 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1537 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1538 { "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1539 { "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1540 { "bt", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1541 { "bbt", BBO(16,BOT,0,0), BBOY_MASK, PWRCOM, { BI, BD } },
1542 { "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1543 { "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1544 { "btl", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1545 { "bbtl", BBO(16,BOT,0,1), BBOY_MASK, PWRCOM, { BI, BD } },
1546 { "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1547 { "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1548 { "bta", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1549 { "bbta", BBO(16,BOT,1,0), BBOY_MASK, PWRCOM, { BI, BDA } },
1550 { "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1551 { "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1552 { "btla", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1553 { "bbtla", BBO(16,BOT,1,1), BBOY_MASK, PWRCOM, { BI, BDA } },
1554 { "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1555 { "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1556 { "bf", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1557 { "bbf", BBO(16,BOF,0,0), BBOY_MASK, PWRCOM, { BI, BD } },
1558 { "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1559 { "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1560 { "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1561 { "bbfl", BBO(16,BOF,0,1), BBOY_MASK, PWRCOM, { BI, BD } },
1562 { "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1563 { "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1564 { "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1565 { "bbfa", BBO(16,BOF,1,0), BBOY_MASK, PWRCOM, { BI, BDA } },
1566 { "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1567 { "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1568 { "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1569 { "bbfla", BBO(16,BOF,1,1), BBOY_MASK, PWRCOM, { BI, BDA } },
1570 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1571 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1572 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1573 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1574 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1575 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1576 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1577 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1578 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1579 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1580 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1581 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1582 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1583 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1584 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1585 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1586 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1587 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1588 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1589 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1590 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1591 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1592 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1593 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1594 { "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } },
1595 { "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } },
1596 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
1597 { "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } },
1598 { "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } },
1599 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
1600 { "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } },
1601 { "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } },
1602 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
1603 { "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } },
1604 { "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } },
1605 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
1606
1607 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1608 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
1609 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
1610 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
1611 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
1612
1613 { "b", B(18,0,0), B_MASK, COM, { LI } },
1614 { "bl", B(18,0,1), B_MASK, COM, { LI } },
1615 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
1616 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
1617
1618 { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
1619
1620 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1621 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
1622 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1623 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
1624 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1625 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1626 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1627 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1628 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1629 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1630 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1631 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1632 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1633 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1634 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1635 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1636 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1637 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1638 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1639 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1640 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1641 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1642 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1643 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1644 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1645 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1646 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1647 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1648 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1649 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1650 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1651 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1652 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1653 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1654 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1655 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1656 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1657 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1658 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1659 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1660 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1661 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1662 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1663 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1664 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1665 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1666 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1667 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1668 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1669 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1670 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1671 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1672 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1673 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1674 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1675 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1676 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1677 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1678 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1679 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1680 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1681 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1682 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1683 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1684 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1685 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1686 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1687 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1688 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1689 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1690 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1691 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1692 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1693 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1694 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1695 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1696 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1697 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1698 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1699 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1700 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1701 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1702 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1703 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1704 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1705 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1706 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1707 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1708 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1709 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1710 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1711 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1712 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1713 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1714 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1715 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1716 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1717 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1718 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1719 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1720 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1721 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1722 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1723 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1724 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1725 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1726 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1727 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1728 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
1729 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1730 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } },
1731 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
1732 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
1733 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1734 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } },
1735 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
1736 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
1737 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1738 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } },
1739 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
1740 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
1741 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1742 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } },
1743 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
1744 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
1745 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1746 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1747 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
1748 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1749 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1750 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
1751 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1752 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1753 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
1754 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1755 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1756 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
1757 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1758 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1759 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
1760 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1761 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1762 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
1763 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1764 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1765 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
1766 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1767 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1768 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
1769 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
1770 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1771 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1772 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1773 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1774 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
1775 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
1776
1777 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
1778 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
1779
1780 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
1781 { "rfci", XL(19,51), 0xffffffff, PPC, { 0 } },
1782
1783 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
1784
1785 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
1786
1787 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
1788 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
1789
1790 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
1791 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
1792
1793 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
1794
1795 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
1796
1797 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
1798 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
1799
1800 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
1801
1802 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
1803 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
1804
1805 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
1806 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
1807 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1808 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1809 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1810 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1811 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1812 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1813 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1814 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1815 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1816 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1817 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1818 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1819 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1820 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1821 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1822 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1823 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1824 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1825 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1826 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1827 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1828 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1829 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1830 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1831 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1832 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1833 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1834 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1835 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1836 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1837 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1838 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1839 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1840 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1841 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1842 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1843 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1844 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1845 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1846 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1847 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1848 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1849 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1850 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1851 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1852 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1853 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1854 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1855 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1856 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1857 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1858 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1859 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1860 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1861 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1862 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1863 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1864 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1865 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1866 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1867 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1868 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1869 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1870 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1871 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1872 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1873 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1874 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1875 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1876 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1877 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1878 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1879 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
1880 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1881 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } },
1882 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
1883 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1884 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } },
1885 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
1886 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1887 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } },
1888 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
1889 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1890 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } },
1891 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
1892 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1893 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1894 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
1895 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1896 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1897 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
1898 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
1899
1900 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
1901 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
1902
1903 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
1904 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
1905
1906 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
1907 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
1908 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
1909 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
1910 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
1911 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
1912 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
1913 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
1914
1915 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
1916 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
1917
1918 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
1919 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
1920 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
1921 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
1922 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
1923 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
1924
1925 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
1926 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
1927 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
1928
1929 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
1930 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
1931
1932 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
1933 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
1934
1935 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
1936 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
1937
1938 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
1939 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
1940
1941 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
1942 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
1943
1944 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
1945 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
1946 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
1947 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
1948 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
1949 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
1950
1951 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
1952 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
1953
1954 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
1955 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
1956
1957 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
1958 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
1959
1960 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
1961 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
1962 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
1963 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
1964
1965 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
1966 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
1967
1968 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
1969 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
1970 { "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
1971 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
1972
1973 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
1974 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
1975 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
1976 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
1977 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
1978 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
1979 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
1980 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
1981 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
1982 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
1983 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
1984 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
1985 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
1986 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
1987 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
1988 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
1989 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
1990 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
1991 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
1992 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
1993 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
1994 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
1995 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
1996 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
1997 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
1998 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
1999 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
2000 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
2001 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
2002 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
2003 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
2004
2005 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2006 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2007 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2008 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2009 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2010 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
2011 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2012 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2013 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2014 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2015 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2016 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2017
2018 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2019 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2020
2021 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2022 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2023 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2024 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2025 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2026 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2027 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2028 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2029
2030 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2031 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2032
2033 { "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
2034
2035 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2036
2037 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
2038
2039 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
2040 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
2041
2042 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
2043 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
2044 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
2045 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
2046
2047 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
2048 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
2049 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
2050 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
2051
2052 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
2053 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
2054
2055 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
2056 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
2057
2058 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
2059 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
2060
2061 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2062 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2063 { "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2064 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2065
2066 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2067 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2068 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2069 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2070 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2071 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2072 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2073 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2074
2075 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
2076
2077 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2078
2079 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
2080 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
2081
2082 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
2083 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
2084
2085 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
2086 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
2087
2088 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
2089 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
2090 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
2091 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
2092 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
2093 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
2094 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
2095 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
2096 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
2097 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
2098 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
2099 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
2100 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
2101 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
2102 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
2103
2104 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2105 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2106
2107 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2108 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2109
2110 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
2111
2112 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
2113
2114 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2115
2116 { "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
2117
2118 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
2119 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
2120 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
2121 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
2122
2123 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
2124 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
2125 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
2126 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
2127
2128 { "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
2129
2130 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
2131
2132 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
2133 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
2134 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
2135 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
2136
2137 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2138 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2139 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2140 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2141 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2142 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2143 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2144 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2145
2146 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2147 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2148 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2149 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2150 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2151 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2152 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2153 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2154
2155 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
2156 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
2157
2158 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
2159
2160 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
2161
2162 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2163
2164 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
2165 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
2166
2167 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
2168 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
2169
2170 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
2171 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
2172
2173 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
2174
2175 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
2176 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
2177
2178 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
2179 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
2180
2181 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2182 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2183 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2184 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2185 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2186 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2187 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2188 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2189
2190 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2191 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2192 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2193 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2194 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2195 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2196 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2197 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2198
2199 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
2200
2201 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
2202
2203 { "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
2204
2205 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
2206 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
2207
2208 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
2209 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
2210
2211 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2212 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2213 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2214 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2215 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2216 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2217 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2218 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2219
2220 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2221 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2222 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
2223 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
2224
2225 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2226 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2227 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2228 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2229 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2230 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2231 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2232 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2233
2234 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2235 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2236 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2237 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2238 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2239 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2240 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2241 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2242
2243 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
2244 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
2245
2246 { "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
2247
2248 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
2249
2250 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
2251 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
2252
2253 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
2254 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
2255 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
2256 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
2257
2258 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2259 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2260 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2261 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2262 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2263 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2264 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2265 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2266
2267 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
2268 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
2269
2270 { "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
2271
2272 { "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
2273
2274 { "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } },
2275
2276 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
2277 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
2278
2279 { "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
2280 { "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
2281
2282 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2283
2284 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
2285
2286 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
2287 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
2288
2289 { "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } },
2290
2291 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
2292 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
2293 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
2294 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
2295
2296 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
2297 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
2298 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
2299 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
2300 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
2301 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
2302 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
2303 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
2304 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
2305 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
2306 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
2307 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
2308 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
2309 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
2310 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
2311 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
2312 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
2313 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
2314 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
2315 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2316 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2317 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2318 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2319 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
2320
2321 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
2322
2323 { "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
2324
2325 { "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } },
2326
2327 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
2328 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
2329 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
2330 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
2331
2332 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
2333 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
2334 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
2335 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
2336
2337 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2338
2339 { "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
2340 { "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2341
2342 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
2343
2344 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
2345
2346 { "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
2347
2348 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
2349
2350 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
2351
2352 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
2353
2354 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
2355
2356 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
2357 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
2358
2359 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
2360 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
2361
2362 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
2363
2364 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2365
2366 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
2367
2368 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
2369 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
2370 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
2371 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
2372
2373 { "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } },
2374
2375 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2376 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2377 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
2378 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
2379
2380 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
2381 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
2382 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
2383 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
2384
2385 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
2386 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
2387 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
2388 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
2389 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
2390 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
2391 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
2392 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
2393 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
2394 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
2395 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
2396 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
2397 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
2398 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
2399 { "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
2400 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
2401 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
2402 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
2403 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
2404 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2405 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2406 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2407 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2408 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
2409
2410 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
2411
2412 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
2413 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
2414
2415 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
2416 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
2417 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
2418 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
2419
2420 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2421 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2422 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
2423 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
2424
2425 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
2426 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
2427 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
2428 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
2429
2430 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
2431
2432 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
2433
2434 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
2435
2436 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
2437
2438 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
2439 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
2440
2441 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
2442 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
2443
2444 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
2445
2446 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
2447 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
2448 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
2449 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
2450
2451 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
2452 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
2453
2454 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
2455 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
2456
2457 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
2458 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
2459
2460 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
2461
2462 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
2463
2464 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
2465
2466 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
2467 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
2468
2469 { "sync", X(31,598), 0xffffffff, PPCCOM, { 0 } },
2470 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
2471
2472 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
2473
2474 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
2475
2476 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
2477
2478 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
2479
2480 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
2481
2482 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
2483 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
2484
2485 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
2486 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
2487
2488 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
2489
2490 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
2491 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
2492
2493 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
2494 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
2495
2496 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
2497
2498 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
2499 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
2500
2501 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
2502 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
2503
2504 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
2505
2506 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
2507 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
2508
2509 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
2510 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
2511
2512 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
2513
2514 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
2515 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
2516
2517 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
2518
2519 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
2520 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
2521 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
2522 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
2523
2524 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
2525 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
2526
2527 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
2528
2529 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
2530 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
2531 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
2532 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
2533
2534 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
2535
2536 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
2537
2538 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
2539 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
2540
2541 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
2542 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
2543
2544 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
2545 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
2546 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
2547 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
2548
2549 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
2550 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
2551
2552 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
2553 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
2554
2555 { "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } },
2556
2557 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
2558
2559 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
2560
2561 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
2562
2563 { "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
2564 { "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
2565
2566 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
2567
2568 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2569 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2570
2571 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
2572 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
2573
2574 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
2575 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
2576
2577 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
2578
2579 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
2580
2581 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
2582 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
2583
2584 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
2585 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
2586
2587 { "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
2588
2589 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
2590
2591 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
2592
2593 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
2594
2595 { "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
2596
2597 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
2598
2599 { "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
2600
2601 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
2602
2603 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
2604 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
2605
2606 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
2607 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
2608
2609 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
2610
2611 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
2612
2613 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
2614
2615 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
2616
2617 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
2618
2619 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
2620
2621 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
2622
2623 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
2624
2625 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
2626
2627 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
2628
2629 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
2630
2631 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
2632
2633 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
2634
2635 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2636 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2637
2638 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2639 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2640
2641 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2642 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2643
2644 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2645 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2646
2647 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2648 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2649
2650 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2651 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2652
2653 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2654 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2655
2656 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2657 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2658
2659 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2660 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2661
2662 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2663 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2664
2665 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
2666
2667 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
2668
2669 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
2670
2671 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
2672
2673 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
2674
2675 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
2676 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
2677
2678 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
2679 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
2680 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
2681 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
2682
2683 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
2684 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
2685 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
2686 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
2687
2688 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
2689 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
2690 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
2691 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
2692
2693 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
2694 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
2695 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
2696 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
2697
2698 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
2699 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
2700 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
2701 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
2702
2703 { "fsqrt", A(63,22,0), AFRAFRC_MASK, POWER2, { FRT, FRB } },
2704 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, POWER2, { FRT, FRB } },
2705 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2706 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2707
2708 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2709 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2710
2711 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
2712 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
2713 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
2714 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
2715
2716 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2717 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2718
2719 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
2720 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
2721 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
2722 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
2723
2724 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
2725 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
2726 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
2727 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
2728
2729 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
2730 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
2731 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
2732 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
2733
2734 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
2735 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
2736 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
2737 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
2738
2739 { "fcmpo", X(63,30), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
2740
2741 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
2742 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
2743
2744 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
2745 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
2746
2747 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
2748
2749 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
2750 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
2751
2752 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
2753 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
2754
2755 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
2756 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
2757
2758 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
2759 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
2760
2761 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
2762 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
2763
2764 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
2765 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
2766
2767 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
2768 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
2769
2770 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
2771 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
2772
2773 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
2774 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
2775
2776 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
2777 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
2778
2779 };
2780
2781 const int powerpc_num_opcodes =
2782 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
2783
2784 /* The macro table. This is only used by the assembler. */
2785
2786 const struct powerpc_macro powerpc_macros[] = {
2787 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
2788 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
2789 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
2790 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
2791 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
2792 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
2793 { "rotrdi", 3, PPC64, "rldicl %0,%1,64-(%2),0" },
2794 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,64-(%2),0" },
2795 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
2796 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
2797 { "srdi", 3, PPC64, "rldicl %0,%1,64-(%2),%2" },
2798 { "srdi.", 3, PPC64, "rldicl. %0,%1,64-(%2),%2" },
2799 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
2800 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
2801 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
2802 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
2803
2804 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
2805 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
2806 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
2807 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
2808 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2809 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2810 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
2811 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
2812 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,32-(%2),0,31" },
2813 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,32-(%2),0,31" },
2814 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
2815 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
2816 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
2817 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
2818 { "srwi", 3, PPCCOM, "rlwinm %0,%1,32-(%2),%2,31" },
2819 { "sri", 3, PWRCOM, "rlinm %0,%1,32-(%2),%2,31" },
2820 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,32-(%2),%2,31" },
2821 { "sri.", 3, PWRCOM, "rlinm. %0,%1,32-(%2),%2,31" },
2822 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
2823 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
2824 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
2825 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
2826
2827 };
2828
2829 const int powerpc_num_macros =
2830 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
2831