1 // Copyright 2015, ARM Limited
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 #ifndef VIXL_A64_CONSTANTS_A64_H_
28 #define VIXL_A64_CONSTANTS_A64_H_
29
30 #include <stdint.h>
31
32 #include "jit/arm64/vixl/Globals-vixl.h"
33
34 namespace vixl {
35
36 // Supervisor Call (svc) specific support.
37 //
38 // The SVC instruction encodes an optional 16-bit immediate value.
39 // The simulator understands the codes below.
40 enum SVCSimulatorCodes {
41 kCallRtRedirected = 0x10, // Transition to x86_64 C code.
42 kMarkStackPointer = 0x11, // Push the current SP on a special Simulator stack.
43 kCheckStackPointer = 0x12 // Pop from the special Simulator stack and compare to SP.
44 };
45
46 const unsigned kNumberOfRegisters = 32;
47 const unsigned kNumberOfVRegisters = 32;
48 const unsigned kNumberOfFPRegisters = kNumberOfVRegisters;
49 // Callee saved registers are x21-x30(lr).
50 const int kNumberOfCalleeSavedRegisters = 10;
51 const int kFirstCalleeSavedRegisterIndex = 21;
52 // Callee saved FP registers are d8-d15.
53 const int kNumberOfCalleeSavedFPRegisters = 8;
54 const int kFirstCalleeSavedFPRegisterIndex = 8;
55
56 #define REGISTER_CODE_LIST(R) \
57 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
58 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
59 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
60 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
61
62 #define INSTRUCTION_FIELDS_LIST(V_) \
63 /* Register fields */ \
64 V_(Rd, 4, 0, Bits) /* Destination register. */ \
65 V_(Rn, 9, 5, Bits) /* First source register. */ \
66 V_(Rm, 20, 16, Bits) /* Second source register. */ \
67 V_(Ra, 14, 10, Bits) /* Third source register. */ \
68 V_(Rt, 4, 0, Bits) /* Load/store register. */ \
69 V_(Rt2, 14, 10, Bits) /* Load/store second register. */ \
70 V_(Rs, 20, 16, Bits) /* Exclusive access status. */ \
71 \
72 /* Common bits */ \
73 V_(SixtyFourBits, 31, 31, Bits) \
74 V_(FlagsUpdate, 29, 29, Bits) \
75 \
76 /* PC relative addressing */ \
77 V_(ImmPCRelHi, 23, 5, SignedBits) \
78 V_(ImmPCRelLo, 30, 29, Bits) \
79 \
80 /* Add/subtract/logical shift register */ \
81 V_(ShiftDP, 23, 22, Bits) \
82 V_(ImmDPShift, 15, 10, Bits) \
83 \
84 /* Add/subtract immediate */ \
85 V_(ImmAddSub, 21, 10, Bits) \
86 V_(ShiftAddSub, 23, 22, Bits) \
87 \
88 /* Add/substract extend */ \
89 V_(ImmExtendShift, 12, 10, Bits) \
90 V_(ExtendMode, 15, 13, Bits) \
91 \
92 /* Move wide */ \
93 V_(ImmMoveWide, 20, 5, Bits) \
94 V_(ShiftMoveWide, 22, 21, Bits) \
95 \
96 /* Logical immediate, bitfield and extract */ \
97 V_(BitN, 22, 22, Bits) \
98 V_(ImmRotate, 21, 16, Bits) \
99 V_(ImmSetBits, 15, 10, Bits) \
100 V_(ImmR, 21, 16, Bits) \
101 V_(ImmS, 15, 10, Bits) \
102 \
103 /* Test and branch immediate */ \
104 V_(ImmTestBranch, 18, 5, SignedBits) \
105 V_(ImmTestBranchBit40, 23, 19, Bits) \
106 V_(ImmTestBranchBit5, 31, 31, Bits) \
107 \
108 /* Conditionals */ \
109 V_(Condition, 15, 12, Bits) \
110 V_(ConditionBranch, 3, 0, Bits) \
111 V_(Nzcv, 3, 0, Bits) \
112 V_(ImmCondCmp, 20, 16, Bits) \
113 V_(ImmCondBranch, 23, 5, SignedBits) \
114 \
115 /* Floating point */ \
116 V_(FPType, 23, 22, Bits) \
117 V_(ImmFP, 20, 13, Bits) \
118 V_(FPScale, 15, 10, Bits) \
119 \
120 /* Load Store */ \
121 V_(ImmLS, 20, 12, SignedBits) \
122 V_(ImmLSUnsigned, 21, 10, Bits) \
123 V_(ImmLSPair, 21, 15, SignedBits) \
124 V_(ImmShiftLS, 12, 12, Bits) \
125 V_(LSOpc, 23, 22, Bits) \
126 V_(LSVector, 26, 26, Bits) \
127 V_(LSSize, 31, 30, Bits) \
128 V_(ImmPrefetchOperation, 4, 0, Bits) \
129 V_(PrefetchHint, 4, 3, Bits) \
130 V_(PrefetchTarget, 2, 1, Bits) \
131 V_(PrefetchStream, 0, 0, Bits) \
132 \
133 /* Other immediates */ \
134 V_(ImmUncondBranch, 25, 0, SignedBits) \
135 V_(ImmCmpBranch, 23, 5, SignedBits) \
136 V_(ImmLLiteral, 23, 5, SignedBits) \
137 V_(ImmException, 20, 5, Bits) \
138 V_(ImmHint, 11, 5, Bits) \
139 V_(ImmBarrierDomain, 11, 10, Bits) \
140 V_(ImmBarrierType, 9, 8, Bits) \
141 \
142 /* System (MRS, MSR, SYS) */ \
143 V_(ImmSystemRegister, 19, 5, Bits) \
144 V_(SysO0, 19, 19, Bits) \
145 V_(SysOp, 18, 5, Bits) \
146 V_(SysOp1, 18, 16, Bits) \
147 V_(SysOp2, 7, 5, Bits) \
148 V_(CRn, 15, 12, Bits) \
149 V_(CRm, 11, 8, Bits) \
150 \
151 /* Load-/store-exclusive */ \
152 V_(LdStXLoad, 22, 22, Bits) \
153 V_(LdStXNotExclusive, 23, 23, Bits) \
154 V_(LdStXAcquireRelease, 15, 15, Bits) \
155 V_(LdStXSizeLog2, 31, 30, Bits) \
156 V_(LdStXPair, 21, 21, Bits) \
157 \
158 /* NEON generic fields */ \
159 V_(NEONQ, 30, 30, Bits) \
160 V_(NEONSize, 23, 22, Bits) \
161 V_(NEONLSSize, 11, 10, Bits) \
162 V_(NEONS, 12, 12, Bits) \
163 V_(NEONL, 21, 21, Bits) \
164 V_(NEONM, 20, 20, Bits) \
165 V_(NEONH, 11, 11, Bits) \
166 V_(ImmNEONExt, 14, 11, Bits) \
167 V_(ImmNEON5, 20, 16, Bits) \
168 V_(ImmNEON4, 14, 11, Bits) \
169 \
170 /* NEON Modified Immediate fields */ \
171 V_(ImmNEONabc, 18, 16, Bits) \
172 V_(ImmNEONdefgh, 9, 5, Bits) \
173 V_(NEONModImmOp, 29, 29, Bits) \
174 V_(NEONCmode, 15, 12, Bits) \
175 \
176 /* NEON Shift Immediate fields */ \
177 V_(ImmNEONImmhImmb, 22, 16, Bits) \
178 V_(ImmNEONImmh, 22, 19, Bits) \
179 V_(ImmNEONImmb, 18, 16, Bits)
180
181 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
182 /* NZCV */ \
183 V_(Flags, 31, 28, Bits) \
184 V_(N, 31, 31, Bits) \
185 V_(Z, 30, 30, Bits) \
186 V_(C, 29, 29, Bits) \
187 V_(V, 28, 28, Bits) \
188 M_(NZCV, Flags_mask) \
189 /* FPCR */ \
190 V_(AHP, 26, 26, Bits) \
191 V_(DN, 25, 25, Bits) \
192 V_(FZ, 24, 24, Bits) \
193 V_(RMode, 23, 22, Bits) \
194 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
195
196 // Fields offsets.
197 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \
198 const int Name##_offset = LowBit; \
199 const int Name##_width = HighBit - LowBit + 1; \
200 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
201 #define NOTHING(A, B)
202 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS)
203 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
204 #undef NOTHING
205 #undef DECLARE_FIELDS_BITS
206
207 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
208 // from ImmPCRelLo and ImmPCRelHi.
209 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
210
211 // Condition codes.
212 enum Condition {
213 eq = 0, // Z set Equal.
214 ne = 1, // Z clear Not equal.
215 cs = 2, // C set Carry set.
216 cc = 3, // C clear Carry clear.
217 mi = 4, // N set Negative.
218 pl = 5, // N clear Positive or zero.
219 vs = 6, // V set Overflow.
220 vc = 7, // V clear No overflow.
221 hi = 8, // C set, Z clear Unsigned higher.
222 ls = 9, // C clear or Z set Unsigned lower or same.
223 ge = 10, // N == V Greater or equal.
224 lt = 11, // N != V Less than.
225 gt = 12, // Z clear, N == V Greater than.
226 le = 13, // Z set or N != V Less then or equal
227 al = 14, // Always.
228 nv = 15, // Behaves as always/al.
229
230 // Aliases.
231 hs = cs, // C set Unsigned higher or same.
232 lo = cc, // C clear Unsigned lower.
233
234 // Mozilla expanded aliases.
235 Equal = 0, Zero = 0,
236 NotEqual = 1, NonZero = 1,
237 AboveOrEqual = 2, CarrySet = 2,
238 Below = 3, CarryClear = 3,
239 Signed = 4,
240 NotSigned = 5,
241 Overflow = 6,
242 NoOverflow = 7,
243 Above = 8,
244 BelowOrEqual = 9,
245 GreaterThanOrEqual_ = 10,
246 LessThan_ = 11,
247 GreaterThan_ = 12,
248 LessThanOrEqual_ = 13,
249 Always = 14,
250 Never = 15
251 };
252
InvertCondition(Condition cond)253 inline Condition InvertCondition(Condition cond) {
254 // Conditions al and nv behave identically, as "always true". They can't be
255 // inverted, because there is no "always false" condition.
256 VIXL_ASSERT((cond != al) && (cond != nv));
257 return static_cast<Condition>(cond ^ 1);
258 }
259
260 enum FPTrapFlags {
261 EnableTrap = 1,
262 DisableTrap = 0
263 };
264
265 enum FlagsUpdate {
266 SetFlags = 1,
267 LeaveFlags = 0
268 };
269
270 enum StatusFlags {
271 NoFlag = 0,
272
273 // Derive the flag combinations from the system register bit descriptions.
274 NFlag = N_mask,
275 ZFlag = Z_mask,
276 CFlag = C_mask,
277 VFlag = V_mask,
278 NZFlag = NFlag | ZFlag,
279 NCFlag = NFlag | CFlag,
280 NVFlag = NFlag | VFlag,
281 ZCFlag = ZFlag | CFlag,
282 ZVFlag = ZFlag | VFlag,
283 CVFlag = CFlag | VFlag,
284 NZCFlag = NFlag | ZFlag | CFlag,
285 NZVFlag = NFlag | ZFlag | VFlag,
286 NCVFlag = NFlag | CFlag | VFlag,
287 ZCVFlag = ZFlag | CFlag | VFlag,
288 NZCVFlag = NFlag | ZFlag | CFlag | VFlag,
289
290 // Floating-point comparison results.
291 FPEqualFlag = ZCFlag,
292 FPLessThanFlag = NFlag,
293 FPGreaterThanFlag = CFlag,
294 FPUnorderedFlag = CVFlag
295 };
296
297 enum Shift {
298 NO_SHIFT = -1,
299 LSL = 0x0,
300 LSR = 0x1,
301 ASR = 0x2,
302 ROR = 0x3,
303 MSL = 0x4
304 };
305
306 enum Extend {
307 NO_EXTEND = -1,
308 UXTB = 0,
309 UXTH = 1,
310 UXTW = 2,
311 UXTX = 3,
312 SXTB = 4,
313 SXTH = 5,
314 SXTW = 6,
315 SXTX = 7
316 };
317
318 enum SystemHint {
319 NOP = 0,
320 YIELD = 1,
321 WFE = 2,
322 WFI = 3,
323 SEV = 4,
324 SEVL = 5,
325 // No-op on architectures where this instruction is not defined.
326 // https://developer.arm.com/-/media/developer/pdf/Cache_Speculation_Side-channels_22Feb18.pdf
327 CSDB = 0x14
328 };
329
330 enum BarrierDomain {
331 OuterShareable = 0,
332 NonShareable = 1,
333 InnerShareable = 2,
334 FullSystem = 3
335 };
336
337 enum BarrierType {
338 BarrierOther = 0,
339 BarrierReads = 1,
340 BarrierWrites = 2,
341 BarrierAll = 3
342 };
343
344 enum PrefetchOperation {
345 PLDL1KEEP = 0x00,
346 PLDL1STRM = 0x01,
347 PLDL2KEEP = 0x02,
348 PLDL2STRM = 0x03,
349 PLDL3KEEP = 0x04,
350 PLDL3STRM = 0x05,
351
352 PLIL1KEEP = 0x08,
353 PLIL1STRM = 0x09,
354 PLIL2KEEP = 0x0a,
355 PLIL2STRM = 0x0b,
356 PLIL3KEEP = 0x0c,
357 PLIL3STRM = 0x0d,
358
359 PSTL1KEEP = 0x10,
360 PSTL1STRM = 0x11,
361 PSTL2KEEP = 0x12,
362 PSTL2STRM = 0x13,
363 PSTL3KEEP = 0x14,
364 PSTL3STRM = 0x15
365 };
366
367 // System/special register names.
368 // This information is not encoded as one field but as the concatenation of
369 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
370 enum SystemRegister {
371 NZCV = ((0x1 << SysO0_offset) |
372 (0x3 << SysOp1_offset) |
373 (0x4 << CRn_offset) |
374 (0x2 << CRm_offset) |
375 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset,
376 FPCR = ((0x1 << SysO0_offset) |
377 (0x3 << SysOp1_offset) |
378 (0x4 << CRn_offset) |
379 (0x4 << CRm_offset) |
380 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset
381 };
382
383 enum InstructionCacheOp {
384 IVAU = ((0x3 << SysOp1_offset) |
385 (0x7 << CRn_offset) |
386 (0x5 << CRm_offset) |
387 (0x1 << SysOp2_offset)) >> SysOp_offset
388 };
389
390 enum DataCacheOp {
391 CVAC = ((0x3 << SysOp1_offset) |
392 (0x7 << CRn_offset) |
393 (0xa << CRm_offset) |
394 (0x1 << SysOp2_offset)) >> SysOp_offset,
395 CVAU = ((0x3 << SysOp1_offset) |
396 (0x7 << CRn_offset) |
397 (0xb << CRm_offset) |
398 (0x1 << SysOp2_offset)) >> SysOp_offset,
399 CIVAC = ((0x3 << SysOp1_offset) |
400 (0x7 << CRn_offset) |
401 (0xe << CRm_offset) |
402 (0x1 << SysOp2_offset)) >> SysOp_offset,
403 ZVA = ((0x3 << SysOp1_offset) |
404 (0x7 << CRn_offset) |
405 (0x4 << CRm_offset) |
406 (0x1 << SysOp2_offset)) >> SysOp_offset
407 };
408
409 // Instruction enumerations.
410 //
411 // These are the masks that define a class of instructions, and the list of
412 // instructions within each class. Each enumeration has a Fixed, FMask and
413 // Mask value.
414 //
415 // Fixed: The fixed bits in this instruction class.
416 // FMask: The mask used to extract the fixed bits in the class.
417 // Mask: The mask used to identify the instructions within a class.
418 //
419 // The enumerations can be used like this:
420 //
421 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
422 // switch(instr->Mask(PCRelAddressingMask)) {
423 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
424 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
425 // default: printf("Unknown instruction\n");
426 // }
427
428
429 // Generic fields.
430 enum GenericInstrField {
431 SixtyFourBits = 0x80000000,
432 ThirtyTwoBits = 0x00000000,
433 FP32 = 0x00000000,
434 FP64 = 0x00400000
435 };
436
437 enum NEONFormatField {
438 NEONFormatFieldMask = 0x40C00000,
439 NEON_Q = 0x40000000,
440 NEON_8B = 0x00000000,
441 NEON_16B = NEON_8B | NEON_Q,
442 NEON_4H = 0x00400000,
443 NEON_8H = NEON_4H | NEON_Q,
444 NEON_2S = 0x00800000,
445 NEON_4S = NEON_2S | NEON_Q,
446 NEON_1D = 0x00C00000,
447 NEON_2D = 0x00C00000 | NEON_Q
448 };
449
450 enum NEONFPFormatField {
451 NEONFPFormatFieldMask = 0x40400000,
452 NEON_FP_2S = FP32,
453 NEON_FP_4S = FP32 | NEON_Q,
454 NEON_FP_2D = FP64 | NEON_Q
455 };
456
457 enum NEONLSFormatField {
458 NEONLSFormatFieldMask = 0x40000C00,
459 LS_NEON_8B = 0x00000000,
460 LS_NEON_16B = LS_NEON_8B | NEON_Q,
461 LS_NEON_4H = 0x00000400,
462 LS_NEON_8H = LS_NEON_4H | NEON_Q,
463 LS_NEON_2S = 0x00000800,
464 LS_NEON_4S = LS_NEON_2S | NEON_Q,
465 LS_NEON_1D = 0x00000C00,
466 LS_NEON_2D = LS_NEON_1D | NEON_Q
467 };
468
469 enum NEONScalarFormatField {
470 NEONScalarFormatFieldMask = 0x00C00000,
471 NEONScalar = 0x10000000,
472 NEON_B = 0x00000000,
473 NEON_H = 0x00400000,
474 NEON_S = 0x00800000,
475 NEON_D = 0x00C00000
476 };
477
478 // PC relative addressing.
479 enum PCRelAddressingOp {
480 PCRelAddressingFixed = 0x10000000,
481 PCRelAddressingFMask = 0x1F000000,
482 PCRelAddressingMask = 0x9F000000,
483 ADR = PCRelAddressingFixed | 0x00000000,
484 ADRP = PCRelAddressingFixed | 0x80000000
485 };
486
487 // Add/sub (immediate, shifted and extended.)
488 const int kSFOffset = 31;
489 enum AddSubOp {
490 AddSubOpMask = 0x60000000,
491 AddSubSetFlagsBit = 0x20000000,
492 ADD = 0x00000000,
493 ADDS = ADD | AddSubSetFlagsBit,
494 SUB = 0x40000000,
495 SUBS = SUB | AddSubSetFlagsBit
496 };
497
498 #define ADD_SUB_OP_LIST(V) \
499 V(ADD), \
500 V(ADDS), \
501 V(SUB), \
502 V(SUBS)
503
504 enum AddSubImmediateOp {
505 AddSubImmediateFixed = 0x11000000,
506 AddSubImmediateFMask = 0x1F000000,
507 AddSubImmediateMask = 0xFF000000,
508 #define ADD_SUB_IMMEDIATE(A) \
509 A##_w_imm = AddSubImmediateFixed | A, \
510 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
511 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE)
512 #undef ADD_SUB_IMMEDIATE
513 };
514
515 enum AddSubShiftedOp {
516 AddSubShiftedFixed = 0x0B000000,
517 AddSubShiftedFMask = 0x1F200000,
518 AddSubShiftedMask = 0xFF200000,
519 #define ADD_SUB_SHIFTED(A) \
520 A##_w_shift = AddSubShiftedFixed | A, \
521 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
522 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED)
523 #undef ADD_SUB_SHIFTED
524 };
525
526 enum AddSubExtendedOp {
527 AddSubExtendedFixed = 0x0B200000,
528 AddSubExtendedFMask = 0x1F200000,
529 AddSubExtendedMask = 0xFFE00000,
530 #define ADD_SUB_EXTENDED(A) \
531 A##_w_ext = AddSubExtendedFixed | A, \
532 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
533 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED)
534 #undef ADD_SUB_EXTENDED
535 };
536
537 // Add/sub with carry.
538 enum AddSubWithCarryOp {
539 AddSubWithCarryFixed = 0x1A000000,
540 AddSubWithCarryFMask = 0x1FE00000,
541 AddSubWithCarryMask = 0xFFE0FC00,
542 ADC_w = AddSubWithCarryFixed | ADD,
543 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits,
544 ADC = ADC_w,
545 ADCS_w = AddSubWithCarryFixed | ADDS,
546 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
547 SBC_w = AddSubWithCarryFixed | SUB,
548 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits,
549 SBC = SBC_w,
550 SBCS_w = AddSubWithCarryFixed | SUBS,
551 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits
552 };
553
554
555 // Logical (immediate and shifted register).
556 enum LogicalOp {
557 LogicalOpMask = 0x60200000,
558 NOT = 0x00200000,
559 AND = 0x00000000,
560 BIC = AND | NOT,
561 ORR = 0x20000000,
562 ORN = ORR | NOT,
563 EOR = 0x40000000,
564 EON = EOR | NOT,
565 ANDS = 0x60000000,
566 BICS = ANDS | NOT
567 };
568
569 // Logical immediate.
570 enum LogicalImmediateOp {
571 LogicalImmediateFixed = 0x12000000,
572 LogicalImmediateFMask = 0x1F800000,
573 LogicalImmediateMask = 0xFF800000,
574 AND_w_imm = LogicalImmediateFixed | AND,
575 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits,
576 ORR_w_imm = LogicalImmediateFixed | ORR,
577 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
578 EOR_w_imm = LogicalImmediateFixed | EOR,
579 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits,
580 ANDS_w_imm = LogicalImmediateFixed | ANDS,
581 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
582 };
583
584 // Logical shifted register.
585 enum LogicalShiftedOp {
586 LogicalShiftedFixed = 0x0A000000,
587 LogicalShiftedFMask = 0x1F000000,
588 LogicalShiftedMask = 0xFF200000,
589 AND_w = LogicalShiftedFixed | AND,
590 AND_x = LogicalShiftedFixed | AND | SixtyFourBits,
591 AND_shift = AND_w,
592 BIC_w = LogicalShiftedFixed | BIC,
593 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
594 BIC_shift = BIC_w,
595 ORR_w = LogicalShiftedFixed | ORR,
596 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
597 ORR_shift = ORR_w,
598 ORN_w = LogicalShiftedFixed | ORN,
599 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
600 ORN_shift = ORN_w,
601 EOR_w = LogicalShiftedFixed | EOR,
602 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits,
603 EOR_shift = EOR_w,
604 EON_w = LogicalShiftedFixed | EON,
605 EON_x = LogicalShiftedFixed | EON | SixtyFourBits,
606 EON_shift = EON_w,
607 ANDS_w = LogicalShiftedFixed | ANDS,
608 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
609 ANDS_shift = ANDS_w,
610 BICS_w = LogicalShiftedFixed | BICS,
611 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
612 BICS_shift = BICS_w
613 };
614
615 // Move wide immediate.
616 enum MoveWideImmediateOp {
617 MoveWideImmediateFixed = 0x12800000,
618 MoveWideImmediateFMask = 0x1F800000,
619 MoveWideImmediateMask = 0xFF800000,
620 MOVN = 0x00000000,
621 MOVZ = 0x40000000,
622 MOVK = 0x60000000,
623 MOVN_w = MoveWideImmediateFixed | MOVN,
624 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
625 MOVZ_w = MoveWideImmediateFixed | MOVZ,
626 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
627 MOVK_w = MoveWideImmediateFixed | MOVK,
628 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
629 };
630
631 // Bitfield.
632 const int kBitfieldNOffset = 22;
633 enum BitfieldOp {
634 BitfieldFixed = 0x13000000,
635 BitfieldFMask = 0x1F800000,
636 BitfieldMask = 0xFF800000,
637 SBFM_w = BitfieldFixed | 0x00000000,
638 SBFM_x = BitfieldFixed | 0x80000000,
639 SBFM = SBFM_w,
640 BFM_w = BitfieldFixed | 0x20000000,
641 BFM_x = BitfieldFixed | 0xA0000000,
642 BFM = BFM_w,
643 UBFM_w = BitfieldFixed | 0x40000000,
644 UBFM_x = BitfieldFixed | 0xC0000000,
645 UBFM = UBFM_w
646 // Bitfield N field.
647 };
648
649 // Extract.
650 enum ExtractOp {
651 ExtractFixed = 0x13800000,
652 ExtractFMask = 0x1F800000,
653 ExtractMask = 0xFFA00000,
654 EXTR_w = ExtractFixed | 0x00000000,
655 EXTR_x = ExtractFixed | 0x80000000,
656 EXTR = EXTR_w
657 };
658
659 // Unconditional branch.
660 enum UnconditionalBranchOp {
661 UnconditionalBranchFixed = 0x14000000,
662 UnconditionalBranchFMask = 0x7C000000,
663 UnconditionalBranchMask = 0xFC000000,
664 B = UnconditionalBranchFixed | 0x00000000,
665 BL = UnconditionalBranchFixed | 0x80000000
666 };
667
668 // Unconditional branch to register.
669 enum UnconditionalBranchToRegisterOp {
670 UnconditionalBranchToRegisterFixed = 0xD6000000,
671 UnconditionalBranchToRegisterFMask = 0xFE000000,
672 UnconditionalBranchToRegisterMask = 0xFFFFFC1F,
673 BR = UnconditionalBranchToRegisterFixed | 0x001F0000,
674 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
675 RET = UnconditionalBranchToRegisterFixed | 0x005F0000
676 };
677
678 // Compare and branch.
679 enum CompareBranchOp {
680 CompareBranchFixed = 0x34000000,
681 CompareBranchFMask = 0x7E000000,
682 CompareBranchMask = 0xFF000000,
683 CBZ_w = CompareBranchFixed | 0x00000000,
684 CBZ_x = CompareBranchFixed | 0x80000000,
685 CBZ = CBZ_w,
686 CBNZ_w = CompareBranchFixed | 0x01000000,
687 CBNZ_x = CompareBranchFixed | 0x81000000,
688 CBNZ = CBNZ_w
689 };
690
691 // Test and branch.
692 enum TestBranchOp {
693 TestBranchFixed = 0x36000000,
694 TestBranchFMask = 0x7E000000,
695 TestBranchMask = 0x7F000000,
696 TBZ = TestBranchFixed | 0x00000000,
697 TBNZ = TestBranchFixed | 0x01000000
698 };
699
700 // Conditional branch.
701 enum ConditionalBranchOp {
702 ConditionalBranchFixed = 0x54000000,
703 ConditionalBranchFMask = 0xFE000000,
704 ConditionalBranchMask = 0xFF000010,
705 B_cond = ConditionalBranchFixed | 0x00000000
706 };
707
708 // System.
709 // System instruction encoding is complicated because some instructions use op
710 // and CR fields to encode parameters. To handle this cleanly, the system
711 // instructions are split into more than one enum.
712
713 enum SystemOp {
714 SystemFixed = 0xD5000000,
715 SystemFMask = 0xFFC00000
716 };
717
718 enum SystemSysRegOp {
719 SystemSysRegFixed = 0xD5100000,
720 SystemSysRegFMask = 0xFFD00000,
721 SystemSysRegMask = 0xFFF00000,
722 MRS = SystemSysRegFixed | 0x00200000,
723 MSR = SystemSysRegFixed | 0x00000000
724 };
725
726 enum SystemHintOp {
727 SystemHintFixed = 0xD503201F,
728 SystemHintFMask = 0xFFFFF01F,
729 SystemHintMask = 0xFFFFF01F,
730 HINT = SystemHintFixed | 0x00000000
731 };
732
733 enum SystemSysOp {
734 SystemSysFixed = 0xD5080000,
735 SystemSysFMask = 0xFFF80000,
736 SystemSysMask = 0xFFF80000,
737 SYS = SystemSysFixed | 0x00000000
738 };
739
740 // Exception.
741 enum ExceptionOp {
742 ExceptionFixed = 0xD4000000,
743 ExceptionFMask = 0xFF000000,
744 ExceptionMask = 0xFFE0001F,
745 HLT = ExceptionFixed | 0x00400000,
746 BRK = ExceptionFixed | 0x00200000,
747 SVC = ExceptionFixed | 0x00000001,
748 HVC = ExceptionFixed | 0x00000002,
749 SMC = ExceptionFixed | 0x00000003,
750 DCPS1 = ExceptionFixed | 0x00A00001,
751 DCPS2 = ExceptionFixed | 0x00A00002,
752 DCPS3 = ExceptionFixed | 0x00A00003
753 };
754
755 enum MemBarrierOp {
756 MemBarrierFixed = 0xD503309F,
757 MemBarrierFMask = 0xFFFFF09F,
758 MemBarrierMask = 0xFFFFF0FF,
759 DSB = MemBarrierFixed | 0x00000000,
760 DMB = MemBarrierFixed | 0x00000020,
761 ISB = MemBarrierFixed | 0x00000040
762 };
763
764 enum SystemExclusiveMonitorOp {
765 SystemExclusiveMonitorFixed = 0xD503305F,
766 SystemExclusiveMonitorFMask = 0xFFFFF0FF,
767 SystemExclusiveMonitorMask = 0xFFFFF0FF,
768 CLREX = SystemExclusiveMonitorFixed
769 };
770
771 // Any load or store.
772 enum LoadStoreAnyOp {
773 LoadStoreAnyFMask = 0x0a000000,
774 LoadStoreAnyFixed = 0x08000000
775 };
776
777 // Any load pair or store pair.
778 enum LoadStorePairAnyOp {
779 LoadStorePairAnyFMask = 0x3a000000,
780 LoadStorePairAnyFixed = 0x28000000
781 };
782
783 #define LOAD_STORE_PAIR_OP_LIST(V) \
784 V(STP, w, 0x00000000), \
785 V(LDP, w, 0x00400000), \
786 V(LDPSW, x, 0x40400000), \
787 V(STP, x, 0x80000000), \
788 V(LDP, x, 0x80400000), \
789 V(STP, s, 0x04000000), \
790 V(LDP, s, 0x04400000), \
791 V(STP, d, 0x44000000), \
792 V(LDP, d, 0x44400000), \
793 V(STP, q, 0x84000000), \
794 V(LDP, q, 0x84400000)
795
796 // Load/store pair (post, pre and offset.)
797 enum LoadStorePairOp {
798 LoadStorePairMask = 0xC4400000,
799 LoadStorePairLBit = 1 << 22,
800 #define LOAD_STORE_PAIR(A, B, C) \
801 A##_##B = C
802 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
803 #undef LOAD_STORE_PAIR
804 };
805
806 enum LoadStorePairPostIndexOp {
807 LoadStorePairPostIndexFixed = 0x28800000,
808 LoadStorePairPostIndexFMask = 0x3B800000,
809 LoadStorePairPostIndexMask = 0xFFC00000,
810 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \
811 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
812 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX)
813 #undef LOAD_STORE_PAIR_POST_INDEX
814 };
815
816 enum LoadStorePairPreIndexOp {
817 LoadStorePairPreIndexFixed = 0x29800000,
818 LoadStorePairPreIndexFMask = 0x3B800000,
819 LoadStorePairPreIndexMask = 0xFFC00000,
820 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \
821 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
822 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX)
823 #undef LOAD_STORE_PAIR_PRE_INDEX
824 };
825
826 enum LoadStorePairOffsetOp {
827 LoadStorePairOffsetFixed = 0x29000000,
828 LoadStorePairOffsetFMask = 0x3B800000,
829 LoadStorePairOffsetMask = 0xFFC00000,
830 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \
831 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
832 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET)
833 #undef LOAD_STORE_PAIR_OFFSET
834 };
835
836 enum LoadStorePairNonTemporalOp {
837 LoadStorePairNonTemporalFixed = 0x28000000,
838 LoadStorePairNonTemporalFMask = 0x3B800000,
839 LoadStorePairNonTemporalMask = 0xFFC00000,
840 LoadStorePairNonTemporalLBit = 1 << 22,
841 STNP_w = LoadStorePairNonTemporalFixed | STP_w,
842 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w,
843 STNP_x = LoadStorePairNonTemporalFixed | STP_x,
844 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x,
845 STNP_s = LoadStorePairNonTemporalFixed | STP_s,
846 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s,
847 STNP_d = LoadStorePairNonTemporalFixed | STP_d,
848 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d,
849 STNP_q = LoadStorePairNonTemporalFixed | STP_q,
850 LDNP_q = LoadStorePairNonTemporalFixed | LDP_q
851 };
852
853 // Load literal.
854 enum LoadLiteralOp {
855 LoadLiteralFixed = 0x18000000,
856 LoadLiteralFMask = 0x3B000000,
857 LoadLiteralMask = 0xFF000000,
858 LDR_w_lit = LoadLiteralFixed | 0x00000000,
859 LDR_x_lit = LoadLiteralFixed | 0x40000000,
860 LDRSW_x_lit = LoadLiteralFixed | 0x80000000,
861 PRFM_lit = LoadLiteralFixed | 0xC0000000,
862 LDR_s_lit = LoadLiteralFixed | 0x04000000,
863 LDR_d_lit = LoadLiteralFixed | 0x44000000,
864 LDR_q_lit = LoadLiteralFixed | 0x84000000
865 };
866
867 #define LOAD_STORE_OP_LIST(V) \
868 V(ST, RB, w, 0x00000000), \
869 V(ST, RH, w, 0x40000000), \
870 V(ST, R, w, 0x80000000), \
871 V(ST, R, x, 0xC0000000), \
872 V(LD, RB, w, 0x00400000), \
873 V(LD, RH, w, 0x40400000), \
874 V(LD, R, w, 0x80400000), \
875 V(LD, R, x, 0xC0400000), \
876 V(LD, RSB, x, 0x00800000), \
877 V(LD, RSH, x, 0x40800000), \
878 V(LD, RSW, x, 0x80800000), \
879 V(LD, RSB, w, 0x00C00000), \
880 V(LD, RSH, w, 0x40C00000), \
881 V(ST, R, b, 0x04000000), \
882 V(ST, R, h, 0x44000000), \
883 V(ST, R, s, 0x84000000), \
884 V(ST, R, d, 0xC4000000), \
885 V(ST, R, q, 0x04800000), \
886 V(LD, R, b, 0x04400000), \
887 V(LD, R, h, 0x44400000), \
888 V(LD, R, s, 0x84400000), \
889 V(LD, R, d, 0xC4400000), \
890 V(LD, R, q, 0x04C00000)
891
892 // Load/store (post, pre, offset and unsigned.)
893 enum LoadStoreOp {
894 LoadStoreMask = 0xC4C00000,
895 LoadStoreVMask = 0x04000000,
896 #define LOAD_STORE(A, B, C, D) \
897 A##B##_##C = D
898 LOAD_STORE_OP_LIST(LOAD_STORE),
899 #undef LOAD_STORE
900 PRFM = 0xC0800000
901 };
902
903 // Load/store unscaled offset.
904 enum LoadStoreUnscaledOffsetOp {
905 LoadStoreUnscaledOffsetFixed = 0x38000000,
906 LoadStoreUnscaledOffsetFMask = 0x3B200C00,
907 LoadStoreUnscaledOffsetMask = 0xFFE00C00,
908 PRFUM = LoadStoreUnscaledOffsetFixed | PRFM,
909 #define LOAD_STORE_UNSCALED(A, B, C, D) \
910 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
911 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
912 #undef LOAD_STORE_UNSCALED
913 };
914
915 // Load/store post index.
916 enum LoadStorePostIndex {
917 LoadStorePostIndexFixed = 0x38000400,
918 LoadStorePostIndexFMask = 0x3B200C00,
919 LoadStorePostIndexMask = 0xFFE00C00,
920 #define LOAD_STORE_POST_INDEX(A, B, C, D) \
921 A##B##_##C##_post = LoadStorePostIndexFixed | D
922 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX)
923 #undef LOAD_STORE_POST_INDEX
924 };
925
926 // Load/store pre index.
927 enum LoadStorePreIndex {
928 LoadStorePreIndexFixed = 0x38000C00,
929 LoadStorePreIndexFMask = 0x3B200C00,
930 LoadStorePreIndexMask = 0xFFE00C00,
931 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \
932 A##B##_##C##_pre = LoadStorePreIndexFixed | D
933 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX)
934 #undef LOAD_STORE_PRE_INDEX
935 };
936
937 // Load/store unsigned offset.
938 enum LoadStoreUnsignedOffset {
939 LoadStoreUnsignedOffsetFixed = 0x39000000,
940 LoadStoreUnsignedOffsetFMask = 0x3B000000,
941 LoadStoreUnsignedOffsetMask = 0xFFC00000,
942 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM,
943 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
944 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
945 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET)
946 #undef LOAD_STORE_UNSIGNED_OFFSET
947 };
948
949 // Load/store register offset.
950 enum LoadStoreRegisterOffset {
951 LoadStoreRegisterOffsetFixed = 0x38200800,
952 LoadStoreRegisterOffsetFMask = 0x3B200C00,
953 LoadStoreRegisterOffsetMask = 0xFFE00C00,
954 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM,
955 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
956 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
957 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
958 #undef LOAD_STORE_REGISTER_OFFSET
959 };
960
961 enum LoadStoreExclusive {
962 LoadStoreExclusiveFixed = 0x08000000,
963 LoadStoreExclusiveFMask = 0x3F000000,
964 LoadStoreExclusiveMask = 0xFFE08000,
965 STXRB_w = LoadStoreExclusiveFixed | 0x00000000,
966 STXRH_w = LoadStoreExclusiveFixed | 0x40000000,
967 STXR_w = LoadStoreExclusiveFixed | 0x80000000,
968 STXR_x = LoadStoreExclusiveFixed | 0xC0000000,
969 LDXRB_w = LoadStoreExclusiveFixed | 0x00400000,
970 LDXRH_w = LoadStoreExclusiveFixed | 0x40400000,
971 LDXR_w = LoadStoreExclusiveFixed | 0x80400000,
972 LDXR_x = LoadStoreExclusiveFixed | 0xC0400000,
973 STXP_w = LoadStoreExclusiveFixed | 0x80200000,
974 STXP_x = LoadStoreExclusiveFixed | 0xC0200000,
975 LDXP_w = LoadStoreExclusiveFixed | 0x80600000,
976 LDXP_x = LoadStoreExclusiveFixed | 0xC0600000,
977 STLXRB_w = LoadStoreExclusiveFixed | 0x00008000,
978 STLXRH_w = LoadStoreExclusiveFixed | 0x40008000,
979 STLXR_w = LoadStoreExclusiveFixed | 0x80008000,
980 STLXR_x = LoadStoreExclusiveFixed | 0xC0008000,
981 LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000,
982 LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000,
983 LDAXR_w = LoadStoreExclusiveFixed | 0x80408000,
984 LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000,
985 STLXP_w = LoadStoreExclusiveFixed | 0x80208000,
986 STLXP_x = LoadStoreExclusiveFixed | 0xC0208000,
987 LDAXP_w = LoadStoreExclusiveFixed | 0x80608000,
988 LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000,
989 STLRB_w = LoadStoreExclusiveFixed | 0x00808000,
990 STLRH_w = LoadStoreExclusiveFixed | 0x40808000,
991 STLR_w = LoadStoreExclusiveFixed | 0x80808000,
992 STLR_x = LoadStoreExclusiveFixed | 0xC0808000,
993 LDARB_w = LoadStoreExclusiveFixed | 0x00C08000,
994 LDARH_w = LoadStoreExclusiveFixed | 0x40C08000,
995 LDAR_w = LoadStoreExclusiveFixed | 0x80C08000,
996 LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000
997 };
998
999 // Conditional compare.
1000 enum ConditionalCompareOp {
1001 ConditionalCompareMask = 0x60000000,
1002 CCMN = 0x20000000,
1003 CCMP = 0x60000000
1004 };
1005
1006 // Conditional compare register.
1007 enum ConditionalCompareRegisterOp {
1008 ConditionalCompareRegisterFixed = 0x1A400000,
1009 ConditionalCompareRegisterFMask = 0x1FE00800,
1010 ConditionalCompareRegisterMask = 0xFFE00C10,
1011 CCMN_w = ConditionalCompareRegisterFixed | CCMN,
1012 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN,
1013 CCMP_w = ConditionalCompareRegisterFixed | CCMP,
1014 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
1015 };
1016
1017 // Conditional compare immediate.
1018 enum ConditionalCompareImmediateOp {
1019 ConditionalCompareImmediateFixed = 0x1A400800,
1020 ConditionalCompareImmediateFMask = 0x1FE00800,
1021 ConditionalCompareImmediateMask = 0xFFE00C10,
1022 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
1023 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN,
1024 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP,
1025 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
1026 };
1027
1028 // Conditional select.
1029 enum ConditionalSelectOp {
1030 ConditionalSelectFixed = 0x1A800000,
1031 ConditionalSelectFMask = 0x1FE00000,
1032 ConditionalSelectMask = 0xFFE00C00,
1033 CSEL_w = ConditionalSelectFixed | 0x00000000,
1034 CSEL_x = ConditionalSelectFixed | 0x80000000,
1035 CSEL = CSEL_w,
1036 CSINC_w = ConditionalSelectFixed | 0x00000400,
1037 CSINC_x = ConditionalSelectFixed | 0x80000400,
1038 CSINC = CSINC_w,
1039 CSINV_w = ConditionalSelectFixed | 0x40000000,
1040 CSINV_x = ConditionalSelectFixed | 0xC0000000,
1041 CSINV = CSINV_w,
1042 CSNEG_w = ConditionalSelectFixed | 0x40000400,
1043 CSNEG_x = ConditionalSelectFixed | 0xC0000400,
1044 CSNEG = CSNEG_w
1045 };
1046
1047 // Data processing 1 source.
1048 enum DataProcessing1SourceOp {
1049 DataProcessing1SourceFixed = 0x5AC00000,
1050 DataProcessing1SourceFMask = 0x5FE00000,
1051 DataProcessing1SourceMask = 0xFFFFFC00,
1052 RBIT = DataProcessing1SourceFixed | 0x00000000,
1053 RBIT_w = RBIT,
1054 RBIT_x = RBIT | SixtyFourBits,
1055 REV16 = DataProcessing1SourceFixed | 0x00000400,
1056 REV16_w = REV16,
1057 REV16_x = REV16 | SixtyFourBits,
1058 REV = DataProcessing1SourceFixed | 0x00000800,
1059 REV_w = REV,
1060 REV32_x = REV | SixtyFourBits,
1061 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00,
1062 CLZ = DataProcessing1SourceFixed | 0x00001000,
1063 CLZ_w = CLZ,
1064 CLZ_x = CLZ | SixtyFourBits,
1065 CLS = DataProcessing1SourceFixed | 0x00001400,
1066 CLS_w = CLS,
1067 CLS_x = CLS | SixtyFourBits
1068 };
1069
1070 // Data processing 2 source.
1071 enum DataProcessing2SourceOp {
1072 DataProcessing2SourceFixed = 0x1AC00000,
1073 DataProcessing2SourceFMask = 0x5FE00000,
1074 DataProcessing2SourceMask = 0xFFE0FC00,
1075 UDIV_w = DataProcessing2SourceFixed | 0x00000800,
1076 UDIV_x = DataProcessing2SourceFixed | 0x80000800,
1077 UDIV = UDIV_w,
1078 SDIV_w = DataProcessing2SourceFixed | 0x00000C00,
1079 SDIV_x = DataProcessing2SourceFixed | 0x80000C00,
1080 SDIV = SDIV_w,
1081 LSLV_w = DataProcessing2SourceFixed | 0x00002000,
1082 LSLV_x = DataProcessing2SourceFixed | 0x80002000,
1083 LSLV = LSLV_w,
1084 LSRV_w = DataProcessing2SourceFixed | 0x00002400,
1085 LSRV_x = DataProcessing2SourceFixed | 0x80002400,
1086 LSRV = LSRV_w,
1087 ASRV_w = DataProcessing2SourceFixed | 0x00002800,
1088 ASRV_x = DataProcessing2SourceFixed | 0x80002800,
1089 ASRV = ASRV_w,
1090 RORV_w = DataProcessing2SourceFixed | 0x00002C00,
1091 RORV_x = DataProcessing2SourceFixed | 0x80002C00,
1092 RORV = RORV_w,
1093 CRC32B = DataProcessing2SourceFixed | 0x00004000,
1094 CRC32H = DataProcessing2SourceFixed | 0x00004400,
1095 CRC32W = DataProcessing2SourceFixed | 0x00004800,
1096 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00,
1097 CRC32CB = DataProcessing2SourceFixed | 0x00005000,
1098 CRC32CH = DataProcessing2SourceFixed | 0x00005400,
1099 CRC32CW = DataProcessing2SourceFixed | 0x00005800,
1100 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
1101 };
1102
1103 // Data processing 3 source.
1104 enum DataProcessing3SourceOp {
1105 DataProcessing3SourceFixed = 0x1B000000,
1106 DataProcessing3SourceFMask = 0x1F000000,
1107 DataProcessing3SourceMask = 0xFFE08000,
1108 MADD_w = DataProcessing3SourceFixed | 0x00000000,
1109 MADD_x = DataProcessing3SourceFixed | 0x80000000,
1110 MADD = MADD_w,
1111 MSUB_w = DataProcessing3SourceFixed | 0x00008000,
1112 MSUB_x = DataProcessing3SourceFixed | 0x80008000,
1113 MSUB = MSUB_w,
1114 SMADDL_x = DataProcessing3SourceFixed | 0x80200000,
1115 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000,
1116 SMULH_x = DataProcessing3SourceFixed | 0x80400000,
1117 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000,
1118 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000,
1119 UMULH_x = DataProcessing3SourceFixed | 0x80C00000
1120 };
1121
1122 // Floating point compare.
1123 enum FPCompareOp {
1124 FPCompareFixed = 0x1E202000,
1125 FPCompareFMask = 0x5F203C00,
1126 FPCompareMask = 0xFFE0FC1F,
1127 FCMP_s = FPCompareFixed | 0x00000000,
1128 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1129 FCMP = FCMP_s,
1130 FCMP_s_zero = FPCompareFixed | 0x00000008,
1131 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1132 FCMP_zero = FCMP_s_zero,
1133 FCMPE_s = FPCompareFixed | 0x00000010,
1134 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1135 FCMPE = FCMPE_s,
1136 FCMPE_s_zero = FPCompareFixed | 0x00000018,
1137 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018,
1138 FCMPE_zero = FCMPE_s_zero
1139 };
1140
1141 // Floating point conditional compare.
1142 enum FPConditionalCompareOp {
1143 FPConditionalCompareFixed = 0x1E200400,
1144 FPConditionalCompareFMask = 0x5F200C00,
1145 FPConditionalCompareMask = 0xFFE00C10,
1146 FCCMP_s = FPConditionalCompareFixed | 0x00000000,
1147 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1148 FCCMP = FCCMP_s,
1149 FCCMPE_s = FPConditionalCompareFixed | 0x00000010,
1150 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1151 FCCMPE = FCCMPE_s
1152 };
1153
1154 // Floating point conditional select.
1155 enum FPConditionalSelectOp {
1156 FPConditionalSelectFixed = 0x1E200C00,
1157 FPConditionalSelectFMask = 0x5F200C00,
1158 FPConditionalSelectMask = 0xFFE00C00,
1159 FCSEL_s = FPConditionalSelectFixed | 0x00000000,
1160 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1161 FCSEL = FCSEL_s
1162 };
1163
1164 // Floating point immediate.
1165 enum FPImmediateOp {
1166 FPImmediateFixed = 0x1E201000,
1167 FPImmediateFMask = 0x5F201C00,
1168 FPImmediateMask = 0xFFE01C00,
1169 FMOV_s_imm = FPImmediateFixed | 0x00000000,
1170 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
1171 };
1172
1173 // Floating point data processing 1 source.
1174 enum FPDataProcessing1SourceOp {
1175 FPDataProcessing1SourceFixed = 0x1E204000,
1176 FPDataProcessing1SourceFMask = 0x5F207C00,
1177 FPDataProcessing1SourceMask = 0xFFFFFC00,
1178 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
1179 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
1180 FMOV = FMOV_s,
1181 FABS_s = FPDataProcessing1SourceFixed | 0x00008000,
1182 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
1183 FABS = FABS_s,
1184 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000,
1185 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
1186 FNEG = FNEG_s,
1187 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000,
1188 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
1189 FSQRT = FSQRT_s,
1190 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
1191 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
1192 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000,
1193 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000,
1194 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000,
1195 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000,
1196 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
1197 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
1198 FRINTN = FRINTN_s,
1199 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
1200 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
1201 FRINTP = FRINTP_s,
1202 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
1203 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
1204 FRINTM = FRINTM_s,
1205 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
1206 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
1207 FRINTZ = FRINTZ_s,
1208 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
1209 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
1210 FRINTA = FRINTA_s,
1211 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
1212 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
1213 FRINTX = FRINTX_s,
1214 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
1215 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
1216 FRINTI = FRINTI_s
1217 };
1218
1219 // Floating point data processing 2 source.
1220 enum FPDataProcessing2SourceOp {
1221 FPDataProcessing2SourceFixed = 0x1E200800,
1222 FPDataProcessing2SourceFMask = 0x5F200C00,
1223 FPDataProcessing2SourceMask = 0xFFE0FC00,
1224 FMUL = FPDataProcessing2SourceFixed | 0x00000000,
1225 FMUL_s = FMUL,
1226 FMUL_d = FMUL | FP64,
1227 FDIV = FPDataProcessing2SourceFixed | 0x00001000,
1228 FDIV_s = FDIV,
1229 FDIV_d = FDIV | FP64,
1230 FADD = FPDataProcessing2SourceFixed | 0x00002000,
1231 FADD_s = FADD,
1232 FADD_d = FADD | FP64,
1233 FSUB = FPDataProcessing2SourceFixed | 0x00003000,
1234 FSUB_s = FSUB,
1235 FSUB_d = FSUB | FP64,
1236 FMAX = FPDataProcessing2SourceFixed | 0x00004000,
1237 FMAX_s = FMAX,
1238 FMAX_d = FMAX | FP64,
1239 FMIN = FPDataProcessing2SourceFixed | 0x00005000,
1240 FMIN_s = FMIN,
1241 FMIN_d = FMIN | FP64,
1242 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000,
1243 FMAXNM_s = FMAXNM,
1244 FMAXNM_d = FMAXNM | FP64,
1245 FMINNM = FPDataProcessing2SourceFixed | 0x00007000,
1246 FMINNM_s = FMINNM,
1247 FMINNM_d = FMINNM | FP64,
1248 FNMUL = FPDataProcessing2SourceFixed | 0x00008000,
1249 FNMUL_s = FNMUL,
1250 FNMUL_d = FNMUL | FP64
1251 };
1252
1253 // Floating point data processing 3 source.
1254 enum FPDataProcessing3SourceOp {
1255 FPDataProcessing3SourceFixed = 0x1F000000,
1256 FPDataProcessing3SourceFMask = 0x5F000000,
1257 FPDataProcessing3SourceMask = 0xFFE08000,
1258 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000,
1259 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000,
1260 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000,
1261 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000,
1262 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000,
1263 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000,
1264 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000,
1265 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000
1266 };
1267
1268 // Conversion between floating point and integer.
1269 enum FPIntegerConvertOp {
1270 FPIntegerConvertFixed = 0x1E200000,
1271 FPIntegerConvertFMask = 0x5F20FC00,
1272 FPIntegerConvertMask = 0xFFFFFC00,
1273 FCVTNS = FPIntegerConvertFixed | 0x00000000,
1274 FCVTNS_ws = FCVTNS,
1275 FCVTNS_xs = FCVTNS | SixtyFourBits,
1276 FCVTNS_wd = FCVTNS | FP64,
1277 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
1278 FCVTNU = FPIntegerConvertFixed | 0x00010000,
1279 FCVTNU_ws = FCVTNU,
1280 FCVTNU_xs = FCVTNU | SixtyFourBits,
1281 FCVTNU_wd = FCVTNU | FP64,
1282 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
1283 FCVTPS = FPIntegerConvertFixed | 0x00080000,
1284 FCVTPS_ws = FCVTPS,
1285 FCVTPS_xs = FCVTPS | SixtyFourBits,
1286 FCVTPS_wd = FCVTPS | FP64,
1287 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
1288 FCVTPU = FPIntegerConvertFixed | 0x00090000,
1289 FCVTPU_ws = FCVTPU,
1290 FCVTPU_xs = FCVTPU | SixtyFourBits,
1291 FCVTPU_wd = FCVTPU | FP64,
1292 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
1293 FCVTMS = FPIntegerConvertFixed | 0x00100000,
1294 FCVTMS_ws = FCVTMS,
1295 FCVTMS_xs = FCVTMS | SixtyFourBits,
1296 FCVTMS_wd = FCVTMS | FP64,
1297 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
1298 FCVTMU = FPIntegerConvertFixed | 0x00110000,
1299 FCVTMU_ws = FCVTMU,
1300 FCVTMU_xs = FCVTMU | SixtyFourBits,
1301 FCVTMU_wd = FCVTMU | FP64,
1302 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
1303 FCVTZS = FPIntegerConvertFixed | 0x00180000,
1304 FCVTZS_ws = FCVTZS,
1305 FCVTZS_xs = FCVTZS | SixtyFourBits,
1306 FCVTZS_wd = FCVTZS | FP64,
1307 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
1308 FCVTZU = FPIntegerConvertFixed | 0x00190000,
1309 FCVTZU_ws = FCVTZU,
1310 FCVTZU_xs = FCVTZU | SixtyFourBits,
1311 FCVTZU_wd = FCVTZU | FP64,
1312 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
1313 SCVTF = FPIntegerConvertFixed | 0x00020000,
1314 SCVTF_sw = SCVTF,
1315 SCVTF_sx = SCVTF | SixtyFourBits,
1316 SCVTF_dw = SCVTF | FP64,
1317 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
1318 UCVTF = FPIntegerConvertFixed | 0x00030000,
1319 UCVTF_sw = UCVTF,
1320 UCVTF_sx = UCVTF | SixtyFourBits,
1321 UCVTF_dw = UCVTF | FP64,
1322 UCVTF_dx = UCVTF | SixtyFourBits | FP64,
1323 FCVTAS = FPIntegerConvertFixed | 0x00040000,
1324 FCVTAS_ws = FCVTAS,
1325 FCVTAS_xs = FCVTAS | SixtyFourBits,
1326 FCVTAS_wd = FCVTAS | FP64,
1327 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
1328 FCVTAU = FPIntegerConvertFixed | 0x00050000,
1329 FCVTAU_ws = FCVTAU,
1330 FCVTAU_xs = FCVTAU | SixtyFourBits,
1331 FCVTAU_wd = FCVTAU | FP64,
1332 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
1333 FMOV_ws = FPIntegerConvertFixed | 0x00060000,
1334 FMOV_sw = FPIntegerConvertFixed | 0x00070000,
1335 FMOV_xd = FMOV_ws | SixtyFourBits | FP64,
1336 FMOV_dx = FMOV_sw | SixtyFourBits | FP64,
1337 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000,
1338 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000
1339 };
1340
1341 // Conversion between fixed point and floating point.
1342 enum FPFixedPointConvertOp {
1343 FPFixedPointConvertFixed = 0x1E000000,
1344 FPFixedPointConvertFMask = 0x5F200000,
1345 FPFixedPointConvertMask = 0xFFFF0000,
1346 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000,
1347 FCVTZS_ws_fixed = FCVTZS_fixed,
1348 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
1349 FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
1350 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
1351 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000,
1352 FCVTZU_ws_fixed = FCVTZU_fixed,
1353 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
1354 FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
1355 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
1356 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000,
1357 SCVTF_sw_fixed = SCVTF_fixed,
1358 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits,
1359 SCVTF_dw_fixed = SCVTF_fixed | FP64,
1360 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64,
1361 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000,
1362 UCVTF_sw_fixed = UCVTF_fixed,
1363 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits,
1364 UCVTF_dw_fixed = UCVTF_fixed | FP64,
1365 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64
1366 };
1367
1368 // Crypto - two register SHA.
1369 enum Crypto2RegSHAOp {
1370 Crypto2RegSHAFixed = 0x5E280800,
1371 Crypto2RegSHAFMask = 0xFF3E0C00
1372 };
1373
1374 // Crypto - three register SHA.
1375 enum Crypto3RegSHAOp {
1376 Crypto3RegSHAFixed = 0x5E000000,
1377 Crypto3RegSHAFMask = 0xFF208C00
1378 };
1379
1380 // Crypto - AES.
1381 enum CryptoAESOp {
1382 CryptoAESFixed = 0x4E280800,
1383 CryptoAESFMask = 0xFF3E0C00
1384 };
1385
1386 // NEON instructions with two register operands.
1387 enum NEON2RegMiscOp {
1388 NEON2RegMiscFixed = 0x0E200800,
1389 NEON2RegMiscFMask = 0x9F3E0C00,
1390 NEON2RegMiscMask = 0xBF3FFC00,
1391 NEON2RegMiscUBit = 0x20000000,
1392 NEON_REV64 = NEON2RegMiscFixed | 0x00000000,
1393 NEON_REV32 = NEON2RegMiscFixed | 0x20000000,
1394 NEON_REV16 = NEON2RegMiscFixed | 0x00001000,
1395 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000,
1396 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit,
1397 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000,
1398 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit,
1399 NEON_CLS = NEON2RegMiscFixed | 0x00004000,
1400 NEON_CLZ = NEON2RegMiscFixed | 0x20004000,
1401 NEON_CNT = NEON2RegMiscFixed | 0x00005000,
1402 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000,
1403 NEON_SADALP = NEON2RegMiscFixed | 0x00006000,
1404 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit,
1405 NEON_SQABS = NEON2RegMiscFixed | 0x00007000,
1406 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000,
1407 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000,
1408 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000,
1409 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000,
1410 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000,
1411 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000,
1412 NEON_ABS = NEON2RegMiscFixed | 0x0000B000,
1413 NEON_NEG = NEON2RegMiscFixed | 0x2000B000,
1414 NEON_XTN = NEON2RegMiscFixed | 0x00012000,
1415 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000,
1416 NEON_SHLL = NEON2RegMiscFixed | 0x20013000,
1417 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000,
1418 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit,
1419
1420 NEON2RegMiscOpcode = 0x0001F000,
1421 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode,
1422 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode,
1423 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode,
1424 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode,
1425
1426 // These instructions use only one bit of the size field. The other bit is
1427 // used to distinguish between instructions.
1428 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000,
1429 NEON_FABS = NEON2RegMiscFixed | 0x0080F000,
1430 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000,
1431 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000,
1432 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000,
1433 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000,
1434 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000,
1435 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000,
1436 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000,
1437 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000,
1438 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000,
1439 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000,
1440 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000,
1441 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000,
1442 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit,
1443 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000,
1444 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit,
1445 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000,
1446 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit,
1447 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000,
1448 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit,
1449 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000,
1450 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit,
1451 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000,
1452 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000,
1453 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit,
1454 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000,
1455 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000,
1456 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000,
1457 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000,
1458 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000,
1459 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000,
1460 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000,
1461 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000,
1462 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000,
1463
1464 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode,
1465 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode
1466 };
1467
1468 // NEON instructions with three same-type operands.
1469 enum NEON3SameOp {
1470 NEON3SameFixed = 0x0E200400,
1471 NEON3SameFMask = 0x9F200400,
1472 NEON3SameMask = 0xBF20FC00,
1473 NEON3SameUBit = 0x20000000,
1474 NEON_ADD = NEON3SameFixed | 0x00008000,
1475 NEON_ADDP = NEON3SameFixed | 0x0000B800,
1476 NEON_SHADD = NEON3SameFixed | 0x00000000,
1477 NEON_SHSUB = NEON3SameFixed | 0x00002000,
1478 NEON_SRHADD = NEON3SameFixed | 0x00001000,
1479 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800,
1480 NEON_CMGE = NEON3SameFixed | 0x00003800,
1481 NEON_CMGT = NEON3SameFixed | 0x00003000,
1482 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT,
1483 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE,
1484 NEON_CMTST = NEON3SameFixed | 0x00008800,
1485 NEON_MLA = NEON3SameFixed | 0x00009000,
1486 NEON_MLS = NEON3SameFixed | 0x20009000,
1487 NEON_MUL = NEON3SameFixed | 0x00009800,
1488 NEON_PMUL = NEON3SameFixed | 0x20009800,
1489 NEON_SRSHL = NEON3SameFixed | 0x00005000,
1490 NEON_SQSHL = NEON3SameFixed | 0x00004800,
1491 NEON_SQRSHL = NEON3SameFixed | 0x00005800,
1492 NEON_SSHL = NEON3SameFixed | 0x00004000,
1493 NEON_SMAX = NEON3SameFixed | 0x00006000,
1494 NEON_SMAXP = NEON3SameFixed | 0x0000A000,
1495 NEON_SMIN = NEON3SameFixed | 0x00006800,
1496 NEON_SMINP = NEON3SameFixed | 0x0000A800,
1497 NEON_SABD = NEON3SameFixed | 0x00007000,
1498 NEON_SABA = NEON3SameFixed | 0x00007800,
1499 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD,
1500 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA,
1501 NEON_SQADD = NEON3SameFixed | 0x00000800,
1502 NEON_SQSUB = NEON3SameFixed | 0x00002800,
1503 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000,
1504 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD,
1505 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB,
1506 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD,
1507 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX,
1508 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP,
1509 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN,
1510 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP,
1511 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL,
1512 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD,
1513 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL,
1514 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL,
1515 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB,
1516 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL,
1517 NEON_SQDMULH = NEON3SameFixed | 0x0000B000,
1518 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000,
1519
1520 // NEON floating point instructions with three same-type operands.
1521 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000,
1522 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000,
1523 NEON3SameFPMask = NEON3SameMask | 0x00800000,
1524 NEON_FADD = NEON3SameFixed | 0x0000D000,
1525 NEON_FSUB = NEON3SameFixed | 0x0080D000,
1526 NEON_FMUL = NEON3SameFixed | 0x2000D800,
1527 NEON_FDIV = NEON3SameFixed | 0x2000F800,
1528 NEON_FMAX = NEON3SameFixed | 0x0000F000,
1529 NEON_FMAXNM = NEON3SameFixed | 0x0000C000,
1530 NEON_FMAXP = NEON3SameFixed | 0x2000F000,
1531 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000,
1532 NEON_FMIN = NEON3SameFixed | 0x0080F000,
1533 NEON_FMINNM = NEON3SameFixed | 0x0080C000,
1534 NEON_FMINP = NEON3SameFixed | 0x2080F000,
1535 NEON_FMINNMP = NEON3SameFixed | 0x2080C000,
1536 NEON_FMLA = NEON3SameFixed | 0x0000C800,
1537 NEON_FMLS = NEON3SameFixed | 0x0080C800,
1538 NEON_FMULX = NEON3SameFixed | 0x0000D800,
1539 NEON_FRECPS = NEON3SameFixed | 0x0000F800,
1540 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800,
1541 NEON_FABD = NEON3SameFixed | 0x2080D000,
1542 NEON_FADDP = NEON3SameFixed | 0x2000D000,
1543 NEON_FCMEQ = NEON3SameFixed | 0x0000E000,
1544 NEON_FCMGE = NEON3SameFixed | 0x2000E000,
1545 NEON_FCMGT = NEON3SameFixed | 0x2080E000,
1546 NEON_FACGE = NEON3SameFixed | 0x2000E800,
1547 NEON_FACGT = NEON3SameFixed | 0x2080E800,
1548
1549 // NEON logical instructions with three same-type operands.
1550 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800,
1551 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800,
1552 NEON3SameLogicalMask = 0xBFE0FC00,
1553 NEON3SameLogicalFormatMask = NEON_Q,
1554 NEON_AND = NEON3SameLogicalFixed | 0x00000000,
1555 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000,
1556 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000,
1557 NEON_EOR = NEON3SameLogicalFixed | 0x20000000,
1558 NEON_BIC = NEON3SameLogicalFixed | 0x00400000,
1559 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000,
1560 NEON_BIT = NEON3SameLogicalFixed | 0x20800000,
1561 NEON_BSL = NEON3SameLogicalFixed | 0x20400000
1562 };
1563
1564 // NEON instructions with three different-type operands.
1565 enum NEON3DifferentOp {
1566 NEON3DifferentFixed = 0x0E200000,
1567 NEON3DifferentFMask = 0x9F200C00,
1568 NEON3DifferentMask = 0xFF20FC00,
1569 NEON_ADDHN = NEON3DifferentFixed | 0x00004000,
1570 NEON_ADDHN2 = NEON_ADDHN | NEON_Q,
1571 NEON_PMULL = NEON3DifferentFixed | 0x0000E000,
1572 NEON_PMULL2 = NEON_PMULL | NEON_Q,
1573 NEON_RADDHN = NEON3DifferentFixed | 0x20004000,
1574 NEON_RADDHN2 = NEON_RADDHN | NEON_Q,
1575 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000,
1576 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q,
1577 NEON_SABAL = NEON3DifferentFixed | 0x00005000,
1578 NEON_SABAL2 = NEON_SABAL | NEON_Q,
1579 NEON_SABDL = NEON3DifferentFixed | 0x00007000,
1580 NEON_SABDL2 = NEON_SABDL | NEON_Q,
1581 NEON_SADDL = NEON3DifferentFixed | 0x00000000,
1582 NEON_SADDL2 = NEON_SADDL | NEON_Q,
1583 NEON_SADDW = NEON3DifferentFixed | 0x00001000,
1584 NEON_SADDW2 = NEON_SADDW | NEON_Q,
1585 NEON_SMLAL = NEON3DifferentFixed | 0x00008000,
1586 NEON_SMLAL2 = NEON_SMLAL | NEON_Q,
1587 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000,
1588 NEON_SMLSL2 = NEON_SMLSL | NEON_Q,
1589 NEON_SMULL = NEON3DifferentFixed | 0x0000C000,
1590 NEON_SMULL2 = NEON_SMULL | NEON_Q,
1591 NEON_SSUBL = NEON3DifferentFixed | 0x00002000,
1592 NEON_SSUBL2 = NEON_SSUBL | NEON_Q,
1593 NEON_SSUBW = NEON3DifferentFixed | 0x00003000,
1594 NEON_SSUBW2 = NEON_SSUBW | NEON_Q,
1595 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000,
1596 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q,
1597 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000,
1598 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q,
1599 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000,
1600 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q,
1601 NEON_SUBHN = NEON3DifferentFixed | 0x00006000,
1602 NEON_SUBHN2 = NEON_SUBHN | NEON_Q,
1603 NEON_UABAL = NEON_SABAL | NEON3SameUBit,
1604 NEON_UABAL2 = NEON_UABAL | NEON_Q,
1605 NEON_UABDL = NEON_SABDL | NEON3SameUBit,
1606 NEON_UABDL2 = NEON_UABDL | NEON_Q,
1607 NEON_UADDL = NEON_SADDL | NEON3SameUBit,
1608 NEON_UADDL2 = NEON_UADDL | NEON_Q,
1609 NEON_UADDW = NEON_SADDW | NEON3SameUBit,
1610 NEON_UADDW2 = NEON_UADDW | NEON_Q,
1611 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit,
1612 NEON_UMLAL2 = NEON_UMLAL | NEON_Q,
1613 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit,
1614 NEON_UMLSL2 = NEON_UMLSL | NEON_Q,
1615 NEON_UMULL = NEON_SMULL | NEON3SameUBit,
1616 NEON_UMULL2 = NEON_UMULL | NEON_Q,
1617 NEON_USUBL = NEON_SSUBL | NEON3SameUBit,
1618 NEON_USUBL2 = NEON_USUBL | NEON_Q,
1619 NEON_USUBW = NEON_SSUBW | NEON3SameUBit,
1620 NEON_USUBW2 = NEON_USUBW | NEON_Q
1621 };
1622
1623 // NEON instructions operating across vectors.
1624 enum NEONAcrossLanesOp {
1625 NEONAcrossLanesFixed = 0x0E300800,
1626 NEONAcrossLanesFMask = 0x9F3E0C00,
1627 NEONAcrossLanesMask = 0xBF3FFC00,
1628 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000,
1629 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000,
1630 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000,
1631 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000,
1632 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000,
1633 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000,
1634 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000,
1635
1636 // NEON floating point across instructions.
1637 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x0000C000,
1638 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x0000C000,
1639 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x00800000,
1640
1641 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000,
1642 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000,
1643 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000,
1644 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000
1645 };
1646
1647 // NEON instructions with indexed element operand.
1648 enum NEONByIndexedElementOp {
1649 NEONByIndexedElementFixed = 0x0F000000,
1650 NEONByIndexedElementFMask = 0x9F000400,
1651 NEONByIndexedElementMask = 0xBF00F400,
1652 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000,
1653 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000,
1654 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000,
1655 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000,
1656 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000,
1657 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000,
1658 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000,
1659 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000,
1660 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000,
1661 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000,
1662 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000,
1663 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000,
1664 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000,
1665 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000,
1666
1667 // Floating point instructions.
1668 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000,
1669 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000,
1670 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000,
1671 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000,
1672 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000,
1673 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000
1674 };
1675
1676 // NEON register copy.
1677 enum NEONCopyOp {
1678 NEONCopyFixed = 0x0E000400,
1679 NEONCopyFMask = 0x9FE08400,
1680 NEONCopyMask = 0x3FE08400,
1681 NEONCopyInsElementMask = NEONCopyMask | 0x40000000,
1682 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800,
1683 NEONCopyDupElementMask = NEONCopyMask | 0x20007800,
1684 NEONCopyDupGeneralMask = NEONCopyDupElementMask,
1685 NEONCopyUmovMask = NEONCopyMask | 0x20007800,
1686 NEONCopySmovMask = NEONCopyMask | 0x20007800,
1687 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000,
1688 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800,
1689 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000,
1690 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800,
1691 NEON_SMOV = NEONCopyFixed | 0x00002800,
1692 NEON_UMOV = NEONCopyFixed | 0x00003800
1693 };
1694
1695 // NEON extract.
1696 enum NEONExtractOp {
1697 NEONExtractFixed = 0x2E000000,
1698 NEONExtractFMask = 0xBF208400,
1699 NEONExtractMask = 0xBFE08400,
1700 NEON_EXT = NEONExtractFixed | 0x00000000
1701 };
1702
1703 enum NEONLoadStoreMultiOp {
1704 NEONLoadStoreMultiL = 0x00400000,
1705 NEONLoadStoreMulti1_1v = 0x00007000,
1706 NEONLoadStoreMulti1_2v = 0x0000A000,
1707 NEONLoadStoreMulti1_3v = 0x00006000,
1708 NEONLoadStoreMulti1_4v = 0x00002000,
1709 NEONLoadStoreMulti2 = 0x00008000,
1710 NEONLoadStoreMulti3 = 0x00004000,
1711 NEONLoadStoreMulti4 = 0x00000000
1712 };
1713
1714 // NEON load/store multiple structures.
1715 enum NEONLoadStoreMultiStructOp {
1716 NEONLoadStoreMultiStructFixed = 0x0C000000,
1717 NEONLoadStoreMultiStructFMask = 0xBFBF0000,
1718 NEONLoadStoreMultiStructMask = 0xBFFFF000,
1719 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed,
1720 NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed |
1721 NEONLoadStoreMultiL,
1722 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v,
1723 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v,
1724 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v,
1725 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v,
1726 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2,
1727 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3,
1728 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4,
1729 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v,
1730 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v,
1731 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v,
1732 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v,
1733 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2,
1734 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3,
1735 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4
1736 };
1737
1738 // NEON load/store multiple structures with post-index addressing.
1739 enum NEONLoadStoreMultiStructPostIndexOp {
1740 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
1741 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
1742 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000,
1743 NEONLoadStoreMultiStructPostIndex = 0x00800000,
1744 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex,
1745 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex,
1746 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex,
1747 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex,
1748 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex,
1749 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex,
1750 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex,
1751 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex,
1752 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex,
1753 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex,
1754 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex,
1755 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex,
1756 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex,
1757 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
1758 };
1759
1760 enum NEONLoadStoreSingleOp {
1761 NEONLoadStoreSingle1 = 0x00000000,
1762 NEONLoadStoreSingle2 = 0x00200000,
1763 NEONLoadStoreSingle3 = 0x00002000,
1764 NEONLoadStoreSingle4 = 0x00202000,
1765 NEONLoadStoreSingleL = 0x00400000,
1766 NEONLoadStoreSingle_b = 0x00000000,
1767 NEONLoadStoreSingle_h = 0x00004000,
1768 NEONLoadStoreSingle_s = 0x00008000,
1769 NEONLoadStoreSingle_d = 0x00008400,
1770 NEONLoadStoreSingleAllLanes = 0x0000C000,
1771 NEONLoadStoreSingleLenMask = 0x00202000
1772 };
1773
1774 // NEON load/store single structure.
1775 enum NEONLoadStoreSingleStructOp {
1776 NEONLoadStoreSingleStructFixed = 0x0D000000,
1777 NEONLoadStoreSingleStructFMask = 0xBF9F0000,
1778 NEONLoadStoreSingleStructMask = 0xBFFFE000,
1779 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed,
1780 NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed |
1781 NEONLoadStoreSingleL,
1782 NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 |
1783 NEONLoadStoreSingleStructLoad,
1784 NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 |
1785 NEONLoadStoreSingleStructLoad,
1786 NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 |
1787 NEONLoadStoreSingleStructLoad,
1788 NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 |
1789 NEONLoadStoreSingleStructLoad,
1790 NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 |
1791 NEONLoadStoreSingleStructFixed,
1792 NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 |
1793 NEONLoadStoreSingleStructFixed,
1794 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 |
1795 NEONLoadStoreSingleStructFixed,
1796 NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 |
1797 NEONLoadStoreSingleStructFixed,
1798 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b,
1799 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h,
1800 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s,
1801 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d,
1802 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes,
1803 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b,
1804 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h,
1805 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s,
1806 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d,
1807
1808 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b,
1809 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h,
1810 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s,
1811 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d,
1812 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes,
1813 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b,
1814 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h,
1815 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s,
1816 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d,
1817
1818 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b,
1819 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h,
1820 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s,
1821 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d,
1822 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes,
1823 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b,
1824 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h,
1825 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s,
1826 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d,
1827
1828 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b,
1829 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h,
1830 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s,
1831 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d,
1832 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes,
1833 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b,
1834 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h,
1835 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s,
1836 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d
1837 };
1838
1839 // NEON load/store single structure with post-index addressing.
1840 enum NEONLoadStoreSingleStructPostIndexOp {
1841 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
1842 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
1843 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000,
1844 NEONLoadStoreSingleStructPostIndex = 0x00800000,
1845 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
1846 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
1847 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
1848 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex,
1849 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex,
1850 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex,
1851 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex,
1852 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex,
1853 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex,
1854
1855 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex,
1856 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex,
1857 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex,
1858 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex,
1859 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex,
1860 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex,
1861 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex,
1862 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex,
1863 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex,
1864
1865 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex,
1866 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex,
1867 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex,
1868 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex,
1869 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex,
1870 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex,
1871 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex,
1872 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex,
1873 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex,
1874
1875 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex,
1876 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex,
1877 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex,
1878 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex,
1879 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex,
1880 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex,
1881 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex,
1882 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex,
1883 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex
1884 };
1885
1886 // NEON modified immediate.
1887 enum NEONModifiedImmediateOp {
1888 NEONModifiedImmediateFixed = 0x0F000400,
1889 NEONModifiedImmediateFMask = 0x9FF80400,
1890 NEONModifiedImmediateOpBit = 0x20000000,
1891 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000,
1892 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000,
1893 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000,
1894 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000
1895 };
1896
1897 // NEON shift immediate.
1898 enum NEONShiftImmediateOp {
1899 NEONShiftImmediateFixed = 0x0F000400,
1900 NEONShiftImmediateFMask = 0x9F800400,
1901 NEONShiftImmediateMask = 0xBF80FC00,
1902 NEONShiftImmediateUBit = 0x20000000,
1903 NEON_SHL = NEONShiftImmediateFixed | 0x00005000,
1904 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000,
1905 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000,
1906 NEON_SLI = NEONShiftImmediateFixed | 0x20005000,
1907 NEON_SRI = NEONShiftImmediateFixed | 0x20004000,
1908 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000,
1909 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800,
1910 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000,
1911 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800,
1912 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000,
1913 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800,
1914 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000,
1915 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800,
1916 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000,
1917 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000,
1918 NEON_USHR = NEONShiftImmediateFixed | 0x20000000,
1919 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000,
1920 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000,
1921 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000,
1922 NEON_USRA = NEONShiftImmediateFixed | 0x20001000,
1923 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000,
1924 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000,
1925 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000,
1926 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000,
1927 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800,
1928 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800,
1929 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000,
1930 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000
1931 };
1932
1933 // NEON table.
1934 enum NEONTableOp {
1935 NEONTableFixed = 0x0E000000,
1936 NEONTableFMask = 0xBF208C00,
1937 NEONTableExt = 0x00001000,
1938 NEONTableMask = 0xBF20FC00,
1939 NEON_TBL_1v = NEONTableFixed | 0x00000000,
1940 NEON_TBL_2v = NEONTableFixed | 0x00002000,
1941 NEON_TBL_3v = NEONTableFixed | 0x00004000,
1942 NEON_TBL_4v = NEONTableFixed | 0x00006000,
1943 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt,
1944 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt,
1945 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt,
1946 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt
1947 };
1948
1949 // NEON perm.
1950 enum NEONPermOp {
1951 NEONPermFixed = 0x0E000800,
1952 NEONPermFMask = 0xBF208C00,
1953 NEONPermMask = 0x3F20FC00,
1954 NEON_UZP1 = NEONPermFixed | 0x00001000,
1955 NEON_TRN1 = NEONPermFixed | 0x00002000,
1956 NEON_ZIP1 = NEONPermFixed | 0x00003000,
1957 NEON_UZP2 = NEONPermFixed | 0x00005000,
1958 NEON_TRN2 = NEONPermFixed | 0x00006000,
1959 NEON_ZIP2 = NEONPermFixed | 0x00007000
1960 };
1961
1962 // NEON scalar instructions with two register operands.
1963 enum NEONScalar2RegMiscOp {
1964 NEONScalar2RegMiscFixed = 0x5E200800,
1965 NEONScalar2RegMiscFMask = 0xDF3E0C00,
1966 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
1967 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero,
1968 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero,
1969 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero,
1970 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero,
1971 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero,
1972 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS,
1973 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS,
1974 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG,
1975 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG,
1976 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN,
1977 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN,
1978 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN,
1979 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD,
1980 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD,
1981
1982 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode,
1983 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode,
1984
1985 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000,
1986 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE,
1987 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE,
1988 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF,
1989 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF,
1990 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero,
1991 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero,
1992 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero,
1993 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero,
1994 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero,
1995 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000,
1996 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS,
1997 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU,
1998 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS,
1999 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU,
2000 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS,
2001 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU,
2002 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS,
2003 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU,
2004 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS,
2005 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU,
2006 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN
2007 };
2008
2009 // NEON scalar instructions with three same-type operands.
2010 enum NEONScalar3SameOp {
2011 NEONScalar3SameFixed = 0x5E200400,
2012 NEONScalar3SameFMask = 0xDF200400,
2013 NEONScalar3SameMask = 0xFF20FC00,
2014 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD,
2015 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ,
2016 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE,
2017 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT,
2018 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI,
2019 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS,
2020 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST,
2021 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB,
2022 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD,
2023 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD,
2024 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB,
2025 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB,
2026 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL,
2027 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL,
2028 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL,
2029 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL,
2030 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL,
2031 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL,
2032 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL,
2033 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL,
2034 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH,
2035 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH,
2036
2037 // NEON floating point scalar instructions with three same-type operands.
2038 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000,
2039 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000,
2040 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000,
2041 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE,
2042 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT,
2043 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ,
2044 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE,
2045 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT,
2046 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX,
2047 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS,
2048 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS,
2049 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD
2050 };
2051
2052 // NEON scalar instructions with three different-type operands.
2053 enum NEONScalar3DiffOp {
2054 NEONScalar3DiffFixed = 0x5E200000,
2055 NEONScalar3DiffFMask = 0xDF200C00,
2056 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask,
2057 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL,
2058 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL,
2059 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL
2060 };
2061
2062 // NEON scalar instructions with indexed element operand.
2063 enum NEONScalarByIndexedElementOp {
2064 NEONScalarByIndexedElementFixed = 0x5F000000,
2065 NEONScalarByIndexedElementFMask = 0xDF000400,
2066 NEONScalarByIndexedElementMask = 0xFF00F400,
2067 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement,
2068 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement,
2069 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement,
2070 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement,
2071 NEON_SQRDMULH_byelement_scalar
2072 = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement,
2073
2074 // Floating point instructions.
2075 NEONScalarByIndexedElementFPFixed
2076 = NEONScalarByIndexedElementFixed | 0x00800000,
2077 NEONScalarByIndexedElementFPMask
2078 = NEONScalarByIndexedElementMask | 0x00800000,
2079 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement,
2080 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement,
2081 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement,
2082 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement
2083 };
2084
2085 // NEON scalar register copy.
2086 enum NEONScalarCopyOp {
2087 NEONScalarCopyFixed = 0x5E000400,
2088 NEONScalarCopyFMask = 0xDFE08400,
2089 NEONScalarCopyMask = 0xFFE0FC00,
2090 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT
2091 };
2092
2093 // NEON scalar pairwise instructions.
2094 enum NEONScalarPairwiseOp {
2095 NEONScalarPairwiseFixed = 0x5E300800,
2096 NEONScalarPairwiseFMask = 0xDF3E0C00,
2097 NEONScalarPairwiseMask = 0xFFB1F800,
2098 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000,
2099 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000,
2100 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000,
2101 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000,
2102 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000,
2103 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000
2104 };
2105
2106 // NEON scalar shift immediate.
2107 enum NEONScalarShiftImmediateOp {
2108 NEONScalarShiftImmediateFixed = 0x5F000400,
2109 NEONScalarShiftImmediateFMask = 0xDF800400,
2110 NEONScalarShiftImmediateMask = 0xFF80FC00,
2111 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL,
2112 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI,
2113 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI,
2114 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR,
2115 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR,
2116 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR,
2117 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR,
2118 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA,
2119 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA,
2120 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA,
2121 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA,
2122 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN,
2123 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN,
2124 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN,
2125 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN,
2126 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN,
2127 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN,
2128 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU,
2129 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm,
2130 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm,
2131 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm,
2132 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm,
2133 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
2134 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
2135 };
2136
2137 // Unimplemented and unallocated instructions. These are defined to make fixed
2138 // bit assertion easier.
2139 enum UnimplementedOp {
2140 UnimplementedFixed = 0x00000000,
2141 UnimplementedFMask = 0x00000000
2142 };
2143
2144 enum UnallocatedOp {
2145 UnallocatedFixed = 0x00000000,
2146 UnallocatedFMask = 0x00000000
2147 };
2148
2149 } // namespace vixl
2150
2151 #endif // VIXL_A64_CONSTANTS_A64_H_
2152