1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 2 // All Rights Reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are 6 // met: 7 // 8 // - Redistributions of source code must retain the above copyright notice, 9 // this list of conditions and the following disclaimer. 10 // 11 // - Redistribution in binary form must reproduce the above copyright 12 // notice, this list of conditions and the following disclaimer in the 13 // documentation and/or other materials provided with the distribution. 14 // 15 // - Neither the name of Sun Microsystems or the names of contributors may 16 // be used to endorse or promote products derived from this software without 17 // specific prior written permission. 18 // 19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31 // The original source code covered by the above license above has been 32 // modified significantly by Google Inc. 33 // Copyright 2012 the V8 project authors. All rights reserved. 34 35 #ifndef V8_CODEGEN_MIPS64_ASSEMBLER_MIPS64_H_ 36 #define V8_CODEGEN_MIPS64_ASSEMBLER_MIPS64_H_ 37 38 #include <stdio.h> 39 40 #include <memory> 41 #include <set> 42 43 #include "src/codegen/assembler.h" 44 #include "src/codegen/external-reference.h" 45 #include "src/codegen/label.h" 46 #include "src/codegen/machine-type.h" 47 #include "src/codegen/mips64/constants-mips64.h" 48 #include "src/codegen/mips64/register-mips64.h" 49 #include "src/objects/contexts.h" 50 #include "src/objects/smi.h" 51 52 namespace v8 { 53 namespace internal { 54 55 class SafepointTableBuilder; 56 57 // ----------------------------------------------------------------------------- 58 // Machine instruction Operands. 59 constexpr int kSmiShift = kSmiTagSize + kSmiShiftSize; 60 constexpr uint64_t kSmiShiftMask = (1UL << kSmiShift) - 1; 61 // Class Operand represents a shifter operand in data processing instructions. 62 class Operand { 63 public: 64 // Immediate. 65 V8_INLINE explicit Operand(int64_t immediate, 66 RelocInfo::Mode rmode = RelocInfo::NONE) rm_(no_reg)67 : rm_(no_reg), rmode_(rmode) { 68 value_.immediate = immediate; 69 } Operand(const ExternalReference & f)70 V8_INLINE explicit Operand(const ExternalReference& f) 71 : rm_(no_reg), rmode_(RelocInfo::EXTERNAL_REFERENCE) { 72 value_.immediate = static_cast<int64_t>(f.address()); 73 } 74 V8_INLINE explicit Operand(const char* s); 75 explicit Operand(Handle<HeapObject> handle); Operand(Smi value)76 V8_INLINE explicit Operand(Smi value) : rm_(no_reg), rmode_(RelocInfo::NONE) { 77 value_.immediate = static_cast<intptr_t>(value.ptr()); 78 } 79 80 static Operand EmbeddedNumber(double number); // Smi or HeapNumber. 81 static Operand EmbeddedStringConstant(const StringConstantBase* str); 82 83 // Register. Operand(Register rm)84 V8_INLINE explicit Operand(Register rm) : rm_(rm) {} 85 86 // Return true if this is a register operand. 87 V8_INLINE bool is_reg() const; 88 89 inline int64_t immediate() const; 90 IsImmediate()91 bool IsImmediate() const { return !rm_.is_valid(); } 92 heap_object_request()93 HeapObjectRequest heap_object_request() const { 94 DCHECK(IsHeapObjectRequest()); 95 return value_.heap_object_request; 96 } 97 IsHeapObjectRequest()98 bool IsHeapObjectRequest() const { 99 DCHECK_IMPLIES(is_heap_object_request_, IsImmediate()); 100 DCHECK_IMPLIES(is_heap_object_request_, 101 rmode_ == RelocInfo::FULL_EMBEDDED_OBJECT || 102 rmode_ == RelocInfo::CODE_TARGET); 103 return is_heap_object_request_; 104 } 105 rm()106 Register rm() const { return rm_; } 107 rmode()108 RelocInfo::Mode rmode() const { return rmode_; } 109 110 private: 111 Register rm_; 112 union Value { Value()113 Value() {} 114 HeapObjectRequest heap_object_request; // if is_heap_object_request_ 115 int64_t immediate; // otherwise 116 } value_; // valid if rm_ == no_reg 117 bool is_heap_object_request_ = false; 118 RelocInfo::Mode rmode_; 119 120 friend class Assembler; 121 friend class MacroAssembler; 122 }; 123 124 // On MIPS we have only one addressing mode with base_reg + offset. 125 // Class MemOperand represents a memory operand in load and store instructions. 126 class V8_EXPORT_PRIVATE MemOperand : public Operand { 127 public: 128 // Immediate value attached to offset. 129 enum OffsetAddend { offset_minus_one = -1, offset_zero = 0 }; 130 131 explicit MemOperand(Register rn, int32_t offset = 0); 132 explicit MemOperand(Register rn, int32_t unit, int32_t multiplier, 133 OffsetAddend offset_addend = offset_zero); offset()134 int32_t offset() const { return offset_; } 135 OffsetIsInt16Encodable()136 bool OffsetIsInt16Encodable() const { return is_int16(offset_); } 137 138 private: 139 int32_t offset_; 140 141 friend class Assembler; 142 }; 143 144 class V8_EXPORT_PRIVATE Assembler : public AssemblerBase { 145 public: 146 // Create an assembler. Instructions and relocation information are emitted 147 // into a buffer, with the instructions starting from the beginning and the 148 // relocation information starting from the end of the buffer. See CodeDesc 149 // for a detailed comment on the layout (globals.h). 150 // 151 // If the provided buffer is nullptr, the assembler allocates and grows its 152 // own buffer. Otherwise it takes ownership of the provided buffer. 153 explicit Assembler(const AssemblerOptions&, 154 std::unique_ptr<AssemblerBuffer> = {}); 155 ~Assembler()156 virtual ~Assembler() {} 157 158 // GetCode emits any pending (non-emitted) code and fills the descriptor desc. 159 static constexpr int kNoHandlerTable = 0; 160 static constexpr SafepointTableBuilder* kNoSafepointTable = nullptr; 161 void GetCode(Isolate* isolate, CodeDesc* desc, 162 SafepointTableBuilder* safepoint_table_builder, 163 int handler_table_offset); 164 165 // Convenience wrapper for code without safepoint or handler tables. GetCode(Isolate * isolate,CodeDesc * desc)166 void GetCode(Isolate* isolate, CodeDesc* desc) { 167 GetCode(isolate, desc, kNoSafepointTable, kNoHandlerTable); 168 } 169 170 // This function is called when on-heap-compilation invariants are 171 // invalidated. For instance, when the assembler buffer grows or a GC happens 172 // between Code object allocation and Code object finalization. 173 void FixOnHeapReferences(bool update_embedded_objects = true); 174 175 // This function is called when we fallback from on-heap to off-heap 176 // compilation and patch on-heap references to handles. 177 void FixOnHeapReferencesToHandles(); 178 179 // Unused on this architecture. MaybeEmitOutOfLineConstantPool()180 void MaybeEmitOutOfLineConstantPool() {} 181 182 // Mips uses BlockTrampolinePool to prevent generating trampoline inside a 183 // continuous instruction block. For Call instruction, it prevents generating 184 // trampoline between jalr and delay slot instruction. In the destructor of 185 // BlockTrampolinePool, it must check if it needs to generate trampoline 186 // immediately, if it does not do this, the branch range will go beyond the 187 // max branch offset, that means the pc_offset after call CheckTrampolinePool 188 // may be not the Call instruction's location. So we use last_call_pc here for 189 // safepoint record. pc_offset_for_safepoint()190 int pc_offset_for_safepoint() { 191 #ifdef DEBUG 192 Instr instr1 = 193 instr_at(static_cast<int>(last_call_pc_ - buffer_start_ - kInstrSize)); 194 Instr instr2 = instr_at( 195 static_cast<int>(last_call_pc_ - buffer_start_ - kInstrSize * 2)); 196 if (GetOpcodeField(instr1) != SPECIAL) { // instr1 == jialc. 197 DCHECK((kArchVariant == kMips64r6) && GetOpcodeField(instr1) == POP76 && 198 GetRs(instr1) == 0); 199 } else { 200 if (GetFunctionField(instr1) == SLL) { // instr1 == nop, instr2 == jalr. 201 DCHECK(GetOpcodeField(instr2) == SPECIAL && 202 GetFunctionField(instr2) == JALR); 203 } else { // instr1 == jalr. 204 DCHECK(GetFunctionField(instr1) == JALR); 205 } 206 } 207 #endif 208 return static_cast<int>(last_call_pc_ - buffer_start_); 209 } 210 211 // Label operations & relative jumps (PPUM Appendix D). 212 // 213 // Takes a branch opcode (cc) and a label (L) and generates 214 // either a backward branch or a forward branch and links it 215 // to the label fixup chain. Usage: 216 // 217 // Label L; // unbound label 218 // j(cc, &L); // forward branch to unbound label 219 // bind(&L); // bind label to the current pc 220 // j(cc, &L); // backward branch to bound label 221 // bind(&L); // illegal: a label may be bound only once 222 // 223 // Note: The same Label can be used for forward and backward branches 224 // but it may be bound only once. 225 void bind(Label* L); // Binds an unbound label L to current code position. 226 227 enum OffsetSize : int { kOffset26 = 26, kOffset21 = 21, kOffset16 = 16 }; 228 229 // Determines if Label is bound and near enough so that branch instruction 230 // can be used to reach it, instead of jump instruction. 231 bool is_near(Label* L); 232 bool is_near(Label* L, OffsetSize bits); 233 bool is_near_branch(Label* L); is_near_pre_r6(Label * L)234 inline bool is_near_pre_r6(Label* L) { 235 DCHECK(!(kArchVariant == kMips64r6)); 236 return pc_offset() - L->pos() < kMaxBranchOffset - 4 * kInstrSize; 237 } is_near_r6(Label * L)238 inline bool is_near_r6(Label* L) { 239 DCHECK_EQ(kArchVariant, kMips64r6); 240 return pc_offset() - L->pos() < kMaxCompactBranchOffset - 4 * kInstrSize; 241 } 242 243 int BranchOffset(Instr instr); 244 245 // Returns the branch offset to the given label from the current code 246 // position. Links the label to the current position if it is still unbound. 247 // Manages the jump elimination optimization if the second parameter is true. 248 int32_t branch_offset_helper(Label* L, OffsetSize bits); branch_offset(Label * L)249 inline int32_t branch_offset(Label* L) { 250 return branch_offset_helper(L, OffsetSize::kOffset16); 251 } branch_offset21(Label * L)252 inline int32_t branch_offset21(Label* L) { 253 return branch_offset_helper(L, OffsetSize::kOffset21); 254 } branch_offset26(Label * L)255 inline int32_t branch_offset26(Label* L) { 256 return branch_offset_helper(L, OffsetSize::kOffset26); 257 } shifted_branch_offset(Label * L)258 inline int32_t shifted_branch_offset(Label* L) { 259 return branch_offset(L) >> 2; 260 } shifted_branch_offset21(Label * L)261 inline int32_t shifted_branch_offset21(Label* L) { 262 return branch_offset21(L) >> 2; 263 } shifted_branch_offset26(Label * L)264 inline int32_t shifted_branch_offset26(Label* L) { 265 return branch_offset26(L) >> 2; 266 } 267 uint64_t jump_address(Label* L); 268 uint64_t jump_offset(Label* L); 269 uint64_t branch_long_offset(Label* L); 270 271 // Puts a labels target address at the given position. 272 // The high 8 bits are set to zero. 273 void label_at_put(Label* L, int at_offset); 274 275 // Read/Modify the code target address in the branch/call instruction at pc. 276 // The isolate argument is unused (and may be nullptr) when skipping flushing. 277 static Address target_address_at(Address pc); 278 V8_INLINE static void set_target_address_at( 279 Address pc, Address target, 280 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { 281 set_target_value_at(pc, target, icache_flush_mode); 282 } 283 // On MIPS there is no Constant Pool so we skip that parameter. target_address_at(Address pc,Address constant_pool)284 V8_INLINE static Address target_address_at(Address pc, 285 Address constant_pool) { 286 return target_address_at(pc); 287 } 288 V8_INLINE static void set_target_address_at( 289 Address pc, Address constant_pool, Address target, 290 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { 291 set_target_address_at(pc, target, icache_flush_mode); 292 } 293 294 static void set_target_value_at( 295 Address pc, uint64_t target, 296 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); 297 298 static void JumpLabelToJumpRegister(Address pc); 299 300 // This sets the branch destination (which gets loaded at the call address). 301 // This is for calls and branches within generated code. The serializer 302 // has already deserialized the lui/ori instructions etc. 303 inline static void deserialization_set_special_target_at( 304 Address instruction_payload, Code code, Address target); 305 306 // Get the size of the special target encoded at 'instruction_payload'. 307 inline static int deserialization_special_target_size( 308 Address instruction_payload); 309 310 // This sets the internal reference at the pc. 311 inline static void deserialization_set_target_internal_reference_at( 312 Address pc, Address target, 313 RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE); 314 315 // Difference between address of current opcode and target address offset. 316 static constexpr int kBranchPCOffset = kInstrSize; 317 318 // Difference between address of current opcode and target address offset, 319 // when we are generatinga sequence of instructions for long relative PC 320 // branches 321 static constexpr int kLongBranchPCOffset = 3 * kInstrSize; 322 323 // Adjust ra register in branch delay slot of bal instruction so to skip 324 // instructions not needed after optimization of PIC in 325 // TurboAssembler::BranchAndLink method. 326 327 static constexpr int kOptimizedBranchAndLinkLongReturnOffset = 4 * kInstrSize; 328 329 // Here we are patching the address in the LUI/ORI instruction pair. 330 // These values are used in the serialization process and must be zero for 331 // MIPS platform, as Code, Embedded Object or External-reference pointers 332 // are split across two consecutive instructions and don't exist separately 333 // in the code, so the serializer should not step forwards in memory after 334 // a target is resolved and written. 335 static constexpr int kSpecialTargetSize = 0; 336 337 // Number of consecutive instructions used to store 32bit/64bit constant. 338 // This constant was used in RelocInfo::target_address_address() function 339 // to tell serializer address of the instruction that follows 340 // LUI/ORI instruction pair. 341 static constexpr int kInstructionsFor32BitConstant = 2; 342 static constexpr int kInstructionsFor64BitConstant = 4; 343 344 // Difference between address of current opcode and value read from pc 345 // register. 346 static constexpr int kPcLoadDelta = 4; 347 348 // Max offset for instructions with 16-bit offset field 349 static constexpr int kMaxBranchOffset = (1 << (18 - 1)) - 1; 350 351 // Max offset for compact branch instructions with 26-bit offset field 352 static constexpr int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1; 353 354 static constexpr int kTrampolineSlotsSize = 355 kArchVariant == kMips64r6 ? 2 * kInstrSize : 7 * kInstrSize; 356 GetScratchRegisterList()357 RegList* GetScratchRegisterList() { return &scratch_register_list_; } 358 359 // --------------------------------------------------------------------------- 360 // Code generation. 361 362 // Insert the smallest number of nop instructions 363 // possible to align the pc offset to a multiple 364 // of m. m must be a power of 2 (>= 4). 365 void Align(int m); 366 // Insert the smallest number of zero bytes possible to align the pc offset 367 // to a mulitple of m. m must be a power of 2 (>= 2). 368 void DataAlign(int m); 369 // Aligns code to something that's optimal for a jump target for the platform. 370 void CodeTargetAlign(); LoopHeaderAlign()371 void LoopHeaderAlign() { CodeTargetAlign(); } 372 373 // Different nop operations are used by the code generator to detect certain 374 // states of the generated code. 375 enum NopMarkerTypes { 376 NON_MARKING_NOP = 0, 377 DEBUG_BREAK_NOP, 378 // IC markers. 379 PROPERTY_ACCESS_INLINED, 380 PROPERTY_ACCESS_INLINED_CONTEXT, 381 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE, 382 // Helper values. 383 LAST_CODE_MARKER, 384 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED, 385 }; 386 387 // Type == 0 is the default non-marking nop. For mips this is a 388 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero 389 // marking, to avoid conflict with ssnop and ehb instructions. 390 void nop(unsigned int type = 0) { 391 DCHECK_LT(type, 32); 392 Register nop_rt_reg = (type == 0) ? zero_reg : at; 393 sll(zero_reg, nop_rt_reg, type, true); 394 } 395 396 // --------Branch-and-jump-instructions---------- 397 // We don't use likely variant of instructions. 398 void b(int16_t offset); b(Label * L)399 inline void b(Label* L) { b(shifted_branch_offset(L)); } 400 void bal(int16_t offset); bal(Label * L)401 inline void bal(Label* L) { bal(shifted_branch_offset(L)); } 402 void bc(int32_t offset); bc(Label * L)403 inline void bc(Label* L) { bc(shifted_branch_offset26(L)); } 404 void balc(int32_t offset); balc(Label * L)405 inline void balc(Label* L) { balc(shifted_branch_offset26(L)); } 406 407 void beq(Register rs, Register rt, int16_t offset); beq(Register rs,Register rt,Label * L)408 inline void beq(Register rs, Register rt, Label* L) { 409 beq(rs, rt, shifted_branch_offset(L)); 410 } 411 void bgez(Register rs, int16_t offset); 412 void bgezc(Register rt, int16_t offset); bgezc(Register rt,Label * L)413 inline void bgezc(Register rt, Label* L) { 414 bgezc(rt, shifted_branch_offset(L)); 415 } 416 void bgeuc(Register rs, Register rt, int16_t offset); bgeuc(Register rs,Register rt,Label * L)417 inline void bgeuc(Register rs, Register rt, Label* L) { 418 bgeuc(rs, rt, shifted_branch_offset(L)); 419 } 420 void bgec(Register rs, Register rt, int16_t offset); bgec(Register rs,Register rt,Label * L)421 inline void bgec(Register rs, Register rt, Label* L) { 422 bgec(rs, rt, shifted_branch_offset(L)); 423 } 424 void bgezal(Register rs, int16_t offset); 425 void bgezalc(Register rt, int16_t offset); bgezalc(Register rt,Label * L)426 inline void bgezalc(Register rt, Label* L) { 427 bgezalc(rt, shifted_branch_offset(L)); 428 } 429 void bgezall(Register rs, int16_t offset); bgezall(Register rs,Label * L)430 inline void bgezall(Register rs, Label* L) { 431 bgezall(rs, branch_offset(L) >> 2); 432 } 433 void bgtz(Register rs, int16_t offset); 434 void bgtzc(Register rt, int16_t offset); bgtzc(Register rt,Label * L)435 inline void bgtzc(Register rt, Label* L) { 436 bgtzc(rt, shifted_branch_offset(L)); 437 } 438 void blez(Register rs, int16_t offset); 439 void blezc(Register rt, int16_t offset); blezc(Register rt,Label * L)440 inline void blezc(Register rt, Label* L) { 441 blezc(rt, shifted_branch_offset(L)); 442 } 443 void bltz(Register rs, int16_t offset); 444 void bltzc(Register rt, int16_t offset); bltzc(Register rt,Label * L)445 inline void bltzc(Register rt, Label* L) { 446 bltzc(rt, shifted_branch_offset(L)); 447 } 448 void bltuc(Register rs, Register rt, int16_t offset); bltuc(Register rs,Register rt,Label * L)449 inline void bltuc(Register rs, Register rt, Label* L) { 450 bltuc(rs, rt, shifted_branch_offset(L)); 451 } 452 void bltc(Register rs, Register rt, int16_t offset); bltc(Register rs,Register rt,Label * L)453 inline void bltc(Register rs, Register rt, Label* L) { 454 bltc(rs, rt, shifted_branch_offset(L)); 455 } 456 void bltzal(Register rs, int16_t offset); nal()457 void nal() { bltzal(zero_reg, 0); } 458 void blezalc(Register rt, int16_t offset); blezalc(Register rt,Label * L)459 inline void blezalc(Register rt, Label* L) { 460 blezalc(rt, shifted_branch_offset(L)); 461 } 462 void bltzalc(Register rt, int16_t offset); bltzalc(Register rt,Label * L)463 inline void bltzalc(Register rt, Label* L) { 464 bltzalc(rt, shifted_branch_offset(L)); 465 } 466 void bgtzalc(Register rt, int16_t offset); bgtzalc(Register rt,Label * L)467 inline void bgtzalc(Register rt, Label* L) { 468 bgtzalc(rt, shifted_branch_offset(L)); 469 } 470 void beqzalc(Register rt, int16_t offset); beqzalc(Register rt,Label * L)471 inline void beqzalc(Register rt, Label* L) { 472 beqzalc(rt, shifted_branch_offset(L)); 473 } 474 void beqc(Register rs, Register rt, int16_t offset); beqc(Register rs,Register rt,Label * L)475 inline void beqc(Register rs, Register rt, Label* L) { 476 beqc(rs, rt, shifted_branch_offset(L)); 477 } 478 void beqzc(Register rs, int32_t offset); beqzc(Register rs,Label * L)479 inline void beqzc(Register rs, Label* L) { 480 beqzc(rs, shifted_branch_offset21(L)); 481 } 482 void bnezalc(Register rt, int16_t offset); bnezalc(Register rt,Label * L)483 inline void bnezalc(Register rt, Label* L) { 484 bnezalc(rt, shifted_branch_offset(L)); 485 } 486 void bnec(Register rs, Register rt, int16_t offset); bnec(Register rs,Register rt,Label * L)487 inline void bnec(Register rs, Register rt, Label* L) { 488 bnec(rs, rt, shifted_branch_offset(L)); 489 } 490 void bnezc(Register rt, int32_t offset); bnezc(Register rt,Label * L)491 inline void bnezc(Register rt, Label* L) { 492 bnezc(rt, shifted_branch_offset21(L)); 493 } 494 void bne(Register rs, Register rt, int16_t offset); bne(Register rs,Register rt,Label * L)495 inline void bne(Register rs, Register rt, Label* L) { 496 bne(rs, rt, shifted_branch_offset(L)); 497 } 498 void bovc(Register rs, Register rt, int16_t offset); bovc(Register rs,Register rt,Label * L)499 inline void bovc(Register rs, Register rt, Label* L) { 500 bovc(rs, rt, shifted_branch_offset(L)); 501 } 502 void bnvc(Register rs, Register rt, int16_t offset); bnvc(Register rs,Register rt,Label * L)503 inline void bnvc(Register rs, Register rt, Label* L) { 504 bnvc(rs, rt, shifted_branch_offset(L)); 505 } 506 507 // Never use the int16_t b(l)cond version with a branch offset 508 // instead of using the Label* version. 509 510 void jalr(Register rs, Register rd = ra); 511 void jr(Register target); 512 void jic(Register rt, int16_t offset); 513 void jialc(Register rt, int16_t offset); 514 515 // Following instructions are deprecated and require 256 MB 516 // code alignment. Use PC-relative instructions instead. 517 void j(int64_t target); 518 void jal(int64_t target); 519 void j(Label* target); 520 void jal(Label* target); 521 522 // -------Data-processing-instructions--------- 523 524 // Arithmetic. 525 void addu(Register rd, Register rs, Register rt); 526 void subu(Register rd, Register rs, Register rt); 527 528 void div(Register rs, Register rt); 529 void divu(Register rs, Register rt); 530 void ddiv(Register rs, Register rt); 531 void ddivu(Register rs, Register rt); 532 void div(Register rd, Register rs, Register rt); 533 void divu(Register rd, Register rs, Register rt); 534 void ddiv(Register rd, Register rs, Register rt); 535 void ddivu(Register rd, Register rs, Register rt); 536 void mod(Register rd, Register rs, Register rt); 537 void modu(Register rd, Register rs, Register rt); 538 void dmod(Register rd, Register rs, Register rt); 539 void dmodu(Register rd, Register rs, Register rt); 540 541 void mul(Register rd, Register rs, Register rt); 542 void muh(Register rd, Register rs, Register rt); 543 void mulu(Register rd, Register rs, Register rt); 544 void muhu(Register rd, Register rs, Register rt); 545 void mult(Register rs, Register rt); 546 void multu(Register rs, Register rt); 547 void dmul(Register rd, Register rs, Register rt); 548 void dmuh(Register rd, Register rs, Register rt); 549 void dmulu(Register rd, Register rs, Register rt); 550 void dmuhu(Register rd, Register rs, Register rt); 551 void daddu(Register rd, Register rs, Register rt); 552 void dsubu(Register rd, Register rs, Register rt); 553 void dmult(Register rs, Register rt); 554 void dmultu(Register rs, Register rt); 555 556 void addiu(Register rd, Register rs, int32_t j); 557 void daddiu(Register rd, Register rs, int32_t j); 558 559 // Logical. 560 void and_(Register rd, Register rs, Register rt); 561 void or_(Register rd, Register rs, Register rt); 562 void xor_(Register rd, Register rs, Register rt); 563 void nor(Register rd, Register rs, Register rt); 564 565 void andi(Register rd, Register rs, int32_t j); 566 void ori(Register rd, Register rs, int32_t j); 567 void xori(Register rd, Register rs, int32_t j); 568 void lui(Register rd, int32_t j); 569 void aui(Register rt, Register rs, int32_t j); 570 void daui(Register rt, Register rs, int32_t j); 571 void dahi(Register rs, int32_t j); 572 void dati(Register rs, int32_t j); 573 574 // Shifts. 575 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop 576 // and may cause problems in normal code. coming_from_nop makes sure this 577 // doesn't happen. 578 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false); 579 void sllv(Register rd, Register rt, Register rs); 580 void srl(Register rd, Register rt, uint16_t sa); 581 void srlv(Register rd, Register rt, Register rs); 582 void sra(Register rt, Register rd, uint16_t sa); 583 void srav(Register rt, Register rd, Register rs); 584 void rotr(Register rd, Register rt, uint16_t sa); 585 void rotrv(Register rd, Register rt, Register rs); 586 void dsll(Register rd, Register rt, uint16_t sa); 587 void dsllv(Register rd, Register rt, Register rs); 588 void dsrl(Register rd, Register rt, uint16_t sa); 589 void dsrlv(Register rd, Register rt, Register rs); 590 void drotr(Register rd, Register rt, uint16_t sa); 591 void drotr32(Register rd, Register rt, uint16_t sa); 592 void drotrv(Register rd, Register rt, Register rs); 593 void dsra(Register rt, Register rd, uint16_t sa); 594 void dsrav(Register rd, Register rt, Register rs); 595 void dsll32(Register rt, Register rd, uint16_t sa); 596 void dsrl32(Register rt, Register rd, uint16_t sa); 597 void dsra32(Register rt, Register rd, uint16_t sa); 598 599 // ------------Memory-instructions------------- 600 601 void lb(Register rd, const MemOperand& rs); 602 void lbu(Register rd, const MemOperand& rs); 603 void lh(Register rd, const MemOperand& rs); 604 void lhu(Register rd, const MemOperand& rs); 605 void lw(Register rd, const MemOperand& rs); 606 void lwu(Register rd, const MemOperand& rs); 607 void lwl(Register rd, const MemOperand& rs); 608 void lwr(Register rd, const MemOperand& rs); 609 void sb(Register rd, const MemOperand& rs); 610 void sh(Register rd, const MemOperand& rs); 611 void sw(Register rd, const MemOperand& rs); 612 void swl(Register rd, const MemOperand& rs); 613 void swr(Register rd, const MemOperand& rs); 614 void ldl(Register rd, const MemOperand& rs); 615 void ldr(Register rd, const MemOperand& rs); 616 void sdl(Register rd, const MemOperand& rs); 617 void sdr(Register rd, const MemOperand& rs); 618 void ld(Register rd, const MemOperand& rs); 619 void sd(Register rd, const MemOperand& rs); 620 621 // ----------Atomic instructions-------------- 622 623 void ll(Register rd, const MemOperand& rs); 624 void sc(Register rd, const MemOperand& rs); 625 void lld(Register rd, const MemOperand& rs); 626 void scd(Register rd, const MemOperand& rs); 627 628 // ---------PC-Relative-instructions----------- 629 630 void addiupc(Register rs, int32_t imm19); 631 void lwpc(Register rs, int32_t offset19); 632 void lwupc(Register rs, int32_t offset19); 633 void ldpc(Register rs, int32_t offset18); 634 void auipc(Register rs, int16_t imm16); 635 void aluipc(Register rs, int16_t imm16); 636 637 // ----------------Prefetch-------------------- 638 639 void pref(int32_t hint, const MemOperand& rs); 640 641 // -------------Misc-instructions-------------- 642 643 // Break / Trap instructions. 644 void break_(uint32_t code, bool break_as_stop = false); 645 void stop(uint32_t code = kMaxStopCode); 646 void tge(Register rs, Register rt, uint16_t code); 647 void tgeu(Register rs, Register rt, uint16_t code); 648 void tlt(Register rs, Register rt, uint16_t code); 649 void tltu(Register rs, Register rt, uint16_t code); 650 void teq(Register rs, Register rt, uint16_t code); 651 void tne(Register rs, Register rt, uint16_t code); 652 653 // Memory barrier instruction. 654 void sync(); 655 656 // Move from HI/LO register. 657 void mfhi(Register rd); 658 void mflo(Register rd); 659 660 // Set on less than. 661 void slt(Register rd, Register rs, Register rt); 662 void sltu(Register rd, Register rs, Register rt); 663 void slti(Register rd, Register rs, int32_t j); 664 void sltiu(Register rd, Register rs, int32_t j); 665 666 // Conditional move. 667 void movz(Register rd, Register rs, Register rt); 668 void movn(Register rd, Register rs, Register rt); 669 void movt(Register rd, Register rs, uint16_t cc = 0); 670 void movf(Register rd, Register rs, uint16_t cc = 0); 671 672 void sel(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 673 void sel_s(FPURegister fd, FPURegister fs, FPURegister ft); 674 void sel_d(FPURegister fd, FPURegister fs, FPURegister ft); 675 void seleqz(Register rd, Register rs, Register rt); 676 void seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs, 677 FPURegister ft); 678 void selnez(Register rs, Register rt, Register rd); 679 void selnez(SecondaryField fmt, FPURegister fd, FPURegister fs, 680 FPURegister ft); 681 void seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft); 682 void seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft); 683 void selnez_d(FPURegister fd, FPURegister fs, FPURegister ft); 684 void selnez_s(FPURegister fd, FPURegister fs, FPURegister ft); 685 686 void movz_s(FPURegister fd, FPURegister fs, Register rt); 687 void movz_d(FPURegister fd, FPURegister fs, Register rt); 688 void movt_s(FPURegister fd, FPURegister fs, uint16_t cc = 0); 689 void movt_d(FPURegister fd, FPURegister fs, uint16_t cc = 0); 690 void movf_s(FPURegister fd, FPURegister fs, uint16_t cc = 0); 691 void movf_d(FPURegister fd, FPURegister fs, uint16_t cc = 0); 692 void movn_s(FPURegister fd, FPURegister fs, Register rt); 693 void movn_d(FPURegister fd, FPURegister fs, Register rt); 694 // Bit twiddling. 695 void clz(Register rd, Register rs); 696 void dclz(Register rd, Register rs); 697 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); 698 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); 699 void dext_(Register rt, Register rs, uint16_t pos, uint16_t size); 700 void dextm_(Register rt, Register rs, uint16_t pos, uint16_t size); 701 void dextu_(Register rt, Register rs, uint16_t pos, uint16_t size); 702 void dins_(Register rt, Register rs, uint16_t pos, uint16_t size); 703 void dinsm_(Register rt, Register rs, uint16_t pos, uint16_t size); 704 void dinsu_(Register rt, Register rs, uint16_t pos, uint16_t size); 705 void bitswap(Register rd, Register rt); 706 void dbitswap(Register rd, Register rt); 707 void align(Register rd, Register rs, Register rt, uint8_t bp); 708 void dalign(Register rd, Register rs, Register rt, uint8_t bp); 709 710 void wsbh(Register rd, Register rt); 711 void dsbh(Register rd, Register rt); 712 void dshd(Register rd, Register rt); 713 void seh(Register rd, Register rt); 714 void seb(Register rd, Register rt); 715 716 // --------Coprocessor-instructions---------------- 717 718 // Load, store, and move. 719 void lwc1(FPURegister fd, const MemOperand& src); 720 void ldc1(FPURegister fd, const MemOperand& src); 721 722 void swc1(FPURegister fs, const MemOperand& dst); 723 void sdc1(FPURegister fs, const MemOperand& dst); 724 725 void mtc1(Register rt, FPURegister fs); 726 void mthc1(Register rt, FPURegister fs); 727 void dmtc1(Register rt, FPURegister fs); 728 729 void mfc1(Register rt, FPURegister fs); 730 void mfhc1(Register rt, FPURegister fs); 731 void dmfc1(Register rt, FPURegister fs); 732 733 void ctc1(Register rt, FPUControlRegister fs); 734 void cfc1(Register rt, FPUControlRegister fs); 735 736 // Arithmetic. 737 void add_s(FPURegister fd, FPURegister fs, FPURegister ft); 738 void add_d(FPURegister fd, FPURegister fs, FPURegister ft); 739 void sub_s(FPURegister fd, FPURegister fs, FPURegister ft); 740 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft); 741 void mul_s(FPURegister fd, FPURegister fs, FPURegister ft); 742 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft); 743 void madd_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 744 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 745 void msub_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 746 void msub_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 747 void maddf_s(FPURegister fd, FPURegister fs, FPURegister ft); 748 void maddf_d(FPURegister fd, FPURegister fs, FPURegister ft); 749 void msubf_s(FPURegister fd, FPURegister fs, FPURegister ft); 750 void msubf_d(FPURegister fd, FPURegister fs, FPURegister ft); 751 void div_s(FPURegister fd, FPURegister fs, FPURegister ft); 752 void div_d(FPURegister fd, FPURegister fs, FPURegister ft); 753 void abs_s(FPURegister fd, FPURegister fs); 754 void abs_d(FPURegister fd, FPURegister fs); 755 void mov_d(FPURegister fd, FPURegister fs); 756 void mov_s(FPURegister fd, FPURegister fs); 757 void neg_s(FPURegister fd, FPURegister fs); 758 void neg_d(FPURegister fd, FPURegister fs); 759 void sqrt_s(FPURegister fd, FPURegister fs); 760 void sqrt_d(FPURegister fd, FPURegister fs); 761 void rsqrt_s(FPURegister fd, FPURegister fs); 762 void rsqrt_d(FPURegister fd, FPURegister fs); 763 void recip_d(FPURegister fd, FPURegister fs); 764 void recip_s(FPURegister fd, FPURegister fs); 765 766 // Conversion. 767 void cvt_w_s(FPURegister fd, FPURegister fs); 768 void cvt_w_d(FPURegister fd, FPURegister fs); 769 void trunc_w_s(FPURegister fd, FPURegister fs); 770 void trunc_w_d(FPURegister fd, FPURegister fs); 771 void round_w_s(FPURegister fd, FPURegister fs); 772 void round_w_d(FPURegister fd, FPURegister fs); 773 void floor_w_s(FPURegister fd, FPURegister fs); 774 void floor_w_d(FPURegister fd, FPURegister fs); 775 void ceil_w_s(FPURegister fd, FPURegister fs); 776 void ceil_w_d(FPURegister fd, FPURegister fs); 777 void rint_s(FPURegister fd, FPURegister fs); 778 void rint_d(FPURegister fd, FPURegister fs); 779 void rint(SecondaryField fmt, FPURegister fd, FPURegister fs); 780 781 void cvt_l_s(FPURegister fd, FPURegister fs); 782 void cvt_l_d(FPURegister fd, FPURegister fs); 783 void trunc_l_s(FPURegister fd, FPURegister fs); 784 void trunc_l_d(FPURegister fd, FPURegister fs); 785 void round_l_s(FPURegister fd, FPURegister fs); 786 void round_l_d(FPURegister fd, FPURegister fs); 787 void floor_l_s(FPURegister fd, FPURegister fs); 788 void floor_l_d(FPURegister fd, FPURegister fs); 789 void ceil_l_s(FPURegister fd, FPURegister fs); 790 void ceil_l_d(FPURegister fd, FPURegister fs); 791 792 void class_s(FPURegister fd, FPURegister fs); 793 void class_d(FPURegister fd, FPURegister fs); 794 795 void min(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 796 void mina(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 797 void max(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 798 void maxa(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 799 void min_s(FPURegister fd, FPURegister fs, FPURegister ft); 800 void min_d(FPURegister fd, FPURegister fs, FPURegister ft); 801 void max_s(FPURegister fd, FPURegister fs, FPURegister ft); 802 void max_d(FPURegister fd, FPURegister fs, FPURegister ft); 803 void mina_s(FPURegister fd, FPURegister fs, FPURegister ft); 804 void mina_d(FPURegister fd, FPURegister fs, FPURegister ft); 805 void maxa_s(FPURegister fd, FPURegister fs, FPURegister ft); 806 void maxa_d(FPURegister fd, FPURegister fs, FPURegister ft); 807 808 void cvt_s_w(FPURegister fd, FPURegister fs); 809 void cvt_s_l(FPURegister fd, FPURegister fs); 810 void cvt_s_d(FPURegister fd, FPURegister fs); 811 812 void cvt_d_w(FPURegister fd, FPURegister fs); 813 void cvt_d_l(FPURegister fd, FPURegister fs); 814 void cvt_d_s(FPURegister fd, FPURegister fs); 815 816 // Conditions and branches for MIPSr6. 817 void cmp(FPUCondition cond, SecondaryField fmt, FPURegister fd, 818 FPURegister ft, FPURegister fs); 819 void cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); 820 void cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); 821 822 void bc1eqz(int16_t offset, FPURegister ft); bc1eqz(Label * L,FPURegister ft)823 inline void bc1eqz(Label* L, FPURegister ft) { 824 bc1eqz(shifted_branch_offset(L), ft); 825 } 826 void bc1nez(int16_t offset, FPURegister ft); bc1nez(Label * L,FPURegister ft)827 inline void bc1nez(Label* L, FPURegister ft) { 828 bc1nez(shifted_branch_offset(L), ft); 829 } 830 831 // Conditions and branches for non MIPSr6. 832 void c(FPUCondition cond, SecondaryField fmt, FPURegister ft, FPURegister fs, 833 uint16_t cc = 0); 834 void c_s(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); 835 void c_d(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); 836 837 void bc1f(int16_t offset, uint16_t cc = 0); 838 inline void bc1f(Label* L, uint16_t cc = 0) { 839 bc1f(shifted_branch_offset(L), cc); 840 } 841 void bc1t(int16_t offset, uint16_t cc = 0); 842 inline void bc1t(Label* L, uint16_t cc = 0) { 843 bc1t(shifted_branch_offset(L), cc); 844 } 845 void fcmp(FPURegister src1, const double src2, FPUCondition cond); 846 847 // MSA instructions 848 void bz_v(MSARegister wt, int16_t offset); bz_v(MSARegister wt,Label * L)849 inline void bz_v(MSARegister wt, Label* L) { 850 bz_v(wt, shifted_branch_offset(L)); 851 } 852 void bz_b(MSARegister wt, int16_t offset); bz_b(MSARegister wt,Label * L)853 inline void bz_b(MSARegister wt, Label* L) { 854 bz_b(wt, shifted_branch_offset(L)); 855 } 856 void bz_h(MSARegister wt, int16_t offset); bz_h(MSARegister wt,Label * L)857 inline void bz_h(MSARegister wt, Label* L) { 858 bz_h(wt, shifted_branch_offset(L)); 859 } 860 void bz_w(MSARegister wt, int16_t offset); bz_w(MSARegister wt,Label * L)861 inline void bz_w(MSARegister wt, Label* L) { 862 bz_w(wt, shifted_branch_offset(L)); 863 } 864 void bz_d(MSARegister wt, int16_t offset); bz_d(MSARegister wt,Label * L)865 inline void bz_d(MSARegister wt, Label* L) { 866 bz_d(wt, shifted_branch_offset(L)); 867 } 868 void bnz_v(MSARegister wt, int16_t offset); bnz_v(MSARegister wt,Label * L)869 inline void bnz_v(MSARegister wt, Label* L) { 870 bnz_v(wt, shifted_branch_offset(L)); 871 } 872 void bnz_b(MSARegister wt, int16_t offset); bnz_b(MSARegister wt,Label * L)873 inline void bnz_b(MSARegister wt, Label* L) { 874 bnz_b(wt, shifted_branch_offset(L)); 875 } 876 void bnz_h(MSARegister wt, int16_t offset); bnz_h(MSARegister wt,Label * L)877 inline void bnz_h(MSARegister wt, Label* L) { 878 bnz_h(wt, shifted_branch_offset(L)); 879 } 880 void bnz_w(MSARegister wt, int16_t offset); bnz_w(MSARegister wt,Label * L)881 inline void bnz_w(MSARegister wt, Label* L) { 882 bnz_w(wt, shifted_branch_offset(L)); 883 } 884 void bnz_d(MSARegister wt, int16_t offset); bnz_d(MSARegister wt,Label * L)885 inline void bnz_d(MSARegister wt, Label* L) { 886 bnz_d(wt, shifted_branch_offset(L)); 887 } 888 889 void ld_b(MSARegister wd, const MemOperand& rs); 890 void ld_h(MSARegister wd, const MemOperand& rs); 891 void ld_w(MSARegister wd, const MemOperand& rs); 892 void ld_d(MSARegister wd, const MemOperand& rs); 893 void st_b(MSARegister wd, const MemOperand& rs); 894 void st_h(MSARegister wd, const MemOperand& rs); 895 void st_w(MSARegister wd, const MemOperand& rs); 896 void st_d(MSARegister wd, const MemOperand& rs); 897 898 void ldi_b(MSARegister wd, int32_t imm10); 899 void ldi_h(MSARegister wd, int32_t imm10); 900 void ldi_w(MSARegister wd, int32_t imm10); 901 void ldi_d(MSARegister wd, int32_t imm10); 902 903 void addvi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 904 void addvi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 905 void addvi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 906 void addvi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 907 void subvi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 908 void subvi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 909 void subvi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 910 void subvi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 911 void maxi_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 912 void maxi_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 913 void maxi_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 914 void maxi_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 915 void maxi_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 916 void maxi_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 917 void maxi_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 918 void maxi_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 919 void mini_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 920 void mini_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 921 void mini_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 922 void mini_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 923 void mini_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 924 void mini_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 925 void mini_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 926 void mini_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 927 void ceqi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 928 void ceqi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 929 void ceqi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 930 void ceqi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 931 void clti_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 932 void clti_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 933 void clti_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 934 void clti_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 935 void clti_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 936 void clti_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 937 void clti_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 938 void clti_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 939 void clei_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 940 void clei_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 941 void clei_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 942 void clei_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 943 void clei_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 944 void clei_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 945 void clei_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 946 void clei_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 947 948 void andi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 949 void ori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 950 void nori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 951 void xori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 952 void bmnzi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 953 void bmzi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 954 void bseli_b(MSARegister wd, MSARegister ws, uint32_t imm8); 955 void shf_b(MSARegister wd, MSARegister ws, uint32_t imm8); 956 void shf_h(MSARegister wd, MSARegister ws, uint32_t imm8); 957 void shf_w(MSARegister wd, MSARegister ws, uint32_t imm8); 958 959 void and_v(MSARegister wd, MSARegister ws, MSARegister wt); 960 void or_v(MSARegister wd, MSARegister ws, MSARegister wt); 961 void nor_v(MSARegister wd, MSARegister ws, MSARegister wt); 962 void xor_v(MSARegister wd, MSARegister ws, MSARegister wt); 963 void bmnz_v(MSARegister wd, MSARegister ws, MSARegister wt); 964 void bmz_v(MSARegister wd, MSARegister ws, MSARegister wt); 965 void bsel_v(MSARegister wd, MSARegister ws, MSARegister wt); 966 967 void fill_b(MSARegister wd, Register rs); 968 void fill_h(MSARegister wd, Register rs); 969 void fill_w(MSARegister wd, Register rs); 970 void fill_d(MSARegister wd, Register rs); 971 void pcnt_b(MSARegister wd, MSARegister ws); 972 void pcnt_h(MSARegister wd, MSARegister ws); 973 void pcnt_w(MSARegister wd, MSARegister ws); 974 void pcnt_d(MSARegister wd, MSARegister ws); 975 void nloc_b(MSARegister wd, MSARegister ws); 976 void nloc_h(MSARegister wd, MSARegister ws); 977 void nloc_w(MSARegister wd, MSARegister ws); 978 void nloc_d(MSARegister wd, MSARegister ws); 979 void nlzc_b(MSARegister wd, MSARegister ws); 980 void nlzc_h(MSARegister wd, MSARegister ws); 981 void nlzc_w(MSARegister wd, MSARegister ws); 982 void nlzc_d(MSARegister wd, MSARegister ws); 983 984 void fclass_w(MSARegister wd, MSARegister ws); 985 void fclass_d(MSARegister wd, MSARegister ws); 986 void ftrunc_s_w(MSARegister wd, MSARegister ws); 987 void ftrunc_s_d(MSARegister wd, MSARegister ws); 988 void ftrunc_u_w(MSARegister wd, MSARegister ws); 989 void ftrunc_u_d(MSARegister wd, MSARegister ws); 990 void fsqrt_w(MSARegister wd, MSARegister ws); 991 void fsqrt_d(MSARegister wd, MSARegister ws); 992 void frsqrt_w(MSARegister wd, MSARegister ws); 993 void frsqrt_d(MSARegister wd, MSARegister ws); 994 void frcp_w(MSARegister wd, MSARegister ws); 995 void frcp_d(MSARegister wd, MSARegister ws); 996 void frint_w(MSARegister wd, MSARegister ws); 997 void frint_d(MSARegister wd, MSARegister ws); 998 void flog2_w(MSARegister wd, MSARegister ws); 999 void flog2_d(MSARegister wd, MSARegister ws); 1000 void fexupl_w(MSARegister wd, MSARegister ws); 1001 void fexupl_d(MSARegister wd, MSARegister ws); 1002 void fexupr_w(MSARegister wd, MSARegister ws); 1003 void fexupr_d(MSARegister wd, MSARegister ws); 1004 void ffql_w(MSARegister wd, MSARegister ws); 1005 void ffql_d(MSARegister wd, MSARegister ws); 1006 void ffqr_w(MSARegister wd, MSARegister ws); 1007 void ffqr_d(MSARegister wd, MSARegister ws); 1008 void ftint_s_w(MSARegister wd, MSARegister ws); 1009 void ftint_s_d(MSARegister wd, MSARegister ws); 1010 void ftint_u_w(MSARegister wd, MSARegister ws); 1011 void ftint_u_d(MSARegister wd, MSARegister ws); 1012 void ffint_s_w(MSARegister wd, MSARegister ws); 1013 void ffint_s_d(MSARegister wd, MSARegister ws); 1014 void ffint_u_w(MSARegister wd, MSARegister ws); 1015 void ffint_u_d(MSARegister wd, MSARegister ws); 1016 1017 void sll_b(MSARegister wd, MSARegister ws, MSARegister wt); 1018 void sll_h(MSARegister wd, MSARegister ws, MSARegister wt); 1019 void sll_w(MSARegister wd, MSARegister ws, MSARegister wt); 1020 void sll_d(MSARegister wd, MSARegister ws, MSARegister wt); 1021 void sra_b(MSARegister wd, MSARegister ws, MSARegister wt); 1022 void sra_h(MSARegister wd, MSARegister ws, MSARegister wt); 1023 void sra_w(MSARegister wd, MSARegister ws, MSARegister wt); 1024 void sra_d(MSARegister wd, MSARegister ws, MSARegister wt); 1025 void srl_b(MSARegister wd, MSARegister ws, MSARegister wt); 1026 void srl_h(MSARegister wd, MSARegister ws, MSARegister wt); 1027 void srl_w(MSARegister wd, MSARegister ws, MSARegister wt); 1028 void srl_d(MSARegister wd, MSARegister ws, MSARegister wt); 1029 void bclr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1030 void bclr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1031 void bclr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1032 void bclr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1033 void bset_b(MSARegister wd, MSARegister ws, MSARegister wt); 1034 void bset_h(MSARegister wd, MSARegister ws, MSARegister wt); 1035 void bset_w(MSARegister wd, MSARegister ws, MSARegister wt); 1036 void bset_d(MSARegister wd, MSARegister ws, MSARegister wt); 1037 void bneg_b(MSARegister wd, MSARegister ws, MSARegister wt); 1038 void bneg_h(MSARegister wd, MSARegister ws, MSARegister wt); 1039 void bneg_w(MSARegister wd, MSARegister ws, MSARegister wt); 1040 void bneg_d(MSARegister wd, MSARegister ws, MSARegister wt); 1041 void binsl_b(MSARegister wd, MSARegister ws, MSARegister wt); 1042 void binsl_h(MSARegister wd, MSARegister ws, MSARegister wt); 1043 void binsl_w(MSARegister wd, MSARegister ws, MSARegister wt); 1044 void binsl_d(MSARegister wd, MSARegister ws, MSARegister wt); 1045 void binsr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1046 void binsr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1047 void binsr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1048 void binsr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1049 void addv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1050 void addv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1051 void addv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1052 void addv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1053 void subv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1054 void subv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1055 void subv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1056 void subv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1057 void max_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1058 void max_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1059 void max_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1060 void max_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1061 void max_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1062 void max_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1063 void max_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1064 void max_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1065 void min_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1066 void min_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1067 void min_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1068 void min_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1069 void min_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1070 void min_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1071 void min_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1072 void min_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1073 void max_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1074 void max_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1075 void max_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1076 void max_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1077 void min_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1078 void min_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1079 void min_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1080 void min_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1081 void ceq_b(MSARegister wd, MSARegister ws, MSARegister wt); 1082 void ceq_h(MSARegister wd, MSARegister ws, MSARegister wt); 1083 void ceq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1084 void ceq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1085 void clt_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1086 void clt_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1087 void clt_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1088 void clt_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1089 void clt_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1090 void clt_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1091 void clt_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1092 void clt_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1093 void cle_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1094 void cle_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1095 void cle_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1096 void cle_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1097 void cle_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1098 void cle_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1099 void cle_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1100 void cle_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1101 void add_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1102 void add_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1103 void add_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1104 void add_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1105 void adds_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1106 void adds_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1107 void adds_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1108 void adds_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1109 void adds_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1110 void adds_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1111 void adds_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1112 void adds_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1113 void adds_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1114 void adds_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1115 void adds_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1116 void adds_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1117 void ave_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1118 void ave_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1119 void ave_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1120 void ave_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1121 void ave_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1122 void ave_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1123 void ave_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1124 void ave_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1125 void aver_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1126 void aver_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1127 void aver_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1128 void aver_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1129 void aver_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1130 void aver_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1131 void aver_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1132 void aver_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1133 void subs_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1134 void subs_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1135 void subs_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1136 void subs_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1137 void subs_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1138 void subs_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1139 void subs_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1140 void subs_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1141 void subsus_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1142 void subsus_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1143 void subsus_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1144 void subsus_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1145 void subsus_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1146 void subsus_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1147 void subsus_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1148 void subsus_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1149 void subsuu_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1150 void subsuu_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1151 void subsuu_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1152 void subsuu_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1153 void subsuu_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1154 void subsuu_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1155 void subsuu_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1156 void subsuu_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1157 void asub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1158 void asub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1159 void asub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1160 void asub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1161 void asub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1162 void asub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1163 void asub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1164 void asub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1165 void mulv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1166 void mulv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1167 void mulv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1168 void mulv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1169 void maddv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1170 void maddv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1171 void maddv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1172 void maddv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1173 void msubv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1174 void msubv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1175 void msubv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1176 void msubv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1177 void div_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1178 void div_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1179 void div_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1180 void div_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1181 void div_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1182 void div_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1183 void div_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1184 void div_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1185 void mod_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1186 void mod_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1187 void mod_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1188 void mod_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1189 void mod_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1190 void mod_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1191 void mod_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1192 void mod_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1193 void dotp_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1194 void dotp_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1195 void dotp_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1196 void dotp_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1197 void dotp_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1198 void dotp_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1199 void dotp_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1200 void dotp_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1201 void dpadd_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1202 void dpadd_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1203 void dpadd_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1204 void dpadd_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1205 void dpadd_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1206 void dpadd_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1207 void dpadd_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1208 void dpadd_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1209 void dpsub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1210 void dpsub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1211 void dpsub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1212 void dpsub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1213 void dpsub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1214 void dpsub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1215 void dpsub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1216 void dpsub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1217 void sld_b(MSARegister wd, MSARegister ws, Register rt); 1218 void sld_h(MSARegister wd, MSARegister ws, Register rt); 1219 void sld_w(MSARegister wd, MSARegister ws, Register rt); 1220 void sld_d(MSARegister wd, MSARegister ws, Register rt); 1221 void splat_b(MSARegister wd, MSARegister ws, Register rt); 1222 void splat_h(MSARegister wd, MSARegister ws, Register rt); 1223 void splat_w(MSARegister wd, MSARegister ws, Register rt); 1224 void splat_d(MSARegister wd, MSARegister ws, Register rt); 1225 void pckev_b(MSARegister wd, MSARegister ws, MSARegister wt); 1226 void pckev_h(MSARegister wd, MSARegister ws, MSARegister wt); 1227 void pckev_w(MSARegister wd, MSARegister ws, MSARegister wt); 1228 void pckev_d(MSARegister wd, MSARegister ws, MSARegister wt); 1229 void pckod_b(MSARegister wd, MSARegister ws, MSARegister wt); 1230 void pckod_h(MSARegister wd, MSARegister ws, MSARegister wt); 1231 void pckod_w(MSARegister wd, MSARegister ws, MSARegister wt); 1232 void pckod_d(MSARegister wd, MSARegister ws, MSARegister wt); 1233 void ilvl_b(MSARegister wd, MSARegister ws, MSARegister wt); 1234 void ilvl_h(MSARegister wd, MSARegister ws, MSARegister wt); 1235 void ilvl_w(MSARegister wd, MSARegister ws, MSARegister wt); 1236 void ilvl_d(MSARegister wd, MSARegister ws, MSARegister wt); 1237 void ilvr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1238 void ilvr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1239 void ilvr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1240 void ilvr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1241 void ilvev_b(MSARegister wd, MSARegister ws, MSARegister wt); 1242 void ilvev_h(MSARegister wd, MSARegister ws, MSARegister wt); 1243 void ilvev_w(MSARegister wd, MSARegister ws, MSARegister wt); 1244 void ilvev_d(MSARegister wd, MSARegister ws, MSARegister wt); 1245 void ilvod_b(MSARegister wd, MSARegister ws, MSARegister wt); 1246 void ilvod_h(MSARegister wd, MSARegister ws, MSARegister wt); 1247 void ilvod_w(MSARegister wd, MSARegister ws, MSARegister wt); 1248 void ilvod_d(MSARegister wd, MSARegister ws, MSARegister wt); 1249 void vshf_b(MSARegister wd, MSARegister ws, MSARegister wt); 1250 void vshf_h(MSARegister wd, MSARegister ws, MSARegister wt); 1251 void vshf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1252 void vshf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1253 void srar_b(MSARegister wd, MSARegister ws, MSARegister wt); 1254 void srar_h(MSARegister wd, MSARegister ws, MSARegister wt); 1255 void srar_w(MSARegister wd, MSARegister ws, MSARegister wt); 1256 void srar_d(MSARegister wd, MSARegister ws, MSARegister wt); 1257 void srlr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1258 void srlr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1259 void srlr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1260 void srlr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1261 void hadd_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1262 void hadd_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1263 void hadd_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1264 void hadd_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1265 void hadd_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1266 void hadd_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1267 void hadd_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1268 void hadd_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1269 void hsub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1270 void hsub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1271 void hsub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1272 void hsub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1273 void hsub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1274 void hsub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1275 void hsub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1276 void hsub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1277 1278 void fcaf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1279 void fcaf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1280 void fcun_w(MSARegister wd, MSARegister ws, MSARegister wt); 1281 void fcun_d(MSARegister wd, MSARegister ws, MSARegister wt); 1282 void fceq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1283 void fceq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1284 void fcueq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1285 void fcueq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1286 void fclt_w(MSARegister wd, MSARegister ws, MSARegister wt); 1287 void fclt_d(MSARegister wd, MSARegister ws, MSARegister wt); 1288 void fcult_w(MSARegister wd, MSARegister ws, MSARegister wt); 1289 void fcult_d(MSARegister wd, MSARegister ws, MSARegister wt); 1290 void fcle_w(MSARegister wd, MSARegister ws, MSARegister wt); 1291 void fcle_d(MSARegister wd, MSARegister ws, MSARegister wt); 1292 void fcule_w(MSARegister wd, MSARegister ws, MSARegister wt); 1293 void fcule_d(MSARegister wd, MSARegister ws, MSARegister wt); 1294 void fsaf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1295 void fsaf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1296 void fsun_w(MSARegister wd, MSARegister ws, MSARegister wt); 1297 void fsun_d(MSARegister wd, MSARegister ws, MSARegister wt); 1298 void fseq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1299 void fseq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1300 void fsueq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1301 void fsueq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1302 void fslt_w(MSARegister wd, MSARegister ws, MSARegister wt); 1303 void fslt_d(MSARegister wd, MSARegister ws, MSARegister wt); 1304 void fsult_w(MSARegister wd, MSARegister ws, MSARegister wt); 1305 void fsult_d(MSARegister wd, MSARegister ws, MSARegister wt); 1306 void fsle_w(MSARegister wd, MSARegister ws, MSARegister wt); 1307 void fsle_d(MSARegister wd, MSARegister ws, MSARegister wt); 1308 void fsule_w(MSARegister wd, MSARegister ws, MSARegister wt); 1309 void fsule_d(MSARegister wd, MSARegister ws, MSARegister wt); 1310 void fadd_w(MSARegister wd, MSARegister ws, MSARegister wt); 1311 void fadd_d(MSARegister wd, MSARegister ws, MSARegister wt); 1312 void fsub_w(MSARegister wd, MSARegister ws, MSARegister wt); 1313 void fsub_d(MSARegister wd, MSARegister ws, MSARegister wt); 1314 void fmul_w(MSARegister wd, MSARegister ws, MSARegister wt); 1315 void fmul_d(MSARegister wd, MSARegister ws, MSARegister wt); 1316 void fdiv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1317 void fdiv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1318 void fmadd_w(MSARegister wd, MSARegister ws, MSARegister wt); 1319 void fmadd_d(MSARegister wd, MSARegister ws, MSARegister wt); 1320 void fmsub_w(MSARegister wd, MSARegister ws, MSARegister wt); 1321 void fmsub_d(MSARegister wd, MSARegister ws, MSARegister wt); 1322 void fexp2_w(MSARegister wd, MSARegister ws, MSARegister wt); 1323 void fexp2_d(MSARegister wd, MSARegister ws, MSARegister wt); 1324 void fexdo_h(MSARegister wd, MSARegister ws, MSARegister wt); 1325 void fexdo_w(MSARegister wd, MSARegister ws, MSARegister wt); 1326 void ftq_h(MSARegister wd, MSARegister ws, MSARegister wt); 1327 void ftq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1328 void fmin_w(MSARegister wd, MSARegister ws, MSARegister wt); 1329 void fmin_d(MSARegister wd, MSARegister ws, MSARegister wt); 1330 void fmin_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1331 void fmin_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1332 void fmax_w(MSARegister wd, MSARegister ws, MSARegister wt); 1333 void fmax_d(MSARegister wd, MSARegister ws, MSARegister wt); 1334 void fmax_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1335 void fmax_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1336 void fcor_w(MSARegister wd, MSARegister ws, MSARegister wt); 1337 void fcor_d(MSARegister wd, MSARegister ws, MSARegister wt); 1338 void fcune_w(MSARegister wd, MSARegister ws, MSARegister wt); 1339 void fcune_d(MSARegister wd, MSARegister ws, MSARegister wt); 1340 void fcne_w(MSARegister wd, MSARegister ws, MSARegister wt); 1341 void fcne_d(MSARegister wd, MSARegister ws, MSARegister wt); 1342 void mul_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1343 void mul_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1344 void madd_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1345 void madd_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1346 void msub_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1347 void msub_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1348 void fsor_w(MSARegister wd, MSARegister ws, MSARegister wt); 1349 void fsor_d(MSARegister wd, MSARegister ws, MSARegister wt); 1350 void fsune_w(MSARegister wd, MSARegister ws, MSARegister wt); 1351 void fsune_d(MSARegister wd, MSARegister ws, MSARegister wt); 1352 void fsne_w(MSARegister wd, MSARegister ws, MSARegister wt); 1353 void fsne_d(MSARegister wd, MSARegister ws, MSARegister wt); 1354 void mulr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1355 void mulr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1356 void maddr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1357 void maddr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1358 void msubr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1359 void msubr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1360 1361 void sldi_b(MSARegister wd, MSARegister ws, uint32_t n); 1362 void sldi_h(MSARegister wd, MSARegister ws, uint32_t n); 1363 void sldi_w(MSARegister wd, MSARegister ws, uint32_t n); 1364 void sldi_d(MSARegister wd, MSARegister ws, uint32_t n); 1365 void splati_b(MSARegister wd, MSARegister ws, uint32_t n); 1366 void splati_h(MSARegister wd, MSARegister ws, uint32_t n); 1367 void splati_w(MSARegister wd, MSARegister ws, uint32_t n); 1368 void splati_d(MSARegister wd, MSARegister ws, uint32_t n); 1369 void copy_s_b(Register rd, MSARegister ws, uint32_t n); 1370 void copy_s_h(Register rd, MSARegister ws, uint32_t n); 1371 void copy_s_w(Register rd, MSARegister ws, uint32_t n); 1372 void copy_s_d(Register rd, MSARegister ws, uint32_t n); 1373 void copy_u_b(Register rd, MSARegister ws, uint32_t n); 1374 void copy_u_h(Register rd, MSARegister ws, uint32_t n); 1375 void copy_u_w(Register rd, MSARegister ws, uint32_t n); 1376 void insert_b(MSARegister wd, uint32_t n, Register rs); 1377 void insert_h(MSARegister wd, uint32_t n, Register rs); 1378 void insert_w(MSARegister wd, uint32_t n, Register rs); 1379 void insert_d(MSARegister wd, uint32_t n, Register rs); 1380 void insve_b(MSARegister wd, uint32_t n, MSARegister ws); 1381 void insve_h(MSARegister wd, uint32_t n, MSARegister ws); 1382 void insve_w(MSARegister wd, uint32_t n, MSARegister ws); 1383 void insve_d(MSARegister wd, uint32_t n, MSARegister ws); 1384 void move_v(MSARegister wd, MSARegister ws); 1385 void ctcmsa(MSAControlRegister cd, Register rs); 1386 void cfcmsa(Register rd, MSAControlRegister cs); 1387 1388 void slli_b(MSARegister wd, MSARegister ws, uint32_t m); 1389 void slli_h(MSARegister wd, MSARegister ws, uint32_t m); 1390 void slli_w(MSARegister wd, MSARegister ws, uint32_t m); 1391 void slli_d(MSARegister wd, MSARegister ws, uint32_t m); 1392 void srai_b(MSARegister wd, MSARegister ws, uint32_t m); 1393 void srai_h(MSARegister wd, MSARegister ws, uint32_t m); 1394 void srai_w(MSARegister wd, MSARegister ws, uint32_t m); 1395 void srai_d(MSARegister wd, MSARegister ws, uint32_t m); 1396 void srli_b(MSARegister wd, MSARegister ws, uint32_t m); 1397 void srli_h(MSARegister wd, MSARegister ws, uint32_t m); 1398 void srli_w(MSARegister wd, MSARegister ws, uint32_t m); 1399 void srli_d(MSARegister wd, MSARegister ws, uint32_t m); 1400 void bclri_b(MSARegister wd, MSARegister ws, uint32_t m); 1401 void bclri_h(MSARegister wd, MSARegister ws, uint32_t m); 1402 void bclri_w(MSARegister wd, MSARegister ws, uint32_t m); 1403 void bclri_d(MSARegister wd, MSARegister ws, uint32_t m); 1404 void bseti_b(MSARegister wd, MSARegister ws, uint32_t m); 1405 void bseti_h(MSARegister wd, MSARegister ws, uint32_t m); 1406 void bseti_w(MSARegister wd, MSARegister ws, uint32_t m); 1407 void bseti_d(MSARegister wd, MSARegister ws, uint32_t m); 1408 void bnegi_b(MSARegister wd, MSARegister ws, uint32_t m); 1409 void bnegi_h(MSARegister wd, MSARegister ws, uint32_t m); 1410 void bnegi_w(MSARegister wd, MSARegister ws, uint32_t m); 1411 void bnegi_d(MSARegister wd, MSARegister ws, uint32_t m); 1412 void binsli_b(MSARegister wd, MSARegister ws, uint32_t m); 1413 void binsli_h(MSARegister wd, MSARegister ws, uint32_t m); 1414 void binsli_w(MSARegister wd, MSARegister ws, uint32_t m); 1415 void binsli_d(MSARegister wd, MSARegister ws, uint32_t m); 1416 void binsri_b(MSARegister wd, MSARegister ws, uint32_t m); 1417 void binsri_h(MSARegister wd, MSARegister ws, uint32_t m); 1418 void binsri_w(MSARegister wd, MSARegister ws, uint32_t m); 1419 void binsri_d(MSARegister wd, MSARegister ws, uint32_t m); 1420 void sat_s_b(MSARegister wd, MSARegister ws, uint32_t m); 1421 void sat_s_h(MSARegister wd, MSARegister ws, uint32_t m); 1422 void sat_s_w(MSARegister wd, MSARegister ws, uint32_t m); 1423 void sat_s_d(MSARegister wd, MSARegister ws, uint32_t m); 1424 void sat_u_b(MSARegister wd, MSARegister ws, uint32_t m); 1425 void sat_u_h(MSARegister wd, MSARegister ws, uint32_t m); 1426 void sat_u_w(MSARegister wd, MSARegister ws, uint32_t m); 1427 void sat_u_d(MSARegister wd, MSARegister ws, uint32_t m); 1428 void srari_b(MSARegister wd, MSARegister ws, uint32_t m); 1429 void srari_h(MSARegister wd, MSARegister ws, uint32_t m); 1430 void srari_w(MSARegister wd, MSARegister ws, uint32_t m); 1431 void srari_d(MSARegister wd, MSARegister ws, uint32_t m); 1432 void srlri_b(MSARegister wd, MSARegister ws, uint32_t m); 1433 void srlri_h(MSARegister wd, MSARegister ws, uint32_t m); 1434 void srlri_w(MSARegister wd, MSARegister ws, uint32_t m); 1435 void srlri_d(MSARegister wd, MSARegister ws, uint32_t m); 1436 1437 // Check the code size generated from label to here. SizeOfCodeGeneratedSince(Label * label)1438 int SizeOfCodeGeneratedSince(Label* label) { 1439 return pc_offset() - label->pos(); 1440 } 1441 1442 // Check the number of instructions generated from label to here. InstructionsGeneratedSince(Label * label)1443 int InstructionsGeneratedSince(Label* label) { 1444 return SizeOfCodeGeneratedSince(label) / kInstrSize; 1445 } 1446 1447 // Class for scoping postponing the trampoline pool generation. 1448 class V8_NODISCARD BlockTrampolinePoolScope { 1449 public: BlockTrampolinePoolScope(Assembler * assem)1450 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) { 1451 assem_->StartBlockTrampolinePool(); 1452 } ~BlockTrampolinePoolScope()1453 ~BlockTrampolinePoolScope() { assem_->EndBlockTrampolinePool(); } 1454 1455 private: 1456 Assembler* assem_; 1457 1458 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope); 1459 }; 1460 1461 // Class for postponing the assembly buffer growth. Typically used for 1462 // sequences of instructions that must be emitted as a unit, before 1463 // buffer growth (and relocation) can occur. 1464 // This blocking scope is not nestable. 1465 class V8_NODISCARD BlockGrowBufferScope { 1466 public: BlockGrowBufferScope(Assembler * assem)1467 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) { 1468 assem_->StartBlockGrowBuffer(); 1469 } ~BlockGrowBufferScope()1470 ~BlockGrowBufferScope() { assem_->EndBlockGrowBuffer(); } 1471 1472 private: 1473 Assembler* assem_; 1474 1475 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope); 1476 }; 1477 1478 // Record a deoptimization reason that can be used by a log or cpu profiler. 1479 // Use --trace-deopt to enable. 1480 void RecordDeoptReason(DeoptimizeReason reason, uint32_t node_id, 1481 SourcePosition position, int id); 1482 1483 static int RelocateInternalReference(RelocInfo::Mode rmode, Address pc, 1484 intptr_t pc_delta); 1485 1486 // Writes a single byte or word of data in the code stream. Used for 1487 // inline tables, e.g., jump-tables. 1488 void db(uint8_t data); 1489 void dd(uint32_t data, RelocInfo::Mode rmode = RelocInfo::NONE); 1490 void dq(uint64_t data, RelocInfo::Mode rmode = RelocInfo::NONE); 1491 void dp(uintptr_t data, RelocInfo::Mode rmode = RelocInfo::NONE) { 1492 dq(data, rmode); 1493 } 1494 void dd(Label* label); 1495 1496 // Postpone the generation of the trampoline pool for the specified number of 1497 // instructions. 1498 void BlockTrampolinePoolFor(int instructions); 1499 1500 // Check if there is less than kGap bytes available in the buffer. 1501 // If this is the case, we need to grow the buffer before emitting 1502 // an instruction or relocation information. overflow()1503 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; } 1504 1505 // Get the number of bytes available in the buffer. available_space()1506 inline intptr_t available_space() const { 1507 return reloc_info_writer.pos() - pc_; 1508 } 1509 1510 // Read/patch instructions. instr_at(Address pc)1511 static Instr instr_at(Address pc) { return *reinterpret_cast<Instr*>(pc); } instr_at_put(Address pc,Instr instr)1512 static void instr_at_put(Address pc, Instr instr) { 1513 *reinterpret_cast<Instr*>(pc) = instr; 1514 } instr_at(int pos)1515 Instr instr_at(int pos) { 1516 return *reinterpret_cast<Instr*>(buffer_start_ + pos); 1517 } instr_at_put(int pos,Instr instr)1518 void instr_at_put(int pos, Instr instr) { 1519 *reinterpret_cast<Instr*>(buffer_start_ + pos) = instr; 1520 } 1521 1522 // Check if an instruction is a branch of some kind. 1523 static bool IsBranch(Instr instr); 1524 static bool IsMsaBranch(Instr instr); 1525 static bool IsBc(Instr instr); 1526 static bool IsNal(Instr instr); 1527 static bool IsBzc(Instr instr); 1528 1529 static bool IsBeq(Instr instr); 1530 static bool IsBne(Instr instr); 1531 static bool IsBeqzc(Instr instr); 1532 static bool IsBnezc(Instr instr); 1533 static bool IsBeqc(Instr instr); 1534 static bool IsBnec(Instr instr); 1535 1536 static bool IsJump(Instr instr); 1537 static bool IsJ(Instr instr); 1538 static bool IsLui(Instr instr); 1539 static bool IsOri(Instr instr); 1540 static bool IsMov(Instr instr, Register rd, Register rs); 1541 1542 static bool IsJal(Instr instr); 1543 static bool IsJr(Instr instr); 1544 static bool IsJalr(Instr instr); 1545 1546 static bool IsNop(Instr instr, unsigned int type); 1547 static bool IsPop(Instr instr); 1548 static bool IsPush(Instr instr); 1549 static bool IsLwRegFpOffset(Instr instr); 1550 static bool IsSwRegFpOffset(Instr instr); 1551 static bool IsLwRegFpNegOffset(Instr instr); 1552 static bool IsSwRegFpNegOffset(Instr instr); 1553 1554 static Register GetRtReg(Instr instr); 1555 static Register GetRsReg(Instr instr); 1556 static Register GetRdReg(Instr instr); 1557 1558 static uint32_t GetRt(Instr instr); 1559 static uint32_t GetRtField(Instr instr); 1560 static uint32_t GetRs(Instr instr); 1561 static uint32_t GetRsField(Instr instr); 1562 static uint32_t GetRd(Instr instr); 1563 static uint32_t GetRdField(Instr instr); 1564 static uint32_t GetSa(Instr instr); 1565 static uint32_t GetSaField(Instr instr); 1566 static uint32_t GetOpcodeField(Instr instr); 1567 static uint32_t GetFunction(Instr instr); 1568 static uint32_t GetFunctionField(Instr instr); 1569 static uint32_t GetImmediate16(Instr instr); 1570 static uint32_t GetLabelConst(Instr instr); 1571 1572 static int32_t GetBranchOffset(Instr instr); 1573 static bool IsLw(Instr instr); 1574 static int16_t GetLwOffset(Instr instr); 1575 static Instr SetLwOffset(Instr instr, int16_t offset); 1576 1577 static bool IsSw(Instr instr); 1578 static Instr SetSwOffset(Instr instr, int16_t offset); 1579 static bool IsAddImmediate(Instr instr); 1580 static Instr SetAddImmediateOffset(Instr instr, int16_t offset); 1581 1582 static bool IsAndImmediate(Instr instr); 1583 static bool IsEmittedConstant(Instr instr); 1584 1585 void CheckTrampolinePool(); 1586 IsPrevInstrCompactBranch()1587 bool IsPrevInstrCompactBranch() { return prev_instr_compact_branch_; } IsCompactBranchSupported()1588 static bool IsCompactBranchSupported() { return kArchVariant == kMips64r6; } 1589 UnboundLabelsCount()1590 inline int UnboundLabelsCount() { return unbound_labels_count_; } 1591 1592 protected: 1593 // Load Scaled Address instructions. 1594 void lsa(Register rd, Register rt, Register rs, uint8_t sa); 1595 void dlsa(Register rd, Register rt, Register rs, uint8_t sa); 1596 1597 // Readable constants for base and offset adjustment helper, these indicate if 1598 // aside from offset, another value like offset + 4 should fit into int16. 1599 enum class OffsetAccessType : bool { 1600 SINGLE_ACCESS = false, 1601 TWO_ACCESSES = true 1602 }; 1603 1604 // Helper function for memory load/store using base register and offset. 1605 void AdjustBaseAndOffset( 1606 MemOperand* src, 1607 OffsetAccessType access_type = OffsetAccessType::SINGLE_ACCESS, 1608 int second_access_add_to_offset = 4); 1609 1610 inline static void set_target_internal_reference_encoded_at(Address pc, 1611 Address target); 1612 buffer_space()1613 int64_t buffer_space() const { return reloc_info_writer.pos() - pc_; } 1614 1615 // Decode branch instruction at pos and return branch target pos. 1616 int target_at(int pos, bool is_internal); 1617 1618 // Patch branch instruction at pos to branch to given branch target pos. 1619 void target_at_put(int pos, int target_pos, bool is_internal); 1620 1621 // Say if we need to relocate with this mode. 1622 bool MustUseReg(RelocInfo::Mode rmode); 1623 1624 // Record reloc info for current pc_. 1625 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1626 1627 // Block the emission of the trampoline pool before pc_offset. BlockTrampolinePoolBefore(int pc_offset)1628 void BlockTrampolinePoolBefore(int pc_offset) { 1629 if (no_trampoline_pool_before_ < pc_offset) 1630 no_trampoline_pool_before_ = pc_offset; 1631 } 1632 StartBlockTrampolinePool()1633 void StartBlockTrampolinePool() { trampoline_pool_blocked_nesting_++; } 1634 EndBlockTrampolinePool()1635 void EndBlockTrampolinePool() { 1636 trampoline_pool_blocked_nesting_--; 1637 if (trampoline_pool_blocked_nesting_ == 0) { 1638 CheckTrampolinePoolQuick(1); 1639 } 1640 } 1641 is_trampoline_pool_blocked()1642 bool is_trampoline_pool_blocked() const { 1643 return trampoline_pool_blocked_nesting_ > 0; 1644 } 1645 has_exception()1646 bool has_exception() const { return internal_trampoline_exception_; } 1647 is_trampoline_emitted()1648 bool is_trampoline_emitted() const { return trampoline_emitted_; } 1649 1650 // Temporarily block automatic assembly buffer growth. StartBlockGrowBuffer()1651 void StartBlockGrowBuffer() { 1652 DCHECK(!block_buffer_growth_); 1653 block_buffer_growth_ = true; 1654 } 1655 EndBlockGrowBuffer()1656 void EndBlockGrowBuffer() { 1657 DCHECK(block_buffer_growth_); 1658 block_buffer_growth_ = false; 1659 } 1660 is_buffer_growth_blocked()1661 bool is_buffer_growth_blocked() const { return block_buffer_growth_; } 1662 EmitForbiddenSlotInstruction()1663 void EmitForbiddenSlotInstruction() { 1664 if (IsPrevInstrCompactBranch()) { 1665 nop(); 1666 } 1667 } 1668 1669 void CheckTrampolinePoolQuick(int extra_instructions = 0) { 1670 if (pc_offset() >= next_buffer_check_ - extra_instructions * kInstrSize) { 1671 CheckTrampolinePool(); 1672 } 1673 } 1674 set_last_call_pc_(byte * pc)1675 void set_last_call_pc_(byte* pc) { last_call_pc_ = pc; } 1676 1677 #ifdef DEBUG EmbeddedObjectMatches(int pc_offset,Handle<Object> object)1678 bool EmbeddedObjectMatches(int pc_offset, Handle<Object> object) { 1679 return target_address_at( 1680 reinterpret_cast<Address>(buffer_->start() + pc_offset)) == 1681 (IsOnHeap() ? object->ptr() : object.address()); 1682 } 1683 #endif 1684 1685 private: 1686 // Avoid overflows for displacements etc. 1687 static const int kMaximalBufferSize = 512 * MB; 1688 1689 // Buffer size and constant pool distance are checked together at regular 1690 // intervals of kBufferCheckInterval emitted bytes. 1691 static constexpr int kBufferCheckInterval = 1 * KB / 2; 1692 1693 // Code generation. 1694 // The relocation writer's position is at least kGap bytes below the end of 1695 // the generated instructions. This is so that multi-instruction sequences do 1696 // not have to check for overflow. The same is true for writes of large 1697 // relocation info entries. 1698 static constexpr int kGap = 64; 1699 STATIC_ASSERT(AssemblerBase::kMinimalBufferSize >= 2 * kGap); 1700 1701 // Repeated checking whether the trampoline pool should be emitted is rather 1702 // expensive. By default we only check again once a number of instructions 1703 // has been generated. 1704 static constexpr int kCheckConstIntervalInst = 32; 1705 static constexpr int kCheckConstInterval = 1706 kCheckConstIntervalInst * kInstrSize; 1707 1708 int next_buffer_check_; // pc offset of next buffer check. 1709 1710 // Emission of the trampoline pool may be blocked in some code sequences. 1711 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero. 1712 int no_trampoline_pool_before_; // Block emission before this pc offset. 1713 1714 // Keep track of the last emitted pool to guarantee a maximal distance. 1715 int last_trampoline_pool_end_; // pc offset of the end of the last pool. 1716 1717 // Automatic growth of the assembly buffer may be blocked for some sequences. 1718 bool block_buffer_growth_; // Block growth when true. 1719 1720 // Relocation information generation. 1721 // Each relocation is encoded as a variable size value. 1722 static constexpr int kMaxRelocSize = RelocInfoWriter::kMaxSize; 1723 RelocInfoWriter reloc_info_writer; 1724 1725 // The bound position, before this we cannot do instruction elimination. 1726 int last_bound_pos_; 1727 1728 // Readable constants for compact branch handling in emit() 1729 enum class CompactBranchType : bool { NO = false, COMPACT_BRANCH = true }; 1730 1731 // Code emission. 1732 inline void CheckBuffer(); 1733 void GrowBuffer(); 1734 inline void emit(Instr x, 1735 CompactBranchType is_compact_branch = CompactBranchType::NO); 1736 inline void emit(uint64_t x); 1737 inline void CheckForEmitInForbiddenSlot(); 1738 template <typename T> 1739 inline void EmitHelper(T x); 1740 inline void EmitHelper(Instr x, CompactBranchType is_compact_branch); 1741 1742 // Instruction generation. 1743 // We have 3 different kind of encoding layout on MIPS. 1744 // However due to many different types of objects encoded in the same fields 1745 // we have quite a few aliases for each mode. 1746 // Using the same structure to refer to Register and FPURegister would spare a 1747 // few aliases, but mixing both does not look clean to me. 1748 // Anyway we could surely implement this differently. 1749 1750 void GenInstrRegister(Opcode opcode, Register rs, Register rt, Register rd, 1751 uint16_t sa = 0, SecondaryField func = nullptrSF); 1752 1753 void GenInstrRegister(Opcode opcode, Register rs, Register rt, uint16_t msb, 1754 uint16_t lsb, SecondaryField func); 1755 1756 void GenInstrRegister(Opcode opcode, SecondaryField fmt, FPURegister ft, 1757 FPURegister fs, FPURegister fd, 1758 SecondaryField func = nullptrSF); 1759 1760 void GenInstrRegister(Opcode opcode, FPURegister fr, FPURegister ft, 1761 FPURegister fs, FPURegister fd, 1762 SecondaryField func = nullptrSF); 1763 1764 void GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, 1765 FPURegister fs, FPURegister fd, 1766 SecondaryField func = nullptrSF); 1767 1768 void GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, 1769 FPUControlRegister fs, SecondaryField func = nullptrSF); 1770 1771 void GenInstrImmediate( 1772 Opcode opcode, Register rs, Register rt, int32_t j, 1773 CompactBranchType is_compact_branch = CompactBranchType::NO); 1774 void GenInstrImmediate( 1775 Opcode opcode, Register rs, SecondaryField SF, int32_t j, 1776 CompactBranchType is_compact_branch = CompactBranchType::NO); 1777 void GenInstrImmediate( 1778 Opcode opcode, Register r1, FPURegister r2, int32_t j, 1779 CompactBranchType is_compact_branch = CompactBranchType::NO); 1780 void GenInstrImmediate(Opcode opcode, Register base, Register rt, 1781 int32_t offset9, int bit6, SecondaryField func); 1782 void GenInstrImmediate( 1783 Opcode opcode, Register rs, int32_t offset21, 1784 CompactBranchType is_compact_branch = CompactBranchType::NO); 1785 void GenInstrImmediate(Opcode opcode, Register rs, uint32_t offset21); 1786 void GenInstrImmediate( 1787 Opcode opcode, int32_t offset26, 1788 CompactBranchType is_compact_branch = CompactBranchType::NO); 1789 1790 void GenInstrJump(Opcode opcode, uint32_t address); 1791 1792 // MSA 1793 void GenInstrMsaI8(SecondaryField operation, uint32_t imm8, MSARegister ws, 1794 MSARegister wd); 1795 1796 void GenInstrMsaI5(SecondaryField operation, SecondaryField df, int32_t imm5, 1797 MSARegister ws, MSARegister wd); 1798 1799 void GenInstrMsaBit(SecondaryField operation, SecondaryField df, uint32_t m, 1800 MSARegister ws, MSARegister wd); 1801 1802 void GenInstrMsaI10(SecondaryField operation, SecondaryField df, 1803 int32_t imm10, MSARegister wd); 1804 1805 template <typename RegType> 1806 void GenInstrMsa3R(SecondaryField operation, SecondaryField df, RegType t, 1807 MSARegister ws, MSARegister wd); 1808 1809 template <typename DstType, typename SrcType> 1810 void GenInstrMsaElm(SecondaryField operation, SecondaryField df, uint32_t n, 1811 SrcType src, DstType dst); 1812 1813 void GenInstrMsa3RF(SecondaryField operation, uint32_t df, MSARegister wt, 1814 MSARegister ws, MSARegister wd); 1815 1816 void GenInstrMsaVec(SecondaryField operation, MSARegister wt, MSARegister ws, 1817 MSARegister wd); 1818 1819 void GenInstrMsaMI10(SecondaryField operation, int32_t s10, Register rs, 1820 MSARegister wd); 1821 1822 void GenInstrMsa2R(SecondaryField operation, SecondaryField df, 1823 MSARegister ws, MSARegister wd); 1824 1825 void GenInstrMsa2RF(SecondaryField operation, SecondaryField df, 1826 MSARegister ws, MSARegister wd); 1827 1828 void GenInstrMsaBranch(SecondaryField operation, MSARegister wt, 1829 int32_t offset16); 1830 is_valid_msa_df_m(SecondaryField bit_df,uint32_t m)1831 inline bool is_valid_msa_df_m(SecondaryField bit_df, uint32_t m) { 1832 switch (bit_df) { 1833 case BIT_DF_b: 1834 return is_uint3(m); 1835 case BIT_DF_h: 1836 return is_uint4(m); 1837 case BIT_DF_w: 1838 return is_uint5(m); 1839 case BIT_DF_d: 1840 return is_uint6(m); 1841 default: 1842 return false; 1843 } 1844 } 1845 is_valid_msa_df_n(SecondaryField elm_df,uint32_t n)1846 inline bool is_valid_msa_df_n(SecondaryField elm_df, uint32_t n) { 1847 switch (elm_df) { 1848 case ELM_DF_B: 1849 return is_uint4(n); 1850 case ELM_DF_H: 1851 return is_uint3(n); 1852 case ELM_DF_W: 1853 return is_uint2(n); 1854 case ELM_DF_D: 1855 return is_uint1(n); 1856 default: 1857 return false; 1858 } 1859 } 1860 1861 // Labels. 1862 void print(const Label* L); 1863 void bind_to(Label* L, int pos); 1864 void next(Label* L, bool is_internal); 1865 1866 // One trampoline consists of: 1867 // - space for trampoline slots, 1868 // - space for labels. 1869 // 1870 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize. 1871 // Space for trampoline slots precedes space for labels. Each label is of one 1872 // instruction size, so total amount for labels is equal to 1873 // label_count * kInstrSize. 1874 class Trampoline { 1875 public: Trampoline()1876 Trampoline() { 1877 start_ = 0; 1878 next_slot_ = 0; 1879 free_slot_count_ = 0; 1880 end_ = 0; 1881 } Trampoline(int start,int slot_count)1882 Trampoline(int start, int slot_count) { 1883 start_ = start; 1884 next_slot_ = start; 1885 free_slot_count_ = slot_count; 1886 end_ = start + slot_count * kTrampolineSlotsSize; 1887 } start()1888 int start() { return start_; } end()1889 int end() { return end_; } take_slot()1890 int take_slot() { 1891 int trampoline_slot = kInvalidSlotPos; 1892 if (free_slot_count_ <= 0) { 1893 // We have run out of space on trampolines. 1894 // Make sure we fail in debug mode, so we become aware of each case 1895 // when this happens. 1896 DCHECK(0); 1897 // Internal exception will be caught. 1898 } else { 1899 trampoline_slot = next_slot_; 1900 free_slot_count_--; 1901 next_slot_ += kTrampolineSlotsSize; 1902 } 1903 return trampoline_slot; 1904 } 1905 1906 private: 1907 int start_; 1908 int end_; 1909 int next_slot_; 1910 int free_slot_count_; 1911 }; 1912 1913 int32_t get_trampoline_entry(int32_t pos); 1914 int unbound_labels_count_; 1915 // After trampoline is emitted, long branches are used in generated code for 1916 // the forward branches whose target offsets could be beyond reach of branch 1917 // instruction. We use this information to trigger different mode of 1918 // branch instruction generation, where we use jump instructions rather 1919 // than regular branch instructions. 1920 bool trampoline_emitted_; 1921 static constexpr int kInvalidSlotPos = -1; 1922 1923 // Internal reference positions, required for unbounded internal reference 1924 // labels. 1925 std::set<int64_t> internal_reference_positions_; is_internal_reference(Label * L)1926 bool is_internal_reference(Label* L) { 1927 return internal_reference_positions_.find(L->pos()) != 1928 internal_reference_positions_.end(); 1929 } 1930 EmittedCompactBranchInstruction()1931 void EmittedCompactBranchInstruction() { prev_instr_compact_branch_ = true; } ClearCompactBranchState()1932 void ClearCompactBranchState() { prev_instr_compact_branch_ = false; } 1933 bool prev_instr_compact_branch_ = false; 1934 1935 Trampoline trampoline_; 1936 bool internal_trampoline_exception_; 1937 1938 // Keep track of the last Call's position to ensure that safepoint can get the 1939 // correct information even if there is a trampoline immediately after the 1940 // Call. 1941 byte* last_call_pc_; 1942 1943 RegList scratch_register_list_; 1944 1945 private: 1946 void AllocateAndInstallRequestedHeapObjects(Isolate* isolate); 1947 1948 int WriteCodeComments(); 1949 1950 friend class RegExpMacroAssemblerMIPS; 1951 friend class RelocInfo; 1952 friend class BlockTrampolinePoolScope; 1953 friend class EnsureSpace; 1954 }; 1955 1956 class EnsureSpace { 1957 public: 1958 explicit inline EnsureSpace(Assembler* assembler); 1959 }; 1960 1961 class V8_EXPORT_PRIVATE V8_NODISCARD UseScratchRegisterScope { 1962 public: 1963 explicit UseScratchRegisterScope(Assembler* assembler); 1964 ~UseScratchRegisterScope(); 1965 1966 Register Acquire(); 1967 bool hasAvailable() const; 1968 Include(const RegList & list)1969 void Include(const RegList& list) { *available_ |= list; } Exclude(const RegList & list)1970 void Exclude(const RegList& list) { *available_ &= ~list; } 1971 void Include(const Register& reg1, const Register& reg2 = no_reg) { 1972 RegList list(reg1.bit() | reg2.bit()); 1973 Include(list); 1974 } 1975 void Exclude(const Register& reg1, const Register& reg2 = no_reg) { 1976 RegList list(reg1.bit() | reg2.bit()); 1977 Exclude(list); 1978 } 1979 1980 private: 1981 RegList* available_; 1982 RegList old_available_; 1983 }; 1984 1985 // Helper struct for load lane and store lane to indicate what memory size 1986 // to be encoded in the opcode, and the new lane index. 1987 class LoadStoreLaneParams { 1988 public: 1989 MSASize sz; 1990 uint8_t laneidx; 1991 1992 LoadStoreLaneParams(MachineRepresentation rep, uint8_t laneidx); 1993 1994 private: LoadStoreLaneParams(uint8_t laneidx,MSASize sz,int lanes)1995 LoadStoreLaneParams(uint8_t laneidx, MSASize sz, int lanes) 1996 : sz(sz), laneidx(laneidx % lanes) {} 1997 }; 1998 1999 } // namespace internal 2000 } // namespace v8 2001 2002 #endif // V8_CODEGEN_MIPS64_ASSEMBLER_MIPS64_H_ 2003