1
2 /*
3 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 */
18
19 #if defined(TARGET_LINUX_POWER)
20 #error "Source cannot be compiled for POWER architectures"
21 #include "xmm2altivec.h"
22 #else
23 #include <immintrin.h>
24 #endif
25 #include "acos_defs.h"
26
27 extern "C" __m256 __fvs_acos_fma3_256(__m256 const a);
28
__fvs_acos_fma3_256(__m256 const a)29 __m256 __fvs_acos_fma3_256(__m256 const a)
30 {
31 __m256 const ABS_MASK = (__m256)_mm256_set1_epi32(ABS_MASK_I);
32 __m256 const SGN_MASK = (__m256)_mm256_set1_epi32(SGN_MASK_I);
33 __m256 const ONE = _mm256_set1_ps(1.0f);
34 __m256i const ZERO = _mm256_set1_epi32(0);
35 __m256i const THRESHOLD = (__m256i)_mm256_set1_ps(THRESHOLD_F);
36 __m256 const PI = _mm256_set1_ps(PI_F);
37
38 // p0 coefficients
39 __m256 const A0 = _mm256_set1_ps(A0_F);
40 __m256 const B0 = _mm256_set1_ps(B0_F);
41 __m256 const C0 = _mm256_set1_ps(C0_F);
42 __m256 const D0 = _mm256_set1_ps(D0_F);
43 __m256 const E0 = _mm256_set1_ps(E0_F);
44 __m256 const F0 = _mm256_set1_ps(F0_F);
45
46 // p1 coefficients
47 __m256 const A1 = _mm256_set1_ps(A1_F);
48 __m256 const B1 = _mm256_set1_ps(B1_F);
49 __m256 const C1 = _mm256_set1_ps(C1_F);
50 __m256 const D1 = _mm256_set1_ps(D1_F);
51 __m256 const E1 = _mm256_set1_ps(E1_F);
52 __m256 const F1 = _mm256_set1_ps(F1_F);
53
54 __m256 x, x2, a3, sq, p0, p1, res, c, cmp0;
55 x = _mm256_and_ps(ABS_MASK, a);
56 sq = _mm256_sub_ps(ONE, x);
57 sq = _mm256_sqrt_ps(sq); // sqrt(1 - |a|)
58
59 __m256 pi_mask = (__m256)_mm256_cmpgt_epi32(ZERO, (__m256i)a);
60 cmp0 = (__m256)_mm256_cmpgt_epi32((__m256i)x, THRESHOLD);
61
62 // polynomials evaluation
63 x2 = _mm256_mul_ps(a, a);
64 c = _mm256_sub_ps(F0, a);
65 p1 = _mm256_fmadd_ps(A1, x, B1);
66 p0 = _mm256_fmadd_ps(A0, x2, B0);
67 p1 = _mm256_fmadd_ps(p1, x, C1);
68 p0 = _mm256_fmadd_ps(p0, x2, C0);
69 p1 = _mm256_fmadd_ps(p1, x, D1);
70 a3 = _mm256_mul_ps(x2, a);
71 p0 = _mm256_fmadd_ps(p0, x2, D0);
72 p1 = _mm256_fmadd_ps(p1, x, E1);
73 p0 = _mm256_fmadd_ps(p0, x2, E0);
74 p1 = _mm256_fmadd_ps(p1, x, F1);
75 p0 = _mm256_fmadd_ps(p0, a3, c);
76
77 pi_mask = _mm256_and_ps(pi_mask, PI);
78 p1 = _mm256_fmsub_ps(sq, p1, pi_mask);
79
80 __m256 sign;
81 sign = _mm256_and_ps(a, SGN_MASK);
82
83 __m256 fix;
84 fix = _mm256_cmp_ps(a, ONE, _CMP_GT_OQ);
85 fix = _mm256_and_ps(fix, SGN_MASK);
86 fix = _mm256_xor_ps(fix, sign);
87 p1 = _mm256_xor_ps(p1, fix);
88
89 res = _mm256_blendv_ps(p0, p1, cmp0);
90
91 return res;
92 }
93