1 /* 2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 * 16 */ 17 18 #ifndef MACHREG_H_ 19 #define MACHREG_H_ 20 21 #include "gbldefs.h" 22 23 extern const int scratch_regs[]; 24 25 /* Define registers for x86-32. 26 */ 27 28 /*------------------------------------------------------------------------ 29 * Registers must be listed with the callee-saved registers at the 30 * end, and must be numbered as follows: 31 * 32 * non-callee-saved GP regs: 1 --> (IR_FIRST_CALLEE_SAVE - 1) 33 * callee-saved GP regs: IR_FIRST_CALLEE_SAVE --> IR_LAST_CALLEE_SAVE 34 * 35 * and similarly for the XM registers. This numbering is assumed in 36 * function 'save_callee_save_regs()'. 37 *----------------------------------------------------------------------*/ 38 39 /*------------- 40 * GP registers 41 *-----------*/ 42 43 typedef enum { 44 NO_REG = -1, 45 IR_EAX = 1, 46 IR_ECX, 47 IR_EDX, 48 IR_ESI, /* = 4; first callee-saved on x86-32 */ 49 IR_EDI, 50 IR_EBX, 51 IR_EBP, /* = 7; last callee-saved on x86-32, i.e. 4 c.s. GP regs */ 52 IR_ESP /* = 8 */ 53 } IR_REGS; 54 55 #define IR_FIRST_CALLEE_SAVE IR_ESI 56 #define IR_LAST_CALLEE_SAVE IR_EBP 57 58 #define GP_REG_NAMES \ 59 { \ 60 "%badreg0", "%eax", "%ecx", "%edx", "%esi", "%edi", "%ebx", "%ebp", "%esp" \ 61 } 62 63 #define WORD_REG_NAMES \ 64 { \ 65 "%badreg1", "%eax", "%ecx", "%edx", "%esi", "%edi", "%ebx", "%ebp", "%esp" \ 66 } 67 68 #define HALF_REG_NAMES \ 69 { \ 70 "%badreg2", "%ax", "%cx", "%dx", "%si", "%di", "%bx", "%bp", "%sp" \ 71 } 72 73 #define BYTE_REG_NAMES \ 74 { \ 75 "%badreg3", "%al", "%cl", "%dl", "%badreg4", "%badreg5", "%bl", \ 76 "%badreg6", "%badreg7" \ 77 } 78 79 /* Synonyms for GP register symbols. 80 */ 81 #define IR_RAX IR_EAX 82 #define IR_RCX IR_ECX 83 #define IR_RDX IR_EDX 84 #define IR_RSI IR_ESI 85 #define IR_RDI IR_EDI 86 #define IR_RBX IR_EBX 87 #define IR_FRAMEP IR_EBP 88 #define IR_STACKP IR_ESP 89 90 #define N_GP_REGS 8 91 #define IR_FIRST 1 92 #define IR_LAST 8 93 94 /*--------------------------- 95 * XMM, YMM and ZMM registers 96 *-------------------------*/ 97 98 typedef enum { 99 XR_XMM0 = 1, 100 XR_XMM1, 101 XR_XMM2, 102 XR_XMM3, 103 XR_XMM4, 104 XR_XMM5, 105 XR_XMM6, 106 XR_XMM7 107 } XR_REGS; 108 109 /* 32-bit ABI - no callee-saved xmm registers. Note, the last 110 * non-callee-saved XM register must be ( XR_FIRST_CALLEE_SAVE - 1 ). 111 */ 112 #define XR_FIRST_CALLEE_SAVE 9 /* no callee-saved xmm regs */ 113 #define XR_LAST_CALLEE_SAVE 8 114 115 #define XMM_REG_NAMES \ 116 { \ 117 "%badxmm", "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", \ 118 "%xmm7" \ 119 } 120 121 #define YMM_REG_NAMES \ 122 { \ 123 "%badymm", "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", \ 124 "%ymm7" \ 125 } 126 127 #define ZMM_REG_NAMES \ 128 { \ 129 "%badzmm", "%zmm0", "%zmm1", "%zmm2", "%zmm3", "%zmm4", "%zmm5", "%zmm6", \ 130 "%zmm7" \ 131 } 132 133 #define MAX_N_XMM_REGS 8 134 #define XR_FIRST 1 135 #define XR_LAST 8 136 #define XR_NUM_REGS 8 /* only used in {hammer,llvm}/src/llvect.c */ 137 138 #define MAX_N_REGS (N_GP_REGS + MAX_N_XMM_REGS) 139 140 /*------------------------------------------------------------------ 141 * Assembly code representation of register names. These arrays are 142 * defined and initialised in cgassem.c and read in assem.c, 143 * cgassem.c, cggenai.c, exp_rte.c and xprolog.c. 144 *----------------------------------------------------------------*/ 145 146 #define IR_NUM_NAMES N_GP_REGS + 1 /* only used in dwarf2.c! */ 147 148 extern char *gp_reg[N_GP_REGS + 1]; /* GP_REG_NAMES */ 149 extern char *word_reg[N_GP_REGS + 1]; /* WORD_REG_NAMES */ 150 extern char *half_reg[N_GP_REGS + 1]; /* HALF_REG_NAMES */ 151 extern char *byte_reg[N_GP_REGS + 1]; /* BYTE_REG_NAMES */ 152 extern char *xm_reg[MAX_N_XMM_REGS + 1]; /* XMM_REG_NAMES */ 153 extern char *ym_reg[MAX_N_XMM_REGS + 1]; /* YMM_REG_NAMES */ 154 extern char *zm_reg[MAX_N_XMM_REGS + 1]; /* ZMM_REG_NAMES */ 155 156 #define RAX gp_reg[IR_EAX] 157 #define RBX gp_reg[IR_EBX] 158 #define RCX gp_reg[IR_ECX] 159 #define RDX gp_reg[IR_EDX] 160 #define RDI gp_reg[IR_EDI] 161 #define RSI gp_reg[IR_ESI] 162 #define RBP gp_reg[IR_EBP] 163 #define RSP gp_reg[IR_ESP] 164 165 #define EAX word_reg[IR_EAX] 166 #define EBX word_reg[IR_EBX] 167 #define ECX word_reg[IR_ECX] 168 #define EDX word_reg[IR_EDX] 169 #define EDI word_reg[IR_EDI] 170 #define ESI word_reg[IR_ESI] 171 #define EBP word_reg[IR_EBP] 172 #define ESP word_reg[IR_ESP] 173 174 /* bobt, july 03 ------------------ I did up to here ..... */ 175 176 #define FR_RETVAL XR_XMM0 177 #define SP_RETVAL XR_XMM0 178 #define DP_RETVAL XR_XMM0 179 #define CS_RETVAL XR_XMM0 180 #define CD_RETVAL XR_XMM0 181 182 #define IR_RETVAL IR_RAX 183 #define AR_RETVAL IR_RAX 184 #define MEMARG_OFFSET 8 185 186 #define MR_MAX_IREG_ARGS 0 187 #define MR_MAX_XREG_ARGS 8 188 /* not used to pass args */ 189 #define MR_MAX_FREG_ARGS 0 190 191 #define MR_MAX_IREG_RES 2 192 #define MR_MAX_XREG_RES 2 193 194 /* Use macros ARG_IR, ARG_XR, etc. 195 */ 196 extern int mr_arg_ir[MR_MAX_IREG_ARGS + 1]; /* defd in machreg.c */ 197 extern int mr_arg_xr[MR_MAX_XREG_ARGS + 1]; /* defd in machreg.c */ 198 extern int mr_res_ir[MR_MAX_IREG_RES + 1]; 199 extern int mr_res_xr[MR_MAX_XREG_RES + 1]; 200 201 #define ARG_IR(i) (scratch_regs[i]) /* initialized in machreg.c */ 202 #define ARG_XR(i) (mr_arg_xr[i]) 203 #define RES_IR(i) (mr_res_ir[i]) 204 #define RES_XR(i) (mr_res_xr[i]) 205 206 #define AR(i) IR_RETVAL /* used only for pgftn/386 */ 207 #define IR(i) ARG_IR(i) 208 #define SP(i) ARG_XR(i) 209 #define DP(i) ARG_XR(i) 210 #define ISP(i) (i + 100) /* not used? */ 211 #define IDP(i) (i + 100) 212 213 /* Macro for defining alternate-return register for fortran subprograms. 214 */ 215 #define IR_ARET IR_RETVAL 216 217 /* Macros for unpacking/packing KR registers. 218 */ 219 #define KR_LSH(i) (((i) >> 8) & 0xff) 220 #define KR_MSH(i) ((i)&0xff) 221 #define KR_PACK(ms, ls) (((ls) << 8) | (ms)) 222 223 /* Macro for defining the KR register in which the value of a 64-bit integer 224 * function is returned. 225 */ 226 #define KR_RETVAL KR_PACK(IR_EDX, IR_EAX) 227 228 /* Define MR_UNIQ, the number of unique register classes for the machine. 229 */ 230 #define MR_UNIQ 3 231 232 #define GR_THRESHOLD 2 233 234 /* Macros for defining the global registers in each of the unique register 235 * classes. For each global set, the lower and upper bounds are specified 236 * in the form MR_L<i> .. MR_U<i>, where i = 1 to MR_UNIQ. 237 */ 238 /***** i386 general purpose regs - allow 3 global *****/ 239 #define MR_L1 1 240 #define MR_U1 3 241 #define MR_MAX1 (MR_U1 - MR_L1 + 1) 242 243 /***** i387 floating-point regs - allow 3 global *****/ 244 #define MR_L2 2 245 #define MR_U2 4 246 #define MR_MAX2 (MR_U2 - MR_L2 + 1) 247 248 /***** i387 xmm floating-point regs - allow 3 global *****/ 249 #define MR_L3 2 250 #define MR_U3 4 251 #define MR_MAX3 (MR_U3 - MR_L3 + 1) 252 253 /* Total number of globals: used by the optimizer for register history 254 * tables. 255 */ 256 #define MR_NUMGLB (MR_MAX1 + MR_MAX2 + MR_MAX3) 257 258 /* Number of integer registers which are available for global 259 * assignment when calls are or are not present. 260 */ 261 #define MR_IR_AVAIL(c) 0 262 263 /* Define gindex bounds for the set of global irs/ars and scratch 264 * irs/ars. MUST BE CONSISTENT with mr_gindex(). 265 */ 266 #define MR_GI_IR_LOW 0 267 #define MR_GI_IR_HIGH (MR_U1 - MR_L1) 268 #define MR_GI_IS_SCR_IR(i) ((i) > (MR_U1 - MR_L1)) 269 270 /* Machine Register Information - 271 * 272 * This information is in two pieces: 273 * 1. a structure exists for each machine's register class which defines 274 * the attributes of registers. 275 * These attributes define a register set with the following properties: 276 * 1). a set is just an increasing set of numbers, 277 * 2). scratch registers are allocated in increasing order (towards 278 * the globals), 279 * 3). globals are allocated in decreasing order (towards the 280 * scratch registers). 281 * 4). the scratch set that can be changed by a procedure 282 * [min .. first_global-1] 283 * 5). the scratch set that can be changed by an intrinisic 284 * [min .. intrinsic] 285 * 286 * 2. a structure exists for all of the generic register classes which will 287 * map a register type (macros in registers.h) to the appropriate 288 * machine register class. 289 */ 290 291 /***** Machine Register Table *****/ 292 293 typedef struct { 294 char min; /* minimum register # */ 295 char max; /* maximum register # */ 296 char intrinsic; /* last scratch that can be changed by an intrinsic */ 297 const char first_global; /* first register # that can be global 298 * Note that the globals are allocated in increasing 299 * order (first_global down to last_global). 300 */ 301 const char end_global; /* absolute last register # that can be global. */ 302 /* the following two really define the working set 303 of registers that can be assigned. */ 304 char next_global; /* next global register # */ 305 char last_global; /* last register # that can be global. */ 306 char nused; /* number of global registers assigned */ 307 const char mapbase; /* offset in register bit vector where 308 this class of MACH_REGS begins. */ 309 const char Class; /* class or type of register. code generator needs 310 to know what kind of registers these represent. 311 'i' (integer), 'f' (float stk), 'x' (float xmm) */ 312 } MACH_REG; 313 314 /***** Register Mapping Table *****/ 315 316 typedef struct { 317 char max; /* maximum number of registers */ 318 char nused; /* number of registers assigned */ 319 char joined; /* non-zero value if registers are formed from 320 * multiple machine registers. 1==>next machine 321 * register is used; other values TBD. 322 */ 323 int rcand; /* register candidate list */ 324 MACH_REG *mach_reg; /* pointer to struct of the actual registers */ 325 INT const_flag; /* flag controlling assignment of consts */ 326 } REG; /* [rtype] */ 327 328 /***** Register Set Information for a block *****/ 329 330 typedef struct {/* three -word bit-vector */ 331 int xr; 332 } RGSET; 333 334 #define RGSETG(i) rgsetb.stg_base[i] 335 336 #define RGSET_XR(i) rgsetb.stg_base[i].xr 337 338 #define SET_RGSET_XR(i, reg) \ 339 { \ 340 RGSET_XR(i) |= (1 << (reg)); \ 341 } 342 343 #define TST_RGSET_XR(i, reg) ((RGSET_XR(i) >> (reg)) & 1) 344 345 typedef struct { 346 RGSET *stg_base; 347 int stg_avail; 348 int stg_size; 349 } RGSETB; 350 351 /***** External Data Declarations *****/ 352 353 extern REG reg[]; 354 extern RGSETB rgsetb; 355 356 /***** External Function Declarations *****/ 357 358 int mr_getnext(int rtype); 359 int mr_getreg(int rtype); 360 int mr_get_rgset(); 361 int mr_gindex(int rtype, int regno); 362 void mr_end(); 363 void mr_init(); 364 void mr_reset_frglobals(); 365 void mr_reset(int rtype); 366 void mr_reset_numglobals(int); 367 368 #endif 369