1 /* Subroutines used to generate function calls and handle built-in
2 instructions on IBM RS/6000.
3 Copyright (C) 1991-2021 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #define IN_TARGET_CODE 1
22
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "backend.h"
27 #include "rtl.h"
28 #include "tree.h"
29 #include "memmodel.h"
30 #include "gimple.h"
31 #include "cfghooks.h"
32 #include "cfgloop.h"
33 #include "df.h"
34 #include "tm_p.h"
35 #include "stringpool.h"
36 #include "expmed.h"
37 #include "optabs.h"
38 #include "regs.h"
39 #include "ira.h"
40 #include "recog.h"
41 #include "cgraph.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
44 #include "flags.h"
45 #include "alias.h"
46 #include "fold-const.h"
47 #include "attribs.h"
48 #include "stor-layout.h"
49 #include "calls.h"
50 #include "print-tree.h"
51 #include "varasm.h"
52 #include "explow.h"
53 #include "expr.h"
54 #include "output.h"
55 #include "common/common-target.h"
56 #include "langhooks.h"
57 #include "gimplify.h"
58 #include "gimple-fold.h"
59 #include "gimple-iterator.h"
60 #include "ssa.h"
61 #include "tree-ssa-propagate.h"
62 #include "builtins.h"
63 #include "tree-vector-builder.h"
64 #if TARGET_XCOFF
65 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
66 #endif
67 #include "ppc-auxv.h"
68 #include "targhooks.h"
69 #include "opts.h"
70
71 #include "rs6000-internal.h"
72
73 #if TARGET_MACHO
74 #include "gstab.h" /* for N_SLINE */
75 #include "dbxout.h" /* dbxout_ */
76 #endif
77
78 #ifndef TARGET_PROFILE_KERNEL
79 #define TARGET_PROFILE_KERNEL 0
80 #endif
81
82 #ifdef HAVE_AS_GNU_ATTRIBUTE
83 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
84 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
85 # endif
86 #endif
87
88 #ifndef TARGET_NO_PROTOTYPE
89 #define TARGET_NO_PROTOTYPE 0
90 #endif
91
92 struct builtin_compatibility
93 {
94 const enum rs6000_builtins code;
95 const char *const name;
96 };
97
98 struct builtin_description
99 {
100 const HOST_WIDE_INT mask;
101 const enum insn_code icode;
102 const char *const name;
103 const enum rs6000_builtins code;
104 };
105
106 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
107 static const struct
108 {
109 const char *cpu;
110 unsigned int cpuid;
111 } cpu_is_info[] = {
112 { "power10", PPC_PLATFORM_POWER10 },
113 { "power9", PPC_PLATFORM_POWER9 },
114 { "power8", PPC_PLATFORM_POWER8 },
115 { "power7", PPC_PLATFORM_POWER7 },
116 { "power6x", PPC_PLATFORM_POWER6X },
117 { "power6", PPC_PLATFORM_POWER6 },
118 { "power5+", PPC_PLATFORM_POWER5_PLUS },
119 { "power5", PPC_PLATFORM_POWER5 },
120 { "ppc970", PPC_PLATFORM_PPC970 },
121 { "power4", PPC_PLATFORM_POWER4 },
122 { "ppca2", PPC_PLATFORM_PPCA2 },
123 { "ppc476", PPC_PLATFORM_PPC476 },
124 { "ppc464", PPC_PLATFORM_PPC464 },
125 { "ppc440", PPC_PLATFORM_PPC440 },
126 { "ppc405", PPC_PLATFORM_PPC405 },
127 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
128 };
129
130 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
131 static const struct
132 {
133 const char *hwcap;
134 int mask;
135 unsigned int id;
136 } cpu_supports_info[] = {
137 /* AT_HWCAP masks. */
138 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
139 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
140 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
141 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
142 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
143 { "booke", PPC_FEATURE_BOOKE, 0 },
144 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
145 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
146 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
147 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
148 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
149 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
150 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
151 { "notb", PPC_FEATURE_NO_TB, 0 },
152 { "pa6t", PPC_FEATURE_PA6T, 0 },
153 { "power4", PPC_FEATURE_POWER4, 0 },
154 { "power5", PPC_FEATURE_POWER5, 0 },
155 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
156 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
157 { "ppc32", PPC_FEATURE_32, 0 },
158 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
159 { "ppc64", PPC_FEATURE_64, 0 },
160 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
161 { "smt", PPC_FEATURE_SMT, 0 },
162 { "spe", PPC_FEATURE_HAS_SPE, 0 },
163 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
164 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
165 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
166
167 /* AT_HWCAP2 masks. */
168 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
169 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
170 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
171 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
172 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
173 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
174 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
175 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
176 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
177 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
178 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
179 { "darn", PPC_FEATURE2_DARN, 1 },
180 { "scv", PPC_FEATURE2_SCV, 1 },
181 { "arch_3_1", PPC_FEATURE2_ARCH_3_1, 1 },
182 { "mma", PPC_FEATURE2_MMA, 1 },
183 };
184
185 static void altivec_init_builtins (void);
186 static tree builtin_function_type (machine_mode, machine_mode,
187 machine_mode, machine_mode,
188 enum rs6000_builtins, const char *name);
189 static void rs6000_common_init_builtins (void);
190 static void htm_init_builtins (void);
191 static void mma_init_builtins (void);
192
193
194 /* Hash table to keep track of the argument types for builtin functions. */
195
196 struct GTY((for_user)) builtin_hash_struct
197 {
198 tree type;
199 machine_mode mode[4]; /* return value + 3 arguments. */
200 unsigned char uns_p[4]; /* and whether the types are unsigned. */
201 };
202
203 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
204 {
205 static hashval_t hash (builtin_hash_struct *);
206 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
207 };
208
209 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
210
211 /* Hash function for builtin functions with up to 3 arguments and a return
212 type. */
213 hashval_t
hash(builtin_hash_struct * bh)214 builtin_hasher::hash (builtin_hash_struct *bh)
215 {
216 unsigned ret = 0;
217 int i;
218
219 for (i = 0; i < 4; i++)
220 {
221 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
222 ret = (ret * 2) + bh->uns_p[i];
223 }
224
225 return ret;
226 }
227
228 /* Compare builtin hash entries H1 and H2 for equivalence. */
229 bool
equal(builtin_hash_struct * p1,builtin_hash_struct * p2)230 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
231 {
232 return ((p1->mode[0] == p2->mode[0])
233 && (p1->mode[1] == p2->mode[1])
234 && (p1->mode[2] == p2->mode[2])
235 && (p1->mode[3] == p2->mode[3])
236 && (p1->uns_p[0] == p2->uns_p[0])
237 && (p1->uns_p[1] == p2->uns_p[1])
238 && (p1->uns_p[2] == p2->uns_p[2])
239 && (p1->uns_p[3] == p2->uns_p[3]));
240 }
241
242
243 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
244 #undef RS6000_BUILTIN_0
245 #undef RS6000_BUILTIN_1
246 #undef RS6000_BUILTIN_2
247 #undef RS6000_BUILTIN_3
248 #undef RS6000_BUILTIN_4
249 #undef RS6000_BUILTIN_A
250 #undef RS6000_BUILTIN_D
251 #undef RS6000_BUILTIN_H
252 #undef RS6000_BUILTIN_M
253 #undef RS6000_BUILTIN_P
254 #undef RS6000_BUILTIN_X
255
256 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
257 { NAME, ICODE, MASK, ATTR },
258
259 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
260 { NAME, ICODE, MASK, ATTR },
261
262 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
263 { NAME, ICODE, MASK, ATTR },
264
265 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
266 { NAME, ICODE, MASK, ATTR },
267
268 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) \
269 { NAME, ICODE, MASK, ATTR },
270
271 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
272 { NAME, ICODE, MASK, ATTR },
273
274 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
275 { NAME, ICODE, MASK, ATTR },
276
277 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
278 { NAME, ICODE, MASK, ATTR },
279
280 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) \
281 { NAME, ICODE, MASK, ATTR },
282
283 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
284 { NAME, ICODE, MASK, ATTR },
285
286 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
287 { NAME, ICODE, MASK, ATTR },
288
289 struct rs6000_builtin_info_type {
290 const char *name;
291 const enum insn_code icode;
292 const HOST_WIDE_INT mask;
293 const unsigned attr;
294 };
295
296 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
297 {
298 #include "rs6000-builtin.def"
299 };
300
301 #undef RS6000_BUILTIN_0
302 #undef RS6000_BUILTIN_1
303 #undef RS6000_BUILTIN_2
304 #undef RS6000_BUILTIN_3
305 #undef RS6000_BUILTIN_4
306 #undef RS6000_BUILTIN_A
307 #undef RS6000_BUILTIN_D
308 #undef RS6000_BUILTIN_H
309 #undef RS6000_BUILTIN_M
310 #undef RS6000_BUILTIN_P
311 #undef RS6000_BUILTIN_X
312
313 const struct altivec_builtin_types altivec_overloaded_builtins[] = {
314 /* Unary AltiVec/VSX builtins. */
315 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
316 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
317 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
318 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
319 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
320 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
321 { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
322 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
323 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
324 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
325 { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
326 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
327 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
328 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
329 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
330 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
331 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
332 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
333 { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
334 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
335 { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
336 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
337 { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
338 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
339 { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
340 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
341 { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
342 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
343 { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
344 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
345 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
346 RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
347 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
348 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
349 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
350 RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
351 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
352 RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
353 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
354 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
355 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
356 RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
357 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
358 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
359 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
360 RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
361 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
362 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
363 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
364 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
365 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
366 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
367 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
368 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
369 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
370 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
371 { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
372 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
373 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
374 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
375 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
376 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
377 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
378 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
379 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
380 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
381 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
382 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
383 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
384 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
385 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
386 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
387 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
388 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
389 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
390 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
391 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
392 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
393 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
394 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
395 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
396 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
397 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
398 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
399 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
400 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
401 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
402 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
403 { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF,
404 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
405 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
406 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
407 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
408 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
409 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
410 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
411 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
412 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
413 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
414 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
415 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
416 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
417 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
418 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
419 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
420 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
421 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
422 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
423 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
424 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
425 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
426 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
427 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
428 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
429 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
430 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
431 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
432 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
433 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
434 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
435 { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF,
436 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
437 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
438 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
439 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
440 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
441 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
442 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
443 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
444 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
445 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
446 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
447 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
448 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
449
450 /* Binary AltiVec/VSX builtins. */
451 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
452 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
453 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
454 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
455 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
456 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
457 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
458 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
459 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
460 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
461 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
462 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
463 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
464 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
465 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
466 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
467 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
468 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
469 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
470 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
471 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
472 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
473 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
474 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
475 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
476 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
477 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
478 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
479 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
480 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
481 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
482 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
483 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
484 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
485 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
486 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
487 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
488 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
489 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
490 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
491 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
492 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
493 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
494 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
495 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
496 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
497 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
498 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
499 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
500 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
501 { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
502 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
503 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
504 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
505 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
506 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
507 RS6000_BTI_unsigned_V1TI, 0 },
508 { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
509 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
510 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
511 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
512 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
513 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
514 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
515 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
516 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
517 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
518 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
519 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
520 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
521 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
522 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
523 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
524 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
525 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
526 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
527 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
528 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
529 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
530 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
531 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
532 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
533 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
534 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
535 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
536 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
537 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
538 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
539 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
540 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
541 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
542 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
543 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
544 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
545 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
546 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
547 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
548 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
549 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
550 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
551 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
552 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
553 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
554 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
555 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
556 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
557 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
558 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
559 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
560 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
561 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
562 RS6000_BTI_unsigned_V4SI, 0 },
563 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
564 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
565 RS6000_BTI_unsigned_V1TI, 0 },
566 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
567 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
568 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
569 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
570 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
571 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
572 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
573 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
574 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
575 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
576 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
577 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
578 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
579 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
580 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
581 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
582 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
583 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
584 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
585 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
586 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
587 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
588 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
589 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
590 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
591 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
592 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
593 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
594 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
595 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
596 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
597 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
598 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
599 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
600 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
601 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
602 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
603 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
604 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
605 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
606 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
607 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
608 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
609 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
610 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
611 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
612 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
613 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
614 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
615 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
616 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
617 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
618 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
619 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
620 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
621 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
622 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
623 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
624 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
625 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
626 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
627 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
628 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
629 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
630 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
631 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
632 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
633 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
634 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
635 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
636 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
637 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
638 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
639 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
640 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
641 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
642 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
643 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
644 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
645 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
646 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
647 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
648 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
649 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
650 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
651 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
652 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
653 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
654 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
655 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
656 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
657
658 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
659 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
660 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
661 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
662 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF,
663 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
664 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
665 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
666 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
667 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
668 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF,
669 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
670 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
671 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
672 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
673 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
674 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI,
675 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
676 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
677 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
678 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
679 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
680 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
681 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
682 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS,
683 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
684 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
685 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
686 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
687 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
688 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
689 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
690 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI,
691 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
692 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
693 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
694 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
695 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
696 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS,
697 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
698 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
699 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
700 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
701 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
702 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
703 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
704 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI,
705 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
706 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
707 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
708 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
709 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
710 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS,
711 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
712 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
713 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
714 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
715 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
716 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
717 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
718 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI,
719 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
720 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
721 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
722 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
723 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
724 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS,
725 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
726
727 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
728 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
729 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
730 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
731 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF,
732 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
733 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
734 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
735 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
736 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
737 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF,
738 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
739 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
740 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
741 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
742 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
743 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI,
744 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
745 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
746 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
747 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
748 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
749 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
750 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
751 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS,
752 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
753 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
754 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
755 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
756 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
757 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
758 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
759 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI,
760 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
761 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
762 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
763 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
764 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
765 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS,
766 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
767 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
768 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
769 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
770 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
771 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
772 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
773 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI,
774 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
775 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
776 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
777 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
778 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
779 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS,
780 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
781 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
782 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
783 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
784 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
785 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
786 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
787 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI,
788 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
789 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
790 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
791 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
792 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
793 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS,
794 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
795
796 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
797 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
798 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
799 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
800 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
801 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
802 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
803 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
804 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
805 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
806 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
807 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
808 { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
809 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
810 { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
811 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
812 { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
813 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
814 { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
815 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
816 { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
817 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
818 { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
819 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
820 { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
821 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
822 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
823 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
824 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
825 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
826 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
827 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
828 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
829 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
830 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
831 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
832 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
833 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
834 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
835 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
836 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
837 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
838 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
839 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
840 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
841 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
842 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
843 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
844 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
845 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
846 { ALTIVEC_BUILTIN_VEC_CMPEQ, P10V_BUILTIN_VCMPEQUT,
847 RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
848 { ALTIVEC_BUILTIN_VEC_CMPEQ, P10V_BUILTIN_VCMPEQUT,
849 RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
850 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
851 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
852 { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
853 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
854 { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
855 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
856
857 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
858 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
859 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
860 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
861
862 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
863 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
864 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
865 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
866
867 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
868 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
869 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
870 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
871
872 { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
873 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
874 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
875 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
876 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
877 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
878 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
879 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
880 RS6000_BTI_unsigned_V16QI, 0},
881 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
882 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
883 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
884 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
885 RS6000_BTI_unsigned_V8HI, 0},
886 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
887 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
888 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
889 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
890 RS6000_BTI_unsigned_V4SI, 0},
891 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
892 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
893 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
894 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
895 RS6000_BTI_unsigned_V2DI, 0},
896
897 { ALTIVEC_BUILTIN_VEC_CMPGE, P10V_BUILTIN_CMPGE_1TI,
898 RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0},
899 { ALTIVEC_BUILTIN_VEC_CMPGE, P10V_BUILTIN_CMPGE_U1TI,
900 RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI,
901 RS6000_BTI_unsigned_V1TI, 0},
902 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
903 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
904 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
905 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
906 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
907 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
908 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
909 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
910 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
911 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
912 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
913 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
914 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
915 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
916 { ALTIVEC_BUILTIN_VEC_CMPGT, P10V_BUILTIN_VCMPGTUT,
917 RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
918 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
919 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
920 { ALTIVEC_BUILTIN_VEC_CMPGT, P10V_BUILTIN_VCMPGTST,
921 RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
922 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
923 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
924 { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
925 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
926 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
927 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
928 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
929 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
930 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
931 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
932 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
933 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
934 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
935 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
936 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
937 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
938 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
939 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
940 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
941 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
942 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
943 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
944 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
945 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
946 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
947 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
948 RS6000_BTI_unsigned_V16QI, 0},
949 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
950 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
951 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
952 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
953 RS6000_BTI_unsigned_V8HI, 0},
954 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
955 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
956 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
957 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
958 RS6000_BTI_unsigned_V4SI, 0},
959 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
960 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
961 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
962 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
963 RS6000_BTI_unsigned_V2DI, 0},
964 { ALTIVEC_BUILTIN_VEC_CMPLE, P10V_BUILTIN_CMPLE_1TI,
965 RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0},
966 { ALTIVEC_BUILTIN_VEC_CMPLE, P10V_BUILTIN_CMPLE_U1TI,
967 RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI,
968 RS6000_BTI_unsigned_V1TI, 0},
969 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
970 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
971 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
972 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
973 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
974 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
975 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
976 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
977 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
978 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
979 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
980 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
981 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
982 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
983 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
984 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
985 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
986 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
987 { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
988 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
989 { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
990 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
991 { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
992 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
993 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
994 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
995 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
996 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
997 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
998 RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
999 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
1000 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
1001 { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
1002 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1003 { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
1004 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1005 { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
1006 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1007 { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
1008 RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1009 { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
1010 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1011 { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
1012 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1013
1014 { P8V_BUILTIN_VEC_BCDADD, MISC_BUILTIN_BCDADD_V1TI,
1015 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1016 { P8V_BUILTIN_VEC_BCDADD, MISC_BUILTIN_BCDADD_V16QI,
1017 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
1018 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1019 { P8V_BUILTIN_VEC_BCDADD_LT, MISC_BUILTIN_BCDADD_LT_V1TI,
1020 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1021 { P8V_BUILTIN_VEC_BCDADD_LT, MISC_BUILTIN_BCDADD_LT_V16QI,
1022 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1023 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1024 { P8V_BUILTIN_VEC_BCDADD_EQ, MISC_BUILTIN_BCDADD_EQ_V1TI,
1025 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1026 { P8V_BUILTIN_VEC_BCDADD_EQ, MISC_BUILTIN_BCDADD_EQ_V16QI,
1027 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1028 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1029 { P8V_BUILTIN_VEC_BCDADD_GT, MISC_BUILTIN_BCDADD_GT_V1TI,
1030 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1031 { P8V_BUILTIN_VEC_BCDADD_GT, MISC_BUILTIN_BCDADD_GT_V16QI,
1032 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1033 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1034 { P8V_BUILTIN_VEC_BCDADD_OV, MISC_BUILTIN_BCDADD_OV_V1TI,
1035 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1036 { P8V_BUILTIN_VEC_BCDADD_OV, MISC_BUILTIN_BCDADD_OV_V16QI,
1037 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1038 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1039 { P8V_BUILTIN_VEC_BCDINVALID, MISC_BUILTIN_BCDINVALID_V1TI,
1040 RS6000_BTI_INTSI, RS6000_BTI_V1TI, 0, 0 },
1041 { P8V_BUILTIN_VEC_BCDINVALID, MISC_BUILTIN_BCDINVALID_V16QI,
1042 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
1043
1044 { P9V_BUILTIN_VEC_BCDMUL10, P9V_BUILTIN_BCDMUL10_V16QI,
1045 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
1046 { P9V_BUILTIN_VEC_BCDDIV10, P9V_BUILTIN_BCDDIV10_V16QI,
1047 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
1048
1049 { P8V_BUILTIN_VEC_DENBCD, MISC_BUILTIN_DENBCD_V16QI,
1050 RS6000_BTI_dfloat128, RS6000_BTI_unsigned_V16QI, 0, 0 },
1051
1052 { P8V_BUILTIN_VEC_BCDSUB, MISC_BUILTIN_BCDSUB_V1TI,
1053 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1054 { P8V_BUILTIN_VEC_BCDSUB, MISC_BUILTIN_BCDSUB_V16QI,
1055 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
1056 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1057 { P8V_BUILTIN_VEC_BCDSUB_LT, MISC_BUILTIN_BCDSUB_LT_V1TI,
1058 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1059 { P8V_BUILTIN_VEC_BCDSUB_LT, MISC_BUILTIN_BCDSUB_LT_V16QI,
1060 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1061 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1062 { P8V_BUILTIN_VEC_BCDSUB_LE, MISC_BUILTIN_BCDSUB_LE_V1TI,
1063 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1064 { P8V_BUILTIN_VEC_BCDSUB_LE, MISC_BUILTIN_BCDSUB_LE_V16QI,
1065 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1066 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1067 { P8V_BUILTIN_VEC_BCDSUB_EQ, MISC_BUILTIN_BCDSUB_EQ_V1TI,
1068 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1069 { P8V_BUILTIN_VEC_BCDSUB_EQ, MISC_BUILTIN_BCDSUB_EQ_V16QI,
1070 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1071 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1072 { P8V_BUILTIN_VEC_BCDSUB_GT, MISC_BUILTIN_BCDSUB_GT_V1TI,
1073 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1074 { P8V_BUILTIN_VEC_BCDSUB_GT, MISC_BUILTIN_BCDSUB_GT_V16QI,
1075 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1076 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1077 { P8V_BUILTIN_VEC_BCDSUB_GE, MISC_BUILTIN_BCDSUB_GE_V1TI,
1078 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1079 { P8V_BUILTIN_VEC_BCDSUB_GE, MISC_BUILTIN_BCDSUB_GE_V16QI,
1080 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1081 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1082 { P8V_BUILTIN_VEC_BCDSUB_OV, MISC_BUILTIN_BCDSUB_OV_V1TI,
1083 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI },
1084 { P8V_BUILTIN_VEC_BCDSUB_OV, MISC_BUILTIN_BCDSUB_OV_V16QI,
1085 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
1086 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
1087
1088
1089 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
1090 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1091 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
1092 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1093 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
1094 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1095 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
1096 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1097
1098 { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVS_V4SI,
1099 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1100 { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVU_V4SI,
1101 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1102 RS6000_BTI_unsigned_V4SI, 0 },
1103 { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVS_V2DI,
1104 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1105 { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVU_V2DI,
1106 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
1107 RS6000_BTI_unsigned_V2DI, 0 },
1108 { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIV_V1TI,
1109 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1110 { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_UDIV_V1TI,
1111 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1112 RS6000_BTI_unsigned_V1TI, 0 },
1113
1114 { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVES_V4SI,
1115 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1116 { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVEU_V4SI,
1117 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1118 RS6000_BTI_unsigned_V4SI, 0 },
1119 { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVES_V2DI,
1120 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1121 { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVEU_V2DI,
1122 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
1123 RS6000_BTI_unsigned_V2DI, 0 },
1124 { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVES_V1TI,
1125 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1126 { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVEU_V1TI,
1127 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1128 RS6000_BTI_unsigned_V1TI, 0 },
1129
1130 { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODS_V4SI,
1131 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1132 { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODU_V4SI,
1133 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1134 RS6000_BTI_unsigned_V4SI, 0 },
1135 { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODS_V2DI,
1136 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1137 { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODU_V2DI,
1138 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
1139 RS6000_BTI_unsigned_V2DI, 0 },
1140 { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODS_V1TI,
1141 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1142 { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODU_V1TI,
1143 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1144 RS6000_BTI_unsigned_V1TI, 0 },
1145
1146 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
1147 RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
1148 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
1149 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1150
1151 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI,
1152 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1153 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI,
1154 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1155 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF,
1156 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1157
1158 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI,
1159 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1160 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI,
1161 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1162 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF,
1163 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1164
1165 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI,
1166 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1167 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI,
1168 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1169 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF,
1170 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1171
1172 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI,
1173 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1174 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI,
1175 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1176 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF,
1177 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1178
1179 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF,
1180 RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
1181 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
1182 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1183 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF,
1184 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1185 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI,
1186 RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1187 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI,
1188 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI,
1189 RS6000_BTI_unsigned_V2DI, 0 },
1190 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF,
1191 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1192 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI,
1193 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1194 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI,
1195 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1196 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF,
1197 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1198 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI,
1199 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1200 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
1201 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1202
1203 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1204 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
1205 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1206 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 },
1207 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1208 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
1209 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI,
1210 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
1211
1212 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1213 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1214 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1215 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1216 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1217 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1218 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1219 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1220 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1221 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1222 ~RS6000_BTI_unsigned_V2DI, 0 },
1223 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1224 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1225 ~RS6000_BTI_unsigned_long_long, 0 },
1226 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1227 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1228 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1229 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1230 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1231 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1232 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1233 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1234 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1235 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1236 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1237 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1238 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1239 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1240 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1241 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1242 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1243 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1244 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1245 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1246 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1247 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1248 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1249 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1250 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1251 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1252 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1253 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1254 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1255 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1256 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1257 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1258 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1259 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1260 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1261 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1262 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1263 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1264 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1265 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1266 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1267 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1268 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1269 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1270 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1271 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1272 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1273 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1274 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1275 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1276 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1277 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1278 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1279 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1280 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1281 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1282 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1283 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1284 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1285 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1286 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1287 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1288 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1289 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1290 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1291 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1292 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1293 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1294 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1295 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1296 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1297 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1298 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1299 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1300 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1301 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1302 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1303 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1304
1305 /* vector signed__int128 vec_xl_sext (signed long long, signed char *);
1306 vector signed__int128 vec_xl_sext (signed long long, signed short *);
1307 vector signed__int128 vec_xl_sext (signed long long, signed int *);
1308 vector signed__int128 vec_xl_sext (signed long long, signed longlong *); */
1309 { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRBX,
1310 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1311 { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRHX,
1312 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1313 { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRWX,
1314 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1315 { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRDX,
1316 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1317 { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRDX,
1318 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1319
1320 /* vector unsigned__int128 vec_xl_zext (signed long long, unsigned char *);
1321 vector unsigned__int128 vec_xl_zext (signed long long, unsigned short *);
1322 vector unsigned__int128 vec_xl_zext (signed long long, unsigned int *);
1323 vector unsigned__int128 vec_xl_zext (signed long long, unsigned longlong *); */
1324 { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRBX,
1325 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1326 { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRHX,
1327 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1328 { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRWX,
1329 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1330 { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRDX,
1331 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1332 { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRDX,
1333 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
1334
1335 /* void vec_xst_trunc (vector signed __int128, signed long long, signed char *);
1336 void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *);
1337 void vec_xst_trunc (vector signed __int128, signed long long, signed char *);
1338 void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *);
1339 void vec_xst_trunc (vector signed __int128, signed long long, signed char *);
1340 void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *);
1341 void vec_xst_trunc (vector signed __int128, signed long long, signed char *);
1342 void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *); */
1343 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRBX, RS6000_BTI_void,
1344 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
1345 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRBX, RS6000_BTI_void,
1346 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
1347 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRHX, RS6000_BTI_void,
1348 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
1349 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRHX, RS6000_BTI_void,
1350 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
1351 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRWX, RS6000_BTI_void,
1352 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
1353 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRWX, RS6000_BTI_void,
1354 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
1355 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void,
1356 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
1357 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void,
1358 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long },
1359 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void,
1360 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI },
1361 { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void,
1362 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI },
1363
1364 /* vector float vec_ldl (int, vector float *);
1365 vector float vec_ldl (int, float *); */
1366 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1367 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1368 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1369 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1370
1371 /* vector bool int vec_ldl (int, vector bool int *);
1372 vector bool int vec_ldl (int, bool int *);
1373 vector int vec_ldl (int, vector int *);
1374 vector int vec_ldl (int, int *);
1375 vector unsigned int vec_ldl (int, vector unsigned int *);
1376 vector unsigned int vec_ldl (int, unsigned int *); */
1377 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1378 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1379 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1380 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 },
1381 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1382 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1383 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1384 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1385 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1386 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1387 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1388 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1389
1390 /* vector bool short vec_ldl (int, vector bool short *);
1391 vector bool short vec_ldl (int, bool short *);
1392 vector pixel vec_ldl (int, vector pixel *);
1393 vector short vec_ldl (int, vector short *);
1394 vector short vec_ldl (int, short *);
1395 vector unsigned short vec_ldl (int, vector unsigned short *);
1396 vector unsigned short vec_ldl (int, unsigned short *); */
1397 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1398 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1399 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1400 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 },
1401 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1402 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1403 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1404 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1405 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1406 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1407 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1408 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1409 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1410 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1411
1412 /* vector bool char vec_ldl (int, vector bool char *);
1413 vector bool char vec_ldl (int, bool char *);
1414 vector char vec_ldl (int, vector char *);
1415 vector char vec_ldl (int, char *);
1416 vector unsigned char vec_ldl (int, vector unsigned char *);
1417 vector unsigned char vec_ldl (int, unsigned char *); */
1418 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1419 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1420 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1421 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 },
1422 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1423 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1424 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1425 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1426 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1427 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1428 ~RS6000_BTI_unsigned_V16QI, 0 },
1429 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1430 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1431
1432 /* vector double vec_ldl (int, vector double *);
1433 vector double vec_ldl (int, double *); */
1434 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1435 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1436 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1437 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1438
1439 /* vector long long vec_ldl (int, vector long long *);
1440 vector long long vec_ldl (int, long long *);
1441 vector unsigned long long vec_ldl (int, vector unsigned long long *);
1442 vector unsigned long long vec_ldl (int, unsigned long long *);
1443 vector bool long long vec_ldl (int, vector bool long long *);
1444 vector bool long long vec_ldl (int, bool long long *); */
1445 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1446 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1447 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1448 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1449 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1450 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1451 ~RS6000_BTI_unsigned_V2DI, 0 },
1452 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1453 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1454 ~RS6000_BTI_unsigned_long_long, 0 },
1455 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1456 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1457 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1458 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 },
1459
1460 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1461 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1462 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1463 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1464 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1465 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1466 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1467 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1468 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1469 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1470 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1471 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1472 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1473 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1474 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1475 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1476 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1477 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1478 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1479 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1480 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1481 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1482 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1483 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1484 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1485 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1486 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1487 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1488 ~RS6000_BTI_unsigned_long_long, 0 },
1489 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1490 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1491 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1492 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1493 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1494 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1495 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1496 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1497 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1498 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1499 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1500 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1501 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1502 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1503 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1504 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1505 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1506 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1507 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1508 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1509 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1510 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1511 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1512 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1513 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1514 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1515 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1516 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1517 ~RS6000_BTI_unsigned_long_long, 0 },
1518 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1519 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1520 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1521 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1522 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1523 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1524 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1525 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1526 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1527 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1528 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1529 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1530 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1531 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1532 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1533 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1534 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1535 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1536 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1537 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1538 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1539 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1540 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1541 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1542 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1543 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1544 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1545 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1546 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1547 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1548 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1549 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1550 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1551 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1552 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1553 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1554 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1555 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1556 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1557 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1558 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1559 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1560 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1561 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1562 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1563 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1564 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1565 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1566 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1567 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1568 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1569 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1570 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1571 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1572 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1573 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1574 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1575 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1576 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1577 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1578 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1579 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1580 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1581 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1582 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1583 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1584 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1585 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1586 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1587 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1588 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1589 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1590 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1591 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1592 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1593 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1594 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1595 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1596 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1597 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1598 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1599 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1600 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1601 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1602 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1603 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1604 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1605 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1606 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1607 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1608 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1609 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1610 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1611 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1612 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1613 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1614 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1615 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1616 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1617 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1618 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1619 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1620 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1621 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1622 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1623 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1624 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1625 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1626 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1627 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1628 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1629 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1630 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1631 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1632 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1633 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1634 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1635 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1636 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1637 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1638 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1639 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1640 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1641 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1642 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1643 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1644 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1645 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1646 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1647 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1648 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1649 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1650 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1651 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1652 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1653 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1654 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1655 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1656 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1657 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1658 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1659 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1660 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1661 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1662 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1663 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1664 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1665 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1666 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1667 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1668 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1669 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1670 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1671 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1672 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1673 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1674 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1675 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1676 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1677 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1678 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1679 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1680 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1681 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1682 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1683 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1684 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1685 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1686 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1687 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1688 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1689 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1690 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1691 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1692 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1693 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1694 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1695 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1696 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1697 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1698 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1699 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1700 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1701 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1702 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1703 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1704 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1705 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1706 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1707 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1708 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1709 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1710 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
1711 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1712 { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
1713 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1714 { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
1715 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1716 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1717 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1718 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1719 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1720 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1721 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1722 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1723 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1724 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1725 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1726 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1727 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1728 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1729 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1730 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1731 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1732 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1733 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1734 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1735 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1736 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1737 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1738 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1739 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1740 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1741 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1742 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1743 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1744 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1745 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1746 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1747 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1748 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1749 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1750 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1751 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1752 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1753 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1754 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1755 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1756 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1757 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1758 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1759 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1760 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1761 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1762 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1763 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1764 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1765 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1766 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1767 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1768 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1769 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1770 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1771 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1772 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1773 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1774 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1775 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1776 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1777 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1778 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1779 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1780 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1781 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1782 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1783 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1784 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1785 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1786 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
1787 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1788 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1789 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1790 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1791 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1792 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1793 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1794 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1795 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1796 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1797 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1798 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1799 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1800 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1801 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1802 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1803 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1804 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1805 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1806 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1807 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1808 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1809 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1810 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1811 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1812 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1813 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1814 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1815 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1816 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1817 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1818 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1819 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1820 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1821 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1822 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1823 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1824 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1825 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1826 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1827 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1828 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1829 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1830 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1831 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1832 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1833 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1834 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1835 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1836 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1837 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1838 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1839 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1840 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1841 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1842 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1843 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1844 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
1845 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1846 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
1847 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1848 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1849 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1850 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1851 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1852 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1853 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1854 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1855 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1856 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1857 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1858 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1859 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1860 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
1861 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1862 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1863 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1864 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1865 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1866 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1867 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1868 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
1869 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1870 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1871 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1872 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1873 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1874 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1875 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1876 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
1877 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1878 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1879 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1880 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1881 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1882 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
1883 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1884 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1885 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1886 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1887 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1888 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
1889 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1890 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1891 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1892 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1893 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1894 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
1895 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1896 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1897 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1898 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1899 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1900 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
1901 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1902 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1903 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1904 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1905 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1906 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
1907 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1908 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1909 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1910 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1911 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1912 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
1913 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1914 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1915 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1916 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1917 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1918 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
1919 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1920 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1921 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1922 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1923 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1924 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
1925 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1926 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1927 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1928 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1929 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1930 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
1931 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1932 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
1933 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1934 { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
1935 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1936 { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
1937 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1938 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1939 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1940 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1941 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1942 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
1943 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1944 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1945 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1946 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1947 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1948 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1949 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1950 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1951 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1952 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
1953 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1954 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1955 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1956 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1957 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1958 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
1959 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1960 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1961 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1962 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1963 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1964 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
1965 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1966 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1967 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1968 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1969 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1970 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1971 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1972 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1973 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1974 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
1975 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1976 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1977 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1978 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1979 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1980 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1981 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1982 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1983 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1984 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
1985 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1986 { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHS_V4SI,
1987 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1988 { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHU_V4SI,
1989 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1990 RS6000_BTI_unsigned_V4SI, 0 },
1991 { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHS_V2DI,
1992 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1993 { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHU_V2DI,
1994 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
1995 RS6000_BTI_unsigned_V2DI, 0 },
1996
1997 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
1998 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1999 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
2000 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2001 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
2002 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2003 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2004 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2005 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW,
2006 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2007 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
2008 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2009 RS6000_BTI_unsigned_V4SI, 0 },
2010 { ALTIVEC_BUILTIN_VEC_MULE, P10V_BUILTIN_VMULESD,
2011 RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2012 { ALTIVEC_BUILTIN_VEC_MULE, P10V_BUILTIN_VMULEUD,
2013 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
2014 RS6000_BTI_unsigned_V2DI, 0 },
2015 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
2016 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2017 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
2018 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2019 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
2020 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2021 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
2022 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2023 { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW,
2024 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2025 { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW,
2026 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2027 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
2028 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2029 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
2030 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2031 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
2032 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2033 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW,
2034 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2035 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW,
2036 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2037 RS6000_BTI_unsigned_V4SI, 0 },
2038 { ALTIVEC_BUILTIN_VEC_MULO, P10V_BUILTIN_VMULOSD,
2039 RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2040 { ALTIVEC_BUILTIN_VEC_MULO, P10V_BUILTIN_VMULOUD,
2041 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
2042 RS6000_BTI_unsigned_V2DI, 0 },
2043 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2044 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2045 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
2046 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2047 { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
2048 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2049 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
2050 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2051 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
2052 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2053 { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW,
2054 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2055 { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW,
2056 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2057
2058 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
2059 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2060 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
2061 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2062 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
2063 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2064 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
2065 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2066 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
2067 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2068 { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
2069 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2070 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
2071 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2072 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
2073 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2074
2075 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SF,
2076 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2077 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DF,
2078 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2079 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
2080 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2081 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
2082 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2083 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI,
2084 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2085 { ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI,
2086 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_bool_V1TI, 0 },
2087 { ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI,
2088 RS6000_BTI_V1TI, RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, 0 },
2089 { ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI_UNS,
2090 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
2091 { ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI_UNS,
2092 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_bool_V1TI, 0 },
2093 { ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI_UNS,
2094 RS6000_BTI_unsigned_V1TI, RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
2095 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
2096 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2097 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
2098 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2099 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
2100 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2101 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS,
2102 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2103 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI,
2104 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2105 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
2106 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2107 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS,
2108 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2109 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI,
2110 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2111 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS,
2112 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2113 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS,
2114 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2115 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI,
2116 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2117 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
2118 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2119 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS,
2120 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2121
2122 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
2123 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2124 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
2125 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
2126 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF,
2127 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
2128 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
2129 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2130 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
2131 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
2132 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF,
2133 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
2134 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
2135 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2136 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
2137 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2138 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI,
2139 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2140 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
2141 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2142 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
2143 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2144 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
2145 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2146 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS,
2147 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2148 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
2149 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2150 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
2151 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2152 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
2153 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2154 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI,
2155 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2156 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
2157 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2158 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
2159 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2160 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS,
2161 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2162 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
2163 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2164 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
2165 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2166 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
2167 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2168 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI,
2169 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2170 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
2171 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2172 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
2173 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2174 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS,
2175 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2176 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
2177 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2178 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
2179 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2180 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
2181 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2182 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI,
2183 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2184 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
2185 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2186 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
2187 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2188 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS,
2189 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2190
2191 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2192 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2193 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2194 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2195 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2196 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2197 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2198 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2199 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2200 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2201 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2202 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2203 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2204 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2205 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2206 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2207 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2208 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2209 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF,
2210 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2211
2212 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI,
2213 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2214 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI,
2215 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2216 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI,
2217 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2218 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI,
2219 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2220 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF,
2221 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2222 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF,
2223 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2224
2225 { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
2226 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2227 { P9V_BUILTIN_VEC_CONVERT_4F32_8F16, P9V_BUILTIN_CONVERT_4F32_8F16,
2228 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2229
2230 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2231 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2232 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
2233 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2234 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2235 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2236 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI,
2237 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2238 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2239 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2240 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI,
2241 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2242 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2243 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2244 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI,
2245 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2246 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2247 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2248 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI,
2249 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2250 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2251 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2252 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI,
2253 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2254 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2255 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2256 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI,
2257 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2258 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2259 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2260 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI,
2261 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2262 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2263 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2264 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI,
2265 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2266
2267 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2268 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI,
2269 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2270 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2271 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI,
2272 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2273 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2274 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2275 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2276 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2277 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI,
2278 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2279 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2280 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2281 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2282 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX,
2283 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI,
2284 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2285
2286 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2287 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2288 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2289 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2290 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2291 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2292 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2293 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2294 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2295 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2296 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2297 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2298 { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2299 RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2300 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2301 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2302 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2303 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2304 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2305 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2306 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2307 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2308 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2309 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2310 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2311 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2312 { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2313 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2314 { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2315 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2316 { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2317 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2318 { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2319 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2320 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2321 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2322 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2323 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2324 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2325 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2326 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2327 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2328 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2329 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2330 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKUDUS,
2331 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2332 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2333 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2334 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2335 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2336 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2337 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2338 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2339 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2340 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2341 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2342 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2343 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2344 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2345 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2346 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2347 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2348 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2349 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2350 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2351 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2352 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2353 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2354 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2355 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2356 { ALTIVEC_BUILTIN_VEC_RL, P10V_BUILTIN_VRLQ,
2357 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
2358 { ALTIVEC_BUILTIN_VEC_RL, P10V_BUILTIN_VRLQ,
2359 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2360 RS6000_BTI_unsigned_V1TI, 0 },
2361 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2362 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2363 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2364 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2365 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2366 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2367 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2368 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2369 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2370 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2371 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2372 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2373 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2374 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2375 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2376 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2377 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2378 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2379 { P9V_BUILTIN_VEC_RLMI, P10V_BUILTIN_VRLQMI,
2380 RS6000_BTI_V1TI, RS6000_BTI_V1TI,
2381 RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI },
2382 { P9V_BUILTIN_VEC_RLMI, P10V_BUILTIN_VRLQMI,
2383 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2384 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
2385 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2386 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2387 RS6000_BTI_unsigned_V4SI, 0 },
2388 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2389 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2390 RS6000_BTI_unsigned_V2DI, 0 },
2391 { P9V_BUILTIN_VEC_RLNM, P10V_BUILTIN_VRLQNM,
2392 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2393 RS6000_BTI_unsigned_V1TI, 0 },
2394 { P9V_BUILTIN_VEC_RLNM, P10V_BUILTIN_VRLQNM,
2395 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
2396 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2397 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2398 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2399 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2400 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2401 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2402 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2403 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2404 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2405 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2406 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2407 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2408 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2409 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2410 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2411 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2412 { ALTIVEC_BUILTIN_VEC_SL, P10V_BUILTIN_VSLQ,
2413 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
2414 { ALTIVEC_BUILTIN_VEC_SL, P10V_BUILTIN_VSLQ,
2415 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2416 RS6000_BTI_unsigned_V1TI, 0 },
2417 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2418 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2419 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2420 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2421 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2422 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2423 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2424 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2425 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2426 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2427 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2428 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2429 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2430 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2431 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2432 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2433 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2434 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2435 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2436 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2437 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2438 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2439 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2440 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2441 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2442 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2443 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2444 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2445 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2446 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2447 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2448 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2449 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2450 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2451 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2452 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2453 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2454 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2455 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2456 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2457 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2458 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2459 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2460 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2461 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2462 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2463 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2464 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2465 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2466 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2467 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2468 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2469 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2470 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2471 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2472 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2473 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2474 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2475 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2476 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2477 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2478 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2479 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2480 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2481 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2482 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2483 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2484 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2485 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2486 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2487 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2488 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2489 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2490 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2491 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2492 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2493
2494 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2495 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2496 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2497 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2498 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2499 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2500 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2501 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2502 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2503 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 },
2504
2505 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2506 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2507 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2508 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2509 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2510 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2511 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2512 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2513 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2514 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2515 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2516 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2517 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2518 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2519 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2520 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2521 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2522 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2523 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2524 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2525 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2526 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2527 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2528 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2529 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2530 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2531 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2532 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2533 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2534 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2535 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2536 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2537 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2538 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2539 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2540 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2541 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2542 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2543 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2544 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2545 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2546 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2547 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2548 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2549 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2550 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2551 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2552 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2553 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2554 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2555 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2556 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2557 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2558 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2559 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2560 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2561 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2562 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2563 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2564 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2565 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2566 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2567 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2568 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2569 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2570 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2571 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2572 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2573 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2574 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
2575 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2576 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2577 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2578 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2579 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2580 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2581 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2582 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2583 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2584 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2585 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2586 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2587 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2588 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2589 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2590 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2591 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2592 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2593 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2594 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2595 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2596 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2597 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2598 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2599 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2600 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2601 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2602 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2603 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2604 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2605 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2606 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2607 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2608 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2609 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2610 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2611 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2612 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2613 { ALTIVEC_BUILTIN_VEC_SR, P10V_BUILTIN_VSRQ,
2614 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
2615 { ALTIVEC_BUILTIN_VEC_SR, P10V_BUILTIN_VSRQ,
2616 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2617 RS6000_BTI_unsigned_V1TI, 0 },
2618 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2619 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2620 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2621 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2622 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2623 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2624 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2625 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2626 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2627 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2628 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2629 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2630 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2631 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2632 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2633 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2634 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2635 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2636 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2637 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2638 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2639 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2640 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2641 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2642 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2643 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2644 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2645 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2646 { ALTIVEC_BUILTIN_VEC_SRA, P10V_BUILTIN_VSRAQ,
2647 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
2648 { ALTIVEC_BUILTIN_VEC_SRA, P10V_BUILTIN_VSRAQ,
2649 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2650 RS6000_BTI_unsigned_V1TI, 0 },
2651 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2652 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2653 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2654 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2655 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2656 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2657 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2658 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2659 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2660 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2661 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2662 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2663 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2664 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2665 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2666 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2667 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2668 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2669 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2670 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2671 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2672 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2673 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2674 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2675 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2676 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2677 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2678 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2679 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2680 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2681 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2682 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2683 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2684 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2685 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2686 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2687 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2688 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2689 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2690 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2691 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2692 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2693 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2694 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2695 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2696 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2697 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2698 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2699 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2700 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2701 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2702 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2703 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2704 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2705 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2706 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2707 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2708 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2709 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2710 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2711 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2712 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2713 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2714 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2715 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2716 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2717 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2718 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2719 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2720 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2721 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2722 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2723 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2724 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2725 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2726 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2727 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2728 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2729 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2730 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2731 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2732 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2733 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2734 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2735 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2736 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2737 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2738 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2739 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2740 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2741 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2742 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2743 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2744 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2745 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2746 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2747 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2748 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2749 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2750 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2751 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2752 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2753 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2754 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2755 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2756 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2757 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2758 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2759 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2760 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2761 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2762 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2763 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2764 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2765 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2766 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2767
2768 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2769 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2770 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2771 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2772 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2773 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2774 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2775 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2776 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2777 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2778 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2779 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2780 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2781 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2782 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2783 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2784 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2785 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2786 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2787 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2788 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2789 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2790 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2791 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2792 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2793 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2794 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2795 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2796 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2797 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2798 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2799 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2800 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2801 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2802 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2803 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2804 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2805 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2806 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2807 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2808 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2809 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2810 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2811 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2812 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2813 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2814 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2815 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2816 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
2817 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2818 { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
2819 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2820 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2821 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2822 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2823 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2824 RS6000_BTI_unsigned_V1TI, 0 },
2825 { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
2826 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2827 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2828 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2829 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2830 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2831 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2832 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2833 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2834 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2835 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2836 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2837 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2838 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2839 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2840 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2841 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2842 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2843 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2844 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2845 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2846 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2847 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2848 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2849 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2850 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2851 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2852 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2853 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2854 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2855 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2856 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2857 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2858 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2859 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2860 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2861 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2862 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2863 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2864 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2865 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2866 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2867 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2868 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2869 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2870 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2871 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2872 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2873 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2874 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2875
2876 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2877 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2878 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2879 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2880 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2881 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2882 RS6000_BTI_unsigned_V1TI, 0 },
2883 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2884 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2885
2886 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2887 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2888 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2889 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2890 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2891 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2892 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2893 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2894 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2895 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2896 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2897 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2898 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2899 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2900 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2901 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2902 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2903 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2904 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2905 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2906 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2907 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2908 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2909 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2910 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2911 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2912 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2913 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2914 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2915 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2916 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2917 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2918 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2919 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2920 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2921 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2922 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2923 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2924 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2925 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2926 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2927 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2928 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2929 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2930 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2931 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2932 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2933 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2934 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2935 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2936 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2937 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2938 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2939 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2940 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2941 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2942 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2943 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2944 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2945 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2946 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2947 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2948 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2949 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2950 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2951 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2952 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2953 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2954 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2955 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2956 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2957 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2958 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2959 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2960 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2961 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2962 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2963 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2964 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2965 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2966 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2967 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2968 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2969 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2970 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
2971 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2972 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
2973 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2974 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
2975 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
2976 { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
2977 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
2978 { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
2979 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2980 { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
2981 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2982 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
2983 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2984 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
2985 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2986
2987 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
2988 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
2989 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF,
2990 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
2991 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2992 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
2993 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2994 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 },
2995 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI,
2996 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
2997 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
2998 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
2999 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3000 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3001 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3002 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
3003 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3004 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3005 ~RS6000_BTI_unsigned_V2DI, 0 },
3006 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3007 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3008 ~RS6000_BTI_unsigned_long_long, 0 },
3009 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI,
3010 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
3011
3012 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
3013 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3014 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF,
3015 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3016 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3017 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3018 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3019 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3020 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3021 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3022 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI,
3023 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3024 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3025 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3026 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3027 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3028 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3029 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3030 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI,
3031 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3032 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3033 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3034 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3035 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3036 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3037 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3038 ~RS6000_BTI_unsigned_V16QI, 0 },
3039 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI,
3040 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3041
3042 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
3043 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3044 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF,
3045 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3046 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
3047 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
3048 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI,
3049 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
3050 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3051 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3052 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3053 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3054 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3055 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3056 ~RS6000_BTI_unsigned_V2DI, 0 },
3057 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI,
3058 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3059 ~RS6000_BTI_unsigned_long_long, 0 },
3060 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
3061 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3062 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF,
3063 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3064 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3065 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3066 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3067 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3068 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3069 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3070 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI,
3071 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3072 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3073 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3074 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3075 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3076 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3077 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3078 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI,
3079 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3080 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3081 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3082 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3083 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3084 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3085 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3086 ~RS6000_BTI_unsigned_V16QI, 0 },
3087 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI,
3088 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3089
3090 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF,
3091 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3092 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
3093 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
3094 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF,
3095 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
3096 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF,
3097 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
3098 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
3099 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
3100 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF,
3101 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
3102 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
3103 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
3104 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
3105 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
3106 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI,
3107 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
3108 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
3109 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3110 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
3111 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3112 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
3113 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3114 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS,
3115 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
3116 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
3117 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
3118 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
3119 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3120 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
3121 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3122 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI,
3123 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3124 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
3125 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3126 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
3127 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3128 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS,
3129 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3130 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
3131 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
3132 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
3133 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3134 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
3135 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3136 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI,
3137 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3138 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
3139 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3140 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
3141 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3142 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS,
3143 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3144
3145 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
3146 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3147 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
3148 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3149 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI,
3150 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3151 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
3152 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3153 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
3154 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3155 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
3156 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
3157 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
3158 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
3159 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
3160 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3161 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS,
3162 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3163
3164 /* Ternary AltiVec/VSX builtins. */
3165 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3166 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3167 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3168 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3169 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3170 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3171 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3172 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3173 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3174 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3175 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3176 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3177 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3178 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3179 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3180 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3181 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3182 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3183 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3184 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3185 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3186 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3187 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3188 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3189 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3190 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3191 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3192 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3193 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3194 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3195 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3196 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3197 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3198 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3199 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3200 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3201 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3202 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3203 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3204 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3205 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3206 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3207 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3208 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3209 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3210 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3211 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3212 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3213 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3214 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3215 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3216 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3217 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3218 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3219 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3220 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3221 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3222 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3223 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3224 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3225 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3226 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3227 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3228 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3229 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3230 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3231 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3232 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3233 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3234 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3235 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3236 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3237 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3238 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3239 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3240 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3241 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3242 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3243 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3244 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3245 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3246 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3247 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3248 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3249 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3250 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3251 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3252 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3253 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3254 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3255 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3256 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3257 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3258 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3259 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3260 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3261 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3262 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3263 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3264 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3265 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3266 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3267 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3268 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3269 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3270 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3271 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3272 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3273 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3274 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3275 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3276 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3277 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3278 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3279 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3280 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3281 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3282 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3283 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3284 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3285 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3286 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3287 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3288 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3289 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3290 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3291 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3292 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3293 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3294 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3295 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3296 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3297 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3298 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3299 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3300 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3301 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3302 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3303 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3304 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3305 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3306 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3307 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3308 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3309 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3310 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3311 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3312 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3313 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3314 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3315 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3316 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3317 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3318 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3319 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3320 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3321 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3322 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3323 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3324 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3325 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3326 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3327 { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3328 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3329 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3330 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3331 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3332 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3333 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3334 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3335 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3336 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3337 { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3338 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3339 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3340 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3341 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3342 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3343 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3344 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3345 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3346 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3347 { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3348 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3349 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3350 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3351 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3352 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3353 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3354 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3355 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3356 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3357 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3358 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3359 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3360 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3361
3362 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUDM,
3363 RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V1TI },
3364 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUDM,
3365 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI },
3366
3367 { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3368 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3369 { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3370 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3371 { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3372 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3373 { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3374 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3375 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3376 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3377 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3378 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3379 { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3380 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3381 { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3382 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3383 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3384 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3385 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3386 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3387 { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3388 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3389 { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3390 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3391 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3392 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3393 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3394 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
3395 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3396 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
3397 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3398 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3399 RS6000_BTI_unsigned_V16QI },
3400 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3401 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3402 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3403 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3404 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3405 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3406 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3407 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3408 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3409 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3410 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3411 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3412 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3413 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3414 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3415 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3416 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3417 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3418 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3419 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3420 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3421 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3422 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3423 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3424 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3425 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3426
3427 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3428 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
3429 RS6000_BTI_bool_V16QI },
3430 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3431 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3432 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR,
3433 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3434 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3435
3436 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3437 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3438 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3439 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3440 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3441 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3442 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3443 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3444 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3445 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3446 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3447 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3448 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3449 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3450 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3451 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3452 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3453 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3454 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3455 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
3456 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3457 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3458 RS6000_BTI_bool_V2DI },
3459 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3460 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3461 RS6000_BTI_unsigned_V2DI },
3462 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3463 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3464 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3465 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
3466 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3467 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3468 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3469 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
3470 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3471 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3472 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3473 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3474 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3475 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3476 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3477 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3478 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3479 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3480 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3481 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3482 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3483 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3484 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3485 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3486 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3487 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3488 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3489 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3490 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3491 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3492 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3493 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3494 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3495 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3496 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3497 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3498 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3499 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3500 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3501 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3502 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3503 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3504 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3505 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3506 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3507 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
3508 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3509 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
3510 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3511 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI },
3512 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3513 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3514 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3515 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
3516 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3517 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3518 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3519 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI },
3520 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3521 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI },
3522 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3523 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
3524 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3525 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3526 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3527 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI },
3528 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3529 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
3530 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3531 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI },
3532 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3533 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
3534 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
3535 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3536
3537 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3538 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
3539 RS6000_BTI_INTSI },
3540 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3541 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3542 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
3543 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3544 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
3545 RS6000_BTI_INTSI },
3546 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3547 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3548 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
3549 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3550 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
3551 RS6000_BTI_INTSI },
3552 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3553 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3554 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
3555 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3556 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
3557 RS6000_BTI_INTSI },
3558 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3559 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3560 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
3561
3562 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3563 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3564 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3565 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3566 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3567 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3568 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3569 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
3570 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3571 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3572 ~RS6000_BTI_unsigned_V2DI },
3573 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3574 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3575 ~RS6000_BTI_unsigned_long_long },
3576 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3577 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3578 ~RS6000_BTI_bool_V2DI },
3579 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3580 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3581 ~RS6000_BTI_long_long },
3582 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3583 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3584 ~RS6000_BTI_unsigned_long_long },
3585 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3586 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3587 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3588 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3589 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3590 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3591 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3592 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3593 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3594 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3595 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3596 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3597 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3598 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3599 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3600 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3601 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3602 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3603 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3604 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3605 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3606 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3607 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3608 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3609 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3610 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3611 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3612 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3613 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3614 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3615 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3616 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3617 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3618 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3619 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3620 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3621 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3622 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3623 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3624 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3625 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3626 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3627 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3628 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3629 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3630 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3631 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3632 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3633 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3634 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3635 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3636 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3637 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3638 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3639 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3640 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3641 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3642 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3643 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3644 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3645 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3646 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3647 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3648 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3649 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3650 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3651 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3652 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3653 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3654 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3655 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3656 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3657 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3658 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3659 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3660 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3661 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3662 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3663 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3664 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3665 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3666 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3667 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3668 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3669 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3670 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3671 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3672 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3673 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3674 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3675 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3676 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3677 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3678 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3679 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3680 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3681 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3682 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3683 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3684 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3685 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3686 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3687 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3688 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3689 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3690 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3691 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3692 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3693 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3694 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3695 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3696 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3697 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3698 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3699 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3700 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3701 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3702 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3703 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3704 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3705 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3706 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3707 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3708 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3709 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3710 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3711 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3712 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3713 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3714 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3715 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3716 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3717 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3718 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3719 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3720 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3721 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3722 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3723 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3724 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3725 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3726 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3727 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3728 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3729 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3730 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3731 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3732 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3733 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3734 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3735 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3736 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3737 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3738 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3739 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3740 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3741 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3742 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3743 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3744 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3745 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3746 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3747 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3748 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3749 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3750 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3751 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3752 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3753 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3754 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3755 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3756 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3757 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3758 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3759 ~RS6000_BTI_unsigned_V2DI },
3760 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3761 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3762 ~RS6000_BTI_bool_V2DI },
3763 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3764 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3765 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3766 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3767 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3768 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3769 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3770 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3771 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3772 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3773 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3774 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3775 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3776 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3777 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3778 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3779 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3780 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3781 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3782 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3783 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3784 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3785 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3786 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3787 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3788 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3789 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3790 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3791 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3792 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3793 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3794 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3795 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3796 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3797 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3798 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3799 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3800 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3801 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3802 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3803 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3804 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3805 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3806 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3807 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3808 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3809 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3810 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3811 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3812 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3813 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3814 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3815 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3816 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3817 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3818 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3819 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3820 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3821 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3822 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3823 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3824 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3825 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3826 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3827 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3828 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3829 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3830 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3831 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3832 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3833 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3834 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3835 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3836 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3837 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3838 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3839 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3840 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3841 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3842 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3843 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3844 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3845 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3846 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3847 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3848 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3849 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3850 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3851 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3852 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3853 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3854 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3855 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3856 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3857 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3858 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3859 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3860 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3861 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3862 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3863 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3864 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3865 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3866 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3867 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3868 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3869 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3870 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3871 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3872 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3873 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3874 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3875 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3876 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3877 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3878 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3879 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3880 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3881 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3882 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3883 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3884 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3885 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3886 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3887 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3888 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3889 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3890 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3891 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3892 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3893 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3894 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3895 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3896 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3897 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3898 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3899 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3900 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3901 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3902 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3903 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3904 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3905 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3906 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3907 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
3908 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3909 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF,
3910 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3911 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3912 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3913 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3914 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long },
3915 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void,
3916 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long },
3917 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3918 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3919 ~RS6000_BTI_unsigned_V2DI },
3920 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI,
3921 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3922 ~RS6000_BTI_bool_V2DI },
3923 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
3924 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3925 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF,
3926 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3927 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3928 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3929 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3930 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3931 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3932 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3933 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3934 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3935 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3936 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3937 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3938 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3939 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI,
3940 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3941 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3942 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3943 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3944 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3945 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3946 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3947 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3948 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3949 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3950 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3951 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3952 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3953 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3954 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3955 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3956 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3957 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3958 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3959 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3960 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3961 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3962 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3963 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3964 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3965 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3966 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3967 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI,
3968 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3969 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI,
3970 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3971 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
3972 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3973 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF,
3974 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3975 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
3976 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI },
3977 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI,
3978 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI },
3979 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3980 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3981 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3982 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
3983 ~RS6000_BTI_long_long },
3984 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3985 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3986 ~RS6000_BTI_unsigned_V2DI },
3987 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI,
3988 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3989 ~RS6000_BTI_unsigned_long_long },
3990 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
3991 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3992 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF,
3993 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3994 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3995 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3996 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3997 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3998 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
3999 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4000 ~RS6000_BTI_unsigned_V4SI },
4001 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI,
4002 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4003 ~RS6000_BTI_UINTSI },
4004 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4005 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4006 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4007 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4008 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4009 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4010 ~RS6000_BTI_unsigned_V8HI },
4011 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI,
4012 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4013 ~RS6000_BTI_UINTHI },
4014 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4015 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4016 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4017 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4018 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4019 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4020 ~RS6000_BTI_unsigned_V16QI },
4021 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
4022 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4023 ~RS6000_BTI_UINTQI },
4024 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
4025 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
4026 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
4027 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4028 RS6000_BTI_INTSI },
4029 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
4030 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
4031 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
4032 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4033 RS6000_BTI_INTSI },
4034 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
4035 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
4036 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
4037 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4038 RS6000_BTI_INTSI },
4039 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
4040 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
4041 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
4042 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4043 RS6000_BTI_INTSI },
4044 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
4045 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
4046 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
4047 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
4048
4049 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
4050 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
4051 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
4052 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
4053 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
4054 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4055 RS6000_BTI_INTSI },
4056 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
4057 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
4058 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
4059 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
4060 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
4061 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4062 RS6000_BTI_INTSI },
4063 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
4064 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
4065 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
4066 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4067 RS6000_BTI_INTSI },
4068 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
4069 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
4070 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
4071 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4072 RS6000_BTI_INTSI },
4073
4074 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
4075 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
4076 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
4077 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
4078 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4079 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
4080 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4081 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 },
4082 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4083 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
4084 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4085 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 },
4086 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4087 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4088 ~RS6000_BTI_unsigned_V2DI, 0 },
4089 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4090 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
4091 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
4092 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
4093 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
4094 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
4095 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
4096 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
4097 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4098 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
4099 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4100 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
4101 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4102 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
4103 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4104 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
4105 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4106 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4107 ~RS6000_BTI_unsigned_V4SI, 0 },
4108 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4109 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
4110 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4111 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4112 ~RS6000_BTI_unsigned_long, 0 },
4113 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4114 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
4115 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4116 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
4117 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4118 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
4119 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4120 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
4121 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4122 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4123 ~RS6000_BTI_unsigned_V8HI, 0 },
4124 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4125 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
4126 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4127 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
4128 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4129 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
4130 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4131 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
4132 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4133 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4134 ~RS6000_BTI_unsigned_V16QI, 0 },
4135 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4136 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
4137
4138 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4139 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4140 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4141 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
4142 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4143 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI,
4144 ~RS6000_BTI_long_long },
4145 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4146 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI,
4147 ~RS6000_BTI_unsigned_long_long },
4148 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4149 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI },
4150 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI,
4151 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI },
4152 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4153 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4154 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4155 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4156 ~RS6000_BTI_unsigned_V2DI },
4157 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4158 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4159 ~RS6000_BTI_bool_V2DI },
4160 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4161 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4162 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4163 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4164 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4165 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4166 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4167 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4168 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4169 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4170 ~RS6000_BTI_unsigned_V4SI },
4171 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4172 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4173 ~RS6000_BTI_UINTSI },
4174 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4175 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4176 ~RS6000_BTI_bool_V4SI },
4177 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4178 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4179 ~RS6000_BTI_UINTSI },
4180 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4181 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4182 ~RS6000_BTI_INTSI },
4183 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4184 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4185 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4186 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4187 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4188 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4189 ~RS6000_BTI_unsigned_V8HI },
4190 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4191 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4192 ~RS6000_BTI_UINTHI },
4193 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4194 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4195 ~RS6000_BTI_bool_V8HI },
4196 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4197 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4198 ~RS6000_BTI_UINTHI },
4199 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4200 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4201 ~RS6000_BTI_INTHI },
4202 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4203 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4204 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4205 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4206 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4207 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4208 ~RS6000_BTI_unsigned_V16QI },
4209 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4210 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4211 ~RS6000_BTI_UINTQI },
4212 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4213 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4214 ~RS6000_BTI_bool_V16QI },
4215 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4216 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4217 ~RS6000_BTI_UINTQI },
4218 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4219 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4220 ~RS6000_BTI_INTQI },
4221 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4222 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
4223 ~RS6000_BTI_pixel_V8HI },
4224
4225 /* Predicates. */
4226 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4227 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4228 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4229 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4230 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4231 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4232 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4233 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4234 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4235 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4236 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4237 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4238 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4239 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4240 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4241 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4242 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4243 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4244 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4245 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4246 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4247 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4248 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4249 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4250 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4251 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4252 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4253 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4254 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4255 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4256 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4257 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4258 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4259 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4260 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4261 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4262 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4263 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4264 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4265 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4266 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4267 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4268 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P10V_BUILTIN_VCMPGTUT_P,
4269 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
4270 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4271 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4272 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4273 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4274 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4275 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4276 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P10V_BUILTIN_VCMPGTST_P,
4277 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
4278 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
4279 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4280 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
4281 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4282
4283
4284 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4285 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4286 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4287 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4288 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4289 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4290 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4291 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4292 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4293 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4294 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4295 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4296 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4297 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
4298 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4299 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4300 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4301 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4302 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4303 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4304 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4305 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4306 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4307 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4308 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4309 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4310 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4311 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
4312 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4313 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
4314 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4315 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4316 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4317 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4318 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4319 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4320 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4321 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4322 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4323 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4324 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4325 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4326 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4327 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
4328 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4329 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4330 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4331 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4332 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4333 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4334 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4335 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4336 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4337 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4338 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4339 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4340 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4341 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
4342 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P10V_BUILTIN_VCMPEQUT_P,
4343 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
4344 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P10V_BUILTIN_VCMPEQUT_P,
4345 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
4346 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
4347 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4348 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
4349 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4350
4351
4352 /* cmpge is the same as cmpgt for all cases except floating point.
4353 There is further code to deal with this special case in
4354 altivec_build_resolved_builtin. */
4355 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4356 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4357 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4358 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4359 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4360 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4361 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4362 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4363 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4364 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4365 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4366 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4367 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4368 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4369 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4370 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4371 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4372 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4373 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4374 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4375 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4376 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4377 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4378 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4379 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4380 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4381 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4382 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4383 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4384 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4385 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4386 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4387 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4388 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4389 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4390 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4391 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4392 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4393 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4394 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4395 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4396 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4397 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P10V_BUILTIN_VCMPGTUT_P,
4398 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
4399 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4400 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4401 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4402 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4403 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4404 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4405 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P10V_BUILTIN_VCMPGTST_P,
4406 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
4407 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
4408 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4409 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
4410 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4411
4412 /* Power8 vector overloaded functions. */
4413 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4414 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4415 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4416 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4417 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4418 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4419 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
4420 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4421 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
4422 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4423 RS6000_BTI_unsigned_V16QI, 0 },
4424 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
4425 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4426 RS6000_BTI_bool_V16QI, 0 },
4427 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS,
4428 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4429 RS6000_BTI_unsigned_V16QI, 0 },
4430 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4431 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4432 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4433 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4434 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4435 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4436 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
4437 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4438 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
4439 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4440 RS6000_BTI_unsigned_V8HI, 0 },
4441 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
4442 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4443 RS6000_BTI_bool_V8HI, 0 },
4444 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS,
4445 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4446 RS6000_BTI_unsigned_V8HI, 0 },
4447 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4448 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4449 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4450 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4451 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4452 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4453 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
4454 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4455 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
4456 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4457 RS6000_BTI_unsigned_V4SI, 0 },
4458 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
4459 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4460 RS6000_BTI_bool_V4SI, 0 },
4461 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS,
4462 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4463 RS6000_BTI_unsigned_V4SI, 0 },
4464 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4465 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4466 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4467 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4468 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4469 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4470 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
4471 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4472 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
4473 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4474 RS6000_BTI_unsigned_V2DI, 0 },
4475 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
4476 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4477 RS6000_BTI_bool_V2DI, 0 },
4478 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS,
4479 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4480 RS6000_BTI_unsigned_V2DI, 0 },
4481 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4482 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4483 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4484 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4485
4486 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4487 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4488 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4489 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4490 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4491 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4492 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
4493 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4494 RS6000_BTI_unsigned_V16QI, 0 },
4495 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
4496 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4497 RS6000_BTI_bool_V16QI, 0 },
4498 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
4499 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4500 RS6000_BTI_unsigned_V16QI, 0 },
4501 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS,
4502 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4503 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4504 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4505 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4506 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4507 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4508 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4509 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
4510 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4511 RS6000_BTI_unsigned_V8HI, 0 },
4512 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
4513 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4514 RS6000_BTI_bool_V8HI, 0 },
4515 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
4516 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4517 RS6000_BTI_unsigned_V8HI, 0 },
4518 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS,
4519 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4520 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4521 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4522 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4523 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4524 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4525 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4526 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
4527 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4528 RS6000_BTI_unsigned_V4SI, 0 },
4529 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
4530 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4531 RS6000_BTI_bool_V4SI, 0 },
4532 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
4533 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4534 RS6000_BTI_unsigned_V4SI, 0 },
4535 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS,
4536 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4537 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4538 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4539 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4540 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4541 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4542 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4543 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
4544 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4545 RS6000_BTI_unsigned_V2DI, 0 },
4546 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
4547 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4548 RS6000_BTI_bool_V2DI, 0 },
4549 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
4550 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4551 RS6000_BTI_unsigned_V2DI, 0 },
4552 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS,
4553 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4554 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4555 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4556 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4557 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4558
4559 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4560 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4561 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4562 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4563 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4564 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4565 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
4566 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4567 RS6000_BTI_unsigned_V16QI, 0 },
4568 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
4569 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4570 RS6000_BTI_bool_V16QI, 0 },
4571 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
4572 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4573 RS6000_BTI_unsigned_V16QI, 0 },
4574 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS,
4575 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4576 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4577 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4578 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4579 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4580 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4581 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4582 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
4583 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4584 RS6000_BTI_unsigned_V8HI, 0 },
4585 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
4586 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4587 RS6000_BTI_bool_V8HI, 0 },
4588 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
4589 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4590 RS6000_BTI_unsigned_V8HI, 0 },
4591 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS,
4592 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4593 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4594 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4595 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4596 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4597 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4598 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4599 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
4600 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4601 RS6000_BTI_unsigned_V4SI, 0 },
4602 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
4603 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4604 RS6000_BTI_bool_V4SI, 0 },
4605 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
4606 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4607 RS6000_BTI_unsigned_V4SI, 0 },
4608 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS,
4609 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4610 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4611 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4612 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4613 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4614 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4615 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4616 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
4617 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4618 RS6000_BTI_unsigned_V2DI, 0 },
4619 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
4620 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4621 RS6000_BTI_bool_V2DI, 0 },
4622 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
4623 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4624 RS6000_BTI_unsigned_V2DI, 0 },
4625 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS,
4626 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4627 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4628 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4629 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4630 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4631
4632 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4633 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4634 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4635 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4636 RS6000_BTI_unsigned_V1TI, 0 },
4637
4638 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4639 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4640 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4641 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4642 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4643 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4644 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4645 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4646 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4647 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4648 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4649 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4650
4651 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4652 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4653 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4654 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4655 RS6000_BTI_unsigned_V1TI, 0 },
4656
4657 { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4658 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4659 RS6000_BTI_unsigned_V16QI, 0 },
4660 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4661 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4662 RS6000_BTI_unsigned_V16QI, 0 },
4663 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4664 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4665 RS6000_BTI_unsigned_V16QI, 0 },
4666
4667 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4668 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4669 RS6000_BTI_unsigned_V16QI, 0 },
4670 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4671 RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4672 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4673 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4674 RS6000_BTI_unsigned_V16QI, 0 },
4675 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4676 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4677 RS6000_BTI_unsigned_V16QI, 0 },
4678
4679 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4680 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4681 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4682 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4683 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4684 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4685 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4686 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4687 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4688 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4689 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4690 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4691 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4692 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4693 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4694 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4695
4696 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4697 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4698 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4699 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4700
4701 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4702 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4703 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4704 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4705
4706 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4707 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4708 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4709 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4710
4711 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4712 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4713 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4714 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4715
4716 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4717 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4718 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4719 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4720
4721 { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4722 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4723 { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4724 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4725
4726 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4727 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4728 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4729 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4730
4731 { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4732 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4733 { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4734 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4735
4736 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4737 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4738 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4739 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4740
4741 { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4742 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4743 { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4744 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4745
4746 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4747 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4748 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4749 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4750
4751 { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4752 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4753 { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4754 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4755
4756 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4757 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4758 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4759 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4760 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4761 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4762 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4763 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4764 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4765 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4766 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4767 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4768 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4769 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4770 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4771 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4772
4773 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4774 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4775 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4776 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4777
4778 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4779 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4780 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4781 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4782
4783 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4784 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4785 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4786 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4787
4788 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4789 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4790 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4791 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4792
4793 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
4794 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4795 RS6000_BTI_unsigned_V16QI, 0 },
4796 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
4797 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4798 RS6000_BTI_unsigned_V8HI, 0 },
4799 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
4800 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4801 RS6000_BTI_unsigned_V4SI, 0 },
4802
4803 { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
4804 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4805 RS6000_BTI_unsigned_V16QI, 0 },
4806
4807 { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
4808 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4809 RS6000_BTI_unsigned_V8HI, 0 },
4810
4811 { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
4812 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4813 RS6000_BTI_unsigned_V4SI, 0 },
4814
4815 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
4816 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4817 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
4818 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4819
4820 { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
4821 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4822 { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
4823 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4824
4825 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
4826 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4827 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
4828 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4829
4830 { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
4831 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4832 { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
4833 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4834
4835 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
4836 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4837 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
4838 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4839
4840 { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
4841 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4842 { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
4843 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4844
4845 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4846 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4847 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4848 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4849
4850 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4851 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4852 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4853 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4854
4855 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4856 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4857 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4858 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4859
4860 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4861 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4862 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4863 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4864
4865 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
4866 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4867 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
4868 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4869 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP,
4870 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4871
4872 { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
4873 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4874 { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
4875 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4876 { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP,
4877 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4878
4879 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
4880 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4881 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
4882 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4883 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP,
4884 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4885
4886 { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
4887 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4888 { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
4889 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4890 { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP,
4891 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4892
4893 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
4894 RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
4895 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP,
4896 RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 },
4897
4898 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
4899 RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
4900 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP,
4901 RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 },
4902
4903 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
4904 RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
4905 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
4906 RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
4907
4908 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP,
4909 RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 },
4910 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF,
4911 RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 },
4912
4913 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT,
4914 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4915 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT,
4916 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4917 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT,
4918 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4919 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT,
4920 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4921 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ,
4922 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4923 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ,
4924 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4925 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO,
4926 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4927 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO,
4928 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
4929
4930 { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,
4931 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4932 RS6000_BTI_unsigned_long_long, 0 },
4933
4934 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4935 RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4936 RS6000_BTI_unsigned_long_long, 0 },
4937 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4938 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4939 RS6000_BTI_unsigned_long_long, 0 },
4940
4941 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4942 RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4943 RS6000_BTI_unsigned_long_long, 0 },
4944 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4945 RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4946 RS6000_BTI_unsigned_long_long, 0 },
4947
4948 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4949 RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4950 RS6000_BTI_unsigned_long_long, 0 },
4951 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4952 RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4953 RS6000_BTI_unsigned_long_long, 0 },
4954
4955 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4956 RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4957 RS6000_BTI_unsigned_long_long, 0 },
4958 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4959 RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4960 RS6000_BTI_unsigned_long_long, 0 },
4961
4962 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4963 RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4964 RS6000_BTI_unsigned_long_long, 0 },
4965 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4966 RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4967 RS6000_BTI_unsigned_long_long, 0 },
4968
4969 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4970 RS6000_BTI_V2DF, ~RS6000_BTI_double,
4971 RS6000_BTI_unsigned_long_long, 0 },
4972 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4973 RS6000_BTI_V4SF, ~RS6000_BTI_float,
4974 RS6000_BTI_unsigned_long_long, 0 },
4975 /* At an appropriate future time, add support for the
4976 RS6000_BTI_Float16 (exact name to be determined) type here. */
4977
4978 { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,
4979 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,
4980 ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},
4981
4982 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4983 RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4984 RS6000_BTI_unsigned_long_long },
4985 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4986 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4987 RS6000_BTI_unsigned_long_long },
4988
4989 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4990 RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4991 RS6000_BTI_unsigned_long_long },
4992 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4993 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4994 RS6000_BTI_unsigned_long_long },
4995
4996 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4997 RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4998 RS6000_BTI_unsigned_long_long },
4999 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5000 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
5001 RS6000_BTI_unsigned_long_long },
5002
5003 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5004 RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
5005 RS6000_BTI_unsigned_long_long },
5006 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5007 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
5008 RS6000_BTI_unsigned_long_long },
5009
5010 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5011 RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
5012 RS6000_BTI_unsigned_long_long },
5013 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5014 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
5015 RS6000_BTI_unsigned_long_long },
5016
5017 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5018 RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
5019 RS6000_BTI_unsigned_long_long },
5020 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
5021 RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
5022 RS6000_BTI_unsigned_long_long },
5023 /* At an appropriate future time, add support for the
5024 RS6000_BTI_Float16 (exact name to be determined) type here. */
5025
5026 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5027 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
5028 RS6000_BTI_bool_V16QI, 0 },
5029 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5030 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5031 RS6000_BTI_V16QI, 0 },
5032 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
5033 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5034 RS6000_BTI_unsigned_V16QI, 0 },
5035
5036 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5037 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
5038 RS6000_BTI_bool_V8HI, 0 },
5039 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5040 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5041 RS6000_BTI_V8HI, 0 },
5042 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
5043 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5044 RS6000_BTI_unsigned_V8HI, 0 },
5045
5046 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5047 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
5048 RS6000_BTI_bool_V4SI, 0 },
5049 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5050 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5051 RS6000_BTI_V4SI, 0 },
5052 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
5053 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5054 RS6000_BTI_unsigned_V4SI, 0 },
5055 { ALTIVEC_BUILTIN_VEC_CMPNE, P10V_BUILTIN_CMPNET,
5056 RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI,
5057 RS6000_BTI_V1TI, 0 },
5058 { ALTIVEC_BUILTIN_VEC_CMPNE, P10V_BUILTIN_CMPNET,
5059 RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI,
5060 RS6000_BTI_unsigned_V1TI, 0 },
5061
5062 /* The following 2 entries have been deprecated. */
5063 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5064 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5065 RS6000_BTI_unsigned_V16QI, 0 },
5066 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5067 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5068 RS6000_BTI_bool_V16QI, 0 },
5069 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5070 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5071 RS6000_BTI_unsigned_V16QI, 0 },
5072
5073 /* The following 2 entries have been deprecated. */
5074 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5075 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5076 RS6000_BTI_V16QI, 0 },
5077 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5078 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5079 RS6000_BTI_bool_V16QI, 0 },
5080 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5081 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
5082 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
5083 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5084 RS6000_BTI_bool_V16QI, 0 },
5085
5086 /* The following 2 entries have been deprecated. */
5087 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5088 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5089 RS6000_BTI_unsigned_V8HI, 0 },
5090 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5091 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5092 RS6000_BTI_bool_V8HI, 0 },
5093 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5094 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5095 RS6000_BTI_unsigned_V8HI, 0 },
5096 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5097 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
5098
5099 /* The following 2 entries have been deprecated. */
5100 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5101 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5102 RS6000_BTI_V8HI, 0 },
5103 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5104 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5105 RS6000_BTI_bool_V8HI, 0 },
5106 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5107 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5108 RS6000_BTI_bool_V8HI, 0 },
5109 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
5110 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5111 RS6000_BTI_pixel_V8HI, 0 },
5112
5113 /* The following 2 entries have been deprecated. */
5114 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5115 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5116 RS6000_BTI_unsigned_V4SI, 0 },
5117 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5118 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5119 RS6000_BTI_bool_V4SI, 0 },
5120 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5121 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5122 RS6000_BTI_unsigned_V4SI, 0 },
5123
5124 /* The following 2 entries have been deprecated. */
5125 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5126 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5127 RS6000_BTI_V4SI, 0 },
5128 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5129 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5130 RS6000_BTI_bool_V4SI, 0 },
5131 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5132 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5133 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
5134 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5135 RS6000_BTI_bool_V4SI, 0 },
5136
5137 /* The following 2 entries have been deprecated. */
5138 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5139 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5140 RS6000_BTI_unsigned_V2DI, 0 },
5141 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5142 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5143 RS6000_BTI_bool_V2DI, 0 },
5144 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5145 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5146 RS6000_BTI_unsigned_V2DI, 0
5147 },
5148
5149 /* The following 2 entries have been deprecated. */
5150 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5151 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5152 RS6000_BTI_V2DI, 0 },
5153 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5154 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5155 RS6000_BTI_bool_V2DI, 0 },
5156 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5157 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5158 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5159 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5160 RS6000_BTI_bool_V2DI, 0 },
5161 { P9V_BUILTIN_VEC_VCMPNE_P, P10V_BUILTIN_VCMPNET_P,
5162 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5163 { P9V_BUILTIN_VEC_VCMPNE_P, P10V_BUILTIN_VCMPNET_P,
5164 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
5165
5166 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
5167 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5168 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
5169 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5170
5171 /* The following 2 entries have been deprecated. */
5172 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5173 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5174 RS6000_BTI_unsigned_V16QI, 0 },
5175 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5176 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5177 RS6000_BTI_bool_V16QI, 0 },
5178 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5179 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5180 RS6000_BTI_unsigned_V16QI, 0 },
5181
5182 /* The following 2 entries have been deprecated. */
5183 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5184 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5185 RS6000_BTI_V16QI, 0 },
5186 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5187 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5188 RS6000_BTI_bool_V16QI, 0 },
5189 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5190 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
5191 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5192 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5193 RS6000_BTI_bool_V16QI, 0 },
5194
5195 /* The following 2 entries have been deprecated. */
5196 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5197 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5198 RS6000_BTI_unsigned_V8HI, 0 },
5199 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5200 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5201 RS6000_BTI_bool_V8HI, 0 },
5202 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5203 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5204 RS6000_BTI_unsigned_V8HI, 0 },
5205 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5206 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
5207
5208 /* The following 2 entries have been deprecated. */
5209 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5210 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5211 RS6000_BTI_V8HI, 0 },
5212 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5213 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5214 RS6000_BTI_bool_V8HI, 0 },
5215 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5216 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5217 RS6000_BTI_bool_V8HI, 0 },
5218 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5219 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5220 RS6000_BTI_pixel_V8HI, 0 },
5221
5222 /* The following 2 entries have been deprecated. */
5223 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5224 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5225 RS6000_BTI_unsigned_V4SI, 0 },
5226 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5227 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5228 RS6000_BTI_bool_V4SI, 0 },
5229 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5230 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5231 RS6000_BTI_unsigned_V4SI, 0 },
5232
5233 /* The following 2 entries have been deprecated. */
5234 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5235 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5236 RS6000_BTI_V4SI, 0 },
5237 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5238 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5239 RS6000_BTI_bool_V4SI, 0 },
5240 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5241 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5242 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5243 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5244 RS6000_BTI_bool_V4SI, 0 },
5245
5246 /* The following 2 entries have been deprecated. */
5247 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5248 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5249 RS6000_BTI_unsigned_V2DI, 0 },
5250 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5251 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5252 RS6000_BTI_bool_V2DI, 0 },
5253 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5254 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5255 RS6000_BTI_unsigned_V2DI, 0
5256 },
5257
5258 /* The following 2 entries have been deprecated. */
5259 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5260 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5261 RS6000_BTI_V2DI, 0 },
5262 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5263 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5264 RS6000_BTI_bool_V2DI, 0 },
5265 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5266 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5267 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5268 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5269 RS6000_BTI_bool_V2DI, 0 },
5270 { P9V_BUILTIN_VEC_VCMPAE_P, P10V_BUILTIN_VCMPAET_P,
5271 RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5272 { P9V_BUILTIN_VEC_VCMPAE_P, P10V_BUILTIN_VCMPAET_P,
5273 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
5274 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
5275 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5276 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
5277 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5278
5279 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5280 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5281 RS6000_BTI_unsigned_V16QI },
5282 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5283 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
5284
5285 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5286 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5287 RS6000_BTI_unsigned_V8HI },
5288 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5289 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
5290
5291 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5292 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5293 RS6000_BTI_unsigned_V4SI },
5294 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5295 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
5296
5297 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5298 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5299 RS6000_BTI_V16QI, 0 },
5300 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5301 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5302 RS6000_BTI_unsigned_V16QI, 0 },
5303
5304 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5305 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5306 RS6000_BTI_V8HI, 0 },
5307 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5308 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5309 RS6000_BTI_unsigned_V8HI, 0 },
5310
5311 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5312 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5313 RS6000_BTI_V4SI, 0 },
5314 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5315 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5316 RS6000_BTI_unsigned_V4SI, 0 },
5317
5318 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5319 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5320 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI,
5321 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5322
5323 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5324 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5325 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI,
5326 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5327 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI,
5328 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
5329 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI,
5330 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 },
5331
5332 { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B,
5333 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
5334
5335 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
5336 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5337 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
5338 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5339
5340 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5341 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5342 RS6000_BTI_V16QI, 0 },
5343 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5344 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5345 RS6000_BTI_unsigned_V16QI, 0 },
5346
5347 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5348 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5349 RS6000_BTI_V8HI, 0 },
5350 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5351 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5352 RS6000_BTI_unsigned_V8HI, 0 },
5353
5354 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5355 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5356 RS6000_BTI_V4SI, 0 },
5357 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5358 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5359 RS6000_BTI_unsigned_V4SI, 0 },
5360 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5361 RS6000_BTI_float, RS6000_BTI_UINTSI,
5362 RS6000_BTI_V4SF, 0 },
5363
5364 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5365 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5366 RS6000_BTI_V16QI, 0 },
5367 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5368 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5369 RS6000_BTI_unsigned_V16QI, 0 },
5370
5371 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5372 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5373 RS6000_BTI_V8HI, 0 },
5374 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5375 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5376 RS6000_BTI_unsigned_V8HI, 0 },
5377
5378 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5379 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5380 RS6000_BTI_V4SI, 0 },
5381 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5382 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5383 RS6000_BTI_unsigned_V4SI, 0 },
5384 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5385 RS6000_BTI_float, RS6000_BTI_UINTSI,
5386 RS6000_BTI_V4SF, 0 },
5387
5388 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5389 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5390 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5391 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5392
5393 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5394 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI,
5395 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5396 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
5397 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5398 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
5399
5400 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5401 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5402 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5403 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5404 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5405
5406 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5407 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5408 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5409 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5410 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5411
5412 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5413 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5414 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5415 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5416 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5417
5418 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5419 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5420 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5421 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5422 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5423
5424 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5425 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5426 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5427 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5428 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5429 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5430
5431 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5432 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5433 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5434 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5435 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5436 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5437
5438 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5439 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5440 RS6000_BTI_unsigned_V2DI, 0 },
5441 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5442 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5443 RS6000_BTI_bool_V2DI, 0 },
5444 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5445 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5446 RS6000_BTI_unsigned_V2DI, 0 },
5447
5448 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5449 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5450 RS6000_BTI_unsigned_V2DI, 0 },
5451 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5452 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5453 RS6000_BTI_bool_V2DI, 0 },
5454 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5455 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5456 RS6000_BTI_unsigned_V2DI, 0 },
5457
5458 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5459 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5460 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5461 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5462 RS6000_BTI_unsigned_V2DI, 0 },
5463 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI,
5464 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5465 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF,
5466 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5467 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF,
5468 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5469 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5470 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5471 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5472 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5473 RS6000_BTI_unsigned_V4SI, 0 },
5474 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5475 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5476
5477 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5478 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5479 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5480 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5481 RS6000_BTI_unsigned_V4SI, 0 },
5482 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI,
5483 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5484 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5485 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5486 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5487 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5488 RS6000_BTI_unsigned_V2DI, 0 },
5489 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI,
5490 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5491 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF,
5492 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5493 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF,
5494 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5495
5496 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5497 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5498 RS6000_BTI_unsigned_V16QI, 0 },
5499 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5500 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5501 RS6000_BTI_unsigned_V8HI, 0 },
5502 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5503 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5504 RS6000_BTI_unsigned_V4SI, 0 },
5505 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5506 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5507 RS6000_BTI_unsigned_V2DI, 0 },
5508
5509 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5510 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5511 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5512 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5513 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5514 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5515 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5516 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5517 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5518 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5519 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5520 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5521 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5522 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5523 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5524 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5525
5526 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5527 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5528 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5529 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5530
5531 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5532 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 },
5533 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5534 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5535
5536 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5537 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 },
5538 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5539 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5540
5541 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5542 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5543 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5544 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5545
5546 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5547 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5548 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5549 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5550
5551 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5552 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5553 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5554 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5555
5556 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5557 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5558 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5559 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5560
5561 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5562 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5563 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5564 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5565
5566 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5567 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5568 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5569 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5570 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5571 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5572 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5573 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5574 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5575 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5576 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5577 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5578 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5579 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5580 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5581 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5582
5583 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5584 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5585 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5586 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5587
5588 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5589 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5590 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5591 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5592
5593 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5594 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5595 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5596 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5597 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5598 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5599 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5600 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5601
5602 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5603 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5604 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5605 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5606 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5607 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5608 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5609 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5610 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5611 RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 },
5612 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5613 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5614
5615 { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5616 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5617 { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5618 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5619 { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5620 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5621
5622 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5623 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5624 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5625 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5626 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5627 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5628
5629 { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5630 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5631
5632 { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5633 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5634
5635 { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5636 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5637
5638 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5639 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5640 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5641 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5642
5643 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5644 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5645 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5646 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5647
5648 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5649 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5650 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5651 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5652
5653 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5654 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5655 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5656 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5657
5658 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5659 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5660 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5661 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5662 RS6000_BTI_unsigned_V1TI, 0 },
5663
5664 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5665 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5666 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5667 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5668 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5669 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5670 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5671 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5672 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5673 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5674 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5675 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5676
5677 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5678 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5679 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5680 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5681 RS6000_BTI_unsigned_V1TI, 0 },
5682
5683 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32,
5684 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 },
5685 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB,
5686 RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5687
5688 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5689 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5690 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5691 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5692
5693 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5694 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5695 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5696 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5697
5698 { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5699 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5700 RS6000_BTI_unsigned_V16QI, 0 },
5701 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5702 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5703 RS6000_BTI_unsigned_V16QI, 0 },
5704
5705 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5706 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5707 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI,
5708 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5709 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5710 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5711 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5712 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5713 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI,
5714 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5715 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5716 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5717 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5718 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5719 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI,
5720 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5721 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5722 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5723 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5724 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5725 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI,
5726 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5727 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5728 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5729 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5730 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5731 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI,
5732 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5733 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF,
5734 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5735 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF,
5736 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5737
5738 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5739 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5740 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5741 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5742 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5743 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5744 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5745 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5746 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5747 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5748 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5749 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5750 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5751 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5752 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5753 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5754 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF,
5755 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5756 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF,
5757 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5758 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5759 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5760 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5761 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5762 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5763 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5764 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5765 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5766
5767 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF,
5768 RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 },
5769 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF,
5770 RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 },
5771 { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF,
5772 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5773 { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
5774 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5775 { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF,
5776 RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5777
5778 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
5779 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5780 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF,
5781 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5782 { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF,
5783 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5784 { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
5785 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5786 { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF,
5787 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
5788 RS6000_BTI_V2DF, 0 },
5789
5790 /* Crypto builtins. */
5791 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5792 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5793 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5794 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5795 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5796 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5797 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5798 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5799 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5800 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5801 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5802 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5803
5804 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5805 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5806 RS6000_BTI_unsigned_V16QI, 0 },
5807 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5808 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5809 RS6000_BTI_unsigned_V8HI, 0 },
5810 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5811 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5812 RS6000_BTI_unsigned_V4SI, 0 },
5813 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
5814 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5815 RS6000_BTI_unsigned_V2DI, 0 },
5816
5817 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
5818 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5819 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5820 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
5821 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5822 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5823
5824 /* Sign extend builtins that work work on ISA 3.0, not added until ISA 3.1 */
5825 { P9V_BUILTIN_VEC_VSIGNEXTI, P9V_BUILTIN_VSIGNEXTSB2W,
5826 RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0, 0 },
5827 { P9V_BUILTIN_VEC_VSIGNEXTI, P9V_BUILTIN_VSIGNEXTSH2W,
5828 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
5829
5830 { P9V_BUILTIN_VEC_VSIGNEXTLL, P9V_BUILTIN_VSIGNEXTSB2D,
5831 RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0, 0 },
5832 { P9V_BUILTIN_VEC_VSIGNEXTLL, P9V_BUILTIN_VSIGNEXTSH2D,
5833 RS6000_BTI_V2DI, RS6000_BTI_V8HI, 0, 0 },
5834 { P9V_BUILTIN_VEC_VSIGNEXTLL, P9V_BUILTIN_VSIGNEXTSW2D,
5835 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5836
5837 /* Overloaded built-in functions for ISA3.1 (power10). */
5838 { P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB,
5839 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
5840 { P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB,
5841 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5842 RS6000_BTI_UINTSI, 0 },
5843 { P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB,
5844 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
5845 { P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB,
5846 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5847 RS6000_BTI_UINTSI, 0 },
5848
5849 { P10_BUILTIN_VEC_GNB, P10V_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
5850 RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTQI, 0 },
5851 { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V2DI,
5852 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
5853 { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V4SI,
5854 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
5855 { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V8HI,
5856 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
5857 { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V16QI,
5858 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5859 RS6000_BTI_INTSI, 0 },
5860
5861 /* The overloaded XXEVAL definitions are handled specially because the
5862 fourth unsigned char operand is not encoded in this table. */
5863 { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
5864 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5865 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5866 { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
5867 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5868 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5869 { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
5870 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5871 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5872 { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
5873 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5874 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5875 { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
5876 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5877 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5878
5879 /* The overloaded XXPERMX definitions are handled specially because the
5880 fourth unsigned char operand is not encoded in this table. */
5881 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5882 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
5883 RS6000_BTI_unsigned_V16QI },
5884 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5885 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5886 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5887 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5888 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
5889 RS6000_BTI_unsigned_V16QI },
5890 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5891 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5892 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
5893 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5894 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
5895 RS6000_BTI_unsigned_V16QI },
5896 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5897 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5898 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
5899 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5900 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
5901 RS6000_BTI_unsigned_V16QI },
5902 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5903 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5904 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
5905 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5906 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF,
5907 RS6000_BTI_unsigned_V16QI },
5908 { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
5909 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF,
5910 RS6000_BTI_unsigned_V16QI },
5911
5912 { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTBL,
5913 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
5914 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
5915 { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTHL,
5916 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
5917 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
5918 { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTWL,
5919 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5920 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
5921 { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTDL,
5922 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5923 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
5924
5925 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRBL,
5926 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI,
5927 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
5928 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRHL,
5929 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI,
5930 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI },
5931 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRWL,
5932 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI,
5933 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI },
5934 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRDL,
5935 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI,
5936 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI },
5937 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRBL,
5938 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5939 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
5940 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRHL,
5941 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5942 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
5943 { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRWL,
5944 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5945 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
5946
5947 { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTBR,
5948 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
5949 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
5950 { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTHR,
5951 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
5952 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
5953 { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTWR,
5954 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5955 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
5956 { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTDR,
5957 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5958 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
5959
5960 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRBR,
5961 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI,
5962 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
5963 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRHR,
5964 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI,
5965 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI },
5966 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRWR,
5967 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI,
5968 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI },
5969 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRDR,
5970 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI,
5971 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI },
5972 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRBR,
5973 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5974 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
5975 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRHR,
5976 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5977 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
5978 { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRWR,
5979 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5980 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
5981
5982 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV4SI,
5983 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5984 RS6000_BTI_UINTSI, RS6000_BTI_UINTQI },
5985 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SI,
5986 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI },
5987 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SF,
5988 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI },
5989 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV2DI,
5990 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5991 RS6000_BTI_UINTDI, RS6000_BTI_UINTQI },
5992 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DI,
5993 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI },
5994 { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DF,
5995 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI },
5996
5997 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV4SI,
5998 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5999 RS6000_BTI_UINTSI, RS6000_BTI_UINTQI },
6000 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SI,
6001 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI },
6002 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SF,
6003 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI },
6004 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV2DI,
6005 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
6006 RS6000_BTI_UINTDI, RS6000_BTI_UINTQI },
6007 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DI,
6008 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI },
6009 { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DF,
6010 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI },
6011
6012 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI,
6013 RS6000_BTI_V16QI, RS6000_BTI_V16QI,
6014 RS6000_BTI_V16QI, RS6000_BTI_UINTQI },
6015 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI,
6016 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
6017 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
6018 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI,
6019 RS6000_BTI_V8HI, RS6000_BTI_V8HI,
6020 RS6000_BTI_V8HI, RS6000_BTI_UINTQI },
6021 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI,
6022 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
6023 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
6024 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI,
6025 RS6000_BTI_V4SI, RS6000_BTI_V4SI,
6026 RS6000_BTI_V4SI, RS6000_BTI_UINTQI },
6027 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI,
6028 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
6029 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
6030 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI,
6031 RS6000_BTI_V2DI, RS6000_BTI_V2DI,
6032 RS6000_BTI_V2DI, RS6000_BTI_UINTQI },
6033 { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI,
6034 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
6035 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
6036
6037 { P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SI,
6038 RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0, 0 },
6039 { P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SF,
6040 RS6000_BTI_V4SF, RS6000_BTI_float, 0, 0 },
6041
6042 { P10_BUILTIN_VEC_XXSPLTID, P10V_BUILTIN_VXXSPLTID,
6043 RS6000_BTI_V2DF, RS6000_BTI_float, 0, 0 },
6044
6045 { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI,
6046 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_UINTQI, RS6000_BTI_INTSI },
6047 { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI,
6048 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI,
6049 RS6000_BTI_UINTSI },
6050 { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SF,
6051 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_UINTQI, RS6000_BTI_float },
6052
6053 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI,
6054 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
6055 RS6000_BTI_unsigned_V16QI },
6056 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI,
6057 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
6058 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
6059 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI,
6060 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
6061 RS6000_BTI_unsigned_V8HI },
6062 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI,
6063 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
6064 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
6065 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI,
6066 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
6067 RS6000_BTI_unsigned_V4SI },
6068 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI,
6069 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
6070 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
6071 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI,
6072 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
6073 RS6000_BTI_unsigned_V2DI },
6074 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI,
6075 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
6076 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
6077 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SF,
6078 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF,
6079 RS6000_BTI_unsigned_V4SI },
6080 { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DF,
6081 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF,
6082 RS6000_BTI_unsigned_V2DI },
6083
6084 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI,
6085 RS6000_BTI_V16QI, RS6000_BTI_V16QI,
6086 RS6000_BTI_V16QI, RS6000_BTI_UINTQI },
6087 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI,
6088 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
6089 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
6090 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI,
6091 RS6000_BTI_V8HI, RS6000_BTI_V8HI,
6092 RS6000_BTI_V8HI, RS6000_BTI_UINTQI },
6093 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI,
6094 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
6095 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
6096 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI,
6097 RS6000_BTI_V4SI, RS6000_BTI_V4SI,
6098 RS6000_BTI_V4SI, RS6000_BTI_UINTQI },
6099 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI,
6100 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
6101 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
6102 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI,
6103 RS6000_BTI_V2DI, RS6000_BTI_V2DI,
6104 RS6000_BTI_V2DI, RS6000_BTI_UINTQI },
6105 { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI,
6106 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
6107 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
6108
6109 { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL,
6110 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
6111 { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL,
6112 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
6113
6114 { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL,
6115 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
6116 { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL,
6117 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
6118
6119 { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P,
6120 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
6121 { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P,
6122 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
6123
6124 { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P,
6125 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
6126 { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P,
6127 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
6128
6129 { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR,
6130 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
6131 { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR,
6132 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
6133
6134 { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR,
6135 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
6136 { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR,
6137 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
6138
6139 { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P,
6140 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
6141 { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P,
6142 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
6143
6144 { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P,
6145 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
6146 { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P,
6147 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
6148
6149 { P10_BUILTIN_VEC_MTVSRBM, P10V_BUILTIN_MTVSRBM,
6150 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI, 0, 0 },
6151 { P10_BUILTIN_VEC_MTVSRHM, P10V_BUILTIN_MTVSRHM,
6152 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTDI, 0, 0 },
6153 { P10_BUILTIN_VEC_MTVSRWM, P10V_BUILTIN_MTVSRWM,
6154 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTDI, 0, 0 },
6155 { P10_BUILTIN_VEC_MTVSRDM, P10V_BUILTIN_MTVSRDM,
6156 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI, 0, 0 },
6157 { P10_BUILTIN_VEC_MTVSRQM, P10V_BUILTIN_MTVSRQM,
6158 RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTDI, 0, 0 },
6159
6160 { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBB,
6161 RS6000_BTI_unsigned_long_long,
6162 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, 0 },
6163 { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBH,
6164 RS6000_BTI_unsigned_long_long,
6165 RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI, 0 },
6166 { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBW,
6167 RS6000_BTI_unsigned_long_long,
6168 RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI, 0 },
6169 { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBD,
6170 RS6000_BTI_unsigned_long_long,
6171 RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI, 0 },
6172
6173 { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMB,
6174 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
6175 { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMH,
6176 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
6177 { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMW,
6178 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
6179 { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMD,
6180 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
6181 { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMQ,
6182 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
6183
6184 { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMB,
6185 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
6186 { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMH,
6187 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
6188 { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMW,
6189 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 0, 0 },
6190 { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMD,
6191 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 0, 0 },
6192 { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMQ,
6193 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, 0, 0 },
6194
6195 { P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10V_BUILTIN_XVTLSBB_ZEROS,
6196 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
6197 { P10_BUILTIN_VEC_XVTLSBB_ONES, P10V_BUILTIN_XVTLSBB_ONES,
6198 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
6199
6200 { P10_BUILTIN_VEC_SIGNEXT, P10V_BUILTIN_VSIGNEXTSD2Q,
6201 RS6000_BTI_V1TI, RS6000_BTI_V2DI, 0, 0 },
6202
6203 { RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 }
6204 };
6205
6206 /* Nonzero if we can use a floating-point register to pass this arg. */
6207 #define USE_FP_FOR_ARG_P(CUM,MODE) \
6208 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
6209 && (CUM)->fregno <= FP_ARG_MAX_REG \
6210 && TARGET_HARD_FLOAT)
6211
6212 /* Nonzero if we can use an AltiVec register to pass this arg. */
6213 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
6214 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
6215 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
6216 && TARGET_ALTIVEC_ABI \
6217 && (NAMED))
6218
6219 /* Walk down the type tree of TYPE counting consecutive base elements.
6220 If *MODEP is VOIDmode, then set it to the first valid floating point
6221 or vector type. If a non-floating point or vector type is found, or
6222 if a floating point or vector type that doesn't match a non-VOIDmode
6223 *MODEP is found, then return -1, otherwise return the count in the
6224 sub-tree. */
6225
6226 static int
rs6000_aggregate_candidate(const_tree type,machine_mode * modep,int * empty_base_seen)6227 rs6000_aggregate_candidate (const_tree type, machine_mode *modep,
6228 int *empty_base_seen)
6229 {
6230 machine_mode mode;
6231 HOST_WIDE_INT size;
6232
6233 switch (TREE_CODE (type))
6234 {
6235 case REAL_TYPE:
6236 mode = TYPE_MODE (type);
6237 if (!SCALAR_FLOAT_MODE_P (mode))
6238 return -1;
6239
6240 if (*modep == VOIDmode)
6241 *modep = mode;
6242
6243 if (*modep == mode)
6244 return 1;
6245
6246 break;
6247
6248 case COMPLEX_TYPE:
6249 mode = TYPE_MODE (TREE_TYPE (type));
6250 if (!SCALAR_FLOAT_MODE_P (mode))
6251 return -1;
6252
6253 if (*modep == VOIDmode)
6254 *modep = mode;
6255
6256 if (*modep == mode)
6257 return 2;
6258
6259 break;
6260
6261 case VECTOR_TYPE:
6262 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
6263 return -1;
6264
6265 /* Use V4SImode as representative of all 128-bit vector types. */
6266 size = int_size_in_bytes (type);
6267 switch (size)
6268 {
6269 case 16:
6270 mode = V4SImode;
6271 break;
6272 default:
6273 return -1;
6274 }
6275
6276 if (*modep == VOIDmode)
6277 *modep = mode;
6278
6279 /* Vector modes are considered to be opaque: two vectors are
6280 equivalent for the purposes of being homogeneous aggregates
6281 if they are the same size. */
6282 if (*modep == mode)
6283 return 1;
6284
6285 break;
6286
6287 case ARRAY_TYPE:
6288 {
6289 int count;
6290 tree index = TYPE_DOMAIN (type);
6291
6292 /* Can't handle incomplete types nor sizes that are not
6293 fixed. */
6294 if (!COMPLETE_TYPE_P (type)
6295 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
6296 return -1;
6297
6298 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep,
6299 empty_base_seen);
6300 if (count == -1
6301 || !index
6302 || !TYPE_MAX_VALUE (index)
6303 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
6304 || !TYPE_MIN_VALUE (index)
6305 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
6306 || count < 0)
6307 return -1;
6308
6309 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
6310 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
6311
6312 /* There must be no padding. */
6313 if (wi::to_wide (TYPE_SIZE (type))
6314 != count * GET_MODE_BITSIZE (*modep))
6315 return -1;
6316
6317 return count;
6318 }
6319
6320 case RECORD_TYPE:
6321 {
6322 int count = 0;
6323 int sub_count;
6324 tree field;
6325
6326 /* Can't handle incomplete types nor sizes that are not
6327 fixed. */
6328 if (!COMPLETE_TYPE_P (type)
6329 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
6330 return -1;
6331
6332 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6333 {
6334 if (TREE_CODE (field) != FIELD_DECL)
6335 continue;
6336
6337 if (DECL_FIELD_ABI_IGNORED (field))
6338 {
6339 if (lookup_attribute ("no_unique_address",
6340 DECL_ATTRIBUTES (field)))
6341 *empty_base_seen |= 2;
6342 else
6343 *empty_base_seen |= 1;
6344 continue;
6345 }
6346
6347 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep,
6348 empty_base_seen);
6349 if (sub_count < 0)
6350 return -1;
6351 count += sub_count;
6352 }
6353
6354 /* There must be no padding. */
6355 if (wi::to_wide (TYPE_SIZE (type))
6356 != count * GET_MODE_BITSIZE (*modep))
6357 return -1;
6358
6359 return count;
6360 }
6361
6362 case UNION_TYPE:
6363 case QUAL_UNION_TYPE:
6364 {
6365 /* These aren't very interesting except in a degenerate case. */
6366 int count = 0;
6367 int sub_count;
6368 tree field;
6369
6370 /* Can't handle incomplete types nor sizes that are not
6371 fixed. */
6372 if (!COMPLETE_TYPE_P (type)
6373 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
6374 return -1;
6375
6376 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6377 {
6378 if (TREE_CODE (field) != FIELD_DECL)
6379 continue;
6380
6381 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep,
6382 empty_base_seen);
6383 if (sub_count < 0)
6384 return -1;
6385 count = count > sub_count ? count : sub_count;
6386 }
6387
6388 /* There must be no padding. */
6389 if (wi::to_wide (TYPE_SIZE (type))
6390 != count * GET_MODE_BITSIZE (*modep))
6391 return -1;
6392
6393 return count;
6394 }
6395
6396 default:
6397 break;
6398 }
6399
6400 return -1;
6401 }
6402
6403 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
6404 float or vector aggregate that shall be passed in FP/vector registers
6405 according to the ELFv2 ABI, return the homogeneous element mode in
6406 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
6407
6408 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
6409
6410 bool
rs6000_discover_homogeneous_aggregate(machine_mode mode,const_tree type,machine_mode * elt_mode,int * n_elts)6411 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
6412 machine_mode *elt_mode,
6413 int *n_elts)
6414 {
6415 /* Note that we do not accept complex types at the top level as
6416 homogeneous aggregates; these types are handled via the
6417 targetm.calls.split_complex_arg mechanism. Complex types
6418 can be elements of homogeneous aggregates, however. */
6419 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
6420 && AGGREGATE_TYPE_P (type))
6421 {
6422 machine_mode field_mode = VOIDmode;
6423 int empty_base_seen = 0;
6424 int field_count = rs6000_aggregate_candidate (type, &field_mode,
6425 &empty_base_seen);
6426
6427 if (field_count > 0)
6428 {
6429 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
6430 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
6431
6432 /* The ELFv2 ABI allows homogeneous aggregates to occupy
6433 up to AGGR_ARG_NUM_REG registers. */
6434 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
6435 {
6436 if (elt_mode)
6437 *elt_mode = field_mode;
6438 if (n_elts)
6439 *n_elts = field_count;
6440 if (empty_base_seen && warn_psabi)
6441 {
6442 static unsigned last_reported_type_uid;
6443 unsigned uid = TYPE_UID (TYPE_MAIN_VARIANT (type));
6444 if (uid != last_reported_type_uid)
6445 {
6446 const char *url
6447 = CHANGES_ROOT_URL "gcc-10/changes.html#empty_base";
6448 if (empty_base_seen & 1)
6449 inform (input_location,
6450 "parameter passing for argument of type %qT "
6451 "when C++17 is enabled changed to match C++14 "
6452 "%{in GCC 10.1%}", type, url);
6453 else
6454 inform (input_location,
6455 "parameter passing for argument of type %qT "
6456 "with %<[[no_unique_address]]%> members "
6457 "changed %{in GCC 10.1%}", type, url);
6458 last_reported_type_uid = uid;
6459 }
6460 }
6461 return true;
6462 }
6463 }
6464 }
6465
6466 if (elt_mode)
6467 *elt_mode = mode;
6468 if (n_elts)
6469 *n_elts = 1;
6470 return false;
6471 }
6472
6473 /* Return a nonzero value to say to return the function value in
6474 memory, just as large structures are always returned. TYPE will be
6475 the data type of the value, and FNTYPE will be the type of the
6476 function doing the returning, or @code{NULL} for libcalls.
6477
6478 The AIX ABI for the RS/6000 specifies that all structures are
6479 returned in memory. The Darwin ABI does the same.
6480
6481 For the Darwin 64 Bit ABI, a function result can be returned in
6482 registers or in memory, depending on the size of the return data
6483 type. If it is returned in registers, the value occupies the same
6484 registers as it would if it were the first and only function
6485 argument. Otherwise, the function places its result in memory at
6486 the location pointed to by GPR3.
6487
6488 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
6489 but a draft put them in memory, and GCC used to implement the draft
6490 instead of the final standard. Therefore, aix_struct_return
6491 controls this instead of DEFAULT_ABI; V.4 targets needing backward
6492 compatibility can change DRAFT_V4_STRUCT_RET to override the
6493 default, and -m switches get the final word. See
6494 rs6000_option_override_internal for more details.
6495
6496 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
6497 long double support is enabled. These values are returned in memory.
6498
6499 int_size_in_bytes returns -1 for variable size objects, which go in
6500 memory always. The cast to unsigned makes -1 > 8. */
6501
6502 bool
rs6000_return_in_memory(const_tree type,const_tree fntype ATTRIBUTE_UNUSED)6503 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6504 {
6505 /* We do not allow MMA types being used as return values. Only report
6506 the invalid return value usage the first time we encounter it. */
6507 if (cfun
6508 && !cfun->machine->mma_return_type_error
6509 && TREE_TYPE (cfun->decl) == fntype
6510 && (TYPE_MODE (type) == OOmode || TYPE_MODE (type) == XOmode))
6511 {
6512 /* Record we have now handled function CFUN, so the next time we
6513 are called, we do not re-report the same error. */
6514 cfun->machine->mma_return_type_error = true;
6515 if (TYPE_CANONICAL (type) != NULL_TREE)
6516 type = TYPE_CANONICAL (type);
6517 error ("invalid use of MMA type %qs as a function return value",
6518 IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))));
6519 }
6520
6521 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
6522 if (TARGET_MACHO
6523 && rs6000_darwin64_abi
6524 && TREE_CODE (type) == RECORD_TYPE
6525 && int_size_in_bytes (type) > 0)
6526 {
6527 CUMULATIVE_ARGS valcum;
6528 rtx valret;
6529
6530 valcum.words = 0;
6531 valcum.fregno = FP_ARG_MIN_REG;
6532 valcum.vregno = ALTIVEC_ARG_MIN_REG;
6533 /* Do a trial code generation as if this were going to be passed
6534 as an argument; if any part goes in memory, we return NULL. */
6535 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
6536 if (valret)
6537 return false;
6538 /* Otherwise fall through to more conventional ABI rules. */
6539 }
6540
6541 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
6542 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
6543 NULL, NULL))
6544 return false;
6545
6546 /* The ELFv2 ABI returns aggregates up to 16B in registers */
6547 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
6548 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
6549 return false;
6550
6551 if (AGGREGATE_TYPE_P (type)
6552 && (aix_struct_return
6553 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
6554 return true;
6555
6556 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6557 modes only exist for GCC vector types if -maltivec. */
6558 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
6559 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6560 return false;
6561
6562 /* Return synthetic vectors in memory. */
6563 if (TREE_CODE (type) == VECTOR_TYPE
6564 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6565 {
6566 static bool warned_for_return_big_vectors = false;
6567 if (!warned_for_return_big_vectors)
6568 {
6569 warning (OPT_Wpsabi, "GCC vector returned by reference: "
6570 "non-standard ABI extension with no compatibility "
6571 "guarantee");
6572 warned_for_return_big_vectors = true;
6573 }
6574 return true;
6575 }
6576
6577 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
6578 && FLOAT128_IEEE_P (TYPE_MODE (type)))
6579 return true;
6580
6581 return false;
6582 }
6583
6584 /* Specify whether values returned in registers should be at the most
6585 significant end of a register. We want aggregates returned by
6586 value to match the way aggregates are passed to functions. */
6587
6588 bool
rs6000_return_in_msb(const_tree valtype)6589 rs6000_return_in_msb (const_tree valtype)
6590 {
6591 return (DEFAULT_ABI == ABI_ELFv2
6592 && BYTES_BIG_ENDIAN
6593 && AGGREGATE_TYPE_P (valtype)
6594 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
6595 == PAD_UPWARD));
6596 }
6597
6598 #ifdef HAVE_AS_GNU_ATTRIBUTE
6599 /* Return TRUE if a call to function FNDECL may be one that
6600 potentially affects the function calling ABI of the object file. */
6601
6602 static bool
call_ABI_of_interest(tree fndecl)6603 call_ABI_of_interest (tree fndecl)
6604 {
6605 if (rs6000_gnu_attr && symtab->state == EXPANSION)
6606 {
6607 struct cgraph_node *c_node;
6608
6609 /* Libcalls are always interesting. */
6610 if (fndecl == NULL_TREE)
6611 return true;
6612
6613 /* Any call to an external function is interesting. */
6614 if (DECL_EXTERNAL (fndecl))
6615 return true;
6616
6617 /* Interesting functions that we are emitting in this object file. */
6618 c_node = cgraph_node::get (fndecl);
6619 c_node = c_node->ultimate_alias_target ();
6620 return !c_node->only_called_directly_p ();
6621 }
6622 return false;
6623 }
6624 #endif
6625
6626 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6627 for a call to a function whose data type is FNTYPE.
6628 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
6629
6630 For incoming args we set the number of arguments in the prototype large
6631 so we never return a PARALLEL. */
6632
6633 void
init_cumulative_args(CUMULATIVE_ARGS * cum,tree fntype,rtx libname ATTRIBUTE_UNUSED,int incoming,int libcall,int n_named_args,tree fndecl,machine_mode return_mode ATTRIBUTE_UNUSED)6634 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
6635 rtx libname ATTRIBUTE_UNUSED, int incoming,
6636 int libcall, int n_named_args,
6637 tree fndecl,
6638 machine_mode return_mode ATTRIBUTE_UNUSED)
6639 {
6640 static CUMULATIVE_ARGS zero_cumulative;
6641
6642 *cum = zero_cumulative;
6643 cum->words = 0;
6644 cum->fregno = FP_ARG_MIN_REG;
6645 cum->vregno = ALTIVEC_ARG_MIN_REG;
6646 cum->prototype = (fntype && prototype_p (fntype));
6647 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
6648 ? CALL_LIBCALL : CALL_NORMAL);
6649 cum->sysv_gregno = GP_ARG_MIN_REG;
6650 cum->stdarg = stdarg_p (fntype);
6651 cum->libcall = libcall;
6652
6653 cum->nargs_prototype = 0;
6654 if (incoming || cum->prototype)
6655 cum->nargs_prototype = n_named_args;
6656
6657 /* Check for a longcall attribute. */
6658 if ((!fntype && rs6000_default_long_calls)
6659 || (fntype
6660 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
6661 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
6662 cum->call_cookie |= CALL_LONG;
6663 else if (DEFAULT_ABI != ABI_DARWIN)
6664 {
6665 bool is_local = (fndecl
6666 && !DECL_EXTERNAL (fndecl)
6667 && !DECL_WEAK (fndecl)
6668 && (*targetm.binds_local_p) (fndecl));
6669 if (is_local)
6670 ;
6671 else if (flag_plt)
6672 {
6673 if (fntype
6674 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype)))
6675 cum->call_cookie |= CALL_LONG;
6676 }
6677 else
6678 {
6679 if (!(fntype
6680 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype))))
6681 cum->call_cookie |= CALL_LONG;
6682 }
6683 }
6684
6685 if (TARGET_DEBUG_ARG)
6686 {
6687 fprintf (stderr, "\ninit_cumulative_args:");
6688 if (fntype)
6689 {
6690 tree ret_type = TREE_TYPE (fntype);
6691 fprintf (stderr, " ret code = %s,",
6692 get_tree_code_name (TREE_CODE (ret_type)));
6693 }
6694
6695 if (cum->call_cookie & CALL_LONG)
6696 fprintf (stderr, " longcall,");
6697
6698 fprintf (stderr, " proto = %d, nargs = %d\n",
6699 cum->prototype, cum->nargs_prototype);
6700 }
6701
6702 #ifdef HAVE_AS_GNU_ATTRIBUTE
6703 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
6704 {
6705 cum->escapes = call_ABI_of_interest (fndecl);
6706 if (cum->escapes)
6707 {
6708 tree return_type;
6709
6710 if (fntype)
6711 {
6712 return_type = TREE_TYPE (fntype);
6713 return_mode = TYPE_MODE (return_type);
6714 }
6715 else
6716 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
6717
6718 if (return_type != NULL)
6719 {
6720 if (TREE_CODE (return_type) == RECORD_TYPE
6721 && TYPE_TRANSPARENT_AGGR (return_type))
6722 {
6723 return_type = TREE_TYPE (first_field (return_type));
6724 return_mode = TYPE_MODE (return_type);
6725 }
6726 if (AGGREGATE_TYPE_P (return_type)
6727 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
6728 <= 8))
6729 rs6000_returns_struct = true;
6730 }
6731 if (SCALAR_FLOAT_MODE_P (return_mode))
6732 {
6733 rs6000_passes_float = true;
6734 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
6735 && (FLOAT128_IBM_P (return_mode)
6736 || FLOAT128_IEEE_P (return_mode)
6737 || (return_type != NULL
6738 && (TYPE_MAIN_VARIANT (return_type)
6739 == long_double_type_node))))
6740 rs6000_passes_long_double = true;
6741
6742 /* Note if we passed or return a IEEE 128-bit type. We changed
6743 the mangling for these types, and we may need to make an alias
6744 with the old mangling. */
6745 if (FLOAT128_IEEE_P (return_mode))
6746 rs6000_passes_ieee128 = true;
6747 }
6748 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
6749 rs6000_passes_vector = true;
6750 }
6751 }
6752 #endif
6753
6754 if (fntype
6755 && !TARGET_ALTIVEC
6756 && TARGET_ALTIVEC_ABI
6757 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
6758 {
6759 error ("cannot return value in vector register because"
6760 " altivec instructions are disabled, use %qs"
6761 " to enable them", "-maltivec");
6762 }
6763 }
6764
6765
6766 /* On rs6000, function arguments are promoted, as are function return
6767 values. */
6768
6769 machine_mode
rs6000_promote_function_mode(const_tree type ATTRIBUTE_UNUSED,machine_mode mode,int * punsignedp ATTRIBUTE_UNUSED,const_tree,int for_return ATTRIBUTE_UNUSED)6770 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
6771 machine_mode mode,
6772 int *punsignedp ATTRIBUTE_UNUSED,
6773 const_tree, int for_return ATTRIBUTE_UNUSED)
6774 {
6775 PROMOTE_MODE (mode, *punsignedp, type);
6776
6777 return mode;
6778 }
6779
6780 /* Return true if TYPE must be passed on the stack and not in registers. */
6781
6782 bool
rs6000_must_pass_in_stack(const function_arg_info & arg)6783 rs6000_must_pass_in_stack (const function_arg_info &arg)
6784 {
6785 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
6786 return must_pass_in_stack_var_size (arg);
6787 else
6788 return must_pass_in_stack_var_size_or_pad (arg);
6789 }
6790
6791 static inline bool
is_complex_IBM_long_double(machine_mode mode)6792 is_complex_IBM_long_double (machine_mode mode)
6793 {
6794 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
6795 }
6796
6797 /* Whether ABI_V4 passes MODE args to a function in floating point
6798 registers. */
6799
6800 static bool
abi_v4_pass_in_fpr(machine_mode mode,bool named)6801 abi_v4_pass_in_fpr (machine_mode mode, bool named)
6802 {
6803 if (!TARGET_HARD_FLOAT)
6804 return false;
6805 if (mode == DFmode)
6806 return true;
6807 if (mode == SFmode && named)
6808 return true;
6809 /* ABI_V4 passes complex IBM long double in 8 gprs.
6810 Stupid, but we can't change the ABI now. */
6811 if (is_complex_IBM_long_double (mode))
6812 return false;
6813 if (FLOAT128_2REG_P (mode))
6814 return true;
6815 if (DECIMAL_FLOAT_MODE_P (mode))
6816 return true;
6817 return false;
6818 }
6819
6820 /* Implement TARGET_FUNCTION_ARG_PADDING.
6821
6822 For the AIX ABI structs are always stored left shifted in their
6823 argument slot. */
6824
6825 pad_direction
rs6000_function_arg_padding(machine_mode mode,const_tree type)6826 rs6000_function_arg_padding (machine_mode mode, const_tree type)
6827 {
6828 #ifndef AGGREGATE_PADDING_FIXED
6829 #define AGGREGATE_PADDING_FIXED 0
6830 #endif
6831 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
6832 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
6833 #endif
6834
6835 if (!AGGREGATE_PADDING_FIXED)
6836 {
6837 /* GCC used to pass structures of the same size as integer types as
6838 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
6839 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
6840 passed padded downward, except that -mstrict-align further
6841 muddied the water in that multi-component structures of 2 and 4
6842 bytes in size were passed padded upward.
6843
6844 The following arranges for best compatibility with previous
6845 versions of gcc, but removes the -mstrict-align dependency. */
6846 if (BYTES_BIG_ENDIAN)
6847 {
6848 HOST_WIDE_INT size = 0;
6849
6850 if (mode == BLKmode)
6851 {
6852 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
6853 size = int_size_in_bytes (type);
6854 }
6855 else
6856 size = GET_MODE_SIZE (mode);
6857
6858 if (size == 1 || size == 2 || size == 4)
6859 return PAD_DOWNWARD;
6860 }
6861 return PAD_UPWARD;
6862 }
6863
6864 if (AGGREGATES_PAD_UPWARD_ALWAYS)
6865 {
6866 if (type != 0 && AGGREGATE_TYPE_P (type))
6867 return PAD_UPWARD;
6868 }
6869
6870 /* Fall back to the default. */
6871 return default_function_arg_padding (mode, type);
6872 }
6873
6874 /* If defined, a C expression that gives the alignment boundary, in bits,
6875 of an argument with the specified mode and type. If it is not defined,
6876 PARM_BOUNDARY is used for all arguments.
6877
6878 V.4 wants long longs and doubles to be double word aligned. Just
6879 testing the mode size is a boneheaded way to do this as it means
6880 that other types such as complex int are also double word aligned.
6881 However, we're stuck with this because changing the ABI might break
6882 existing library interfaces.
6883
6884 Quadword align Altivec/VSX vectors.
6885 Quadword align large synthetic vector types. */
6886
6887 unsigned int
rs6000_function_arg_boundary(machine_mode mode,const_tree type)6888 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
6889 {
6890 machine_mode elt_mode;
6891 int n_elts;
6892
6893 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
6894
6895 if (DEFAULT_ABI == ABI_V4
6896 && (GET_MODE_SIZE (mode) == 8
6897 || (TARGET_HARD_FLOAT
6898 && !is_complex_IBM_long_double (mode)
6899 && FLOAT128_2REG_P (mode))))
6900 return 64;
6901 else if (FLOAT128_VECTOR_P (mode))
6902 return 128;
6903 else if (type && TREE_CODE (type) == VECTOR_TYPE
6904 && int_size_in_bytes (type) >= 8
6905 && int_size_in_bytes (type) < 16)
6906 return 64;
6907 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
6908 || (type && TREE_CODE (type) == VECTOR_TYPE
6909 && int_size_in_bytes (type) >= 16))
6910 return 128;
6911
6912 /* Aggregate types that need > 8 byte alignment are quadword-aligned
6913 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
6914 -mcompat-align-parm is used. */
6915 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
6916 || DEFAULT_ABI == ABI_ELFv2)
6917 && type && TYPE_ALIGN (type) > 64)
6918 {
6919 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
6920 or homogeneous float/vector aggregates here. We already handled
6921 vector aggregates above, but still need to check for float here. */
6922 bool aggregate_p = (AGGREGATE_TYPE_P (type)
6923 && !SCALAR_FLOAT_MODE_P (elt_mode));
6924
6925 /* We used to check for BLKmode instead of the above aggregate type
6926 check. Warn when this results in any difference to the ABI. */
6927 if (aggregate_p != (mode == BLKmode))
6928 {
6929 static bool warned;
6930 if (!warned && warn_psabi)
6931 {
6932 warned = true;
6933 inform (input_location,
6934 "the ABI of passing aggregates with %d-byte alignment"
6935 " has changed in GCC 5",
6936 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
6937 }
6938 }
6939
6940 if (aggregate_p)
6941 return 128;
6942 }
6943
6944 /* Similar for the Darwin64 ABI. Note that for historical reasons we
6945 implement the "aggregate type" check as a BLKmode check here; this
6946 means certain aggregate types are in fact not aligned. */
6947 if (TARGET_MACHO && rs6000_darwin64_abi
6948 && mode == BLKmode
6949 && type && TYPE_ALIGN (type) > 64)
6950 return 128;
6951
6952 return PARM_BOUNDARY;
6953 }
6954
6955 /* The offset in words to the start of the parameter save area. */
6956
6957 static unsigned int
rs6000_parm_offset(void)6958 rs6000_parm_offset (void)
6959 {
6960 return (DEFAULT_ABI == ABI_V4 ? 2
6961 : DEFAULT_ABI == ABI_ELFv2 ? 4
6962 : 6);
6963 }
6964
6965 /* For a function parm of MODE and TYPE, return the starting word in
6966 the parameter area. NWORDS of the parameter area are already used. */
6967
6968 static unsigned int
rs6000_parm_start(machine_mode mode,const_tree type,unsigned int nwords)6969 rs6000_parm_start (machine_mode mode, const_tree type,
6970 unsigned int nwords)
6971 {
6972 unsigned int align;
6973
6974 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
6975 return nwords + (-(rs6000_parm_offset () + nwords) & align);
6976 }
6977
6978 /* Compute the size (in words) of a function argument. */
6979
6980 static unsigned long
rs6000_arg_size(machine_mode mode,const_tree type)6981 rs6000_arg_size (machine_mode mode, const_tree type)
6982 {
6983 unsigned long size;
6984
6985 if (mode != BLKmode)
6986 size = GET_MODE_SIZE (mode);
6987 else
6988 size = int_size_in_bytes (type);
6989
6990 if (TARGET_32BIT)
6991 return (size + 3) >> 2;
6992 else
6993 return (size + 7) >> 3;
6994 }
6995
6996 /* Use this to flush pending int fields. */
6997
6998 static void
rs6000_darwin64_record_arg_advance_flush(CUMULATIVE_ARGS * cum,HOST_WIDE_INT bitpos,int final)6999 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
7000 HOST_WIDE_INT bitpos, int final)
7001 {
7002 unsigned int startbit, endbit;
7003 int intregs, intoffset;
7004
7005 /* Handle the situations where a float is taking up the first half
7006 of the GPR, and the other half is empty (typically due to
7007 alignment restrictions). We can detect this by a 8-byte-aligned
7008 int field, or by seeing that this is the final flush for this
7009 argument. Count the word and continue on. */
7010 if (cum->floats_in_gpr == 1
7011 && (cum->intoffset % 64 == 0
7012 || (cum->intoffset == -1 && final)))
7013 {
7014 cum->words++;
7015 cum->floats_in_gpr = 0;
7016 }
7017
7018 if (cum->intoffset == -1)
7019 return;
7020
7021 intoffset = cum->intoffset;
7022 cum->intoffset = -1;
7023 cum->floats_in_gpr = 0;
7024
7025 if (intoffset % BITS_PER_WORD != 0)
7026 {
7027 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
7028 if (!int_mode_for_size (bits, 0).exists ())
7029 {
7030 /* We couldn't find an appropriate mode, which happens,
7031 e.g., in packed structs when there are 3 bytes to load.
7032 Back intoffset back to the beginning of the word in this
7033 case. */
7034 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
7035 }
7036 }
7037
7038 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
7039 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
7040 intregs = (endbit - startbit) / BITS_PER_WORD;
7041 cum->words += intregs;
7042 /* words should be unsigned. */
7043 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
7044 {
7045 int pad = (endbit/BITS_PER_WORD) - cum->words;
7046 cum->words += pad;
7047 }
7048 }
7049
7050 /* The darwin64 ABI calls for us to recurse down through structs,
7051 looking for elements passed in registers. Unfortunately, we have
7052 to track int register count here also because of misalignments
7053 in powerpc alignment mode. */
7054
7055 static void
rs6000_darwin64_record_arg_advance_recurse(CUMULATIVE_ARGS * cum,const_tree type,HOST_WIDE_INT startbitpos)7056 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
7057 const_tree type,
7058 HOST_WIDE_INT startbitpos)
7059 {
7060 tree f;
7061
7062 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
7063 if (TREE_CODE (f) == FIELD_DECL)
7064 {
7065 HOST_WIDE_INT bitpos = startbitpos;
7066 tree ftype = TREE_TYPE (f);
7067 machine_mode mode;
7068 if (ftype == error_mark_node)
7069 continue;
7070 mode = TYPE_MODE (ftype);
7071
7072 if (DECL_SIZE (f) != 0
7073 && tree_fits_uhwi_p (bit_position (f)))
7074 bitpos += int_bit_position (f);
7075
7076 /* ??? FIXME: else assume zero offset. */
7077
7078 if (TREE_CODE (ftype) == RECORD_TYPE)
7079 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
7080 else if (USE_FP_FOR_ARG_P (cum, mode))
7081 {
7082 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
7083 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7084 cum->fregno += n_fpregs;
7085 /* Single-precision floats present a special problem for
7086 us, because they are smaller than an 8-byte GPR, and so
7087 the structure-packing rules combined with the standard
7088 varargs behavior mean that we want to pack float/float
7089 and float/int combinations into a single register's
7090 space. This is complicated by the arg advance flushing,
7091 which works on arbitrarily large groups of int-type
7092 fields. */
7093 if (mode == SFmode)
7094 {
7095 if (cum->floats_in_gpr == 1)
7096 {
7097 /* Two floats in a word; count the word and reset
7098 the float count. */
7099 cum->words++;
7100 cum->floats_in_gpr = 0;
7101 }
7102 else if (bitpos % 64 == 0)
7103 {
7104 /* A float at the beginning of an 8-byte word;
7105 count it and put off adjusting cum->words until
7106 we see if a arg advance flush is going to do it
7107 for us. */
7108 cum->floats_in_gpr++;
7109 }
7110 else
7111 {
7112 /* The float is at the end of a word, preceded
7113 by integer fields, so the arg advance flush
7114 just above has already set cum->words and
7115 everything is taken care of. */
7116 }
7117 }
7118 else
7119 cum->words += n_fpregs;
7120 }
7121 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
7122 {
7123 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7124 cum->vregno++;
7125 cum->words += 2;
7126 }
7127 else if (cum->intoffset == -1)
7128 cum->intoffset = bitpos;
7129 }
7130 }
7131
7132 /* Check for an item that needs to be considered specially under the darwin 64
7133 bit ABI. These are record types where the mode is BLK or the structure is
7134 8 bytes in size. */
7135 int
rs6000_darwin64_struct_check_p(machine_mode mode,const_tree type)7136 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
7137 {
7138 return rs6000_darwin64_abi
7139 && ((mode == BLKmode
7140 && TREE_CODE (type) == RECORD_TYPE
7141 && int_size_in_bytes (type) > 0)
7142 || (type && TREE_CODE (type) == RECORD_TYPE
7143 && int_size_in_bytes (type) == 8)) ? 1 : 0;
7144 }
7145
7146 /* Update the data in CUM to advance over an argument
7147 of mode MODE and data type TYPE.
7148 (TYPE is null for libcalls where that information may not be available.)
7149
7150 Note that for args passed by reference, function_arg will be called
7151 with MODE and TYPE set to that of the pointer to the arg, not the arg
7152 itself. */
7153
7154 static void
rs6000_function_arg_advance_1(CUMULATIVE_ARGS * cum,machine_mode mode,const_tree type,bool named,int depth)7155 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
7156 const_tree type, bool named, int depth)
7157 {
7158 machine_mode elt_mode;
7159 int n_elts;
7160
7161 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
7162
7163 /* Only tick off an argument if we're not recursing. */
7164 if (depth == 0)
7165 cum->nargs_prototype--;
7166
7167 #ifdef HAVE_AS_GNU_ATTRIBUTE
7168 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
7169 && cum->escapes)
7170 {
7171 if (SCALAR_FLOAT_MODE_P (mode))
7172 {
7173 rs6000_passes_float = true;
7174 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
7175 && (FLOAT128_IBM_P (mode)
7176 || FLOAT128_IEEE_P (mode)
7177 || (type != NULL
7178 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
7179 rs6000_passes_long_double = true;
7180
7181 /* Note if we passed or return a IEEE 128-bit type. We changed the
7182 mangling for these types, and we may need to make an alias with
7183 the old mangling. */
7184 if (FLOAT128_IEEE_P (mode))
7185 rs6000_passes_ieee128 = true;
7186 }
7187 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
7188 rs6000_passes_vector = true;
7189 }
7190 #endif
7191
7192 if (TARGET_ALTIVEC_ABI
7193 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
7194 || (type && TREE_CODE (type) == VECTOR_TYPE
7195 && int_size_in_bytes (type) == 16)))
7196 {
7197 bool stack = false;
7198
7199 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
7200 {
7201 cum->vregno += n_elts;
7202
7203 if (!TARGET_ALTIVEC)
7204 error ("cannot pass argument in vector register because"
7205 " altivec instructions are disabled, use %qs"
7206 " to enable them", "-maltivec");
7207
7208 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7209 even if it is going to be passed in a vector register.
7210 Darwin does the same for variable-argument functions. */
7211 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7212 && TARGET_64BIT)
7213 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
7214 stack = true;
7215 }
7216 else
7217 stack = true;
7218
7219 if (stack)
7220 {
7221 int align;
7222
7223 /* Vector parameters must be 16-byte aligned. In 32-bit
7224 mode this means we need to take into account the offset
7225 to the parameter save area. In 64-bit mode, they just
7226 have to start on an even word, since the parameter save
7227 area is 16-byte aligned. */
7228 if (TARGET_32BIT)
7229 align = -(rs6000_parm_offset () + cum->words) & 3;
7230 else
7231 align = cum->words & 1;
7232 cum->words += align + rs6000_arg_size (mode, type);
7233
7234 if (TARGET_DEBUG_ARG)
7235 {
7236 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
7237 cum->words, align);
7238 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
7239 cum->nargs_prototype, cum->prototype,
7240 GET_MODE_NAME (mode));
7241 }
7242 }
7243 }
7244 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7245 {
7246 int size = int_size_in_bytes (type);
7247 /* Variable sized types have size == -1 and are
7248 treated as if consisting entirely of ints.
7249 Pad to 16 byte boundary if needed. */
7250 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
7251 && (cum->words % 2) != 0)
7252 cum->words++;
7253 /* For varargs, we can just go up by the size of the struct. */
7254 if (!named)
7255 cum->words += (size + 7) / 8;
7256 else
7257 {
7258 /* It is tempting to say int register count just goes up by
7259 sizeof(type)/8, but this is wrong in a case such as
7260 { int; double; int; } [powerpc alignment]. We have to
7261 grovel through the fields for these too. */
7262 cum->intoffset = 0;
7263 cum->floats_in_gpr = 0;
7264 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
7265 rs6000_darwin64_record_arg_advance_flush (cum,
7266 size * BITS_PER_UNIT, 1);
7267 }
7268 if (TARGET_DEBUG_ARG)
7269 {
7270 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
7271 cum->words, TYPE_ALIGN (type), size);
7272 fprintf (stderr,
7273 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
7274 cum->nargs_prototype, cum->prototype,
7275 GET_MODE_NAME (mode));
7276 }
7277 }
7278 else if (DEFAULT_ABI == ABI_V4)
7279 {
7280 if (abi_v4_pass_in_fpr (mode, named))
7281 {
7282 /* _Decimal128 must use an even/odd register pair. This assumes
7283 that the register number is odd when fregno is odd. */
7284 if (mode == TDmode && (cum->fregno % 2) == 1)
7285 cum->fregno++;
7286
7287 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
7288 <= FP_ARG_V4_MAX_REG)
7289 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
7290 else
7291 {
7292 cum->fregno = FP_ARG_V4_MAX_REG + 1;
7293 if (mode == DFmode || FLOAT128_IBM_P (mode)
7294 || mode == DDmode || mode == TDmode)
7295 cum->words += cum->words & 1;
7296 cum->words += rs6000_arg_size (mode, type);
7297 }
7298 }
7299 else
7300 {
7301 int n_words = rs6000_arg_size (mode, type);
7302 int gregno = cum->sysv_gregno;
7303
7304 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
7305 As does any other 2 word item such as complex int due to a
7306 historical mistake. */
7307 if (n_words == 2)
7308 gregno += (1 - gregno) & 1;
7309
7310 /* Multi-reg args are not split between registers and stack. */
7311 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7312 {
7313 /* Long long is aligned on the stack. So are other 2 word
7314 items such as complex int due to a historical mistake. */
7315 if (n_words == 2)
7316 cum->words += cum->words & 1;
7317 cum->words += n_words;
7318 }
7319
7320 /* Note: continuing to accumulate gregno past when we've started
7321 spilling to the stack indicates the fact that we've started
7322 spilling to the stack to expand_builtin_saveregs. */
7323 cum->sysv_gregno = gregno + n_words;
7324 }
7325
7326 if (TARGET_DEBUG_ARG)
7327 {
7328 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
7329 cum->words, cum->fregno);
7330 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
7331 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
7332 fprintf (stderr, "mode = %4s, named = %d\n",
7333 GET_MODE_NAME (mode), named);
7334 }
7335 }
7336 else
7337 {
7338 int n_words = rs6000_arg_size (mode, type);
7339 int start_words = cum->words;
7340 int align_words = rs6000_parm_start (mode, type, start_words);
7341
7342 cum->words = align_words + n_words;
7343
7344 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
7345 {
7346 /* _Decimal128 must be passed in an even/odd float register pair.
7347 This assumes that the register number is odd when fregno is
7348 odd. */
7349 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
7350 cum->fregno++;
7351 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
7352 }
7353
7354 if (TARGET_DEBUG_ARG)
7355 {
7356 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
7357 cum->words, cum->fregno);
7358 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
7359 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
7360 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
7361 named, align_words - start_words, depth);
7362 }
7363 }
7364 }
7365
7366 void
rs6000_function_arg_advance(cumulative_args_t cum,const function_arg_info & arg)7367 rs6000_function_arg_advance (cumulative_args_t cum,
7368 const function_arg_info &arg)
7369 {
7370 rs6000_function_arg_advance_1 (get_cumulative_args (cum),
7371 arg.mode, arg.type, arg.named, 0);
7372 }
7373
7374 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
7375 structure between cum->intoffset and bitpos to integer registers. */
7376
7377 static void
rs6000_darwin64_record_arg_flush(CUMULATIVE_ARGS * cum,HOST_WIDE_INT bitpos,rtx rvec[],int * k)7378 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
7379 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
7380 {
7381 machine_mode mode;
7382 unsigned int regno;
7383 unsigned int startbit, endbit;
7384 int this_regno, intregs, intoffset;
7385 rtx reg;
7386
7387 if (cum->intoffset == -1)
7388 return;
7389
7390 intoffset = cum->intoffset;
7391 cum->intoffset = -1;
7392
7393 /* If this is the trailing part of a word, try to only load that
7394 much into the register. Otherwise load the whole register. Note
7395 that in the latter case we may pick up unwanted bits. It's not a
7396 problem at the moment but may wish to revisit. */
7397
7398 if (intoffset % BITS_PER_WORD != 0)
7399 {
7400 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
7401 if (!int_mode_for_size (bits, 0).exists (&mode))
7402 {
7403 /* We couldn't find an appropriate mode, which happens,
7404 e.g., in packed structs when there are 3 bytes to load.
7405 Back intoffset back to the beginning of the word in this
7406 case. */
7407 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
7408 mode = word_mode;
7409 }
7410 }
7411 else
7412 mode = word_mode;
7413
7414 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
7415 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
7416 intregs = (endbit - startbit) / BITS_PER_WORD;
7417 this_regno = cum->words + intoffset / BITS_PER_WORD;
7418
7419 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
7420 cum->use_stack = 1;
7421
7422 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
7423 if (intregs <= 0)
7424 return;
7425
7426 intoffset /= BITS_PER_UNIT;
7427 do
7428 {
7429 regno = GP_ARG_MIN_REG + this_regno;
7430 reg = gen_rtx_REG (mode, regno);
7431 rvec[(*k)++] =
7432 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
7433
7434 this_regno += 1;
7435 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
7436 mode = word_mode;
7437 intregs -= 1;
7438 }
7439 while (intregs > 0);
7440 }
7441
7442 /* Recursive workhorse for the following. */
7443
7444 static void
rs6000_darwin64_record_arg_recurse(CUMULATIVE_ARGS * cum,const_tree type,HOST_WIDE_INT startbitpos,rtx rvec[],int * k)7445 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
7446 HOST_WIDE_INT startbitpos, rtx rvec[],
7447 int *k)
7448 {
7449 tree f;
7450
7451 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
7452 if (TREE_CODE (f) == FIELD_DECL)
7453 {
7454 HOST_WIDE_INT bitpos = startbitpos;
7455 tree ftype = TREE_TYPE (f);
7456 machine_mode mode;
7457 if (ftype == error_mark_node)
7458 continue;
7459 mode = TYPE_MODE (ftype);
7460
7461 if (DECL_SIZE (f) != 0
7462 && tree_fits_uhwi_p (bit_position (f)))
7463 bitpos += int_bit_position (f);
7464
7465 /* ??? FIXME: else assume zero offset. */
7466
7467 if (TREE_CODE (ftype) == RECORD_TYPE)
7468 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
7469 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
7470 {
7471 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
7472 #if 0
7473 switch (mode)
7474 {
7475 case E_SCmode: mode = SFmode; break;
7476 case E_DCmode: mode = DFmode; break;
7477 case E_TCmode: mode = TFmode; break;
7478 default: break;
7479 }
7480 #endif
7481 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
7482 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
7483 {
7484 gcc_assert (cum->fregno == FP_ARG_MAX_REG
7485 && (mode == TFmode || mode == TDmode));
7486 /* Long double or _Decimal128 split over regs and memory. */
7487 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
7488 cum->use_stack=1;
7489 }
7490 rvec[(*k)++]
7491 = gen_rtx_EXPR_LIST (VOIDmode,
7492 gen_rtx_REG (mode, cum->fregno++),
7493 GEN_INT (bitpos / BITS_PER_UNIT));
7494 if (FLOAT128_2REG_P (mode))
7495 cum->fregno++;
7496 }
7497 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
7498 {
7499 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
7500 rvec[(*k)++]
7501 = gen_rtx_EXPR_LIST (VOIDmode,
7502 gen_rtx_REG (mode, cum->vregno++),
7503 GEN_INT (bitpos / BITS_PER_UNIT));
7504 }
7505 else if (cum->intoffset == -1)
7506 cum->intoffset = bitpos;
7507 }
7508 }
7509
7510 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
7511 the register(s) to be used for each field and subfield of a struct
7512 being passed by value, along with the offset of where the
7513 register's value may be found in the block. FP fields go in FP
7514 register, vector fields go in vector registers, and everything
7515 else goes in int registers, packed as in memory.
7516
7517 This code is also used for function return values. RETVAL indicates
7518 whether this is the case.
7519
7520 Much of this is taken from the SPARC V9 port, which has a similar
7521 calling convention. */
7522
7523 rtx
rs6000_darwin64_record_arg(CUMULATIVE_ARGS * orig_cum,const_tree type,bool named,bool retval)7524 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
7525 bool named, bool retval)
7526 {
7527 rtx rvec[FIRST_PSEUDO_REGISTER];
7528 int k = 1, kbase = 1;
7529 HOST_WIDE_INT typesize = int_size_in_bytes (type);
7530 /* This is a copy; modifications are not visible to our caller. */
7531 CUMULATIVE_ARGS copy_cum = *orig_cum;
7532 CUMULATIVE_ARGS *cum = ©_cum;
7533
7534 /* Pad to 16 byte boundary if needed. */
7535 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
7536 && (cum->words % 2) != 0)
7537 cum->words++;
7538
7539 cum->intoffset = 0;
7540 cum->use_stack = 0;
7541 cum->named = named;
7542
7543 /* Put entries into rvec[] for individual FP and vector fields, and
7544 for the chunks of memory that go in int regs. Note we start at
7545 element 1; 0 is reserved for an indication of using memory, and
7546 may or may not be filled in below. */
7547 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
7548 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
7549
7550 /* If any part of the struct went on the stack put all of it there.
7551 This hack is because the generic code for
7552 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
7553 parts of the struct are not at the beginning. */
7554 if (cum->use_stack)
7555 {
7556 if (retval)
7557 return NULL_RTX; /* doesn't go in registers at all */
7558 kbase = 0;
7559 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7560 }
7561 if (k > 1 || cum->use_stack)
7562 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
7563 else
7564 return NULL_RTX;
7565 }
7566
7567 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
7568
7569 static rtx
rs6000_mixed_function_arg(machine_mode mode,const_tree type,int align_words)7570 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
7571 int align_words)
7572 {
7573 int n_units;
7574 int i, k;
7575 rtx rvec[GP_ARG_NUM_REG + 1];
7576
7577 if (align_words >= GP_ARG_NUM_REG)
7578 return NULL_RTX;
7579
7580 n_units = rs6000_arg_size (mode, type);
7581
7582 /* Optimize the simple case where the arg fits in one gpr, except in
7583 the case of BLKmode due to assign_parms assuming that registers are
7584 BITS_PER_WORD wide. */
7585 if (n_units == 0
7586 || (n_units == 1 && mode != BLKmode))
7587 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
7588
7589 k = 0;
7590 if (align_words + n_units > GP_ARG_NUM_REG)
7591 /* Not all of the arg fits in gprs. Say that it goes in memory too,
7592 using a magic NULL_RTX component.
7593 This is not strictly correct. Only some of the arg belongs in
7594 memory, not all of it. However, the normal scheme using
7595 function_arg_partial_nregs can result in unusual subregs, eg.
7596 (subreg:SI (reg:DF) 4), which are not handled well. The code to
7597 store the whole arg to memory is often more efficient than code
7598 to store pieces, and we know that space is available in the right
7599 place for the whole arg. */
7600 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7601
7602 i = 0;
7603 do
7604 {
7605 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
7606 rtx off = GEN_INT (i++ * 4);
7607 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7608 }
7609 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
7610
7611 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
7612 }
7613
7614 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
7615 but must also be copied into the parameter save area starting at
7616 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
7617 to the GPRs and/or memory. Return the number of elements used. */
7618
7619 static int
rs6000_psave_function_arg(machine_mode mode,const_tree type,int align_words,rtx * rvec)7620 rs6000_psave_function_arg (machine_mode mode, const_tree type,
7621 int align_words, rtx *rvec)
7622 {
7623 int k = 0;
7624
7625 if (align_words < GP_ARG_NUM_REG)
7626 {
7627 int n_words = rs6000_arg_size (mode, type);
7628
7629 if (align_words + n_words > GP_ARG_NUM_REG
7630 || mode == BLKmode
7631 || (TARGET_32BIT && TARGET_POWERPC64))
7632 {
7633 /* If this is partially on the stack, then we only
7634 include the portion actually in registers here. */
7635 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
7636 int i = 0;
7637
7638 if (align_words + n_words > GP_ARG_NUM_REG)
7639 {
7640 /* Not all of the arg fits in gprs. Say that it goes in memory
7641 too, using a magic NULL_RTX component. Also see comment in
7642 rs6000_mixed_function_arg for why the normal
7643 function_arg_partial_nregs scheme doesn't work in this case. */
7644 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7645 }
7646
7647 do
7648 {
7649 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
7650 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
7651 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7652 }
7653 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
7654 }
7655 else
7656 {
7657 /* The whole arg fits in gprs. */
7658 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
7659 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
7660 }
7661 }
7662 else
7663 {
7664 /* It's entirely in memory. */
7665 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
7666 }
7667
7668 return k;
7669 }
7670
7671 /* RVEC is a vector of K components of an argument of mode MODE.
7672 Construct the final function_arg return value from it. */
7673
7674 static rtx
rs6000_finish_function_arg(machine_mode mode,rtx * rvec,int k)7675 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
7676 {
7677 gcc_assert (k >= 1);
7678
7679 /* Avoid returning a PARALLEL in the trivial cases. */
7680 if (k == 1)
7681 {
7682 if (XEXP (rvec[0], 0) == NULL_RTX)
7683 return NULL_RTX;
7684
7685 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
7686 return XEXP (rvec[0], 0);
7687 }
7688
7689 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
7690 }
7691
7692 /* Determine where to put an argument to a function.
7693 Value is zero to push the argument on the stack,
7694 or a hard register in which to store the argument.
7695
7696 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7697 the preceding args and about the function being called. It is
7698 not modified in this routine.
7699 ARG is a description of the argument.
7700
7701 On RS/6000 the first eight words of non-FP are normally in registers
7702 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
7703 Under V.4, the first 8 FP args are in registers.
7704
7705 If this is floating-point and no prototype is specified, we use
7706 both an FP and integer register (or possibly FP reg and stack). Library
7707 functions (when CALL_LIBCALL is set) always have the proper types for args,
7708 so we can pass the FP value just in one register. emit_library_function
7709 doesn't support PARALLEL anyway.
7710
7711 Note that for args passed by reference, function_arg will be called
7712 with ARG describing the pointer to the arg, not the arg itself. */
7713
7714 rtx
rs6000_function_arg(cumulative_args_t cum_v,const function_arg_info & arg)7715 rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
7716 {
7717 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7718 tree type = arg.type;
7719 machine_mode mode = arg.mode;
7720 bool named = arg.named;
7721 enum rs6000_abi abi = DEFAULT_ABI;
7722 machine_mode elt_mode;
7723 int n_elts;
7724
7725 /* We do not allow MMA types being used as function arguments. */
7726 if (mode == OOmode || mode == XOmode)
7727 {
7728 if (TYPE_CANONICAL (type) != NULL_TREE)
7729 type = TYPE_CANONICAL (type);
7730 error ("invalid use of MMA operand of type %qs as a function parameter",
7731 IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))));
7732 return NULL_RTX;
7733 }
7734
7735 /* Return a marker to indicate whether CR1 needs to set or clear the
7736 bit that V.4 uses to say fp args were passed in registers.
7737 Assume that we don't need the marker for software floating point,
7738 or compiler generated library calls. */
7739 if (arg.end_marker_p ())
7740 {
7741 if (abi == ABI_V4
7742 && (cum->call_cookie & CALL_LIBCALL) == 0
7743 && (cum->stdarg
7744 || (cum->nargs_prototype < 0
7745 && (cum->prototype || TARGET_NO_PROTOTYPE)))
7746 && TARGET_HARD_FLOAT)
7747 return GEN_INT (cum->call_cookie
7748 | ((cum->fregno == FP_ARG_MIN_REG)
7749 ? CALL_V4_SET_FP_ARGS
7750 : CALL_V4_CLEAR_FP_ARGS));
7751
7752 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
7753 }
7754
7755 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
7756
7757 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7758 {
7759 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
7760 if (rslt != NULL_RTX)
7761 return rslt;
7762 /* Else fall through to usual handling. */
7763 }
7764
7765 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
7766 {
7767 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
7768 rtx r, off;
7769 int i, k = 0;
7770
7771 /* Do we also need to pass this argument in the parameter save area?
7772 Library support functions for IEEE 128-bit are assumed to not need the
7773 value passed both in GPRs and in vector registers. */
7774 if (TARGET_64BIT && !cum->prototype
7775 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
7776 {
7777 int align_words = ROUND_UP (cum->words, 2);
7778 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
7779 }
7780
7781 /* Describe where this argument goes in the vector registers. */
7782 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
7783 {
7784 r = gen_rtx_REG (elt_mode, cum->vregno + i);
7785 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
7786 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7787 }
7788
7789 return rs6000_finish_function_arg (mode, rvec, k);
7790 }
7791 else if (TARGET_ALTIVEC_ABI
7792 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7793 || (type && TREE_CODE (type) == VECTOR_TYPE
7794 && int_size_in_bytes (type) == 16)))
7795 {
7796 if (named || abi == ABI_V4)
7797 return NULL_RTX;
7798 else
7799 {
7800 /* Vector parameters to varargs functions under AIX or Darwin
7801 get passed in memory and possibly also in GPRs. */
7802 int align, align_words, n_words;
7803 machine_mode part_mode;
7804
7805 /* Vector parameters must be 16-byte aligned. In 32-bit
7806 mode this means we need to take into account the offset
7807 to the parameter save area. In 64-bit mode, they just
7808 have to start on an even word, since the parameter save
7809 area is 16-byte aligned. */
7810 if (TARGET_32BIT)
7811 align = -(rs6000_parm_offset () + cum->words) & 3;
7812 else
7813 align = cum->words & 1;
7814 align_words = cum->words + align;
7815
7816 /* Out of registers? Memory, then. */
7817 if (align_words >= GP_ARG_NUM_REG)
7818 return NULL_RTX;
7819
7820 if (TARGET_32BIT && TARGET_POWERPC64)
7821 return rs6000_mixed_function_arg (mode, type, align_words);
7822
7823 /* The vector value goes in GPRs. Only the part of the
7824 value in GPRs is reported here. */
7825 part_mode = mode;
7826 n_words = rs6000_arg_size (mode, type);
7827 if (align_words + n_words > GP_ARG_NUM_REG)
7828 /* Fortunately, there are only two possibilities, the value
7829 is either wholly in GPRs or half in GPRs and half not. */
7830 part_mode = DImode;
7831
7832 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
7833 }
7834 }
7835
7836 else if (abi == ABI_V4)
7837 {
7838 if (abi_v4_pass_in_fpr (mode, named))
7839 {
7840 /* _Decimal128 must use an even/odd register pair. This assumes
7841 that the register number is odd when fregno is odd. */
7842 if (mode == TDmode && (cum->fregno % 2) == 1)
7843 cum->fregno++;
7844
7845 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
7846 <= FP_ARG_V4_MAX_REG)
7847 return gen_rtx_REG (mode, cum->fregno);
7848 else
7849 return NULL_RTX;
7850 }
7851 else
7852 {
7853 int n_words = rs6000_arg_size (mode, type);
7854 int gregno = cum->sysv_gregno;
7855
7856 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
7857 As does any other 2 word item such as complex int due to a
7858 historical mistake. */
7859 if (n_words == 2)
7860 gregno += (1 - gregno) & 1;
7861
7862 /* Multi-reg args are not split between registers and stack. */
7863 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7864 return NULL_RTX;
7865
7866 if (TARGET_32BIT && TARGET_POWERPC64)
7867 return rs6000_mixed_function_arg (mode, type,
7868 gregno - GP_ARG_MIN_REG);
7869 return gen_rtx_REG (mode, gregno);
7870 }
7871 }
7872 else
7873 {
7874 int align_words = rs6000_parm_start (mode, type, cum->words);
7875
7876 /* _Decimal128 must be passed in an even/odd float register pair.
7877 This assumes that the register number is odd when fregno is odd. */
7878 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
7879 cum->fregno++;
7880
7881 if (USE_FP_FOR_ARG_P (cum, elt_mode)
7882 && !(TARGET_AIX && !TARGET_ELF
7883 && type != NULL && AGGREGATE_TYPE_P (type)))
7884 {
7885 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
7886 rtx r, off;
7887 int i, k = 0;
7888 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
7889 int fpr_words;
7890
7891 /* Do we also need to pass this argument in the parameter
7892 save area? */
7893 if (type && (cum->nargs_prototype <= 0
7894 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7895 && TARGET_XL_COMPAT
7896 && align_words >= GP_ARG_NUM_REG)))
7897 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
7898
7899 /* Describe where this argument goes in the fprs. */
7900 for (i = 0; i < n_elts
7901 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
7902 {
7903 /* Check if the argument is split over registers and memory.
7904 This can only ever happen for long double or _Decimal128;
7905 complex types are handled via split_complex_arg. */
7906 machine_mode fmode = elt_mode;
7907 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
7908 {
7909 gcc_assert (FLOAT128_2REG_P (fmode));
7910 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
7911 }
7912
7913 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
7914 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
7915 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7916 }
7917
7918 /* If there were not enough FPRs to hold the argument, the rest
7919 usually goes into memory. However, if the current position
7920 is still within the register parameter area, a portion may
7921 actually have to go into GPRs.
7922
7923 Note that it may happen that the portion of the argument
7924 passed in the first "half" of the first GPR was already
7925 passed in the last FPR as well.
7926
7927 For unnamed arguments, we already set up GPRs to cover the
7928 whole argument in rs6000_psave_function_arg, so there is
7929 nothing further to do at this point. */
7930 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
7931 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
7932 && cum->nargs_prototype > 0)
7933 {
7934 static bool warned;
7935
7936 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
7937 int n_words = rs6000_arg_size (mode, type);
7938
7939 align_words += fpr_words;
7940 n_words -= fpr_words;
7941
7942 do
7943 {
7944 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
7945 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
7946 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
7947 }
7948 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
7949
7950 if (!warned && warn_psabi)
7951 {
7952 warned = true;
7953 inform (input_location,
7954 "the ABI of passing homogeneous %<float%> aggregates"
7955 " has changed in GCC 5");
7956 }
7957 }
7958
7959 return rs6000_finish_function_arg (mode, rvec, k);
7960 }
7961 else if (align_words < GP_ARG_NUM_REG)
7962 {
7963 if (TARGET_32BIT && TARGET_POWERPC64)
7964 return rs6000_mixed_function_arg (mode, type, align_words);
7965
7966 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
7967 }
7968 else
7969 return NULL_RTX;
7970 }
7971 }
7972
7973 /* For an arg passed partly in registers and partly in memory, this is
7974 the number of bytes passed in registers. For args passed entirely in
7975 registers or entirely in memory, zero. When an arg is described by a
7976 PARALLEL, perhaps using more than one register type, this function
7977 returns the number of bytes used by the first element of the PARALLEL. */
7978
7979 int
rs6000_arg_partial_bytes(cumulative_args_t cum_v,const function_arg_info & arg)7980 rs6000_arg_partial_bytes (cumulative_args_t cum_v,
7981 const function_arg_info &arg)
7982 {
7983 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7984 bool passed_in_gprs = true;
7985 int ret = 0;
7986 int align_words;
7987 machine_mode elt_mode;
7988 int n_elts;
7989
7990 rs6000_discover_homogeneous_aggregate (arg.mode, arg.type,
7991 &elt_mode, &n_elts);
7992
7993 if (DEFAULT_ABI == ABI_V4)
7994 return 0;
7995
7996 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, arg.named))
7997 {
7998 /* If we are passing this arg in the fixed parameter save area (gprs or
7999 memory) as well as VRs, we do not use the partial bytes mechanism;
8000 instead, rs6000_function_arg will return a PARALLEL including a memory
8001 element as necessary. Library support functions for IEEE 128-bit are
8002 assumed to not need the value passed both in GPRs and in vector
8003 registers. */
8004 if (TARGET_64BIT && !cum->prototype
8005 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
8006 return 0;
8007
8008 /* Otherwise, we pass in VRs only. Check for partial copies. */
8009 passed_in_gprs = false;
8010 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
8011 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
8012 }
8013
8014 /* In this complicated case we just disable the partial_nregs code. */
8015 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (arg.mode, arg.type))
8016 return 0;
8017
8018 align_words = rs6000_parm_start (arg.mode, arg.type, cum->words);
8019
8020 if (USE_FP_FOR_ARG_P (cum, elt_mode)
8021 && !(TARGET_AIX && !TARGET_ELF && arg.aggregate_type_p ()))
8022 {
8023 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
8024
8025 /* If we are passing this arg in the fixed parameter save area
8026 (gprs or memory) as well as FPRs, we do not use the partial
8027 bytes mechanism; instead, rs6000_function_arg will return a
8028 PARALLEL including a memory element as necessary. */
8029 if (arg.type
8030 && (cum->nargs_prototype <= 0
8031 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
8032 && TARGET_XL_COMPAT
8033 && align_words >= GP_ARG_NUM_REG)))
8034 return 0;
8035
8036 /* Otherwise, we pass in FPRs only. Check for partial copies. */
8037 passed_in_gprs = false;
8038 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
8039 {
8040 /* Compute number of bytes / words passed in FPRs. If there
8041 is still space available in the register parameter area
8042 *after* that amount, a part of the argument will be passed
8043 in GPRs. In that case, the total amount passed in any
8044 registers is equal to the amount that would have been passed
8045 in GPRs if everything were passed there, so we fall back to
8046 the GPR code below to compute the appropriate value. */
8047 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
8048 * MIN (8, GET_MODE_SIZE (elt_mode)));
8049 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
8050
8051 if (align_words + fpr_words < GP_ARG_NUM_REG)
8052 passed_in_gprs = true;
8053 else
8054 ret = fpr;
8055 }
8056 }
8057
8058 if (passed_in_gprs
8059 && align_words < GP_ARG_NUM_REG
8060 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (arg.mode, arg.type))
8061 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
8062
8063 if (ret != 0 && TARGET_DEBUG_ARG)
8064 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
8065
8066 return ret;
8067 }
8068
8069 /* A C expression that indicates when an argument must be passed by
8070 reference. If nonzero for an argument, a copy of that argument is
8071 made in memory and a pointer to the argument is passed instead of
8072 the argument itself. The pointer is passed in whatever way is
8073 appropriate for passing a pointer to that type.
8074
8075 Under V.4, aggregates and long double are passed by reference.
8076
8077 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8078 reference unless the AltiVec vector extension ABI is in force.
8079
8080 As an extension to all ABIs, variable sized types are passed by
8081 reference. */
8082
8083 bool
rs6000_pass_by_reference(cumulative_args_t,const function_arg_info & arg)8084 rs6000_pass_by_reference (cumulative_args_t, const function_arg_info &arg)
8085 {
8086 if (!arg.type)
8087 return 0;
8088
8089 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
8090 && FLOAT128_IEEE_P (TYPE_MODE (arg.type)))
8091 {
8092 if (TARGET_DEBUG_ARG)
8093 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
8094 return 1;
8095 }
8096
8097 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (arg.type))
8098 {
8099 if (TARGET_DEBUG_ARG)
8100 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
8101 return 1;
8102 }
8103
8104 if (int_size_in_bytes (arg.type) < 0)
8105 {
8106 if (TARGET_DEBUG_ARG)
8107 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
8108 return 1;
8109 }
8110
8111 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8112 modes only exist for GCC vector types if -maltivec. */
8113 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (arg.mode))
8114 {
8115 if (TARGET_DEBUG_ARG)
8116 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
8117 return 1;
8118 }
8119
8120 /* Pass synthetic vectors in memory. */
8121 if (TREE_CODE (arg.type) == VECTOR_TYPE
8122 && int_size_in_bytes (arg.type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
8123 {
8124 static bool warned_for_pass_big_vectors = false;
8125 if (TARGET_DEBUG_ARG)
8126 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
8127 if (!warned_for_pass_big_vectors)
8128 {
8129 warning (OPT_Wpsabi, "GCC vector passed by reference: "
8130 "non-standard ABI extension with no compatibility "
8131 "guarantee");
8132 warned_for_pass_big_vectors = true;
8133 }
8134 return 1;
8135 }
8136
8137 return 0;
8138 }
8139
8140 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
8141 already processes. Return true if the parameter must be passed
8142 (fully or partially) on the stack. */
8143
8144 static bool
rs6000_parm_needs_stack(cumulative_args_t args_so_far,tree type)8145 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
8146 {
8147 int unsignedp;
8148 rtx entry_parm;
8149
8150 /* Catch errors. */
8151 if (type == NULL || type == error_mark_node)
8152 return true;
8153
8154 /* Handle types with no storage requirement. */
8155 if (TYPE_MODE (type) == VOIDmode)
8156 return false;
8157
8158 /* Handle complex types. */
8159 if (TREE_CODE (type) == COMPLEX_TYPE)
8160 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
8161 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
8162
8163 /* Handle transparent aggregates. */
8164 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
8165 && TYPE_TRANSPARENT_AGGR (type))
8166 type = TREE_TYPE (first_field (type));
8167
8168 /* See if this arg was passed by invisible reference. */
8169 function_arg_info arg (type, /*named=*/true);
8170 apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg);
8171
8172 /* Find mode as it is passed by the ABI. */
8173 unsignedp = TYPE_UNSIGNED (type);
8174 arg.mode = promote_mode (arg.type, arg.mode, &unsignedp);
8175
8176 /* If we must pass in stack, we need a stack. */
8177 if (rs6000_must_pass_in_stack (arg))
8178 return true;
8179
8180 /* If there is no incoming register, we need a stack. */
8181 entry_parm = rs6000_function_arg (args_so_far, arg);
8182 if (entry_parm == NULL)
8183 return true;
8184
8185 /* Likewise if we need to pass both in registers and on the stack. */
8186 if (GET_CODE (entry_parm) == PARALLEL
8187 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
8188 return true;
8189
8190 /* Also true if we're partially in registers and partially not. */
8191 if (rs6000_arg_partial_bytes (args_so_far, arg) != 0)
8192 return true;
8193
8194 /* Update info on where next arg arrives in registers. */
8195 rs6000_function_arg_advance (args_so_far, arg);
8196 return false;
8197 }
8198
8199 /* Return true if FUN has no prototype, has a variable argument
8200 list, or passes any parameter in memory. */
8201
8202 static bool
rs6000_function_parms_need_stack(tree fun,bool incoming)8203 rs6000_function_parms_need_stack (tree fun, bool incoming)
8204 {
8205 tree fntype, result;
8206 CUMULATIVE_ARGS args_so_far_v;
8207 cumulative_args_t args_so_far;
8208
8209 if (!fun)
8210 /* Must be a libcall, all of which only use reg parms. */
8211 return false;
8212
8213 fntype = fun;
8214 if (!TYPE_P (fun))
8215 fntype = TREE_TYPE (fun);
8216
8217 /* Varargs functions need the parameter save area. */
8218 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
8219 return true;
8220
8221 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
8222 args_so_far = pack_cumulative_args (&args_so_far_v);
8223
8224 /* When incoming, we will have been passed the function decl.
8225 It is necessary to use the decl to handle K&R style functions,
8226 where TYPE_ARG_TYPES may not be available. */
8227 if (incoming)
8228 {
8229 gcc_assert (DECL_P (fun));
8230 result = DECL_RESULT (fun);
8231 }
8232 else
8233 result = TREE_TYPE (fntype);
8234
8235 if (result && aggregate_value_p (result, fntype))
8236 {
8237 if (!TYPE_P (result))
8238 result = TREE_TYPE (result);
8239 result = build_pointer_type (result);
8240 rs6000_parm_needs_stack (args_so_far, result);
8241 }
8242
8243 if (incoming)
8244 {
8245 tree parm;
8246
8247 for (parm = DECL_ARGUMENTS (fun);
8248 parm && parm != void_list_node;
8249 parm = TREE_CHAIN (parm))
8250 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
8251 return true;
8252 }
8253 else
8254 {
8255 function_args_iterator args_iter;
8256 tree arg_type;
8257
8258 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
8259 if (rs6000_parm_needs_stack (args_so_far, arg_type))
8260 return true;
8261 }
8262
8263 return false;
8264 }
8265
8266 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
8267 usually a constant depending on the ABI. However, in the ELFv2 ABI
8268 the register parameter area is optional when calling a function that
8269 has a prototype is scope, has no variable argument list, and passes
8270 all parameters in registers. */
8271
8272 int
rs6000_reg_parm_stack_space(tree fun,bool incoming)8273 rs6000_reg_parm_stack_space (tree fun, bool incoming)
8274 {
8275 int reg_parm_stack_space;
8276
8277 switch (DEFAULT_ABI)
8278 {
8279 default:
8280 reg_parm_stack_space = 0;
8281 break;
8282
8283 case ABI_AIX:
8284 case ABI_DARWIN:
8285 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
8286 break;
8287
8288 case ABI_ELFv2:
8289 /* ??? Recomputing this every time is a bit expensive. Is there
8290 a place to cache this information? */
8291 if (rs6000_function_parms_need_stack (fun, incoming))
8292 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
8293 else
8294 reg_parm_stack_space = 0;
8295 break;
8296 }
8297
8298 return reg_parm_stack_space;
8299 }
8300
8301 static void
rs6000_move_block_from_reg(int regno,rtx x,int nregs)8302 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
8303 {
8304 int i;
8305 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
8306
8307 if (nregs == 0)
8308 return;
8309
8310 for (i = 0; i < nregs; i++)
8311 {
8312 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
8313 if (reload_completed)
8314 {
8315 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
8316 tem = NULL_RTX;
8317 else
8318 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
8319 i * GET_MODE_SIZE (reg_mode));
8320 }
8321 else
8322 tem = replace_equiv_address (tem, XEXP (tem, 0));
8323
8324 gcc_assert (tem);
8325
8326 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
8327 }
8328 }
8329
8330 /* Perform any needed actions needed for a function that is receiving a
8331 variable number of arguments.
8332
8333 CUM is as above.
8334
8335 ARG is the last named argument.
8336
8337 PRETEND_SIZE is a variable that should be set to the amount of stack
8338 that must be pushed by the prolog to pretend that our caller pushed
8339 it.
8340
8341 Normally, this macro will push all remaining incoming registers on the
8342 stack and set PRETEND_SIZE to the length of the registers pushed. */
8343
8344 void
setup_incoming_varargs(cumulative_args_t cum,const function_arg_info & arg,int * pretend_size ATTRIBUTE_UNUSED,int no_rtl)8345 setup_incoming_varargs (cumulative_args_t cum,
8346 const function_arg_info &arg,
8347 int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
8348 {
8349 CUMULATIVE_ARGS next_cum;
8350 int reg_size = TARGET_32BIT ? 4 : 8;
8351 rtx save_area = NULL_RTX, mem;
8352 int first_reg_offset;
8353 alias_set_type set;
8354
8355 /* Skip the last named argument. */
8356 next_cum = *get_cumulative_args (cum);
8357 rs6000_function_arg_advance_1 (&next_cum, arg.mode, arg.type, arg.named, 0);
8358
8359 if (DEFAULT_ABI == ABI_V4)
8360 {
8361 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
8362
8363 if (! no_rtl)
8364 {
8365 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
8366 HOST_WIDE_INT offset = 0;
8367
8368 /* Try to optimize the size of the varargs save area.
8369 The ABI requires that ap.reg_save_area is doubleword
8370 aligned, but we don't need to allocate space for all
8371 the bytes, only those to which we actually will save
8372 anything. */
8373 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
8374 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
8375 if (TARGET_HARD_FLOAT
8376 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8377 && cfun->va_list_fpr_size)
8378 {
8379 if (gpr_reg_num)
8380 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
8381 * UNITS_PER_FP_WORD;
8382 if (cfun->va_list_fpr_size
8383 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8384 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
8385 else
8386 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8387 * UNITS_PER_FP_WORD;
8388 }
8389 if (gpr_reg_num)
8390 {
8391 offset = -((first_reg_offset * reg_size) & ~7);
8392 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
8393 {
8394 gpr_reg_num = cfun->va_list_gpr_size;
8395 if (reg_size == 4 && (first_reg_offset & 1))
8396 gpr_reg_num++;
8397 }
8398 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
8399 }
8400 else if (fpr_size)
8401 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
8402 * UNITS_PER_FP_WORD
8403 - (int) (GP_ARG_NUM_REG * reg_size);
8404
8405 if (gpr_size + fpr_size)
8406 {
8407 rtx reg_save_area
8408 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
8409 gcc_assert (MEM_P (reg_save_area));
8410 reg_save_area = XEXP (reg_save_area, 0);
8411 if (GET_CODE (reg_save_area) == PLUS)
8412 {
8413 gcc_assert (XEXP (reg_save_area, 0)
8414 == virtual_stack_vars_rtx);
8415 gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1)));
8416 offset += INTVAL (XEXP (reg_save_area, 1));
8417 }
8418 else
8419 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
8420 }
8421
8422 cfun->machine->varargs_save_offset = offset;
8423 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
8424 }
8425 }
8426 else
8427 {
8428 first_reg_offset = next_cum.words;
8429 save_area = crtl->args.internal_arg_pointer;
8430
8431 if (targetm.calls.must_pass_in_stack (arg))
8432 first_reg_offset += rs6000_arg_size (TYPE_MODE (arg.type), arg.type);
8433 }
8434
8435 set = get_varargs_alias_set ();
8436 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
8437 && cfun->va_list_gpr_size)
8438 {
8439 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
8440
8441 if (va_list_gpr_counter_field)
8442 /* V4 va_list_gpr_size counts number of registers needed. */
8443 n_gpr = cfun->va_list_gpr_size;
8444 else
8445 /* char * va_list instead counts number of bytes needed. */
8446 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
8447
8448 if (nregs > n_gpr)
8449 nregs = n_gpr;
8450
8451 mem = gen_rtx_MEM (BLKmode,
8452 plus_constant (Pmode, save_area,
8453 first_reg_offset * reg_size));
8454 MEM_NOTRAP_P (mem) = 1;
8455 set_mem_alias_set (mem, set);
8456 set_mem_align (mem, BITS_PER_WORD);
8457
8458 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
8459 nregs);
8460 }
8461
8462 /* Save FP registers if needed. */
8463 if (DEFAULT_ABI == ABI_V4
8464 && TARGET_HARD_FLOAT
8465 && ! no_rtl
8466 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8467 && cfun->va_list_fpr_size)
8468 {
8469 int fregno = next_cum.fregno, nregs;
8470 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
8471 rtx lab = gen_label_rtx ();
8472 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
8473 * UNITS_PER_FP_WORD);
8474
8475 emit_jump_insn
8476 (gen_rtx_SET (pc_rtx,
8477 gen_rtx_IF_THEN_ELSE (VOIDmode,
8478 gen_rtx_NE (VOIDmode, cr1,
8479 const0_rtx),
8480 gen_rtx_LABEL_REF (VOIDmode, lab),
8481 pc_rtx)));
8482
8483 for (nregs = 0;
8484 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
8485 fregno++, off += UNITS_PER_FP_WORD, nregs++)
8486 {
8487 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
8488 plus_constant (Pmode, save_area, off));
8489 MEM_NOTRAP_P (mem) = 1;
8490 set_mem_alias_set (mem, set);
8491 set_mem_align (mem, GET_MODE_ALIGNMENT (
8492 TARGET_HARD_FLOAT ? DFmode : SFmode));
8493 emit_move_insn (mem, gen_rtx_REG (
8494 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
8495 }
8496
8497 emit_label (lab);
8498 }
8499 }
8500
8501 /* Create the va_list data type. */
8502
8503 tree
rs6000_build_builtin_va_list(void)8504 rs6000_build_builtin_va_list (void)
8505 {
8506 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
8507
8508 /* For AIX, prefer 'char *' because that's what the system
8509 header files like. */
8510 if (DEFAULT_ABI != ABI_V4)
8511 return build_pointer_type (char_type_node);
8512
8513 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
8514 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
8515 get_identifier ("__va_list_tag"), record);
8516
8517 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
8518 unsigned_char_type_node);
8519 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
8520 unsigned_char_type_node);
8521 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
8522 every user file. */
8523 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8524 get_identifier ("reserved"), short_unsigned_type_node);
8525 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8526 get_identifier ("overflow_arg_area"),
8527 ptr_type_node);
8528 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
8529 get_identifier ("reg_save_area"),
8530 ptr_type_node);
8531
8532 va_list_gpr_counter_field = f_gpr;
8533 va_list_fpr_counter_field = f_fpr;
8534
8535 DECL_FIELD_CONTEXT (f_gpr) = record;
8536 DECL_FIELD_CONTEXT (f_fpr) = record;
8537 DECL_FIELD_CONTEXT (f_res) = record;
8538 DECL_FIELD_CONTEXT (f_ovf) = record;
8539 DECL_FIELD_CONTEXT (f_sav) = record;
8540
8541 TYPE_STUB_DECL (record) = type_decl;
8542 TYPE_NAME (record) = type_decl;
8543 TYPE_FIELDS (record) = f_gpr;
8544 DECL_CHAIN (f_gpr) = f_fpr;
8545 DECL_CHAIN (f_fpr) = f_res;
8546 DECL_CHAIN (f_res) = f_ovf;
8547 DECL_CHAIN (f_ovf) = f_sav;
8548
8549 layout_type (record);
8550
8551 /* The correct type is an array type of one element. */
8552 return build_array_type (record, build_index_type (size_zero_node));
8553 }
8554
8555 /* Implement va_start. */
8556
8557 void
rs6000_va_start(tree valist,rtx nextarg)8558 rs6000_va_start (tree valist, rtx nextarg)
8559 {
8560 HOST_WIDE_INT words, n_gpr, n_fpr;
8561 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
8562 tree gpr, fpr, ovf, sav, t;
8563
8564 /* Only SVR4 needs something special. */
8565 if (DEFAULT_ABI != ABI_V4)
8566 {
8567 std_expand_builtin_va_start (valist, nextarg);
8568 return;
8569 }
8570
8571 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8572 f_fpr = DECL_CHAIN (f_gpr);
8573 f_res = DECL_CHAIN (f_fpr);
8574 f_ovf = DECL_CHAIN (f_res);
8575 f_sav = DECL_CHAIN (f_ovf);
8576
8577 valist = build_simple_mem_ref (valist);
8578 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8579 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
8580 f_fpr, NULL_TREE);
8581 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
8582 f_ovf, NULL_TREE);
8583 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
8584 f_sav, NULL_TREE);
8585
8586 /* Count number of gp and fp argument registers used. */
8587 words = crtl->args.info.words;
8588 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
8589 GP_ARG_NUM_REG);
8590 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
8591 FP_ARG_NUM_REG);
8592
8593 if (TARGET_DEBUG_ARG)
8594 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
8595 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
8596 words, n_gpr, n_fpr);
8597
8598 if (cfun->va_list_gpr_size)
8599 {
8600 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8601 build_int_cst (NULL_TREE, n_gpr));
8602 TREE_SIDE_EFFECTS (t) = 1;
8603 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8604 }
8605
8606 if (cfun->va_list_fpr_size)
8607 {
8608 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8609 build_int_cst (NULL_TREE, n_fpr));
8610 TREE_SIDE_EFFECTS (t) = 1;
8611 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8612
8613 #ifdef HAVE_AS_GNU_ATTRIBUTE
8614 if (call_ABI_of_interest (cfun->decl))
8615 rs6000_passes_float = true;
8616 #endif
8617 }
8618
8619 /* Find the overflow area. */
8620 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
8621 if (words != 0)
8622 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
8623 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8624 TREE_SIDE_EFFECTS (t) = 1;
8625 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8626
8627 /* If there were no va_arg invocations, don't set up the register
8628 save area. */
8629 if (!cfun->va_list_gpr_size
8630 && !cfun->va_list_fpr_size
8631 && n_gpr < GP_ARG_NUM_REG
8632 && n_fpr < FP_ARG_V4_MAX_REG)
8633 return;
8634
8635 /* Find the register save area. */
8636 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
8637 if (cfun->machine->varargs_save_offset)
8638 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
8639 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8640 TREE_SIDE_EFFECTS (t) = 1;
8641 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8642 }
8643
8644 /* Implement va_arg. */
8645
8646 tree
rs6000_gimplify_va_arg(tree valist,tree type,gimple_seq * pre_p,gimple_seq * post_p)8647 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8648 gimple_seq *post_p)
8649 {
8650 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
8651 tree gpr, fpr, ovf, sav, reg, t, u;
8652 int size, rsize, n_reg, sav_ofs, sav_scale;
8653 tree lab_false, lab_over, addr;
8654 int align;
8655 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
8656 int regalign = 0;
8657 gimple *stmt;
8658
8659 if (pass_va_arg_by_reference (type))
8660 {
8661 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
8662 return build_va_arg_indirect_ref (t);
8663 }
8664
8665 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
8666 earlier version of gcc, with the property that it always applied alignment
8667 adjustments to the va-args (even for zero-sized types). The cheapest way
8668 to deal with this is to replicate the effect of the part of
8669 std_gimplify_va_arg_expr that carries out the align adjust, for the case
8670 of relevance.
8671 We don't need to check for pass-by-reference because of the test above.
8672 We can return a simplifed answer, since we know there's no offset to add. */
8673
8674 if (((TARGET_MACHO
8675 && rs6000_darwin64_abi)
8676 || DEFAULT_ABI == ABI_ELFv2
8677 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
8678 && integer_zerop (TYPE_SIZE (type)))
8679 {
8680 unsigned HOST_WIDE_INT align, boundary;
8681 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
8682 align = PARM_BOUNDARY / BITS_PER_UNIT;
8683 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
8684 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
8685 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
8686 boundary /= BITS_PER_UNIT;
8687 if (boundary > align)
8688 {
8689 tree t ;
8690 /* This updates arg ptr by the amount that would be necessary
8691 to align the zero-sized (but not zero-alignment) item. */
8692 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
8693 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
8694 gimplify_and_add (t, pre_p);
8695
8696 t = fold_convert (sizetype, valist_tmp);
8697 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
8698 fold_convert (TREE_TYPE (valist),
8699 fold_build2 (BIT_AND_EXPR, sizetype, t,
8700 size_int (-boundary))));
8701 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
8702 gimplify_and_add (t, pre_p);
8703 }
8704 /* Since it is zero-sized there's no increment for the item itself. */
8705 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
8706 return build_va_arg_indirect_ref (valist_tmp);
8707 }
8708
8709 if (DEFAULT_ABI != ABI_V4)
8710 {
8711 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
8712 {
8713 tree elem_type = TREE_TYPE (type);
8714 machine_mode elem_mode = TYPE_MODE (elem_type);
8715 int elem_size = GET_MODE_SIZE (elem_mode);
8716
8717 if (elem_size < UNITS_PER_WORD)
8718 {
8719 tree real_part, imag_part;
8720 gimple_seq post = NULL;
8721
8722 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
8723 &post);
8724 /* Copy the value into a temporary, lest the formal temporary
8725 be reused out from under us. */
8726 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
8727 gimple_seq_add_seq (pre_p, post);
8728
8729 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
8730 post_p);
8731
8732 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
8733 }
8734 }
8735
8736 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
8737 }
8738
8739 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8740 f_fpr = DECL_CHAIN (f_gpr);
8741 f_res = DECL_CHAIN (f_fpr);
8742 f_ovf = DECL_CHAIN (f_res);
8743 f_sav = DECL_CHAIN (f_ovf);
8744
8745 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8746 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
8747 f_fpr, NULL_TREE);
8748 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
8749 f_ovf, NULL_TREE);
8750 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
8751 f_sav, NULL_TREE);
8752
8753 size = int_size_in_bytes (type);
8754 rsize = (size + 3) / 4;
8755 int pad = 4 * rsize - size;
8756 align = 1;
8757
8758 machine_mode mode = TYPE_MODE (type);
8759 if (abi_v4_pass_in_fpr (mode, false))
8760 {
8761 /* FP args go in FP registers, if present. */
8762 reg = fpr;
8763 n_reg = (size + 7) / 8;
8764 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
8765 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
8766 if (mode != SFmode && mode != SDmode)
8767 align = 8;
8768 }
8769 else
8770 {
8771 /* Otherwise into GP registers. */
8772 reg = gpr;
8773 n_reg = rsize;
8774 sav_ofs = 0;
8775 sav_scale = 4;
8776 if (n_reg == 2)
8777 align = 8;
8778 }
8779
8780 /* Pull the value out of the saved registers.... */
8781
8782 lab_over = NULL;
8783 addr = create_tmp_var (ptr_type_node, "addr");
8784
8785 /* AltiVec vectors never go in registers when -mabi=altivec. */
8786 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8787 align = 16;
8788 else
8789 {
8790 lab_false = create_artificial_label (input_location);
8791 lab_over = create_artificial_label (input_location);
8792
8793 /* Long long is aligned in the registers. As are any other 2 gpr
8794 item such as complex int due to a historical mistake. */
8795 u = reg;
8796 if (n_reg == 2 && reg == gpr)
8797 {
8798 regalign = 1;
8799 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8800 build_int_cst (TREE_TYPE (reg), n_reg - 1));
8801 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
8802 unshare_expr (reg), u);
8803 }
8804 /* _Decimal128 is passed in even/odd fpr pairs; the stored
8805 reg number is 0 for f1, so we want to make it odd. */
8806 else if (reg == fpr && mode == TDmode)
8807 {
8808 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8809 build_int_cst (TREE_TYPE (reg), 1));
8810 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
8811 }
8812
8813 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
8814 t = build2 (GE_EXPR, boolean_type_node, u, t);
8815 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8816 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8817 gimplify_and_add (t, pre_p);
8818
8819 t = sav;
8820 if (sav_ofs)
8821 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
8822
8823 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
8824 build_int_cst (TREE_TYPE (reg), n_reg));
8825 u = fold_convert (sizetype, u);
8826 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
8827 t = fold_build_pointer_plus (t, u);
8828
8829 /* _Decimal32 varargs are located in the second word of the 64-bit
8830 FP register for 32-bit binaries. */
8831 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
8832 t = fold_build_pointer_plus_hwi (t, size);
8833
8834 /* Args are passed right-aligned. */
8835 if (BYTES_BIG_ENDIAN)
8836 t = fold_build_pointer_plus_hwi (t, pad);
8837
8838 gimplify_assign (addr, t, pre_p);
8839
8840 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8841
8842 stmt = gimple_build_label (lab_false);
8843 gimple_seq_add_stmt (pre_p, stmt);
8844
8845 if ((n_reg == 2 && !regalign) || n_reg > 2)
8846 {
8847 /* Ensure that we don't find any more args in regs.
8848 Alignment has taken care of for special cases. */
8849 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
8850 }
8851 }
8852
8853 /* ... otherwise out of the overflow area. */
8854
8855 /* Care for on-stack alignment if needed. */
8856 t = ovf;
8857 if (align != 1)
8858 {
8859 t = fold_build_pointer_plus_hwi (t, align - 1);
8860 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
8861 build_int_cst (TREE_TYPE (t), -align));
8862 }
8863
8864 /* Args are passed right-aligned. */
8865 if (BYTES_BIG_ENDIAN)
8866 t = fold_build_pointer_plus_hwi (t, pad);
8867
8868 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8869
8870 gimplify_assign (unshare_expr (addr), t, pre_p);
8871
8872 t = fold_build_pointer_plus_hwi (t, size);
8873 gimplify_assign (unshare_expr (ovf), t, pre_p);
8874
8875 if (lab_over)
8876 {
8877 stmt = gimple_build_label (lab_over);
8878 gimple_seq_add_stmt (pre_p, stmt);
8879 }
8880
8881 if (STRICT_ALIGNMENT
8882 && (TYPE_ALIGN (type)
8883 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
8884 {
8885 /* The value (of type complex double, for example) may not be
8886 aligned in memory in the saved registers, so copy via a
8887 temporary. (This is the same code as used for SPARC.) */
8888 tree tmp = create_tmp_var (type, "va_arg_tmp");
8889 tree dest_addr = build_fold_addr_expr (tmp);
8890
8891 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
8892 3, dest_addr, addr, size_int (rsize * 4));
8893 TREE_ADDRESSABLE (tmp) = 1;
8894
8895 gimplify_and_add (copy, pre_p);
8896 addr = dest_addr;
8897 }
8898
8899 addr = fold_convert (ptrtype, addr);
8900 return build_va_arg_indirect_ref (addr);
8901 }
8902
8903 /* Builtins. */
8904
8905 static void
def_builtin(const char * name,tree type,enum rs6000_builtins code)8906 def_builtin (const char *name, tree type, enum rs6000_builtins code)
8907 {
8908 tree t;
8909 unsigned classify = rs6000_builtin_info[(int)code].attr;
8910 const char *attr_string = "";
8911
8912 /* Don't define the builtin if it doesn't have a type. See PR92661. */
8913 if (type == NULL_TREE)
8914 return;
8915
8916 gcc_assert (name != NULL);
8917 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
8918
8919 if (rs6000_builtin_decls[(int)code])
8920 fatal_error (input_location,
8921 "internal error: builtin function %qs already processed",
8922 name);
8923
8924 rs6000_builtin_decls[(int)code] = t =
8925 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
8926
8927 /* Set any special attributes. */
8928 if ((classify & RS6000_BTC_CONST) != 0)
8929 {
8930 /* const function, function only depends on the inputs. */
8931 TREE_READONLY (t) = 1;
8932 TREE_NOTHROW (t) = 1;
8933 attr_string = ", const";
8934 }
8935 else if ((classify & RS6000_BTC_PURE) != 0)
8936 {
8937 /* pure function, function can read global memory, but does not set any
8938 external state. */
8939 DECL_PURE_P (t) = 1;
8940 TREE_NOTHROW (t) = 1;
8941 attr_string = ", pure";
8942 }
8943 else if ((classify & RS6000_BTC_FP) != 0)
8944 {
8945 /* Function is a math function. If rounding mode is on, then treat the
8946 function as not reading global memory, but it can have arbitrary side
8947 effects. If it is off, then assume the function is a const function.
8948 This mimics the ATTR_MATHFN_FPROUNDING attribute in
8949 builtin-attribute.def that is used for the math functions. */
8950 TREE_NOTHROW (t) = 1;
8951 if (flag_rounding_math)
8952 {
8953 DECL_PURE_P (t) = 1;
8954 DECL_IS_NOVOPS (t) = 1;
8955 attr_string = ", fp, pure";
8956 }
8957 else
8958 {
8959 TREE_READONLY (t) = 1;
8960 attr_string = ", fp, const";
8961 }
8962 }
8963 else if ((classify & (RS6000_BTC_QUAD | RS6000_BTC_PAIR)) != 0)
8964 /* The function uses a register quad and/or pair. Nothing to do. */
8965 ;
8966 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
8967 gcc_unreachable ();
8968
8969 if (TARGET_DEBUG_BUILTIN)
8970 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
8971 (int)code, name, attr_string);
8972 }
8973
8974 static const struct builtin_compatibility bdesc_compat[] =
8975 {
8976 #define RS6000_BUILTIN_COMPAT
8977 #include "rs6000-builtin.def"
8978 };
8979 #undef RS6000_BUILTIN_COMPAT
8980
8981 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
8982
8983 #undef RS6000_BUILTIN_0
8984 #undef RS6000_BUILTIN_1
8985 #undef RS6000_BUILTIN_2
8986 #undef RS6000_BUILTIN_3
8987 #undef RS6000_BUILTIN_4
8988 #undef RS6000_BUILTIN_A
8989 #undef RS6000_BUILTIN_D
8990 #undef RS6000_BUILTIN_H
8991 #undef RS6000_BUILTIN_M
8992 #undef RS6000_BUILTIN_P
8993 #undef RS6000_BUILTIN_X
8994
8995 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
8996 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
8997 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
8998 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
8999 { MASK, ICODE, NAME, ENUM },
9000
9001 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
9002 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9003 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9004 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
9005 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
9006 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9007 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9008
9009 static const struct builtin_description bdesc_3arg[] =
9010 {
9011 #include "rs6000-builtin.def"
9012 };
9013
9014 /* Simple quaternary operations: VECd = foo (VECa, VECb, VECc, VECd). */
9015
9016 #undef RS6000_BUILTIN_0
9017 #undef RS6000_BUILTIN_1
9018 #undef RS6000_BUILTIN_2
9019 #undef RS6000_BUILTIN_3
9020 #undef RS6000_BUILTIN_4
9021 #undef RS6000_BUILTIN_A
9022 #undef RS6000_BUILTIN_D
9023 #undef RS6000_BUILTIN_H
9024 #undef RS6000_BUILTIN_M
9025 #undef RS6000_BUILTIN_P
9026 #undef RS6000_BUILTIN_X
9027
9028 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9029 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9030 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9031 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9032 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) \
9033 { MASK, ICODE, NAME, ENUM },
9034
9035 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9036 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9037 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
9038 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
9039 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9040 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9041
9042 static const struct builtin_description bdesc_4arg[] =
9043 {
9044 #include "rs6000-builtin.def"
9045 };
9046
9047 /* DST operations: void foo (void *, const int, const char). */
9048
9049 #undef RS6000_BUILTIN_0
9050 #undef RS6000_BUILTIN_1
9051 #undef RS6000_BUILTIN_2
9052 #undef RS6000_BUILTIN_3
9053 #undef RS6000_BUILTIN_4
9054 #undef RS6000_BUILTIN_A
9055 #undef RS6000_BUILTIN_D
9056 #undef RS6000_BUILTIN_H
9057 #undef RS6000_BUILTIN_M
9058 #undef RS6000_BUILTIN_P
9059 #undef RS6000_BUILTIN_X
9060
9061 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9062 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9063 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9064 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9065 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
9066 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9067 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9068 { MASK, ICODE, NAME, ENUM },
9069
9070 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
9071 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
9072 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9073 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9074
9075 static const struct builtin_description bdesc_dst[] =
9076 {
9077 #include "rs6000-builtin.def"
9078 };
9079
9080 /* Simple binary operations: VECc = foo (VECa, VECb). */
9081
9082 #undef RS6000_BUILTIN_0
9083 #undef RS6000_BUILTIN_1
9084 #undef RS6000_BUILTIN_2
9085 #undef RS6000_BUILTIN_3
9086 #undef RS6000_BUILTIN_4
9087 #undef RS6000_BUILTIN_A
9088 #undef RS6000_BUILTIN_D
9089 #undef RS6000_BUILTIN_H
9090 #undef RS6000_BUILTIN_M
9091 #undef RS6000_BUILTIN_P
9092 #undef RS6000_BUILTIN_X
9093
9094 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9095 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9096 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9097 { MASK, ICODE, NAME, ENUM },
9098
9099 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9100 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
9101 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9102 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9103 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
9104 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
9105 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9106 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9107
9108 static const struct builtin_description bdesc_2arg[] =
9109 {
9110 #include "rs6000-builtin.def"
9111 };
9112
9113 #undef RS6000_BUILTIN_0
9114 #undef RS6000_BUILTIN_1
9115 #undef RS6000_BUILTIN_2
9116 #undef RS6000_BUILTIN_3
9117 #undef RS6000_BUILTIN_4
9118 #undef RS6000_BUILTIN_A
9119 #undef RS6000_BUILTIN_D
9120 #undef RS6000_BUILTIN_H
9121 #undef RS6000_BUILTIN_M
9122 #undef RS6000_BUILTIN_P
9123 #undef RS6000_BUILTIN_X
9124
9125 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9126 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9127 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9128 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9129 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
9130 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9131 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9132 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
9133 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
9134 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9135 { MASK, ICODE, NAME, ENUM },
9136
9137 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9138
9139 /* AltiVec predicates. */
9140
9141 static const struct builtin_description bdesc_altivec_preds[] =
9142 {
9143 #include "rs6000-builtin.def"
9144 };
9145
9146 /* ABS* operations. */
9147
9148 #undef RS6000_BUILTIN_0
9149 #undef RS6000_BUILTIN_1
9150 #undef RS6000_BUILTIN_2
9151 #undef RS6000_BUILTIN_3
9152 #undef RS6000_BUILTIN_4
9153 #undef RS6000_BUILTIN_A
9154 #undef RS6000_BUILTIN_D
9155 #undef RS6000_BUILTIN_H
9156 #undef RS6000_BUILTIN_M
9157 #undef RS6000_BUILTIN_P
9158 #undef RS6000_BUILTIN_X
9159
9160 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9161 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9162 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9163 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9164 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
9165 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9166 { MASK, ICODE, NAME, ENUM },
9167
9168 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9169 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
9170 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
9171 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9172 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9173
9174 static const struct builtin_description bdesc_abs[] =
9175 {
9176 #include "rs6000-builtin.def"
9177 };
9178
9179 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9180 foo (VECa). */
9181
9182 #undef RS6000_BUILTIN_0
9183 #undef RS6000_BUILTIN_1
9184 #undef RS6000_BUILTIN_2
9185 #undef RS6000_BUILTIN_3
9186 #undef RS6000_BUILTIN_4
9187 #undef RS6000_BUILTIN_A
9188 #undef RS6000_BUILTIN_D
9189 #undef RS6000_BUILTIN_H
9190 #undef RS6000_BUILTIN_M
9191 #undef RS6000_BUILTIN_P
9192 #undef RS6000_BUILTIN_X
9193
9194 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9195 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9196 { MASK, ICODE, NAME, ENUM },
9197
9198 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9199 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9200 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
9201 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9202 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9203 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
9204 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
9205 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9206 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9207
9208 static const struct builtin_description bdesc_1arg[] =
9209 {
9210 #include "rs6000-builtin.def"
9211 };
9212
9213 /* Simple no-argument operations: result = __builtin_darn_32 () */
9214
9215 #undef RS6000_BUILTIN_0
9216 #undef RS6000_BUILTIN_1
9217 #undef RS6000_BUILTIN_2
9218 #undef RS6000_BUILTIN_3
9219 #undef RS6000_BUILTIN_4
9220 #undef RS6000_BUILTIN_A
9221 #undef RS6000_BUILTIN_D
9222 #undef RS6000_BUILTIN_H
9223 #undef RS6000_BUILTIN_M
9224 #undef RS6000_BUILTIN_P
9225 #undef RS6000_BUILTIN_X
9226
9227 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
9228 { MASK, ICODE, NAME, ENUM },
9229
9230 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9231 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9232 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9233 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
9234 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9235 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9236 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
9237 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
9238 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9239 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9240
9241 static const struct builtin_description bdesc_0arg[] =
9242 {
9243 #include "rs6000-builtin.def"
9244 };
9245
9246 /* HTM builtins. */
9247 #undef RS6000_BUILTIN_0
9248 #undef RS6000_BUILTIN_1
9249 #undef RS6000_BUILTIN_2
9250 #undef RS6000_BUILTIN_3
9251 #undef RS6000_BUILTIN_4
9252 #undef RS6000_BUILTIN_A
9253 #undef RS6000_BUILTIN_D
9254 #undef RS6000_BUILTIN_H
9255 #undef RS6000_BUILTIN_M
9256 #undef RS6000_BUILTIN_P
9257 #undef RS6000_BUILTIN_X
9258
9259 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9260 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9261 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9262 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9263 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
9264 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9265 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9266 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
9267 { MASK, ICODE, NAME, ENUM },
9268
9269 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE)
9270 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9271 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9272
9273 static const struct builtin_description bdesc_htm[] =
9274 {
9275 #include "rs6000-builtin.def"
9276 };
9277
9278 /* MMA builtins. */
9279 #undef RS6000_BUILTIN_0
9280 #undef RS6000_BUILTIN_1
9281 #undef RS6000_BUILTIN_2
9282 #undef RS6000_BUILTIN_3
9283 #undef RS6000_BUILTIN_4
9284 #undef RS6000_BUILTIN_A
9285 #undef RS6000_BUILTIN_D
9286 #undef RS6000_BUILTIN_H
9287 #undef RS6000_BUILTIN_M
9288 #undef RS6000_BUILTIN_P
9289 #undef RS6000_BUILTIN_X
9290
9291 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
9292 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9293 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9294 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9295 #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE)
9296 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9297 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9298 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
9299 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) \
9300 { MASK, ICODE, NAME, ENUM },
9301
9302 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9303 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9304
9305 static const struct builtin_description bdesc_mma[] =
9306 {
9307 #include "rs6000-builtin.def"
9308 };
9309
9310 #undef RS6000_BUILTIN_0
9311 #undef RS6000_BUILTIN_1
9312 #undef RS6000_BUILTIN_2
9313 #undef RS6000_BUILTIN_3
9314 #undef RS6000_BUILTIN_4
9315 #undef RS6000_BUILTIN_A
9316 #undef RS6000_BUILTIN_D
9317 #undef RS6000_BUILTIN_H
9318 #undef RS6000_BUILTIN_M
9319 #undef RS6000_BUILTIN_P
9320 #undef RS6000_BUILTIN_X
9321
9322 /* Return true if a builtin function is overloaded. */
9323 bool
rs6000_overloaded_builtin_p(enum rs6000_builtins fncode)9324 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
9325 {
9326 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
9327 }
9328
9329 const char *
rs6000_overloaded_builtin_name(enum rs6000_builtins fncode)9330 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
9331 {
9332 return rs6000_builtin_info[(int)fncode].name;
9333 }
9334
9335 /* Expand an expression EXP that calls a builtin without arguments. */
9336 static rtx
rs6000_expand_zeroop_builtin(enum insn_code icode,rtx target)9337 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
9338 {
9339 rtx pat;
9340 machine_mode tmode = insn_data[icode].operand[0].mode;
9341
9342 if (icode == CODE_FOR_nothing)
9343 /* Builtin not supported on this processor. */
9344 return 0;
9345
9346 if (icode == CODE_FOR_rs6000_mffsl
9347 && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
9348 {
9349 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>");
9350 return const0_rtx;
9351 }
9352
9353 if (target == 0
9354 || GET_MODE (target) != tmode
9355 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9356 target = gen_reg_rtx (tmode);
9357
9358 pat = GEN_FCN (icode) (target);
9359 if (! pat)
9360 return 0;
9361 emit_insn (pat);
9362
9363 return target;
9364 }
9365
9366
9367 static rtx
rs6000_expand_mtfsf_builtin(enum insn_code icode,tree exp)9368 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
9369 {
9370 rtx pat;
9371 tree arg0 = CALL_EXPR_ARG (exp, 0);
9372 tree arg1 = CALL_EXPR_ARG (exp, 1);
9373 rtx op0 = expand_normal (arg0);
9374 rtx op1 = expand_normal (arg1);
9375 machine_mode mode0 = insn_data[icode].operand[0].mode;
9376 machine_mode mode1 = insn_data[icode].operand[1].mode;
9377
9378 if (icode == CODE_FOR_nothing)
9379 /* Builtin not supported on this processor. */
9380 return 0;
9381
9382 /* If we got invalid arguments bail out before generating bad rtl. */
9383 if (arg0 == error_mark_node || arg1 == error_mark_node)
9384 return const0_rtx;
9385
9386 if (!CONST_INT_P (op0)
9387 || INTVAL (op0) > 255
9388 || INTVAL (op0) < 0)
9389 {
9390 error ("argument 1 must be an 8-bit field value");
9391 return const0_rtx;
9392 }
9393
9394 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
9395 op0 = copy_to_mode_reg (mode0, op0);
9396
9397 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
9398 op1 = copy_to_mode_reg (mode1, op1);
9399
9400 pat = GEN_FCN (icode) (op0, op1);
9401 if (!pat)
9402 return const0_rtx;
9403 emit_insn (pat);
9404
9405 return NULL_RTX;
9406 }
9407
9408 static rtx
rs6000_expand_mtfsb_builtin(enum insn_code icode,tree exp)9409 rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
9410 {
9411 rtx pat;
9412 tree arg0 = CALL_EXPR_ARG (exp, 0);
9413 rtx op0 = expand_normal (arg0);
9414
9415 if (icode == CODE_FOR_nothing)
9416 /* Builtin not supported on this processor. */
9417 return 0;
9418
9419 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
9420 {
9421 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with "
9422 "%<-msoft-float%>");
9423 return const0_rtx;
9424 }
9425
9426 /* If we got invalid arguments bail out before generating bad rtl. */
9427 if (arg0 == error_mark_node)
9428 return const0_rtx;
9429
9430 /* Only allow bit numbers 0 to 31. */
9431 if (!u5bit_cint_operand (op0, VOIDmode))
9432 {
9433 error ("Argument must be a constant between 0 and 31.");
9434 return const0_rtx;
9435 }
9436
9437 pat = GEN_FCN (icode) (op0);
9438 if (!pat)
9439 return const0_rtx;
9440 emit_insn (pat);
9441
9442 return NULL_RTX;
9443 }
9444
9445 static rtx
rs6000_expand_set_fpscr_rn_builtin(enum insn_code icode,tree exp)9446 rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
9447 {
9448 rtx pat;
9449 tree arg0 = CALL_EXPR_ARG (exp, 0);
9450 rtx op0 = expand_normal (arg0);
9451 machine_mode mode0 = insn_data[icode].operand[0].mode;
9452
9453 if (icode == CODE_FOR_nothing)
9454 /* Builtin not supported on this processor. */
9455 return 0;
9456
9457 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
9458 {
9459 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>");
9460 return const0_rtx;
9461 }
9462
9463 /* If we got invalid arguments bail out before generating bad rtl. */
9464 if (arg0 == error_mark_node)
9465 return const0_rtx;
9466
9467 /* If the argument is a constant, check the range. Argument can only be a
9468 2-bit value. Unfortunately, can't check the range of the value at
9469 compile time if the argument is a variable. The least significant two
9470 bits of the argument, regardless of type, are used to set the rounding
9471 mode. All other bits are ignored. */
9472 if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode))
9473 {
9474 error ("Argument must be a value between 0 and 3.");
9475 return const0_rtx;
9476 }
9477
9478 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
9479 op0 = copy_to_mode_reg (mode0, op0);
9480
9481 pat = GEN_FCN (icode) (op0);
9482 if (!pat)
9483 return const0_rtx;
9484 emit_insn (pat);
9485
9486 return NULL_RTX;
9487 }
9488 static rtx
rs6000_expand_set_fpscr_drn_builtin(enum insn_code icode,tree exp)9489 rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
9490 {
9491 rtx pat;
9492 tree arg0 = CALL_EXPR_ARG (exp, 0);
9493 rtx op0 = expand_normal (arg0);
9494 machine_mode mode0 = insn_data[icode].operand[0].mode;
9495
9496 if (TARGET_32BIT)
9497 /* Builtin not supported in 32-bit mode. */
9498 fatal_error (input_location,
9499 "%<__builtin_set_fpscr_drn%> is not supported "
9500 "in 32-bit mode");
9501
9502 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
9503 {
9504 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>");
9505 return const0_rtx;
9506 }
9507
9508 if (icode == CODE_FOR_nothing)
9509 /* Builtin not supported on this processor. */
9510 return 0;
9511
9512 /* If we got invalid arguments bail out before generating bad rtl. */
9513 if (arg0 == error_mark_node)
9514 return const0_rtx;
9515
9516 /* If the argument is a constant, check the range. Agrument can only be a
9517 3-bit value. Unfortunately, can't check the range of the value at
9518 compile time if the argument is a variable. The least significant two
9519 bits of the argument, regardless of type, are used to set the rounding
9520 mode. All other bits are ignored. */
9521 if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode))
9522 {
9523 error ("Argument must be a value between 0 and 7.");
9524 return const0_rtx;
9525 }
9526
9527 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
9528 op0 = copy_to_mode_reg (mode0, op0);
9529
9530 pat = GEN_FCN (icode) (op0);
9531 if (! pat)
9532 return const0_rtx;
9533 emit_insn (pat);
9534
9535 return NULL_RTX;
9536 }
9537
9538 static rtx
rs6000_expand_unop_builtin(enum insn_code icode,tree exp,rtx target)9539 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
9540 {
9541 rtx pat;
9542 tree arg0 = CALL_EXPR_ARG (exp, 0);
9543 rtx op0 = expand_normal (arg0);
9544 machine_mode tmode = insn_data[icode].operand[0].mode;
9545 machine_mode mode0 = insn_data[icode].operand[1].mode;
9546
9547 if (icode == CODE_FOR_nothing)
9548 /* Builtin not supported on this processor. */
9549 return 0;
9550
9551 /* If we got invalid arguments bail out before generating bad rtl. */
9552 if (arg0 == error_mark_node)
9553 return const0_rtx;
9554
9555 if (icode == CODE_FOR_altivec_vspltisb
9556 || icode == CODE_FOR_altivec_vspltish
9557 || icode == CODE_FOR_altivec_vspltisw)
9558 {
9559 /* Only allow 5-bit *signed* literals. */
9560 if (!CONST_INT_P (op0)
9561 || INTVAL (op0) > 15
9562 || INTVAL (op0) < -16)
9563 {
9564 error ("argument 1 must be a 5-bit signed literal");
9565 return CONST0_RTX (tmode);
9566 }
9567 }
9568
9569 if (target == 0
9570 || GET_MODE (target) != tmode
9571 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9572 target = gen_reg_rtx (tmode);
9573
9574 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9575 op0 = copy_to_mode_reg (mode0, op0);
9576
9577 pat = GEN_FCN (icode) (target, op0);
9578 if (! pat)
9579 return 0;
9580 emit_insn (pat);
9581
9582 return target;
9583 }
9584
9585 static rtx
altivec_expand_abs_builtin(enum insn_code icode,tree exp,rtx target)9586 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
9587 {
9588 rtx pat, scratch1, scratch2;
9589 tree arg0 = CALL_EXPR_ARG (exp, 0);
9590 rtx op0 = expand_normal (arg0);
9591 machine_mode tmode = insn_data[icode].operand[0].mode;
9592 machine_mode mode0 = insn_data[icode].operand[1].mode;
9593
9594 /* If we have invalid arguments, bail out before generating bad rtl. */
9595 if (arg0 == error_mark_node)
9596 return const0_rtx;
9597
9598 if (target == 0
9599 || GET_MODE (target) != tmode
9600 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9601 target = gen_reg_rtx (tmode);
9602
9603 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9604 op0 = copy_to_mode_reg (mode0, op0);
9605
9606 scratch1 = gen_reg_rtx (mode0);
9607 scratch2 = gen_reg_rtx (mode0);
9608
9609 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
9610 if (! pat)
9611 return 0;
9612 emit_insn (pat);
9613
9614 return target;
9615 }
9616
9617 static rtx
rs6000_expand_binop_builtin(enum insn_code icode,tree exp,rtx target)9618 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
9619 {
9620 rtx pat;
9621 tree arg0 = CALL_EXPR_ARG (exp, 0);
9622 tree arg1 = CALL_EXPR_ARG (exp, 1);
9623 rtx op0 = expand_normal (arg0);
9624 rtx op1 = expand_normal (arg1);
9625 machine_mode tmode = insn_data[icode].operand[0].mode;
9626 machine_mode mode0 = insn_data[icode].operand[1].mode;
9627 machine_mode mode1 = insn_data[icode].operand[2].mode;
9628
9629 if (icode == CODE_FOR_nothing)
9630 /* Builtin not supported on this processor. */
9631 return 0;
9632
9633 /* If we got invalid arguments bail out before generating bad rtl. */
9634 if (arg0 == error_mark_node || arg1 == error_mark_node)
9635 return const0_rtx;
9636
9637 if (icode == CODE_FOR_unpackv1ti
9638 || icode == CODE_FOR_unpackkf
9639 || icode == CODE_FOR_unpacktf
9640 || icode == CODE_FOR_unpackif
9641 || icode == CODE_FOR_unpacktd
9642 || icode == CODE_FOR_vec_cntmb_v16qi
9643 || icode == CODE_FOR_vec_cntmb_v8hi
9644 || icode == CODE_FOR_vec_cntmb_v4si
9645 || icode == CODE_FOR_vec_cntmb_v2di)
9646 {
9647 /* Only allow 1-bit unsigned literals. */
9648 STRIP_NOPS (arg1);
9649 if (TREE_CODE (arg1) != INTEGER_CST
9650 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
9651 {
9652 error ("argument 2 must be a 1-bit unsigned literal");
9653 return CONST0_RTX (tmode);
9654 }
9655 }
9656 else if (icode == CODE_FOR_altivec_vspltw)
9657 {
9658 /* Only allow 2-bit unsigned literals. */
9659 STRIP_NOPS (arg1);
9660 if (TREE_CODE (arg1) != INTEGER_CST
9661 || TREE_INT_CST_LOW (arg1) & ~3)
9662 {
9663 error ("argument 2 must be a 2-bit unsigned literal");
9664 return CONST0_RTX (tmode);
9665 }
9666 }
9667 else if (icode == CODE_FOR_vgnb)
9668 {
9669 /* Only allow unsigned literals in range 2..7. */
9670 /* Note that arg1 is second operand. */
9671 STRIP_NOPS (arg1);
9672 if (TREE_CODE (arg1) != INTEGER_CST
9673 || (TREE_INT_CST_LOW (arg1) & ~7)
9674 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 2, 7))
9675 {
9676 error ("argument 2 must be unsigned literal between "
9677 "2 and 7 inclusive");
9678 return CONST0_RTX (tmode);
9679 }
9680 }
9681 else if (icode == CODE_FOR_altivec_vsplth)
9682 {
9683 /* Only allow 3-bit unsigned literals. */
9684 STRIP_NOPS (arg1);
9685 if (TREE_CODE (arg1) != INTEGER_CST
9686 || TREE_INT_CST_LOW (arg1) & ~7)
9687 {
9688 error ("argument 2 must be a 3-bit unsigned literal");
9689 return CONST0_RTX (tmode);
9690 }
9691 }
9692 else if (icode == CODE_FOR_altivec_vspltb)
9693 {
9694 /* Only allow 4-bit unsigned literals. */
9695 STRIP_NOPS (arg1);
9696 if (TREE_CODE (arg1) != INTEGER_CST
9697 || TREE_INT_CST_LOW (arg1) & ~15)
9698 {
9699 error ("argument 2 must be a 4-bit unsigned literal");
9700 return CONST0_RTX (tmode);
9701 }
9702 }
9703 else if (icode == CODE_FOR_altivec_vcfux
9704 || icode == CODE_FOR_altivec_vcfsx
9705 || icode == CODE_FOR_altivec_vctsxs
9706 || icode == CODE_FOR_altivec_vctuxs
9707 || icode == CODE_FOR_vsx_xvcvuxddp_scale
9708 || icode == CODE_FOR_vsx_xvcvsxddp_scale)
9709 {
9710 /* Only allow 5-bit unsigned literals. */
9711 STRIP_NOPS (arg1);
9712 if (TREE_CODE (arg1) != INTEGER_CST
9713 || TREE_INT_CST_LOW (arg1) & ~0x1f)
9714 {
9715 error ("argument 2 must be a 5-bit unsigned literal");
9716 return CONST0_RTX (tmode);
9717 }
9718 }
9719 else if (icode == CODE_FOR_dfptstsfi_eq_dd
9720 || icode == CODE_FOR_dfptstsfi_lt_dd
9721 || icode == CODE_FOR_dfptstsfi_gt_dd
9722 || icode == CODE_FOR_dfptstsfi_unordered_dd
9723 || icode == CODE_FOR_dfptstsfi_eq_td
9724 || icode == CODE_FOR_dfptstsfi_lt_td
9725 || icode == CODE_FOR_dfptstsfi_gt_td
9726 || icode == CODE_FOR_dfptstsfi_unordered_td)
9727 {
9728 /* Only allow 6-bit unsigned literals. */
9729 STRIP_NOPS (arg0);
9730 if (TREE_CODE (arg0) != INTEGER_CST
9731 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
9732 {
9733 error ("argument 1 must be a 6-bit unsigned literal");
9734 return CONST0_RTX (tmode);
9735 }
9736 }
9737 else if (icode == CODE_FOR_xststdcqp_kf
9738 || icode == CODE_FOR_xststdcqp_tf
9739 || icode == CODE_FOR_xststdcdp
9740 || icode == CODE_FOR_xststdcsp
9741 || icode == CODE_FOR_xvtstdcdp
9742 || icode == CODE_FOR_xvtstdcsp)
9743 {
9744 /* Only allow 7-bit unsigned literals. */
9745 STRIP_NOPS (arg1);
9746 if (TREE_CODE (arg1) != INTEGER_CST
9747 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
9748 {
9749 error ("argument 2 must be a 7-bit unsigned literal");
9750 return CONST0_RTX (tmode);
9751 }
9752 }
9753
9754 if (target == 0
9755 || GET_MODE (target) != tmode
9756 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9757 target = gen_reg_rtx (tmode);
9758
9759 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9760 op0 = copy_to_mode_reg (mode0, op0);
9761 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9762 op1 = copy_to_mode_reg (mode1, op1);
9763
9764 pat = GEN_FCN (icode) (target, op0, op1);
9765 if (! pat)
9766 return 0;
9767 emit_insn (pat);
9768
9769 return target;
9770 }
9771
9772 static rtx
altivec_expand_predicate_builtin(enum insn_code icode,tree exp,rtx target)9773 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
9774 {
9775 rtx pat, scratch;
9776 tree cr6_form = CALL_EXPR_ARG (exp, 0);
9777 tree arg0 = CALL_EXPR_ARG (exp, 1);
9778 tree arg1 = CALL_EXPR_ARG (exp, 2);
9779 rtx op0 = expand_normal (arg0);
9780 rtx op1 = expand_normal (arg1);
9781 machine_mode tmode = SImode;
9782 machine_mode mode0 = insn_data[icode].operand[1].mode;
9783 machine_mode mode1 = insn_data[icode].operand[2].mode;
9784 int cr6_form_int;
9785
9786 if (TREE_CODE (cr6_form) != INTEGER_CST)
9787 {
9788 error ("argument 1 of %qs must be a constant",
9789 "__builtin_altivec_predicate");
9790 return const0_rtx;
9791 }
9792 else
9793 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
9794
9795 gcc_assert (mode0 == mode1);
9796
9797 /* If we have invalid arguments, bail out before generating bad rtl. */
9798 if (arg0 == error_mark_node || arg1 == error_mark_node)
9799 return const0_rtx;
9800
9801 if (target == 0
9802 || GET_MODE (target) != tmode
9803 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9804 target = gen_reg_rtx (tmode);
9805
9806 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9807 op0 = copy_to_mode_reg (mode0, op0);
9808 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9809 op1 = copy_to_mode_reg (mode1, op1);
9810
9811 /* Note that for many of the relevant operations (e.g. cmpne or
9812 cmpeq) with float or double operands, it makes more sense for the
9813 mode of the allocated scratch register to select a vector of
9814 integer. But the choice to copy the mode of operand 0 was made
9815 long ago and there are no plans to change it. */
9816 scratch = gen_reg_rtx (mode0);
9817
9818 pat = GEN_FCN (icode) (scratch, op0, op1);
9819 if (! pat)
9820 return 0;
9821 emit_insn (pat);
9822
9823 /* The vec_any* and vec_all* predicates use the same opcodes for two
9824 different operations, but the bits in CR6 will be different
9825 depending on what information we want. So we have to play tricks
9826 with CR6 to get the right bits out.
9827
9828 If you think this is disgusting, look at the specs for the
9829 AltiVec predicates. */
9830
9831 switch (cr6_form_int)
9832 {
9833 case 0:
9834 emit_insn (gen_cr6_test_for_zero (target));
9835 break;
9836 case 1:
9837 emit_insn (gen_cr6_test_for_zero_reverse (target));
9838 break;
9839 case 2:
9840 emit_insn (gen_cr6_test_for_lt (target));
9841 break;
9842 case 3:
9843 emit_insn (gen_cr6_test_for_lt_reverse (target));
9844 break;
9845 default:
9846 error ("argument 1 of %qs is out of range",
9847 "__builtin_altivec_predicate");
9848 break;
9849 }
9850
9851 return target;
9852 }
9853
9854 rtx
swap_endian_selector_for_mode(machine_mode mode)9855 swap_endian_selector_for_mode (machine_mode mode)
9856 {
9857 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
9858 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
9859 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
9860 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
9861
9862 unsigned int *swaparray, i;
9863 rtx perm[16];
9864
9865 switch (mode)
9866 {
9867 case E_V1TImode:
9868 swaparray = swap1;
9869 break;
9870 case E_V2DFmode:
9871 case E_V2DImode:
9872 swaparray = swap2;
9873 break;
9874 case E_V4SFmode:
9875 case E_V4SImode:
9876 swaparray = swap4;
9877 break;
9878 case E_V8HImode:
9879 swaparray = swap8;
9880 break;
9881 default:
9882 gcc_unreachable ();
9883 }
9884
9885 for (i = 0; i < 16; ++i)
9886 perm[i] = GEN_INT (swaparray[i]);
9887
9888 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
9889 gen_rtvec_v (16, perm)));
9890 }
9891
9892 /* For the load and sign extend rightmost elements; load and zero extend
9893 rightmost element builtins. */
9894 static rtx
altivec_expand_lxvr_builtin(enum insn_code icode,tree exp,rtx target,bool blk,bool sign_extend)9895 altivec_expand_lxvr_builtin (enum insn_code icode, tree exp, rtx target, bool blk, bool sign_extend)
9896 {
9897 rtx pat, addr;
9898 tree arg0 = CALL_EXPR_ARG (exp, 0);
9899 tree arg1 = CALL_EXPR_ARG (exp, 1);
9900 machine_mode tmode = insn_data[icode].operand[0].mode;
9901 machine_mode smode = insn_data[icode].operand[1].mode;
9902 machine_mode mode0 = Pmode;
9903 machine_mode mode1 = Pmode;
9904 rtx op0 = expand_normal (arg0);
9905 rtx op1 = expand_normal (arg1);
9906
9907 if (icode == CODE_FOR_nothing)
9908 /* Builtin not supported on this processor. */
9909 return 0;
9910
9911 /* If we got invalid arguments bail out before generating bad rtl. */
9912 if (arg0 == error_mark_node || arg1 == error_mark_node)
9913 return const0_rtx;
9914
9915 if (target == 0
9916 || GET_MODE (target) != tmode
9917 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9918 target = gen_reg_rtx (tmode);
9919
9920 op1 = copy_to_mode_reg (mode1, op1);
9921
9922 if (op0 == const0_rtx)
9923 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
9924 else
9925 {
9926 op0 = copy_to_mode_reg (mode0, op0);
9927 addr = gen_rtx_MEM (blk ? BLKmode : smode,
9928 gen_rtx_PLUS (Pmode, op1, op0));
9929 }
9930
9931 if (sign_extend)
9932 {
9933 rtx discratch = gen_reg_rtx (DImode);
9934 rtx tiscratch = gen_reg_rtx (TImode);
9935
9936 /* Emit the lxvr*x insn. */
9937 pat = GEN_FCN (icode) (tiscratch, addr);
9938 if (!pat)
9939 return 0;
9940 emit_insn (pat);
9941
9942 /* Emit a sign extension from QI,HI,WI to double (DI). */
9943 rtx scratch = gen_lowpart (smode, tiscratch);
9944 if (icode == CODE_FOR_vsx_lxvrbx)
9945 emit_insn (gen_extendqidi2 (discratch, scratch));
9946 else if (icode == CODE_FOR_vsx_lxvrhx)
9947 emit_insn (gen_extendhidi2 (discratch, scratch));
9948 else if (icode == CODE_FOR_vsx_lxvrwx)
9949 emit_insn (gen_extendsidi2 (discratch, scratch));
9950 /* Assign discratch directly if scratch is already DI. */
9951 if (icode == CODE_FOR_vsx_lxvrdx)
9952 discratch = scratch;
9953
9954 /* Emit the sign extension from DI (double) to TI (quad). */
9955 emit_insn (gen_extendditi2 (target, discratch));
9956
9957 return target;
9958 }
9959 else
9960 {
9961 /* Zero extend. */
9962 pat = GEN_FCN (icode) (target, addr);
9963 if (!pat)
9964 return 0;
9965 emit_insn (pat);
9966 return target;
9967 }
9968 return 0;
9969 }
9970
9971 static rtx
altivec_expand_lv_builtin(enum insn_code icode,tree exp,rtx target,bool blk)9972 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
9973 {
9974 rtx pat, addr;
9975 tree arg0 = CALL_EXPR_ARG (exp, 0);
9976 tree arg1 = CALL_EXPR_ARG (exp, 1);
9977 machine_mode tmode = insn_data[icode].operand[0].mode;
9978 machine_mode mode0 = Pmode;
9979 machine_mode mode1 = Pmode;
9980 rtx op0 = expand_normal (arg0);
9981 rtx op1 = expand_normal (arg1);
9982
9983 if (icode == CODE_FOR_nothing)
9984 /* Builtin not supported on this processor. */
9985 return 0;
9986
9987 /* If we got invalid arguments bail out before generating bad rtl. */
9988 if (arg0 == error_mark_node || arg1 == error_mark_node)
9989 return const0_rtx;
9990
9991 if (target == 0
9992 || GET_MODE (target) != tmode
9993 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9994 target = gen_reg_rtx (tmode);
9995
9996 op1 = copy_to_mode_reg (mode1, op1);
9997
9998 /* For LVX, express the RTL accurately by ANDing the address with -16.
9999 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
10000 so the raw address is fine. */
10001 if (icode == CODE_FOR_altivec_lvx_v1ti
10002 || icode == CODE_FOR_altivec_lvx_v2df
10003 || icode == CODE_FOR_altivec_lvx_v2di
10004 || icode == CODE_FOR_altivec_lvx_v4sf
10005 || icode == CODE_FOR_altivec_lvx_v4si
10006 || icode == CODE_FOR_altivec_lvx_v8hi
10007 || icode == CODE_FOR_altivec_lvx_v16qi)
10008 {
10009 rtx rawaddr;
10010 if (op0 == const0_rtx)
10011 rawaddr = op1;
10012 else
10013 {
10014 op0 = copy_to_mode_reg (mode0, op0);
10015 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
10016 }
10017 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
10018 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
10019
10020 emit_insn (gen_rtx_SET (target, addr));
10021 }
10022 else
10023 {
10024 if (op0 == const0_rtx)
10025 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
10026 else
10027 {
10028 op0 = copy_to_mode_reg (mode0, op0);
10029 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
10030 gen_rtx_PLUS (Pmode, op1, op0));
10031 }
10032
10033 pat = GEN_FCN (icode) (target, addr);
10034 if (! pat)
10035 return 0;
10036 emit_insn (pat);
10037 }
10038
10039 return target;
10040 }
10041
10042 static rtx
altivec_expand_stxvl_builtin(enum insn_code icode,tree exp)10043 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
10044 {
10045 rtx pat;
10046 tree arg0 = CALL_EXPR_ARG (exp, 0);
10047 tree arg1 = CALL_EXPR_ARG (exp, 1);
10048 tree arg2 = CALL_EXPR_ARG (exp, 2);
10049 rtx op0 = expand_normal (arg0);
10050 rtx op1 = expand_normal (arg1);
10051 rtx op2 = expand_normal (arg2);
10052 machine_mode mode0 = insn_data[icode].operand[0].mode;
10053 machine_mode mode1 = insn_data[icode].operand[1].mode;
10054 machine_mode mode2 = insn_data[icode].operand[2].mode;
10055
10056 if (icode == CODE_FOR_nothing)
10057 /* Builtin not supported on this processor. */
10058 return NULL_RTX;
10059
10060 /* If we got invalid arguments bail out before generating bad rtl. */
10061 if (arg0 == error_mark_node
10062 || arg1 == error_mark_node
10063 || arg2 == error_mark_node)
10064 return NULL_RTX;
10065
10066 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10067 op0 = copy_to_mode_reg (mode0, op0);
10068 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10069 op1 = copy_to_mode_reg (mode1, op1);
10070 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10071 op2 = copy_to_mode_reg (mode2, op2);
10072
10073 pat = GEN_FCN (icode) (op0, op1, op2);
10074 if (pat)
10075 emit_insn (pat);
10076
10077 return NULL_RTX;
10078 }
10079
10080 static rtx
altivec_expand_stv_builtin(enum insn_code icode,tree exp)10081 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
10082 {
10083 tree arg0 = CALL_EXPR_ARG (exp, 0);
10084 tree arg1 = CALL_EXPR_ARG (exp, 1);
10085 tree arg2 = CALL_EXPR_ARG (exp, 2);
10086 rtx op0 = expand_normal (arg0);
10087 rtx op1 = expand_normal (arg1);
10088 rtx op2 = expand_normal (arg2);
10089 rtx pat, addr, rawaddr, truncrtx;
10090 machine_mode tmode = insn_data[icode].operand[0].mode;
10091 machine_mode smode = insn_data[icode].operand[1].mode;
10092 machine_mode mode1 = Pmode;
10093 machine_mode mode2 = Pmode;
10094
10095 /* Invalid arguments. Bail before doing anything stoopid! */
10096 if (arg0 == error_mark_node
10097 || arg1 == error_mark_node
10098 || arg2 == error_mark_node)
10099 return const0_rtx;
10100
10101 op2 = copy_to_mode_reg (mode2, op2);
10102
10103 /* For STVX, express the RTL accurately by ANDing the address with -16.
10104 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
10105 so the raw address is fine. */
10106 if (icode == CODE_FOR_altivec_stvx_v2df
10107 || icode == CODE_FOR_altivec_stvx_v2di
10108 || icode == CODE_FOR_altivec_stvx_v4sf
10109 || icode == CODE_FOR_altivec_stvx_v4si
10110 || icode == CODE_FOR_altivec_stvx_v8hi
10111 || icode == CODE_FOR_altivec_stvx_v16qi)
10112 {
10113 if (op1 == const0_rtx)
10114 rawaddr = op2;
10115 else
10116 {
10117 op1 = copy_to_mode_reg (mode1, op1);
10118 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
10119 }
10120
10121 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
10122 addr = gen_rtx_MEM (tmode, addr);
10123
10124 op0 = copy_to_mode_reg (tmode, op0);
10125
10126 emit_insn (gen_rtx_SET (addr, op0));
10127 }
10128 else if (icode == CODE_FOR_vsx_stxvrbx
10129 || icode == CODE_FOR_vsx_stxvrhx
10130 || icode == CODE_FOR_vsx_stxvrwx
10131 || icode == CODE_FOR_vsx_stxvrdx)
10132 {
10133 truncrtx = gen_rtx_TRUNCATE (tmode, op0);
10134 op0 = copy_to_mode_reg (E_TImode, truncrtx);
10135
10136 if (op1 == const0_rtx)
10137 addr = gen_rtx_MEM (Pmode, op2);
10138 else
10139 {
10140 op1 = copy_to_mode_reg (mode1, op1);
10141 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
10142 }
10143 pat = GEN_FCN (icode) (addr, op0);
10144 if (pat)
10145 emit_insn (pat);
10146 }
10147 else
10148 {
10149 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
10150 op0 = copy_to_mode_reg (smode, op0);
10151
10152 if (op1 == const0_rtx)
10153 addr = gen_rtx_MEM (tmode, op2);
10154 else
10155 {
10156 op1 = copy_to_mode_reg (mode1, op1);
10157 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
10158 }
10159
10160 pat = GEN_FCN (icode) (addr, op0);
10161 if (pat)
10162 emit_insn (pat);
10163 }
10164
10165 return NULL_RTX;
10166 }
10167
10168 /* Expand the MMA built-in in EXP.
10169 Store true in *EXPANDEDP if we found a built-in to expand. */
10170
10171 static rtx
mma_expand_builtin(tree exp,rtx target,bool * expandedp)10172 mma_expand_builtin (tree exp, rtx target, bool *expandedp)
10173 {
10174 unsigned i;
10175 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10176 enum rs6000_builtins fcode
10177 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
10178 const struct builtin_description *d = bdesc_mma;
10179
10180 /* Expand the MMA built-in. */
10181 for (i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++)
10182 if (d->code == fcode)
10183 break;
10184
10185 if (i >= ARRAY_SIZE (bdesc_mma))
10186 {
10187 *expandedp = false;
10188 return NULL_RTX;
10189 }
10190
10191 *expandedp = true;
10192
10193 tree arg;
10194 call_expr_arg_iterator iter;
10195 enum insn_code icode = d->icode;
10196 const struct insn_operand_data *insn_op;
10197 rtx op[MAX_MMA_OPERANDS];
10198 unsigned nopnds = 0;
10199 unsigned attr = rs6000_builtin_info[fcode].attr;
10200 bool void_func = (attr & RS6000_BTC_VOID);
10201 machine_mode tmode = VOIDmode;
10202
10203 if (TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node)
10204 {
10205 tmode = insn_data[icode].operand[0].mode;
10206 if (!target
10207 || GET_MODE (target) != tmode
10208 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
10209 target = gen_reg_rtx (tmode);
10210 op[nopnds++] = target;
10211 }
10212 else
10213 target = const0_rtx;
10214
10215 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10216 {
10217 if (arg == error_mark_node)
10218 return const0_rtx;
10219
10220 rtx opnd;
10221 insn_op = &insn_data[icode].operand[nopnds];
10222 if (TREE_CODE (arg) == ADDR_EXPR
10223 && MEM_P (DECL_RTL (TREE_OPERAND (arg, 0))))
10224 opnd = DECL_RTL (TREE_OPERAND (arg, 0));
10225 else
10226 opnd = expand_normal (arg);
10227
10228 if (!(*insn_op->predicate) (opnd, insn_op->mode))
10229 {
10230 if (!strcmp (insn_op->constraint, "n"))
10231 {
10232 if (!CONST_INT_P (opnd))
10233 error ("argument %d must be an unsigned literal", nopnds);
10234 else
10235 error ("argument %d is an unsigned literal that is "
10236 "out of range", nopnds);
10237 return const0_rtx;
10238 }
10239 opnd = copy_to_mode_reg (insn_op->mode, opnd);
10240 }
10241
10242 /* Some MMA instructions have INOUT accumulator operands, so force
10243 their target register to be the same as their input register. */
10244 if (!void_func
10245 && nopnds == 1
10246 && !strcmp (insn_op->constraint, "0")
10247 && insn_op->mode == tmode
10248 && REG_P (opnd)
10249 && (*insn_data[icode].operand[0].predicate) (opnd, tmode))
10250 target = op[0] = opnd;
10251
10252 op[nopnds++] = opnd;
10253 }
10254
10255 unsigned attr_args = attr & RS6000_BTC_OPND_MASK;
10256 if (attr & RS6000_BTC_QUAD
10257 || fcode == VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL)
10258 attr_args++;
10259
10260 gcc_assert (nopnds == attr_args);
10261
10262 rtx pat;
10263 switch (nopnds)
10264 {
10265 case 1:
10266 pat = GEN_FCN (icode) (op[0]);
10267 break;
10268 case 2:
10269 pat = GEN_FCN (icode) (op[0], op[1]);
10270 break;
10271 case 3:
10272 /* The ASSEMBLE builtin source operands are reversed in little-endian
10273 mode, so reorder them. */
10274 if (fcode == VSX_BUILTIN_ASSEMBLE_PAIR_INTERNAL && !WORDS_BIG_ENDIAN)
10275 std::swap (op[1], op[2]);
10276 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
10277 break;
10278 case 4:
10279 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
10280 break;
10281 case 5:
10282 /* The ASSEMBLE builtin source operands are reversed in little-endian
10283 mode, so reorder them. */
10284 if (fcode == MMA_BUILTIN_ASSEMBLE_ACC_INTERNAL && !WORDS_BIG_ENDIAN)
10285 {
10286 std::swap (op[1], op[4]);
10287 std::swap (op[2], op[3]);
10288 }
10289 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
10290 break;
10291 case 6:
10292 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]);
10293 break;
10294 case 7:
10295 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5], op[6]);
10296 break;
10297 default:
10298 gcc_unreachable ();
10299 }
10300 if (!pat)
10301 return NULL_RTX;
10302 emit_insn (pat);
10303
10304 return target;
10305 }
10306
10307 /* Return the appropriate SPR number associated with the given builtin. */
10308 static inline HOST_WIDE_INT
htm_spr_num(enum rs6000_builtins code)10309 htm_spr_num (enum rs6000_builtins code)
10310 {
10311 if (code == HTM_BUILTIN_GET_TFHAR
10312 || code == HTM_BUILTIN_SET_TFHAR)
10313 return TFHAR_SPR;
10314 else if (code == HTM_BUILTIN_GET_TFIAR
10315 || code == HTM_BUILTIN_SET_TFIAR)
10316 return TFIAR_SPR;
10317 else if (code == HTM_BUILTIN_GET_TEXASR
10318 || code == HTM_BUILTIN_SET_TEXASR)
10319 return TEXASR_SPR;
10320 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
10321 || code == HTM_BUILTIN_SET_TEXASRU);
10322 return TEXASRU_SPR;
10323 }
10324
10325 /* Return the correct ICODE value depending on whether we are
10326 setting or reading the HTM SPRs. */
10327 static inline enum insn_code
rs6000_htm_spr_icode(bool nonvoid)10328 rs6000_htm_spr_icode (bool nonvoid)
10329 {
10330 if (nonvoid)
10331 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
10332 else
10333 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
10334 }
10335
10336 /* Expand the HTM builtin in EXP and store the result in TARGET.
10337 Store true in *EXPANDEDP if we found a builtin to expand. */
10338 static rtx
htm_expand_builtin(tree exp,rtx target,bool * expandedp)10339 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
10340 {
10341 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10342 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
10343 enum rs6000_builtins fcode
10344 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
10345 const struct builtin_description *d;
10346 size_t i;
10347
10348 *expandedp = true;
10349
10350 if (!TARGET_POWERPC64
10351 && (fcode == HTM_BUILTIN_TABORTDC
10352 || fcode == HTM_BUILTIN_TABORTDCI))
10353 {
10354 size_t uns_fcode = (size_t)fcode;
10355 const char *name = rs6000_builtin_info[uns_fcode].name;
10356 error ("builtin %qs is only valid in 64-bit mode", name);
10357 return const0_rtx;
10358 }
10359
10360 /* Expand the HTM builtins. */
10361 d = bdesc_htm;
10362 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
10363 if (d->code == fcode)
10364 {
10365 rtx op[MAX_HTM_OPERANDS], pat;
10366 int nopnds = 0;
10367 tree arg;
10368 call_expr_arg_iterator iter;
10369 unsigned attr = rs6000_builtin_info[fcode].attr;
10370 enum insn_code icode = d->icode;
10371 const struct insn_operand_data *insn_op;
10372 bool uses_spr = (attr & RS6000_BTC_SPR);
10373 rtx cr = NULL_RTX;
10374
10375 if (uses_spr)
10376 icode = rs6000_htm_spr_icode (nonvoid);
10377 insn_op = &insn_data[icode].operand[0];
10378
10379 if (nonvoid)
10380 {
10381 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
10382 if (!target
10383 || GET_MODE (target) != tmode
10384 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
10385 target = gen_reg_rtx (tmode);
10386 if (uses_spr)
10387 op[nopnds++] = target;
10388 }
10389
10390 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10391 {
10392 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
10393 return const0_rtx;
10394
10395 insn_op = &insn_data[icode].operand[nopnds];
10396
10397 op[nopnds] = expand_normal (arg);
10398
10399 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
10400 {
10401 if (!strcmp (insn_op->constraint, "n"))
10402 {
10403 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
10404 if (!CONST_INT_P (op[nopnds]))
10405 error ("argument %d must be an unsigned literal", arg_num);
10406 else
10407 error ("argument %d is an unsigned literal that is "
10408 "out of range", arg_num);
10409 return const0_rtx;
10410 }
10411 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
10412 }
10413
10414 nopnds++;
10415 }
10416
10417 /* Handle the builtins for extended mnemonics. These accept
10418 no arguments, but map to builtins that take arguments. */
10419 switch (fcode)
10420 {
10421 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
10422 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
10423 op[nopnds++] = GEN_INT (1);
10424 if (flag_checking)
10425 attr |= RS6000_BTC_UNARY;
10426 break;
10427 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
10428 op[nopnds++] = GEN_INT (0);
10429 if (flag_checking)
10430 attr |= RS6000_BTC_UNARY;
10431 break;
10432 default:
10433 break;
10434 }
10435
10436 /* If this builtin accesses SPRs, then pass in the appropriate
10437 SPR number and SPR regno as the last two operands. */
10438 if (uses_spr)
10439 {
10440 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
10441 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
10442 }
10443 /* If this builtin accesses a CR, then pass in a scratch
10444 CR as the last operand. */
10445 else if (attr & RS6000_BTC_CR)
10446 { cr = gen_reg_rtx (CCmode);
10447 op[nopnds++] = cr;
10448 }
10449
10450 if (flag_checking)
10451 {
10452 int expected_nopnds = 0;
10453 if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_UNARY)
10454 expected_nopnds = 1;
10455 else if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_BINARY)
10456 expected_nopnds = 2;
10457 else if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_TERNARY)
10458 expected_nopnds = 3;
10459 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_QUATERNARY)
10460 expected_nopnds = 4;
10461 if (!(attr & RS6000_BTC_VOID))
10462 expected_nopnds += 1;
10463 if (uses_spr)
10464 expected_nopnds += 1;
10465
10466 gcc_assert (nopnds == expected_nopnds
10467 && nopnds <= MAX_HTM_OPERANDS);
10468 }
10469
10470 switch (nopnds)
10471 {
10472 case 1:
10473 pat = GEN_FCN (icode) (op[0]);
10474 break;
10475 case 2:
10476 pat = GEN_FCN (icode) (op[0], op[1]);
10477 break;
10478 case 3:
10479 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
10480 break;
10481 case 4:
10482 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
10483 break;
10484 default:
10485 gcc_unreachable ();
10486 }
10487 if (!pat)
10488 return NULL_RTX;
10489 emit_insn (pat);
10490
10491 if (attr & RS6000_BTC_CR)
10492 {
10493 if (fcode == HTM_BUILTIN_TBEGIN)
10494 {
10495 /* Emit code to set TARGET to true or false depending on
10496 whether the tbegin. instruction successfully or failed
10497 to start a transaction. We do this by placing the 1's
10498 complement of CR's EQ bit into TARGET. */
10499 rtx scratch = gen_reg_rtx (SImode);
10500 emit_insn (gen_rtx_SET (scratch,
10501 gen_rtx_EQ (SImode, cr,
10502 const0_rtx)));
10503 emit_insn (gen_rtx_SET (target,
10504 gen_rtx_XOR (SImode, scratch,
10505 GEN_INT (1))));
10506 }
10507 else
10508 {
10509 /* Emit code to copy the 4-bit condition register field
10510 CR into the least significant end of register TARGET. */
10511 rtx scratch1 = gen_reg_rtx (SImode);
10512 rtx scratch2 = gen_reg_rtx (SImode);
10513 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
10514 emit_insn (gen_movcc (subreg, cr));
10515 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
10516 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
10517 }
10518 }
10519
10520 if (nonvoid)
10521 return target;
10522 return const0_rtx;
10523 }
10524
10525 *expandedp = false;
10526 return NULL_RTX;
10527 }
10528
10529 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
10530
10531 static rtx
cpu_expand_builtin(enum rs6000_builtins fcode,tree exp ATTRIBUTE_UNUSED,rtx target)10532 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
10533 rtx target)
10534 {
10535 /* __builtin_cpu_init () is a nop, so expand to nothing. */
10536 if (fcode == RS6000_BUILTIN_CPU_INIT)
10537 return const0_rtx;
10538
10539 if (target == 0 || GET_MODE (target) != SImode)
10540 target = gen_reg_rtx (SImode);
10541
10542 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
10543 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
10544 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
10545 to a STRING_CST. */
10546 if (TREE_CODE (arg) == ARRAY_REF
10547 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
10548 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
10549 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
10550 arg = TREE_OPERAND (arg, 0);
10551
10552 if (TREE_CODE (arg) != STRING_CST)
10553 {
10554 error ("builtin %qs only accepts a string argument",
10555 rs6000_builtin_info[(size_t) fcode].name);
10556 return const0_rtx;
10557 }
10558
10559 if (fcode == RS6000_BUILTIN_CPU_IS)
10560 {
10561 const char *cpu = TREE_STRING_POINTER (arg);
10562 rtx cpuid = NULL_RTX;
10563 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
10564 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
10565 {
10566 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
10567 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
10568 break;
10569 }
10570 if (cpuid == NULL_RTX)
10571 {
10572 /* Invalid CPU argument. */
10573 error ("cpu %qs is an invalid argument to builtin %qs",
10574 cpu, rs6000_builtin_info[(size_t) fcode].name);
10575 return const0_rtx;
10576 }
10577
10578 rtx platform = gen_reg_rtx (SImode);
10579 rtx tcbmem = gen_const_mem (SImode,
10580 gen_rtx_PLUS (Pmode,
10581 gen_rtx_REG (Pmode, TLS_REGNUM),
10582 GEN_INT (TCB_PLATFORM_OFFSET)));
10583 emit_move_insn (platform, tcbmem);
10584 emit_insn (gen_eqsi3 (target, platform, cpuid));
10585 }
10586 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
10587 {
10588 const char *hwcap = TREE_STRING_POINTER (arg);
10589 rtx mask = NULL_RTX;
10590 int hwcap_offset;
10591 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
10592 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
10593 {
10594 mask = GEN_INT (cpu_supports_info[i].mask);
10595 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
10596 break;
10597 }
10598 if (mask == NULL_RTX)
10599 {
10600 /* Invalid HWCAP argument. */
10601 error ("%s %qs is an invalid argument to builtin %qs",
10602 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
10603 return const0_rtx;
10604 }
10605
10606 rtx tcb_hwcap = gen_reg_rtx (SImode);
10607 rtx tcbmem = gen_const_mem (SImode,
10608 gen_rtx_PLUS (Pmode,
10609 gen_rtx_REG (Pmode, TLS_REGNUM),
10610 GEN_INT (hwcap_offset)));
10611 emit_move_insn (tcb_hwcap, tcbmem);
10612 rtx scratch1 = gen_reg_rtx (SImode);
10613 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
10614 rtx scratch2 = gen_reg_rtx (SImode);
10615 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
10616 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
10617 }
10618 else
10619 gcc_unreachable ();
10620
10621 /* Record that we have expanded a CPU builtin, so that we can later
10622 emit a reference to the special symbol exported by LIBC to ensure we
10623 do not link against an old LIBC that doesn't support this feature. */
10624 cpu_builtin_p = true;
10625
10626 #else
10627 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
10628 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
10629
10630 /* For old LIBCs, always return FALSE. */
10631 emit_move_insn (target, GEN_INT (0));
10632 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
10633
10634 return target;
10635 }
10636
10637 static rtx
rs6000_expand_quaternop_builtin(enum insn_code icode,tree exp,rtx target)10638 rs6000_expand_quaternop_builtin (enum insn_code icode, tree exp, rtx target)
10639 {
10640 rtx pat;
10641 tree arg0 = CALL_EXPR_ARG (exp, 0);
10642 tree arg1 = CALL_EXPR_ARG (exp, 1);
10643 tree arg2 = CALL_EXPR_ARG (exp, 2);
10644 tree arg3 = CALL_EXPR_ARG (exp, 3);
10645 rtx op0 = expand_normal (arg0);
10646 rtx op1 = expand_normal (arg1);
10647 rtx op2 = expand_normal (arg2);
10648 rtx op3 = expand_normal (arg3);
10649 machine_mode tmode = insn_data[icode].operand[0].mode;
10650 machine_mode mode0 = insn_data[icode].operand[1].mode;
10651 machine_mode mode1 = insn_data[icode].operand[2].mode;
10652 machine_mode mode2 = insn_data[icode].operand[3].mode;
10653 machine_mode mode3 = insn_data[icode].operand[4].mode;
10654
10655 if (icode == CODE_FOR_nothing)
10656 /* Builtin not supported on this processor. */
10657 return 0;
10658
10659 /* If we got invalid arguments bail out before generating bad rtl. */
10660 if (arg0 == error_mark_node
10661 || arg1 == error_mark_node
10662 || arg2 == error_mark_node
10663 || arg3 == error_mark_node)
10664 return const0_rtx;
10665
10666 /* Check and prepare argument depending on the instruction code.
10667
10668 Note that a switch statement instead of the sequence of tests
10669 would be incorrect as many of the CODE_FOR values could be
10670 CODE_FOR_nothing and that would yield multiple alternatives
10671 with identical values. We'd never reach here at runtime in
10672 this case. */
10673 if (icode == CODE_FOR_xxeval)
10674 {
10675 /* Only allow 8-bit unsigned literals. */
10676 STRIP_NOPS (arg3);
10677 if (TREE_CODE (arg3) != INTEGER_CST
10678 || TREE_INT_CST_LOW (arg3) & ~0xff)
10679 {
10680 error ("argument 4 must be an 8-bit unsigned literal");
10681 return CONST0_RTX (tmode);
10682 }
10683 }
10684
10685 else if (icode == CODE_FOR_xxpermx)
10686 {
10687 /* Only allow 3-bit unsigned literals. */
10688 STRIP_NOPS (arg3);
10689 if (TREE_CODE (arg3) != INTEGER_CST
10690 || TREE_INT_CST_LOW (arg3) & ~0x7)
10691 {
10692 error ("argument 4 must be a 3-bit unsigned literal");
10693 return CONST0_RTX (tmode);
10694 }
10695 }
10696
10697 else if (icode == CODE_FOR_vreplace_elt_v4si
10698 || icode == CODE_FOR_vreplace_elt_v4sf)
10699 {
10700 /* Check whether the 3rd argument is an integer constant in the range
10701 0 to 3 inclusive. */
10702 STRIP_NOPS (arg2);
10703 if (TREE_CODE (arg2) != INTEGER_CST
10704 || !IN_RANGE (TREE_INT_CST_LOW (arg2), 0, 3))
10705 {
10706 error ("argument 3 must be in the range 0 to 3");
10707 return CONST0_RTX (tmode);
10708 }
10709 }
10710
10711 else if (icode == CODE_FOR_vreplace_un_v4si
10712 || icode == CODE_FOR_vreplace_un_v4sf)
10713 {
10714 /* Check whether the 3rd argument is an integer constant in the range
10715 0 to 12 inclusive. */
10716 STRIP_NOPS (arg2);
10717 if (TREE_CODE (arg2) != INTEGER_CST
10718 || !IN_RANGE(TREE_INT_CST_LOW (arg2), 0, 12))
10719 {
10720 error ("argument 3 must be in the range 0 to 12");
10721 return CONST0_RTX (tmode);
10722 }
10723 }
10724
10725 else if (icode == CODE_FOR_vsldb_v16qi
10726 || icode == CODE_FOR_vsldb_v8hi
10727 || icode == CODE_FOR_vsldb_v4si
10728 || icode == CODE_FOR_vsldb_v2di
10729 || icode == CODE_FOR_vsrdb_v16qi
10730 || icode == CODE_FOR_vsrdb_v8hi
10731 || icode == CODE_FOR_vsrdb_v4si
10732 || icode == CODE_FOR_vsrdb_v2di)
10733 {
10734 /* Check whether the 3rd argument is an integer constant in the range
10735 0 to 7 inclusive. */
10736 STRIP_NOPS (arg2);
10737 if (TREE_CODE (arg2) != INTEGER_CST
10738 || !IN_RANGE (TREE_INT_CST_LOW (arg2), 0, 7))
10739 {
10740 error ("argument 3 must be a constant in the range 0 to 7");
10741 return CONST0_RTX (tmode);
10742 }
10743 }
10744
10745 if (target == 0
10746 || GET_MODE (target) != tmode
10747 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10748 target = gen_reg_rtx (tmode);
10749
10750 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10751 op0 = copy_to_mode_reg (mode0, op0);
10752 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10753 op1 = copy_to_mode_reg (mode1, op1);
10754 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10755 op2 = copy_to_mode_reg (mode2, op2);
10756 if (! (*insn_data[icode].operand[4].predicate) (op3, mode3))
10757 op3 = copy_to_mode_reg (mode3, op3);
10758
10759 pat = GEN_FCN (icode) (target, op0, op1, op2, op3);
10760 if (! pat)
10761 return 0;
10762 emit_insn (pat);
10763
10764 return target;
10765 }
10766
10767 static rtx
rs6000_expand_ternop_builtin(enum insn_code icode,tree exp,rtx target)10768 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
10769 {
10770 rtx pat;
10771 tree arg0 = CALL_EXPR_ARG (exp, 0);
10772 tree arg1 = CALL_EXPR_ARG (exp, 1);
10773 tree arg2 = CALL_EXPR_ARG (exp, 2);
10774 rtx op0 = expand_normal (arg0);
10775 rtx op1 = expand_normal (arg1);
10776 rtx op2 = expand_normal (arg2);
10777 machine_mode tmode = insn_data[icode].operand[0].mode;
10778 machine_mode mode0 = insn_data[icode].operand[1].mode;
10779 machine_mode mode1 = insn_data[icode].operand[2].mode;
10780 machine_mode mode2 = insn_data[icode].operand[3].mode;
10781
10782 if (icode == CODE_FOR_nothing)
10783 /* Builtin not supported on this processor. */
10784 return 0;
10785
10786 /* If we got invalid arguments bail out before generating bad rtl. */
10787 if (arg0 == error_mark_node
10788 || arg1 == error_mark_node
10789 || arg2 == error_mark_node)
10790 return const0_rtx;
10791
10792 /* Check and prepare argument depending on the instruction code.
10793
10794 Note that a switch statement instead of the sequence of tests
10795 would be incorrect as many of the CODE_FOR values could be
10796 CODE_FOR_nothing and that would yield multiple alternatives
10797 with identical values. We'd never reach here at runtime in
10798 this case. */
10799 if (icode == CODE_FOR_altivec_vsldoi_v4sf
10800 || icode == CODE_FOR_altivec_vsldoi_v2df
10801 || icode == CODE_FOR_altivec_vsldoi_v4si
10802 || icode == CODE_FOR_altivec_vsldoi_v8hi
10803 || icode == CODE_FOR_altivec_vsldoi_v16qi)
10804 {
10805 /* Only allow 4-bit unsigned literals. */
10806 STRIP_NOPS (arg2);
10807 if (TREE_CODE (arg2) != INTEGER_CST
10808 || TREE_INT_CST_LOW (arg2) & ~0xf)
10809 {
10810 error ("argument 3 must be a 4-bit unsigned literal");
10811 return CONST0_RTX (tmode);
10812 }
10813 }
10814 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
10815 || icode == CODE_FOR_vsx_xxpermdi_v2di
10816 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
10817 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
10818 || icode == CODE_FOR_vsx_xxpermdi_v1ti
10819 || icode == CODE_FOR_vsx_xxpermdi_v4sf
10820 || icode == CODE_FOR_vsx_xxpermdi_v4si
10821 || icode == CODE_FOR_vsx_xxpermdi_v8hi
10822 || icode == CODE_FOR_vsx_xxpermdi_v16qi
10823 || icode == CODE_FOR_vsx_xxsldwi_v16qi
10824 || icode == CODE_FOR_vsx_xxsldwi_v8hi
10825 || icode == CODE_FOR_vsx_xxsldwi_v4si
10826 || icode == CODE_FOR_vsx_xxsldwi_v4sf
10827 || icode == CODE_FOR_vsx_xxsldwi_v2di
10828 || icode == CODE_FOR_vsx_xxsldwi_v2df)
10829 {
10830 /* Only allow 2-bit unsigned literals. */
10831 STRIP_NOPS (arg2);
10832 if (TREE_CODE (arg2) != INTEGER_CST
10833 || TREE_INT_CST_LOW (arg2) & ~0x3)
10834 {
10835 error ("argument 3 must be a 2-bit unsigned literal");
10836 return CONST0_RTX (tmode);
10837 }
10838 }
10839 else if (icode == CODE_FOR_vsx_set_v2df
10840 || icode == CODE_FOR_vsx_set_v2di
10841 || icode == CODE_FOR_bcdadd_v16qi
10842 || icode == CODE_FOR_bcdadd_v1ti
10843 || icode == CODE_FOR_bcdadd_lt_v16qi
10844 || icode == CODE_FOR_bcdadd_lt_v1ti
10845 || icode == CODE_FOR_bcdadd_eq_v16qi
10846 || icode == CODE_FOR_bcdadd_eq_v1ti
10847 || icode == CODE_FOR_bcdadd_gt_v16qi
10848 || icode == CODE_FOR_bcdadd_gt_v1ti
10849 || icode == CODE_FOR_bcdsub_v16qi
10850 || icode == CODE_FOR_bcdsub_v1ti
10851 || icode == CODE_FOR_bcdsub_lt_v16qi
10852 || icode == CODE_FOR_bcdsub_lt_v1ti
10853 || icode == CODE_FOR_bcdsub_eq_v16qi
10854 || icode == CODE_FOR_bcdsub_eq_v1ti
10855 || icode == CODE_FOR_bcdsub_gt_v16qi
10856 || icode == CODE_FOR_bcdsub_gt_v1ti)
10857 {
10858 /* Only allow 1-bit unsigned literals. */
10859 STRIP_NOPS (arg2);
10860 if (TREE_CODE (arg2) != INTEGER_CST
10861 || TREE_INT_CST_LOW (arg2) & ~0x1)
10862 {
10863 error ("argument 3 must be a 1-bit unsigned literal");
10864 return CONST0_RTX (tmode);
10865 }
10866 }
10867 else if (icode == CODE_FOR_dfp_ddedpd_dd
10868 || icode == CODE_FOR_dfp_ddedpd_td)
10869 {
10870 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
10871 STRIP_NOPS (arg0);
10872 if (TREE_CODE (arg0) != INTEGER_CST
10873 || TREE_INT_CST_LOW (arg2) & ~0x3)
10874 {
10875 error ("argument 1 must be 0 or 2");
10876 return CONST0_RTX (tmode);
10877 }
10878 }
10879 else if (icode == CODE_FOR_dfp_denbcd_dd
10880 || icode == CODE_FOR_dfp_denbcd_td
10881 || icode == CODE_FOR_dfp_denbcd_v16qi)
10882 {
10883 /* Only allow 1-bit unsigned literals. */
10884 STRIP_NOPS (arg0);
10885 if (TREE_CODE (arg0) != INTEGER_CST
10886 || TREE_INT_CST_LOW (arg0) & ~0x1)
10887 {
10888 error ("argument 1 must be a 1-bit unsigned literal");
10889 return CONST0_RTX (tmode);
10890 }
10891 }
10892 else if (icode == CODE_FOR_dfp_dscli_dd
10893 || icode == CODE_FOR_dfp_dscli_td
10894 || icode == CODE_FOR_dfp_dscri_dd
10895 || icode == CODE_FOR_dfp_dscri_td)
10896 {
10897 /* Only allow 6-bit unsigned literals. */
10898 STRIP_NOPS (arg1);
10899 if (TREE_CODE (arg1) != INTEGER_CST
10900 || TREE_INT_CST_LOW (arg1) & ~0x3f)
10901 {
10902 error ("argument 2 must be a 6-bit unsigned literal");
10903 return CONST0_RTX (tmode);
10904 }
10905 }
10906 else if (icode == CODE_FOR_crypto_vshasigmaw
10907 || icode == CODE_FOR_crypto_vshasigmad)
10908 {
10909 /* Check whether the 2nd and 3rd arguments are integer constants and in
10910 range and prepare arguments. */
10911 STRIP_NOPS (arg1);
10912 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
10913 {
10914 error ("argument 2 must be 0 or 1");
10915 return CONST0_RTX (tmode);
10916 }
10917
10918 STRIP_NOPS (arg2);
10919 if (TREE_CODE (arg2) != INTEGER_CST
10920 || wi::geu_p (wi::to_wide (arg2), 16))
10921 {
10922 error ("argument 3 must be in the range [0, 15]");
10923 return CONST0_RTX (tmode);
10924 }
10925 }
10926
10927 if (target == 0
10928 || GET_MODE (target) != tmode
10929 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10930 target = gen_reg_rtx (tmode);
10931
10932 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10933 op0 = copy_to_mode_reg (mode0, op0);
10934 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10935 op1 = copy_to_mode_reg (mode1, op1);
10936 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10937 op2 = copy_to_mode_reg (mode2, op2);
10938
10939 pat = GEN_FCN (icode) (target, op0, op1, op2);
10940 if (! pat)
10941 return 0;
10942 emit_insn (pat);
10943
10944 return target;
10945 }
10946
10947
10948 /* Expand the dst builtins. */
10949 static rtx
altivec_expand_dst_builtin(tree exp,rtx target ATTRIBUTE_UNUSED,bool * expandedp)10950 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10951 bool *expandedp)
10952 {
10953 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10954 enum rs6000_builtins fcode
10955 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
10956 tree arg0, arg1, arg2;
10957 machine_mode mode0, mode1;
10958 rtx pat, op0, op1, op2;
10959 const struct builtin_description *d;
10960 size_t i;
10961
10962 *expandedp = false;
10963
10964 /* Handle DST variants. */
10965 d = bdesc_dst;
10966 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10967 if (d->code == fcode)
10968 {
10969 arg0 = CALL_EXPR_ARG (exp, 0);
10970 arg1 = CALL_EXPR_ARG (exp, 1);
10971 arg2 = CALL_EXPR_ARG (exp, 2);
10972 op0 = expand_normal (arg0);
10973 op1 = expand_normal (arg1);
10974 op2 = expand_normal (arg2);
10975 mode0 = insn_data[d->icode].operand[0].mode;
10976 mode1 = insn_data[d->icode].operand[1].mode;
10977
10978 /* Invalid arguments, bail out before generating bad rtl. */
10979 if (arg0 == error_mark_node
10980 || arg1 == error_mark_node
10981 || arg2 == error_mark_node)
10982 return const0_rtx;
10983
10984 *expandedp = true;
10985 STRIP_NOPS (arg2);
10986 if (TREE_CODE (arg2) != INTEGER_CST
10987 || TREE_INT_CST_LOW (arg2) & ~0x3)
10988 {
10989 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
10990 return const0_rtx;
10991 }
10992
10993 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
10994 op0 = copy_to_mode_reg (Pmode, op0);
10995 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
10996 op1 = copy_to_mode_reg (mode1, op1);
10997
10998 pat = GEN_FCN (d->icode) (op0, op1, op2);
10999 if (pat != 0)
11000 emit_insn (pat);
11001
11002 return NULL_RTX;
11003 }
11004
11005 return NULL_RTX;
11006 }
11007
11008 /* Expand vec_init builtin. */
11009 static rtx
altivec_expand_vec_init_builtin(tree type,tree exp,rtx target)11010 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
11011 {
11012 machine_mode tmode = TYPE_MODE (type);
11013 machine_mode inner_mode = GET_MODE_INNER (tmode);
11014 int i, n_elt = GET_MODE_NUNITS (tmode);
11015
11016 gcc_assert (VECTOR_MODE_P (tmode));
11017 gcc_assert (n_elt == call_expr_nargs (exp));
11018
11019 if (!target || !register_operand (target, tmode))
11020 target = gen_reg_rtx (tmode);
11021
11022 /* If we have a vector compromised of a single element, such as V1TImode, do
11023 the initialization directly. */
11024 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
11025 {
11026 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
11027 emit_move_insn (target, gen_lowpart (tmode, x));
11028 }
11029 else
11030 {
11031 rtvec v = rtvec_alloc (n_elt);
11032
11033 for (i = 0; i < n_elt; ++i)
11034 {
11035 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
11036 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
11037 }
11038
11039 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
11040 }
11041
11042 return target;
11043 }
11044
11045 /* Return the integer constant in ARG. Constrain it to be in the range
11046 of the subparts of VEC_TYPE; issue an error if not. */
11047
11048 static int
get_element_number(tree vec_type,tree arg)11049 get_element_number (tree vec_type, tree arg)
11050 {
11051 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
11052
11053 if (!tree_fits_uhwi_p (arg)
11054 || (elt = tree_to_uhwi (arg), elt > max))
11055 {
11056 error ("selector must be an integer constant in the range [0, %wi]", max);
11057 return 0;
11058 }
11059
11060 return elt;
11061 }
11062
11063 /* Expand vec_set builtin. */
11064 static rtx
altivec_expand_vec_set_builtin(tree exp)11065 altivec_expand_vec_set_builtin (tree exp)
11066 {
11067 machine_mode tmode, mode1;
11068 tree arg0, arg1, arg2;
11069 int elt;
11070 rtx op0, op1;
11071
11072 arg0 = CALL_EXPR_ARG (exp, 0);
11073 arg1 = CALL_EXPR_ARG (exp, 1);
11074 arg2 = CALL_EXPR_ARG (exp, 2);
11075
11076 tmode = TYPE_MODE (TREE_TYPE (arg0));
11077 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
11078 gcc_assert (VECTOR_MODE_P (tmode));
11079
11080 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
11081 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
11082 elt = get_element_number (TREE_TYPE (arg0), arg2);
11083
11084 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
11085 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
11086
11087 op0 = force_reg (tmode, op0);
11088 op1 = force_reg (mode1, op1);
11089
11090 rs6000_expand_vector_set (op0, op1, GEN_INT (elt));
11091
11092 return op0;
11093 }
11094
11095 /* Expand vec_ext builtin. */
11096 static rtx
altivec_expand_vec_ext_builtin(tree exp,rtx target)11097 altivec_expand_vec_ext_builtin (tree exp, rtx target)
11098 {
11099 machine_mode tmode, mode0;
11100 tree arg0, arg1;
11101 rtx op0;
11102 rtx op1;
11103
11104 arg0 = CALL_EXPR_ARG (exp, 0);
11105 arg1 = CALL_EXPR_ARG (exp, 1);
11106
11107 op0 = expand_normal (arg0);
11108 op1 = expand_normal (arg1);
11109
11110 if (TREE_CODE (arg1) == INTEGER_CST)
11111 {
11112 unsigned HOST_WIDE_INT elt;
11113 unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0));
11114 unsigned int truncated_selector;
11115 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0)
11116 returns low-order bits of INTEGER_CST for modulo indexing. */
11117 elt = TREE_INT_CST_LOW (arg1);
11118 truncated_selector = elt % size;
11119 op1 = GEN_INT (truncated_selector);
11120 }
11121
11122 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
11123 mode0 = TYPE_MODE (TREE_TYPE (arg0));
11124 gcc_assert (VECTOR_MODE_P (mode0));
11125
11126 op0 = force_reg (mode0, op0);
11127
11128 if (optimize || !target || !register_operand (target, tmode))
11129 target = gen_reg_rtx (tmode);
11130
11131 rs6000_expand_vector_extract (target, op0, op1);
11132
11133 return target;
11134 }
11135
11136 /* Expand the builtin in EXP and store the result in TARGET. Store
11137 true in *EXPANDEDP if we found a builtin to expand. */
11138 static rtx
altivec_expand_builtin(tree exp,rtx target,bool * expandedp)11139 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
11140 {
11141 const struct builtin_description *d;
11142 size_t i;
11143 enum insn_code icode;
11144 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11145 tree arg0, arg1, arg2;
11146 rtx op0, pat;
11147 machine_mode tmode, mode0;
11148 enum rs6000_builtins fcode
11149 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
11150
11151 if (rs6000_overloaded_builtin_p (fcode))
11152 {
11153 *expandedp = true;
11154 error ("unresolved overload for Altivec builtin %qF", fndecl);
11155
11156 /* Given it is invalid, just generate a normal call. */
11157 return expand_call (exp, target, false);
11158 }
11159
11160 target = altivec_expand_dst_builtin (exp, target, expandedp);
11161 if (*expandedp)
11162 return target;
11163
11164 *expandedp = true;
11165
11166 switch (fcode)
11167 {
11168 case ALTIVEC_BUILTIN_STVX_V2DF:
11169 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
11170 case ALTIVEC_BUILTIN_STVX_V2DI:
11171 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
11172 case ALTIVEC_BUILTIN_STVX_V4SF:
11173 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
11174 case ALTIVEC_BUILTIN_STVX:
11175 case ALTIVEC_BUILTIN_STVX_V4SI:
11176 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
11177 case ALTIVEC_BUILTIN_STVX_V8HI:
11178 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
11179 case ALTIVEC_BUILTIN_STVX_V16QI:
11180 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
11181 case ALTIVEC_BUILTIN_STVEBX:
11182 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
11183 case ALTIVEC_BUILTIN_STVEHX:
11184 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
11185 case ALTIVEC_BUILTIN_STVEWX:
11186 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
11187
11188 case P10_BUILTIN_TR_STXVRBX:
11189 return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrbx, exp);
11190 case P10_BUILTIN_TR_STXVRHX:
11191 return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrhx, exp);
11192 case P10_BUILTIN_TR_STXVRWX:
11193 return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrwx, exp);
11194 case P10_BUILTIN_TR_STXVRDX:
11195 return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrdx, exp);
11196
11197 case ALTIVEC_BUILTIN_STVXL_V2DF:
11198 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
11199 case ALTIVEC_BUILTIN_STVXL_V2DI:
11200 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
11201 case ALTIVEC_BUILTIN_STVXL_V4SF:
11202 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
11203 case ALTIVEC_BUILTIN_STVXL:
11204 case ALTIVEC_BUILTIN_STVXL_V4SI:
11205 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
11206 case ALTIVEC_BUILTIN_STVXL_V8HI:
11207 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
11208 case ALTIVEC_BUILTIN_STVXL_V16QI:
11209 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
11210
11211 case ALTIVEC_BUILTIN_STVLX:
11212 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
11213 case ALTIVEC_BUILTIN_STVLXL:
11214 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
11215 case ALTIVEC_BUILTIN_STVRX:
11216 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
11217 case ALTIVEC_BUILTIN_STVRXL:
11218 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
11219
11220 case P9V_BUILTIN_STXVL:
11221 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
11222
11223 case P9V_BUILTIN_XST_LEN_R:
11224 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
11225
11226 case VSX_BUILTIN_STXVD2X_V1TI:
11227 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
11228 case VSX_BUILTIN_STXVD2X_V2DF:
11229 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
11230 case VSX_BUILTIN_STXVD2X_V2DI:
11231 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
11232 case VSX_BUILTIN_STXVW4X_V4SF:
11233 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
11234 case VSX_BUILTIN_STXVW4X_V4SI:
11235 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
11236 case VSX_BUILTIN_STXVW4X_V8HI:
11237 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
11238 case VSX_BUILTIN_STXVW4X_V16QI:
11239 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
11240
11241 /* For the following on big endian, it's ok to use any appropriate
11242 unaligned-supporting store, so use a generic expander. For
11243 little-endian, the exact element-reversing instruction must
11244 be used. */
11245 case VSX_BUILTIN_ST_ELEMREV_V1TI:
11246 {
11247 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
11248 : CODE_FOR_vsx_st_elemrev_v1ti);
11249 return altivec_expand_stv_builtin (code, exp);
11250 }
11251 case VSX_BUILTIN_ST_ELEMREV_V2DF:
11252 {
11253 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
11254 : CODE_FOR_vsx_st_elemrev_v2df);
11255 return altivec_expand_stv_builtin (code, exp);
11256 }
11257 case VSX_BUILTIN_ST_ELEMREV_V2DI:
11258 {
11259 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
11260 : CODE_FOR_vsx_st_elemrev_v2di);
11261 return altivec_expand_stv_builtin (code, exp);
11262 }
11263 case VSX_BUILTIN_ST_ELEMREV_V4SF:
11264 {
11265 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
11266 : CODE_FOR_vsx_st_elemrev_v4sf);
11267 return altivec_expand_stv_builtin (code, exp);
11268 }
11269 case VSX_BUILTIN_ST_ELEMREV_V4SI:
11270 {
11271 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
11272 : CODE_FOR_vsx_st_elemrev_v4si);
11273 return altivec_expand_stv_builtin (code, exp);
11274 }
11275 case VSX_BUILTIN_ST_ELEMREV_V8HI:
11276 {
11277 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
11278 : CODE_FOR_vsx_st_elemrev_v8hi);
11279 return altivec_expand_stv_builtin (code, exp);
11280 }
11281 case VSX_BUILTIN_ST_ELEMREV_V16QI:
11282 {
11283 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
11284 : CODE_FOR_vsx_st_elemrev_v16qi);
11285 return altivec_expand_stv_builtin (code, exp);
11286 }
11287
11288 case ALTIVEC_BUILTIN_MFVSCR:
11289 icode = CODE_FOR_altivec_mfvscr;
11290 tmode = insn_data[icode].operand[0].mode;
11291
11292 if (target == 0
11293 || GET_MODE (target) != tmode
11294 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11295 target = gen_reg_rtx (tmode);
11296
11297 pat = GEN_FCN (icode) (target);
11298 if (! pat)
11299 return 0;
11300 emit_insn (pat);
11301 return target;
11302
11303 case ALTIVEC_BUILTIN_MTVSCR:
11304 icode = CODE_FOR_altivec_mtvscr;
11305 arg0 = CALL_EXPR_ARG (exp, 0);
11306 op0 = expand_normal (arg0);
11307 mode0 = insn_data[icode].operand[0].mode;
11308
11309 /* If we got invalid arguments bail out before generating bad rtl. */
11310 if (arg0 == error_mark_node)
11311 return const0_rtx;
11312
11313 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
11314 op0 = copy_to_mode_reg (mode0, op0);
11315
11316 pat = GEN_FCN (icode) (op0);
11317 if (pat)
11318 emit_insn (pat);
11319 return NULL_RTX;
11320
11321 case ALTIVEC_BUILTIN_DSSALL:
11322 emit_insn (gen_altivec_dssall ());
11323 return NULL_RTX;
11324
11325 case ALTIVEC_BUILTIN_DSS:
11326 icode = CODE_FOR_altivec_dss;
11327 arg0 = CALL_EXPR_ARG (exp, 0);
11328 STRIP_NOPS (arg0);
11329 op0 = expand_normal (arg0);
11330 mode0 = insn_data[icode].operand[0].mode;
11331
11332 /* If we got invalid arguments bail out before generating bad rtl. */
11333 if (arg0 == error_mark_node)
11334 return const0_rtx;
11335
11336 if (TREE_CODE (arg0) != INTEGER_CST
11337 || TREE_INT_CST_LOW (arg0) & ~0x3)
11338 {
11339 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
11340 return const0_rtx;
11341 }
11342
11343 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
11344 op0 = copy_to_mode_reg (mode0, op0);
11345
11346 emit_insn (gen_altivec_dss (op0));
11347 return NULL_RTX;
11348
11349 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
11350 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
11351 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
11352 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
11353 case VSX_BUILTIN_VEC_INIT_V2DF:
11354 case VSX_BUILTIN_VEC_INIT_V2DI:
11355 case VSX_BUILTIN_VEC_INIT_V1TI:
11356 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
11357
11358 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
11359 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
11360 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
11361 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
11362 case VSX_BUILTIN_VEC_SET_V2DF:
11363 case VSX_BUILTIN_VEC_SET_V2DI:
11364 case VSX_BUILTIN_VEC_SET_V1TI:
11365 return altivec_expand_vec_set_builtin (exp);
11366
11367 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
11368 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
11369 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
11370 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
11371 case VSX_BUILTIN_VEC_EXT_V2DF:
11372 case VSX_BUILTIN_VEC_EXT_V2DI:
11373 case VSX_BUILTIN_VEC_EXT_V1TI:
11374 return altivec_expand_vec_ext_builtin (exp, target);
11375
11376 case P9V_BUILTIN_VEC_EXTRACT4B:
11377 arg1 = CALL_EXPR_ARG (exp, 1);
11378 STRIP_NOPS (arg1);
11379
11380 /* Generate a normal call if it is invalid. */
11381 if (arg1 == error_mark_node)
11382 return expand_call (exp, target, false);
11383
11384 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
11385 {
11386 error ("second argument to %qs must be [0, 12]", "vec_vextract4b");
11387 return expand_call (exp, target, false);
11388 }
11389 break;
11390
11391 case P9V_BUILTIN_VEC_INSERT4B:
11392 arg2 = CALL_EXPR_ARG (exp, 2);
11393 STRIP_NOPS (arg2);
11394
11395 /* Generate a normal call if it is invalid. */
11396 if (arg2 == error_mark_node)
11397 return expand_call (exp, target, false);
11398
11399 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
11400 {
11401 error ("third argument to %qs must be [0, 12]", "vec_vinsert4b");
11402 return expand_call (exp, target, false);
11403 }
11404 break;
11405
11406 case P10_BUILTIN_VEC_XXGENPCVM:
11407 arg1 = CALL_EXPR_ARG (exp, 1);
11408 STRIP_NOPS (arg1);
11409
11410 /* Generate a normal call if it is invalid. */
11411 if (arg1 == error_mark_node)
11412 return expand_call (exp, target, false);
11413
11414 if (TREE_CODE (arg1) != INTEGER_CST
11415 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 3))
11416 {
11417 size_t uns_fcode = (size_t) fcode;
11418 const char *name = rs6000_builtin_info[uns_fcode].name;
11419 error ("Second argument of %qs must be in the range [0, 3].", name);
11420 return expand_call (exp, target, false);
11421 }
11422 break;
11423
11424 default:
11425 break;
11426 /* Fall through. */
11427 }
11428
11429 /* Expand abs* operations. */
11430 d = bdesc_abs;
11431 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
11432 if (d->code == fcode)
11433 return altivec_expand_abs_builtin (d->icode, exp, target);
11434
11435 /* Expand the AltiVec predicates. */
11436 d = bdesc_altivec_preds;
11437 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
11438 if (d->code == fcode)
11439 return altivec_expand_predicate_builtin (d->icode, exp, target);
11440
11441 /* LV* are funky. We initialized them differently. */
11442 switch (fcode)
11443 {
11444 case ALTIVEC_BUILTIN_LVSL:
11445 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
11446 exp, target, false);
11447 case ALTIVEC_BUILTIN_LVSR:
11448 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
11449 exp, target, false);
11450 case ALTIVEC_BUILTIN_LVEBX:
11451 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
11452 exp, target, false);
11453 case ALTIVEC_BUILTIN_LVEHX:
11454 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
11455 exp, target, false);
11456 case ALTIVEC_BUILTIN_LVEWX:
11457 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
11458 exp, target, false);
11459 case P10_BUILTIN_SE_LXVRBX:
11460 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrbx,
11461 exp, target, false, true);
11462 case P10_BUILTIN_SE_LXVRHX:
11463 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrhx,
11464 exp, target, false, true);
11465 case P10_BUILTIN_SE_LXVRWX:
11466 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrwx,
11467 exp, target, false, true);
11468 case P10_BUILTIN_SE_LXVRDX:
11469 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrdx,
11470 exp, target, false, true);
11471 case P10_BUILTIN_ZE_LXVRBX:
11472 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrbx,
11473 exp, target, false, false);
11474 case P10_BUILTIN_ZE_LXVRHX:
11475 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrhx,
11476 exp, target, false, false);
11477 case P10_BUILTIN_ZE_LXVRWX:
11478 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrwx,
11479 exp, target, false, false);
11480 case P10_BUILTIN_ZE_LXVRDX:
11481 return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrdx,
11482 exp, target, false, false);
11483 case ALTIVEC_BUILTIN_LVXL_V2DF:
11484 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
11485 exp, target, false);
11486 case ALTIVEC_BUILTIN_LVXL_V2DI:
11487 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
11488 exp, target, false);
11489 case ALTIVEC_BUILTIN_LVXL_V4SF:
11490 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
11491 exp, target, false);
11492 case ALTIVEC_BUILTIN_LVXL:
11493 case ALTIVEC_BUILTIN_LVXL_V4SI:
11494 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
11495 exp, target, false);
11496 case ALTIVEC_BUILTIN_LVXL_V8HI:
11497 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
11498 exp, target, false);
11499 case ALTIVEC_BUILTIN_LVXL_V16QI:
11500 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
11501 exp, target, false);
11502 case ALTIVEC_BUILTIN_LVX_V1TI:
11503 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
11504 exp, target, false);
11505 case ALTIVEC_BUILTIN_LVX_V2DF:
11506 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
11507 exp, target, false);
11508 case ALTIVEC_BUILTIN_LVX_V2DI:
11509 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
11510 exp, target, false);
11511 case ALTIVEC_BUILTIN_LVX_V4SF:
11512 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
11513 exp, target, false);
11514 case ALTIVEC_BUILTIN_LVX:
11515 case ALTIVEC_BUILTIN_LVX_V4SI:
11516 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
11517 exp, target, false);
11518 case ALTIVEC_BUILTIN_LVX_V8HI:
11519 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
11520 exp, target, false);
11521 case ALTIVEC_BUILTIN_LVX_V16QI:
11522 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
11523 exp, target, false);
11524 case ALTIVEC_BUILTIN_LVLX:
11525 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
11526 exp, target, true);
11527 case ALTIVEC_BUILTIN_LVLXL:
11528 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
11529 exp, target, true);
11530 case ALTIVEC_BUILTIN_LVRX:
11531 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
11532 exp, target, true);
11533 case ALTIVEC_BUILTIN_LVRXL:
11534 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
11535 exp, target, true);
11536 case VSX_BUILTIN_LXVD2X_V1TI:
11537 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
11538 exp, target, false);
11539 case VSX_BUILTIN_LXVD2X_V2DF:
11540 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
11541 exp, target, false);
11542 case VSX_BUILTIN_LXVD2X_V2DI:
11543 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
11544 exp, target, false);
11545 case VSX_BUILTIN_LXVW4X_V4SF:
11546 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
11547 exp, target, false);
11548 case VSX_BUILTIN_LXVW4X_V4SI:
11549 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
11550 exp, target, false);
11551 case VSX_BUILTIN_LXVW4X_V8HI:
11552 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
11553 exp, target, false);
11554 case VSX_BUILTIN_LXVW4X_V16QI:
11555 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
11556 exp, target, false);
11557 /* For the following on big endian, it's ok to use any appropriate
11558 unaligned-supporting load, so use a generic expander. For
11559 little-endian, the exact element-reversing instruction must
11560 be used. */
11561 case VSX_BUILTIN_LD_ELEMREV_V2DF:
11562 {
11563 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
11564 : CODE_FOR_vsx_ld_elemrev_v2df);
11565 return altivec_expand_lv_builtin (code, exp, target, false);
11566 }
11567 case VSX_BUILTIN_LD_ELEMREV_V1TI:
11568 {
11569 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
11570 : CODE_FOR_vsx_ld_elemrev_v1ti);
11571 return altivec_expand_lv_builtin (code, exp, target, false);
11572 }
11573 case VSX_BUILTIN_LD_ELEMREV_V2DI:
11574 {
11575 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
11576 : CODE_FOR_vsx_ld_elemrev_v2di);
11577 return altivec_expand_lv_builtin (code, exp, target, false);
11578 }
11579 case VSX_BUILTIN_LD_ELEMREV_V4SF:
11580 {
11581 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
11582 : CODE_FOR_vsx_ld_elemrev_v4sf);
11583 return altivec_expand_lv_builtin (code, exp, target, false);
11584 }
11585 case VSX_BUILTIN_LD_ELEMREV_V4SI:
11586 {
11587 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
11588 : CODE_FOR_vsx_ld_elemrev_v4si);
11589 return altivec_expand_lv_builtin (code, exp, target, false);
11590 }
11591 case VSX_BUILTIN_LD_ELEMREV_V8HI:
11592 {
11593 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
11594 : CODE_FOR_vsx_ld_elemrev_v8hi);
11595 return altivec_expand_lv_builtin (code, exp, target, false);
11596 }
11597 case VSX_BUILTIN_LD_ELEMREV_V16QI:
11598 {
11599 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
11600 : CODE_FOR_vsx_ld_elemrev_v16qi);
11601 return altivec_expand_lv_builtin (code, exp, target, false);
11602 }
11603 break;
11604 default:
11605 break;
11606 /* Fall through. */
11607 }
11608
11609 *expandedp = false;
11610 return NULL_RTX;
11611 }
11612
11613 /* Check whether a builtin function is supported in this target
11614 configuration. */
11615 bool
rs6000_builtin_is_supported_p(enum rs6000_builtins fncode)11616 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
11617 {
11618 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
11619 if ((fnmask & rs6000_builtin_mask) != fnmask)
11620 return false;
11621 else
11622 return true;
11623 }
11624
11625 /* Raise an error message for a builtin function that is called without the
11626 appropriate target options being set. */
11627
11628 static void
rs6000_invalid_builtin(enum rs6000_builtins fncode)11629 rs6000_invalid_builtin (enum rs6000_builtins fncode)
11630 {
11631 size_t uns_fncode = (size_t) fncode;
11632 const char *name = rs6000_builtin_info[uns_fncode].name;
11633 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
11634
11635 gcc_assert (name != NULL);
11636 if ((fnmask & RS6000_BTM_CELL) != 0)
11637 error ("%qs is only valid for the cell processor", name);
11638 else if ((fnmask & RS6000_BTM_VSX) != 0)
11639 error ("%qs requires the %qs option", name, "-mvsx");
11640 else if ((fnmask & RS6000_BTM_HTM) != 0)
11641 error ("%qs requires the %qs option", name, "-mhtm");
11642 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
11643 error ("%qs requires the %qs option", name, "-maltivec");
11644 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
11645 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
11646 error ("%qs requires the %qs and %qs options", name, "-mhard-dfp",
11647 "-mpower8-vector");
11648 else if ((fnmask & RS6000_BTM_DFP) != 0)
11649 error ("%qs requires the %qs option", name, "-mhard-dfp");
11650 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
11651 error ("%qs requires the %qs option", name, "-mpower8-vector");
11652 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
11653 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
11654 error ("%qs requires the %qs and %qs options", name, "-mcpu=power9",
11655 "-m64");
11656 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
11657 error ("%qs requires the %qs option", name, "-mcpu=power9");
11658 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
11659 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
11660 error ("%qs requires the %qs and %qs options", name, "-mcpu=power9",
11661 "-m64");
11662 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
11663 error ("%qs requires the %qs option", name, "-mcpu=power9");
11664 else if ((fnmask & RS6000_BTM_P10) != 0)
11665 error ("%qs requires the %qs option", name, "-mcpu=power10");
11666 else if ((fnmask & RS6000_BTM_MMA) != 0)
11667 error ("%qs requires the %qs option", name, "-mmma");
11668 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
11669 {
11670 if (!TARGET_HARD_FLOAT)
11671 error ("%qs requires the %qs option", name, "-mhard-float");
11672 else
11673 error ("%qs requires the %qs option", name,
11674 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
11675 }
11676 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
11677 error ("%qs requires the %qs option", name, "-mhard-float");
11678 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
11679 error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name);
11680 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
11681 error ("%qs requires the %qs option", name, "%<-mfloat128%>");
11682 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
11683 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
11684 error ("%qs requires the %qs (or newer), and %qs or %qs options",
11685 name, "-mcpu=power7", "-m64", "-mpowerpc64");
11686 else
11687 error ("%qs is not supported with the current options", name);
11688 }
11689
11690 /* Target hook for early folding of built-ins, shamelessly stolen
11691 from ia64.c. */
11692
11693 tree
rs6000_fold_builtin(tree fndecl ATTRIBUTE_UNUSED,int n_args ATTRIBUTE_UNUSED,tree * args ATTRIBUTE_UNUSED,bool ignore ATTRIBUTE_UNUSED)11694 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
11695 int n_args ATTRIBUTE_UNUSED,
11696 tree *args ATTRIBUTE_UNUSED,
11697 bool ignore ATTRIBUTE_UNUSED)
11698 {
11699 #ifdef SUBTARGET_FOLD_BUILTIN
11700 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
11701 #else
11702 return NULL_TREE;
11703 #endif
11704 }
11705
11706 /* Helper function to sort out which built-ins may be valid without having
11707 a LHS. */
11708 static bool
rs6000_builtin_valid_without_lhs(enum rs6000_builtins fn_code)11709 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
11710 {
11711 /* Check for built-ins explicitly marked as a void function. */
11712 if (rs6000_builtin_info[fn_code].attr & RS6000_BTC_VOID)
11713 return true;
11714
11715 switch (fn_code)
11716 {
11717 case ALTIVEC_BUILTIN_STVX_V16QI:
11718 case ALTIVEC_BUILTIN_STVX_V8HI:
11719 case ALTIVEC_BUILTIN_STVX_V4SI:
11720 case ALTIVEC_BUILTIN_STVX_V4SF:
11721 case ALTIVEC_BUILTIN_STVX_V2DI:
11722 case ALTIVEC_BUILTIN_STVX_V2DF:
11723 case VSX_BUILTIN_STXVW4X_V16QI:
11724 case VSX_BUILTIN_STXVW4X_V8HI:
11725 case VSX_BUILTIN_STXVW4X_V4SF:
11726 case VSX_BUILTIN_STXVW4X_V4SI:
11727 case VSX_BUILTIN_STXVD2X_V2DF:
11728 case VSX_BUILTIN_STXVD2X_V2DI:
11729 return true;
11730 default:
11731 return false;
11732 }
11733 }
11734
11735 /* Helper function to handle the gimple folding of a vector compare
11736 operation. This sets up true/false vectors, and uses the
11737 VEC_COND_EXPR operation.
11738 CODE indicates which comparison is to be made. (EQ, GT, ...).
11739 TYPE indicates the type of the result.
11740 Code is inserted before GSI. */
11741 static tree
fold_build_vec_cmp(tree_code code,tree type,tree arg0,tree arg1,gimple_stmt_iterator * gsi)11742 fold_build_vec_cmp (tree_code code, tree type, tree arg0, tree arg1,
11743 gimple_stmt_iterator *gsi)
11744 {
11745 tree cmp_type = truth_type_for (type);
11746 tree zero_vec = build_zero_cst (type);
11747 tree minus_one_vec = build_minus_one_cst (type);
11748 tree temp = create_tmp_reg_or_ssa_name (cmp_type);
11749 gimple *g = gimple_build_assign (temp, code, arg0, arg1);
11750 gsi_insert_before (gsi, g, GSI_SAME_STMT);
11751 return fold_build3 (VEC_COND_EXPR, type, temp, minus_one_vec, zero_vec);
11752 }
11753
11754 /* Helper function to handle the in-between steps for the
11755 vector compare built-ins. */
11756 static void
fold_compare_helper(gimple_stmt_iterator * gsi,tree_code code,gimple * stmt)11757 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
11758 {
11759 tree arg0 = gimple_call_arg (stmt, 0);
11760 tree arg1 = gimple_call_arg (stmt, 1);
11761 tree lhs = gimple_call_lhs (stmt);
11762 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1, gsi);
11763 gimple *g = gimple_build_assign (lhs, cmp);
11764 gimple_set_location (g, gimple_location (stmt));
11765 gsi_replace (gsi, g, true);
11766 }
11767
11768 /* Helper function to map V2DF and V4SF types to their
11769 integral equivalents (V2DI and V4SI). */
map_to_integral_tree_type(tree input_tree_type)11770 tree map_to_integral_tree_type (tree input_tree_type)
11771 {
11772 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
11773 return input_tree_type;
11774 else
11775 {
11776 if (types_compatible_p (TREE_TYPE (input_tree_type),
11777 TREE_TYPE (V2DF_type_node)))
11778 return V2DI_type_node;
11779 else if (types_compatible_p (TREE_TYPE (input_tree_type),
11780 TREE_TYPE (V4SF_type_node)))
11781 return V4SI_type_node;
11782 else
11783 gcc_unreachable ();
11784 }
11785 }
11786
11787 /* Helper function to handle the vector merge[hl] built-ins. The
11788 implementation difference between h and l versions for this code are in
11789 the values used when building of the permute vector for high word versus
11790 low word merge. The variance is keyed off the use_high parameter. */
11791 static void
fold_mergehl_helper(gimple_stmt_iterator * gsi,gimple * stmt,int use_high)11792 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
11793 {
11794 tree arg0 = gimple_call_arg (stmt, 0);
11795 tree arg1 = gimple_call_arg (stmt, 1);
11796 tree lhs = gimple_call_lhs (stmt);
11797 tree lhs_type = TREE_TYPE (lhs);
11798 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
11799 int midpoint = n_elts / 2;
11800 int offset = 0;
11801
11802 if (use_high == 1)
11803 offset = midpoint;
11804
11805 /* The permute_type will match the lhs for integral types. For double and
11806 float types, the permute type needs to map to the V2 or V4 type that
11807 matches size. */
11808 tree permute_type;
11809 permute_type = map_to_integral_tree_type (lhs_type);
11810 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
11811
11812 for (int i = 0; i < midpoint; i++)
11813 {
11814 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
11815 offset + i));
11816 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
11817 offset + n_elts + i));
11818 }
11819
11820 tree permute = elts.build ();
11821
11822 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
11823 gimple_set_location (g, gimple_location (stmt));
11824 gsi_replace (gsi, g, true);
11825 }
11826
11827 /* Helper function to handle the vector merge[eo] built-ins. */
11828 static void
fold_mergeeo_helper(gimple_stmt_iterator * gsi,gimple * stmt,int use_odd)11829 fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
11830 {
11831 tree arg0 = gimple_call_arg (stmt, 0);
11832 tree arg1 = gimple_call_arg (stmt, 1);
11833 tree lhs = gimple_call_lhs (stmt);
11834 tree lhs_type = TREE_TYPE (lhs);
11835 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
11836
11837 /* The permute_type will match the lhs for integral types. For double and
11838 float types, the permute type needs to map to the V2 or V4 type that
11839 matches size. */
11840 tree permute_type;
11841 permute_type = map_to_integral_tree_type (lhs_type);
11842
11843 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
11844
11845 /* Build the permute vector. */
11846 for (int i = 0; i < n_elts / 2; i++)
11847 {
11848 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
11849 2*i + use_odd));
11850 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
11851 2*i + use_odd + n_elts));
11852 }
11853
11854 tree permute = elts.build ();
11855
11856 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
11857 gimple_set_location (g, gimple_location (stmt));
11858 gsi_replace (gsi, g, true);
11859 }
11860
11861 /* Expand the MMA built-ins early, so that we can convert the pass-by-reference
11862 __vector_quad arguments into pass-by-value arguments, leading to more
11863 efficient code generation. */
11864
11865 bool
rs6000_gimple_fold_mma_builtin(gimple_stmt_iterator * gsi)11866 rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi)
11867 {
11868 gimple *stmt = gsi_stmt (*gsi);
11869 tree fndecl = gimple_call_fndecl (stmt);
11870 enum rs6000_builtins fncode
11871 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
11872 unsigned attr = rs6000_builtin_info[fncode].attr;
11873
11874 if ((attr & RS6000_BTC_GIMPLE) == 0)
11875 return false;
11876
11877 unsigned nopnds = (attr & RS6000_BTC_OPND_MASK);
11878 gimple_seq new_seq = NULL;
11879 gimple *new_call;
11880 tree new_decl;
11881
11882 if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC
11883 || fncode == VSX_BUILTIN_DISASSEMBLE_PAIR)
11884 {
11885 /* This is an MMA disassemble built-in function. */
11886 push_gimplify_context (true);
11887 unsigned nvec = (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) ? 4 : 2;
11888 tree dst_ptr = gimple_call_arg (stmt, 0);
11889 tree src_ptr = gimple_call_arg (stmt, 1);
11890 tree src_type = TREE_TYPE (src_ptr);
11891 tree src = create_tmp_reg_or_ssa_name (TREE_TYPE (src_type));
11892 gimplify_assign (src, build_simple_mem_ref (src_ptr), &new_seq);
11893
11894 /* If we are not disassembling an accumulator/pair or our destination is
11895 another accumulator/pair, then just copy the entire thing as is. */
11896 if ((fncode == MMA_BUILTIN_DISASSEMBLE_ACC
11897 && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_quad_type_node)
11898 || (fncode == VSX_BUILTIN_DISASSEMBLE_PAIR
11899 && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_pair_type_node))
11900 {
11901 tree dst = build_simple_mem_ref (build1 (VIEW_CONVERT_EXPR,
11902 src_type, dst_ptr));
11903 gimplify_assign (dst, src, &new_seq);
11904 pop_gimplify_context (NULL);
11905 gsi_replace_with_seq (gsi, new_seq, true);
11906 return true;
11907 }
11908
11909 /* If we're disassembling an accumulator into a different type, we need
11910 to emit a xxmfacc instruction now, since we cannot do it later. */
11911 if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC)
11912 {
11913 new_decl = rs6000_builtin_decls[MMA_BUILTIN_XXMFACC_INTERNAL];
11914 new_call = gimple_build_call (new_decl, 1, src);
11915 src = create_tmp_reg_or_ssa_name (vector_quad_type_node);
11916 gimple_call_set_lhs (new_call, src);
11917 gimple_seq_add_stmt (&new_seq, new_call);
11918 }
11919
11920 /* Copy the accumulator/pair vector by vector. */
11921 new_decl = rs6000_builtin_decls[fncode + 1];
11922 tree dst_type = build_pointer_type_for_mode (unsigned_V16QI_type_node,
11923 ptr_mode, true);
11924 tree dst_base = build1 (VIEW_CONVERT_EXPR, dst_type, dst_ptr);
11925 for (unsigned i = 0; i < nvec; i++)
11926 {
11927 unsigned index = WORDS_BIG_ENDIAN ? i : nvec - 1 - i;
11928 tree dst = build2 (MEM_REF, unsigned_V16QI_type_node, dst_base,
11929 build_int_cst (dst_type, index * 16));
11930 tree dstssa = create_tmp_reg_or_ssa_name (unsigned_V16QI_type_node);
11931 new_call = gimple_build_call (new_decl, 2, src,
11932 build_int_cstu (uint16_type_node, i));
11933 gimple_call_set_lhs (new_call, dstssa);
11934 gimple_seq_add_stmt (&new_seq, new_call);
11935 gimplify_assign (dst, dstssa, &new_seq);
11936 }
11937 pop_gimplify_context (NULL);
11938 gsi_replace_with_seq (gsi, new_seq, true);
11939 return true;
11940 }
11941 else if (fncode == VSX_BUILTIN_LXVP)
11942 {
11943 push_gimplify_context (true);
11944 tree offset = gimple_call_arg (stmt, 0);
11945 tree ptr = gimple_call_arg (stmt, 1);
11946 tree lhs = gimple_call_lhs (stmt);
11947 tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR,
11948 TREE_TYPE (ptr), ptr, offset));
11949 gimplify_assign (lhs, mem, &new_seq);
11950 pop_gimplify_context (NULL);
11951 gsi_replace_with_seq (gsi, new_seq, true);
11952 return true;
11953 }
11954 else if (fncode == VSX_BUILTIN_STXVP)
11955 {
11956 push_gimplify_context (true);
11957 tree src = gimple_call_arg (stmt, 0);
11958 tree offset = gimple_call_arg (stmt, 1);
11959 tree ptr = gimple_call_arg (stmt, 2);
11960 tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR,
11961 TREE_TYPE (ptr), ptr, offset));
11962 gimplify_assign (mem, src, &new_seq);
11963 pop_gimplify_context (NULL);
11964 gsi_replace_with_seq (gsi, new_seq, true);
11965 return true;
11966 }
11967
11968 /* Convert this built-in into an internal version that uses pass-by-value
11969 arguments. The internal built-in follows immediately after this one. */
11970 new_decl = rs6000_builtin_decls[fncode + 1];
11971 tree lhs, op[MAX_MMA_OPERANDS];
11972 tree acc = gimple_call_arg (stmt, 0);
11973 push_gimplify_context (true);
11974
11975 if ((attr & RS6000_BTC_QUAD) != 0)
11976 {
11977 /* This built-in has a pass-by-reference accumulator input, so load it
11978 into a temporary accumulator for use as a pass-by-value input. */
11979 op[0] = create_tmp_reg_or_ssa_name (vector_quad_type_node);
11980 for (unsigned i = 1; i < nopnds; i++)
11981 op[i] = gimple_call_arg (stmt, i);
11982 gimplify_assign (op[0], build_simple_mem_ref (acc), &new_seq);
11983 }
11984 else
11985 {
11986 /* This built-in does not use its pass-by-reference accumulator argument
11987 as an input argument, so remove it from the input list. */
11988 nopnds--;
11989 for (unsigned i = 0; i < nopnds; i++)
11990 op[i] = gimple_call_arg (stmt, i + 1);
11991 }
11992
11993 switch (nopnds)
11994 {
11995 case 0:
11996 new_call = gimple_build_call (new_decl, 0);
11997 break;
11998 case 1:
11999 new_call = gimple_build_call (new_decl, 1, op[0]);
12000 break;
12001 case 2:
12002 new_call = gimple_build_call (new_decl, 2, op[0], op[1]);
12003 break;
12004 case 3:
12005 new_call = gimple_build_call (new_decl, 3, op[0], op[1], op[2]);
12006 break;
12007 case 4:
12008 new_call = gimple_build_call (new_decl, 4, op[0], op[1], op[2], op[3]);
12009 break;
12010 case 5:
12011 new_call = gimple_build_call (new_decl, 5, op[0], op[1], op[2], op[3],
12012 op[4]);
12013 break;
12014 case 6:
12015 new_call = gimple_build_call (new_decl, 6, op[0], op[1], op[2], op[3],
12016 op[4], op[5]);
12017 break;
12018 case 7:
12019 new_call = gimple_build_call (new_decl, 7, op[0], op[1], op[2], op[3],
12020 op[4], op[5], op[6]);
12021 break;
12022 default:
12023 gcc_unreachable ();
12024 }
12025
12026 if (fncode == VSX_BUILTIN_BUILD_PAIR || fncode == VSX_BUILTIN_ASSEMBLE_PAIR)
12027 lhs = create_tmp_reg_or_ssa_name (vector_pair_type_node);
12028 else
12029 lhs = create_tmp_reg_or_ssa_name (vector_quad_type_node);
12030 gimple_call_set_lhs (new_call, lhs);
12031 gimple_seq_add_stmt (&new_seq, new_call);
12032 gimplify_assign (build_simple_mem_ref (acc), lhs, &new_seq);
12033 pop_gimplify_context (NULL);
12034 gsi_replace_with_seq (gsi, new_seq, true);
12035
12036 return true;
12037 }
12038
12039 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
12040 a constant, use rs6000_fold_builtin.) */
12041
12042 bool
rs6000_gimple_fold_builtin(gimple_stmt_iterator * gsi)12043 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
12044 {
12045 gimple *stmt = gsi_stmt (*gsi);
12046 tree fndecl = gimple_call_fndecl (stmt);
12047 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
12048 enum rs6000_builtins fn_code
12049 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
12050 tree arg0, arg1, lhs, temp;
12051 enum tree_code bcode;
12052 gimple *g;
12053
12054 size_t uns_fncode = (size_t) fn_code;
12055 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
12056 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
12057 const char *fn_name2 = (icode != CODE_FOR_nothing)
12058 ? get_insn_name ((int) icode)
12059 : "nothing";
12060
12061 if (TARGET_DEBUG_BUILTIN)
12062 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
12063 fn_code, fn_name1, fn_name2);
12064
12065 if (!rs6000_fold_gimple)
12066 return false;
12067
12068 /* Prevent gimple folding for code that does not have a LHS, unless it is
12069 allowed per the rs6000_builtin_valid_without_lhs helper function. */
12070 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
12071 return false;
12072
12073 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
12074 if (!rs6000_builtin_is_supported_p (fn_code))
12075 return false;
12076
12077 if (rs6000_gimple_fold_mma_builtin (gsi))
12078 return true;
12079
12080 switch (fn_code)
12081 {
12082 /* Flavors of vec_add. We deliberately don't expand
12083 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
12084 TImode, resulting in much poorer code generation. */
12085 case ALTIVEC_BUILTIN_VADDUBM:
12086 case ALTIVEC_BUILTIN_VADDUHM:
12087 case ALTIVEC_BUILTIN_VADDUWM:
12088 case P8V_BUILTIN_VADDUDM:
12089 case ALTIVEC_BUILTIN_VADDFP:
12090 case VSX_BUILTIN_XVADDDP:
12091 bcode = PLUS_EXPR;
12092 do_binary:
12093 arg0 = gimple_call_arg (stmt, 0);
12094 arg1 = gimple_call_arg (stmt, 1);
12095 lhs = gimple_call_lhs (stmt);
12096 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs)))
12097 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs))))
12098 {
12099 /* Ensure the binary operation is performed in a type
12100 that wraps if it is integral type. */
12101 gimple_seq stmts = NULL;
12102 tree type = unsigned_type_for (TREE_TYPE (lhs));
12103 tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
12104 type, arg0);
12105 tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
12106 type, arg1);
12107 tree res = gimple_build (&stmts, gimple_location (stmt), bcode,
12108 type, uarg0, uarg1);
12109 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12110 g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR,
12111 build1 (VIEW_CONVERT_EXPR,
12112 TREE_TYPE (lhs), res));
12113 gsi_replace (gsi, g, true);
12114 return true;
12115 }
12116 g = gimple_build_assign (lhs, bcode, arg0, arg1);
12117 gimple_set_location (g, gimple_location (stmt));
12118 gsi_replace (gsi, g, true);
12119 return true;
12120 /* Flavors of vec_sub. We deliberately don't expand
12121 P8V_BUILTIN_VSUBUQM. */
12122 case ALTIVEC_BUILTIN_VSUBUBM:
12123 case ALTIVEC_BUILTIN_VSUBUHM:
12124 case ALTIVEC_BUILTIN_VSUBUWM:
12125 case P8V_BUILTIN_VSUBUDM:
12126 case ALTIVEC_BUILTIN_VSUBFP:
12127 case VSX_BUILTIN_XVSUBDP:
12128 bcode = MINUS_EXPR;
12129 goto do_binary;
12130 case VSX_BUILTIN_XVMULSP:
12131 case VSX_BUILTIN_XVMULDP:
12132 arg0 = gimple_call_arg (stmt, 0);
12133 arg1 = gimple_call_arg (stmt, 1);
12134 lhs = gimple_call_lhs (stmt);
12135 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
12136 gimple_set_location (g, gimple_location (stmt));
12137 gsi_replace (gsi, g, true);
12138 return true;
12139 /* Even element flavors of vec_mul (signed). */
12140 case ALTIVEC_BUILTIN_VMULESB:
12141 case ALTIVEC_BUILTIN_VMULESH:
12142 case P8V_BUILTIN_VMULESW:
12143 /* Even element flavors of vec_mul (unsigned). */
12144 case ALTIVEC_BUILTIN_VMULEUB:
12145 case ALTIVEC_BUILTIN_VMULEUH:
12146 case P8V_BUILTIN_VMULEUW:
12147 arg0 = gimple_call_arg (stmt, 0);
12148 arg1 = gimple_call_arg (stmt, 1);
12149 lhs = gimple_call_lhs (stmt);
12150 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
12151 gimple_set_location (g, gimple_location (stmt));
12152 gsi_replace (gsi, g, true);
12153 return true;
12154 /* Odd element flavors of vec_mul (signed). */
12155 case ALTIVEC_BUILTIN_VMULOSB:
12156 case ALTIVEC_BUILTIN_VMULOSH:
12157 case P8V_BUILTIN_VMULOSW:
12158 /* Odd element flavors of vec_mul (unsigned). */
12159 case ALTIVEC_BUILTIN_VMULOUB:
12160 case ALTIVEC_BUILTIN_VMULOUH:
12161 case P8V_BUILTIN_VMULOUW:
12162 arg0 = gimple_call_arg (stmt, 0);
12163 arg1 = gimple_call_arg (stmt, 1);
12164 lhs = gimple_call_lhs (stmt);
12165 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
12166 gimple_set_location (g, gimple_location (stmt));
12167 gsi_replace (gsi, g, true);
12168 return true;
12169 /* Flavors of vec_div (Integer). */
12170 case VSX_BUILTIN_DIV_V2DI:
12171 case VSX_BUILTIN_UDIV_V2DI:
12172 arg0 = gimple_call_arg (stmt, 0);
12173 arg1 = gimple_call_arg (stmt, 1);
12174 lhs = gimple_call_lhs (stmt);
12175 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
12176 gimple_set_location (g, gimple_location (stmt));
12177 gsi_replace (gsi, g, true);
12178 return true;
12179 /* Flavors of vec_div (Float). */
12180 case VSX_BUILTIN_XVDIVSP:
12181 case VSX_BUILTIN_XVDIVDP:
12182 arg0 = gimple_call_arg (stmt, 0);
12183 arg1 = gimple_call_arg (stmt, 1);
12184 lhs = gimple_call_lhs (stmt);
12185 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
12186 gimple_set_location (g, gimple_location (stmt));
12187 gsi_replace (gsi, g, true);
12188 return true;
12189 /* Flavors of vec_and. */
12190 case ALTIVEC_BUILTIN_VAND_V16QI_UNS:
12191 case ALTIVEC_BUILTIN_VAND_V16QI:
12192 case ALTIVEC_BUILTIN_VAND_V8HI_UNS:
12193 case ALTIVEC_BUILTIN_VAND_V8HI:
12194 case ALTIVEC_BUILTIN_VAND_V4SI_UNS:
12195 case ALTIVEC_BUILTIN_VAND_V4SI:
12196 case ALTIVEC_BUILTIN_VAND_V2DI_UNS:
12197 case ALTIVEC_BUILTIN_VAND_V2DI:
12198 case ALTIVEC_BUILTIN_VAND_V4SF:
12199 case ALTIVEC_BUILTIN_VAND_V2DF:
12200 arg0 = gimple_call_arg (stmt, 0);
12201 arg1 = gimple_call_arg (stmt, 1);
12202 lhs = gimple_call_lhs (stmt);
12203 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
12204 gimple_set_location (g, gimple_location (stmt));
12205 gsi_replace (gsi, g, true);
12206 return true;
12207 /* Flavors of vec_andc. */
12208 case ALTIVEC_BUILTIN_VANDC_V16QI_UNS:
12209 case ALTIVEC_BUILTIN_VANDC_V16QI:
12210 case ALTIVEC_BUILTIN_VANDC_V8HI_UNS:
12211 case ALTIVEC_BUILTIN_VANDC_V8HI:
12212 case ALTIVEC_BUILTIN_VANDC_V4SI_UNS:
12213 case ALTIVEC_BUILTIN_VANDC_V4SI:
12214 case ALTIVEC_BUILTIN_VANDC_V2DI_UNS:
12215 case ALTIVEC_BUILTIN_VANDC_V2DI:
12216 case ALTIVEC_BUILTIN_VANDC_V4SF:
12217 case ALTIVEC_BUILTIN_VANDC_V2DF:
12218 arg0 = gimple_call_arg (stmt, 0);
12219 arg1 = gimple_call_arg (stmt, 1);
12220 lhs = gimple_call_lhs (stmt);
12221 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
12222 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
12223 gimple_set_location (g, gimple_location (stmt));
12224 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12225 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
12226 gimple_set_location (g, gimple_location (stmt));
12227 gsi_replace (gsi, g, true);
12228 return true;
12229 /* Flavors of vec_nand. */
12230 case P8V_BUILTIN_VEC_NAND:
12231 case P8V_BUILTIN_NAND_V16QI_UNS:
12232 case P8V_BUILTIN_NAND_V16QI:
12233 case P8V_BUILTIN_NAND_V8HI_UNS:
12234 case P8V_BUILTIN_NAND_V8HI:
12235 case P8V_BUILTIN_NAND_V4SI_UNS:
12236 case P8V_BUILTIN_NAND_V4SI:
12237 case P8V_BUILTIN_NAND_V2DI_UNS:
12238 case P8V_BUILTIN_NAND_V2DI:
12239 case P8V_BUILTIN_NAND_V4SF:
12240 case P8V_BUILTIN_NAND_V2DF:
12241 arg0 = gimple_call_arg (stmt, 0);
12242 arg1 = gimple_call_arg (stmt, 1);
12243 lhs = gimple_call_lhs (stmt);
12244 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
12245 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
12246 gimple_set_location (g, gimple_location (stmt));
12247 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12248 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
12249 gimple_set_location (g, gimple_location (stmt));
12250 gsi_replace (gsi, g, true);
12251 return true;
12252 /* Flavors of vec_or. */
12253 case ALTIVEC_BUILTIN_VOR_V16QI_UNS:
12254 case ALTIVEC_BUILTIN_VOR_V16QI:
12255 case ALTIVEC_BUILTIN_VOR_V8HI_UNS:
12256 case ALTIVEC_BUILTIN_VOR_V8HI:
12257 case ALTIVEC_BUILTIN_VOR_V4SI_UNS:
12258 case ALTIVEC_BUILTIN_VOR_V4SI:
12259 case ALTIVEC_BUILTIN_VOR_V2DI_UNS:
12260 case ALTIVEC_BUILTIN_VOR_V2DI:
12261 case ALTIVEC_BUILTIN_VOR_V4SF:
12262 case ALTIVEC_BUILTIN_VOR_V2DF:
12263 arg0 = gimple_call_arg (stmt, 0);
12264 arg1 = gimple_call_arg (stmt, 1);
12265 lhs = gimple_call_lhs (stmt);
12266 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
12267 gimple_set_location (g, gimple_location (stmt));
12268 gsi_replace (gsi, g, true);
12269 return true;
12270 /* flavors of vec_orc. */
12271 case P8V_BUILTIN_ORC_V16QI_UNS:
12272 case P8V_BUILTIN_ORC_V16QI:
12273 case P8V_BUILTIN_ORC_V8HI_UNS:
12274 case P8V_BUILTIN_ORC_V8HI:
12275 case P8V_BUILTIN_ORC_V4SI_UNS:
12276 case P8V_BUILTIN_ORC_V4SI:
12277 case P8V_BUILTIN_ORC_V2DI_UNS:
12278 case P8V_BUILTIN_ORC_V2DI:
12279 case P8V_BUILTIN_ORC_V4SF:
12280 case P8V_BUILTIN_ORC_V2DF:
12281 arg0 = gimple_call_arg (stmt, 0);
12282 arg1 = gimple_call_arg (stmt, 1);
12283 lhs = gimple_call_lhs (stmt);
12284 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
12285 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
12286 gimple_set_location (g, gimple_location (stmt));
12287 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12288 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
12289 gimple_set_location (g, gimple_location (stmt));
12290 gsi_replace (gsi, g, true);
12291 return true;
12292 /* Flavors of vec_xor. */
12293 case ALTIVEC_BUILTIN_VXOR_V16QI_UNS:
12294 case ALTIVEC_BUILTIN_VXOR_V16QI:
12295 case ALTIVEC_BUILTIN_VXOR_V8HI_UNS:
12296 case ALTIVEC_BUILTIN_VXOR_V8HI:
12297 case ALTIVEC_BUILTIN_VXOR_V4SI_UNS:
12298 case ALTIVEC_BUILTIN_VXOR_V4SI:
12299 case ALTIVEC_BUILTIN_VXOR_V2DI_UNS:
12300 case ALTIVEC_BUILTIN_VXOR_V2DI:
12301 case ALTIVEC_BUILTIN_VXOR_V4SF:
12302 case ALTIVEC_BUILTIN_VXOR_V2DF:
12303 arg0 = gimple_call_arg (stmt, 0);
12304 arg1 = gimple_call_arg (stmt, 1);
12305 lhs = gimple_call_lhs (stmt);
12306 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
12307 gimple_set_location (g, gimple_location (stmt));
12308 gsi_replace (gsi, g, true);
12309 return true;
12310 /* Flavors of vec_nor. */
12311 case ALTIVEC_BUILTIN_VNOR_V16QI_UNS:
12312 case ALTIVEC_BUILTIN_VNOR_V16QI:
12313 case ALTIVEC_BUILTIN_VNOR_V8HI_UNS:
12314 case ALTIVEC_BUILTIN_VNOR_V8HI:
12315 case ALTIVEC_BUILTIN_VNOR_V4SI_UNS:
12316 case ALTIVEC_BUILTIN_VNOR_V4SI:
12317 case ALTIVEC_BUILTIN_VNOR_V2DI_UNS:
12318 case ALTIVEC_BUILTIN_VNOR_V2DI:
12319 case ALTIVEC_BUILTIN_VNOR_V4SF:
12320 case ALTIVEC_BUILTIN_VNOR_V2DF:
12321 arg0 = gimple_call_arg (stmt, 0);
12322 arg1 = gimple_call_arg (stmt, 1);
12323 lhs = gimple_call_lhs (stmt);
12324 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
12325 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
12326 gimple_set_location (g, gimple_location (stmt));
12327 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12328 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
12329 gimple_set_location (g, gimple_location (stmt));
12330 gsi_replace (gsi, g, true);
12331 return true;
12332 /* flavors of vec_abs. */
12333 case ALTIVEC_BUILTIN_ABS_V16QI:
12334 case ALTIVEC_BUILTIN_ABS_V8HI:
12335 case ALTIVEC_BUILTIN_ABS_V4SI:
12336 case ALTIVEC_BUILTIN_ABS_V4SF:
12337 case P8V_BUILTIN_ABS_V2DI:
12338 case VSX_BUILTIN_XVABSDP:
12339 arg0 = gimple_call_arg (stmt, 0);
12340 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
12341 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
12342 return false;
12343 lhs = gimple_call_lhs (stmt);
12344 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
12345 gimple_set_location (g, gimple_location (stmt));
12346 gsi_replace (gsi, g, true);
12347 return true;
12348 /* flavors of vec_min. */
12349 case VSX_BUILTIN_XVMINDP:
12350 case P8V_BUILTIN_VMINSD:
12351 case P8V_BUILTIN_VMINUD:
12352 case ALTIVEC_BUILTIN_VMINSB:
12353 case ALTIVEC_BUILTIN_VMINSH:
12354 case ALTIVEC_BUILTIN_VMINSW:
12355 case ALTIVEC_BUILTIN_VMINUB:
12356 case ALTIVEC_BUILTIN_VMINUH:
12357 case ALTIVEC_BUILTIN_VMINUW:
12358 case ALTIVEC_BUILTIN_VMINFP:
12359 arg0 = gimple_call_arg (stmt, 0);
12360 arg1 = gimple_call_arg (stmt, 1);
12361 lhs = gimple_call_lhs (stmt);
12362 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
12363 gimple_set_location (g, gimple_location (stmt));
12364 gsi_replace (gsi, g, true);
12365 return true;
12366 /* flavors of vec_max. */
12367 case VSX_BUILTIN_XVMAXDP:
12368 case P8V_BUILTIN_VMAXSD:
12369 case P8V_BUILTIN_VMAXUD:
12370 case ALTIVEC_BUILTIN_VMAXSB:
12371 case ALTIVEC_BUILTIN_VMAXSH:
12372 case ALTIVEC_BUILTIN_VMAXSW:
12373 case ALTIVEC_BUILTIN_VMAXUB:
12374 case ALTIVEC_BUILTIN_VMAXUH:
12375 case ALTIVEC_BUILTIN_VMAXUW:
12376 case ALTIVEC_BUILTIN_VMAXFP:
12377 arg0 = gimple_call_arg (stmt, 0);
12378 arg1 = gimple_call_arg (stmt, 1);
12379 lhs = gimple_call_lhs (stmt);
12380 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
12381 gimple_set_location (g, gimple_location (stmt));
12382 gsi_replace (gsi, g, true);
12383 return true;
12384 /* Flavors of vec_eqv. */
12385 case P8V_BUILTIN_EQV_V16QI:
12386 case P8V_BUILTIN_EQV_V8HI:
12387 case P8V_BUILTIN_EQV_V4SI:
12388 case P8V_BUILTIN_EQV_V4SF:
12389 case P8V_BUILTIN_EQV_V2DF:
12390 case P8V_BUILTIN_EQV_V2DI:
12391 arg0 = gimple_call_arg (stmt, 0);
12392 arg1 = gimple_call_arg (stmt, 1);
12393 lhs = gimple_call_lhs (stmt);
12394 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
12395 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
12396 gimple_set_location (g, gimple_location (stmt));
12397 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12398 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
12399 gimple_set_location (g, gimple_location (stmt));
12400 gsi_replace (gsi, g, true);
12401 return true;
12402 /* Flavors of vec_rotate_left. */
12403 case ALTIVEC_BUILTIN_VRLB:
12404 case ALTIVEC_BUILTIN_VRLH:
12405 case ALTIVEC_BUILTIN_VRLW:
12406 case P8V_BUILTIN_VRLD:
12407 arg0 = gimple_call_arg (stmt, 0);
12408 arg1 = gimple_call_arg (stmt, 1);
12409 lhs = gimple_call_lhs (stmt);
12410 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
12411 gimple_set_location (g, gimple_location (stmt));
12412 gsi_replace (gsi, g, true);
12413 return true;
12414 /* Flavors of vector shift right algebraic.
12415 vec_sra{b,h,w} -> vsra{b,h,w}. */
12416 case ALTIVEC_BUILTIN_VSRAB:
12417 case ALTIVEC_BUILTIN_VSRAH:
12418 case ALTIVEC_BUILTIN_VSRAW:
12419 case P8V_BUILTIN_VSRAD:
12420 {
12421 arg0 = gimple_call_arg (stmt, 0);
12422 arg1 = gimple_call_arg (stmt, 1);
12423 lhs = gimple_call_lhs (stmt);
12424 tree arg1_type = TREE_TYPE (arg1);
12425 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
12426 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
12427 location_t loc = gimple_location (stmt);
12428 /* Force arg1 into the range valid matching the arg0 type. */
12429 /* Build a vector consisting of the max valid bit-size values. */
12430 int n_elts = VECTOR_CST_NELTS (arg1);
12431 tree element_size = build_int_cst (unsigned_element_type,
12432 128 / n_elts);
12433 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
12434 for (int i = 0; i < n_elts; i++)
12435 elts.safe_push (element_size);
12436 tree modulo_tree = elts.build ();
12437 /* Modulo the provided shift value against that vector. */
12438 gimple_seq stmts = NULL;
12439 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
12440 unsigned_arg1_type, arg1);
12441 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
12442 unsigned_arg1_type, unsigned_arg1,
12443 modulo_tree);
12444 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12445 /* And finally, do the shift. */
12446 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1);
12447 gimple_set_location (g, loc);
12448 gsi_replace (gsi, g, true);
12449 return true;
12450 }
12451 /* Flavors of vector shift left.
12452 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
12453 case ALTIVEC_BUILTIN_VSLB:
12454 case ALTIVEC_BUILTIN_VSLH:
12455 case ALTIVEC_BUILTIN_VSLW:
12456 case P8V_BUILTIN_VSLD:
12457 {
12458 location_t loc;
12459 gimple_seq stmts = NULL;
12460 arg0 = gimple_call_arg (stmt, 0);
12461 tree arg0_type = TREE_TYPE (arg0);
12462 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
12463 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
12464 return false;
12465 arg1 = gimple_call_arg (stmt, 1);
12466 tree arg1_type = TREE_TYPE (arg1);
12467 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
12468 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
12469 loc = gimple_location (stmt);
12470 lhs = gimple_call_lhs (stmt);
12471 /* Force arg1 into the range valid matching the arg0 type. */
12472 /* Build a vector consisting of the max valid bit-size values. */
12473 int n_elts = VECTOR_CST_NELTS (arg1);
12474 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
12475 * BITS_PER_UNIT;
12476 tree element_size = build_int_cst (unsigned_element_type,
12477 tree_size_in_bits / n_elts);
12478 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
12479 for (int i = 0; i < n_elts; i++)
12480 elts.safe_push (element_size);
12481 tree modulo_tree = elts.build ();
12482 /* Modulo the provided shift value against that vector. */
12483 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
12484 unsigned_arg1_type, arg1);
12485 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
12486 unsigned_arg1_type, unsigned_arg1,
12487 modulo_tree);
12488 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12489 /* And finally, do the shift. */
12490 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
12491 gimple_set_location (g, gimple_location (stmt));
12492 gsi_replace (gsi, g, true);
12493 return true;
12494 }
12495 /* Flavors of vector shift right. */
12496 case ALTIVEC_BUILTIN_VSRB:
12497 case ALTIVEC_BUILTIN_VSRH:
12498 case ALTIVEC_BUILTIN_VSRW:
12499 case P8V_BUILTIN_VSRD:
12500 {
12501 arg0 = gimple_call_arg (stmt, 0);
12502 arg1 = gimple_call_arg (stmt, 1);
12503 lhs = gimple_call_lhs (stmt);
12504 tree arg1_type = TREE_TYPE (arg1);
12505 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
12506 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
12507 location_t loc = gimple_location (stmt);
12508 gimple_seq stmts = NULL;
12509 /* Convert arg0 to unsigned. */
12510 tree arg0_unsigned
12511 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
12512 unsigned_type_for (TREE_TYPE (arg0)), arg0);
12513 /* Force arg1 into the range valid matching the arg0 type. */
12514 /* Build a vector consisting of the max valid bit-size values. */
12515 int n_elts = VECTOR_CST_NELTS (arg1);
12516 tree element_size = build_int_cst (unsigned_element_type,
12517 128 / n_elts);
12518 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
12519 for (int i = 0; i < n_elts; i++)
12520 elts.safe_push (element_size);
12521 tree modulo_tree = elts.build ();
12522 /* Modulo the provided shift value against that vector. */
12523 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
12524 unsigned_arg1_type, arg1);
12525 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
12526 unsigned_arg1_type, unsigned_arg1,
12527 modulo_tree);
12528 /* Do the shift. */
12529 tree res
12530 = gimple_build (&stmts, RSHIFT_EXPR,
12531 TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1);
12532 /* Convert result back to the lhs type. */
12533 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
12534 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12535 update_call_from_tree (gsi, res);
12536 return true;
12537 }
12538 /* Vector loads. */
12539 case ALTIVEC_BUILTIN_LVX_V16QI:
12540 case ALTIVEC_BUILTIN_LVX_V8HI:
12541 case ALTIVEC_BUILTIN_LVX_V4SI:
12542 case ALTIVEC_BUILTIN_LVX_V4SF:
12543 case ALTIVEC_BUILTIN_LVX_V2DI:
12544 case ALTIVEC_BUILTIN_LVX_V2DF:
12545 case ALTIVEC_BUILTIN_LVX_V1TI:
12546 {
12547 arg0 = gimple_call_arg (stmt, 0); // offset
12548 arg1 = gimple_call_arg (stmt, 1); // address
12549 lhs = gimple_call_lhs (stmt);
12550 location_t loc = gimple_location (stmt);
12551 /* Since arg1 may be cast to a different type, just use ptr_type_node
12552 here instead of trying to enforce TBAA on pointer types. */
12553 tree arg1_type = ptr_type_node;
12554 tree lhs_type = TREE_TYPE (lhs);
12555 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
12556 the tree using the value from arg0. The resulting type will match
12557 the type of arg1. */
12558 gimple_seq stmts = NULL;
12559 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
12560 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
12561 arg1_type, arg1, temp_offset);
12562 /* Mask off any lower bits from the address. */
12563 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
12564 arg1_type, temp_addr,
12565 build_int_cst (arg1_type, -16));
12566 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12567 if (!is_gimple_mem_ref_addr (aligned_addr))
12568 {
12569 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
12570 gimple *g = gimple_build_assign (t, aligned_addr);
12571 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12572 aligned_addr = t;
12573 }
12574 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
12575 take an offset, but since we've already incorporated the offset
12576 above, here we just pass in a zero. */
12577 gimple *g
12578 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
12579 build_int_cst (arg1_type, 0)));
12580 gimple_set_location (g, loc);
12581 gsi_replace (gsi, g, true);
12582 return true;
12583 }
12584 /* Vector stores. */
12585 case ALTIVEC_BUILTIN_STVX_V16QI:
12586 case ALTIVEC_BUILTIN_STVX_V8HI:
12587 case ALTIVEC_BUILTIN_STVX_V4SI:
12588 case ALTIVEC_BUILTIN_STVX_V4SF:
12589 case ALTIVEC_BUILTIN_STVX_V2DI:
12590 case ALTIVEC_BUILTIN_STVX_V2DF:
12591 {
12592 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
12593 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
12594 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
12595 location_t loc = gimple_location (stmt);
12596 tree arg0_type = TREE_TYPE (arg0);
12597 /* Use ptr_type_node (no TBAA) for the arg2_type.
12598 FIXME: (Richard) "A proper fix would be to transition this type as
12599 seen from the frontend to GIMPLE, for example in a similar way we
12600 do for MEM_REFs by piggy-backing that on an extra argument, a
12601 constant zero pointer of the alias pointer type to use (which would
12602 also serve as a type indicator of the store itself). I'd use a
12603 target specific internal function for this (not sure if we can have
12604 those target specific, but I guess if it's folded away then that's
12605 fine) and get away with the overload set." */
12606 tree arg2_type = ptr_type_node;
12607 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
12608 the tree using the value from arg0. The resulting type will match
12609 the type of arg2. */
12610 gimple_seq stmts = NULL;
12611 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
12612 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
12613 arg2_type, arg2, temp_offset);
12614 /* Mask off any lower bits from the address. */
12615 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
12616 arg2_type, temp_addr,
12617 build_int_cst (arg2_type, -16));
12618 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12619 if (!is_gimple_mem_ref_addr (aligned_addr))
12620 {
12621 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
12622 gimple *g = gimple_build_assign (t, aligned_addr);
12623 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12624 aligned_addr = t;
12625 }
12626 /* The desired gimple result should be similar to:
12627 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
12628 gimple *g
12629 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
12630 build_int_cst (arg2_type, 0)), arg0);
12631 gimple_set_location (g, loc);
12632 gsi_replace (gsi, g, true);
12633 return true;
12634 }
12635
12636 /* unaligned Vector loads. */
12637 case VSX_BUILTIN_LXVW4X_V16QI:
12638 case VSX_BUILTIN_LXVW4X_V8HI:
12639 case VSX_BUILTIN_LXVW4X_V4SF:
12640 case VSX_BUILTIN_LXVW4X_V4SI:
12641 case VSX_BUILTIN_LXVD2X_V2DF:
12642 case VSX_BUILTIN_LXVD2X_V2DI:
12643 {
12644 arg0 = gimple_call_arg (stmt, 0); // offset
12645 arg1 = gimple_call_arg (stmt, 1); // address
12646 lhs = gimple_call_lhs (stmt);
12647 location_t loc = gimple_location (stmt);
12648 /* Since arg1 may be cast to a different type, just use ptr_type_node
12649 here instead of trying to enforce TBAA on pointer types. */
12650 tree arg1_type = ptr_type_node;
12651 tree lhs_type = TREE_TYPE (lhs);
12652 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
12653 required alignment (power) is 4 bytes regardless of data type. */
12654 tree align_ltype = build_aligned_type (lhs_type, 4);
12655 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
12656 the tree using the value from arg0. The resulting type will match
12657 the type of arg1. */
12658 gimple_seq stmts = NULL;
12659 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
12660 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
12661 arg1_type, arg1, temp_offset);
12662 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12663 if (!is_gimple_mem_ref_addr (temp_addr))
12664 {
12665 tree t = make_ssa_name (TREE_TYPE (temp_addr));
12666 gimple *g = gimple_build_assign (t, temp_addr);
12667 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12668 temp_addr = t;
12669 }
12670 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
12671 take an offset, but since we've already incorporated the offset
12672 above, here we just pass in a zero. */
12673 gimple *g;
12674 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
12675 build_int_cst (arg1_type, 0)));
12676 gimple_set_location (g, loc);
12677 gsi_replace (gsi, g, true);
12678 return true;
12679 }
12680
12681 /* unaligned Vector stores. */
12682 case VSX_BUILTIN_STXVW4X_V16QI:
12683 case VSX_BUILTIN_STXVW4X_V8HI:
12684 case VSX_BUILTIN_STXVW4X_V4SF:
12685 case VSX_BUILTIN_STXVW4X_V4SI:
12686 case VSX_BUILTIN_STXVD2X_V2DF:
12687 case VSX_BUILTIN_STXVD2X_V2DI:
12688 {
12689 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
12690 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
12691 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
12692 location_t loc = gimple_location (stmt);
12693 tree arg0_type = TREE_TYPE (arg0);
12694 /* Use ptr_type_node (no TBAA) for the arg2_type. */
12695 tree arg2_type = ptr_type_node;
12696 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
12697 required alignment (power) is 4 bytes regardless of data type. */
12698 tree align_stype = build_aligned_type (arg0_type, 4);
12699 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
12700 the tree using the value from arg1. */
12701 gimple_seq stmts = NULL;
12702 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
12703 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
12704 arg2_type, arg2, temp_offset);
12705 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12706 if (!is_gimple_mem_ref_addr (temp_addr))
12707 {
12708 tree t = make_ssa_name (TREE_TYPE (temp_addr));
12709 gimple *g = gimple_build_assign (t, temp_addr);
12710 gsi_insert_before (gsi, g, GSI_SAME_STMT);
12711 temp_addr = t;
12712 }
12713 gimple *g;
12714 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
12715 build_int_cst (arg2_type, 0)), arg0);
12716 gimple_set_location (g, loc);
12717 gsi_replace (gsi, g, true);
12718 return true;
12719 }
12720
12721 /* Vector Fused multiply-add (fma). */
12722 case ALTIVEC_BUILTIN_VMADDFP:
12723 case VSX_BUILTIN_XVMADDDP:
12724 case ALTIVEC_BUILTIN_VMLADDUHM:
12725 {
12726 arg0 = gimple_call_arg (stmt, 0);
12727 arg1 = gimple_call_arg (stmt, 1);
12728 tree arg2 = gimple_call_arg (stmt, 2);
12729 lhs = gimple_call_lhs (stmt);
12730 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
12731 gimple_call_set_lhs (g, lhs);
12732 gimple_call_set_nothrow (g, true);
12733 gimple_set_location (g, gimple_location (stmt));
12734 gsi_replace (gsi, g, true);
12735 return true;
12736 }
12737
12738 /* Vector compares; EQ, NE, GE, GT, LE. */
12739 case ALTIVEC_BUILTIN_VCMPEQUB:
12740 case ALTIVEC_BUILTIN_VCMPEQUH:
12741 case ALTIVEC_BUILTIN_VCMPEQUW:
12742 case P8V_BUILTIN_VCMPEQUD:
12743 case P10V_BUILTIN_VCMPEQUT:
12744 fold_compare_helper (gsi, EQ_EXPR, stmt);
12745 return true;
12746
12747 case P9V_BUILTIN_CMPNEB:
12748 case P9V_BUILTIN_CMPNEH:
12749 case P9V_BUILTIN_CMPNEW:
12750 case P10V_BUILTIN_CMPNET:
12751 fold_compare_helper (gsi, NE_EXPR, stmt);
12752 return true;
12753
12754 case VSX_BUILTIN_CMPGE_16QI:
12755 case VSX_BUILTIN_CMPGE_U16QI:
12756 case VSX_BUILTIN_CMPGE_8HI:
12757 case VSX_BUILTIN_CMPGE_U8HI:
12758 case VSX_BUILTIN_CMPGE_4SI:
12759 case VSX_BUILTIN_CMPGE_U4SI:
12760 case VSX_BUILTIN_CMPGE_2DI:
12761 case VSX_BUILTIN_CMPGE_U2DI:
12762 case P10V_BUILTIN_CMPGE_1TI:
12763 case P10V_BUILTIN_CMPGE_U1TI:
12764 fold_compare_helper (gsi, GE_EXPR, stmt);
12765 return true;
12766
12767 case ALTIVEC_BUILTIN_VCMPGTSB:
12768 case ALTIVEC_BUILTIN_VCMPGTUB:
12769 case ALTIVEC_BUILTIN_VCMPGTSH:
12770 case ALTIVEC_BUILTIN_VCMPGTUH:
12771 case ALTIVEC_BUILTIN_VCMPGTSW:
12772 case ALTIVEC_BUILTIN_VCMPGTUW:
12773 case P8V_BUILTIN_VCMPGTUD:
12774 case P8V_BUILTIN_VCMPGTSD:
12775 case P10V_BUILTIN_VCMPGTUT:
12776 case P10V_BUILTIN_VCMPGTST:
12777 fold_compare_helper (gsi, GT_EXPR, stmt);
12778 return true;
12779
12780 case VSX_BUILTIN_CMPLE_16QI:
12781 case VSX_BUILTIN_CMPLE_U16QI:
12782 case VSX_BUILTIN_CMPLE_8HI:
12783 case VSX_BUILTIN_CMPLE_U8HI:
12784 case VSX_BUILTIN_CMPLE_4SI:
12785 case VSX_BUILTIN_CMPLE_U4SI:
12786 case VSX_BUILTIN_CMPLE_2DI:
12787 case VSX_BUILTIN_CMPLE_U2DI:
12788 case P10V_BUILTIN_CMPLE_1TI:
12789 case P10V_BUILTIN_CMPLE_U1TI:
12790 fold_compare_helper (gsi, LE_EXPR, stmt);
12791 return true;
12792
12793 /* flavors of vec_splat_[us]{8,16,32}. */
12794 case ALTIVEC_BUILTIN_VSPLTISB:
12795 case ALTIVEC_BUILTIN_VSPLTISH:
12796 case ALTIVEC_BUILTIN_VSPLTISW:
12797 {
12798 arg0 = gimple_call_arg (stmt, 0);
12799 lhs = gimple_call_lhs (stmt);
12800
12801 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
12802 5-bit signed constant in range -16 to +15. */
12803 if (TREE_CODE (arg0) != INTEGER_CST
12804 || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15))
12805 return false;
12806 gimple_seq stmts = NULL;
12807 location_t loc = gimple_location (stmt);
12808 tree splat_value = gimple_convert (&stmts, loc,
12809 TREE_TYPE (TREE_TYPE (lhs)), arg0);
12810 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12811 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
12812 g = gimple_build_assign (lhs, splat_tree);
12813 gimple_set_location (g, gimple_location (stmt));
12814 gsi_replace (gsi, g, true);
12815 return true;
12816 }
12817
12818 /* Flavors of vec_splat. */
12819 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
12820 case ALTIVEC_BUILTIN_VSPLTB:
12821 case ALTIVEC_BUILTIN_VSPLTH:
12822 case ALTIVEC_BUILTIN_VSPLTW:
12823 case VSX_BUILTIN_XXSPLTD_V2DI:
12824 case VSX_BUILTIN_XXSPLTD_V2DF:
12825 {
12826 arg0 = gimple_call_arg (stmt, 0); /* input vector. */
12827 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */
12828 /* Only fold the vec_splat_*() if arg1 is both a constant value and
12829 is a valid index into the arg0 vector. */
12830 unsigned int n_elts = VECTOR_CST_NELTS (arg0);
12831 if (TREE_CODE (arg1) != INTEGER_CST
12832 || TREE_INT_CST_LOW (arg1) > (n_elts -1))
12833 return false;
12834 lhs = gimple_call_lhs (stmt);
12835 tree lhs_type = TREE_TYPE (lhs);
12836 tree arg0_type = TREE_TYPE (arg0);
12837 tree splat;
12838 if (TREE_CODE (arg0) == VECTOR_CST)
12839 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
12840 else
12841 {
12842 /* Determine (in bits) the length and start location of the
12843 splat value for a call to the tree_vec_extract helper. */
12844 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
12845 * BITS_PER_UNIT / n_elts;
12846 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
12847 tree len = build_int_cst (bitsizetype, splat_elem_size);
12848 tree start = build_int_cst (bitsizetype, splat_start_bit);
12849 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
12850 len, start);
12851 }
12852 /* And finally, build the new vector. */
12853 tree splat_tree = build_vector_from_val (lhs_type, splat);
12854 g = gimple_build_assign (lhs, splat_tree);
12855 gimple_set_location (g, gimple_location (stmt));
12856 gsi_replace (gsi, g, true);
12857 return true;
12858 }
12859
12860 /* vec_mergel (integrals). */
12861 case ALTIVEC_BUILTIN_VMRGLH:
12862 case ALTIVEC_BUILTIN_VMRGLW:
12863 case VSX_BUILTIN_XXMRGLW_4SI:
12864 case ALTIVEC_BUILTIN_VMRGLB:
12865 case VSX_BUILTIN_VEC_MERGEL_V2DI:
12866 case VSX_BUILTIN_XXMRGLW_4SF:
12867 case VSX_BUILTIN_VEC_MERGEL_V2DF:
12868 fold_mergehl_helper (gsi, stmt, 1);
12869 return true;
12870 /* vec_mergeh (integrals). */
12871 case ALTIVEC_BUILTIN_VMRGHH:
12872 case ALTIVEC_BUILTIN_VMRGHW:
12873 case VSX_BUILTIN_XXMRGHW_4SI:
12874 case ALTIVEC_BUILTIN_VMRGHB:
12875 case VSX_BUILTIN_VEC_MERGEH_V2DI:
12876 case VSX_BUILTIN_XXMRGHW_4SF:
12877 case VSX_BUILTIN_VEC_MERGEH_V2DF:
12878 fold_mergehl_helper (gsi, stmt, 0);
12879 return true;
12880
12881 /* Flavors of vec_mergee. */
12882 case P8V_BUILTIN_VMRGEW_V4SI:
12883 case P8V_BUILTIN_VMRGEW_V2DI:
12884 case P8V_BUILTIN_VMRGEW_V4SF:
12885 case P8V_BUILTIN_VMRGEW_V2DF:
12886 fold_mergeeo_helper (gsi, stmt, 0);
12887 return true;
12888 /* Flavors of vec_mergeo. */
12889 case P8V_BUILTIN_VMRGOW_V4SI:
12890 case P8V_BUILTIN_VMRGOW_V2DI:
12891 case P8V_BUILTIN_VMRGOW_V4SF:
12892 case P8V_BUILTIN_VMRGOW_V2DF:
12893 fold_mergeeo_helper (gsi, stmt, 1);
12894 return true;
12895
12896 /* d = vec_pack (a, b) */
12897 case P8V_BUILTIN_VPKUDUM:
12898 case ALTIVEC_BUILTIN_VPKUHUM:
12899 case ALTIVEC_BUILTIN_VPKUWUM:
12900 {
12901 arg0 = gimple_call_arg (stmt, 0);
12902 arg1 = gimple_call_arg (stmt, 1);
12903 lhs = gimple_call_lhs (stmt);
12904 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
12905 gimple_set_location (g, gimple_location (stmt));
12906 gsi_replace (gsi, g, true);
12907 return true;
12908 }
12909
12910 /* d = vec_unpackh (a) */
12911 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
12912 in this code is sensitive to endian-ness, and needs to be inverted to
12913 handle both LE and BE targets. */
12914 case ALTIVEC_BUILTIN_VUPKHSB:
12915 case ALTIVEC_BUILTIN_VUPKHSH:
12916 case P8V_BUILTIN_VUPKHSW:
12917 {
12918 arg0 = gimple_call_arg (stmt, 0);
12919 lhs = gimple_call_lhs (stmt);
12920 if (BYTES_BIG_ENDIAN)
12921 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
12922 else
12923 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
12924 gimple_set_location (g, gimple_location (stmt));
12925 gsi_replace (gsi, g, true);
12926 return true;
12927 }
12928 /* d = vec_unpackl (a) */
12929 case ALTIVEC_BUILTIN_VUPKLSB:
12930 case ALTIVEC_BUILTIN_VUPKLSH:
12931 case P8V_BUILTIN_VUPKLSW:
12932 {
12933 arg0 = gimple_call_arg (stmt, 0);
12934 lhs = gimple_call_lhs (stmt);
12935 if (BYTES_BIG_ENDIAN)
12936 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
12937 else
12938 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
12939 gimple_set_location (g, gimple_location (stmt));
12940 gsi_replace (gsi, g, true);
12941 return true;
12942 }
12943 /* There is no gimple type corresponding with pixel, so just return. */
12944 case ALTIVEC_BUILTIN_VUPKHPX:
12945 case ALTIVEC_BUILTIN_VUPKLPX:
12946 return false;
12947
12948 /* vec_perm. */
12949 case ALTIVEC_BUILTIN_VPERM_16QI:
12950 case ALTIVEC_BUILTIN_VPERM_8HI:
12951 case ALTIVEC_BUILTIN_VPERM_4SI:
12952 case ALTIVEC_BUILTIN_VPERM_2DI:
12953 case ALTIVEC_BUILTIN_VPERM_4SF:
12954 case ALTIVEC_BUILTIN_VPERM_2DF:
12955 {
12956 arg0 = gimple_call_arg (stmt, 0);
12957 arg1 = gimple_call_arg (stmt, 1);
12958 tree permute = gimple_call_arg (stmt, 2);
12959 lhs = gimple_call_lhs (stmt);
12960 location_t loc = gimple_location (stmt);
12961 gimple_seq stmts = NULL;
12962 // convert arg0 and arg1 to match the type of the permute
12963 // for the VEC_PERM_EXPR operation.
12964 tree permute_type = (TREE_TYPE (permute));
12965 tree arg0_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
12966 permute_type, arg0);
12967 tree arg1_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
12968 permute_type, arg1);
12969 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
12970 permute_type, arg0_ptype, arg1_ptype,
12971 permute);
12972 // Convert the result back to the desired lhs type upon completion.
12973 tree temp = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR,
12974 TREE_TYPE (lhs), lhs_ptype);
12975 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
12976 g = gimple_build_assign (lhs, temp);
12977 gimple_set_location (g, loc);
12978 gsi_replace (gsi, g, true);
12979 return true;
12980 }
12981
12982 default:
12983 if (TARGET_DEBUG_BUILTIN)
12984 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
12985 fn_code, fn_name1, fn_name2);
12986 break;
12987 }
12988
12989 return false;
12990 }
12991
12992 /* Expand an expression EXP that calls a built-in function,
12993 with result going to TARGET if that's convenient
12994 (and in mode MODE if that's convenient).
12995 SUBTARGET may be used as the target for computing one of EXP's operands.
12996 IGNORE is nonzero if the value is to be ignored. */
12997
12998 rtx
rs6000_expand_builtin(tree exp,rtx target,rtx subtarget ATTRIBUTE_UNUSED,machine_mode mode ATTRIBUTE_UNUSED,int ignore ATTRIBUTE_UNUSED)12999 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13000 machine_mode mode ATTRIBUTE_UNUSED,
13001 int ignore ATTRIBUTE_UNUSED)
13002 {
13003 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13004 enum rs6000_builtins fcode
13005 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl);
13006 size_t uns_fcode = (size_t)fcode;
13007 const struct builtin_description *d;
13008 size_t i;
13009 rtx ret;
13010 bool success;
13011 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
13012 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
13013 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
13014
13015 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
13016 floating point type, depending on whether long double is the IBM extended
13017 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
13018 we only define one variant of the built-in function, and switch the code
13019 when defining it, rather than defining two built-ins and using the
13020 overload table in rs6000-c.c to switch between the two. If we don't have
13021 the proper assembler, don't do this switch because CODE_FOR_*kf* and
13022 CODE_FOR_*tf* will be CODE_FOR_nothing. */
13023 if (FLOAT128_IEEE_P (TFmode))
13024 switch (icode)
13025 {
13026 default:
13027 break;
13028
13029 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
13030 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
13031 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
13032 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
13033 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
13034 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
13035 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
13036 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
13037 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
13038 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
13039 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
13040 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
13041 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
13042
13043 case CODE_FOR_xscmpexpqp_eq_kf:
13044 icode = CODE_FOR_xscmpexpqp_eq_tf;
13045 break;
13046
13047 case CODE_FOR_xscmpexpqp_lt_kf:
13048 icode = CODE_FOR_xscmpexpqp_lt_tf;
13049 break;
13050
13051 case CODE_FOR_xscmpexpqp_gt_kf:
13052 icode = CODE_FOR_xscmpexpqp_gt_tf;
13053 break;
13054
13055 case CODE_FOR_xscmpexpqp_unordered_kf:
13056 icode = CODE_FOR_xscmpexpqp_unordered_tf;
13057 break;
13058 }
13059
13060 if (TARGET_DEBUG_BUILTIN)
13061 {
13062 const char *name1 = rs6000_builtin_info[uns_fcode].name;
13063 const char *name2 = (icode != CODE_FOR_nothing)
13064 ? get_insn_name ((int) icode)
13065 : "nothing";
13066 const char *name3;
13067
13068 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
13069 {
13070 default: name3 = "unknown"; break;
13071 case RS6000_BTC_SPECIAL: name3 = "special"; break;
13072 case RS6000_BTC_UNARY: name3 = "unary"; break;
13073 case RS6000_BTC_BINARY: name3 = "binary"; break;
13074 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
13075 case RS6000_BTC_QUATERNARY:name3 = "quaternary";break;
13076 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
13077 case RS6000_BTC_ABS: name3 = "abs"; break;
13078 case RS6000_BTC_DST: name3 = "dst"; break;
13079 }
13080
13081
13082 fprintf (stderr,
13083 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
13084 (name1) ? name1 : "---", fcode,
13085 (name2) ? name2 : "---", (int) icode,
13086 name3,
13087 func_valid_p ? "" : ", not valid");
13088 }
13089
13090 if (!func_valid_p)
13091 {
13092 rs6000_invalid_builtin (fcode);
13093
13094 /* Given it is invalid, just generate a normal call. */
13095 return expand_call (exp, target, ignore);
13096 }
13097
13098 switch (fcode)
13099 {
13100 case RS6000_BUILTIN_RECIP:
13101 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
13102
13103 case RS6000_BUILTIN_RECIPF:
13104 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
13105
13106 case RS6000_BUILTIN_RSQRTF:
13107 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
13108
13109 case RS6000_BUILTIN_RSQRT:
13110 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
13111
13112 case POWER7_BUILTIN_BPERMD:
13113 return rs6000_expand_binop_builtin (((TARGET_64BIT)
13114 ? CODE_FOR_bpermd_di
13115 : CODE_FOR_bpermd_si), exp, target);
13116
13117 case RS6000_BUILTIN_GET_TB:
13118 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
13119 target);
13120
13121 case RS6000_BUILTIN_MFTB:
13122 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
13123 ? CODE_FOR_rs6000_mftb_di
13124 : CODE_FOR_rs6000_mftb_si),
13125 target);
13126
13127 case RS6000_BUILTIN_MFFS:
13128 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
13129
13130 case RS6000_BUILTIN_MTFSB0:
13131 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
13132
13133 case RS6000_BUILTIN_MTFSB1:
13134 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
13135
13136 case RS6000_BUILTIN_SET_FPSCR_RN:
13137 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
13138 exp);
13139
13140 case RS6000_BUILTIN_SET_FPSCR_DRN:
13141 return
13142 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
13143 exp);
13144
13145 case RS6000_BUILTIN_MFFSL:
13146 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
13147
13148 case RS6000_BUILTIN_MTFSF:
13149 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
13150
13151 case RS6000_BUILTIN_CPU_INIT:
13152 case RS6000_BUILTIN_CPU_IS:
13153 case RS6000_BUILTIN_CPU_SUPPORTS:
13154 return cpu_expand_builtin (fcode, exp, target);
13155
13156 case MISC_BUILTIN_SPEC_BARRIER:
13157 {
13158 emit_insn (gen_speculation_barrier ());
13159 return NULL_RTX;
13160 }
13161
13162 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
13163 {
13164 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
13165 : (int) CODE_FOR_altivec_lvsl_direct);
13166 machine_mode tmode = insn_data[icode2].operand[0].mode;
13167 machine_mode mode = insn_data[icode2].operand[1].mode;
13168 tree arg;
13169 rtx op, addr, pat;
13170
13171 gcc_assert (TARGET_ALTIVEC);
13172
13173 arg = CALL_EXPR_ARG (exp, 0);
13174 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
13175 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
13176 addr = memory_address (mode, op);
13177 /* We need to negate the address. */
13178 op = gen_reg_rtx (GET_MODE (addr));
13179 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
13180 op = gen_rtx_MEM (mode, op);
13181
13182 if (target == 0
13183 || GET_MODE (target) != tmode
13184 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
13185 target = gen_reg_rtx (tmode);
13186
13187 pat = GEN_FCN (icode2) (target, op);
13188 if (!pat)
13189 return 0;
13190 emit_insn (pat);
13191
13192 return target;
13193 }
13194
13195 case ALTIVEC_BUILTIN_VCFUX:
13196 case ALTIVEC_BUILTIN_VCFSX:
13197 case ALTIVEC_BUILTIN_VCTUXS:
13198 case ALTIVEC_BUILTIN_VCTSXS:
13199 /* FIXME: There's got to be a nicer way to handle this case than
13200 constructing a new CALL_EXPR. */
13201 if (call_expr_nargs (exp) == 1)
13202 {
13203 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
13204 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
13205 }
13206 break;
13207
13208 /* For the pack and unpack int128 routines, fix up the builtin so it
13209 uses the correct IBM128 type. */
13210 case MISC_BUILTIN_PACK_IF:
13211 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
13212 {
13213 icode = CODE_FOR_packtf;
13214 fcode = MISC_BUILTIN_PACK_TF;
13215 uns_fcode = (size_t)fcode;
13216 }
13217 break;
13218
13219 case MISC_BUILTIN_UNPACK_IF:
13220 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
13221 {
13222 icode = CODE_FOR_unpacktf;
13223 fcode = MISC_BUILTIN_UNPACK_TF;
13224 uns_fcode = (size_t)fcode;
13225 }
13226 break;
13227
13228 default:
13229 break;
13230 }
13231
13232 if (TARGET_MMA)
13233 {
13234 ret = mma_expand_builtin (exp, target, &success);
13235
13236 if (success)
13237 return ret;
13238 }
13239 if (TARGET_ALTIVEC)
13240 {
13241 ret = altivec_expand_builtin (exp, target, &success);
13242
13243 if (success)
13244 return ret;
13245 }
13246 if (TARGET_HTM)
13247 {
13248 ret = htm_expand_builtin (exp, target, &success);
13249
13250 if (success)
13251 return ret;
13252 }
13253
13254 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_OPND_MASK;
13255 /* RS6000_BTC_SPECIAL represents no-operand operators. */
13256 gcc_assert (attr == RS6000_BTC_UNARY
13257 || attr == RS6000_BTC_BINARY
13258 || attr == RS6000_BTC_TERNARY
13259 || attr == RS6000_BTC_QUATERNARY
13260 || attr == RS6000_BTC_SPECIAL);
13261
13262 /* Handle simple unary operations. */
13263 d = bdesc_1arg;
13264 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
13265 if (d->code == fcode)
13266 return rs6000_expand_unop_builtin (icode, exp, target);
13267
13268 /* Handle simple binary operations. */
13269 d = bdesc_2arg;
13270 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13271 if (d->code == fcode)
13272 return rs6000_expand_binop_builtin (icode, exp, target);
13273
13274 /* Handle simple ternary operations. */
13275 d = bdesc_3arg;
13276 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
13277 if (d->code == fcode)
13278 return rs6000_expand_ternop_builtin (icode, exp, target);
13279
13280 /* Handle simple quaternary operations. */
13281 d = bdesc_4arg;
13282 for (i = 0; i < ARRAY_SIZE (bdesc_4arg); i++, d++)
13283 if (d->code == fcode)
13284 return rs6000_expand_quaternop_builtin (icode, exp, target);
13285
13286 /* Handle simple no-argument operations. */
13287 d = bdesc_0arg;
13288 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
13289 if (d->code == fcode)
13290 return rs6000_expand_zeroop_builtin (icode, target);
13291
13292 gcc_unreachable ();
13293 }
13294
13295 /* Create a builtin vector type with a name. Taking care not to give
13296 the canonical type a name. */
13297
13298 static tree
rs6000_vector_type(const char * name,tree elt_type,unsigned num_elts)13299 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
13300 {
13301 tree result = build_vector_type (elt_type, num_elts);
13302
13303 /* Copy so we don't give the canonical type a name. */
13304 result = build_variant_type_copy (result);
13305
13306 add_builtin_type (name, result);
13307
13308 return result;
13309 }
13310
13311 void
rs6000_init_builtins(void)13312 rs6000_init_builtins (void)
13313 {
13314 tree tdecl;
13315 tree ftype;
13316 machine_mode mode;
13317
13318 if (TARGET_DEBUG_BUILTIN)
13319 fprintf (stderr, "rs6000_init_builtins%s%s\n",
13320 (TARGET_ALTIVEC) ? ", altivec" : "",
13321 (TARGET_VSX) ? ", vsx" : "");
13322
13323 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
13324 : "__vector long long",
13325 long_long_integer_type_node, 2);
13326 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
13327 V4SI_type_node = rs6000_vector_type ("__vector signed int",
13328 intSI_type_node, 4);
13329 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
13330 V8HI_type_node = rs6000_vector_type ("__vector signed short",
13331 intHI_type_node, 8);
13332 V16QI_type_node = rs6000_vector_type ("__vector signed char",
13333 intQI_type_node, 16);
13334
13335 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
13336 unsigned_intQI_type_node, 16);
13337 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
13338 unsigned_intHI_type_node, 8);
13339 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
13340 unsigned_intSI_type_node, 4);
13341 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
13342 ? "__vector unsigned long"
13343 : "__vector unsigned long long",
13344 long_long_unsigned_type_node, 2);
13345
13346 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
13347
13348 const_str_type_node
13349 = build_pointer_type (build_qualified_type (char_type_node,
13350 TYPE_QUAL_CONST));
13351
13352 /* We use V1TI mode as a special container to hold __int128_t items that
13353 must live in VSX registers. */
13354 if (intTI_type_node)
13355 {
13356 V1TI_type_node = rs6000_vector_type ("__vector __int128",
13357 intTI_type_node, 1);
13358 unsigned_V1TI_type_node
13359 = rs6000_vector_type ("__vector unsigned __int128",
13360 unsigned_intTI_type_node, 1);
13361 }
13362
13363 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
13364 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
13365 'vector unsigned short'. */
13366
13367 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
13368 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
13369 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
13370 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
13371 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
13372
13373 long_integer_type_internal_node = long_integer_type_node;
13374 long_unsigned_type_internal_node = long_unsigned_type_node;
13375 long_long_integer_type_internal_node = long_long_integer_type_node;
13376 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
13377 intQI_type_internal_node = intQI_type_node;
13378 uintQI_type_internal_node = unsigned_intQI_type_node;
13379 intHI_type_internal_node = intHI_type_node;
13380 uintHI_type_internal_node = unsigned_intHI_type_node;
13381 intSI_type_internal_node = intSI_type_node;
13382 uintSI_type_internal_node = unsigned_intSI_type_node;
13383 intDI_type_internal_node = intDI_type_node;
13384 uintDI_type_internal_node = unsigned_intDI_type_node;
13385 intTI_type_internal_node = intTI_type_node;
13386 uintTI_type_internal_node = unsigned_intTI_type_node;
13387 float_type_internal_node = float_type_node;
13388 double_type_internal_node = double_type_node;
13389 long_double_type_internal_node = long_double_type_node;
13390 dfloat64_type_internal_node = dfloat64_type_node;
13391 dfloat128_type_internal_node = dfloat128_type_node;
13392 void_type_internal_node = void_type_node;
13393
13394 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
13395 IFmode is the IBM extended 128-bit format that is a pair of doubles.
13396 TFmode will be either IEEE 128-bit floating point or the IBM double-double
13397 format that uses a pair of doubles, depending on the switches and
13398 defaults.
13399
13400 If we don't support for either 128-bit IBM double double or IEEE 128-bit
13401 floating point, we need make sure the type is non-zero or else self-test
13402 fails during bootstrap.
13403
13404 Always create __ibm128 as a separate type, even if the current long double
13405 format is IBM extended double.
13406
13407 For IEEE 128-bit floating point, always create the type __ieee128. If the
13408 user used -mfloat128, rs6000-c.c will create a define from __float128 to
13409 __ieee128. */
13410 if (TARGET_FLOAT128_TYPE)
13411 {
13412 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
13413 ibm128_float_type_node = long_double_type_node;
13414 else
13415 {
13416 ibm128_float_type_node = make_node (REAL_TYPE);
13417 TYPE_PRECISION (ibm128_float_type_node) = 128;
13418 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
13419 layout_type (ibm128_float_type_node);
13420 }
13421
13422 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
13423 "__ibm128");
13424
13425 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
13426 ieee128_float_type_node = long_double_type_node;
13427 else
13428 ieee128_float_type_node = float128_type_node;
13429
13430 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
13431 "__ieee128");
13432 }
13433
13434 else
13435 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
13436
13437 /* Vector pair and vector quad support. */
13438 if (TARGET_EXTRA_BUILTINS)
13439 {
13440 vector_pair_type_node = make_node (OPAQUE_TYPE);
13441 SET_TYPE_MODE (vector_pair_type_node, OOmode);
13442 TYPE_SIZE (vector_pair_type_node) = bitsize_int (GET_MODE_BITSIZE (OOmode));
13443 TYPE_PRECISION (vector_pair_type_node) = GET_MODE_BITSIZE (OOmode);
13444 TYPE_SIZE_UNIT (vector_pair_type_node) = size_int (GET_MODE_SIZE (OOmode));
13445 SET_TYPE_ALIGN (vector_pair_type_node, 256);
13446 TYPE_USER_ALIGN (vector_pair_type_node) = 0;
13447 lang_hooks.types.register_builtin_type (vector_pair_type_node,
13448 "__vector_pair");
13449
13450 vector_quad_type_node = make_node (OPAQUE_TYPE);
13451 SET_TYPE_MODE (vector_quad_type_node, XOmode);
13452 TYPE_SIZE (vector_quad_type_node) = bitsize_int (GET_MODE_BITSIZE (XOmode));
13453 TYPE_PRECISION (vector_quad_type_node) = GET_MODE_BITSIZE (XOmode);
13454 TYPE_SIZE_UNIT (vector_quad_type_node) = size_int (GET_MODE_SIZE (XOmode));
13455 SET_TYPE_ALIGN (vector_quad_type_node, 512);
13456 TYPE_USER_ALIGN (vector_quad_type_node) = 0;
13457 lang_hooks.types.register_builtin_type (vector_quad_type_node,
13458 "__vector_quad");
13459 }
13460
13461 /* Initialize the modes for builtin_function_type, mapping a machine mode to
13462 tree type node. */
13463 builtin_mode_to_type[QImode][0] = integer_type_node;
13464 builtin_mode_to_type[QImode][1] = unsigned_intSI_type_node;
13465 builtin_mode_to_type[HImode][0] = integer_type_node;
13466 builtin_mode_to_type[HImode][1] = unsigned_intSI_type_node;
13467 builtin_mode_to_type[SImode][0] = intSI_type_node;
13468 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
13469 builtin_mode_to_type[DImode][0] = intDI_type_node;
13470 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
13471 builtin_mode_to_type[TImode][0] = intTI_type_node;
13472 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
13473 builtin_mode_to_type[SFmode][0] = float_type_node;
13474 builtin_mode_to_type[DFmode][0] = double_type_node;
13475 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
13476 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
13477 builtin_mode_to_type[TFmode][0] = long_double_type_node;
13478 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
13479 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
13480 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
13481 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
13482 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
13483 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
13484 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
13485 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
13486 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
13487 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
13488 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
13489 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
13490 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
13491 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
13492 builtin_mode_to_type[OOmode][1] = vector_pair_type_node;
13493 builtin_mode_to_type[XOmode][1] = vector_quad_type_node;
13494
13495 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
13496 TYPE_NAME (bool_char_type_node) = tdecl;
13497
13498 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
13499 TYPE_NAME (bool_short_type_node) = tdecl;
13500
13501 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
13502 TYPE_NAME (bool_int_type_node) = tdecl;
13503
13504 tdecl = add_builtin_type ("__pixel", pixel_type_node);
13505 TYPE_NAME (pixel_type_node) = tdecl;
13506
13507 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
13508 bool_char_type_node, 16);
13509 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
13510 bool_short_type_node, 8);
13511 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
13512 bool_int_type_node, 4);
13513 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
13514 ? "__vector __bool long"
13515 : "__vector __bool long long",
13516 bool_long_long_type_node, 2);
13517 bool_V1TI_type_node = rs6000_vector_type ("__vector __bool __int128",
13518 intTI_type_node, 1);
13519 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
13520 pixel_type_node, 8);
13521
13522 /* Create Altivec, VSX and MMA builtins on machines with at least the
13523 general purpose extensions (970 and newer) to allow the use of
13524 the target attribute. */
13525 if (TARGET_EXTRA_BUILTINS)
13526 {
13527 altivec_init_builtins ();
13528 mma_init_builtins ();
13529 }
13530 if (TARGET_HTM)
13531 htm_init_builtins ();
13532
13533 if (TARGET_EXTRA_BUILTINS)
13534 rs6000_common_init_builtins ();
13535
13536 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
13537 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
13538 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
13539
13540 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
13541 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
13542 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
13543
13544 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
13545 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
13546 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
13547
13548 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
13549 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
13550 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
13551
13552 mode = (TARGET_64BIT) ? DImode : SImode;
13553 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
13554 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
13555 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
13556
13557 ftype = build_function_type_list (unsigned_intDI_type_node,
13558 NULL_TREE);
13559 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
13560
13561 if (TARGET_64BIT)
13562 ftype = build_function_type_list (unsigned_intDI_type_node,
13563 NULL_TREE);
13564 else
13565 ftype = build_function_type_list (unsigned_intSI_type_node,
13566 NULL_TREE);
13567 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
13568
13569 ftype = build_function_type_list (double_type_node, NULL_TREE);
13570 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
13571
13572 ftype = build_function_type_list (double_type_node, NULL_TREE);
13573 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
13574
13575 ftype = build_function_type_list (void_type_node,
13576 intSI_type_node,
13577 NULL_TREE);
13578 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
13579
13580 ftype = build_function_type_list (void_type_node,
13581 intSI_type_node,
13582 NULL_TREE);
13583 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
13584
13585 ftype = build_function_type_list (void_type_node,
13586 intDI_type_node,
13587 NULL_TREE);
13588 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
13589
13590 ftype = build_function_type_list (void_type_node,
13591 intDI_type_node,
13592 NULL_TREE);
13593 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
13594
13595 ftype = build_function_type_list (void_type_node,
13596 intSI_type_node, double_type_node,
13597 NULL_TREE);
13598 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
13599
13600 ftype = build_function_type_list (void_type_node, NULL_TREE);
13601 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
13602 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
13603 MISC_BUILTIN_SPEC_BARRIER);
13604
13605 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
13606 NULL_TREE);
13607 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
13608 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
13609
13610 if (TARGET_XCOFF)
13611 {
13612 /* AIX libm provides clog as __clog. */
13613 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
13614 set_user_assembler_name (tdecl, "__clog");
13615
13616 /* When long double is 64 bit, some long double builtins of libc
13617 functions (like __builtin_frexpl) must call the double version
13618 (frexp) not the long double version (frexpl) that expects a 128 bit
13619 argument. */
13620 if (! TARGET_LONG_DOUBLE_128)
13621 {
13622 if ((tdecl = builtin_decl_explicit (BUILT_IN_FMODL)) != NULL_TREE)
13623 set_user_assembler_name (tdecl, "fmod");
13624 if ((tdecl = builtin_decl_explicit (BUILT_IN_FREXPL)) != NULL_TREE)
13625 set_user_assembler_name (tdecl, "frexp");
13626 if ((tdecl = builtin_decl_explicit (BUILT_IN_LDEXPL)) != NULL_TREE)
13627 set_user_assembler_name (tdecl, "ldexp");
13628 if ((tdecl = builtin_decl_explicit (BUILT_IN_MODFL)) != NULL_TREE)
13629 set_user_assembler_name (tdecl, "modf");
13630 }
13631 }
13632
13633 #ifdef SUBTARGET_INIT_BUILTINS
13634 SUBTARGET_INIT_BUILTINS;
13635 #endif
13636
13637 /* Register the compatibility builtins after all of the normal
13638 builtins have been defined. */
13639 const struct builtin_compatibility *d = bdesc_compat;
13640 unsigned i;
13641 for (i = 0; i < ARRAY_SIZE (bdesc_compat); i++, d++)
13642 {
13643 tree decl = rs6000_builtin_decls[(int)d->code];
13644 if (decl != NULL)
13645 add_builtin_function (d->name, TREE_TYPE (decl), (int)d->code,
13646 BUILT_IN_MD, NULL, NULL_TREE);
13647 }
13648 }
13649
13650 /* Returns the rs6000 builtin decl for CODE. */
13651
13652 tree
rs6000_builtin_decl(unsigned code,bool initialize_p ATTRIBUTE_UNUSED)13653 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
13654 {
13655 HOST_WIDE_INT fnmask;
13656
13657 if (code >= RS6000_BUILTIN_COUNT)
13658 return error_mark_node;
13659
13660 fnmask = rs6000_builtin_info[code].mask;
13661 if ((fnmask & rs6000_builtin_mask) != fnmask)
13662 {
13663 rs6000_invalid_builtin ((enum rs6000_builtins)code);
13664 return error_mark_node;
13665 }
13666
13667 return rs6000_builtin_decls[code];
13668 }
13669
13670 static void
altivec_init_builtins(void)13671 altivec_init_builtins (void)
13672 {
13673 const struct builtin_description *d;
13674 size_t i;
13675 tree ftype;
13676 tree decl;
13677
13678 tree pvoid_type_node = build_pointer_type (void_type_node);
13679
13680 tree pcvoid_type_node
13681 = build_pointer_type (build_qualified_type (void_type_node,
13682 TYPE_QUAL_CONST));
13683
13684 tree int_ftype_opaque
13685 = build_function_type_list (integer_type_node,
13686 opaque_V4SI_type_node, NULL_TREE);
13687 tree opaque_ftype_opaque
13688 = build_function_type_list (integer_type_node, NULL_TREE);
13689 tree opaque_ftype_opaque_int
13690 = build_function_type_list (opaque_V4SI_type_node,
13691 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
13692 tree opaque_ftype_opaque_opaque_int
13693 = build_function_type_list (opaque_V4SI_type_node,
13694 opaque_V4SI_type_node, opaque_V4SI_type_node,
13695 integer_type_node, NULL_TREE);
13696 tree opaque_ftype_opaque_opaque_opaque
13697 = build_function_type_list (opaque_V4SI_type_node,
13698 opaque_V4SI_type_node, opaque_V4SI_type_node,
13699 opaque_V4SI_type_node, NULL_TREE);
13700 tree opaque_ftype_opaque_opaque
13701 = build_function_type_list (opaque_V4SI_type_node,
13702 opaque_V4SI_type_node, opaque_V4SI_type_node,
13703 NULL_TREE);
13704 tree int_ftype_int_opaque_opaque
13705 = build_function_type_list (integer_type_node,
13706 integer_type_node, opaque_V4SI_type_node,
13707 opaque_V4SI_type_node, NULL_TREE);
13708 tree int_ftype_int_v4si_v4si
13709 = build_function_type_list (integer_type_node,
13710 integer_type_node, V4SI_type_node,
13711 V4SI_type_node, NULL_TREE);
13712 tree int_ftype_int_v2di_v2di
13713 = build_function_type_list (integer_type_node,
13714 integer_type_node, V2DI_type_node,
13715 V2DI_type_node, NULL_TREE);
13716 tree int_ftype_int_v1ti_v1ti
13717 = build_function_type_list (integer_type_node,
13718 integer_type_node, V1TI_type_node,
13719 V1TI_type_node, NULL_TREE);
13720 tree void_ftype_v4si
13721 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
13722 tree v8hi_ftype_void
13723 = build_function_type_list (V8HI_type_node, NULL_TREE);
13724 tree void_ftype_void
13725 = build_function_type_list (void_type_node, NULL_TREE);
13726 tree void_ftype_int
13727 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
13728
13729 tree opaque_ftype_long_pcvoid
13730 = build_function_type_list (opaque_V4SI_type_node,
13731 long_integer_type_node, pcvoid_type_node,
13732 NULL_TREE);
13733 tree v16qi_ftype_pcvoid
13734 = build_function_type_list (V16QI_type_node,
13735 pcvoid_type_node,
13736 NULL_TREE);
13737 tree v16qi_ftype_long_pcvoid
13738 = build_function_type_list (V16QI_type_node,
13739 long_integer_type_node, pcvoid_type_node,
13740 NULL_TREE);
13741 tree v8hi_ftype_long_pcvoid
13742 = build_function_type_list (V8HI_type_node,
13743 long_integer_type_node, pcvoid_type_node,
13744 NULL_TREE);
13745 tree v4si_ftype_long_pcvoid
13746 = build_function_type_list (V4SI_type_node,
13747 long_integer_type_node, pcvoid_type_node,
13748 NULL_TREE);
13749 tree v4sf_ftype_long_pcvoid
13750 = build_function_type_list (V4SF_type_node,
13751 long_integer_type_node, pcvoid_type_node,
13752 NULL_TREE);
13753 tree v2df_ftype_long_pcvoid
13754 = build_function_type_list (V2DF_type_node,
13755 long_integer_type_node, pcvoid_type_node,
13756 NULL_TREE);
13757 tree v2di_ftype_long_pcvoid
13758 = build_function_type_list (V2DI_type_node,
13759 long_integer_type_node, pcvoid_type_node,
13760 NULL_TREE);
13761 tree v1ti_ftype_long_pcvoid
13762 = build_function_type_list (V1TI_type_node,
13763 long_integer_type_node, pcvoid_type_node,
13764 NULL_TREE);
13765
13766 tree void_ftype_opaque_long_pvoid
13767 = build_function_type_list (void_type_node,
13768 opaque_V4SI_type_node, long_integer_type_node,
13769 pvoid_type_node, NULL_TREE);
13770 tree void_ftype_v4si_long_pvoid
13771 = build_function_type_list (void_type_node,
13772 V4SI_type_node, long_integer_type_node,
13773 pvoid_type_node, NULL_TREE);
13774 tree void_ftype_v16qi_long_pvoid
13775 = build_function_type_list (void_type_node,
13776 V16QI_type_node, long_integer_type_node,
13777 pvoid_type_node, NULL_TREE);
13778
13779 tree void_ftype_v16qi_pvoid_long
13780 = build_function_type_list (void_type_node,
13781 V16QI_type_node, pvoid_type_node,
13782 long_integer_type_node, NULL_TREE);
13783
13784 tree void_ftype_v8hi_long_pvoid
13785 = build_function_type_list (void_type_node,
13786 V8HI_type_node, long_integer_type_node,
13787 pvoid_type_node, NULL_TREE);
13788 tree void_ftype_v4sf_long_pvoid
13789 = build_function_type_list (void_type_node,
13790 V4SF_type_node, long_integer_type_node,
13791 pvoid_type_node, NULL_TREE);
13792 tree void_ftype_v2df_long_pvoid
13793 = build_function_type_list (void_type_node,
13794 V2DF_type_node, long_integer_type_node,
13795 pvoid_type_node, NULL_TREE);
13796 tree void_ftype_v1ti_long_pvoid
13797 = build_function_type_list (void_type_node,
13798 V1TI_type_node, long_integer_type_node,
13799 pvoid_type_node, NULL_TREE);
13800 tree void_ftype_v2di_long_pvoid
13801 = build_function_type_list (void_type_node,
13802 V2DI_type_node, long_integer_type_node,
13803 pvoid_type_node, NULL_TREE);
13804 tree int_ftype_int_v8hi_v8hi
13805 = build_function_type_list (integer_type_node,
13806 integer_type_node, V8HI_type_node,
13807 V8HI_type_node, NULL_TREE);
13808 tree int_ftype_int_v16qi_v16qi
13809 = build_function_type_list (integer_type_node,
13810 integer_type_node, V16QI_type_node,
13811 V16QI_type_node, NULL_TREE);
13812 tree int_ftype_int_v4sf_v4sf
13813 = build_function_type_list (integer_type_node,
13814 integer_type_node, V4SF_type_node,
13815 V4SF_type_node, NULL_TREE);
13816 tree int_ftype_int_v2df_v2df
13817 = build_function_type_list (integer_type_node,
13818 integer_type_node, V2DF_type_node,
13819 V2DF_type_node, NULL_TREE);
13820 tree v2di_ftype_v2di
13821 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
13822 tree v4si_ftype_v4si
13823 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
13824 tree v8hi_ftype_v8hi
13825 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
13826 tree v16qi_ftype_v16qi
13827 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
13828 tree v4sf_ftype_v4sf
13829 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
13830 tree v2df_ftype_v2df
13831 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
13832 tree void_ftype_pcvoid_int_int
13833 = build_function_type_list (void_type_node,
13834 pcvoid_type_node, integer_type_node,
13835 integer_type_node, NULL_TREE);
13836
13837 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
13838 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
13839 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
13840 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
13841 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
13842 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
13843 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
13844 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
13845 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
13846 def_builtin ("__builtin_altivec_se_lxvrbx", v16qi_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRBX);
13847 def_builtin ("__builtin_altivec_se_lxvrhx", v8hi_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRHX);
13848 def_builtin ("__builtin_altivec_se_lxvrwx", v4si_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRWX);
13849 def_builtin ("__builtin_altivec_se_lxvrdx", v2di_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRDX);
13850 def_builtin ("__builtin_altivec_ze_lxvrbx", v16qi_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRBX);
13851 def_builtin ("__builtin_altivec_ze_lxvrhx", v8hi_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRHX);
13852 def_builtin ("__builtin_altivec_ze_lxvrwx", v4si_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRWX);
13853 def_builtin ("__builtin_altivec_ze_lxvrdx", v2di_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRDX);
13854 def_builtin ("__builtin_altivec_tr_stxvrbx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRBX);
13855 def_builtin ("__builtin_altivec_tr_stxvrhx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRHX);
13856 def_builtin ("__builtin_altivec_tr_stxvrwx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRWX);
13857 def_builtin ("__builtin_altivec_tr_stxvrdx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRDX);
13858 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
13859 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
13860 ALTIVEC_BUILTIN_LVXL_V2DF);
13861 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
13862 ALTIVEC_BUILTIN_LVXL_V2DI);
13863 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
13864 ALTIVEC_BUILTIN_LVXL_V4SF);
13865 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
13866 ALTIVEC_BUILTIN_LVXL_V4SI);
13867 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
13868 ALTIVEC_BUILTIN_LVXL_V8HI);
13869 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
13870 ALTIVEC_BUILTIN_LVXL_V16QI);
13871 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
13872 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
13873 ALTIVEC_BUILTIN_LVX_V1TI);
13874 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
13875 ALTIVEC_BUILTIN_LVX_V2DF);
13876 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
13877 ALTIVEC_BUILTIN_LVX_V2DI);
13878 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
13879 ALTIVEC_BUILTIN_LVX_V4SF);
13880 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
13881 ALTIVEC_BUILTIN_LVX_V4SI);
13882 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
13883 ALTIVEC_BUILTIN_LVX_V8HI);
13884 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
13885 ALTIVEC_BUILTIN_LVX_V16QI);
13886 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
13887 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
13888 ALTIVEC_BUILTIN_STVX_V2DF);
13889 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
13890 ALTIVEC_BUILTIN_STVX_V2DI);
13891 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
13892 ALTIVEC_BUILTIN_STVX_V4SF);
13893 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
13894 ALTIVEC_BUILTIN_STVX_V4SI);
13895 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
13896 ALTIVEC_BUILTIN_STVX_V8HI);
13897 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
13898 ALTIVEC_BUILTIN_STVX_V16QI);
13899 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
13900 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
13901 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
13902 ALTIVEC_BUILTIN_STVXL_V2DF);
13903 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
13904 ALTIVEC_BUILTIN_STVXL_V2DI);
13905 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
13906 ALTIVEC_BUILTIN_STVXL_V4SF);
13907 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
13908 ALTIVEC_BUILTIN_STVXL_V4SI);
13909 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
13910 ALTIVEC_BUILTIN_STVXL_V8HI);
13911 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
13912 ALTIVEC_BUILTIN_STVXL_V16QI);
13913 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
13914 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
13915 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
13916 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
13917 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
13918 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
13919 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
13920 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
13921 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
13922 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
13923 def_builtin ("__builtin_vec_se_lxvrx", v1ti_ftype_long_pcvoid, P10_BUILTIN_VEC_SE_LXVRX);
13924 def_builtin ("__builtin_vec_ze_lxvrx", v1ti_ftype_long_pcvoid, P10_BUILTIN_VEC_ZE_LXVRX);
13925 def_builtin ("__builtin_vec_tr_stxvrx", void_ftype_opaque_long_pvoid, P10_BUILTIN_VEC_TR_STXVRX);
13926 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
13927 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
13928 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
13929 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
13930 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
13931 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
13932
13933 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
13934 VSX_BUILTIN_LXVD2X_V2DF);
13935 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
13936 VSX_BUILTIN_LXVD2X_V2DI);
13937 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
13938 VSX_BUILTIN_LXVW4X_V4SF);
13939 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
13940 VSX_BUILTIN_LXVW4X_V4SI);
13941 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
13942 VSX_BUILTIN_LXVW4X_V8HI);
13943 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
13944 VSX_BUILTIN_LXVW4X_V16QI);
13945 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
13946 VSX_BUILTIN_STXVD2X_V2DF);
13947 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
13948 VSX_BUILTIN_STXVD2X_V2DI);
13949 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
13950 VSX_BUILTIN_STXVW4X_V4SF);
13951 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
13952 VSX_BUILTIN_STXVW4X_V4SI);
13953 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
13954 VSX_BUILTIN_STXVW4X_V8HI);
13955 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
13956 VSX_BUILTIN_STXVW4X_V16QI);
13957
13958 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
13959 VSX_BUILTIN_LD_ELEMREV_V2DF);
13960 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
13961 VSX_BUILTIN_LD_ELEMREV_V2DI);
13962 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
13963 VSX_BUILTIN_LD_ELEMREV_V4SF);
13964 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
13965 VSX_BUILTIN_LD_ELEMREV_V4SI);
13966 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
13967 VSX_BUILTIN_LD_ELEMREV_V8HI);
13968 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
13969 VSX_BUILTIN_LD_ELEMREV_V16QI);
13970 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
13971 VSX_BUILTIN_ST_ELEMREV_V2DF);
13972 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
13973 VSX_BUILTIN_ST_ELEMREV_V1TI);
13974 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
13975 VSX_BUILTIN_ST_ELEMREV_V2DI);
13976 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
13977 VSX_BUILTIN_ST_ELEMREV_V4SF);
13978 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
13979 VSX_BUILTIN_ST_ELEMREV_V4SI);
13980 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
13981 VSX_BUILTIN_ST_ELEMREV_V8HI);
13982 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
13983 VSX_BUILTIN_ST_ELEMREV_V16QI);
13984
13985 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
13986 VSX_BUILTIN_VEC_LD);
13987 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
13988 VSX_BUILTIN_VEC_ST);
13989 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
13990 VSX_BUILTIN_VEC_XL);
13991 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
13992 VSX_BUILTIN_VEC_XL_BE);
13993 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
13994 VSX_BUILTIN_VEC_XST);
13995 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
13996 VSX_BUILTIN_VEC_XST_BE);
13997
13998 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
13999 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
14000 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
14001
14002 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
14003 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
14004 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
14005 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
14006 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
14007 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
14008 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
14009 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
14010 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
14011 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
14012 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
14013 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
14014
14015 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
14016 ALTIVEC_BUILTIN_VEC_ADDE);
14017 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
14018 ALTIVEC_BUILTIN_VEC_ADDEC);
14019 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
14020 ALTIVEC_BUILTIN_VEC_CMPNE);
14021 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
14022 ALTIVEC_BUILTIN_VEC_MUL);
14023 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
14024 ALTIVEC_BUILTIN_VEC_SUBE);
14025 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
14026 ALTIVEC_BUILTIN_VEC_SUBEC);
14027
14028 /* Cell builtins. */
14029 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
14030 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
14031 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
14032 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
14033
14034 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
14035 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
14036 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
14037 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
14038
14039 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
14040 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
14041 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
14042 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
14043
14044 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
14045 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
14046 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
14047 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
14048
14049 if (TARGET_P9_VECTOR)
14050 {
14051 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
14052 P9V_BUILTIN_STXVL);
14053 def_builtin ("__builtin_altivec_xst_len_r", void_ftype_v16qi_pvoid_long,
14054 P9V_BUILTIN_XST_LEN_R);
14055 }
14056
14057 /* Add the DST variants. */
14058 d = bdesc_dst;
14059 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
14060 {
14061 /* It is expected that these dst built-in functions may have
14062 d->icode equal to CODE_FOR_nothing. */
14063 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
14064 }
14065
14066 /* Initialize the predicates. */
14067 d = bdesc_altivec_preds;
14068 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
14069 {
14070 machine_mode mode1;
14071 tree type;
14072
14073 if (rs6000_overloaded_builtin_p (d->code))
14074 mode1 = VOIDmode;
14075 else
14076 {
14077 /* Cannot define builtin if the instruction is disabled. */
14078 gcc_assert (d->icode != CODE_FOR_nothing);
14079 mode1 = insn_data[d->icode].operand[1].mode;
14080 }
14081
14082 switch (mode1)
14083 {
14084 case E_VOIDmode:
14085 type = int_ftype_int_opaque_opaque;
14086 break;
14087 case E_V1TImode:
14088 type = int_ftype_int_v1ti_v1ti;
14089 break;
14090 case E_V2DImode:
14091 type = int_ftype_int_v2di_v2di;
14092 break;
14093 case E_V4SImode:
14094 type = int_ftype_int_v4si_v4si;
14095 break;
14096 case E_V8HImode:
14097 type = int_ftype_int_v8hi_v8hi;
14098 break;
14099 case E_V16QImode:
14100 type = int_ftype_int_v16qi_v16qi;
14101 break;
14102 case E_V4SFmode:
14103 type = int_ftype_int_v4sf_v4sf;
14104 break;
14105 case E_V2DFmode:
14106 type = int_ftype_int_v2df_v2df;
14107 break;
14108 default:
14109 gcc_unreachable ();
14110 }
14111
14112 def_builtin (d->name, type, d->code);
14113 }
14114
14115 /* Initialize the abs* operators. */
14116 d = bdesc_abs;
14117 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
14118 {
14119 machine_mode mode0;
14120 tree type;
14121
14122 /* Cannot define builtin if the instruction is disabled. */
14123 gcc_assert (d->icode != CODE_FOR_nothing);
14124 mode0 = insn_data[d->icode].operand[0].mode;
14125
14126 switch (mode0)
14127 {
14128 case E_V2DImode:
14129 type = v2di_ftype_v2di;
14130 break;
14131 case E_V4SImode:
14132 type = v4si_ftype_v4si;
14133 break;
14134 case E_V8HImode:
14135 type = v8hi_ftype_v8hi;
14136 break;
14137 case E_V16QImode:
14138 type = v16qi_ftype_v16qi;
14139 break;
14140 case E_V4SFmode:
14141 type = v4sf_ftype_v4sf;
14142 break;
14143 case E_V2DFmode:
14144 type = v2df_ftype_v2df;
14145 break;
14146 default:
14147 gcc_unreachable ();
14148 }
14149
14150 def_builtin (d->name, type, d->code);
14151 }
14152
14153 /* Initialize target builtin that implements
14154 targetm.vectorize.builtin_mask_for_load. */
14155
14156 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
14157 v16qi_ftype_pcvoid,
14158 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
14159 BUILT_IN_MD, NULL, NULL_TREE);
14160 TREE_READONLY (decl) = 1;
14161 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
14162 altivec_builtin_mask_for_load = decl;
14163
14164 /* Access to the vec_init patterns. */
14165 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
14166 integer_type_node, integer_type_node,
14167 integer_type_node, NULL_TREE);
14168 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
14169
14170 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
14171 short_integer_type_node,
14172 short_integer_type_node,
14173 short_integer_type_node,
14174 short_integer_type_node,
14175 short_integer_type_node,
14176 short_integer_type_node,
14177 short_integer_type_node, NULL_TREE);
14178 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
14179
14180 ftype = build_function_type_list (V16QI_type_node, char_type_node,
14181 char_type_node, char_type_node,
14182 char_type_node, char_type_node,
14183 char_type_node, char_type_node,
14184 char_type_node, char_type_node,
14185 char_type_node, char_type_node,
14186 char_type_node, char_type_node,
14187 char_type_node, char_type_node,
14188 char_type_node, NULL_TREE);
14189 def_builtin ("__builtin_vec_init_v16qi", ftype,
14190 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
14191
14192 ftype = build_function_type_list (V4SF_type_node, float_type_node,
14193 float_type_node, float_type_node,
14194 float_type_node, NULL_TREE);
14195 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
14196
14197 /* VSX builtins. */
14198 ftype = build_function_type_list (V2DF_type_node, double_type_node,
14199 double_type_node, NULL_TREE);
14200 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
14201
14202 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
14203 intDI_type_node, NULL_TREE);
14204 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
14205
14206 /* Access to the vec_set patterns. */
14207 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
14208 intSI_type_node,
14209 integer_type_node, NULL_TREE);
14210 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
14211
14212 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
14213 intHI_type_node,
14214 integer_type_node, NULL_TREE);
14215 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
14216
14217 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
14218 intQI_type_node,
14219 integer_type_node, NULL_TREE);
14220 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
14221
14222 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
14223 float_type_node,
14224 integer_type_node, NULL_TREE);
14225 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
14226
14227 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
14228 double_type_node,
14229 integer_type_node, NULL_TREE);
14230 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
14231
14232 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
14233 intDI_type_node,
14234 integer_type_node, NULL_TREE);
14235 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
14236
14237 /* Access to the vec_extract patterns. */
14238 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
14239 integer_type_node, NULL_TREE);
14240 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
14241
14242 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
14243 integer_type_node, NULL_TREE);
14244 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
14245
14246 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
14247 integer_type_node, NULL_TREE);
14248 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
14249
14250 ftype = build_function_type_list (float_type_node, V4SF_type_node,
14251 integer_type_node, NULL_TREE);
14252 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
14253
14254 ftype = build_function_type_list (double_type_node, V2DF_type_node,
14255 integer_type_node, NULL_TREE);
14256 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
14257
14258 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
14259 integer_type_node, NULL_TREE);
14260 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
14261
14262
14263 if (V1TI_type_node)
14264 {
14265 tree v1ti_ftype_long_pcvoid
14266 = build_function_type_list (V1TI_type_node,
14267 long_integer_type_node, pcvoid_type_node,
14268 NULL_TREE);
14269 tree void_ftype_v1ti_long_pvoid
14270 = build_function_type_list (void_type_node,
14271 V1TI_type_node, long_integer_type_node,
14272 pvoid_type_node, NULL_TREE);
14273 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
14274 VSX_BUILTIN_LD_ELEMREV_V1TI);
14275 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
14276 VSX_BUILTIN_LXVD2X_V1TI);
14277 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
14278 VSX_BUILTIN_STXVD2X_V1TI);
14279 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
14280 NULL_TREE, NULL_TREE);
14281 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
14282 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
14283 intTI_type_node,
14284 integer_type_node, NULL_TREE);
14285 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
14286 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
14287 integer_type_node, NULL_TREE);
14288 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
14289 }
14290
14291 }
14292
14293 static void
mma_init_builtins(void)14294 mma_init_builtins (void)
14295 {
14296 const struct builtin_description *d = bdesc_mma;
14297
14298 for (unsigned i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++)
14299 {
14300 tree op[MAX_MMA_OPERANDS], type;
14301 unsigned icode = (unsigned) d->icode;
14302 unsigned attr = rs6000_builtin_info[d->code].attr;
14303 int attr_args = (attr & RS6000_BTC_OPND_MASK);
14304 bool gimple_func = (attr & RS6000_BTC_GIMPLE);
14305 unsigned nopnds = 0;
14306
14307 if (d->name == 0)
14308 {
14309 if (TARGET_DEBUG_BUILTIN)
14310 fprintf (stderr, "mma_builtin, bdesc_mma[%ld] no name\n",
14311 (long unsigned) i);
14312 continue;
14313 }
14314
14315 if (gimple_func)
14316 {
14317 gcc_assert (icode == CODE_FOR_nothing);
14318 /* Some MMA built-ins that are expanded into gimple are converted
14319 into internal MMA built-ins that are expanded into rtl.
14320 The internal built-in follows immediately after this built-in. */
14321 if (d->code != VSX_BUILTIN_LXVP
14322 && d->code != VSX_BUILTIN_STXVP)
14323 {
14324 op[nopnds++] = void_type_node;
14325 icode = d[1].icode;
14326 }
14327 }
14328 else
14329 {
14330 if (!(d->code == MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL
14331 || d->code == VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL)
14332 && (attr & RS6000_BTC_QUAD) == 0)
14333 attr_args--;
14334
14335 /* Ensure we have the correct number and type of operands. */
14336 gcc_assert (attr_args == insn_data[icode].n_operands - 1);
14337 }
14338
14339 /* This is a disassemble pair/acc function. */
14340 if (d->code == MMA_BUILTIN_DISASSEMBLE_ACC
14341 || d->code == VSX_BUILTIN_DISASSEMBLE_PAIR)
14342 {
14343 op[nopnds++] = build_pointer_type (void_type_node);
14344 if (d->code == MMA_BUILTIN_DISASSEMBLE_ACC)
14345 op[nopnds++] = build_pointer_type (vector_quad_type_node);
14346 else
14347 op[nopnds++] = build_pointer_type (vector_pair_type_node);
14348 }
14349 else if (d->code == VSX_BUILTIN_LXVP)
14350 {
14351 op[nopnds++] = vector_pair_type_node;
14352 op[nopnds++] = sizetype;
14353 op[nopnds++] = build_pointer_type (vector_pair_type_node);
14354 }
14355 else if (d->code == VSX_BUILTIN_STXVP)
14356 {
14357 op[nopnds++] = void_type_node;
14358 op[nopnds++] = vector_pair_type_node;
14359 op[nopnds++] = sizetype;
14360 op[nopnds++] = build_pointer_type (vector_pair_type_node);
14361 }
14362 else
14363 {
14364 /* This is a normal MMA built-in function. */
14365 unsigned j = 0;
14366 if (attr & RS6000_BTC_QUAD
14367 && d->code != MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL
14368 && d->code != VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL)
14369 j = 1;
14370 for (; j < (unsigned) insn_data[icode].n_operands; j++)
14371 {
14372 machine_mode mode = insn_data[icode].operand[j].mode;
14373 if (gimple_func && mode == XOmode)
14374 op[nopnds++] = build_pointer_type (vector_quad_type_node);
14375 else if (gimple_func
14376 && mode == OOmode
14377 && (d->code == VSX_BUILTIN_BUILD_PAIR
14378 || d->code == VSX_BUILTIN_ASSEMBLE_PAIR))
14379 op[nopnds++] = build_pointer_type (vector_pair_type_node);
14380 else
14381 /* MMA uses unsigned types. */
14382 op[nopnds++] = builtin_mode_to_type[mode][1];
14383 }
14384 }
14385
14386 switch (nopnds)
14387 {
14388 case 1:
14389 type = build_function_type_list (op[0], NULL_TREE);
14390 break;
14391 case 2:
14392 type = build_function_type_list (op[0], op[1], NULL_TREE);
14393 break;
14394 case 3:
14395 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
14396 break;
14397 case 4:
14398 type = build_function_type_list (op[0], op[1], op[2], op[3],
14399 NULL_TREE);
14400 break;
14401 case 5:
14402 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4],
14403 NULL_TREE);
14404 break;
14405 case 6:
14406 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4],
14407 op[5], NULL_TREE);
14408 break;
14409 case 7:
14410 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4],
14411 op[5], op[6], NULL_TREE);
14412 break;
14413 default:
14414 gcc_unreachable ();
14415 }
14416
14417 def_builtin (d->name, type, d->code);
14418 }
14419 }
14420
14421 static void
htm_init_builtins(void)14422 htm_init_builtins (void)
14423 {
14424 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
14425 const struct builtin_description *d;
14426 size_t i;
14427
14428 d = bdesc_htm;
14429 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
14430 {
14431 tree op[MAX_HTM_OPERANDS], type;
14432 HOST_WIDE_INT mask = d->mask;
14433 unsigned attr = rs6000_builtin_info[d->code].attr;
14434 bool void_func = (attr & RS6000_BTC_VOID);
14435 int attr_args = (attr & RS6000_BTC_OPND_MASK);
14436 int nopnds = 0;
14437 tree gpr_type_node;
14438 tree rettype;
14439 tree argtype;
14440
14441 /* It is expected that these htm built-in functions may have
14442 d->icode equal to CODE_FOR_nothing. */
14443
14444 if (TARGET_32BIT && TARGET_POWERPC64)
14445 gpr_type_node = long_long_unsigned_type_node;
14446 else
14447 gpr_type_node = long_unsigned_type_node;
14448
14449 if (attr & RS6000_BTC_SPR)
14450 {
14451 rettype = gpr_type_node;
14452 argtype = gpr_type_node;
14453 }
14454 else if (d->code == HTM_BUILTIN_TABORTDC
14455 || d->code == HTM_BUILTIN_TABORTDCI)
14456 {
14457 rettype = unsigned_type_node;
14458 argtype = gpr_type_node;
14459 }
14460 else
14461 {
14462 rettype = unsigned_type_node;
14463 argtype = unsigned_type_node;
14464 }
14465
14466 if ((mask & builtin_mask) != mask)
14467 {
14468 if (TARGET_DEBUG_BUILTIN)
14469 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
14470 continue;
14471 }
14472
14473 if (d->name == 0)
14474 {
14475 if (TARGET_DEBUG_BUILTIN)
14476 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
14477 (long unsigned) i);
14478 continue;
14479 }
14480
14481 op[nopnds++] = (void_func) ? void_type_node : rettype;
14482
14483 if (attr_args == RS6000_BTC_UNARY)
14484 op[nopnds++] = argtype;
14485 else if (attr_args == RS6000_BTC_BINARY)
14486 {
14487 op[nopnds++] = argtype;
14488 op[nopnds++] = argtype;
14489 }
14490 else if (attr_args == RS6000_BTC_TERNARY)
14491 {
14492 op[nopnds++] = argtype;
14493 op[nopnds++] = argtype;
14494 op[nopnds++] = argtype;
14495 }
14496
14497 switch (nopnds)
14498 {
14499 case 1:
14500 type = build_function_type_list (op[0], NULL_TREE);
14501 break;
14502 case 2:
14503 type = build_function_type_list (op[0], op[1], NULL_TREE);
14504 break;
14505 case 3:
14506 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
14507 break;
14508 case 4:
14509 type = build_function_type_list (op[0], op[1], op[2], op[3],
14510 NULL_TREE);
14511 break;
14512 default:
14513 gcc_unreachable ();
14514 }
14515
14516 def_builtin (d->name, type, d->code);
14517 }
14518 }
14519
14520 /* Map types for builtin functions with an explicit return type and
14521 exactly 4 arguments. Functions with fewer than 3 arguments use
14522 builtin_function_type. The number of quaternary built-in
14523 functions is very small. Handle each case specially. */
14524 static tree
builtin_quaternary_function_type(machine_mode mode_ret,machine_mode mode_arg0,machine_mode mode_arg1,machine_mode mode_arg2,machine_mode mode_arg3,enum rs6000_builtins builtin)14525 builtin_quaternary_function_type (machine_mode mode_ret,
14526 machine_mode mode_arg0,
14527 machine_mode mode_arg1,
14528 machine_mode mode_arg2,
14529 machine_mode mode_arg3,
14530 enum rs6000_builtins builtin)
14531 {
14532 tree function_type = NULL;
14533
14534 static tree v2udi_type = builtin_mode_to_type[V2DImode][1];
14535 static tree v16uqi_type = builtin_mode_to_type[V16QImode][1];
14536 static tree uchar_type = builtin_mode_to_type[QImode][1];
14537
14538 static tree xxeval_type =
14539 build_function_type_list (v2udi_type, v2udi_type, v2udi_type,
14540 v2udi_type, uchar_type, NULL_TREE);
14541
14542 static tree xxpermx_type =
14543 build_function_type_list (v2udi_type, v2udi_type, v2udi_type,
14544 v16uqi_type, uchar_type, NULL_TREE);
14545
14546 switch (builtin) {
14547
14548 case P10V_BUILTIN_XXEVAL:
14549 gcc_assert ((mode_ret == V2DImode)
14550 && (mode_arg0 == V2DImode)
14551 && (mode_arg1 == V2DImode)
14552 && (mode_arg2 == V2DImode)
14553 && (mode_arg3 == QImode));
14554 function_type = xxeval_type;
14555 break;
14556
14557 case P10V_BUILTIN_VXXPERMX:
14558 gcc_assert ((mode_ret == V2DImode)
14559 && (mode_arg0 == V2DImode)
14560 && (mode_arg1 == V2DImode)
14561 && (mode_arg2 == V16QImode)
14562 && (mode_arg3 == QImode));
14563 function_type = xxpermx_type;
14564 break;
14565
14566 default:
14567 /* A case for each quaternary built-in must be provided above. */
14568 gcc_unreachable ();
14569 }
14570
14571 return function_type;
14572 }
14573
14574 /* Map types for builtin functions with an explicit return type and up to 3
14575 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
14576 of the argument. */
14577 static tree
builtin_function_type(machine_mode mode_ret,machine_mode mode_arg0,machine_mode mode_arg1,machine_mode mode_arg2,enum rs6000_builtins builtin,const char * name)14578 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
14579 machine_mode mode_arg1, machine_mode mode_arg2,
14580 enum rs6000_builtins builtin, const char *name)
14581 {
14582 struct builtin_hash_struct h;
14583 struct builtin_hash_struct *h2;
14584 int num_args = 3;
14585 int i;
14586 tree ret_type = NULL_TREE;
14587 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
14588
14589 /* Create builtin_hash_table. */
14590 if (builtin_hash_table == NULL)
14591 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
14592
14593 h.type = NULL_TREE;
14594 h.mode[0] = mode_ret;
14595 h.mode[1] = mode_arg0;
14596 h.mode[2] = mode_arg1;
14597 h.mode[3] = mode_arg2;
14598 h.uns_p[0] = 0;
14599 h.uns_p[1] = 0;
14600 h.uns_p[2] = 0;
14601 h.uns_p[3] = 0;
14602
14603 /* If the builtin is a type that produces unsigned results or takes unsigned
14604 arguments, and it is returned as a decl for the vectorizer (such as
14605 widening multiplies, permute), make sure the arguments and return value
14606 are type correct. */
14607 switch (builtin)
14608 {
14609 /* unsigned 1 argument functions. */
14610 case CRYPTO_BUILTIN_VSBOX:
14611 case CRYPTO_BUILTIN_VSBOX_BE:
14612 case P8V_BUILTIN_VGBBD:
14613 case MISC_BUILTIN_CDTBCD:
14614 case MISC_BUILTIN_CBCDTD:
14615 case P10V_BUILTIN_XVCVSPBF16:
14616 case P10V_BUILTIN_XVCVBF16SPN:
14617 case P10V_BUILTIN_MTVSRBM:
14618 case P10V_BUILTIN_MTVSRHM:
14619 case P10V_BUILTIN_MTVSRWM:
14620 case P10V_BUILTIN_MTVSRDM:
14621 case P10V_BUILTIN_MTVSRQM:
14622 case P10V_BUILTIN_VCNTMBB:
14623 case P10V_BUILTIN_VCNTMBH:
14624 case P10V_BUILTIN_VCNTMBW:
14625 case P10V_BUILTIN_VCNTMBD:
14626 case P10V_BUILTIN_VEXPANDMB:
14627 case P10V_BUILTIN_VEXPANDMH:
14628 case P10V_BUILTIN_VEXPANDMW:
14629 case P10V_BUILTIN_VEXPANDMD:
14630 case P10V_BUILTIN_VEXPANDMQ:
14631 h.uns_p[0] = 1;
14632 h.uns_p[1] = 1;
14633 break;
14634
14635 /* unsigned 2 argument functions. */
14636 case ALTIVEC_BUILTIN_VMULEUB:
14637 case ALTIVEC_BUILTIN_VMULEUH:
14638 case P8V_BUILTIN_VMULEUW:
14639 case ALTIVEC_BUILTIN_VMULOUB:
14640 case ALTIVEC_BUILTIN_VMULOUH:
14641 case P8V_BUILTIN_VMULOUW:
14642 case CRYPTO_BUILTIN_VCIPHER:
14643 case CRYPTO_BUILTIN_VCIPHER_BE:
14644 case CRYPTO_BUILTIN_VCIPHERLAST:
14645 case CRYPTO_BUILTIN_VCIPHERLAST_BE:
14646 case CRYPTO_BUILTIN_VNCIPHER:
14647 case CRYPTO_BUILTIN_VNCIPHER_BE:
14648 case CRYPTO_BUILTIN_VNCIPHERLAST:
14649 case CRYPTO_BUILTIN_VNCIPHERLAST_BE:
14650 case CRYPTO_BUILTIN_VPMSUMB:
14651 case CRYPTO_BUILTIN_VPMSUMH:
14652 case CRYPTO_BUILTIN_VPMSUMW:
14653 case CRYPTO_BUILTIN_VPMSUMD:
14654 case CRYPTO_BUILTIN_VPMSUM:
14655 case MISC_BUILTIN_ADDG6S:
14656 case MISC_BUILTIN_DIVWEU:
14657 case MISC_BUILTIN_DIVDEU:
14658 case VSX_BUILTIN_UDIV_V2DI:
14659 case ALTIVEC_BUILTIN_VMAXUB:
14660 case ALTIVEC_BUILTIN_VMINUB:
14661 case ALTIVEC_BUILTIN_VMAXUH:
14662 case ALTIVEC_BUILTIN_VMINUH:
14663 case ALTIVEC_BUILTIN_VMAXUW:
14664 case ALTIVEC_BUILTIN_VMINUW:
14665 case P8V_BUILTIN_VMAXUD:
14666 case P8V_BUILTIN_VMINUD:
14667 case ALTIVEC_BUILTIN_VAND_V16QI_UNS:
14668 case ALTIVEC_BUILTIN_VAND_V8HI_UNS:
14669 case ALTIVEC_BUILTIN_VAND_V4SI_UNS:
14670 case ALTIVEC_BUILTIN_VAND_V2DI_UNS:
14671 case ALTIVEC_BUILTIN_VANDC_V16QI_UNS:
14672 case ALTIVEC_BUILTIN_VANDC_V8HI_UNS:
14673 case ALTIVEC_BUILTIN_VANDC_V4SI_UNS:
14674 case ALTIVEC_BUILTIN_VANDC_V2DI_UNS:
14675 case ALTIVEC_BUILTIN_VNOR_V16QI_UNS:
14676 case ALTIVEC_BUILTIN_VNOR_V8HI_UNS:
14677 case ALTIVEC_BUILTIN_VNOR_V4SI_UNS:
14678 case ALTIVEC_BUILTIN_VNOR_V2DI_UNS:
14679 case ALTIVEC_BUILTIN_VOR_V16QI_UNS:
14680 case ALTIVEC_BUILTIN_VOR_V8HI_UNS:
14681 case ALTIVEC_BUILTIN_VOR_V4SI_UNS:
14682 case ALTIVEC_BUILTIN_VOR_V2DI_UNS:
14683 case ALTIVEC_BUILTIN_VXOR_V16QI_UNS:
14684 case ALTIVEC_BUILTIN_VXOR_V8HI_UNS:
14685 case ALTIVEC_BUILTIN_VXOR_V4SI_UNS:
14686 case ALTIVEC_BUILTIN_VXOR_V2DI_UNS:
14687 case P8V_BUILTIN_EQV_V16QI_UNS:
14688 case P8V_BUILTIN_EQV_V8HI_UNS:
14689 case P8V_BUILTIN_EQV_V4SI_UNS:
14690 case P8V_BUILTIN_EQV_V2DI_UNS:
14691 case P8V_BUILTIN_EQV_V1TI_UNS:
14692 case P8V_BUILTIN_NAND_V16QI_UNS:
14693 case P8V_BUILTIN_NAND_V8HI_UNS:
14694 case P8V_BUILTIN_NAND_V4SI_UNS:
14695 case P8V_BUILTIN_NAND_V2DI_UNS:
14696 case P8V_BUILTIN_NAND_V1TI_UNS:
14697 case P8V_BUILTIN_ORC_V16QI_UNS:
14698 case P8V_BUILTIN_ORC_V8HI_UNS:
14699 case P8V_BUILTIN_ORC_V4SI_UNS:
14700 case P8V_BUILTIN_ORC_V2DI_UNS:
14701 case P8V_BUILTIN_ORC_V1TI_UNS:
14702 case P10V_BUILTIN_VCFUGED:
14703 case P10V_BUILTIN_VCLZDM:
14704 case P10V_BUILTIN_VCTZDM:
14705 case P10V_BUILTIN_VGNB:
14706 case P10V_BUILTIN_VPDEPD:
14707 case P10V_BUILTIN_VPEXTD:
14708 case P10V_BUILTIN_XXGENPCVM_V16QI:
14709 case P10V_BUILTIN_XXGENPCVM_V8HI:
14710 case P10V_BUILTIN_XXGENPCVM_V4SI:
14711 case P10V_BUILTIN_XXGENPCVM_V2DI:
14712 case P10V_BUILTIN_DIVEU_V4SI:
14713 case P10V_BUILTIN_DIVEU_V2DI:
14714 case P10V_BUILTIN_DIVEU_V1TI:
14715 case P10V_BUILTIN_DIVU_V4SI:
14716 case P10V_BUILTIN_DIVU_V2DI:
14717 case P10V_BUILTIN_MODU_V1TI:
14718 case P10V_BUILTIN_MODU_V2DI:
14719 case P10V_BUILTIN_MODU_V4SI:
14720 case P10V_BUILTIN_MULHU_V2DI:
14721 case P10V_BUILTIN_MULHU_V4SI:
14722 case P10V_BUILTIN_VMULEUD:
14723 case P10V_BUILTIN_VMULOUD:
14724 h.uns_p[0] = 1;
14725 h.uns_p[1] = 1;
14726 h.uns_p[2] = 1;
14727 break;
14728
14729 /* unsigned 3 argument functions. */
14730 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
14731 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
14732 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
14733 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
14734 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
14735 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
14736 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
14737 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
14738 case VSX_BUILTIN_VPERM_16QI_UNS:
14739 case VSX_BUILTIN_VPERM_8HI_UNS:
14740 case VSX_BUILTIN_VPERM_4SI_UNS:
14741 case VSX_BUILTIN_VPERM_2DI_UNS:
14742 case VSX_BUILTIN_XXSEL_16QI_UNS:
14743 case VSX_BUILTIN_XXSEL_8HI_UNS:
14744 case VSX_BUILTIN_XXSEL_4SI_UNS:
14745 case VSX_BUILTIN_XXSEL_2DI_UNS:
14746 case CRYPTO_BUILTIN_VPERMXOR:
14747 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
14748 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
14749 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
14750 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
14751 case CRYPTO_BUILTIN_VSHASIGMAW:
14752 case CRYPTO_BUILTIN_VSHASIGMAD:
14753 case CRYPTO_BUILTIN_VSHASIGMA:
14754 case P10V_BUILTIN_VEXTRACTBL:
14755 case P10V_BUILTIN_VEXTRACTHL:
14756 case P10V_BUILTIN_VEXTRACTWL:
14757 case P10V_BUILTIN_VEXTRACTDL:
14758 case P10V_BUILTIN_VEXTRACTBR:
14759 case P10V_BUILTIN_VEXTRACTHR:
14760 case P10V_BUILTIN_VEXTRACTWR:
14761 case P10V_BUILTIN_VEXTRACTDR:
14762 case P10V_BUILTIN_VINSERTGPRBL:
14763 case P10V_BUILTIN_VINSERTGPRHL:
14764 case P10V_BUILTIN_VINSERTGPRWL:
14765 case P10V_BUILTIN_VINSERTGPRDL:
14766 case P10V_BUILTIN_VINSERTVPRBL:
14767 case P10V_BUILTIN_VINSERTVPRHL:
14768 case P10V_BUILTIN_VINSERTVPRWL:
14769 case P10V_BUILTIN_VREPLACE_ELT_UV4SI:
14770 case P10V_BUILTIN_VREPLACE_ELT_UV2DI:
14771 case P10V_BUILTIN_VREPLACE_UN_UV4SI:
14772 case P10V_BUILTIN_VREPLACE_UN_UV2DI:
14773 case P10V_BUILTIN_VXXBLEND_V16QI:
14774 case P10V_BUILTIN_VXXBLEND_V8HI:
14775 case P10V_BUILTIN_VXXBLEND_V4SI:
14776 case P10V_BUILTIN_VXXBLEND_V2DI:
14777 h.uns_p[0] = 1;
14778 h.uns_p[1] = 1;
14779 h.uns_p[2] = 1;
14780 h.uns_p[3] = 1;
14781 break;
14782
14783 /* signed permute functions with unsigned char mask. */
14784 case ALTIVEC_BUILTIN_VPERM_16QI:
14785 case ALTIVEC_BUILTIN_VPERM_8HI:
14786 case ALTIVEC_BUILTIN_VPERM_4SI:
14787 case ALTIVEC_BUILTIN_VPERM_4SF:
14788 case ALTIVEC_BUILTIN_VPERM_2DI:
14789 case ALTIVEC_BUILTIN_VPERM_2DF:
14790 case VSX_BUILTIN_VPERM_16QI:
14791 case VSX_BUILTIN_VPERM_8HI:
14792 case VSX_BUILTIN_VPERM_4SI:
14793 case VSX_BUILTIN_VPERM_4SF:
14794 case VSX_BUILTIN_VPERM_2DI:
14795 case VSX_BUILTIN_VPERM_2DF:
14796 h.uns_p[3] = 1;
14797 break;
14798
14799 /* unsigned args, signed return. */
14800 case VSX_BUILTIN_XVCVUXDSP:
14801 case VSX_BUILTIN_XVCVUXDDP_UNS:
14802 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
14803 h.uns_p[1] = 1;
14804 break;
14805
14806 /* signed args, unsigned return. */
14807 case VSX_BUILTIN_XVCVDPUXDS_UNS:
14808 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
14809 case MISC_BUILTIN_UNPACK_TD:
14810 case MISC_BUILTIN_UNPACK_V1TI:
14811 h.uns_p[0] = 1;
14812 break;
14813
14814 /* unsigned arguments, bool return (compares). */
14815 case ALTIVEC_BUILTIN_VCMPEQUB:
14816 case ALTIVEC_BUILTIN_VCMPEQUH:
14817 case ALTIVEC_BUILTIN_VCMPEQUW:
14818 case P8V_BUILTIN_VCMPEQUD:
14819 case VSX_BUILTIN_CMPGE_U16QI:
14820 case VSX_BUILTIN_CMPGE_U8HI:
14821 case VSX_BUILTIN_CMPGE_U4SI:
14822 case VSX_BUILTIN_CMPGE_U2DI:
14823 case P10V_BUILTIN_CMPGE_U1TI:
14824 case ALTIVEC_BUILTIN_VCMPGTUB:
14825 case ALTIVEC_BUILTIN_VCMPGTUH:
14826 case ALTIVEC_BUILTIN_VCMPGTUW:
14827 case P8V_BUILTIN_VCMPGTUD:
14828 case P10V_BUILTIN_VCMPGTUT:
14829 case P10V_BUILTIN_VCMPEQUT:
14830 h.uns_p[1] = 1;
14831 h.uns_p[2] = 1;
14832 break;
14833
14834 /* unsigned arguments for 128-bit pack instructions. */
14835 case MISC_BUILTIN_PACK_TD:
14836 case MISC_BUILTIN_PACK_V1TI:
14837 h.uns_p[1] = 1;
14838 h.uns_p[2] = 1;
14839 break;
14840
14841 /* unsigned second arguments (vector shift right). */
14842 case ALTIVEC_BUILTIN_VSRB:
14843 case ALTIVEC_BUILTIN_VSRH:
14844 case ALTIVEC_BUILTIN_VSRW:
14845 case P8V_BUILTIN_VSRD:
14846 /* Vector splat immediate insert */
14847 case P10V_BUILTIN_VXXSPLTI32DX_V4SI:
14848 case P10V_BUILTIN_VXXSPLTI32DX_V4SF:
14849 h.uns_p[2] = 1;
14850 break;
14851
14852 case VSX_BUILTIN_LXVP:
14853 h.uns_p[0] = 1;
14854 h.uns_p[2] = 1;
14855 break;
14856
14857 case VSX_BUILTIN_STXVP:
14858 h.uns_p[1] = 1;
14859 h.uns_p[3] = 1;
14860 break;
14861
14862 default:
14863 break;
14864 }
14865
14866 /* Figure out how many args are present. */
14867 while (num_args > 0 && h.mode[num_args] == VOIDmode)
14868 num_args--;
14869
14870 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
14871 if (!ret_type && h.uns_p[0])
14872 ret_type = builtin_mode_to_type[h.mode[0]][0];
14873
14874 /* If the required decimal float type has been disabled,
14875 then return NULL_TREE. */
14876 if (!ret_type && DECIMAL_FLOAT_MODE_P (h.mode[0]))
14877 return NULL_TREE;
14878
14879 if (!ret_type)
14880 fatal_error (input_location,
14881 "internal error: builtin function %qs had an unexpected "
14882 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
14883
14884 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
14885 arg_type[i] = NULL_TREE;
14886
14887 for (i = 0; i < num_args; i++)
14888 {
14889 int m = (int) h.mode[i+1];
14890 int uns_p = h.uns_p[i+1];
14891
14892 arg_type[i] = builtin_mode_to_type[m][uns_p];
14893 if (!arg_type[i] && uns_p)
14894 arg_type[i] = builtin_mode_to_type[m][0];
14895
14896 /* If the required decimal float type has been disabled,
14897 then return NULL_TREE. */
14898 if (!arg_type[i] && DECIMAL_FLOAT_MODE_P (m))
14899 return NULL_TREE;
14900
14901 if (!arg_type[i])
14902 fatal_error (input_location,
14903 "internal error: builtin function %qs, argument %d "
14904 "had unexpected argument type %qs", name, i,
14905 GET_MODE_NAME (m));
14906 }
14907
14908 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
14909 if (*found == NULL)
14910 {
14911 h2 = ggc_alloc<builtin_hash_struct> ();
14912 *h2 = h;
14913 *found = h2;
14914
14915 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
14916 arg_type[2], NULL_TREE);
14917 }
14918
14919 return (*found)->type;
14920 }
14921
14922 static void
rs6000_common_init_builtins(void)14923 rs6000_common_init_builtins (void)
14924 {
14925 const struct builtin_description *d;
14926 size_t i;
14927
14928 tree opaque_ftype_opaque = NULL_TREE;
14929 tree opaque_ftype_opaque_opaque = NULL_TREE;
14930 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
14931 tree opaque_ftype_opaque_opaque_opaque_opaque = NULL_TREE;
14932 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
14933
14934 /* Create Altivec and VSX builtins on machines with at least the
14935 general purpose extensions (970 and newer) to allow the use of
14936 the target attribute. */
14937
14938 if (TARGET_EXTRA_BUILTINS)
14939 builtin_mask |= RS6000_BTM_COMMON;
14940
14941 /* Add the quaternary operators. */
14942 d = bdesc_4arg;
14943 for (i = 0; i < ARRAY_SIZE (bdesc_4arg); i++, d++)
14944 {
14945 tree type;
14946 HOST_WIDE_INT mask = d->mask;
14947
14948 if ((mask & builtin_mask) != mask)
14949 {
14950 if (TARGET_DEBUG_BUILTIN)
14951 fprintf (stderr, "rs6000_builtin, skip quaternary %s\n", d->name);
14952 continue;
14953 }
14954
14955 if (rs6000_overloaded_builtin_p (d->code))
14956 {
14957 type = opaque_ftype_opaque_opaque_opaque_opaque;
14958 if (!type)
14959 type = opaque_ftype_opaque_opaque_opaque_opaque
14960 = build_function_type_list (opaque_V4SI_type_node,
14961 opaque_V4SI_type_node,
14962 opaque_V4SI_type_node,
14963 opaque_V4SI_type_node,
14964 opaque_V4SI_type_node,
14965 NULL_TREE);
14966 }
14967 else
14968 {
14969 enum insn_code icode = d->icode;
14970 if (d->name == 0)
14971 {
14972 if (TARGET_DEBUG_BUILTIN)
14973 fprintf (stderr, "rs6000_builtin, bdesc_4arg[%ld] no name\n",
14974 (long) i);
14975 continue;
14976 }
14977
14978 if (icode == CODE_FOR_nothing)
14979 {
14980 if (TARGET_DEBUG_BUILTIN)
14981 fprintf (stderr,
14982 "rs6000_builtin, skip quaternary %s (no code)\n",
14983 d->name);
14984 continue;
14985 }
14986
14987 type =
14988 builtin_quaternary_function_type (insn_data[icode].operand[0].mode,
14989 insn_data[icode].operand[1].mode,
14990 insn_data[icode].operand[2].mode,
14991 insn_data[icode].operand[3].mode,
14992 insn_data[icode].operand[4].mode,
14993 d->code);
14994 }
14995 def_builtin (d->name, type, d->code);
14996 }
14997
14998 /* Add the ternary operators. */
14999 d = bdesc_3arg;
15000 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
15001 {
15002 tree type;
15003 HOST_WIDE_INT mask = d->mask;
15004
15005 if ((mask & builtin_mask) != mask)
15006 {
15007 if (TARGET_DEBUG_BUILTIN)
15008 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
15009 continue;
15010 }
15011
15012 if (rs6000_overloaded_builtin_p (d->code))
15013 {
15014 if (! (type = opaque_ftype_opaque_opaque_opaque))
15015 type = opaque_ftype_opaque_opaque_opaque
15016 = build_function_type_list (opaque_V4SI_type_node,
15017 opaque_V4SI_type_node,
15018 opaque_V4SI_type_node,
15019 opaque_V4SI_type_node,
15020 NULL_TREE);
15021 }
15022 else
15023 {
15024 enum insn_code icode = d->icode;
15025 if (d->name == 0)
15026 {
15027 if (TARGET_DEBUG_BUILTIN)
15028 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
15029 (long unsigned)i);
15030
15031 continue;
15032 }
15033
15034 if (icode == CODE_FOR_nothing)
15035 {
15036 if (TARGET_DEBUG_BUILTIN)
15037 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
15038 d->name);
15039
15040 continue;
15041 }
15042
15043 type = builtin_function_type (insn_data[icode].operand[0].mode,
15044 insn_data[icode].operand[1].mode,
15045 insn_data[icode].operand[2].mode,
15046 insn_data[icode].operand[3].mode,
15047 d->code, d->name);
15048 }
15049
15050 def_builtin (d->name, type, d->code);
15051 }
15052
15053 /* Add the binary operators. */
15054 d = bdesc_2arg;
15055 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
15056 {
15057 machine_mode mode0, mode1, mode2;
15058 tree type;
15059 HOST_WIDE_INT mask = d->mask;
15060
15061 if ((mask & builtin_mask) != mask)
15062 {
15063 if (TARGET_DEBUG_BUILTIN)
15064 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
15065 continue;
15066 }
15067
15068 if (rs6000_overloaded_builtin_p (d->code))
15069 {
15070 const struct altivec_builtin_types *desc;
15071
15072 /* Verify the builtin we are overloading has already been defined. */
15073 type = NULL_TREE;
15074 for (desc = altivec_overloaded_builtins;
15075 desc->code != RS6000_BUILTIN_NONE; desc++)
15076 if (desc->code == d->code
15077 && rs6000_builtin_decls[(int)desc->overloaded_code])
15078 {
15079 if (! (type = opaque_ftype_opaque_opaque))
15080 type = opaque_ftype_opaque_opaque
15081 = build_function_type_list (opaque_V4SI_type_node,
15082 opaque_V4SI_type_node,
15083 opaque_V4SI_type_node,
15084 NULL_TREE);
15085 break;
15086 }
15087 }
15088 else
15089 {
15090 enum insn_code icode = d->icode;
15091 if (d->name == 0)
15092 {
15093 if (TARGET_DEBUG_BUILTIN)
15094 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
15095 (long unsigned)i);
15096
15097 continue;
15098 }
15099
15100 if (icode == CODE_FOR_nothing)
15101 {
15102 if (TARGET_DEBUG_BUILTIN)
15103 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
15104 d->name);
15105
15106 continue;
15107 }
15108
15109 mode0 = insn_data[icode].operand[0].mode;
15110 mode1 = insn_data[icode].operand[1].mode;
15111 mode2 = insn_data[icode].operand[2].mode;
15112
15113 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
15114 d->code, d->name);
15115 }
15116
15117 def_builtin (d->name, type, d->code);
15118 }
15119
15120 /* Add the simple unary operators. */
15121 d = bdesc_1arg;
15122 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
15123 {
15124 machine_mode mode0, mode1;
15125 tree type;
15126 HOST_WIDE_INT mask = d->mask;
15127
15128 if ((mask & builtin_mask) != mask)
15129 {
15130 if (TARGET_DEBUG_BUILTIN)
15131 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
15132 continue;
15133 }
15134
15135 if (rs6000_overloaded_builtin_p (d->code))
15136 {
15137 if (! (type = opaque_ftype_opaque))
15138 type = opaque_ftype_opaque
15139 = build_function_type_list (opaque_V4SI_type_node,
15140 opaque_V4SI_type_node,
15141 NULL_TREE);
15142 }
15143 else
15144 {
15145 enum insn_code icode = d->icode;
15146 if (d->name == 0)
15147 {
15148 if (TARGET_DEBUG_BUILTIN)
15149 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
15150 (long unsigned)i);
15151
15152 continue;
15153 }
15154
15155 if (icode == CODE_FOR_nothing)
15156 {
15157 if (TARGET_DEBUG_BUILTIN)
15158 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
15159 d->name);
15160
15161 continue;
15162 }
15163
15164 mode0 = insn_data[icode].operand[0].mode;
15165 mode1 = insn_data[icode].operand[1].mode;
15166
15167 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
15168 d->code, d->name);
15169 }
15170
15171 def_builtin (d->name, type, d->code);
15172 }
15173
15174 /* Add the simple no-argument operators. */
15175 d = bdesc_0arg;
15176 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
15177 {
15178 machine_mode mode0;
15179 tree type;
15180 HOST_WIDE_INT mask = d->mask;
15181
15182 if ((mask & builtin_mask) != mask)
15183 {
15184 if (TARGET_DEBUG_BUILTIN)
15185 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
15186 continue;
15187 }
15188 if (rs6000_overloaded_builtin_p (d->code))
15189 {
15190 if (!opaque_ftype_opaque)
15191 opaque_ftype_opaque
15192 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
15193 type = opaque_ftype_opaque;
15194 }
15195 else
15196 {
15197 enum insn_code icode = d->icode;
15198 if (d->name == 0)
15199 {
15200 if (TARGET_DEBUG_BUILTIN)
15201 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
15202 (long unsigned) i);
15203 continue;
15204 }
15205 if (icode == CODE_FOR_nothing)
15206 {
15207 if (TARGET_DEBUG_BUILTIN)
15208 fprintf (stderr,
15209 "rs6000_builtin, skip no-argument %s (no code)\n",
15210 d->name);
15211 continue;
15212 }
15213 mode0 = insn_data[icode].operand[0].mode;
15214 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
15215 d->code, d->name);
15216 }
15217 def_builtin (d->name, type, d->code);
15218 }
15219 }
15220
15221 /* Return the internal arg pointer used for function incoming
15222 arguments. When -fsplit-stack, the arg pointer is r12 so we need
15223 to copy it to a pseudo in order for it to be preserved over calls
15224 and suchlike. We'd really like to use a pseudo here for the
15225 internal arg pointer but data-flow analysis is not prepared to
15226 accept pseudos as live at the beginning of a function. */
15227
15228 rtx
rs6000_internal_arg_pointer(void)15229 rs6000_internal_arg_pointer (void)
15230 {
15231 if (flag_split_stack
15232 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
15233 == NULL))
15234
15235 {
15236 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
15237 {
15238 rtx pat;
15239
15240 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
15241 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
15242
15243 /* Put the pseudo initialization right after the note at the
15244 beginning of the function. */
15245 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
15246 gen_rtx_REG (Pmode, 12));
15247 push_topmost_sequence ();
15248 emit_insn_after (pat, get_insns ());
15249 pop_topmost_sequence ();
15250 }
15251 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
15252 FIRST_PARM_OFFSET (current_function_decl));
15253 return copy_to_reg (ret);
15254 }
15255 return virtual_incoming_args_rtx;
15256 }
15257
15258
15259 /* A C compound statement that outputs the assembler code for a thunk
15260 function, used to implement C++ virtual function calls with
15261 multiple inheritance. The thunk acts as a wrapper around a virtual
15262 function, adjusting the implicit object parameter before handing
15263 control off to the real function.
15264
15265 First, emit code to add the integer DELTA to the location that
15266 contains the incoming first argument. Assume that this argument
15267 contains a pointer, and is the one used to pass the `this' pointer
15268 in C++. This is the incoming argument *before* the function
15269 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15270 values of all other incoming arguments.
15271
15272 After the addition, emit code to jump to FUNCTION, which is a
15273 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15274 not touch the return address. Hence returning from FUNCTION will
15275 return to whoever called the current `thunk'.
15276
15277 The effect must be as if FUNCTION had been called directly with the
15278 adjusted first argument. This macro is responsible for emitting
15279 all of the code for a thunk function; output_function_prologue()
15280 and output_function_epilogue() are not invoked.
15281
15282 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15283 been extracted from it.) It might possibly be useful on some
15284 targets, but probably not.
15285
15286 If you do not define this macro, the target-independent code in the
15287 C++ frontend will generate a less efficient heavyweight thunk that
15288 calls FUNCTION instead of jumping to it. The generic approach does
15289 not support varargs. */
15290
15291 void
rs6000_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset,tree function)15292 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15293 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15294 tree function)
15295 {
15296 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
15297 rtx this_rtx, funexp;
15298 rtx_insn *insn;
15299
15300 reload_completed = 1;
15301 epilogue_completed = 1;
15302
15303 /* Mark the end of the (empty) prologue. */
15304 emit_note (NOTE_INSN_PROLOGUE_END);
15305
15306 /* Find the "this" pointer. If the function returns a structure,
15307 the structure return pointer is in r3. */
15308 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15309 this_rtx = gen_rtx_REG (Pmode, 4);
15310 else
15311 this_rtx = gen_rtx_REG (Pmode, 3);
15312
15313 /* Apply the constant offset, if required. */
15314 if (delta)
15315 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
15316
15317 /* Apply the offset from the vtable, if required. */
15318 if (vcall_offset)
15319 {
15320 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15321 rtx tmp = gen_rtx_REG (Pmode, 12);
15322
15323 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
15324 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15325 {
15326 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
15327 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15328 }
15329 else
15330 {
15331 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15332
15333 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15334 }
15335 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
15336 }
15337
15338 /* Generate a tail call to the target function. */
15339 if (!TREE_USED (function))
15340 {
15341 assemble_external (function);
15342 TREE_USED (function) = 1;
15343 }
15344 funexp = XEXP (DECL_RTL (function), 0);
15345 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15346
15347 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx, const0_rtx));
15348 SIBLING_CALL_P (insn) = 1;
15349 emit_barrier ();
15350
15351 /* Run just enough of rest_of_compilation to get the insns emitted.
15352 There's not really enough bulk here to make other passes such as
15353 instruction scheduling worth while. */
15354 insn = get_insns ();
15355 shorten_branches (insn);
15356 assemble_start_function (thunk_fndecl, fnname);
15357 final_start_function (insn, file, 1);
15358 final (insn, file, 1);
15359 final_end_function ();
15360 assemble_end_function (thunk_fndecl, fnname);
15361
15362 reload_completed = 0;
15363 epilogue_completed = 0;
15364 }
15365
15366 #include "gt-rs6000-call.h"
15367