1 /* { dg-require-effective-target power10_ok } */
2 /* { dg-options "-O2 -mdejagnu-cpu=power10" } */
3
4 /* This tests whether GCC generates the ISA 3.1 BRW byte swap instruction for
5 GPR data, but generates XXBRW for data in a vector register. */
6
7 unsigned int
bswap_int(unsigned int a)8 bswap_int (unsigned int a)
9 {
10 return __builtin_bswap32 (a); /* { dg-final { scan-assembler {\mbrw\M} } } */
11 }
12
13 double
bswap_int_dbl(unsigned int a)14 bswap_int_dbl (unsigned int a)
15 {
16 unsigned int b = a;
17 /* Force the value to be loaded into a vector register. */
18 __asm__ (" # %x0" : "+wa" (b));
19
20 /* { dg-final { scan-assembler {\mxxbrw\M} } } */
21 return (double) __builtin_bswap32 (b);
22 }
23