1 /* $NetBSD: ahd_pci.c,v 1.35 2014/03/29 19:28:24 christos Exp $ */
2
3 /*
4 * Product specific probe and attach routines for:
5 * aic7901 and aic7902 SCSI controllers
6 *
7 * Copyright (c) 1994-2001 Justin T. Gibbs.
8 * Copyright (c) 2000-2002 Adaptec Inc.
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions, and the following disclaimer,
16 * without modification.
17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
18 * substantially similar to the "NO WARRANTY" disclaimer below
19 * ("Disclaimer") and any redistribution must be conditioned upon
20 * including a substantially similar Disclaimer requirement for further
21 * binary redistribution.
22 * 3. Neither the names of the above-listed copyright holders nor the names
23 * of any contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * Alternatively, this software may be distributed under the terms of the
27 * GNU General Public License ("GPL") version 2 as published by the Free
28 * Software Foundation.
29 *
30 * NO WARRANTY
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41 * POSSIBILITY OF SUCH DAMAGES.
42 *
43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $
44 *
45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $
46 */
47 /*
48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc.
49 * - April 2003
50 */
51
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.35 2014/03/29 19:28:24 christos Exp $");
54
55 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */
56 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */
57
58 #include <dev/ic/aic79xx_osm.h>
59 #include <dev/ic/aic79xx_inline.h>
60
61 static inline uint64_t
ahd_compose_id(u_int device,u_int vendor,u_int subdevice,u_int subvendor)62 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
63 {
64 uint64_t id;
65
66 id = subvendor
67 | (subdevice << 16)
68 | ((uint64_t)vendor << 32)
69 | ((uint64_t)device << 48);
70
71 return (id);
72 }
73
74 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
75 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull
76 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
77 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
78 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull
79
80 #define ID_AIC7901 0x800F9005FFFF9005ull
81 #define ID_AHA_29320A 0x8000900500609005ull
82 #define ID_AHA_29320ALP 0x8017900500449005ull
83 #define ID_AHA_29320LPE 0x8017900500459005ull
84
85 #define ID_AIC7901A 0x801E9005FFFF9005ull
86 #define ID_AHA_29320LP 0x8014900500449005ull
87
88 #define ID_AIC7902 0x801F9005FFFF9005ull
89 #define ID_AIC7902_B 0x801D9005FFFF9005ull
90 #define ID_AHA_39320 0x8010900500409005ull
91 #define ID_AHA_29320 0x8012900500429005ull
92 #define ID_AHA_29320B 0x8013900500439005ull
93 #define ID_AHA_39320_B 0x8015900500409005ull
94 #define ID_AHA_39320A 0x8016900500409005ull
95 #define ID_AHA_39320D 0x8011900500419005ull
96 #define ID_AHA_39320D_B 0x801C900500419005ull
97 #define ID_AHA_39320_B_DELL 0x8015900501681028ull
98 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull
99 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull
100 #define ID_AIC7902_PCI_REV_A4 0x3
101 #define ID_AIC7902_PCI_REV_B0 0x10
102 #define SUBID_HP 0x0E11
103
104 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
105
106 #define DEVID_9005_TYPE(id) ((id) & 0xF)
107 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
108 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */
109 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
110
111 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
112
113 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
114
115 #define SUBID_9005_TYPE(id) ((id) & 0xF)
116 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */
117 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
118
119 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
120
121 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
122
123 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
124 #define SUBID_9005_SEEPTYPE_NONE 0x0
125 #define SUBID_9005_SEEPTYPE_4K 0x1
126
127 static ahd_device_setup_t ahd_aic7901_setup;
128 static ahd_device_setup_t ahd_aic7901A_setup;
129 static ahd_device_setup_t ahd_aic7902_setup;
130 static ahd_device_setup_t ahd_aic790X_setup;
131
132 static struct ahd_pci_identity ahd_pci_ident_table [] =
133 {
134 /* aic7901 based controllers */
135 {
136 ID_AHA_29320A,
137 ID_ALL_MASK,
138 "Adaptec 29320A Ultra320 SCSI adapter",
139 ahd_aic7901_setup
140 },
141 {
142 ID_AHA_29320ALP,
143 ID_ALL_MASK,
144 "Adaptec 29320ALP Ultra320 SCSI adapter",
145 ahd_aic7901_setup
146 },
147 {
148 ID_AHA_29320LPE,
149 ID_ALL_MASK,
150 "Adaptec 29320LPE Ultra320 SCSI adapter",
151 ahd_aic7901_setup
152 },
153 /* aic7901A based controllers */
154 {
155 ID_AHA_29320LP,
156 ID_ALL_MASK,
157 "Adaptec 29320LP Ultra320 SCSI adapter",
158 ahd_aic7901A_setup
159 },
160 /* aic7902 based controllers */
161 {
162 ID_AHA_39320,
163 ID_ALL_MASK,
164 "Adaptec 39320 Ultra320 SCSI adapter",
165 ahd_aic7902_setup
166 },
167 {
168 ID_AHA_39320_B,
169 ID_ALL_MASK,
170 "Adaptec 39320 Ultra320 SCSI adapter",
171 ahd_aic7902_setup
172 },
173 {
174 ID_AHA_39320_B_DELL,
175 ID_ALL_IROC_MASK,
176 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
177 ahd_aic7902_setup
178 },
179 {
180 ID_AHA_39320A,
181 ID_ALL_MASK,
182 "Adaptec 39320A Ultra320 SCSI adapter",
183 ahd_aic7902_setup
184 },
185 {
186 ID_AHA_39320D,
187 ID_ALL_MASK,
188 "Adaptec 39320D Ultra320 SCSI adapter",
189 ahd_aic7902_setup
190 },
191 {
192 ID_AHA_39320D_HP,
193 ID_ALL_MASK,
194 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
195 ahd_aic7902_setup
196 },
197 {
198 ID_AHA_39320D_B,
199 ID_ALL_MASK,
200 "Adaptec 39320D Ultra320 SCSI adapter",
201 ahd_aic7902_setup
202 },
203 {
204 ID_AHA_39320D_B_HP,
205 ID_ALL_MASK,
206 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
207 ahd_aic7902_setup
208 },
209 /* Generic chip probes for devices we don't know 'exactly' */
210 {
211 ID_AIC7901 & ID_9005_GENERIC_MASK,
212 ID_9005_GENERIC_MASK,
213 "Adaptec AIC7901 Ultra320 SCSI adapter",
214 ahd_aic7901_setup
215 },
216 {
217 ID_AIC7901A & ID_DEV_VENDOR_MASK,
218 ID_DEV_VENDOR_MASK,
219 "Adaptec AIC7901A Ultra320 SCSI adapter",
220 ahd_aic7901A_setup
221 },
222 {
223 ID_AIC7902 & ID_9005_GENERIC_MASK,
224 ID_9005_GENERIC_MASK,
225 "Adaptec AIC7902 Ultra320 SCSI adapter",
226 ahd_aic7902_setup
227 }
228 };
229
230 static const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
231
232 #define DEVCONFIG 0x40
233 #define PCIXINITPAT 0x0000E000ul
234 #define PCIXINIT_PCI33_66 0x0000E000ul
235 #define PCIXINIT_PCIX50_66 0x0000C000ul
236 #define PCIXINIT_PCIX66_100 0x0000A000ul
237 #define PCIXINIT_PCIX100_133 0x00008000ul
238 #define PCI_BUS_MODES_INDEX(devconfig) \
239 (((devconfig) & PCIXINITPAT) >> 13)
240
241 static const char *pci_bus_modes[] =
242 {
243 "PCI bus mode unknown",
244 "PCI bus mode unknown",
245 "PCI bus mode unknown",
246 "PCI bus mode unknown",
247 "PCI-X 101-133 MHz",
248 "PCI-X 67-100 MHz",
249 "PCI-X 50-66 MHz",
250 "PCI 33 or 66 MHz"
251 };
252
253 #define TESTMODE 0x00000800ul
254 #define IRDY_RST 0x00000200ul
255 #define FRAME_RST 0x00000100ul
256 #define PCI64BIT 0x00000080ul
257 #define MRDCEN 0x00000040ul
258 #define ENDIANSEL 0x00000020ul
259 #define MIXQWENDIANEN 0x00000008ul
260 #define DACEN 0x00000004ul
261 #define STPWLEVEL 0x00000002ul
262 #define QWENDIANSEL 0x00000001ul
263
264 #define DEVCONFIG1 0x44
265 #define PREQDIS 0x01
266
267 #define LATTIME 0x0000ff00ul
268
269 static int ahd_check_extport(struct ahd_softc *ahd);
270 static void ahd_configure_termination(struct ahd_softc *ahd,
271 u_int adapter_control);
272 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
273
274 static int ahd_pci_test_register_access(struct ahd_softc *);
275
276 static int ahd_pci_intr(struct ahd_softc *);
277
278 static const struct ahd_pci_identity *
ahd_find_pci_device(pcireg_t id,pcireg_t subid)279 ahd_find_pci_device(pcireg_t id, pcireg_t subid)
280 {
281 u_int64_t full_id;
282 const struct ahd_pci_identity *entry;
283 u_int i;
284
285 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id),
286 PCI_PRODUCT(subid), PCI_VENDOR(subid));
287
288 for (i = 0; i < ahd_num_pci_devs; i++) {
289 entry = &ahd_pci_ident_table[i];
290 if (entry->full_id == (full_id & entry->id_mask))
291 return (entry);
292 }
293 return (NULL);
294 }
295
296 static int
ahd_pci_probe(device_t parent,cfdata_t match,void * aux)297 ahd_pci_probe(device_t parent, cfdata_t match, void *aux)
298 {
299 struct pci_attach_args *pa = aux;
300 const struct ahd_pci_identity *entry;
301 pcireg_t subid;
302
303 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
304 entry = ahd_find_pci_device(pa->pa_id, subid);
305 return entry != NULL ? 1 : 0;
306 }
307
308 static void
ahd_pci_attach(device_t parent,device_t self,void * aux)309 ahd_pci_attach(device_t parent, device_t self, void *aux)
310 {
311 struct pci_attach_args *pa = aux;
312 struct ahd_softc *ahd = device_private(self);
313
314 const struct ahd_pci_identity *entry;
315
316 uint32_t devconfig;
317 pcireg_t command;
318 int error;
319 pcireg_t subid;
320 uint16_t subvendor;
321 pcireg_t reg;
322 int ioh_valid, ioh2_valid, memh_valid;
323 pcireg_t memtype;
324 pci_intr_handle_t ih;
325 const char *intrstr;
326 struct ahd_pci_busdata *bd;
327 char intrbuf[PCI_INTRSTR_LEN];
328
329 ahd->sc_dev = self;
330 ahd_set_name(ahd, device_xname(self));
331 ahd->parent_dmat = pa->pa_dmat;
332
333 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
334 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
335 entry = ahd_find_pci_device(pa->pa_id, subid);
336 if (entry == NULL)
337 return;
338
339 /* Keep information about the PCI bus */
340 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT);
341 if (bd == NULL) {
342 aprint_error("%s: unable to allocate bus-specific data\n",
343 ahd_name(ahd));
344 return;
345 }
346 memset(bd, 0, sizeof(struct ahd_pci_busdata));
347
348 bd->pc = pa->pa_pc;
349 bd->tag = pa->pa_tag;
350 bd->func = pa->pa_function;
351 bd->dev = pa->pa_device;
352
353 ahd->bus_data = bd;
354
355 ahd->description = entry->name;
356
357 ahd->seep_config = malloc(sizeof(*ahd->seep_config),
358 M_DEVBUF, M_NOWAIT);
359 if (ahd->seep_config == NULL) {
360 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd));
361 return;
362 }
363 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config));
364
365 LIST_INIT(&ahd->pending_scbs);
366 ahd_timer_init(&ahd->reset_timer);
367 ahd_timer_init(&ahd->stat_timer);
368 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
369 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
370 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
371 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
372 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
373 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
374 ahd->int_coalescing_stop_threshold =
375 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
376
377 if (ahd_platform_alloc(ahd, NULL) != 0) {
378 ahd_free(ahd);
379 return;
380 }
381
382 /*
383 * Record if this is an HP board.
384 */
385 subvendor = PCI_VENDOR(subid);
386 if (subvendor == SUBID_HP)
387 ahd->flags |= AHD_HP_BOARD;
388
389 error = entry->setup(ahd, pa);
390 if (error != 0)
391 return;
392
393 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
394 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
395 ahd->chip |= AHD_PCI;
396 /* Disable PCIX workarounds when running in PCI mode. */
397 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
398 } else {
399 ahd->chip |= AHD_PCIX;
400 }
401 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
402
403 memh_valid = ioh_valid = ioh2_valid = 0;
404
405 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX,
406 &bd->pcix_off, NULL)) {
407 if (ahd->chip & AHD_PCIX)
408 aprint_error_dev(self,
409 "warning: can't find PCI-X capability\n");
410 ahd->chip &= ~AHD_PCIX;
411 ahd->chip |= AHD_PCI;
412 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
413 }
414
415 /*
416 * Map PCI Registers
417 */
418 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) {
419 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
420 AHD_PCI_MEMADDR);
421 switch (memtype) {
422 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
423 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
424 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR,
425 memtype, 0, &ahd->tags[0],
426 &ahd->bshs[0],
427 NULL, NULL) == 0);
428 if (memh_valid) {
429 ahd->tags[1] = ahd->tags[0];
430 bus_space_subregion(ahd->tags[0], ahd->bshs[0],
431 /*offset*/0x100,
432 /*size*/0x100,
433 &ahd->bshs[1]);
434 if (ahd_pci_test_register_access(ahd) != 0)
435 memh_valid = 0;
436 }
437 break;
438 default:
439 memh_valid = 0;
440 aprint_error("%s: unknown memory type: 0x%x\n",
441 ahd_name(ahd), memtype);
442 break;
443 }
444
445 if (memh_valid) {
446 command &= ~PCI_COMMAND_IO_ENABLE;
447 pci_conf_write(pa->pa_pc, pa->pa_tag,
448 PCI_COMMAND_STATUS_REG, command);
449 }
450 #ifdef AHD_DEBUG
451 printf("%s: doing memory mapping shs0 0x%lx, shs1 0x%lx\n",
452 ahd_name(ahd), ahd->bshs[0], ahd->bshs[1]);
453 #endif
454 }
455
456 if (command & PCI_COMMAND_IO_ENABLE) {
457 /* First BAR */
458 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR,
459 PCI_MAPREG_TYPE_IO, 0,
460 &ahd->tags[0], &ahd->bshs[0],
461 NULL, NULL) == 0);
462
463 /* 2nd BAR */
464 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1,
465 PCI_MAPREG_TYPE_IO, 0,
466 &ahd->tags[1], &ahd->bshs[1],
467 NULL, NULL) == 0);
468
469 if (ioh_valid && ioh2_valid) {
470 KASSERT(memh_valid == 0);
471 command &= ~PCI_COMMAND_MEM_ENABLE;
472 pci_conf_write(pa->pa_pc, pa->pa_tag,
473 PCI_COMMAND_STATUS_REG, command);
474 }
475 #ifdef AHD_DEBUG
476 printf("%s: doing io mapping shs0 0x%lx, shs1 0x%lx\n",
477 ahd_name(ahd), ahd->bshs[0], ahd->bshs[1]);
478 #endif
479
480 }
481
482 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) {
483 aprint_error("%s: unable to map registers\n", ahd_name(ahd));
484 return;
485 }
486
487 aprint_normal("\n");
488 aprint_naive("\n");
489
490 /* power up chip */
491 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
492 pci_activate_null)) && error != EOPNOTSUPP) {
493 aprint_error_dev(self, "cannot activate %d\n", error);
494 return;
495 }
496 /*
497 * Should we bother disabling 39Bit addressing
498 * based on installed memory?
499 */
500 if (sizeof(bus_addr_t) > 4)
501 ahd->flags |= AHD_39BIT_ADDRESSING;
502
503 /*
504 * If we need to support high memory, enable dual
505 * address cycles. This bit must be set to enable
506 * high address bit generation even if we are on a
507 * 64bit bus (PCI64BIT set in devconfig).
508 */
509 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
510 uint32_t dvconfig;
511
512 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd));
513 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
514 dvconfig |= DACEN;
515 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, dvconfig);
516 }
517
518 /* Ensure busmastering is enabled */
519 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
520 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
521 reg | PCI_COMMAND_MASTER_ENABLE);
522
523 ahd_softc_init(ahd);
524
525 /*
526 * Map the interrupt routines
527 */
528 ahd->bus_intr = ahd_pci_intr;
529
530 error = ahd_reset(ahd, /*reinit*/FALSE);
531 if (error != 0) {
532 ahd_free(ahd);
533 return;
534 }
535
536 if (pci_intr_map(pa, &ih)) {
537 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd));
538 ahd_free(ahd);
539 return;
540 }
541 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
542 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd);
543 if (ahd->ih == NULL) {
544 aprint_error("%s: couldn't establish interrupt",
545 ahd_name(ahd));
546 if (intrstr != NULL)
547 aprint_error(" at %s", intrstr);
548 aprint_error("\n");
549 ahd_free(ahd);
550 return;
551 }
552 if (intrstr != NULL)
553 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd),
554 intrstr);
555
556 /* Get the size of the cache */
557 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
558 ahd->pci_cachesize *= 4;
559
560 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
561 /* See if we have a SEEPROM and perform auto-term */
562 error = ahd_check_extport(ahd);
563 if (error != 0)
564 return;
565
566 /* Core initialization */
567 error = ahd_init(ahd);
568 if (error != 0)
569 return;
570
571 /*
572 * Link this softc in with all other ahd instances.
573 */
574 ahd_attach(ahd);
575 }
576
577 CFATTACH_DECL_NEW(ahd_pci, sizeof(struct ahd_softc),
578 ahd_pci_probe, ahd_pci_attach, NULL, NULL);
579
580 /*
581 * Perform some simple tests that should catch situations where
582 * our registers are invalidly mapped.
583 */
584 static int
ahd_pci_test_register_access(struct ahd_softc * ahd)585 ahd_pci_test_register_access(struct ahd_softc *ahd)
586 {
587 uint32_t cmd;
588 struct ahd_pci_busdata *bd = ahd->bus_data;
589 u_int targpcistat;
590 uint32_t pci_status1;
591 int error;
592 uint8_t hcntrl;
593
594 error = EIO;
595
596 /*
597 * Enable PCI error interrupt status, but suppress NMIs
598 * generated by SERR raised due to target aborts.
599 */
600 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG);
601 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG,
602 cmd & ~PCI_COMMAND_SERR_ENABLE);
603
604 /*
605 * First a simple test to see if any
606 * registers can be read. Reading
607 * HCNTRL has no side effects and has
608 * at least one bit that is guaranteed to
609 * be zero so it is a good register to
610 * use for this test.
611 */
612 hcntrl = ahd_inb(ahd, HCNTRL);
613 if (hcntrl == 0xFF)
614 goto fail;
615
616 /*
617 * Next create a situation where write combining
618 * or read prefetching could be initiated by the
619 * CPU or host bridge. Our device does not support
620 * either, so look for data corruption and/or flaged
621 * PCI errors. First pause without causing another
622 * chip reset.
623 */
624 hcntrl &= ~CHIPRST;
625 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
626 while (ahd_is_paused(ahd) == 0)
627 ;
628
629 /* Clear any PCI errors that occurred before our driver attached. */
630 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
631 targpcistat = ahd_inb(ahd, TARGPCISTAT);
632 ahd_outb(ahd, TARGPCISTAT, targpcistat);
633 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG);
634 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1);
635 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
636 ahd_outb(ahd, CLRINT, CLRPCIINT);
637
638 ahd_outb(ahd, SEQCTL0, PERRORDIS);
639 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
640 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
641 goto fail;
642
643 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
644 u_int trgpcistat;
645
646 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
647 trgpcistat = ahd_inb(ahd, TARGPCISTAT);
648 if ((trgpcistat & STA) != 0)
649 goto fail;
650 }
651
652 error = 0;
653
654 fail:
655 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
656
657 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
658 targpcistat = ahd_inb(ahd, TARGPCISTAT);
659
660 /* Silently clear any latched errors. */
661 ahd_outb(ahd, TARGPCISTAT, targpcistat);
662 pci_status1 = pci_conf_read(bd->pc, bd->tag,
663 PCI_COMMAND_STATUS_REG);
664 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG,
665 pci_status1);
666 ahd_outb(ahd, CLRINT, CLRPCIINT);
667 }
668 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
669 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd);
670 return (error);
671 }
672
673 /*
674 * Check the external port logic for a serial eeprom
675 * and termination/cable detection contrls.
676 */
677 static int
ahd_check_extport(struct ahd_softc * ahd)678 ahd_check_extport(struct ahd_softc *ahd)
679 {
680 struct vpd_config vpd;
681 struct seeprom_config *sc;
682 u_int adapter_control;
683 int have_seeprom;
684 int error;
685
686 sc = ahd->seep_config;
687 have_seeprom = ahd_acquire_seeprom(ahd);
688 if (have_seeprom) {
689 u_int start_addr;
690
691 /*
692 * Fetch VPD for this function and parse it.
693 */
694 #ifdef AHD_DEBUG
695 printf("%s: Reading VPD from SEEPROM...",
696 ahd_name(ahd));
697 #endif
698 /* Address is always in units of 16bit words */
699 start_addr = ((2 * sizeof(*sc))
700 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
701
702 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
703 start_addr, sizeof(vpd)/2,
704 /*bytestream*/TRUE);
705 if (error == 0)
706 error = ahd_parse_vpddata(ahd, &vpd);
707 #ifdef AHD_DEBUG
708 printf("%s: VPD parsing %s\n",
709 ahd_name(ahd),
710 error == 0 ? "successful" : "failed");
711 #endif
712
713 #ifdef AHD_DEBUG
714 printf("%s: Reading SEEPROM...", ahd_name(ahd));
715 #endif
716
717 /* Address is always in units of 16bit words */
718 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
719
720 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
721 start_addr, sizeof(*sc)/2,
722 /*bytestream*/FALSE);
723
724 if (error != 0) {
725 #ifdef AHD_DEBUG
726 printf("Unable to read SEEPROM\n");
727 #endif
728 have_seeprom = 0;
729 } else {
730 have_seeprom = ahd_verify_cksum(sc);
731 #ifdef AHD_DEBUG
732 if (have_seeprom == 0)
733 printf ("checksum error\n");
734 else
735 printf ("done.\n");
736 #endif
737 }
738 ahd_release_seeprom(ahd);
739 }
740
741 if (!have_seeprom) {
742 u_int nvram_scb;
743
744 /*
745 * Pull scratch ram settings and treat them as
746 * if they are the contents of an seeprom if
747 * the 'ADPT', 'BIOS', or 'ASPI' signature is found
748 * in SCB 0xFF. We manually compose the data as 16bit
749 * values to avoid endian issues.
750 */
751 ahd_set_scbptr(ahd, 0xFF);
752 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
753 if (nvram_scb != 0xFF
754 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
755 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
756 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
757 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
758 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
759 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
760 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
761 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
762 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
763 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
764 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
765 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
766 uint16_t *sc_data;
767 int i;
768
769 ahd_set_scbptr(ahd, nvram_scb);
770 sc_data = (uint16_t *)sc;
771 for (i = 0; i < 64; i += 2)
772 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
773 have_seeprom = ahd_verify_cksum(sc);
774 if (have_seeprom)
775 ahd->flags |= AHD_SCB_CONFIG_USED;
776 }
777 }
778
779 #ifdef AHD_DEBUG
780 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
781 uint16_t *sc_data;
782 int i;
783
784 printf("%s: Seeprom Contents:", ahd_name(ahd));
785 sc_data = (uint16_t *)sc;
786 for (i = 0; i < (sizeof(*sc)); i += 2)
787 printf("\n\t0x%.4x", sc_data[i]);
788 printf("\n");
789 }
790 #endif
791
792 if (!have_seeprom) {
793 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd));
794 ahd->flags |= AHD_USEDEFAULTS;
795 error = ahd_default_config(ahd);
796 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
797 free(ahd->seep_config, M_DEVBUF);
798 ahd->seep_config = NULL;
799 } else {
800 error = ahd_parse_cfgdata(ahd, sc);
801 adapter_control = sc->adapter_control;
802 }
803 if (error != 0)
804 return (error);
805
806 ahd_configure_termination(ahd, adapter_control);
807
808 return (0);
809 }
810
811 static void
ahd_configure_termination(struct ahd_softc * ahd,u_int adapter_control)812 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
813 {
814 int error;
815 u_int sxfrctl1;
816 uint8_t termctl;
817 uint32_t devconfig;
818 struct ahd_pci_busdata *bd = ahd->bus_data;
819
820 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG);
821 devconfig &= ~STPWLEVEL;
822 if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
823 devconfig |= STPWLEVEL;
824 #ifdef AHD_DEBUG
825 printf("%s: STPWLEVEL is %s\n",
826 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
827 #endif
828 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig);
829
830 /* Make sure current sensing is off. */
831 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
832 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
833 }
834
835 /*
836 * Read to sense. Write to set.
837 */
838 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
839 if ((adapter_control & CFAUTOTERM) == 0) {
840 if (bootverbose)
841 printf("%s: Manual Primary Termination\n",
842 ahd_name(ahd));
843 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
844 if ((adapter_control & CFSTERM) != 0)
845 termctl |= FLX_TERMCTL_ENPRILOW;
846 if ((adapter_control & CFWSTERM) != 0)
847 termctl |= FLX_TERMCTL_ENPRIHIGH;
848 } else if (error != 0) {
849 if (bootverbose)
850 printf("%s: Primary Auto-Term Sensing failed! "
851 "Using Defaults.\n", ahd_name(ahd));
852 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
853 }
854
855 if ((adapter_control & CFSEAUTOTERM) == 0) {
856 if (bootverbose)
857 printf("%s: Manual Secondary Termination\n",
858 ahd_name(ahd));
859 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
860 if ((adapter_control & CFSELOWTERM) != 0)
861 termctl |= FLX_TERMCTL_ENSECLOW;
862 if ((adapter_control & CFSEHIGHTERM) != 0)
863 termctl |= FLX_TERMCTL_ENSECHIGH;
864 } else if (error != 0) {
865 if (bootverbose)
866 printf("%s: Secondary Auto-Term Sensing failed! "
867 "Using Defaults.\n", ahd_name(ahd));
868 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
869 }
870
871 /*
872 * Now set the termination based on what we found.
873 */
874 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
875 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
876 ahd->flags |= AHD_TERM_ENB_A;
877 sxfrctl1 |= STPWEN;
878 }
879 /* Must set the latch once in order to be effective. */
880 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
881 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
882
883 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
884 if (error != 0) {
885 aprint_error("%s: Unable to set termination settings!\n",
886 ahd_name(ahd));
887 } else {
888 if (bootverbose) {
889 printf("%s: Primary High byte termination %sabled\n",
890 ahd_name(ahd),
891 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
892
893 printf("%s: Primary Low byte termination %sabled\n",
894 ahd_name(ahd),
895 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
896
897 printf("%s: Secondary High byte termination %sabled\n",
898 ahd_name(ahd),
899 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
900
901 printf("%s: Secondary Low byte termination %sabled\n",
902 ahd_name(ahd),
903 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
904 }
905 }
906 return;
907 }
908
909 #define DPE 0x80
910 #define SSE 0x40
911 #define RMA 0x20
912 #define RTA 0x10
913 #define STA 0x08
914 #define DPR 0x01
915
916 static const char *split_status_source[] =
917 {
918 "DFF0",
919 "DFF1",
920 "OVLY",
921 "CMC",
922 };
923
924 static const char *pci_status_source[] =
925 {
926 "DFF0",
927 "DFF1",
928 "SG",
929 "CMC",
930 "OVLY",
931 "NONE",
932 "MSI",
933 "TARG"
934 };
935
936 static const char *split_status_strings[] =
937 {
938 "%s: Received split response in %s.\n",
939 "%s: Received split completion error message in %s\n",
940 "%s: Receive overrun in %s\n",
941 "%s: Count not complete in %s\n",
942 "%s: Split completion data bucket in %s\n",
943 "%s: Split completion address error in %s\n",
944 "%s: Split completion byte count error in %s\n",
945 "%s: Signaled Target-abort to early terminate a split in %s\n"
946 };
947
948 static const char *pci_status_strings[] =
949 {
950 "%s: Data Parity Error has been reported via PERR# in %s\n",
951 "%s: Target initial wait state error in %s\n",
952 "%s: Split completion read data parity error in %s\n",
953 "%s: Split completion address attribute parity error in %s\n",
954 "%s: Received a Target Abort in %s\n",
955 "%s: Received a Master Abort in %s\n",
956 "%s: Signal System Error Detected in %s\n",
957 "%s: Address or Write Phase Parity Error Detected in %s.\n"
958 };
959
960 static int
ahd_pci_intr(struct ahd_softc * ahd)961 ahd_pci_intr(struct ahd_softc *ahd)
962 {
963 uint8_t pci_status[8];
964 ahd_mode_state saved_modes;
965 u_int pci_status1;
966 u_int intstat;
967 u_int i;
968 u_int reg;
969 struct ahd_pci_busdata *bd = ahd->bus_data;
970
971 intstat = ahd_inb(ahd, INTSTAT);
972
973 if ((intstat & SPLTINT) != 0)
974 ahd_pci_split_intr(ahd, intstat);
975
976 if ((intstat & PCIINT) == 0)
977 return 0;
978
979 printf("%s: PCI error Interrupt\n", ahd_name(ahd));
980 saved_modes = ahd_save_modes(ahd);
981 ahd_dump_card_state(ahd);
982 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
983 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
984
985 if (i == 5)
986 continue;
987 pci_status[i] = ahd_inb(ahd, reg);
988 /* Clear latched errors. So our interrupt deasserts. */
989 ahd_outb(ahd, reg, pci_status[i]);
990 }
991
992 for (i = 0; i < 8; i++) {
993 u_int bit;
994
995 if (i == 5)
996 continue;
997
998 for (bit = 0; bit < 8; bit++) {
999
1000 if ((pci_status[i] & (0x1 << bit)) != 0) {
1001 static const char *s;
1002
1003 s = pci_status_strings[bit];
1004 if (i == 7/*TARG*/ && bit == 3)
1005 s = "%s: Signaled Target Abort\n";
1006 printf(s, ahd_name(ahd), pci_status_source[i]);
1007 }
1008 }
1009 }
1010 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG);
1011 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1);
1012
1013 ahd_restore_modes(ahd, saved_modes);
1014 ahd_outb(ahd, CLRINT, CLRPCIINT);
1015 ahd_unpause(ahd);
1016
1017 return 1;
1018 }
1019
1020 static void
ahd_pci_split_intr(struct ahd_softc * ahd,u_int intstat)1021 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
1022 {
1023 uint8_t split_status[4];
1024 uint8_t split_status1[4];
1025 uint8_t sg_split_status[2];
1026 uint8_t sg_split_status1[2];
1027 ahd_mode_state saved_modes;
1028 u_int i;
1029 pcireg_t pcix_status;
1030 struct ahd_pci_busdata *bd = ahd->bus_data;
1031
1032 /*
1033 * Check for splits in all modes. Modes 0 and 1
1034 * additionally have SG engine splits to look at.
1035 */
1036 pcix_status = pci_conf_read(bd->pc, bd->tag,
1037 bd->pcix_off + PCIX_STATUS);
1038 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
1039 ahd_name(ahd), pcix_status);
1040
1041 saved_modes = ahd_save_modes(ahd);
1042 for (i = 0; i < 4; i++) {
1043 ahd_set_modes(ahd, i, i);
1044
1045 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
1046 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
1047 /* Clear latched errors. So our interrupt deasserts. */
1048 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
1049 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
1050 if (i > 1)
1051 continue;
1052 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
1053 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
1054 /* Clear latched errors. So our interrupt deasserts. */
1055 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
1056 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
1057 }
1058
1059 for (i = 0; i < 4; i++) {
1060 u_int bit;
1061
1062 for (bit = 0; bit < 8; bit++) {
1063
1064 if ((split_status[i] & (0x1 << bit)) != 0) {
1065 static const char *s;
1066
1067 s = split_status_strings[bit];
1068 printf(s, ahd_name(ahd),
1069 split_status_source[i]);
1070 }
1071
1072 if (i > 0)
1073 continue;
1074
1075 if ((sg_split_status[i] & (0x1 << bit)) != 0) {
1076 static const char *s;
1077
1078 s = split_status_strings[bit];
1079 printf(s, ahd_name(ahd), "SG");
1080 }
1081 }
1082 }
1083 /*
1084 * Clear PCI-X status bits.
1085 */
1086 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCIX_STATUS,
1087 pcix_status);
1088 ahd_outb(ahd, CLRINT, CLRSPLTINT);
1089 ahd_restore_modes(ahd, saved_modes);
1090 }
1091
1092 static int
ahd_aic7901_setup(struct ahd_softc * ahd,struct pci_attach_args * pa)1093 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa)
1094 {
1095
1096 ahd->chip = AHD_AIC7901;
1097 ahd->features = AHD_AIC7901_FE;
1098 return (ahd_aic790X_setup(ahd, pa));
1099 }
1100
1101 static int
ahd_aic7901A_setup(struct ahd_softc * ahd,struct pci_attach_args * pa)1102 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa)
1103 {
1104
1105 ahd->chip = AHD_AIC7901A;
1106 ahd->features = AHD_AIC7901A_FE;
1107 return (ahd_aic790X_setup(ahd, pa));
1108 }
1109
1110 static int
ahd_aic7902_setup(struct ahd_softc * ahd,struct pci_attach_args * pa)1111 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa)
1112 {
1113
1114 ahd->chip = AHD_AIC7902;
1115 ahd->features = AHD_AIC7902_FE;
1116 return (ahd_aic790X_setup(ahd, pa));
1117 }
1118
1119 static int
ahd_aic790X_setup(struct ahd_softc * ahd,struct pci_attach_args * pa)1120 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa)
1121 {
1122 u_int rev;
1123
1124 rev = PCI_REVISION(pa->pa_class);
1125 #ifdef AHD_DEBUG
1126 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev);
1127 #endif
1128 if (rev < ID_AIC7902_PCI_REV_A4) {
1129 aprint_error("%s: Unable to attach to "
1130 "unsupported chip revision %d\n", ahd_name(ahd), rev);
1131 pci_conf_write(pa->pa_pc, pa->pa_tag,
1132 PCI_COMMAND_STATUS_REG, 0);
1133 return (ENXIO);
1134 }
1135
1136 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A';
1137 if (rev < ID_AIC7902_PCI_REV_B0) {
1138 /*
1139 * Enable A series workarounds.
1140 */
1141 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
1142 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
1143 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
1144 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
1145 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
1146 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
1147 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
1148 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
1149 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
1150 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
1151 | AHD_FAINT_LED_BUG;
1152
1153
1154 /*
1155 * IO Cell parameter setup.
1156 */
1157 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
1158
1159 if ((ahd->flags & AHD_HP_BOARD) == 0)
1160 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
1161 } else {
1162 u_int devconfig1;
1163
1164 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
1165 | AHD_NEW_DFCNTRL_OPTS;
1166 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
1167
1168 /*
1169 * Some issues have been resolved in the 7901B.
1170 */
1171 if ((ahd->features & AHD_MULTI_FUNC) != 0)
1172 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG;
1173
1174 /*
1175 * IO Cell parameter setup.
1176 */
1177 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
1178 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
1179 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
1180
1181 /*
1182 * Set the PREQDIS bit for H2B which disables some workaround
1183 * that doesn't work on regular PCI busses.
1184 * XXX - Find out exactly what this does from the hardware
1185 * folks!
1186 */
1187 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1);
1188 pci_conf_write(pa->pa_pc, pa->pa_tag,
1189 DEVCONFIG1, devconfig1|PREQDIS);
1190 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1);
1191 }
1192
1193 return (0);
1194 }
1195