1 /* $NetBSD: if_alc.c,v 1.21 2016/06/10 13:27:14 ozaki-r Exp $ */
2 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */
3 /*-
4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */
31
32 #ifdef _KERNEL_OPT
33 #include "vlan.h"
34 #endif
35
36 #include <sys/param.h>
37 #include <sys/proc.h>
38 #include <sys/endian.h>
39 #include <sys/systm.h>
40 #include <sys/types.h>
41 #include <sys/sockio.h>
42 #include <sys/mbuf.h>
43 #include <sys/queue.h>
44 #include <sys/kernel.h>
45 #include <sys/device.h>
46 #include <sys/callout.h>
47 #include <sys/socket.h>
48 #include <sys/module.h>
49
50 #include <sys/bus.h>
51
52 #include <net/if.h>
53 #include <net/if_dl.h>
54 #include <net/if_llc.h>
55 #include <net/if_media.h>
56 #include <net/if_ether.h>
57
58 #include <net/bpf.h>
59
60 #ifdef INET
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in_var.h>
64 #include <netinet/ip.h>
65 #endif
66
67 #include <net/if_types.h>
68 #include <net/if_vlanvar.h>
69
70 #include <net/bpf.h>
71
72 #include <dev/mii/mii.h>
73 #include <dev/mii/miivar.h>
74
75 #include <dev/pci/pcireg.h>
76 #include <dev/pci/pcivar.h>
77 #include <dev/pci/pcidevs.h>
78
79 #include <dev/pci/if_alcreg.h>
80
81 /*
82 * Devices supported by this driver.
83 */
84 static struct alc_ident alc_ident_table[] = {
85 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024,
86 "Atheros AR8131 PCIe Gigabit Ethernet" },
87 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024,
88 "Atheros AR8132 PCIe Fast Ethernet" },
89 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024,
90 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" },
91 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024,
92 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" },
93 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024,
94 "Atheros AR8152 v1.1 PCIe Fast Ethernet" },
95 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024,
96 "Atheros AR8152 v2.0 PCIe Fast Ethernet" },
97 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161, 9 * 1024,
98 "Atheros AR8161 PCIe Gigabit Ethernet" },
99 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162, 9 * 1024,
100 "Atheros AR8162 PCIe Fast Ethernet" },
101 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171, 9 * 1024,
102 "Atheros AR8171 PCIe Gigabit Ethernet" },
103 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172, 9 * 1024,
104 "Atheros AR8172 PCIe Fast Ethernet" },
105 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200, 9 * 1024,
106 "Killer E2200 Gigabit Ethernet" },
107 { 0, 0, 0, NULL },
108 };
109
110 static int alc_match(device_t, cfdata_t, void *);
111 static void alc_attach(device_t, device_t, void *);
112 static int alc_detach(device_t, int);
113
114 static int alc_init(struct ifnet *);
115 static int alc_init_backend(struct ifnet *, bool);
116 static void alc_start(struct ifnet *);
117 static int alc_ioctl(struct ifnet *, u_long, void *);
118 static void alc_watchdog(struct ifnet *);
119 static int alc_mediachange(struct ifnet *);
120 static void alc_mediastatus(struct ifnet *, struct ifmediareq *);
121
122 static void alc_aspm(struct alc_softc *, int, int);
123 static void alc_aspm_813x(struct alc_softc *, int);
124 static void alc_aspm_816x(struct alc_softc *, int);
125 static void alc_disable_l0s_l1(struct alc_softc *);
126 static int alc_dma_alloc(struct alc_softc *);
127 static void alc_dma_free(struct alc_softc *);
128 static void alc_dsp_fixup(struct alc_softc *, int);
129 static int alc_encap(struct alc_softc *, struct mbuf **);
130 static struct alc_ident *
131 alc_find_ident(struct pci_attach_args *);
132 static void alc_get_macaddr(struct alc_softc *);
133 static void alc_get_macaddr_813x(struct alc_softc *);
134 static void alc_get_macaddr_816x(struct alc_softc *);
135 static void alc_get_macaddr_par(struct alc_softc *);
136 static void alc_init_cmb(struct alc_softc *);
137 static void alc_init_rr_ring(struct alc_softc *);
138 static int alc_init_rx_ring(struct alc_softc *, bool);
139 static void alc_init_smb(struct alc_softc *);
140 static void alc_init_tx_ring(struct alc_softc *);
141 static int alc_intr(void *);
142 static void alc_mac_config(struct alc_softc *);
143 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int);
144 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int);
145 static void alc_mii_writereg_813x(struct alc_softc *, int, int, int);
146 static void alc_mii_writereg_816x(struct alc_softc *, int, int, int);
147 static int alc_miibus_readreg(device_t, int, int);
148 static void alc_miibus_statchg(struct ifnet *);
149 static void alc_miibus_writereg(device_t, int, int, int);
150 static uint32_t alc_miidbg_readreg(struct alc_softc *, int);
151 static void alc_miidbg_writereg(struct alc_softc *, int, int);
152 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int);
153 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int);
154 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool);
155 static void alc_phy_down(struct alc_softc *);
156 static void alc_phy_reset(struct alc_softc *);
157 static void alc_phy_reset_813x(struct alc_softc *);
158 static void alc_phy_reset_816x(struct alc_softc *);
159 static void alc_reset(struct alc_softc *);
160 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
161 static int alc_rxintr(struct alc_softc *);
162 static void alc_iff(struct alc_softc *);
163 static void alc_rxvlan(struct alc_softc *);
164 static void alc_start_queue(struct alc_softc *);
165 static void alc_stats_clear(struct alc_softc *);
166 static void alc_stats_update(struct alc_softc *);
167 static void alc_stop(struct ifnet *, int);
168 static void alc_stop_mac(struct alc_softc *);
169 static void alc_stop_queue(struct alc_softc *);
170 static void alc_tick(void *);
171 static void alc_txeof(struct alc_softc *);
172
173 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 };
174
175 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc),
176 alc_match, alc_attach, alc_detach, NULL);
177
178 int alcdebug = 0;
179 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0)
180
181 #define ETHER_ALIGN 2
182 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4)
183
184 static int
alc_miibus_readreg(device_t dev,int phy,int reg)185 alc_miibus_readreg(device_t dev, int phy, int reg)
186 {
187 struct alc_softc *sc = device_private(dev);
188 int v;
189
190 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
191 v = alc_mii_readreg_816x(sc, phy, reg);
192 else
193 v = alc_mii_readreg_813x(sc, phy, reg);
194 return (v);
195 }
196
197 static uint32_t
alc_mii_readreg_813x(struct alc_softc * sc,int phy,int reg)198 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg)
199 {
200 uint32_t v;
201 int i;
202
203 if (phy != sc->alc_phyaddr)
204 return (0);
205
206 /*
207 * For AR8132 fast ethernet controller, do not report 1000baseT
208 * capability to mii(4). Even though AR8132 uses the same
209 * model/revision number of F1 gigabit PHY, the PHY has no
210 * ability to establish 1000baseT link.
211 */
212 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 &&
213 reg == MII_EXTSR)
214 return 0;
215
216 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
217 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
218 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
219 DELAY(5);
220 v = CSR_READ_4(sc, ALC_MDIO);
221 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
222 break;
223 }
224
225 if (i == 0) {
226 printf("%s: phy read timeout: phy %d, reg %d\n",
227 device_xname(sc->sc_dev), phy, reg);
228 return (0);
229 }
230
231 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
232 }
233
234 static uint32_t
alc_mii_readreg_816x(struct alc_softc * sc,int phy,int reg)235 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg)
236 {
237 uint32_t clk, v;
238 int i;
239
240 if (phy != sc->alc_phyaddr)
241 return (0);
242
243 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
244 clk = MDIO_CLK_25_128;
245 else
246 clk = MDIO_CLK_25_4;
247 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
248 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));
249 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
250 DELAY(5);
251 v = CSR_READ_4(sc, ALC_MDIO);
252 if ((v & MDIO_OP_BUSY) == 0)
253 break;
254 }
255
256 if (i == 0) {
257 printf("%s: phy read timeout: phy %d, reg %d\n",
258 device_xname(sc->sc_dev), phy, reg);
259 return (0);
260 }
261
262 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
263 }
264
265 static void
alc_miibus_writereg(device_t dev,int phy,int reg,int val)266 alc_miibus_writereg(device_t dev, int phy, int reg, int val)
267 {
268 struct alc_softc *sc = device_private(dev);
269
270 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
271 alc_mii_writereg_816x(sc, phy, reg, val);
272 else
273 alc_mii_writereg_813x(sc, phy, reg, val);
274
275 return;
276 }
277
278 static void
alc_mii_writereg_813x(struct alc_softc * sc,int phy,int reg,int val)279 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val)
280 {
281 uint32_t v;
282 int i;
283
284 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
285 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
286 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
287 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
288 DELAY(5);
289 v = CSR_READ_4(sc, ALC_MDIO);
290 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
291 break;
292 }
293
294 if (i == 0)
295 printf("%s: phy write timeout: phy %d, reg %d\n",
296 device_xname(sc->sc_dev), phy, reg);
297
298 return;
299 }
300
301 static void
alc_mii_writereg_816x(struct alc_softc * sc,int phy,int reg,int val)302 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val)
303 {
304 uint32_t clk, v;
305 int i;
306
307 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
308 clk = MDIO_CLK_25_128;
309 else
310 clk = MDIO_CLK_25_4;
311 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
312 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) |
313 MDIO_SUP_PREAMBLE | clk);
314 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
315 DELAY(5);
316 v = CSR_READ_4(sc, ALC_MDIO);
317 if ((v & MDIO_OP_BUSY) == 0)
318 break;
319 }
320
321 if (i == 0)
322 printf("%s: phy write timeout: phy %d, reg %d\n",
323 device_xname(sc->sc_dev), phy, reg);
324
325 return;
326 }
327
328 static void
alc_miibus_statchg(struct ifnet * ifp)329 alc_miibus_statchg(struct ifnet *ifp)
330 {
331 struct alc_softc *sc = ifp->if_softc;
332 struct mii_data *mii = &sc->sc_miibus;
333 uint32_t reg;
334
335 if ((ifp->if_flags & IFF_RUNNING) == 0)
336 return;
337
338 sc->alc_flags &= ~ALC_FLAG_LINK;
339 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
340 (IFM_ACTIVE | IFM_AVALID)) {
341 switch (IFM_SUBTYPE(mii->mii_media_active)) {
342 case IFM_10_T:
343 case IFM_100_TX:
344 sc->alc_flags |= ALC_FLAG_LINK;
345 break;
346 case IFM_1000_T:
347 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
348 sc->alc_flags |= ALC_FLAG_LINK;
349 break;
350 default:
351 break;
352 }
353 }
354 /* Stop Rx/Tx MACs. */
355 alc_stop_mac(sc);
356
357 /* Program MACs with resolved speed/duplex/flow-control. */
358 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
359 alc_start_queue(sc);
360 alc_mac_config(sc);
361 /* Re-enable Tx/Rx MACs. */
362 reg = CSR_READ_4(sc, ALC_MAC_CFG);
363 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
364 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
365 }
366 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active));
367 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active));
368 }
369
370 static uint32_t
alc_miidbg_readreg(struct alc_softc * sc,int reg)371 alc_miidbg_readreg(struct alc_softc *sc, int reg)
372 {
373
374 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
375 reg);
376 return (alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr,
377 ALC_MII_DBG_DATA));
378 }
379
380 static void
alc_miidbg_writereg(struct alc_softc * sc,int reg,int val)381 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val)
382 {
383
384 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
385 reg);
386 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val);
387
388 return;
389 }
390
391 static uint32_t
alc_miiext_readreg(struct alc_softc * sc,int devaddr,int reg)392 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg)
393 {
394 uint32_t clk, v;
395 int i;
396
397 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
398 EXT_MDIO_DEVADDR(devaddr));
399 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
400 clk = MDIO_CLK_25_128;
401 else
402 clk = MDIO_CLK_25_4;
403 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
404 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);
405 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
406 DELAY(5);
407 v = CSR_READ_4(sc, ALC_MDIO);
408 if ((v & MDIO_OP_BUSY) == 0)
409 break;
410 }
411
412 if (i == 0) {
413 printf("%s: phy ext read timeout: %d\n",
414 device_xname(sc->sc_dev), reg);
415 return (0);
416 }
417
418 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
419 }
420
421 static uint32_t
alc_miiext_writereg(struct alc_softc * sc,int devaddr,int reg,int val)422 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val)
423 {
424 uint32_t clk, v;
425 int i;
426
427 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
428 EXT_MDIO_DEVADDR(devaddr));
429 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
430 clk = MDIO_CLK_25_128;
431 else
432 clk = MDIO_CLK_25_4;
433 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
434 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) |
435 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);
436 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
437 DELAY(5);
438 v = CSR_READ_4(sc, ALC_MDIO);
439 if ((v & MDIO_OP_BUSY) == 0)
440 break;
441 }
442
443 if (i == 0) {
444 printf("%s: phy ext write timeout: reg %d\n",
445 device_xname(sc->sc_dev), reg);
446 return (0);
447 }
448
449 return (0);
450 }
451
452 static void
alc_dsp_fixup(struct alc_softc * sc,int media)453 alc_dsp_fixup(struct alc_softc *sc, int media)
454 {
455 uint16_t agc, len, val;
456
457 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
458 return;
459 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0)
460 return;
461
462 /*
463 * Vendor PHY magic.
464 * 1000BT/AZ, wrong cable length
465 */
466 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
467 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6);
468 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) &
469 EXT_CLDCTL6_CAB_LEN_MASK;
470 /* XXX: used to be (alc >> shift) & mask which is 0 */
471 agc = alc_miidbg_readreg(sc, MII_DBG_AGC) & DBG_AGC_2_VGA_MASK;
472 agc >>= DBG_AGC_2_VGA_SHIFT;
473 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G &&
474 agc > DBG_AGC_LONG1G_LIMT) ||
475 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT &&
476 agc > DBG_AGC_LONG1G_LIMT)) {
477 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
478 DBG_AZ_ANADECT_LONG);
479 val = alc_miiext_readreg(sc, MII_EXT_ANEG,
480 MII_EXT_ANEG_AFE);
481 val |= ANEG_AFEE_10BT_100M_TH;
482 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
483 val);
484 } else {
485 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
486 DBG_AZ_ANADECT_DEFAULT);
487 val = alc_miiext_readreg(sc, MII_EXT_ANEG,
488 MII_EXT_ANEG_AFE);
489 val &= ~ANEG_AFEE_10BT_100M_TH;
490 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
491 val);
492 }
493 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
494 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
495 if (media == IFM_1000_T) {
496 /*
497 * Giga link threshold, raise the tolerance of
498 * noise 50%.
499 */
500 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
501 val &= ~DBG_MSE20DB_TH_MASK;
502 val |= (DBG_MSE20DB_TH_HI <<
503 DBG_MSE20DB_TH_SHIFT);
504 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
505 } else if (media == IFM_100_TX)
506 alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
507 DBG_MSE16DB_UP);
508 }
509 } else {
510 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE);
511 val &= ~ANEG_AFEE_10BT_100M_TH;
512 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val);
513 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
514 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
515 alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
516 DBG_MSE16DB_DOWN);
517 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
518 val &= ~DBG_MSE20DB_TH_MASK;
519 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT);
520 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
521 }
522 }
523 }
524
525 static void
alc_mediastatus(struct ifnet * ifp,struct ifmediareq * ifmr)526 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
527 {
528 struct alc_softc *sc = ifp->if_softc;
529 struct mii_data *mii = &sc->sc_miibus;
530
531 if ((ifp->if_flags & IFF_UP) == 0)
532 return;
533
534 mii_pollstat(mii);
535 ifmr->ifm_status = mii->mii_media_status;
536 ifmr->ifm_active = mii->mii_media_active;
537 }
538
539 static int
alc_mediachange(struct ifnet * ifp)540 alc_mediachange(struct ifnet *ifp)
541 {
542 struct alc_softc *sc = ifp->if_softc;
543 struct mii_data *mii = &sc->sc_miibus;
544 int error;
545
546 if (mii->mii_instance != 0) {
547 struct mii_softc *miisc;
548
549 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
550 mii_phy_reset(miisc);
551 }
552 error = mii_mediachg(mii);
553
554 return (error);
555 }
556
557 static struct alc_ident *
alc_find_ident(struct pci_attach_args * pa)558 alc_find_ident(struct pci_attach_args *pa)
559 {
560 struct alc_ident *ident;
561 uint16_t vendor, devid;
562
563 vendor = PCI_VENDOR(pa->pa_id);
564 devid = PCI_PRODUCT(pa->pa_id);
565 for (ident = alc_ident_table; ident->name != NULL; ident++) {
566 if (vendor == ident->vendorid && devid == ident->deviceid)
567 return (ident);
568 }
569
570 return (NULL);
571 }
572
573 static int
alc_match(device_t dev,cfdata_t match,void * aux)574 alc_match(device_t dev, cfdata_t match, void *aux)
575 {
576 struct pci_attach_args *pa = aux;
577
578 return alc_find_ident(pa) != NULL;
579 }
580
581 static void
alc_get_macaddr(struct alc_softc * sc)582 alc_get_macaddr(struct alc_softc *sc)
583 {
584
585 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
586 alc_get_macaddr_816x(sc);
587 else
588 alc_get_macaddr_813x(sc);
589 }
590
591 static void
alc_get_macaddr_813x(struct alc_softc * sc)592 alc_get_macaddr_813x(struct alc_softc *sc)
593 {
594 uint32_t opt;
595 uint16_t val;
596 int eeprom, i;
597
598 eeprom = 0;
599 opt = CSR_READ_4(sc, ALC_OPT_CFG);
600 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
601 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
602 /*
603 * EEPROM found, let TWSI reload EEPROM configuration.
604 * This will set ethernet address of controller.
605 */
606 eeprom++;
607 switch (sc->alc_ident->deviceid) {
608 case PCI_PRODUCT_ATTANSIC_AR8131:
609 case PCI_PRODUCT_ATTANSIC_AR8132:
610 if ((opt & OPT_CFG_CLK_ENB) == 0) {
611 opt |= OPT_CFG_CLK_ENB;
612 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
613 CSR_READ_4(sc, ALC_OPT_CFG);
614 DELAY(1000);
615 }
616 break;
617 case PCI_PRODUCT_ATTANSIC_AR8151:
618 case PCI_PRODUCT_ATTANSIC_AR8151_V2:
619 case PCI_PRODUCT_ATTANSIC_AR8152_B:
620 case PCI_PRODUCT_ATTANSIC_AR8152_B2:
621 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
622 ALC_MII_DBG_ADDR, 0x00);
623 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr,
624 ALC_MII_DBG_DATA);
625 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
626 ALC_MII_DBG_DATA, val & 0xFF7F);
627 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
628 ALC_MII_DBG_ADDR, 0x3B);
629 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr,
630 ALC_MII_DBG_DATA);
631 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
632 ALC_MII_DBG_DATA, val | 0x0008);
633 DELAY(20);
634 break;
635 }
636
637 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
638 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
639 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
640 CSR_READ_4(sc, ALC_WOL_CFG);
641
642 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
643 TWSI_CFG_SW_LD_START);
644 for (i = 100; i > 0; i--) {
645 DELAY(1000);
646 if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
647 TWSI_CFG_SW_LD_START) == 0)
648 break;
649 }
650 if (i == 0)
651 printf("%s: reloading EEPROM timeout!\n",
652 device_xname(sc->sc_dev));
653 } else {
654 if (alcdebug)
655 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev));
656 }
657 if (eeprom != 0) {
658 switch (sc->alc_ident->deviceid) {
659 case PCI_PRODUCT_ATTANSIC_AR8131:
660 case PCI_PRODUCT_ATTANSIC_AR8132:
661 if ((opt & OPT_CFG_CLK_ENB) != 0) {
662 opt &= ~OPT_CFG_CLK_ENB;
663 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
664 CSR_READ_4(sc, ALC_OPT_CFG);
665 DELAY(1000);
666 }
667 break;
668 case PCI_PRODUCT_ATTANSIC_AR8151:
669 case PCI_PRODUCT_ATTANSIC_AR8151_V2:
670 case PCI_PRODUCT_ATTANSIC_AR8152_B:
671 case PCI_PRODUCT_ATTANSIC_AR8152_B2:
672 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
673 ALC_MII_DBG_ADDR, 0x00);
674 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr,
675 ALC_MII_DBG_DATA);
676 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
677 ALC_MII_DBG_DATA, val | 0x0080);
678 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
679 ALC_MII_DBG_ADDR, 0x3B);
680 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr,
681 ALC_MII_DBG_DATA);
682 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
683 ALC_MII_DBG_DATA, val & 0xFFF7);
684 DELAY(20);
685 break;
686 }
687 }
688
689 alc_get_macaddr_par(sc);
690 }
691
692 static void
alc_get_macaddr_816x(struct alc_softc * sc)693 alc_get_macaddr_816x(struct alc_softc *sc)
694 {
695 uint32_t reg;
696 int i, reloaded;
697
698 reloaded = 0;
699 /* Try to reload station address via TWSI. */
700 for (i = 100; i > 0; i--) {
701 reg = CSR_READ_4(sc, ALC_SLD);
702 if ((reg & (SLD_PROGRESS | SLD_START)) == 0)
703 break;
704 DELAY(1000);
705 }
706 if (i != 0) {
707 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);
708 for (i = 100; i > 0; i--) {
709 DELAY(1000);
710 reg = CSR_READ_4(sc, ALC_SLD);
711 if ((reg & SLD_START) == 0)
712 break;
713 }
714 if (i != 0)
715 reloaded++;
716 else if (alcdebug)
717 printf("%s: reloading station address via TWSI timed out!\n",
718 device_xname(sc->sc_dev));
719 }
720
721 /* Try to reload station address from EEPROM or FLASH. */
722 if (reloaded == 0) {
723 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
724 if ((reg & (EEPROM_LD_EEPROM_EXIST |
725 EEPROM_LD_FLASH_EXIST)) != 0) {
726 for (i = 100; i > 0; i--) {
727 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
728 if ((reg & (EEPROM_LD_PROGRESS |
729 EEPROM_LD_START)) == 0)
730 break;
731 DELAY(1000);
732 }
733 if (i != 0) {
734 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |
735 EEPROM_LD_START);
736 for (i = 100; i > 0; i--) {
737 DELAY(1000);
738 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
739 if ((reg & EEPROM_LD_START) == 0)
740 break;
741 }
742 } else if (alcdebug)
743 printf("%s: reloading EEPROM/FLASH timed out!\n",
744 device_xname(sc->sc_dev));
745 }
746 }
747
748 alc_get_macaddr_par(sc);
749 }
750
751
752 static void
alc_get_macaddr_par(struct alc_softc * sc)753 alc_get_macaddr_par(struct alc_softc *sc)
754 {
755 uint32_t ea[2];
756
757 ea[0] = CSR_READ_4(sc, ALC_PAR0);
758 ea[1] = CSR_READ_4(sc, ALC_PAR1);
759 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
760 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
761 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
762 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
763 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
764 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
765 }
766
767 static void
alc_disable_l0s_l1(struct alc_softc * sc)768 alc_disable_l0s_l1(struct alc_softc *sc)
769 {
770 uint32_t pmcfg;
771
772 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
773 /* Another magic from vendor. */
774 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
775 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
776 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
777 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1);
778 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB |
779 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB;
780 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
781 }
782 }
783
784 static void
alc_phy_reset(struct alc_softc * sc)785 alc_phy_reset(struct alc_softc *sc)
786 {
787
788 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
789 alc_phy_reset_816x(sc);
790 else
791 alc_phy_reset_813x(sc);
792 }
793
794 static void
alc_phy_reset_813x(struct alc_softc * sc)795 alc_phy_reset_813x(struct alc_softc *sc)
796 {
797 uint16_t data;
798
799 /* Reset magic from Linux. */
800 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET);
801 CSR_READ_2(sc, ALC_GPHY_CFG);
802 DELAY(10 * 1000);
803
804 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
805 GPHY_CFG_SEL_ANA_RESET);
806 CSR_READ_2(sc, ALC_GPHY_CFG);
807 DELAY(10 * 1000);
808
809 /* DSP fixup, Vendor magic. */
810 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) {
811 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
812 ALC_MII_DBG_ADDR, 0x000A);
813 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr,
814 ALC_MII_DBG_DATA);
815 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
816 ALC_MII_DBG_DATA, data & 0xDFFF);
817 }
818 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 ||
819 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 ||
820 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B ||
821 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) {
822 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
823 ALC_MII_DBG_ADDR, 0x003B);
824 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr,
825 ALC_MII_DBG_DATA);
826 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
827 ALC_MII_DBG_DATA, data & 0xFFF7);
828 DELAY(20 * 1000);
829 }
830 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) {
831 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
832 ALC_MII_DBG_ADDR, 0x0029);
833 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
834 ALC_MII_DBG_DATA, 0x929D);
835 }
836 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 ||
837 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 ||
838 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 ||
839 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) {
840 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
841 ALC_MII_DBG_ADDR, 0x0029);
842 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
843 ALC_MII_DBG_DATA, 0xB6DD);
844 }
845
846 /* Load DSP codes, vendor magic. */
847 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
848 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
849 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
850 ALC_MII_DBG_ADDR, MII_ANA_CFG18);
851 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
852 ALC_MII_DBG_DATA, data);
853
854 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) |
855 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
856 ANA_SERDES_EN_LCKDT;
857 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
858 ALC_MII_DBG_ADDR, MII_ANA_CFG5);
859 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
860 ALC_MII_DBG_DATA, data);
861
862 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) &
863 ANA_LONG_CABLE_TH_100_MASK) |
864 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) &
865 ANA_SHORT_CABLE_TH_100_SHIFT) |
866 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW;
867 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
868 ALC_MII_DBG_ADDR, MII_ANA_CFG54);
869 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
870 ALC_MII_DBG_DATA, data);
871
872 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) |
873 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) |
874 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) |
875 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK);
876 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
877 ALC_MII_DBG_ADDR, MII_ANA_CFG4);
878 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
879 ALC_MII_DBG_DATA, data);
880
881 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) |
882 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB |
883 ANA_OEN_125M;
884 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
885 ALC_MII_DBG_ADDR, MII_ANA_CFG0);
886 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
887 ALC_MII_DBG_DATA, data);
888 DELAY(1000);
889
890 /* Disable hibernation. */
891 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
892 0x0029);
893 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr,
894 ALC_MII_DBG_DATA);
895 data &= ~0x8000;
896 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
897 data);
898
899 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
900 0x000B);
901 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr,
902 ALC_MII_DBG_DATA);
903 data &= ~0x8000;
904 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
905 data);
906 }
907
908 static void
alc_phy_reset_816x(struct alc_softc * sc)909 alc_phy_reset_816x(struct alc_softc *sc)
910 {
911 uint32_t val;
912
913 val = CSR_READ_4(sc, ALC_GPHY_CFG);
914 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
915 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON |
916 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB);
917 val |= GPHY_CFG_SEL_ANA_RESET;
918 #ifdef notyet
919 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET;
920 #else
921 /* Disable PHY hibernation. */
922 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN);
923 #endif
924 CSR_WRITE_4(sc, ALC_GPHY_CFG, val);
925 DELAY(10);
926 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET);
927 DELAY(800);
928
929 /* Vendor PHY magic. */
930 #ifdef notyet
931 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT);
932 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT);
933 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS,
934 EXT_VDRVBIAS_DEFAULT);
935 #else
936 /* Disable PHY hibernation. */
937 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS,
938 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB);
939 alc_miidbg_writereg(sc, MII_DBG_HIBNEG,
940 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE));
941 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT);
942 #endif
943
944 /* XXX Disable EEE. */
945 val = CSR_READ_4(sc, ALC_LPI_CTL);
946 val &= ~LPI_CTL_ENB;
947 CSR_WRITE_4(sc, ALC_LPI_CTL, val);
948 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0);
949
950 /* PHY power saving. */
951 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT);
952 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT);
953 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT);
954 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT);
955 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
956 val &= ~DBG_GREENCFG2_GATE_DFSE_EN;
957 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
958
959 /* RTL8139C, 120m issue. */
960 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78,
961 ANEG_NLP78_120M_DEFAULT);
962 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10,
963 ANEG_S3DIG10_DEFAULT);
964
965 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) {
966 /* Turn off half amplitude. */
967 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3);
968 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT;
969 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val);
970 /* Turn off Green feature. */
971 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
972 val |= DBG_GREENCFG2_BP_GREEN;
973 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
974 /* Turn off half bias. */
975 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5);
976 val |= EXT_CLDCTL5_BP_VD_HLFBIAS;
977 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val);
978 }
979 }
980
981 static void
alc_phy_down(struct alc_softc * sc)982 alc_phy_down(struct alc_softc *sc)
983 {
984 uint32_t gphy;
985
986 switch (sc->alc_ident->deviceid) {
987 case PCI_PRODUCT_ATTANSIC_AR8161:
988 case PCI_PRODUCT_ATTANSIC_E2200:
989 case PCI_PRODUCT_ATTANSIC_AR8162:
990 case PCI_PRODUCT_ATTANSIC_AR8171:
991 case PCI_PRODUCT_ATTANSIC_AR8172:
992 gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
993 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
994 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON);
995 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
996 GPHY_CFG_SEL_ANA_RESET;
997 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW;
998 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
999 break;
1000 case PCI_PRODUCT_ATTANSIC_AR8151:
1001 case PCI_PRODUCT_ATTANSIC_AR8151_V2:
1002 case PCI_PRODUCT_ATTANSIC_AR8152_B:
1003 case PCI_PRODUCT_ATTANSIC_AR8152_B2:
1004 /*
1005 * GPHY power down caused more problems on AR8151 v2.0.
1006 * When driver is reloaded after GPHY power down,
1007 * accesses to PHY/MAC registers hung the system. Only
1008 * cold boot recovered from it. I'm not sure whether
1009 * AR8151 v1.0 also requires this one though. I don't
1010 * have AR8151 v1.0 controller in hand.
1011 * The only option left is to isolate the PHY and
1012 * initiates power down the PHY which in turn saves
1013 * more power when driver is unloaded.
1014 */
1015 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr,
1016 MII_BMCR, BMCR_ISO | BMCR_PDOWN);
1017 break;
1018 default:
1019 /* Force PHY down. */
1020 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
1021 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ |
1022 GPHY_CFG_PWDOWN_HW);
1023 DELAY(1000);
1024 break;
1025 }
1026 }
1027
1028 static void
alc_aspm(struct alc_softc * sc,int init,int media)1029 alc_aspm(struct alc_softc *sc, int init, int media)
1030 {
1031
1032 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
1033 alc_aspm_816x(sc, init);
1034 else
1035 alc_aspm_813x(sc, media);
1036 }
1037
1038 static void
alc_aspm_813x(struct alc_softc * sc,int media)1039 alc_aspm_813x(struct alc_softc *sc, int media)
1040 {
1041 uint32_t pmcfg;
1042 uint16_t linkcfg;
1043
1044 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1045 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
1046 (ALC_FLAG_APS | ALC_FLAG_PCIE))
1047 linkcfg = CSR_READ_2(sc, sc->alc_expcap +
1048 PCIE_LCSR);
1049 else
1050 linkcfg = 0;
1051 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
1052 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
1053 pmcfg |= PM_CFG_MAC_ASPM_CHK;
1054 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT);
1055 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
1056
1057 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1058 /* Disable extended sync except AR8152 B v1.0 */
1059 linkcfg &= ~0x80;
1060 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B &&
1061 sc->alc_rev == ATHEROS_AR8152_B_V10)
1062 linkcfg |= 0x80;
1063 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR,
1064 linkcfg);
1065 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
1066 PM_CFG_HOTRST);
1067 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
1068 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1069 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
1070 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
1071 PM_CFG_PM_REQ_TIMER_SHIFT);
1072 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
1073 }
1074
1075 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1076 if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
1077 pmcfg |= PM_CFG_ASPM_L0S_ENB;
1078 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1079 pmcfg |= PM_CFG_ASPM_L1_ENB;
1080 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1081 if (sc->alc_ident->deviceid ==
1082 PCI_PRODUCT_ATTANSIC_AR8152_B)
1083 pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
1084 pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
1085 PM_CFG_SERDES_PLL_L1_ENB |
1086 PM_CFG_SERDES_BUDS_RX_L1_ENB);
1087 pmcfg |= PM_CFG_CLK_SWH_L1;
1088 if (media == IFM_100_TX || media == IFM_1000_T) {
1089 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
1090 switch (sc->alc_ident->deviceid) {
1091 case PCI_PRODUCT_ATTANSIC_AR8152_B:
1092 pmcfg |= (7 <<
1093 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1094 break;
1095 case PCI_PRODUCT_ATTANSIC_AR8152_B2:
1096 case PCI_PRODUCT_ATTANSIC_AR8151_V2:
1097 pmcfg |= (4 <<
1098 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1099 break;
1100 default:
1101 pmcfg |= (15 <<
1102 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1103 break;
1104 }
1105 }
1106 } else {
1107 pmcfg |= PM_CFG_SERDES_L1_ENB |
1108 PM_CFG_SERDES_PLL_L1_ENB |
1109 PM_CFG_SERDES_BUDS_RX_L1_ENB;
1110 pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
1111 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
1112 }
1113 } else {
1114 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
1115 PM_CFG_SERDES_PLL_L1_ENB);
1116 pmcfg |= PM_CFG_CLK_SWH_L1;
1117 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1118 pmcfg |= PM_CFG_ASPM_L1_ENB;
1119 }
1120 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1121 }
1122
1123 static void
alc_aspm_816x(struct alc_softc * sc,int init)1124 alc_aspm_816x(struct alc_softc *sc, int init)
1125 {
1126 uint32_t pmcfg;
1127
1128 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1129 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK;
1130 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT;
1131 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
1132 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT;
1133 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK;
1134 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT;
1135 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV;
1136 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S |
1137 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB |
1138 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
1139 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB |
1140 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST);
1141 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
1142 (sc->alc_rev & 0x01) != 0)
1143 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB;
1144 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1145 /* Link up, enable both L0s, L1s. */
1146 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
1147 PM_CFG_MAC_ASPM_CHK;
1148 } else {
1149 if (init != 0)
1150 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
1151 PM_CFG_MAC_ASPM_CHK;
1152 else if ((sc->sc_ec.ec_if.if_flags & IFF_RUNNING) != 0)
1153 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK;
1154 }
1155 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1156 }
1157
1158 static void
alc_attach(device_t parent,device_t self,void * aux)1159 alc_attach(device_t parent, device_t self, void *aux)
1160 {
1161
1162 struct alc_softc *sc = device_private(self);
1163 struct pci_attach_args *pa = aux;
1164 pci_chipset_tag_t pc = pa->pa_pc;
1165 pci_intr_handle_t ih;
1166 const char *intrstr;
1167 struct ifnet *ifp;
1168 pcireg_t memtype;
1169 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
1170 uint16_t burst;
1171 int base, mii_flags, state, error = 0;
1172 uint32_t cap, ctl, val;
1173 char intrbuf[PCI_INTRSTR_LEN];
1174
1175 sc->alc_ident = alc_find_ident(pa);
1176
1177 aprint_naive("\n");
1178 aprint_normal(": %s\n", sc->alc_ident->name);
1179
1180 sc->sc_dev = self;
1181 sc->sc_dmat = pa->pa_dmat;
1182 sc->sc_pct = pa->pa_pc;
1183 sc->sc_pcitag = pa->pa_tag;
1184
1185 /*
1186 * Allocate IO memory
1187 */
1188 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR);
1189 switch (memtype) {
1190 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
1191 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M:
1192 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
1193 break;
1194 default:
1195 aprint_error_dev(self, "invalid base address register\n");
1196 break;
1197 }
1198
1199 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt,
1200 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) {
1201 aprint_error_dev(self, "could not map mem space\n");
1202 return;
1203 }
1204
1205 if (pci_intr_map(pa, &ih) != 0) {
1206 printf(": can't map interrupt\n");
1207 goto fail;
1208 }
1209
1210 /*
1211 * Allocate IRQ
1212 */
1213 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf));
1214 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc);
1215 if (sc->sc_irq_handle == NULL) {
1216 printf(": could not establish interrupt");
1217 if (intrstr != NULL)
1218 printf(" at %s", intrstr);
1219 printf("\n");
1220 goto fail;
1221 }
1222 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
1223
1224 /* Set PHY address. */
1225 sc->alc_phyaddr = ALC_PHY_ADDR;
1226
1227 /* Initialize DMA parameters. */
1228 sc->alc_dma_rd_burst = 0;
1229 sc->alc_dma_wr_burst = 0;
1230 sc->alc_rcb = DMA_CFG_RCB_64;
1231 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
1232 &base, NULL)) {
1233 sc->alc_flags |= ALC_FLAG_PCIE;
1234 sc->alc_expcap = base;
1235 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
1236 base + PCIE_DCSR) >> 16;
1237 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12;
1238 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5;
1239 if (alcdebug) {
1240 printf("%s: Read request size : %u bytes.\n",
1241 device_xname(sc->sc_dev),
1242 alc_dma_burst[sc->alc_dma_rd_burst]);
1243 printf("%s: TLP payload size : %u bytes.\n",
1244 device_xname(sc->sc_dev),
1245 alc_dma_burst[sc->alc_dma_wr_burst]);
1246 }
1247 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
1248 sc->alc_dma_rd_burst = 3;
1249 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
1250 sc->alc_dma_wr_burst = 3;
1251
1252 /* Clear data link and flow-control protocol error. */
1253 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
1254 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
1255 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
1256
1257 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1258 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
1259 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
1260 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
1261 CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
1262 PCIE_PHYMISC_FORCE_RCV_DET);
1263 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B &&
1264 sc->alc_rev == ATHEROS_AR8152_B_V10) {
1265 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
1266 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
1267 PCIE_PHYMISC2_SERDES_TH_MASK);
1268 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
1269 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
1270 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
1271 }
1272 /* Disable ASPM L0S and L1. */
1273 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
1274 base + PCIE_LCAP) >> 16;
1275 if ((cap & 0x00000c00) != 0) {
1276 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
1277 base + PCIE_LCSR) >> 16;
1278 if ((ctl & 0x08) != 0)
1279 sc->alc_rcb = DMA_CFG_RCB_128;
1280 if (alcdebug)
1281 printf("%s: RCB %u bytes\n",
1282 device_xname(sc->sc_dev),
1283 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
1284 state = ctl & 0x03;
1285 if (state & 0x01)
1286 sc->alc_flags |= ALC_FLAG_L0S;
1287 if (state & 0x02)
1288 sc->alc_flags |= ALC_FLAG_L1S;
1289 if (alcdebug)
1290 printf("%s: ASPM %s %s\n",
1291 device_xname(sc->sc_dev),
1292 aspm_state[state],
1293 state == 0 ? "disabled" : "enabled");
1294 alc_disable_l0s_l1(sc);
1295 } else {
1296 aprint_debug_dev(sc->sc_dev, "no ASPM support\n");
1297 }
1298 } else {
1299 val = CSR_READ_4(sc, ALC_PDLL_TRNS1);
1300 val &= ~PDLL_TRNS1_D3PLLOFF_ENB;
1301 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val);
1302 val = CSR_READ_4(sc, ALC_MASTER_CFG);
1303 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
1304 (sc->alc_rev & 0x01) != 0) {
1305 if ((val & MASTER_WAKEN_25M) == 0 ||
1306 (val & MASTER_CLK_SEL_DIS) == 0) {
1307 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS;
1308 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1309 }
1310 } else {
1311 if ((val & MASTER_WAKEN_25M) == 0 ||
1312 (val & MASTER_CLK_SEL_DIS) != 0) {
1313 val |= MASTER_WAKEN_25M;
1314 val &= ~MASTER_CLK_SEL_DIS;
1315 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1316 }
1317 }
1318 }
1319 alc_aspm(sc, 1, IFM_UNKNOWN);
1320 }
1321
1322 /* Reset PHY. */
1323 alc_phy_reset(sc);
1324
1325 /* Reset the ethernet controller. */
1326 alc_stop_mac(sc);
1327 alc_reset(sc);
1328
1329 /*
1330 * One odd thing is AR8132 uses the same PHY hardware(F1
1331 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
1332 * the PHY supports 1000Mbps but that's not true. The PHY
1333 * used in AR8132 can't establish gigabit link even if it
1334 * shows the same PHY model/revision number of AR8131.
1335 */
1336 switch (sc->alc_ident->deviceid) {
1337 case PCI_PRODUCT_ATTANSIC_AR8161:
1338 if (PCI_SUBSYS_ID(pci_conf_read(
1339 sc->sc_pct, sc->sc_pcitag, PCI_SUBSYS_ID_REG)) == 0x0091 &&
1340 sc->alc_rev == 0)
1341 sc->alc_flags |= ALC_FLAG_LINK_WAR;
1342 /* FALLTHROUGH */
1343 case PCI_PRODUCT_ATTANSIC_E2200:
1344 case PCI_PRODUCT_ATTANSIC_AR8171:
1345 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY;
1346 break;
1347 case PCI_PRODUCT_ATTANSIC_AR8162:
1348 case PCI_PRODUCT_ATTANSIC_AR8172:
1349 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY;
1350 break;
1351 case PCI_PRODUCT_ATTANSIC_AR8152_B:
1352 case PCI_PRODUCT_ATTANSIC_AR8152_B2:
1353 sc->alc_flags |= ALC_FLAG_APS;
1354 /* FALLTHROUGH */
1355 case PCI_PRODUCT_ATTANSIC_AR8132:
1356 sc->alc_flags |= ALC_FLAG_FASTETHER;
1357 break;
1358 case PCI_PRODUCT_ATTANSIC_AR8151:
1359 case PCI_PRODUCT_ATTANSIC_AR8151_V2:
1360 sc->alc_flags |= ALC_FLAG_APS;
1361 /* FALLTHROUGH */
1362 default:
1363 break;
1364 }
1365 sc->alc_flags |= ALC_FLAG_JUMBO;
1366
1367 /*
1368 * It seems that AR813x/AR815x has silicon bug for SMB. In
1369 * addition, Atheros said that enabling SMB wouldn't improve
1370 * performance. However I think it's bad to access lots of
1371 * registers to extract MAC statistics.
1372 */
1373 sc->alc_flags |= ALC_FLAG_SMB_BUG;
1374 /*
1375 * Don't use Tx CMB. It is known to have silicon bug.
1376 */
1377 sc->alc_flags |= ALC_FLAG_CMB_BUG;
1378 sc->alc_rev = PCI_REVISION(pa->pa_class);
1379 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
1380 MASTER_CHIP_REV_SHIFT;
1381 if (alcdebug) {
1382 printf("%s: PCI device revision : 0x%04x\n",
1383 device_xname(sc->sc_dev), sc->alc_rev);
1384 printf("%s: Chip id/revision : 0x%04x\n",
1385 device_xname(sc->sc_dev), sc->alc_chip_rev);
1386 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev),
1387 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
1388 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
1389 }
1390
1391 error = alc_dma_alloc(sc);
1392 if (error)
1393 goto fail;
1394
1395 callout_init(&sc->sc_tick_ch, 0);
1396 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc);
1397
1398 /* Load station address. */
1399 alc_get_macaddr(sc);
1400
1401 aprint_normal_dev(self, "Ethernet address %s\n",
1402 ether_sprintf(sc->alc_eaddr));
1403
1404 ifp = &sc->sc_ec.ec_if;
1405 ifp->if_softc = sc;
1406 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1407 ifp->if_init = alc_init;
1408 ifp->if_ioctl = alc_ioctl;
1409 ifp->if_start = alc_start;
1410 ifp->if_stop = alc_stop;
1411 ifp->if_watchdog = alc_watchdog;
1412 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1);
1413 IFQ_SET_READY(&ifp->if_snd);
1414 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
1415
1416 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1417
1418 #ifdef ALC_CHECKSUM
1419 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1420 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1421 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
1422 #endif
1423
1424 #if NVLAN > 0
1425 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING;
1426 #endif
1427
1428 /*
1429 * XXX
1430 * It seems enabling Tx checksum offloading makes more trouble.
1431 * Sometimes the controller does not receive any frames when
1432 * Tx checksum offloading is enabled. I'm not sure whether this
1433 * is a bug in Tx checksum offloading logic or I got broken
1434 * sample boards. To safety, don't enable Tx checksum offloading
1435 * by default but give chance to users to toggle it if they know
1436 * their controllers work without problems.
1437 * Fortunately, Tx checksum offloading for AR816x family
1438 * seems to work.
1439 */
1440 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1441 ifp->if_capenable &= ~IFCAP_CSUM_IPv4_Tx;
1442 ifp->if_capabilities &= ~ALC_CSUM_FEATURES;
1443 }
1444
1445 /* Set up MII bus. */
1446 sc->sc_miibus.mii_ifp = ifp;
1447 sc->sc_miibus.mii_readreg = alc_miibus_readreg;
1448 sc->sc_miibus.mii_writereg = alc_miibus_writereg;
1449 sc->sc_miibus.mii_statchg = alc_miibus_statchg;
1450
1451 sc->sc_ec.ec_mii = &sc->sc_miibus;
1452 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange,
1453 alc_mediastatus);
1454 mii_flags = 0;
1455 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0)
1456 mii_flags |= MIIF_DOPAUSE;
1457 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY,
1458 MII_OFFSET_ANY, mii_flags);
1459
1460 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) {
1461 printf("%s: no PHY found!\n", device_xname(sc->sc_dev));
1462 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL,
1463 0, NULL);
1464 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL);
1465 } else
1466 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO);
1467
1468 if_attach(ifp);
1469 ether_ifattach(ifp, sc->alc_eaddr);
1470
1471 if (!pmf_device_register(self, NULL, NULL))
1472 aprint_error_dev(self, "couldn't establish power handler\n");
1473 else
1474 pmf_class_network_register(self, ifp);
1475
1476 return;
1477 fail:
1478 alc_dma_free(sc);
1479 if (sc->sc_irq_handle != NULL) {
1480 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle);
1481 sc->sc_irq_handle = NULL;
1482 }
1483 if (sc->sc_mem_size) {
1484 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size);
1485 sc->sc_mem_size = 0;
1486 }
1487 }
1488
1489 static int
alc_detach(device_t self,int flags)1490 alc_detach(device_t self, int flags)
1491 {
1492 struct alc_softc *sc = device_private(self);
1493 struct ifnet *ifp = &sc->sc_ec.ec_if;
1494 int s;
1495
1496 s = splnet();
1497 alc_stop(ifp, 0);
1498 splx(s);
1499
1500 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY);
1501
1502 /* Delete all remaining media. */
1503 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY);
1504
1505 ether_ifdetach(ifp);
1506 if_detach(ifp);
1507 alc_dma_free(sc);
1508
1509 alc_phy_down(sc);
1510 if (sc->sc_irq_handle != NULL) {
1511 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle);
1512 sc->sc_irq_handle = NULL;
1513 }
1514 if (sc->sc_mem_size) {
1515 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size);
1516 sc->sc_mem_size = 0;
1517 }
1518
1519 return (0);
1520 }
1521
1522 static int
alc_dma_alloc(struct alc_softc * sc)1523 alc_dma_alloc(struct alc_softc *sc)
1524 {
1525 struct alc_txdesc *txd;
1526 struct alc_rxdesc *rxd;
1527 int nsegs, error, i;
1528
1529 /*
1530 * Create DMA stuffs for TX ring
1531 */
1532 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1,
1533 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map);
1534 if (error) {
1535 sc->alc_cdata.alc_tx_ring_map = NULL;
1536 return (ENOBUFS);
1537 }
1538
1539 /* Allocate DMA'able memory for TX ring */
1540 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ,
1541 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1,
1542 &nsegs, BUS_DMA_NOWAIT);
1543 if (error) {
1544 printf("%s: could not allocate DMA'able memory for Tx ring.\n",
1545 device_xname(sc->sc_dev));
1546 return error;
1547 }
1548
1549 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg,
1550 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring,
1551 BUS_DMA_NOWAIT);
1552 if (error)
1553 return (ENOBUFS);
1554
1555 /* Load the DMA map for Tx ring. */
1556 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map,
1557 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK);
1558 if (error) {
1559 printf("%s: could not load DMA'able memory for Tx ring.\n",
1560 device_xname(sc->sc_dev));
1561 bus_dmamem_free(sc->sc_dmat,
1562 &sc->alc_rdata.alc_tx_ring_seg, 1);
1563 return error;
1564 }
1565
1566 sc->alc_rdata.alc_tx_ring_paddr =
1567 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr;
1568
1569 /*
1570 * Create DMA stuffs for RX ring
1571 */
1572 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1,
1573 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map);
1574 if (error)
1575 return (ENOBUFS);
1576
1577 /* Allocate DMA'able memory for RX ring */
1578 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ,
1579 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1,
1580 &nsegs, BUS_DMA_NOWAIT);
1581 if (error) {
1582 printf("%s: could not allocate DMA'able memory for Rx ring.\n",
1583 device_xname(sc->sc_dev));
1584 return error;
1585 }
1586
1587 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg,
1588 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring,
1589 BUS_DMA_NOWAIT);
1590 if (error)
1591 return (ENOBUFS);
1592
1593 /* Load the DMA map for Rx ring. */
1594 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map,
1595 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK);
1596 if (error) {
1597 printf("%s: could not load DMA'able memory for Rx ring.\n",
1598 device_xname(sc->sc_dev));
1599 bus_dmamem_free(sc->sc_dmat,
1600 &sc->alc_rdata.alc_rx_ring_seg, 1);
1601 return error;
1602 }
1603
1604 sc->alc_rdata.alc_rx_ring_paddr =
1605 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr;
1606
1607 /*
1608 * Create DMA stuffs for RX return ring
1609 */
1610 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1,
1611 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map);
1612 if (error)
1613 return (ENOBUFS);
1614
1615 /* Allocate DMA'able memory for RX return ring */
1616 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ,
1617 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1,
1618 &nsegs, BUS_DMA_NOWAIT);
1619 if (error) {
1620 printf("%s: could not allocate DMA'able memory for Rx "
1621 "return ring.\n", device_xname(sc->sc_dev));
1622 return error;
1623 }
1624
1625 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg,
1626 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring,
1627 BUS_DMA_NOWAIT);
1628 if (error)
1629 return (ENOBUFS);
1630
1631 /* Load the DMA map for Rx return ring. */
1632 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map,
1633 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK);
1634 if (error) {
1635 printf("%s: could not load DMA'able memory for Rx return ring."
1636 "\n", device_xname(sc->sc_dev));
1637 bus_dmamem_free(sc->sc_dmat,
1638 &sc->alc_rdata.alc_rr_ring_seg, 1);
1639 return error;
1640 }
1641
1642 sc->alc_rdata.alc_rr_ring_paddr =
1643 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr;
1644
1645 /*
1646 * Create DMA stuffs for CMB block
1647 */
1648 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1,
1649 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT,
1650 &sc->alc_cdata.alc_cmb_map);
1651 if (error)
1652 return (ENOBUFS);
1653
1654 /* Allocate DMA'able memory for CMB block */
1655 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ,
1656 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1,
1657 &nsegs, BUS_DMA_NOWAIT);
1658 if (error) {
1659 printf("%s: could not allocate DMA'able memory for "
1660 "CMB block\n", device_xname(sc->sc_dev));
1661 return error;
1662 }
1663
1664 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg,
1665 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb,
1666 BUS_DMA_NOWAIT);
1667 if (error)
1668 return (ENOBUFS);
1669
1670 /* Load the DMA map for CMB block. */
1671 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map,
1672 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL,
1673 BUS_DMA_WAITOK);
1674 if (error) {
1675 printf("%s: could not load DMA'able memory for CMB block\n",
1676 device_xname(sc->sc_dev));
1677 bus_dmamem_free(sc->sc_dmat,
1678 &sc->alc_rdata.alc_cmb_seg, 1);
1679 return error;
1680 }
1681
1682 sc->alc_rdata.alc_cmb_paddr =
1683 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr;
1684
1685 /*
1686 * Create DMA stuffs for SMB block
1687 */
1688 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1,
1689 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT,
1690 &sc->alc_cdata.alc_smb_map);
1691 if (error)
1692 return (ENOBUFS);
1693
1694 /* Allocate DMA'able memory for SMB block */
1695 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ,
1696 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1,
1697 &nsegs, BUS_DMA_NOWAIT);
1698 if (error) {
1699 printf("%s: could not allocate DMA'able memory for "
1700 "SMB block\n", device_xname(sc->sc_dev));
1701 return error;
1702 }
1703
1704 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg,
1705 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb,
1706 BUS_DMA_NOWAIT);
1707 if (error)
1708 return (ENOBUFS);
1709
1710 /* Load the DMA map for SMB block */
1711 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map,
1712 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL,
1713 BUS_DMA_WAITOK);
1714 if (error) {
1715 printf("%s: could not load DMA'able memory for SMB block\n",
1716 device_xname(sc->sc_dev));
1717 bus_dmamem_free(sc->sc_dmat,
1718 &sc->alc_rdata.alc_smb_seg, 1);
1719 return error;
1720 }
1721
1722 sc->alc_rdata.alc_smb_paddr =
1723 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr;
1724
1725
1726 /* Create DMA maps for Tx buffers. */
1727 for (i = 0; i < ALC_TX_RING_CNT; i++) {
1728 txd = &sc->alc_cdata.alc_txdesc[i];
1729 txd->tx_m = NULL;
1730 txd->tx_dmamap = NULL;
1731 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE,
1732 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT,
1733 &txd->tx_dmamap);
1734 if (error) {
1735 printf("%s: could not create Tx dmamap.\n",
1736 device_xname(sc->sc_dev));
1737 return error;
1738 }
1739 }
1740
1741 /* Create DMA maps for Rx buffers. */
1742 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
1743 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap);
1744 if (error) {
1745 printf("%s: could not create spare Rx dmamap.\n",
1746 device_xname(sc->sc_dev));
1747 return error;
1748 }
1749
1750 for (i = 0; i < ALC_RX_RING_CNT; i++) {
1751 rxd = &sc->alc_cdata.alc_rxdesc[i];
1752 rxd->rx_m = NULL;
1753 rxd->rx_dmamap = NULL;
1754 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
1755 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap);
1756 if (error) {
1757 printf("%s: could not create Rx dmamap.\n",
1758 device_xname(sc->sc_dev));
1759 return error;
1760 }
1761 }
1762
1763 return (0);
1764 }
1765
1766
1767 static void
alc_dma_free(struct alc_softc * sc)1768 alc_dma_free(struct alc_softc *sc)
1769 {
1770 struct alc_txdesc *txd;
1771 struct alc_rxdesc *rxd;
1772 int i;
1773
1774 /* Tx buffers */
1775 for (i = 0; i < ALC_TX_RING_CNT; i++) {
1776 txd = &sc->alc_cdata.alc_txdesc[i];
1777 if (txd->tx_dmamap != NULL) {
1778 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap);
1779 txd->tx_dmamap = NULL;
1780 }
1781 }
1782 /* Rx buffers */
1783 for (i = 0; i < ALC_RX_RING_CNT; i++) {
1784 rxd = &sc->alc_cdata.alc_rxdesc[i];
1785 if (rxd->rx_dmamap != NULL) {
1786 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap);
1787 rxd->rx_dmamap = NULL;
1788 }
1789 }
1790 if (sc->alc_cdata.alc_rx_sparemap != NULL) {
1791 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap);
1792 sc->alc_cdata.alc_rx_sparemap = NULL;
1793 }
1794
1795 /* Tx ring. */
1796 if (sc->alc_cdata.alc_tx_ring_map != NULL)
1797 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map);
1798 if (sc->alc_cdata.alc_tx_ring_map != NULL &&
1799 sc->alc_rdata.alc_tx_ring != NULL)
1800 bus_dmamem_free(sc->sc_dmat,
1801 &sc->alc_rdata.alc_tx_ring_seg, 1);
1802 sc->alc_rdata.alc_tx_ring = NULL;
1803 sc->alc_cdata.alc_tx_ring_map = NULL;
1804
1805 /* Rx ring. */
1806 if (sc->alc_cdata.alc_rx_ring_map != NULL)
1807 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map);
1808 if (sc->alc_cdata.alc_rx_ring_map != NULL &&
1809 sc->alc_rdata.alc_rx_ring != NULL)
1810 bus_dmamem_free(sc->sc_dmat,
1811 &sc->alc_rdata.alc_rx_ring_seg, 1);
1812 sc->alc_rdata.alc_rx_ring = NULL;
1813 sc->alc_cdata.alc_rx_ring_map = NULL;
1814
1815 /* Rx return ring. */
1816 if (sc->alc_cdata.alc_rr_ring_map != NULL)
1817 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map);
1818 if (sc->alc_cdata.alc_rr_ring_map != NULL &&
1819 sc->alc_rdata.alc_rr_ring != NULL)
1820 bus_dmamem_free(sc->sc_dmat,
1821 &sc->alc_rdata.alc_rr_ring_seg, 1);
1822 sc->alc_rdata.alc_rr_ring = NULL;
1823 sc->alc_cdata.alc_rr_ring_map = NULL;
1824
1825 /* CMB block */
1826 if (sc->alc_cdata.alc_cmb_map != NULL)
1827 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map);
1828 if (sc->alc_cdata.alc_cmb_map != NULL &&
1829 sc->alc_rdata.alc_cmb != NULL)
1830 bus_dmamem_free(sc->sc_dmat,
1831 &sc->alc_rdata.alc_cmb_seg, 1);
1832 sc->alc_rdata.alc_cmb = NULL;
1833 sc->alc_cdata.alc_cmb_map = NULL;
1834
1835 /* SMB block */
1836 if (sc->alc_cdata.alc_smb_map != NULL)
1837 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map);
1838 if (sc->alc_cdata.alc_smb_map != NULL &&
1839 sc->alc_rdata.alc_smb != NULL)
1840 bus_dmamem_free(sc->sc_dmat,
1841 &sc->alc_rdata.alc_smb_seg, 1);
1842 sc->alc_rdata.alc_smb = NULL;
1843 sc->alc_cdata.alc_smb_map = NULL;
1844 }
1845
1846 static int
alc_encap(struct alc_softc * sc,struct mbuf ** m_head)1847 alc_encap(struct alc_softc *sc, struct mbuf **m_head)
1848 {
1849 struct alc_txdesc *txd, *txd_last;
1850 struct tx_desc *desc;
1851 struct mbuf *m;
1852 bus_dmamap_t map;
1853 uint32_t cflags, poff, vtag;
1854 int error, idx, nsegs, prod;
1855 #if NVLAN > 0
1856 struct m_tag *mtag;
1857 #endif
1858
1859 m = *m_head;
1860 cflags = vtag = 0;
1861 poff = 0;
1862
1863 prod = sc->alc_cdata.alc_tx_prod;
1864 txd = &sc->alc_cdata.alc_txdesc[prod];
1865 txd_last = txd;
1866 map = txd->tx_dmamap;
1867
1868 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT);
1869
1870 if (error == EFBIG) {
1871 error = 0;
1872
1873 *m_head = m_pullup(*m_head, MHLEN);
1874 if (*m_head == NULL) {
1875 printf("%s: can't defrag TX mbuf\n",
1876 device_xname(sc->sc_dev));
1877 return ENOBUFS;
1878 }
1879
1880 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head,
1881 BUS_DMA_NOWAIT);
1882
1883 if (error != 0) {
1884 printf("%s: could not load defragged TX mbuf\n",
1885 device_xname(sc->sc_dev));
1886 m_freem(*m_head);
1887 *m_head = NULL;
1888 return error;
1889 }
1890 } else if (error) {
1891 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev));
1892 return (error);
1893 }
1894
1895 nsegs = map->dm_nsegs;
1896
1897 if (nsegs == 0) {
1898 m_freem(*m_head);
1899 *m_head = NULL;
1900 return (EIO);
1901 }
1902
1903 /* Check descriptor overrun. */
1904 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) {
1905 bus_dmamap_unload(sc->sc_dmat, map);
1906 return (ENOBUFS);
1907 }
1908 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1909 BUS_DMASYNC_PREWRITE);
1910
1911 m = *m_head;
1912 desc = NULL;
1913 idx = 0;
1914 #if NVLAN > 0
1915 /* Configure VLAN hardware tag insertion. */
1916 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) {
1917 vtag = htons(VLAN_TAG_VALUE(mtag));
1918 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK;
1919 cflags |= TD_INS_VLAN_TAG;
1920 }
1921 #endif
1922 /* Configure Tx checksum offload. */
1923 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) {
1924 cflags |= TD_CUSTOM_CSUM;
1925 /* Set checksum start offset. */
1926 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) &
1927 TD_PLOAD_OFFSET_MASK;
1928 }
1929 for (; idx < nsegs; idx++) {
1930 desc = &sc->alc_rdata.alc_tx_ring[prod];
1931 desc->len =
1932 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag);
1933 desc->flags = htole32(cflags);
1934 desc->addr = htole64(map->dm_segs[idx].ds_addr);
1935 sc->alc_cdata.alc_tx_cnt++;
1936 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
1937 }
1938 /* Update producer index. */
1939 sc->alc_cdata.alc_tx_prod = prod;
1940
1941 /* Finally set EOP on the last descriptor. */
1942 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT;
1943 desc = &sc->alc_rdata.alc_tx_ring[prod];
1944 desc->flags |= htole32(TD_EOP);
1945
1946 /* Swap dmamap of the first and the last. */
1947 txd = &sc->alc_cdata.alc_txdesc[prod];
1948 map = txd_last->tx_dmamap;
1949 txd_last->tx_dmamap = txd->tx_dmamap;
1950 txd->tx_dmamap = map;
1951 txd->tx_m = m;
1952
1953 return (0);
1954 }
1955
1956 static void
alc_start(struct ifnet * ifp)1957 alc_start(struct ifnet *ifp)
1958 {
1959 struct alc_softc *sc = ifp->if_softc;
1960 struct mbuf *m_head;
1961 int enq;
1962
1963 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1964 return;
1965 if ((sc->alc_flags & ALC_FLAG_LINK) == 0)
1966 return;
1967 if (IFQ_IS_EMPTY(&ifp->if_snd))
1968 return;
1969
1970 /* Reclaim transmitted frames. */
1971 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
1972 alc_txeof(sc);
1973
1974 enq = 0;
1975 for (;;) {
1976 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1977 if (m_head == NULL)
1978 break;
1979
1980 /*
1981 * Pack the data into the transmit ring. If we
1982 * don't have room, set the OACTIVE flag and wait
1983 * for the NIC to drain the ring.
1984 */
1985 if (alc_encap(sc, &m_head)) {
1986 if (m_head == NULL)
1987 break;
1988 ifp->if_flags |= IFF_OACTIVE;
1989 break;
1990 }
1991 enq = 1;
1992
1993 /*
1994 * If there's a BPF listener, bounce a copy of this frame
1995 * to him.
1996 */
1997 bpf_mtap(ifp, m_head);
1998 }
1999
2000 if (enq) {
2001 /* Sync descriptors. */
2002 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
2003 sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
2004 BUS_DMASYNC_PREWRITE);
2005 /* Kick. Assume we're using normal Tx priority queue. */
2006 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
2007 (sc->alc_cdata.alc_tx_prod <<
2008 MBOX_TD_PROD_LO_IDX_SHIFT) &
2009 MBOX_TD_PROD_LO_IDX_MASK);
2010 /* Set a timeout in case the chip goes out to lunch. */
2011 ifp->if_timer = ALC_TX_TIMEOUT;
2012 }
2013 }
2014
2015 static void
alc_watchdog(struct ifnet * ifp)2016 alc_watchdog(struct ifnet *ifp)
2017 {
2018 struct alc_softc *sc = ifp->if_softc;
2019
2020 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
2021 printf("%s: watchdog timeout (missed link)\n",
2022 device_xname(sc->sc_dev));
2023 ifp->if_oerrors++;
2024 alc_init_backend(ifp, false);
2025 return;
2026 }
2027
2028 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
2029 ifp->if_oerrors++;
2030 alc_init_backend(ifp, false);
2031 alc_start(ifp);
2032 }
2033
2034 static int
alc_ioctl(struct ifnet * ifp,u_long cmd,void * data)2035 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data)
2036 {
2037 struct alc_softc *sc = ifp->if_softc;
2038 struct mii_data *mii = &sc->sc_miibus;
2039 struct ifreq *ifr = (struct ifreq *)data;
2040 int s, error = 0;
2041
2042 s = splnet();
2043
2044 error = ether_ioctl(ifp, cmd, data);
2045 switch (cmd) {
2046 case SIOCSIFADDR:
2047 ifp->if_flags |= IFF_UP;
2048 if (!(ifp->if_flags & IFF_RUNNING))
2049 alc_init(ifp);
2050 break;
2051
2052 case SIOCSIFFLAGS:
2053 if (ifp->if_flags & IFF_UP) {
2054 if (ifp->if_flags & IFF_RUNNING)
2055 error = ENETRESET;
2056 else
2057 alc_init(ifp);
2058 } else {
2059 if (ifp->if_flags & IFF_RUNNING)
2060 alc_stop(ifp, 0);
2061 }
2062 break;
2063
2064 case SIOCSIFMEDIA:
2065 case SIOCGIFMEDIA:
2066 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2067 break;
2068
2069 default:
2070 error = ether_ioctl(ifp, cmd, data);
2071 break;
2072 }
2073
2074 if (error == ENETRESET) {
2075 if (ifp->if_flags & IFF_RUNNING)
2076 alc_iff(sc);
2077 error = 0;
2078 }
2079
2080 splx(s);
2081 return (error);
2082 }
2083
2084 static void
alc_mac_config(struct alc_softc * sc)2085 alc_mac_config(struct alc_softc *sc)
2086 {
2087 struct mii_data *mii;
2088 uint32_t reg;
2089
2090 mii = &sc->sc_miibus;
2091 reg = CSR_READ_4(sc, ALC_MAC_CFG);
2092 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2093 MAC_CFG_SPEED_MASK);
2094 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 ||
2095 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 ||
2096 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2)
2097 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
2098 /* Reprogram MAC with resolved speed/duplex. */
2099 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2100 case IFM_10_T:
2101 case IFM_100_TX:
2102 reg |= MAC_CFG_SPEED_10_100;
2103 break;
2104 case IFM_1000_T:
2105 reg |= MAC_CFG_SPEED_1000;
2106 break;
2107 }
2108 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2109 reg |= MAC_CFG_FULL_DUPLEX;
2110 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2111 reg |= MAC_CFG_TX_FC;
2112 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2113 reg |= MAC_CFG_RX_FC;
2114 }
2115 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2116 }
2117
2118 static void
alc_stats_clear(struct alc_softc * sc)2119 alc_stats_clear(struct alc_softc *sc)
2120 {
2121 struct smb sb, *smb;
2122 uint32_t *reg;
2123 int i;
2124
2125 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2126 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
2127 sc->alc_cdata.alc_smb_map->dm_mapsize,
2128 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2129 smb = sc->alc_rdata.alc_smb;
2130 /* Update done, clear. */
2131 smb->updated = 0;
2132 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
2133 sc->alc_cdata.alc_smb_map->dm_mapsize,
2134 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2135 } else {
2136 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
2137 reg++) {
2138 CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2139 i += sizeof(uint32_t);
2140 }
2141 /* Read Tx statistics. */
2142 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
2143 reg++) {
2144 CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2145 i += sizeof(uint32_t);
2146 }
2147 }
2148 }
2149
2150 static void
alc_stats_update(struct alc_softc * sc)2151 alc_stats_update(struct alc_softc *sc)
2152 {
2153 struct ifnet *ifp = &sc->sc_ec.ec_if;
2154 struct alc_hw_stats *stat;
2155 struct smb sb, *smb;
2156 uint32_t *reg;
2157 int i;
2158
2159 stat = &sc->alc_stats;
2160 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2161 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
2162 sc->alc_cdata.alc_smb_map->dm_mapsize,
2163 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2164 smb = sc->alc_rdata.alc_smb;
2165 if (smb->updated == 0)
2166 return;
2167 } else {
2168 smb = &sb;
2169 /* Read Rx statistics. */
2170 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
2171 reg++) {
2172 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2173 i += sizeof(uint32_t);
2174 }
2175 /* Read Tx statistics. */
2176 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
2177 reg++) {
2178 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2179 i += sizeof(uint32_t);
2180 }
2181 }
2182
2183 /* Rx stats. */
2184 stat->rx_frames += smb->rx_frames;
2185 stat->rx_bcast_frames += smb->rx_bcast_frames;
2186 stat->rx_mcast_frames += smb->rx_mcast_frames;
2187 stat->rx_pause_frames += smb->rx_pause_frames;
2188 stat->rx_control_frames += smb->rx_control_frames;
2189 stat->rx_crcerrs += smb->rx_crcerrs;
2190 stat->rx_lenerrs += smb->rx_lenerrs;
2191 stat->rx_bytes += smb->rx_bytes;
2192 stat->rx_runts += smb->rx_runts;
2193 stat->rx_fragments += smb->rx_fragments;
2194 stat->rx_pkts_64 += smb->rx_pkts_64;
2195 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2196 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2197 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2198 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2199 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2200 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2201 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2202 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2203 stat->rx_rrs_errs += smb->rx_rrs_errs;
2204 stat->rx_alignerrs += smb->rx_alignerrs;
2205 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2206 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2207 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2208
2209 /* Tx stats. */
2210 stat->tx_frames += smb->tx_frames;
2211 stat->tx_bcast_frames += smb->tx_bcast_frames;
2212 stat->tx_mcast_frames += smb->tx_mcast_frames;
2213 stat->tx_pause_frames += smb->tx_pause_frames;
2214 stat->tx_excess_defer += smb->tx_excess_defer;
2215 stat->tx_control_frames += smb->tx_control_frames;
2216 stat->tx_deferred += smb->tx_deferred;
2217 stat->tx_bytes += smb->tx_bytes;
2218 stat->tx_pkts_64 += smb->tx_pkts_64;
2219 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2220 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2221 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2222 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2223 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2224 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2225 stat->tx_single_colls += smb->tx_single_colls;
2226 stat->tx_multi_colls += smb->tx_multi_colls;
2227 stat->tx_late_colls += smb->tx_late_colls;
2228 stat->tx_excess_colls += smb->tx_excess_colls;
2229 stat->tx_underrun += smb->tx_underrun;
2230 stat->tx_desc_underrun += smb->tx_desc_underrun;
2231 stat->tx_lenerrs += smb->tx_lenerrs;
2232 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2233 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2234 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2235
2236 /* Update counters in ifnet. */
2237 ifp->if_opackets += smb->tx_frames;
2238
2239 ifp->if_collisions += smb->tx_single_colls +
2240 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2241 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT;
2242
2243 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls +
2244 smb->tx_underrun + smb->tx_pkts_truncated;
2245
2246 ifp->if_ipackets += smb->rx_frames;
2247
2248 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2249 smb->rx_runts + smb->rx_pkts_truncated +
2250 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2251 smb->rx_alignerrs;
2252
2253 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2254 /* Update done, clear. */
2255 smb->updated = 0;
2256 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
2257 sc->alc_cdata.alc_smb_map->dm_mapsize,
2258 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2259 }
2260 }
2261
2262 static int
alc_intr(void * arg)2263 alc_intr(void *arg)
2264 {
2265 struct alc_softc *sc = arg;
2266 struct ifnet *ifp = &sc->sc_ec.ec_if;
2267 uint32_t status;
2268
2269 status = CSR_READ_4(sc, ALC_INTR_STATUS);
2270 if ((status & ALC_INTRS) == 0)
2271 return (0);
2272
2273 /* Acknowledge and disable interrupts. */
2274 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
2275
2276 if (ifp->if_flags & IFF_RUNNING) {
2277 if (status & INTR_RX_PKT) {
2278 int error;
2279
2280 error = alc_rxintr(sc);
2281 if (error) {
2282 alc_init_backend(ifp, false);
2283 return (0);
2284 }
2285 }
2286
2287 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
2288 INTR_TXQ_TO_RST)) {
2289 if (status & INTR_DMA_RD_TO_RST)
2290 printf("%s: DMA read error! -- resetting\n",
2291 device_xname(sc->sc_dev));
2292 if (status & INTR_DMA_WR_TO_RST)
2293 printf("%s: DMA write error! -- resetting\n",
2294 device_xname(sc->sc_dev));
2295 if (status & INTR_TXQ_TO_RST)
2296 printf("%s: TxQ reset! -- resetting\n",
2297 device_xname(sc->sc_dev));
2298 alc_init_backend(ifp, false);
2299 return (0);
2300 }
2301
2302 alc_txeof(sc);
2303 if (!IFQ_IS_EMPTY(&ifp->if_snd))
2304 alc_start(ifp);
2305 }
2306
2307 /* Re-enable interrupts. */
2308 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
2309 return (1);
2310 }
2311
2312 static void
alc_txeof(struct alc_softc * sc)2313 alc_txeof(struct alc_softc *sc)
2314 {
2315 struct ifnet *ifp = &sc->sc_ec.ec_if;
2316 struct alc_txdesc *txd;
2317 uint32_t cons, prod;
2318 int prog;
2319
2320 if (sc->alc_cdata.alc_tx_cnt == 0)
2321 return;
2322 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
2323 sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
2324 BUS_DMASYNC_POSTREAD);
2325 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
2326 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
2327 sc->alc_cdata.alc_cmb_map->dm_mapsize,
2328 BUS_DMASYNC_POSTREAD);
2329 prod = sc->alc_rdata.alc_cmb->cons;
2330 } else
2331 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
2332 /* Assume we're using normal Tx priority queue. */
2333 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
2334 MBOX_TD_CONS_LO_IDX_SHIFT;
2335 cons = sc->alc_cdata.alc_tx_cons;
2336 /*
2337 * Go through our Tx list and free mbufs for those
2338 * frames which have been transmitted.
2339 */
2340 for (prog = 0; cons != prod; prog++,
2341 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) {
2342 if (sc->alc_cdata.alc_tx_cnt <= 0)
2343 break;
2344 prog++;
2345 ifp->if_flags &= ~IFF_OACTIVE;
2346 sc->alc_cdata.alc_tx_cnt--;
2347 txd = &sc->alc_cdata.alc_txdesc[cons];
2348 if (txd->tx_m != NULL) {
2349 /* Reclaim transmitted mbufs. */
2350 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0,
2351 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2352 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap);
2353 m_freem(txd->tx_m);
2354 txd->tx_m = NULL;
2355 }
2356 }
2357
2358 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
2359 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
2360 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD);
2361 sc->alc_cdata.alc_tx_cons = cons;
2362 /*
2363 * Unarm watchdog timer only when there is no pending
2364 * frames in Tx queue.
2365 */
2366 if (sc->alc_cdata.alc_tx_cnt == 0)
2367 ifp->if_timer = 0;
2368 }
2369
2370 static int
alc_newbuf(struct alc_softc * sc,struct alc_rxdesc * rxd,bool init)2371 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init)
2372 {
2373 struct mbuf *m;
2374 bus_dmamap_t map;
2375 int error;
2376
2377 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA);
2378 if (m == NULL)
2379 return (ENOBUFS);
2380 MCLGET(m, init ? M_WAITOK : M_DONTWAIT);
2381 if (!(m->m_flags & M_EXT)) {
2382 m_freem(m);
2383 return (ENOBUFS);
2384 }
2385
2386 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX;
2387
2388 error = bus_dmamap_load_mbuf(sc->sc_dmat,
2389 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT);
2390
2391 if (error != 0) {
2392 m_freem(m);
2393
2394 if (init)
2395 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev));
2396
2397 return (error);
2398 }
2399
2400 if (rxd->rx_m != NULL) {
2401 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0,
2402 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
2403 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap);
2404 }
2405 map = rxd->rx_dmamap;
2406 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap;
2407 sc->alc_cdata.alc_rx_sparemap = map;
2408 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize,
2409 BUS_DMASYNC_PREREAD);
2410 rxd->rx_m = m;
2411 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr);
2412 return (0);
2413 }
2414
2415 static int
alc_rxintr(struct alc_softc * sc)2416 alc_rxintr(struct alc_softc *sc)
2417 {
2418 struct ifnet *ifp = &sc->sc_ec.ec_if;
2419 struct rx_rdesc *rrd;
2420 uint32_t nsegs, status;
2421 int rr_cons, prog;
2422
2423 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0,
2424 sc->alc_cdata.alc_rr_ring_map->dm_mapsize,
2425 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2426 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0,
2427 sc->alc_cdata.alc_rx_ring_map->dm_mapsize,
2428 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2429 rr_cons = sc->alc_cdata.alc_rr_cons;
2430 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) {
2431 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons];
2432 status = le32toh(rrd->status);
2433 if ((status & RRD_VALID) == 0)
2434 break;
2435 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo));
2436 if (nsegs == 0) {
2437 /* This should not happen! */
2438 if (alcdebug)
2439 printf("%s: unexpected segment count -- "
2440 "resetting\n", device_xname(sc->sc_dev));
2441 return (EIO);
2442 }
2443 alc_rxeof(sc, rrd);
2444 /* Clear Rx return status. */
2445 rrd->status = 0;
2446 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT);
2447 sc->alc_cdata.alc_rx_cons += nsegs;
2448 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT;
2449 prog += nsegs;
2450 }
2451
2452 if (prog > 0) {
2453 /* Update the consumer index. */
2454 sc->alc_cdata.alc_rr_cons = rr_cons;
2455 /* Sync Rx return descriptors. */
2456 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0,
2457 sc->alc_cdata.alc_rr_ring_map->dm_mapsize,
2458 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2459 /*
2460 * Sync updated Rx descriptors such that controller see
2461 * modified buffer addresses.
2462 */
2463 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0,
2464 sc->alc_cdata.alc_rx_ring_map->dm_mapsize,
2465 BUS_DMASYNC_PREWRITE);
2466 /*
2467 * Let controller know availability of new Rx buffers.
2468 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors
2469 * it may be possible to update ALC_MBOX_RD0_PROD_IDX
2470 * only when Rx buffer pre-fetching is required. In
2471 * addition we already set ALC_RX_RD_FREE_THRESH to
2472 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However
2473 * it still seems that pre-fetching needs more
2474 * experimentation.
2475 */
2476 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
2477 sc->alc_cdata.alc_rx_cons);
2478 }
2479
2480 return (0);
2481 }
2482
2483 /* Receive a frame. */
2484 static void
alc_rxeof(struct alc_softc * sc,struct rx_rdesc * rrd)2485 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd)
2486 {
2487 struct ifnet *ifp = &sc->sc_ec.ec_if;
2488 struct alc_rxdesc *rxd;
2489 struct mbuf *mp, *m;
2490 uint32_t rdinfo, status;
2491 int count, nsegs, rx_cons;
2492
2493 status = le32toh(rrd->status);
2494 rdinfo = le32toh(rrd->rdinfo);
2495 rx_cons = RRD_RD_IDX(rdinfo);
2496 nsegs = RRD_RD_CNT(rdinfo);
2497
2498 sc->alc_cdata.alc_rxlen = RRD_BYTES(status);
2499 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) {
2500 /*
2501 * We want to pass the following frames to upper
2502 * layer regardless of error status of Rx return
2503 * ring.
2504 *
2505 * o IP/TCP/UDP checksum is bad.
2506 * o frame length and protocol specific length
2507 * does not match.
2508 *
2509 * Force network stack compute checksum for
2510 * errored frames.
2511 */
2512 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
2513 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN |
2514 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0)
2515 return;
2516 }
2517
2518 for (count = 0; count < nsegs; count++,
2519 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) {
2520 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons];
2521 mp = rxd->rx_m;
2522 /* Add a new receive buffer to the ring. */
2523 if (alc_newbuf(sc, rxd, false) != 0) {
2524 ifp->if_iqdrops++;
2525 /* Reuse Rx buffers. */
2526 if (sc->alc_cdata.alc_rxhead != NULL)
2527 m_freem(sc->alc_cdata.alc_rxhead);
2528 break;
2529 }
2530
2531 /*
2532 * Assume we've received a full sized frame.
2533 * Actual size is fixed when we encounter the end of
2534 * multi-segmented frame.
2535 */
2536 mp->m_len = sc->alc_buf_size;
2537
2538 /* Chain received mbufs. */
2539 if (sc->alc_cdata.alc_rxhead == NULL) {
2540 sc->alc_cdata.alc_rxhead = mp;
2541 sc->alc_cdata.alc_rxtail = mp;
2542 } else {
2543 mp->m_flags &= ~M_PKTHDR;
2544 sc->alc_cdata.alc_rxprev_tail =
2545 sc->alc_cdata.alc_rxtail;
2546 sc->alc_cdata.alc_rxtail->m_next = mp;
2547 sc->alc_cdata.alc_rxtail = mp;
2548 }
2549
2550 if (count == nsegs - 1) {
2551 /* Last desc. for this frame. */
2552 m = sc->alc_cdata.alc_rxhead;
2553 m->m_flags |= M_PKTHDR;
2554 /*
2555 * It seems that L1C/L2C controller has no way
2556 * to tell hardware to strip CRC bytes.
2557 */
2558 m->m_pkthdr.len =
2559 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN;
2560 if (nsegs > 1) {
2561 /* Set last mbuf size. */
2562 mp->m_len = sc->alc_cdata.alc_rxlen -
2563 (nsegs - 1) * sc->alc_buf_size;
2564 /* Remove the CRC bytes in chained mbufs. */
2565 if (mp->m_len <= ETHER_CRC_LEN) {
2566 sc->alc_cdata.alc_rxtail =
2567 sc->alc_cdata.alc_rxprev_tail;
2568 sc->alc_cdata.alc_rxtail->m_len -=
2569 (ETHER_CRC_LEN - mp->m_len);
2570 sc->alc_cdata.alc_rxtail->m_next = NULL;
2571 m_freem(mp);
2572 } else {
2573 mp->m_len -= ETHER_CRC_LEN;
2574 }
2575 } else
2576 m->m_len = m->m_pkthdr.len;
2577 m_set_rcvif(m, ifp);
2578 #if NVLAN > 0
2579 /*
2580 * Due to hardware bugs, Rx checksum offloading
2581 * was intentionally disabled.
2582 */
2583 if (status & RRD_VLAN_TAG) {
2584 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag));
2585 VLAN_INPUT_TAG(ifp, m, ntohs(vtag), );
2586 }
2587 #endif
2588
2589 bpf_mtap(ifp, m);
2590
2591 /* Pass it on. */
2592 if_percpuq_enqueue(ifp->if_percpuq, m);
2593 }
2594 }
2595 /* Reset mbuf chains. */
2596 ALC_RXCHAIN_RESET(sc);
2597 }
2598
2599 static void
alc_tick(void * xsc)2600 alc_tick(void *xsc)
2601 {
2602 struct alc_softc *sc = xsc;
2603 struct mii_data *mii = &sc->sc_miibus;
2604 int s;
2605
2606 s = splnet();
2607 mii_tick(mii);
2608 alc_stats_update(sc);
2609 splx(s);
2610
2611 callout_schedule(&sc->sc_tick_ch, hz);
2612 }
2613
2614 static void
alc_osc_reset(struct alc_softc * sc)2615 alc_osc_reset(struct alc_softc *sc)
2616 {
2617 uint32_t reg;
2618
2619 reg = CSR_READ_4(sc, ALC_MISC3);
2620 reg &= ~MISC3_25M_BY_SW;
2621 reg |= MISC3_25M_NOTO_INTNL;
2622 CSR_WRITE_4(sc, ALC_MISC3, reg);
2623
2624 reg = CSR_READ_4(sc, ALC_MISC);
2625 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) {
2626 /*
2627 * Restore over-current protection default value.
2628 * This value could be reset by MAC reset.
2629 */
2630 reg &= ~MISC_PSW_OCP_MASK;
2631 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT);
2632 reg &= ~MISC_INTNLOSC_OPEN;
2633 CSR_WRITE_4(sc, ALC_MISC, reg);
2634 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
2635 reg = CSR_READ_4(sc, ALC_MISC2);
2636 reg &= ~MISC2_CALB_START;
2637 CSR_WRITE_4(sc, ALC_MISC2, reg);
2638 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);
2639
2640 } else {
2641 reg &= ~MISC_INTNLOSC_OPEN;
2642 /* Disable isolate for revision A devices. */
2643 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
2644 reg &= ~MISC_ISO_ENB;
2645 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
2646 CSR_WRITE_4(sc, ALC_MISC, reg);
2647 }
2648
2649 DELAY(20);
2650 }
2651
2652 static void
alc_reset(struct alc_softc * sc)2653 alc_reset(struct alc_softc *sc)
2654 {
2655 uint32_t pmcfg, reg;
2656 int i;
2657
2658 pmcfg = 0;
2659 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2660 /* Reset workaround. */
2661 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1);
2662 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
2663 (sc->alc_rev & 0x01) != 0) {
2664 /* Disable L0s/L1s before reset. */
2665 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
2666 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
2667 != 0) {
2668 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB |
2669 PM_CFG_ASPM_L1_ENB);
2670 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
2671 }
2672 }
2673 }
2674 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
2675 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
2676 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2677
2678 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2679 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
2680 DELAY(10);
2681 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)
2682 break;
2683 }
2684 if (i == 0)
2685 printf("%s: MAC reset timeout!\n", device_xname(sc->sc_dev));
2686 }
2687 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
2688 DELAY(10);
2689 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
2690 break;
2691 }
2692 if (i == 0)
2693 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev));
2694
2695 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
2696 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
2697 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC |
2698 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
2699 break;
2700 DELAY(10);
2701 }
2702 if (i == 0)
2703 printf("%s: reset timeout(0x%08x)!\n",
2704 device_xname(sc->sc_dev), reg);
2705
2706 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2707 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
2708 (sc->alc_rev & 0x01) != 0) {
2709 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
2710 reg |= MASTER_CLK_SEL_DIS;
2711 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2712 /* Restore L0s/L1s config. */
2713 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
2714 != 0)
2715 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
2716 }
2717
2718 alc_osc_reset(sc);
2719 reg = CSR_READ_4(sc, ALC_MISC3);
2720 reg &= ~MISC3_25M_BY_SW;
2721 reg |= MISC3_25M_NOTO_INTNL;
2722 CSR_WRITE_4(sc, ALC_MISC3, reg);
2723 reg = CSR_READ_4(sc, ALC_MISC);
2724 reg &= ~MISC_INTNLOSC_OPEN;
2725 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
2726 reg &= ~MISC_ISO_ENB;
2727 CSR_WRITE_4(sc, ALC_MISC, reg);
2728 DELAY(20);
2729 }
2730 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
2731 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B ||
2732 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2)
2733 CSR_WRITE_4(sc, ALC_SERDES_LOCK,
2734 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
2735 SERDES_PHY_CLK_SLOWDOWN);
2736 }
2737
2738 static int
alc_init(struct ifnet * ifp)2739 alc_init(struct ifnet *ifp)
2740 {
2741
2742 return alc_init_backend(ifp, true);
2743 }
2744
2745 static int
alc_init_backend(struct ifnet * ifp,bool init)2746 alc_init_backend(struct ifnet *ifp, bool init)
2747 {
2748 struct alc_softc *sc = ifp->if_softc;
2749 struct mii_data *mii;
2750 uint8_t eaddr[ETHER_ADDR_LEN];
2751 bus_addr_t paddr;
2752 uint32_t reg, rxf_hi, rxf_lo;
2753 int error;
2754
2755 /*
2756 * Cancel any pending I/O.
2757 */
2758 alc_stop(ifp, 0);
2759 /*
2760 * Reset the chip to a known state.
2761 */
2762 alc_reset(sc);
2763
2764 /* Initialize Rx descriptors. */
2765 error = alc_init_rx_ring(sc, init);
2766 if (error != 0) {
2767 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev));
2768 alc_stop(ifp, 0);
2769 return (error);
2770 }
2771 alc_init_rr_ring(sc);
2772 alc_init_tx_ring(sc);
2773 alc_init_cmb(sc);
2774 alc_init_smb(sc);
2775
2776 /* Enable all clocks. */
2777 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2778 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB |
2779 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB |
2780 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB |
2781 CLK_GATING_RXMAC_ENB);
2782 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0)
2783 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER,
2784 IDLE_DECISN_TIMER_DEFAULT_1MS);
2785 } else
2786 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
2787
2788
2789 /* Reprogram the station address. */
2790 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr));
2791 CSR_WRITE_4(sc, ALC_PAR0,
2792 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2793 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
2794 /*
2795 * Clear WOL status and disable all WOL feature as WOL
2796 * would interfere Rx operation under normal environments.
2797 */
2798 CSR_READ_4(sc, ALC_WOL_CFG);
2799 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2800 /* Set Tx descriptor base addresses. */
2801 paddr = sc->alc_rdata.alc_tx_ring_paddr;
2802 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2803 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2804 /* We don't use high priority ring. */
2805 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
2806 /* Set Tx descriptor counter. */
2807 CSR_WRITE_4(sc, ALC_TD_RING_CNT,
2808 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
2809 /* Set Rx descriptor base addresses. */
2810 paddr = sc->alc_rdata.alc_rx_ring_paddr;
2811 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2812 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2813 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
2814 /* We use one Rx ring. */
2815 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
2816 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
2817 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
2818 }
2819 /* Set Rx descriptor counter. */
2820 CSR_WRITE_4(sc, ALC_RD_RING_CNT,
2821 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
2822
2823 /*
2824 * Let hardware split jumbo frames into alc_max_buf_sized chunks.
2825 * if it do not fit the buffer size. Rx return descriptor holds
2826 * a counter that indicates how many fragments were made by the
2827 * hardware. The buffer size should be multiple of 8 bytes.
2828 * Since hardware has limit on the size of buffer size, always
2829 * use the maximum value.
2830 * For strict-alignment architectures make sure to reduce buffer
2831 * size by 8 bytes to make room for alignment fixup.
2832 */
2833 sc->alc_buf_size = RX_BUF_SIZE_MAX;
2834 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
2835
2836 paddr = sc->alc_rdata.alc_rr_ring_paddr;
2837 /* Set Rx return descriptor base addresses. */
2838 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2839 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
2840 /* We use one Rx return ring. */
2841 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
2842 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
2843 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
2844 }\
2845 /* Set Rx return descriptor counter. */
2846 CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
2847 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
2848 paddr = sc->alc_rdata.alc_cmb_paddr;
2849 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
2850 paddr = sc->alc_rdata.alc_smb_paddr;
2851 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2852 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
2853
2854 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) {
2855 /* Reconfigure SRAM - Vendor magic. */
2856 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
2857 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
2858 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
2859 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
2860 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
2861 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
2862 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
2863 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
2864 }
2865
2866 /* Tell hardware that we're ready to load DMA blocks. */
2867 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
2868
2869 /* Configure interrupt moderation timer. */
2870 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
2871 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
2872 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
2873 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0)
2874 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
2875 CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
2876 /*
2877 * We don't want to automatic interrupt clear as task queue
2878 * for the interrupt should know interrupt status.
2879 */
2880 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
2881 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2882 reg |= MASTER_SA_TIMER_ENB;
2883 if (ALC_USECS(sc->alc_int_rx_mod) != 0)
2884 reg |= MASTER_IM_RX_TIMER_ENB;
2885 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 &&
2886 ALC_USECS(sc->alc_int_tx_mod) != 0)
2887 reg |= MASTER_IM_TX_TIMER_ENB;
2888 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2889 /*
2890 * Disable interrupt re-trigger timer. We don't want automatic
2891 * re-triggering of un-ACKed interrupts.
2892 */
2893 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
2894 /* Configure CMB. */
2895 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2896 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3);
2897 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER,
2898 ALC_USECS(sc->alc_int_tx_mod));
2899 } else {
2900 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
2901 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
2902 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
2903 } else
2904 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
2905 }
2906 /*
2907 * Hardware can be configured to issue SMB interrupt based
2908 * on programmed interval. Since there is a callout that is
2909 * invoked for every hz in driver we use that instead of
2910 * relying on periodic SMB interrupt.
2911 */
2912 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
2913 /* Clear MAC statistics. */
2914 alc_stats_clear(sc);
2915
2916 /*
2917 * Always use maximum frame size that controller can support.
2918 * Otherwise received frames that has larger frame length
2919 * than alc(4) MTU would be silently dropped in hardware. This
2920 * would make path-MTU discovery hard as sender wouldn't get
2921 * any responses from receiver. alc(4) supports
2922 * multi-fragmented frames on Rx path so it has no issue on
2923 * assembling fragmented frames. Using maximum frame size also
2924 * removes the need to reinitialize hardware when interface
2925 * MTU configuration was changed.
2926 *
2927 * Be conservative in what you do, be liberal in what you
2928 * accept from others - RFC 793.
2929 */
2930 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen);
2931
2932 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
2933 /* Disable header split(?) */
2934 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
2935
2936 /* Configure IPG/IFG parameters. */
2937 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
2938 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) &
2939 IPG_IFG_IPGT_MASK) |
2940 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) &
2941 IPG_IFG_MIFG_MASK) |
2942 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) &
2943 IPG_IFG_IPG1_MASK) |
2944 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) &
2945 IPG_IFG_IPG2_MASK));
2946 /* Set parameters for half-duplex media. */
2947 CSR_WRITE_4(sc, ALC_HDPX_CFG,
2948 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2949 HDPX_CFG_LCOL_MASK) |
2950 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2951 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2952 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2953 HDPX_CFG_ABEBT_MASK) |
2954 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2955 HDPX_CFG_JAMIPG_MASK));
2956 }
2957
2958 /*
2959 * Set TSO/checksum offload threshold. For frames that is
2960 * larger than this threshold, hardware wouldn't do
2961 * TSO/checksum offloading.
2962 */
2963 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
2964 TSO_OFFLOAD_THRESH_MASK;
2965 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
2966 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB;
2967 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);
2968 /* Configure TxQ. */
2969 reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
2970 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
2971 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B ||
2972 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2)
2973 reg >>= 1;
2974 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
2975 TXQ_CFG_TD_BURST_MASK;
2976 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB;
2977 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
2978 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2979 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT |
2980 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT |
2981 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT |
2982 HQTD_CFG_BURST_ENB);
2983 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);
2984 reg = WRR_PRI_RESTRICT_NONE;
2985 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT |
2986 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT |
2987 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT |
2988 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT);
2989 CSR_WRITE_4(sc, ALC_WRR, reg);
2990 } else {
2991 /* Configure Rx free descriptor pre-fetching. */
2992 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
2993 ((RX_RD_FREE_THRESH_HI_DEFAULT <<
2994 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) |
2995 ((RX_RD_FREE_THRESH_LO_DEFAULT <<
2996 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK));
2997 }
2998
2999 /*
3000 * Configure flow control parameters.
3001 * XON : 80% of Rx FIFO
3002 * XOFF : 30% of Rx FIFO
3003 */
3004 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3005 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
3006 reg &= SRAM_RX_FIFO_LEN_MASK;
3007 reg *= 8;
3008 if (reg > 8 * 1024)
3009 reg -= RX_FIFO_PAUSE_816X_RSVD;
3010 else
3011 reg -= RX_BUF_SIZE_MAX;
3012 reg /= 8;
3013 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
3014 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
3015 RX_FIFO_PAUSE_THRESH_LO_MASK) |
3016 (((RX_FIFO_PAUSE_816X_RSVD / 8) <<
3017 RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
3018 RX_FIFO_PAUSE_THRESH_HI_MASK));
3019 } else if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 ||
3020 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) {
3021 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
3022 rxf_hi = (reg * 8) / 10;
3023 rxf_lo = (reg * 3) / 10;
3024 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
3025 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
3026 RX_FIFO_PAUSE_THRESH_LO_MASK) |
3027 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
3028 RX_FIFO_PAUSE_THRESH_HI_MASK));
3029 }
3030
3031 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
3032 /* Disable RSS until I understand L1C/L2C's RSS logic. */
3033 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
3034 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
3035 }
3036
3037 /* Configure RxQ. */
3038 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
3039 RXQ_CFG_RD_BURST_MASK;
3040 reg |= RXQ_CFG_RSS_MODE_DIS;
3041 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3042 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT <<
3043 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) &
3044 RXQ_CFG_816X_IDT_TBL_SIZE_MASK;
3045 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 &&
3046 sc->alc_ident->deviceid != PCI_PRODUCT_ATTANSIC_AR8151_V2)
3047 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
3048 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3049
3050 /* Configure DMA parameters. */
3051 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
3052 reg |= sc->alc_rcb;
3053 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
3054 reg |= DMA_CFG_CMB_ENB;
3055 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
3056 reg |= DMA_CFG_SMB_ENB;
3057 else
3058 reg |= DMA_CFG_SMB_DIS;
3059 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
3060 DMA_CFG_RD_BURST_SHIFT;
3061 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
3062 DMA_CFG_WR_BURST_SHIFT;
3063 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
3064 DMA_CFG_RD_DELAY_CNT_MASK;
3065 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
3066 DMA_CFG_WR_DELAY_CNT_MASK;
3067 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3068 switch (AR816X_REV(sc->alc_rev)) {
3069 case AR816X_REV_A0:
3070 case AR816X_REV_A1:
3071 reg |= DMA_CFG_RD_CHNL_SEL_1;
3072 break;
3073 case AR816X_REV_B0:
3074 /* FALLTHROUGH */
3075 default:
3076 reg |= DMA_CFG_RD_CHNL_SEL_3;
3077 break;
3078 }
3079 }
3080 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3081
3082 /*
3083 * Configure Tx/Rx MACs.
3084 * - Auto-padding for short frames.
3085 * - Enable CRC generation.
3086 * Actual reconfiguration of MAC for resolved speed/duplex
3087 * is followed after detection of link establishment.
3088 * AR813x/AR815x always does checksum computation regardless
3089 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
3090 * have bug in protocol field in Rx return structure so
3091 * these controllers can't handle fragmented frames. Disable
3092 * Rx checksum offloading until there is a newer controller
3093 * that has sane implementation.
3094 */
3095 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
3096 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
3097 MAC_CFG_PREAMBLE_MASK);
3098 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
3099 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 ||
3100 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 ||
3101 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2)
3102 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
3103 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
3104 reg |= MAC_CFG_SPEED_10_100;
3105 else
3106 reg |= MAC_CFG_SPEED_1000;
3107 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3108
3109 /* Set up the receive filter. */
3110 alc_iff(sc);
3111 alc_rxvlan(sc);
3112
3113 /* Acknowledge all pending interrupts and clear it. */
3114 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
3115 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3116 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
3117
3118 sc->alc_flags &= ~ALC_FLAG_LINK;
3119 /* Switch to the current media. */
3120 mii = &sc->sc_miibus;
3121 mii_mediachg(mii);
3122
3123 callout_schedule(&sc->sc_tick_ch, hz);
3124
3125 ifp->if_flags |= IFF_RUNNING;
3126 ifp->if_flags &= ~IFF_OACTIVE;
3127
3128 return (0);
3129 }
3130
3131 static void
alc_stop(struct ifnet * ifp,int disable)3132 alc_stop(struct ifnet *ifp, int disable)
3133 {
3134 struct alc_softc *sc = ifp->if_softc;
3135 struct alc_txdesc *txd;
3136 struct alc_rxdesc *rxd;
3137 uint32_t reg;
3138 int i;
3139
3140 callout_stop(&sc->sc_tick_ch);
3141
3142 /*
3143 * Mark the interface down and cancel the watchdog timer.
3144 */
3145 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3146 ifp->if_timer = 0;
3147
3148 sc->alc_flags &= ~ALC_FLAG_LINK;
3149
3150 alc_stats_update(sc);
3151
3152 mii_down(&sc->sc_miibus);
3153
3154 /* Disable interrupts. */
3155 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
3156 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3157
3158 /* Disable DMA. */
3159 reg = CSR_READ_4(sc, ALC_DMA_CFG);
3160 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
3161 reg |= DMA_CFG_SMB_DIS;
3162 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3163 DELAY(1000);
3164
3165 /* Stop Rx/Tx MACs. */
3166 alc_stop_mac(sc);
3167
3168 /* Disable interrupts which might be touched in taskq handler. */
3169 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3170
3171 /* Disable L0s/L1s */
3172 alc_aspm(sc, 0, IFM_UNKNOWN);
3173
3174 /* Reclaim Rx buffers that have been processed. */
3175 if (sc->alc_cdata.alc_rxhead != NULL)
3176 m_freem(sc->alc_cdata.alc_rxhead);
3177 ALC_RXCHAIN_RESET(sc);
3178 /*
3179 * Free Tx/Rx mbufs still in the queues.
3180 */
3181 for (i = 0; i < ALC_RX_RING_CNT; i++) {
3182 rxd = &sc->alc_cdata.alc_rxdesc[i];
3183 if (rxd->rx_m != NULL) {
3184 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0,
3185 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
3186 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap);
3187 m_freem(rxd->rx_m);
3188 rxd->rx_m = NULL;
3189 }
3190 }
3191 for (i = 0; i < ALC_TX_RING_CNT; i++) {
3192 txd = &sc->alc_cdata.alc_txdesc[i];
3193 if (txd->tx_m != NULL) {
3194 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0,
3195 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
3196 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap);
3197 m_freem(txd->tx_m);
3198 txd->tx_m = NULL;
3199 }
3200 }
3201 }
3202
3203 static void
alc_stop_mac(struct alc_softc * sc)3204 alc_stop_mac(struct alc_softc *sc)
3205 {
3206 uint32_t reg;
3207 int i;
3208
3209 alc_stop_queue(sc);
3210 /* Disable Rx/Tx MAC. */
3211 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3212 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
3213 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
3214 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3215 }
3216 for (i = ALC_TIMEOUT; i > 0; i--) {
3217 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3218 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0)
3219 break;
3220 DELAY(10);
3221 }
3222 if (i == 0)
3223 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n",
3224 device_xname(sc->sc_dev), reg);
3225 }
3226
3227 static void
alc_start_queue(struct alc_softc * sc)3228 alc_start_queue(struct alc_softc *sc)
3229 {
3230 uint32_t qcfg[] = {
3231 0,
3232 RXQ_CFG_QUEUE0_ENB,
3233 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB,
3234 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB,
3235 RXQ_CFG_ENB
3236 };
3237 uint32_t cfg;
3238
3239 /* Enable RxQ. */
3240 cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
3241 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
3242 cfg &= ~RXQ_CFG_ENB;
3243 cfg |= qcfg[1];
3244 } else
3245 cfg |= RXQ_CFG_QUEUE0_ENB;
3246 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
3247 /* Enable TxQ. */
3248 cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
3249 cfg |= TXQ_CFG_ENB;
3250 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
3251 }
3252
3253 static void
alc_stop_queue(struct alc_softc * sc)3254 alc_stop_queue(struct alc_softc *sc)
3255 {
3256 uint32_t reg;
3257 int i;
3258
3259 /* Disable RxQ. */
3260 reg = CSR_READ_4(sc, ALC_RXQ_CFG);
3261 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
3262 if ((reg & RXQ_CFG_ENB) != 0) {
3263 reg &= ~RXQ_CFG_ENB;
3264 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3265 }
3266 } else {
3267 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) {
3268 reg &= ~RXQ_CFG_QUEUE0_ENB;
3269 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3270 }
3271 }
3272 /* Disable TxQ. */
3273 reg = CSR_READ_4(sc, ALC_TXQ_CFG);
3274 if ((reg & TXQ_CFG_ENB) != 0) {
3275 reg &= ~TXQ_CFG_ENB;
3276 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
3277 }
3278 DELAY(40);
3279 for (i = ALC_TIMEOUT; i > 0; i--) {
3280 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3281 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
3282 break;
3283 DELAY(10);
3284 }
3285 if (i == 0)
3286 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n",
3287 device_xname(sc->sc_dev), reg);
3288 }
3289
3290 static void
alc_init_tx_ring(struct alc_softc * sc)3291 alc_init_tx_ring(struct alc_softc *sc)
3292 {
3293 struct alc_ring_data *rd;
3294 struct alc_txdesc *txd;
3295 int i;
3296
3297 sc->alc_cdata.alc_tx_prod = 0;
3298 sc->alc_cdata.alc_tx_cons = 0;
3299 sc->alc_cdata.alc_tx_cnt = 0;
3300
3301 rd = &sc->alc_rdata;
3302 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ);
3303 for (i = 0; i < ALC_TX_RING_CNT; i++) {
3304 txd = &sc->alc_cdata.alc_txdesc[i];
3305 txd->tx_m = NULL;
3306 }
3307
3308 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
3309 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
3310 }
3311
3312 static int
alc_init_rx_ring(struct alc_softc * sc,bool init)3313 alc_init_rx_ring(struct alc_softc *sc, bool init)
3314 {
3315 struct alc_ring_data *rd;
3316 struct alc_rxdesc *rxd;
3317 int i;
3318
3319 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1;
3320 rd = &sc->alc_rdata;
3321 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ);
3322 for (i = 0; i < ALC_RX_RING_CNT; i++) {
3323 rxd = &sc->alc_cdata.alc_rxdesc[i];
3324 rxd->rx_m = NULL;
3325 rxd->rx_desc = &rd->alc_rx_ring[i];
3326 if (alc_newbuf(sc, rxd, init) != 0)
3327 return (ENOBUFS);
3328 }
3329
3330 /*
3331 * Since controller does not update Rx descriptors, driver
3332 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE
3333 * is enough to ensure coherence.
3334 */
3335 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0,
3336 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
3337 /* Let controller know availability of new Rx buffers. */
3338 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
3339
3340 return (0);
3341 }
3342
3343 static void
alc_init_rr_ring(struct alc_softc * sc)3344 alc_init_rr_ring(struct alc_softc *sc)
3345 {
3346 struct alc_ring_data *rd;
3347
3348 sc->alc_cdata.alc_rr_cons = 0;
3349 ALC_RXCHAIN_RESET(sc);
3350
3351 rd = &sc->alc_rdata;
3352 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ);
3353 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0,
3354 sc->alc_cdata.alc_rr_ring_map->dm_mapsize,
3355 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3356 }
3357
3358 static void
alc_init_cmb(struct alc_softc * sc)3359 alc_init_cmb(struct alc_softc *sc)
3360 {
3361 struct alc_ring_data *rd;
3362
3363 rd = &sc->alc_rdata;
3364 memset(rd->alc_cmb, 0, ALC_CMB_SZ);
3365 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
3366 sc->alc_cdata.alc_cmb_map->dm_mapsize,
3367 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3368 }
3369
3370 static void
alc_init_smb(struct alc_softc * sc)3371 alc_init_smb(struct alc_softc *sc)
3372 {
3373 struct alc_ring_data *rd;
3374
3375 rd = &sc->alc_rdata;
3376 memset(rd->alc_smb, 0, ALC_SMB_SZ);
3377 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
3378 sc->alc_cdata.alc_smb_map->dm_mapsize,
3379 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3380 }
3381
3382 static void
alc_rxvlan(struct alc_softc * sc)3383 alc_rxvlan(struct alc_softc *sc)
3384 {
3385 uint32_t reg;
3386
3387 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3388 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING)
3389 reg |= MAC_CFG_VLAN_TAG_STRIP;
3390 else
3391 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3392 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3393 }
3394
3395 static void
alc_iff(struct alc_softc * sc)3396 alc_iff(struct alc_softc *sc)
3397 {
3398 struct ethercom *ec = &sc->sc_ec;
3399 struct ifnet *ifp = &ec->ec_if;
3400 struct ether_multi *enm;
3401 struct ether_multistep step;
3402 uint32_t crc;
3403 uint32_t mchash[2];
3404 uint32_t rxcfg;
3405
3406 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
3407 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3408 ifp->if_flags &= ~IFF_ALLMULTI;
3409
3410 /*
3411 * Always accept broadcast frames.
3412 */
3413 rxcfg |= MAC_CFG_BCAST;
3414
3415 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) {
3416 ifp->if_flags |= IFF_ALLMULTI;
3417 if (ifp->if_flags & IFF_PROMISC)
3418 rxcfg |= MAC_CFG_PROMISC;
3419 else
3420 rxcfg |= MAC_CFG_ALLMULTI;
3421 mchash[0] = mchash[1] = 0xFFFFFFFF;
3422 } else {
3423 /* Program new filter. */
3424 memset(mchash, 0, sizeof(mchash));
3425
3426 ETHER_FIRST_MULTI(step, ec, enm);
3427 while (enm != NULL) {
3428 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
3429 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3430 ETHER_NEXT_MULTI(step, enm);
3431 }
3432 }
3433
3434 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
3435 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
3436 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
3437 }
3438
3439 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci");
3440
3441 #ifdef _MODULE
3442 #include "ioconf.c"
3443 #endif
3444
3445 static int
if_alc_modcmd(modcmd_t cmd,void * opaque)3446 if_alc_modcmd(modcmd_t cmd, void *opaque)
3447 {
3448 int error = 0;
3449
3450 switch (cmd) {
3451 case MODULE_CMD_INIT:
3452 #ifdef _MODULE
3453 error = config_init_component(cfdriver_ioconf_if_alc,
3454 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc);
3455 #endif
3456 return error;
3457 case MODULE_CMD_FINI:
3458 #ifdef _MODULE
3459 error = config_fini_component(cfdriver_ioconf_if_alc,
3460 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc);
3461 #endif
3462 return error;
3463 default:
3464 return ENOTTY;
3465 }
3466 }
3467