1 /* $NetBSD: if_iwn.c,v 1.78 2016/06/10 13:27:14 ozaki-r Exp $ */
2 /* $OpenBSD: if_iwn.c,v 1.135 2014/09/10 07:22:09 dcoppa Exp $ */
3
4 /*-
5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /*
21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network
22 * adapters.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.78 2016/06/10 13:27:14 ozaki-r Exp $");
26
27 #define IWN_USE_RBUF /* Use local storage for RX */
28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */
29
30 #include <sys/param.h>
31 #include <sys/sockio.h>
32 #include <sys/proc.h>
33 #include <sys/mbuf.h>
34 #include <sys/kernel.h>
35 #include <sys/socket.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #ifdef notyetMODULE
39 #include <sys/module.h>
40 #endif
41 #include <sys/mutex.h>
42 #include <sys/conf.h>
43 #include <sys/kauth.h>
44 #include <sys/callout.h>
45
46 #include <dev/sysmon/sysmonvar.h>
47
48 #include <sys/bus.h>
49 #include <machine/endian.h>
50 #include <machine/intr.h>
51
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pcidevs.h>
55
56 #include <net/bpf.h>
57 #include <net/if.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62
63 #include <netinet/in.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in_var.h>
66 #include <net/if_ether.h>
67 #include <netinet/ip.h>
68
69 #include <net80211/ieee80211_var.h>
70 #include <net80211/ieee80211_amrr.h>
71 #include <net80211/ieee80211_radiotap.h>
72
73 #include <dev/firmload.h>
74
75 #include <dev/pci/if_iwnreg.h>
76 #include <dev/pci/if_iwnvar.h>
77
78 static const pci_product_id_t iwn_devices[] = {
79 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1,
80 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2,
81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1,
82 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2,
83 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3,
84 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4,
85 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1,
86 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2,
87 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1,
88 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2,
89 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1,
90 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2,
91 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1,
92 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2,
93 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1,
94 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2,
95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1,
96 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2,
97 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1,
98 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2,
99 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1,
100 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2,
101 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1,
102 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2,
103 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1,
104 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2,
105 PCI_PRODUCT_INTEL_WIFI_LINK_6235,
106 PCI_PRODUCT_INTEL_WIFI_LINK_6235_2,
107 PCI_PRODUCT_INTEL_WIFI_LINK_100_1,
108 PCI_PRODUCT_INTEL_WIFI_LINK_100_2,
109 PCI_PRODUCT_INTEL_WIFI_LINK_130_1,
110 PCI_PRODUCT_INTEL_WIFI_LINK_130_2,
111 PCI_PRODUCT_INTEL_WIFI_LINK_2230_1,
112 PCI_PRODUCT_INTEL_WIFI_LINK_2230_2,
113 PCI_PRODUCT_INTEL_WIFI_LINK_2200_1,
114 PCI_PRODUCT_INTEL_WIFI_LINK_2200_2,
115 PCI_PRODUCT_INTEL_WIFI_LINK_135_1,
116 PCI_PRODUCT_INTEL_WIFI_LINK_135_2,
117 PCI_PRODUCT_INTEL_WIFI_LINK_105_1,
118 PCI_PRODUCT_INTEL_WIFI_LINK_105_2,
119 };
120
121 /*
122 * Supported rates for 802.11a/b/g modes (in 500Kbps unit).
123 */
124 static const struct ieee80211_rateset iwn_rateset_11a =
125 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } };
126
127 static const struct ieee80211_rateset iwn_rateset_11b =
128 { 4, { 2, 4, 11, 22 } };
129
130 static const struct ieee80211_rateset iwn_rateset_11g =
131 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
132
133 static int iwn_match(device_t , struct cfdata *, void *);
134 static void iwn_attach(device_t , device_t , void *);
135 static int iwn4965_attach(struct iwn_softc *, pci_product_id_t);
136 static int iwn5000_attach(struct iwn_softc *, pci_product_id_t);
137 static void iwn_radiotap_attach(struct iwn_softc *);
138 static int iwn_detach(device_t , int);
139 #if 0
140 static void iwn_power(int, void *);
141 #endif
142 static bool iwn_resume(device_t, const pmf_qual_t *);
143 static int iwn_nic_lock(struct iwn_softc *);
144 static int iwn_eeprom_lock(struct iwn_softc *);
145 static int iwn_init_otprom(struct iwn_softc *);
146 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);
147 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *,
148 void **, bus_size_t, bus_size_t);
149 static void iwn_dma_contig_free(struct iwn_dma_info *);
150 static int iwn_alloc_sched(struct iwn_softc *);
151 static void iwn_free_sched(struct iwn_softc *);
152 static int iwn_alloc_kw(struct iwn_softc *);
153 static void iwn_free_kw(struct iwn_softc *);
154 static int iwn_alloc_ict(struct iwn_softc *);
155 static void iwn_free_ict(struct iwn_softc *);
156 static int iwn_alloc_fwmem(struct iwn_softc *);
157 static void iwn_free_fwmem(struct iwn_softc *);
158 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
159 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
160 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
161 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *,
162 int);
163 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
164 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
165 static void iwn5000_ict_reset(struct iwn_softc *);
166 static int iwn_read_eeprom(struct iwn_softc *);
167 static void iwn4965_read_eeprom(struct iwn_softc *);
168
169 #ifdef IWN_DEBUG
170 static void iwn4965_print_power_group(struct iwn_softc *, int);
171 #endif
172 static void iwn5000_read_eeprom(struct iwn_softc *);
173 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t);
174 static void iwn_read_eeprom_enhinfo(struct iwn_softc *);
175 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *);
176 static void iwn_newassoc(struct ieee80211_node *, int);
177 static int iwn_media_change(struct ifnet *);
178 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int);
179 static void iwn_iter_func(void *, struct ieee80211_node *);
180 static void iwn_calib_timeout(void *);
181 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *,
182 struct iwn_rx_data *);
183 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *,
184 struct iwn_rx_data *);
185 #ifndef IEEE80211_NO_HT
186 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *,
187 struct iwn_rx_data *);
188 #endif
189 static void iwn5000_rx_calib_results(struct iwn_softc *,
190 struct iwn_rx_desc *, struct iwn_rx_data *);
191 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *,
192 struct iwn_rx_data *);
193 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
194 struct iwn_rx_data *);
195 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
196 struct iwn_rx_data *);
197 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int,
198 uint8_t);
199 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *);
200 static void iwn_notif_intr(struct iwn_softc *);
201 static void iwn_wakeup_intr(struct iwn_softc *);
202 static void iwn_fatal_intr(struct iwn_softc *);
203 static int iwn_intr(void *);
204 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t,
205 uint16_t);
206 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t,
207 uint16_t);
208 #ifdef notyet
209 static void iwn5000_reset_sched(struct iwn_softc *, int, int);
210 #endif
211 static int iwn_tx(struct iwn_softc *, struct mbuf *,
212 struct ieee80211_node *, int);
213 static void iwn_start(struct ifnet *);
214 static void iwn_watchdog(struct ifnet *);
215 static int iwn_ioctl(struct ifnet *, u_long, void *);
216 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int);
217 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *,
218 int);
219 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *,
220 int);
221 static int iwn_set_link_quality(struct iwn_softc *,
222 struct ieee80211_node *);
223 static int iwn_add_broadcast_node(struct iwn_softc *, int);
224 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t);
225 static int iwn_set_critical_temp(struct iwn_softc *);
226 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *);
227 static void iwn4965_power_calibration(struct iwn_softc *, int);
228 static int iwn4965_set_txpower(struct iwn_softc *, int);
229 static int iwn5000_set_txpower(struct iwn_softc *, int);
230 static int iwn4965_get_rssi(const struct iwn_rx_stat *);
231 static int iwn5000_get_rssi(const struct iwn_rx_stat *);
232 static int iwn_get_noise(const struct iwn_rx_general_stats *);
233 static int iwn4965_get_temperature(struct iwn_softc *);
234 static int iwn5000_get_temperature(struct iwn_softc *);
235 static int iwn_init_sensitivity(struct iwn_softc *);
236 static void iwn_collect_noise(struct iwn_softc *,
237 const struct iwn_rx_general_stats *);
238 static int iwn4965_init_gains(struct iwn_softc *);
239 static int iwn5000_init_gains(struct iwn_softc *);
240 static int iwn4965_set_gains(struct iwn_softc *);
241 static int iwn5000_set_gains(struct iwn_softc *);
242 static void iwn_tune_sensitivity(struct iwn_softc *,
243 const struct iwn_rx_stats *);
244 static int iwn_send_sensitivity(struct iwn_softc *);
245 static int iwn_set_pslevel(struct iwn_softc *, int, int, int);
246 static int iwn5000_runtime_calib(struct iwn_softc *);
247
248 static int iwn_config_bt_coex_bluetooth(struct iwn_softc *);
249 static int iwn_config_bt_coex_prio_table(struct iwn_softc *);
250 static int iwn_config_bt_coex_adv1(struct iwn_softc *);
251 static int iwn_config_bt_coex_adv2(struct iwn_softc *);
252
253 static int iwn_config(struct iwn_softc *);
254 static uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t,
255 uint8_t);
256 static uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t);
257 static uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t);
258 static int iwn_scan(struct iwn_softc *, uint16_t);
259 static int iwn_auth(struct iwn_softc *);
260 static int iwn_run(struct iwn_softc *);
261 #ifdef IWN_HWCRYPTO
262 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *,
263 struct ieee80211_key *);
264 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *,
265 struct ieee80211_key *);
266 #endif
267 static int iwn_wme_update(struct ieee80211com *);
268 #ifndef IEEE80211_NO_HT
269 static int iwn_ampdu_rx_start(struct ieee80211com *,
270 struct ieee80211_node *, uint8_t);
271 static void iwn_ampdu_rx_stop(struct ieee80211com *,
272 struct ieee80211_node *, uint8_t);
273 static int iwn_ampdu_tx_start(struct ieee80211com *,
274 struct ieee80211_node *, uint8_t);
275 static void iwn_ampdu_tx_stop(struct ieee80211com *,
276 struct ieee80211_node *, uint8_t);
277 static void iwn4965_ampdu_tx_start(struct iwn_softc *,
278 struct ieee80211_node *, uint8_t, uint16_t);
279 static void iwn4965_ampdu_tx_stop(struct iwn_softc *,
280 uint8_t, uint16_t);
281 static void iwn5000_ampdu_tx_start(struct iwn_softc *,
282 struct ieee80211_node *, uint8_t, uint16_t);
283 static void iwn5000_ampdu_tx_stop(struct iwn_softc *,
284 uint8_t, uint16_t);
285 #endif
286 static int iwn5000_query_calibration(struct iwn_softc *);
287 static int iwn5000_send_calibration(struct iwn_softc *);
288 static int iwn5000_send_wimax_coex(struct iwn_softc *);
289 static int iwn6000_temp_offset_calib(struct iwn_softc *);
290 static int iwn2000_temp_offset_calib(struct iwn_softc *);
291 static int iwn4965_post_alive(struct iwn_softc *);
292 static int iwn5000_post_alive(struct iwn_softc *);
293 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *,
294 int);
295 static int iwn4965_load_firmware(struct iwn_softc *);
296 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,
297 const uint8_t *, int);
298 static int iwn5000_load_firmware(struct iwn_softc *);
299 static int iwn_read_firmware_leg(struct iwn_softc *,
300 struct iwn_fw_info *);
301 static int iwn_read_firmware_tlv(struct iwn_softc *,
302 struct iwn_fw_info *, uint16_t);
303 static int iwn_read_firmware(struct iwn_softc *);
304 static int iwn_clock_wait(struct iwn_softc *);
305 static int iwn_apm_init(struct iwn_softc *);
306 static void iwn_apm_stop_master(struct iwn_softc *);
307 static void iwn_apm_stop(struct iwn_softc *);
308 static int iwn4965_nic_config(struct iwn_softc *);
309 static int iwn5000_nic_config(struct iwn_softc *);
310 static int iwn_hw_prepare(struct iwn_softc *);
311 static int iwn_hw_init(struct iwn_softc *);
312 static void iwn_hw_stop(struct iwn_softc *);
313 static int iwn_init(struct ifnet *);
314 static void iwn_stop(struct ifnet *, int);
315
316 /* XXX MCLGETI alternative */
317 static struct mbuf *MCLGETIalt(struct iwn_softc *, int,
318 struct ifnet *, u_int);
319 #ifdef IWN_USE_RBUF
320 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *);
321 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *);
322 static int iwn_alloc_rpool(struct iwn_softc *);
323 static void iwn_free_rpool(struct iwn_softc *);
324 #endif
325
326 /* XXX needed by iwn_scan */
327 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int);
328 static u_int8_t *ieee80211_add_rates(u_int8_t *,
329 const struct ieee80211_rateset *);
330 static u_int8_t *ieee80211_add_xrates(u_int8_t *,
331 const struct ieee80211_rateset *);
332
333 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *,
334 struct iwn_rx_stat *);
335
336 #ifdef IWN_DEBUG
337 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0)
338 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0)
339 int iwn_debug = 0;
340 #else
341 #define DPRINTF(x)
342 #define DPRINTFN(n, x)
343 #endif
344
345 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach,
346 iwn_detach, NULL);
347
348 static int
iwn_match(device_t parent,cfdata_t match __unused,void * aux)349 iwn_match(device_t parent, cfdata_t match __unused, void *aux)
350 {
351 struct pci_attach_args *pa = aux;
352 size_t i;
353
354 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
355 return 0;
356
357 for (i = 0; i < __arraycount(iwn_devices); i++)
358 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i])
359 return 1;
360
361 return 0;
362 }
363
364 static void
iwn_attach(device_t parent __unused,device_t self,void * aux)365 iwn_attach(device_t parent __unused, device_t self, void *aux)
366 {
367 struct iwn_softc *sc = device_private(self);
368 struct ieee80211com *ic = &sc->sc_ic;
369 struct ifnet *ifp = &sc->sc_ec.ec_if;
370 struct pci_attach_args *pa = aux;
371 const char *intrstr;
372 pci_intr_handle_t ih;
373 pcireg_t memtype, reg;
374 int i, error;
375 char intrbuf[PCI_INTRSTR_LEN];
376
377 sc->sc_dev = self;
378 sc->sc_pct = pa->pa_pc;
379 sc->sc_pcitag = pa->pa_tag;
380 sc->sc_dmat = pa->pa_dmat;
381 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE);
382
383 callout_init(&sc->calib_to, 0);
384 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc);
385
386 pci_aprint_devinfo(pa, NULL);
387
388 /*
389 * Get the offset of the PCI Express Capability Structure in PCI
390 * Configuration Space.
391 */
392 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag,
393 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL);
394 if (error == 0) {
395 aprint_error_dev(self,
396 "PCIe capability structure not found!\n");
397 return;
398 }
399
400 /* Clear device-specific "PCI retry timeout" register (41h). */
401 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
402 if (reg & 0xff00)
403 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
404
405 /* Enable bus-mastering and hardware bug workaround. */
406 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */
407 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
408 reg |= PCI_COMMAND_MASTER_ENABLE;
409 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) {
410 DPRINTF(("PCIe INTx Disable set\n"));
411 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE;
412 }
413 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
414
415 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0);
416 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st,
417 &sc->sc_sh, NULL, &sc->sc_sz);
418 if (error != 0) {
419 aprint_error_dev(self, "can't map mem space\n");
420 return;
421 }
422
423 /* Install interrupt handler. */
424 if (pci_intr_map(pa, &ih) != 0) {
425 aprint_error_dev(self, "can't map interrupt\n");
426 return;
427 }
428 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf));
429 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc);
430 if (sc->sc_ih == NULL) {
431 aprint_error_dev(self, "can't establish interrupt");
432 if (intrstr != NULL)
433 aprint_error(" at %s", intrstr);
434 aprint_error("\n");
435 return;
436 }
437 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
438
439 /* Read hardware revision and attach. */
440 sc->hw_type =
441 (IWN_READ(sc, IWN_HW_REV) & IWN_HW_REV_TYPE_MASK)
442 >> IWN_HW_REV_TYPE_SHIFT;
443 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
444 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id));
445 else
446 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id));
447 if (error != 0) {
448 aprint_error_dev(self, "could not attach device\n");
449 return;
450 }
451
452 if ((error = iwn_hw_prepare(sc)) != 0) {
453 aprint_error_dev(self, "hardware not ready\n");
454 return;
455 }
456
457 /* Read MAC address, channels, etc from EEPROM. */
458 if ((error = iwn_read_eeprom(sc)) != 0) {
459 aprint_error_dev(self, "could not read EEPROM\n");
460 return;
461 }
462
463 /* Allocate DMA memory for firmware transfers. */
464 if ((error = iwn_alloc_fwmem(sc)) != 0) {
465 aprint_error_dev(self,
466 "could not allocate memory for firmware\n");
467 return;
468 }
469
470 /* Allocate "Keep Warm" page. */
471 if ((error = iwn_alloc_kw(sc)) != 0) {
472 aprint_error_dev(self, "could not allocate keep warm page\n");
473 goto fail1;
474 }
475
476 /* Allocate ICT table for 5000 Series. */
477 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
478 (error = iwn_alloc_ict(sc)) != 0) {
479 aprint_error_dev(self, "could not allocate ICT table\n");
480 goto fail2;
481 }
482
483 /* Allocate TX scheduler "rings". */
484 if ((error = iwn_alloc_sched(sc)) != 0) {
485 aprint_error_dev(self,
486 "could not allocate TX scheduler rings\n");
487 goto fail3;
488 }
489
490 #ifdef IWN_USE_RBUF
491 /* Allocate RX buffers. */
492 if ((error = iwn_alloc_rpool(sc)) != 0) {
493 aprint_error_dev(self, "could not allocate RX buffers\n");
494 goto fail3;
495 }
496 #endif
497
498 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */
499 for (i = 0; i < sc->ntxqs; i++) {
500 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) {
501 aprint_error_dev(self,
502 "could not allocate TX ring %d\n", i);
503 goto fail4;
504 }
505 }
506
507 /* Allocate RX ring. */
508 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) {
509 aprint_error_dev(self, "could not allocate RX ring\n");
510 goto fail4;
511 }
512
513 /* Clear pending interrupts. */
514 IWN_WRITE(sc, IWN_INT, 0xffffffff);
515
516 /* Count the number of available chains. */
517 sc->ntxchains =
518 ((sc->txchainmask >> 2) & 1) +
519 ((sc->txchainmask >> 1) & 1) +
520 ((sc->txchainmask >> 0) & 1);
521 sc->nrxchains =
522 ((sc->rxchainmask >> 2) & 1) +
523 ((sc->rxchainmask >> 1) & 1) +
524 ((sc->rxchainmask >> 0) & 1);
525 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n",
526 sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
527 ether_sprintf(ic->ic_myaddr));
528
529 ic->ic_ifp = ifp;
530 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
531 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
532 ic->ic_state = IEEE80211_S_INIT;
533
534 /* Set device capabilities. */
535 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN,
536 * and IEEE80211_C_PMGT too. */
537 ic->ic_caps =
538 IEEE80211_C_IBSS | /* IBSS mode support */
539 IEEE80211_C_WPA | /* 802.11i */
540 IEEE80211_C_MONITOR | /* monitor mode supported */
541 IEEE80211_C_TXPMGT | /* tx power management */
542 IEEE80211_C_SHSLOT | /* short slot time supported */
543 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
544 IEEE80211_C_WME; /* 802.11e */
545
546 #ifndef IEEE80211_NO_HT
547 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
548 /* Set HT capabilities. */
549 ic->ic_htcaps =
550 #if IWN_RBUF_SIZE == 8192
551 IEEE80211_HTCAP_AMSDU7935 |
552 #endif
553 IEEE80211_HTCAP_CBW20_40 |
554 IEEE80211_HTCAP_SGI20 |
555 IEEE80211_HTCAP_SGI40;
556 if (sc->hw_type != IWN_HW_REV_TYPE_4965)
557 ic->ic_htcaps |= IEEE80211_HTCAP_GF;
558 if (sc->hw_type == IWN_HW_REV_TYPE_6050)
559 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN;
560 else
561 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS;
562 }
563 #endif /* !IEEE80211_NO_HT */
564
565 /* Set supported legacy rates. */
566 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b;
567 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g;
568 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) {
569 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a;
570 }
571 #ifndef IEEE80211_NO_HT
572 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
573 /* Set supported HT rates. */
574 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */
575 if (sc->nrxchains > 1)
576 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */
577 if (sc->nrxchains > 2)
578 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */
579 }
580 #endif
581
582 /* IBSS channel undefined for now. */
583 ic->ic_ibss_chan = &ic->ic_channels[0];
584
585 ifp->if_softc = sc;
586 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
587 ifp->if_init = iwn_init;
588 ifp->if_ioctl = iwn_ioctl;
589 ifp->if_start = iwn_start;
590 ifp->if_stop = iwn_stop;
591 ifp->if_watchdog = iwn_watchdog;
592 IFQ_SET_READY(&ifp->if_snd);
593 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
594
595 if_attach(ifp);
596 ieee80211_ifattach(ic);
597 ic->ic_node_alloc = iwn_node_alloc;
598 ic->ic_newassoc = iwn_newassoc;
599 #ifdef IWN_HWCRYPTO
600 ic->ic_crypto.cs_key_set = iwn_set_key;
601 ic->ic_crypto.cs_key_delete = iwn_delete_key;
602 #endif
603 ic->ic_wme.wme_update = iwn_wme_update;
604 #ifndef IEEE80211_NO_HT
605 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
606 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
607 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start;
608 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop;
609 #endif
610
611 /* Override 802.11 state transition machine. */
612 sc->sc_newstate = ic->ic_newstate;
613 ic->ic_newstate = iwn_newstate;
614 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status);
615
616 sc->amrr.amrr_min_success_threshold = 1;
617 sc->amrr.amrr_max_success_threshold = 15;
618
619 iwn_radiotap_attach(sc);
620
621 /*
622 * XXX for NetBSD, OpenBSD timeout_set replaced by
623 * callout_init and callout_setfunc, above.
624 */
625
626 if (pmf_device_register(self, NULL, iwn_resume))
627 pmf_class_network_register(self, ifp);
628 else
629 aprint_error_dev(self, "couldn't establish power handler\n");
630
631 /* XXX NetBSD add call to ieee80211_announce for dmesg. */
632 ieee80211_announce(ic);
633
634 return;
635
636 /* Free allocated memory if something failed during attachment. */
637 fail4: while (--i >= 0)
638 iwn_free_tx_ring(sc, &sc->txq[i]);
639 #ifdef IWN_USE_RBUF
640 iwn_free_rpool(sc);
641 #endif
642 iwn_free_sched(sc);
643 fail3: if (sc->ict != NULL)
644 iwn_free_ict(sc);
645 fail2: iwn_free_kw(sc);
646 fail1: iwn_free_fwmem(sc);
647 }
648
649 int
iwn4965_attach(struct iwn_softc * sc,pci_product_id_t pid)650 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid)
651 {
652 struct iwn_ops *ops = &sc->ops;
653
654 ops->load_firmware = iwn4965_load_firmware;
655 ops->read_eeprom = iwn4965_read_eeprom;
656 ops->post_alive = iwn4965_post_alive;
657 ops->nic_config = iwn4965_nic_config;
658 ops->config_bt_coex = iwn_config_bt_coex_bluetooth;
659 ops->update_sched = iwn4965_update_sched;
660 ops->get_temperature = iwn4965_get_temperature;
661 ops->get_rssi = iwn4965_get_rssi;
662 ops->set_txpower = iwn4965_set_txpower;
663 ops->init_gains = iwn4965_init_gains;
664 ops->set_gains = iwn4965_set_gains;
665 ops->add_node = iwn4965_add_node;
666 ops->tx_done = iwn4965_tx_done;
667 #ifndef IEEE80211_NO_HT
668 ops->ampdu_tx_start = iwn4965_ampdu_tx_start;
669 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop;
670 #endif
671 sc->ntxqs = IWN4965_NTXQUEUES;
672 sc->ndmachnls = IWN4965_NDMACHNLS;
673 sc->broadcast_id = IWN4965_ID_BROADCAST;
674 sc->rxonsz = IWN4965_RXONSZ;
675 sc->schedsz = IWN4965_SCHEDSZ;
676 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ;
677 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ;
678 sc->fwsz = IWN4965_FWSZ;
679 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT;
680 sc->limits = &iwn4965_sensitivity_limits;
681 sc->fwname = "iwlwifi-4965-2.ucode";
682 /* Override chains masks, ROM is known to be broken. */
683 sc->txchainmask = IWN_ANT_AB;
684 sc->rxchainmask = IWN_ANT_ABC;
685
686 return 0;
687 }
688
689 int
iwn5000_attach(struct iwn_softc * sc,pci_product_id_t pid)690 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid)
691 {
692 struct iwn_ops *ops = &sc->ops;
693
694 ops->load_firmware = iwn5000_load_firmware;
695 ops->read_eeprom = iwn5000_read_eeprom;
696 ops->post_alive = iwn5000_post_alive;
697 ops->nic_config = iwn5000_nic_config;
698 ops->config_bt_coex = iwn_config_bt_coex_bluetooth;
699 ops->update_sched = iwn5000_update_sched;
700 ops->get_temperature = iwn5000_get_temperature;
701 ops->get_rssi = iwn5000_get_rssi;
702 ops->set_txpower = iwn5000_set_txpower;
703 ops->init_gains = iwn5000_init_gains;
704 ops->set_gains = iwn5000_set_gains;
705 ops->add_node = iwn5000_add_node;
706 ops->tx_done = iwn5000_tx_done;
707 #ifndef IEEE80211_NO_HT
708 ops->ampdu_tx_start = iwn5000_ampdu_tx_start;
709 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop;
710 #endif
711 sc->ntxqs = IWN5000_NTXQUEUES;
712 sc->ndmachnls = IWN5000_NDMACHNLS;
713 sc->broadcast_id = IWN5000_ID_BROADCAST;
714 sc->rxonsz = IWN5000_RXONSZ;
715 sc->schedsz = IWN5000_SCHEDSZ;
716 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ;
717 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ;
718 sc->fwsz = IWN5000_FWSZ;
719 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT;
720
721 switch (sc->hw_type) {
722 case IWN_HW_REV_TYPE_5100:
723 sc->limits = &iwn5000_sensitivity_limits;
724 sc->fwname = "iwlwifi-5000-2.ucode";
725 /* Override chains masks, ROM is known to be broken. */
726 sc->txchainmask = IWN_ANT_B;
727 sc->rxchainmask = IWN_ANT_AB;
728 break;
729 case IWN_HW_REV_TYPE_5150:
730 sc->limits = &iwn5150_sensitivity_limits;
731 sc->fwname = "iwlwifi-5150-2.ucode";
732 break;
733 case IWN_HW_REV_TYPE_5300:
734 case IWN_HW_REV_TYPE_5350:
735 sc->limits = &iwn5000_sensitivity_limits;
736 sc->fwname = "iwlwifi-5000-2.ucode";
737 break;
738 case IWN_HW_REV_TYPE_1000:
739 sc->limits = &iwn1000_sensitivity_limits;
740 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_1 ||
741 pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_2)
742 sc->fwname = "iwlwifi-100-5.ucode";
743 else
744 sc->fwname = "iwlwifi-1000-3.ucode";
745 break;
746 case IWN_HW_REV_TYPE_6000:
747 sc->limits = &iwn6000_sensitivity_limits;
748 sc->fwname = "iwlwifi-6000-4.ucode";
749 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 ||
750 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) {
751 sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
752 /* Override chains masks, ROM is known to be broken. */
753 sc->txchainmask = IWN_ANT_BC;
754 sc->rxchainmask = IWN_ANT_BC;
755 }
756 break;
757 case IWN_HW_REV_TYPE_6050:
758 sc->limits = &iwn6000_sensitivity_limits;
759 sc->fwname = "iwlwifi-6050-5.ucode";
760 break;
761 case IWN_HW_REV_TYPE_6005:
762 sc->limits = &iwn6000_sensitivity_limits;
763 /* Type 6030 cards return IWN_HW_REV_TYPE_6005 */
764 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_1 ||
765 pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_2 ||
766 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_1 ||
767 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_2 ||
768 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235 ||
769 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235_2) {
770 sc->fwname = "iwlwifi-6000g2b-6.ucode";
771 ops->config_bt_coex = iwn_config_bt_coex_adv1;
772 }
773 else
774 sc->fwname = "iwlwifi-6000g2a-5.ucode";
775 break;
776 case IWN_HW_REV_TYPE_2030:
777 sc->limits = &iwn2000_sensitivity_limits;
778 sc->fwname = "iwlwifi-2030-6.ucode";
779 ops->config_bt_coex = iwn_config_bt_coex_adv2;
780 break;
781 case IWN_HW_REV_TYPE_2000:
782 sc->limits = &iwn2000_sensitivity_limits;
783 sc->fwname = "iwlwifi-2000-6.ucode";
784 break;
785 case IWN_HW_REV_TYPE_135:
786 sc->limits = &iwn2000_sensitivity_limits;
787 sc->fwname = "iwlwifi-135-6.ucode";
788 ops->config_bt_coex = iwn_config_bt_coex_adv2;
789 break;
790 case IWN_HW_REV_TYPE_105:
791 sc->limits = &iwn2000_sensitivity_limits;
792 sc->fwname = "iwlwifi-105-6.ucode";
793 break;
794 default:
795 aprint_normal(": adapter type %d not supported\n", sc->hw_type);
796 return ENOTSUP;
797 }
798 return 0;
799 }
800
801 /*
802 * Attach the interface to 802.11 radiotap.
803 */
804 static void
iwn_radiotap_attach(struct iwn_softc * sc)805 iwn_radiotap_attach(struct iwn_softc *sc)
806 {
807 struct ifnet *ifp = sc->sc_ic.ic_ifp;
808
809 bpf_attach2(ifp, DLT_IEEE802_11_RADIO,
810 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN,
811 &sc->sc_drvbpf);
812
813 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
814 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
815 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT);
816
817 sc->sc_txtap_len = sizeof sc->sc_txtapu;
818 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
819 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT);
820 }
821
822 static int
iwn_detach(device_t self,int flags __unused)823 iwn_detach(device_t self, int flags __unused)
824 {
825 struct iwn_softc *sc = device_private(self);
826 struct ifnet *ifp = sc->sc_ic.ic_ifp;
827 int qid;
828
829 callout_stop(&sc->calib_to);
830
831 /* Uninstall interrupt handler. */
832 if (sc->sc_ih != NULL)
833 pci_intr_disestablish(sc->sc_pct, sc->sc_ih);
834
835 /* Free DMA resources. */
836 iwn_free_rx_ring(sc, &sc->rxq);
837 for (qid = 0; qid < sc->ntxqs; qid++)
838 iwn_free_tx_ring(sc, &sc->txq[qid]);
839 #ifdef IWN_USE_RBUF
840 iwn_free_rpool(sc);
841 #endif
842 iwn_free_sched(sc);
843 iwn_free_kw(sc);
844 if (sc->ict != NULL)
845 iwn_free_ict(sc);
846 iwn_free_fwmem(sc);
847
848 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz);
849
850 ieee80211_ifdetach(&sc->sc_ic);
851 if_detach(ifp);
852
853 return 0;
854 }
855
856 #if 0
857 /*
858 * XXX Investigate if clearing the PCI retry timeout could eliminate
859 * the repeated scan calls. Also the calls to if_init and if_start
860 * are similar to the effect of adding the call to ifioctl_common .
861 */
862 static void
863 iwn_power(int why, void *arg)
864 {
865 struct iwn_softc *sc = arg;
866 struct ifnet *ifp;
867 pcireg_t reg;
868 int s;
869
870 if (why != PWR_RESUME)
871 return;
872
873 /* Clear device-specific "PCI retry timeout" register (41h). */
874 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
875 if (reg & 0xff00)
876 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
877
878 s = splnet();
879 ifp = &sc->sc_ic.ic_if;
880 if (ifp->if_flags & IFF_UP) {
881 ifp->if_init(ifp);
882 if (ifp->if_flags & IFF_RUNNING)
883 ifp->if_start(ifp);
884 }
885 splx(s);
886 }
887 #endif
888
889 static bool
iwn_resume(device_t dv,const pmf_qual_t * qual)890 iwn_resume(device_t dv, const pmf_qual_t *qual)
891 {
892 return true;
893 }
894
895 static int
iwn_nic_lock(struct iwn_softc * sc)896 iwn_nic_lock(struct iwn_softc *sc)
897 {
898 int ntries;
899
900 /* Request exclusive access to NIC. */
901 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
902
903 /* Spin until we actually get the lock. */
904 for (ntries = 0; ntries < 1000; ntries++) {
905 if ((IWN_READ(sc, IWN_GP_CNTRL) &
906 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) ==
907 IWN_GP_CNTRL_MAC_ACCESS_ENA)
908 return 0;
909 DELAY(10);
910 }
911 return ETIMEDOUT;
912 }
913
914 static __inline void
iwn_nic_unlock(struct iwn_softc * sc)915 iwn_nic_unlock(struct iwn_softc *sc)
916 {
917 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
918 }
919
920 static __inline uint32_t
iwn_prph_read(struct iwn_softc * sc,uint32_t addr)921 iwn_prph_read(struct iwn_softc *sc, uint32_t addr)
922 {
923 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr);
924 IWN_BARRIER_READ_WRITE(sc);
925 return IWN_READ(sc, IWN_PRPH_RDATA);
926 }
927
928 static __inline void
iwn_prph_write(struct iwn_softc * sc,uint32_t addr,uint32_t data)929 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
930 {
931 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr);
932 IWN_BARRIER_WRITE(sc);
933 IWN_WRITE(sc, IWN_PRPH_WDATA, data);
934 }
935
936 static __inline void
iwn_prph_setbits(struct iwn_softc * sc,uint32_t addr,uint32_t mask)937 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
938 {
939 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);
940 }
941
942 static __inline void
iwn_prph_clrbits(struct iwn_softc * sc,uint32_t addr,uint32_t mask)943 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
944 {
945 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);
946 }
947
948 static __inline void
iwn_prph_write_region_4(struct iwn_softc * sc,uint32_t addr,const uint32_t * data,int count)949 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,
950 const uint32_t *data, int count)
951 {
952 for (; count > 0; count--, data++, addr += 4)
953 iwn_prph_write(sc, addr, *data);
954 }
955
956 static __inline uint32_t
iwn_mem_read(struct iwn_softc * sc,uint32_t addr)957 iwn_mem_read(struct iwn_softc *sc, uint32_t addr)
958 {
959 IWN_WRITE(sc, IWN_MEM_RADDR, addr);
960 IWN_BARRIER_READ_WRITE(sc);
961 return IWN_READ(sc, IWN_MEM_RDATA);
962 }
963
964 static __inline void
iwn_mem_write(struct iwn_softc * sc,uint32_t addr,uint32_t data)965 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
966 {
967 IWN_WRITE(sc, IWN_MEM_WADDR, addr);
968 IWN_BARRIER_WRITE(sc);
969 IWN_WRITE(sc, IWN_MEM_WDATA, data);
970 }
971
972 #ifndef IEEE80211_NO_HT
973 static __inline void
iwn_mem_write_2(struct iwn_softc * sc,uint32_t addr,uint16_t data)974 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)
975 {
976 uint32_t tmp;
977
978 tmp = iwn_mem_read(sc, addr & ~3);
979 if (addr & 3)
980 tmp = (tmp & 0x0000ffff) | data << 16;
981 else
982 tmp = (tmp & 0xffff0000) | data;
983 iwn_mem_write(sc, addr & ~3, tmp);
984 }
985 #endif
986
987 static __inline void
iwn_mem_read_region_4(struct iwn_softc * sc,uint32_t addr,uint32_t * data,int count)988 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,
989 int count)
990 {
991 for (; count > 0; count--, addr += 4)
992 *data++ = iwn_mem_read(sc, addr);
993 }
994
995 static __inline void
iwn_mem_set_region_4(struct iwn_softc * sc,uint32_t addr,uint32_t val,int count)996 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
997 int count)
998 {
999 for (; count > 0; count--, addr += 4)
1000 iwn_mem_write(sc, addr, val);
1001 }
1002
1003 static int
iwn_eeprom_lock(struct iwn_softc * sc)1004 iwn_eeprom_lock(struct iwn_softc *sc)
1005 {
1006 int i, ntries;
1007
1008 for (i = 0; i < 100; i++) {
1009 /* Request exclusive access to EEPROM. */
1010 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
1011 IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1012
1013 /* Spin until we actually get the lock. */
1014 for (ntries = 0; ntries < 100; ntries++) {
1015 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
1016 IWN_HW_IF_CONFIG_EEPROM_LOCKED)
1017 return 0;
1018 DELAY(10);
1019 }
1020 }
1021 return ETIMEDOUT;
1022 }
1023
1024 static __inline void
iwn_eeprom_unlock(struct iwn_softc * sc)1025 iwn_eeprom_unlock(struct iwn_softc *sc)
1026 {
1027 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1028 }
1029
1030 /*
1031 * Initialize access by host to One Time Programmable ROM.
1032 * NB: This kind of ROM can be found on 1000 or 6000 Series only.
1033 */
1034 static int
iwn_init_otprom(struct iwn_softc * sc)1035 iwn_init_otprom(struct iwn_softc *sc)
1036 {
1037 uint16_t prev = 0, base, next;
1038 int count, error;
1039
1040 /* Wait for clock stabilization before accessing prph. */
1041 if ((error = iwn_clock_wait(sc)) != 0)
1042 return error;
1043
1044 if ((error = iwn_nic_lock(sc)) != 0)
1045 return error;
1046 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1047 DELAY(5);
1048 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1049 iwn_nic_unlock(sc);
1050
1051 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
1052 if (sc->hw_type != IWN_HW_REV_TYPE_1000) {
1053 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT,
1054 IWN_RESET_LINK_PWR_MGMT_DIS);
1055 }
1056 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER);
1057 /* Clear ECC status. */
1058 IWN_SETBITS(sc, IWN_OTP_GP,
1059 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS);
1060
1061 /*
1062 * Find the block before last block (contains the EEPROM image)
1063 * for HW without OTP shadow RAM.
1064 */
1065 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
1066 /* Switch to absolute addressing mode. */
1067 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS);
1068 base = 0;
1069 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) {
1070 error = iwn_read_prom_data(sc, base, &next, 2);
1071 if (error != 0)
1072 return error;
1073 if (next == 0) /* End of linked-list. */
1074 break;
1075 prev = base;
1076 base = le16toh(next);
1077 }
1078 if (count == 0 || count == IWN1000_OTP_NBLOCKS)
1079 return EIO;
1080 /* Skip "next" word. */
1081 sc->prom_base = prev + 1;
1082 }
1083 return 0;
1084 }
1085
1086 static int
iwn_read_prom_data(struct iwn_softc * sc,uint32_t addr,void * data,int count)1087 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)
1088 {
1089 uint8_t *out = data;
1090 uint32_t val, tmp;
1091 int ntries;
1092
1093 addr += sc->prom_base;
1094 for (; count > 0; count -= 2, addr++) {
1095 IWN_WRITE(sc, IWN_EEPROM, addr << 2);
1096 for (ntries = 0; ntries < 10; ntries++) {
1097 val = IWN_READ(sc, IWN_EEPROM);
1098 if (val & IWN_EEPROM_READ_VALID)
1099 break;
1100 DELAY(5);
1101 }
1102 if (ntries == 10) {
1103 aprint_error_dev(sc->sc_dev,
1104 "timeout reading ROM at 0x%x\n", addr);
1105 return ETIMEDOUT;
1106 }
1107 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1108 /* OTPROM, check for ECC errors. */
1109 tmp = IWN_READ(sc, IWN_OTP_GP);
1110 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
1111 aprint_error_dev(sc->sc_dev,
1112 "OTPROM ECC error at 0x%x\n", addr);
1113 return EIO;
1114 }
1115 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
1116 /* Correctable ECC error, clear bit. */
1117 IWN_SETBITS(sc, IWN_OTP_GP,
1118 IWN_OTP_GP_ECC_CORR_STTS);
1119 }
1120 }
1121 *out++ = val >> 16;
1122 if (count > 1)
1123 *out++ = val >> 24;
1124 }
1125 return 0;
1126 }
1127
1128 static int
iwn_dma_contig_alloc(bus_dma_tag_t tag,struct iwn_dma_info * dma,void ** kvap,bus_size_t size,bus_size_t alignment)1129 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap,
1130 bus_size_t size, bus_size_t alignment)
1131 {
1132 int nsegs, error;
1133
1134 dma->tag = tag;
1135 dma->size = size;
1136
1137 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT,
1138 &dma->map);
1139 if (error != 0)
1140 goto fail;
1141
1142 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs,
1143 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */
1144 if (error != 0)
1145 goto fail;
1146
1147 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr,
1148 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */
1149 if (error != 0)
1150 goto fail;
1151
1152 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL,
1153 BUS_DMA_NOWAIT);
1154 if (error != 0)
1155 goto fail;
1156
1157 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */
1158 memset(dma->vaddr, 0, size);
1159 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE);
1160
1161 dma->paddr = dma->map->dm_segs[0].ds_addr;
1162 if (kvap != NULL)
1163 *kvap = dma->vaddr;
1164
1165 return 0;
1166
1167 fail: iwn_dma_contig_free(dma);
1168 return error;
1169 }
1170
1171 static void
iwn_dma_contig_free(struct iwn_dma_info * dma)1172 iwn_dma_contig_free(struct iwn_dma_info *dma)
1173 {
1174 if (dma->map != NULL) {
1175 if (dma->vaddr != NULL) {
1176 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size,
1177 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1178 bus_dmamap_unload(dma->tag, dma->map);
1179 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size);
1180 bus_dmamem_free(dma->tag, &dma->seg, 1);
1181 dma->vaddr = NULL;
1182 }
1183 bus_dmamap_destroy(dma->tag, dma->map);
1184 dma->map = NULL;
1185 }
1186 }
1187
1188 static int
iwn_alloc_sched(struct iwn_softc * sc)1189 iwn_alloc_sched(struct iwn_softc *sc)
1190 {
1191 /* TX scheduler rings must be aligned on a 1KB boundary. */
1192 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma,
1193 (void **)&sc->sched, sc->schedsz, 1024);
1194 }
1195
1196 static void
iwn_free_sched(struct iwn_softc * sc)1197 iwn_free_sched(struct iwn_softc *sc)
1198 {
1199 iwn_dma_contig_free(&sc->sched_dma);
1200 }
1201
1202 static int
iwn_alloc_kw(struct iwn_softc * sc)1203 iwn_alloc_kw(struct iwn_softc *sc)
1204 {
1205 /* "Keep Warm" page must be aligned on a 4KB boundary. */
1206 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096,
1207 4096);
1208 }
1209
1210 static void
iwn_free_kw(struct iwn_softc * sc)1211 iwn_free_kw(struct iwn_softc *sc)
1212 {
1213 iwn_dma_contig_free(&sc->kw_dma);
1214 }
1215
1216 static int
iwn_alloc_ict(struct iwn_softc * sc)1217 iwn_alloc_ict(struct iwn_softc *sc)
1218 {
1219 /* ICT table must be aligned on a 4KB boundary. */
1220 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma,
1221 (void **)&sc->ict, IWN_ICT_SIZE, 4096);
1222 }
1223
1224 static void
iwn_free_ict(struct iwn_softc * sc)1225 iwn_free_ict(struct iwn_softc *sc)
1226 {
1227 iwn_dma_contig_free(&sc->ict_dma);
1228 }
1229
1230 static int
iwn_alloc_fwmem(struct iwn_softc * sc)1231 iwn_alloc_fwmem(struct iwn_softc *sc)
1232 {
1233 /* Must be aligned on a 16-byte boundary. */
1234 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL,
1235 sc->fwsz, 16);
1236 }
1237
1238 static void
iwn_free_fwmem(struct iwn_softc * sc)1239 iwn_free_fwmem(struct iwn_softc *sc)
1240 {
1241 iwn_dma_contig_free(&sc->fw_dma);
1242 }
1243
1244 static int
iwn_alloc_rx_ring(struct iwn_softc * sc,struct iwn_rx_ring * ring)1245 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1246 {
1247 bus_size_t size;
1248 int i, error;
1249
1250 ring->cur = 0;
1251
1252 /* Allocate RX descriptors (256-byte aligned). */
1253 size = IWN_RX_RING_COUNT * sizeof (uint32_t);
1254 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma,
1255 (void **)&ring->desc, size, 256);
1256 if (error != 0) {
1257 aprint_error_dev(sc->sc_dev,
1258 "could not allocate RX ring DMA memory\n");
1259 goto fail;
1260 }
1261
1262 /* Allocate RX status area (16-byte aligned). */
1263 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma,
1264 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16);
1265 if (error != 0) {
1266 aprint_error_dev(sc->sc_dev,
1267 "could not allocate RX status DMA memory\n");
1268 goto fail;
1269 }
1270
1271 /*
1272 * Allocate and map RX buffers.
1273 */
1274 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1275 struct iwn_rx_data *data = &ring->data[i];
1276
1277 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1,
1278 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
1279 &data->map);
1280 if (error != 0) {
1281 aprint_error_dev(sc->sc_dev,
1282 "could not create RX buf DMA map\n");
1283 goto fail;
1284 }
1285
1286 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE);
1287 if (data->m == NULL) {
1288 aprint_error_dev(sc->sc_dev,
1289 "could not allocate RX mbuf\n");
1290 error = ENOBUFS;
1291 goto fail;
1292 }
1293
1294 error = bus_dmamap_load(sc->sc_dmat, data->map,
1295 mtod(data->m, void *), IWN_RBUF_SIZE, NULL,
1296 BUS_DMA_NOWAIT | BUS_DMA_READ);
1297 if (error != 0) {
1298 aprint_error_dev(sc->sc_dev,
1299 "can't not map mbuf (error %d)\n", error);
1300 goto fail;
1301 }
1302
1303 /* Set physical address of RX buffer (256-byte aligned). */
1304 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8);
1305 }
1306
1307 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size,
1308 BUS_DMASYNC_PREWRITE);
1309
1310 return 0;
1311
1312 fail: iwn_free_rx_ring(sc, ring);
1313 return error;
1314 }
1315
1316 static void
iwn_reset_rx_ring(struct iwn_softc * sc,struct iwn_rx_ring * ring)1317 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1318 {
1319 int ntries;
1320
1321 if (iwn_nic_lock(sc) == 0) {
1322 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
1323 for (ntries = 0; ntries < 1000; ntries++) {
1324 if (IWN_READ(sc, IWN_FH_RX_STATUS) &
1325 IWN_FH_RX_STATUS_IDLE)
1326 break;
1327 DELAY(10);
1328 }
1329 iwn_nic_unlock(sc);
1330 }
1331 ring->cur = 0;
1332 sc->last_rx_valid = 0;
1333 }
1334
1335 static void
iwn_free_rx_ring(struct iwn_softc * sc,struct iwn_rx_ring * ring)1336 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1337 {
1338 int i;
1339
1340 iwn_dma_contig_free(&ring->desc_dma);
1341 iwn_dma_contig_free(&ring->stat_dma);
1342
1343 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1344 struct iwn_rx_data *data = &ring->data[i];
1345
1346 if (data->m != NULL) {
1347 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
1348 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1349 bus_dmamap_unload(sc->sc_dmat, data->map);
1350 m_freem(data->m);
1351 }
1352 if (data->map != NULL)
1353 bus_dmamap_destroy(sc->sc_dmat, data->map);
1354 }
1355 }
1356
1357 static int
iwn_alloc_tx_ring(struct iwn_softc * sc,struct iwn_tx_ring * ring,int qid)1358 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
1359 {
1360 bus_addr_t paddr;
1361 bus_size_t size;
1362 int i, error;
1363
1364 ring->qid = qid;
1365 ring->queued = 0;
1366 ring->cur = 0;
1367
1368 /* Allocate TX descriptors (256-byte aligned). */
1369 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc);
1370 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma,
1371 (void **)&ring->desc, size, 256);
1372 if (error != 0) {
1373 aprint_error_dev(sc->sc_dev,
1374 "could not allocate TX ring DMA memory\n");
1375 goto fail;
1376 }
1377 /*
1378 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need
1379 * to allocate commands space for other rings.
1380 * XXX Do we really need to allocate descriptors for other rings?
1381 */
1382 if (qid > 4)
1383 return 0;
1384
1385 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd);
1386 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma,
1387 (void **)&ring->cmd, size, 4);
1388 if (error != 0) {
1389 aprint_error_dev(sc->sc_dev,
1390 "could not allocate TX cmd DMA memory\n");
1391 goto fail;
1392 }
1393
1394 paddr = ring->cmd_dma.paddr;
1395 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1396 struct iwn_tx_data *data = &ring->data[i];
1397
1398 data->cmd_paddr = paddr;
1399 data->scratch_paddr = paddr + 12;
1400 paddr += sizeof (struct iwn_tx_cmd);
1401
1402 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
1403 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT,
1404 &data->map);
1405 if (error != 0) {
1406 aprint_error_dev(sc->sc_dev,
1407 "could not create TX buf DMA map\n");
1408 goto fail;
1409 }
1410 }
1411 return 0;
1412
1413 fail: iwn_free_tx_ring(sc, ring);
1414 return error;
1415 }
1416
1417 static void
iwn_reset_tx_ring(struct iwn_softc * sc,struct iwn_tx_ring * ring)1418 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1419 {
1420 int i;
1421
1422 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1423 struct iwn_tx_data *data = &ring->data[i];
1424
1425 if (data->m != NULL) {
1426 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
1427 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1428 bus_dmamap_unload(sc->sc_dmat, data->map);
1429 m_freem(data->m);
1430 data->m = NULL;
1431 }
1432 }
1433 /* Clear TX descriptors. */
1434 memset(ring->desc, 0, ring->desc_dma.size);
1435 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0,
1436 ring->desc_dma.size, BUS_DMASYNC_PREWRITE);
1437 sc->qfullmsk &= ~(1 << ring->qid);
1438 ring->queued = 0;
1439 ring->cur = 0;
1440 }
1441
1442 static void
iwn_free_tx_ring(struct iwn_softc * sc,struct iwn_tx_ring * ring)1443 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1444 {
1445 int i;
1446
1447 iwn_dma_contig_free(&ring->desc_dma);
1448 iwn_dma_contig_free(&ring->cmd_dma);
1449
1450 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1451 struct iwn_tx_data *data = &ring->data[i];
1452
1453 if (data->m != NULL) {
1454 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
1455 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1456 bus_dmamap_unload(sc->sc_dmat, data->map);
1457 m_freem(data->m);
1458 }
1459 if (data->map != NULL)
1460 bus_dmamap_destroy(sc->sc_dmat, data->map);
1461 }
1462 }
1463
1464 static void
iwn5000_ict_reset(struct iwn_softc * sc)1465 iwn5000_ict_reset(struct iwn_softc *sc)
1466 {
1467 /* Disable interrupts. */
1468 IWN_WRITE(sc, IWN_INT_MASK, 0);
1469
1470 /* Reset ICT table. */
1471 memset(sc->ict, 0, IWN_ICT_SIZE);
1472 sc->ict_cur = 0;
1473
1474 /* Set physical address of ICT table (4KB aligned). */
1475 DPRINTF(("enabling ICT\n"));
1476 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
1477 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
1478
1479 /* Enable periodic RX interrupt. */
1480 sc->int_mask |= IWN_INT_RX_PERIODIC;
1481 /* Switch to ICT interrupt mode in driver. */
1482 sc->sc_flags |= IWN_FLAG_USE_ICT;
1483
1484 /* Re-enable interrupts. */
1485 IWN_WRITE(sc, IWN_INT, 0xffffffff);
1486 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
1487 }
1488
1489 static int
iwn_read_eeprom(struct iwn_softc * sc)1490 iwn_read_eeprom(struct iwn_softc *sc)
1491 {
1492 struct iwn_ops *ops = &sc->ops;
1493 struct ieee80211com *ic = &sc->sc_ic;
1494 uint16_t val;
1495 int error;
1496
1497 /* Check whether adapter has an EEPROM or an OTPROM. */
1498 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
1499 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP))
1500 sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
1501 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ?
1502 "OTPROM" : "EEPROM"));
1503
1504 /* Adapter has to be powered on for EEPROM access to work. */
1505 if ((error = iwn_apm_init(sc)) != 0) {
1506 aprint_error_dev(sc->sc_dev,
1507 "could not power ON adapter\n");
1508 return error;
1509 }
1510
1511 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) {
1512 aprint_error_dev(sc->sc_dev,
1513 "bad ROM signature\n");
1514 return EIO;
1515 }
1516 if ((error = iwn_eeprom_lock(sc)) != 0) {
1517 aprint_error_dev(sc->sc_dev,
1518 "could not lock ROM (error=%d)\n", error);
1519 return error;
1520 }
1521 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1522 if ((error = iwn_init_otprom(sc)) != 0) {
1523 aprint_error_dev(sc->sc_dev,
1524 "could not initialize OTPROM\n");
1525 return error;
1526 }
1527 }
1528
1529 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2);
1530 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val)));
1531 /* Check if HT support is bonded out. */
1532 if (val & htole16(IWN_EEPROM_SKU_CAP_11N))
1533 sc->sc_flags |= IWN_FLAG_HAS_11N;
1534
1535 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
1536 sc->rfcfg = le16toh(val);
1537 DPRINTF(("radio config=0x%04x\n", sc->rfcfg));
1538 /* Read Tx/Rx chains from ROM unless it's known to be broken. */
1539 if (sc->txchainmask == 0)
1540 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg);
1541 if (sc->rxchainmask == 0)
1542 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg);
1543
1544 /* Read MAC address. */
1545 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6);
1546
1547 /* Read adapter-specific information from EEPROM. */
1548 ops->read_eeprom(sc);
1549
1550 iwn_apm_stop(sc); /* Power OFF adapter. */
1551
1552 iwn_eeprom_unlock(sc);
1553 return 0;
1554 }
1555
1556 static void
iwn4965_read_eeprom(struct iwn_softc * sc)1557 iwn4965_read_eeprom(struct iwn_softc *sc)
1558 {
1559 uint32_t addr;
1560 uint16_t val;
1561 int i;
1562
1563 /* Read regulatory domain (4 ASCII characters). */
1564 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
1565
1566 /* Read the list of authorized channels (20MHz ones only). */
1567 for (i = 0; i < 5; i++) {
1568 addr = iwn4965_regulatory_bands[i];
1569 iwn_read_eeprom_channels(sc, i, addr);
1570 }
1571
1572 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */
1573 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
1574 sc->maxpwr2GHz = val & 0xff;
1575 sc->maxpwr5GHz = val >> 8;
1576 /* Check that EEPROM values are within valid range. */
1577 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
1578 sc->maxpwr5GHz = 38;
1579 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
1580 sc->maxpwr2GHz = 38;
1581 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz));
1582
1583 /* Read samples for each TX power group. */
1584 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
1585 sizeof sc->bands);
1586
1587 /* Read voltage at which samples were taken. */
1588 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
1589 sc->eeprom_voltage = (int16_t)le16toh(val);
1590 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage));
1591
1592 #ifdef IWN_DEBUG
1593 /* Print samples. */
1594 if (iwn_debug > 0) {
1595 for (i = 0; i < IWN_NBANDS; i++)
1596 iwn4965_print_power_group(sc, i);
1597 }
1598 #endif
1599 }
1600
1601 #ifdef IWN_DEBUG
1602 static void
iwn4965_print_power_group(struct iwn_softc * sc,int i)1603 iwn4965_print_power_group(struct iwn_softc *sc, int i)
1604 {
1605 struct iwn4965_eeprom_band *band = &sc->bands[i];
1606 struct iwn4965_eeprom_chan_samples *chans = band->chans;
1607 int j, c;
1608
1609 aprint_normal("===band %d===\n", i);
1610 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
1611 aprint_normal("chan1 num=%d\n", chans[0].num);
1612 for (c = 0; c < 2; c++) {
1613 for (j = 0; j < IWN_NSAMPLES; j++) {
1614 aprint_normal("chain %d, sample %d: temp=%d gain=%d "
1615 "power=%d pa_det=%d\n", c, j,
1616 chans[0].samples[c][j].temp,
1617 chans[0].samples[c][j].gain,
1618 chans[0].samples[c][j].power,
1619 chans[0].samples[c][j].pa_det);
1620 }
1621 }
1622 aprint_normal("chan2 num=%d\n", chans[1].num);
1623 for (c = 0; c < 2; c++) {
1624 for (j = 0; j < IWN_NSAMPLES; j++) {
1625 aprint_normal("chain %d, sample %d: temp=%d gain=%d "
1626 "power=%d pa_det=%d\n", c, j,
1627 chans[1].samples[c][j].temp,
1628 chans[1].samples[c][j].gain,
1629 chans[1].samples[c][j].power,
1630 chans[1].samples[c][j].pa_det);
1631 }
1632 }
1633 }
1634 #endif
1635
1636 static void
iwn5000_read_eeprom(struct iwn_softc * sc)1637 iwn5000_read_eeprom(struct iwn_softc *sc)
1638 {
1639 struct iwn5000_eeprom_calib_hdr hdr;
1640 int32_t volt;
1641 uint32_t base, addr;
1642 uint16_t val;
1643 int i;
1644
1645 /* Read regulatory domain (4 ASCII characters). */
1646 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1647 base = le16toh(val);
1648 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN,
1649 sc->eeprom_domain, 4);
1650
1651 /* Read the list of authorized channels (20MHz ones only). */
1652 for (i = 0; i < 5; i++) {
1653 addr = base + iwn5000_regulatory_bands[i];
1654 iwn_read_eeprom_channels(sc, i, addr);
1655 }
1656
1657 /* Read enhanced TX power information for 6000 Series. */
1658 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1659 iwn_read_eeprom_enhinfo(sc);
1660
1661 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
1662 base = le16toh(val);
1663 iwn_read_prom_data(sc, base, &hdr, sizeof hdr);
1664 DPRINTF(("calib version=%u pa type=%u voltage=%u\n",
1665 hdr.version, hdr.pa_type, le16toh(hdr.volt)));
1666 sc->calib_ver = hdr.version;
1667
1668 if (sc->hw_type == IWN_HW_REV_TYPE_2030 ||
1669 sc->hw_type == IWN_HW_REV_TYPE_2000 ||
1670 sc->hw_type == IWN_HW_REV_TYPE_135 ||
1671 sc->hw_type == IWN_HW_REV_TYPE_105) {
1672 sc->eeprom_voltage = le16toh(hdr.volt);
1673 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
1674 sc->eeprom_temp = le16toh(val);
1675 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2);
1676 sc->eeprom_rawtemp = le16toh(val);
1677 }
1678
1679 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
1680 /* Compute temperature offset. */
1681 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
1682 sc->eeprom_temp = le16toh(val);
1683 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
1684 volt = le16toh(val);
1685 sc->temp_off = sc->eeprom_temp - (volt / -5);
1686 DPRINTF(("temp=%d volt=%d offset=%dK\n",
1687 sc->eeprom_temp, volt, sc->temp_off));
1688 } else {
1689 /* Read crystal calibration. */
1690 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL,
1691 &sc->eeprom_crystal, sizeof (uint32_t));
1692 DPRINTF(("crystal calibration 0x%08x\n",
1693 le32toh(sc->eeprom_crystal)));
1694 }
1695 }
1696
1697 static void
iwn_read_eeprom_channels(struct iwn_softc * sc,int n,uint32_t addr)1698 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)
1699 {
1700 struct ieee80211com *ic = &sc->sc_ic;
1701 const struct iwn_chan_band *band = &iwn_bands[n];
1702 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND];
1703 uint8_t chan;
1704 int i;
1705
1706 iwn_read_prom_data(sc, addr, channels,
1707 band->nchan * sizeof (struct iwn_eeprom_chan));
1708
1709 for (i = 0; i < band->nchan; i++) {
1710 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID))
1711 continue;
1712
1713 chan = band->chan[i];
1714
1715 if (n == 0) { /* 2GHz band */
1716 ic->ic_channels[chan].ic_freq =
1717 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ);
1718 ic->ic_channels[chan].ic_flags =
1719 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
1720 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
1721
1722 } else { /* 5GHz band */
1723 /*
1724 * Some adapters support channels 7, 8, 11 and 12
1725 * both in the 2GHz and 4.9GHz bands.
1726 * Because of limitations in our net80211 layer,
1727 * we don't support them in the 4.9GHz band.
1728 */
1729 if (chan <= 14)
1730 continue;
1731
1732 ic->ic_channels[chan].ic_freq =
1733 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ);
1734 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A;
1735 /* We have at least one valid 5GHz channel. */
1736 sc->sc_flags |= IWN_FLAG_HAS_5GHZ;
1737 }
1738
1739 /* Is active scan allowed on this channel? */
1740 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) {
1741 ic->ic_channels[chan].ic_flags |=
1742 IEEE80211_CHAN_PASSIVE;
1743 }
1744
1745 /* Save maximum allowed TX power for this channel. */
1746 sc->maxpwr[chan] = channels[i].maxpwr;
1747
1748 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n",
1749 chan, channels[i].flags, sc->maxpwr[chan]));
1750 }
1751 }
1752
1753 static void
iwn_read_eeprom_enhinfo(struct iwn_softc * sc)1754 iwn_read_eeprom_enhinfo(struct iwn_softc *sc)
1755 {
1756 struct iwn_eeprom_enhinfo enhinfo[35];
1757 uint16_t val, base;
1758 int8_t maxpwr;
1759 int i;
1760
1761 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1762 base = le16toh(val);
1763 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO,
1764 enhinfo, sizeof enhinfo);
1765
1766 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr);
1767 for (i = 0; i < __arraycount(enhinfo); i++) {
1768 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0)
1769 continue; /* Skip invalid entries. */
1770
1771 maxpwr = 0;
1772 if (sc->txchainmask & IWN_ANT_A)
1773 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]);
1774 if (sc->txchainmask & IWN_ANT_B)
1775 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]);
1776 if (sc->txchainmask & IWN_ANT_C)
1777 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]);
1778 if (sc->ntxchains == 2)
1779 maxpwr = MAX(maxpwr, enhinfo[i].mimo2);
1780 else if (sc->ntxchains == 3)
1781 maxpwr = MAX(maxpwr, enhinfo[i].mimo3);
1782 maxpwr /= 2; /* Convert half-dBm to dBm. */
1783
1784 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr));
1785 sc->enh_maxpwr[i] = maxpwr;
1786 }
1787 }
1788
1789 static struct ieee80211_node *
iwn_node_alloc(struct ieee80211_node_table * ic __unused)1790 iwn_node_alloc(struct ieee80211_node_table *ic __unused)
1791 {
1792 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO);
1793 }
1794
1795 static void
iwn_newassoc(struct ieee80211_node * ni,int isnew)1796 iwn_newassoc(struct ieee80211_node *ni, int isnew)
1797 {
1798 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
1799 struct iwn_node *wn = (void *)ni;
1800 uint8_t rate;
1801 int ridx, i;
1802
1803 ieee80211_amrr_node_init(&sc->amrr, &wn->amn);
1804 /* Start at lowest available bit-rate, AMRR will raise. */
1805 ni->ni_txrate = 0;
1806
1807 for (i = 0; i < ni->ni_rates.rs_nrates; i++) {
1808 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL;
1809 /* Map 802.11 rate to HW rate index. */
1810 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++)
1811 if (iwn_rates[ridx].rate == rate)
1812 break;
1813 wn->ridx[i] = ridx;
1814 }
1815 }
1816
1817 static int
iwn_media_change(struct ifnet * ifp)1818 iwn_media_change(struct ifnet *ifp)
1819 {
1820 struct iwn_softc *sc = ifp->if_softc;
1821 struct ieee80211com *ic = &sc->sc_ic;
1822 uint8_t rate, ridx;
1823 int error;
1824
1825 error = ieee80211_media_change(ifp);
1826 if (error != ENETRESET)
1827 return error;
1828
1829 if (ic->ic_fixed_rate != -1) {
1830 rate = ic->ic_sup_rates[ic->ic_curmode].
1831 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL;
1832 /* Map 802.11 rate to HW rate index. */
1833 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++)
1834 if (iwn_rates[ridx].rate == rate)
1835 break;
1836 sc->fixed_ridx = ridx;
1837 }
1838
1839 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1840 (IFF_UP | IFF_RUNNING)) {
1841 iwn_stop(ifp, 0);
1842 error = iwn_init(ifp);
1843 }
1844 return error;
1845 }
1846
1847 static int
iwn_newstate(struct ieee80211com * ic,enum ieee80211_state nstate,int arg)1848 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1849 {
1850 struct ifnet *ifp = ic->ic_ifp;
1851 struct iwn_softc *sc = ifp->if_softc;
1852 int error;
1853
1854 callout_stop(&sc->calib_to);
1855
1856 switch (nstate) {
1857 case IEEE80211_S_SCAN:
1858 /* XXX Do not abort a running scan. */
1859 if (sc->sc_flags & IWN_FLAG_SCANNING) {
1860 if (ic->ic_state != nstate)
1861 aprint_error_dev(sc->sc_dev, "scan request(%d) "
1862 "while scanning(%d) ignored\n", nstate,
1863 ic->ic_state);
1864 break;
1865 }
1866
1867 /* XXX Not sure if call and flags are needed. */
1868 ieee80211_node_table_reset(&ic->ic_scan);
1869 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN;
1870 sc->sc_flags |= IWN_FLAG_SCANNING_2GHZ;
1871
1872 /* Make the link LED blink while we're scanning. */
1873 iwn_set_led(sc, IWN_LED_LINK, 10, 10);
1874
1875 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) {
1876 aprint_error_dev(sc->sc_dev,
1877 "could not initiate scan\n");
1878 return error;
1879 }
1880 ic->ic_state = nstate;
1881 return 0;
1882
1883 case IEEE80211_S_ASSOC:
1884 if (ic->ic_state != IEEE80211_S_RUN)
1885 break;
1886 /* FALLTHROUGH */
1887 case IEEE80211_S_AUTH:
1888 /* Reset state to handle reassociations correctly. */
1889 sc->rxon.associd = 0;
1890 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS);
1891 sc->calib.state = IWN_CALIB_STATE_INIT;
1892
1893 if ((error = iwn_auth(sc)) != 0) {
1894 aprint_error_dev(sc->sc_dev,
1895 "could not move to auth state\n");
1896 return error;
1897 }
1898 break;
1899
1900 case IEEE80211_S_RUN:
1901 if ((error = iwn_run(sc)) != 0) {
1902 aprint_error_dev(sc->sc_dev,
1903 "could not move to run state\n");
1904 return error;
1905 }
1906 break;
1907
1908 case IEEE80211_S_INIT:
1909 sc->sc_flags &= ~IWN_FLAG_SCANNING;
1910 sc->calib.state = IWN_CALIB_STATE_INIT;
1911 break;
1912 }
1913
1914 return sc->sc_newstate(ic, nstate, arg);
1915 }
1916
1917 static void
iwn_iter_func(void * arg,struct ieee80211_node * ni)1918 iwn_iter_func(void *arg, struct ieee80211_node *ni)
1919 {
1920 struct iwn_softc *sc = arg;
1921 struct iwn_node *wn = (struct iwn_node *)ni;
1922
1923 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn);
1924 }
1925
1926 static void
iwn_calib_timeout(void * arg)1927 iwn_calib_timeout(void *arg)
1928 {
1929 struct iwn_softc *sc = arg;
1930 struct ieee80211com *ic = &sc->sc_ic;
1931 int s;
1932
1933 s = splnet();
1934 if (ic->ic_fixed_rate == -1) {
1935 if (ic->ic_opmode == IEEE80211_M_STA)
1936 iwn_iter_func(sc, ic->ic_bss);
1937 else
1938 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc);
1939 }
1940 /* Force automatic TX power calibration every 60 secs. */
1941 if (++sc->calib_cnt >= 120) {
1942 uint32_t flags = 0;
1943
1944 DPRINTF(("sending request for statistics\n"));
1945 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags,
1946 sizeof flags, 1);
1947 sc->calib_cnt = 0;
1948 }
1949 splx(s);
1950
1951 /* Automatic rate control triggered every 500ms. */
1952 callout_schedule(&sc->calib_to, hz/2);
1953 }
1954
1955 /*
1956 * Process an RX_PHY firmware notification. This is usually immediately
1957 * followed by an MPDU_RX_DONE notification.
1958 */
1959 static void
iwn_rx_phy(struct iwn_softc * sc,struct iwn_rx_desc * desc,struct iwn_rx_data * data)1960 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc,
1961 struct iwn_rx_data *data)
1962 {
1963 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1);
1964
1965 DPRINTFN(2, ("received PHY stats\n"));
1966 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc),
1967 sizeof (*stat), BUS_DMASYNC_POSTREAD);
1968
1969 /* Save RX statistics, they will be used on MPDU_RX_DONE. */
1970 memcpy(&sc->last_rx_stat, stat, sizeof (*stat));
1971 sc->last_rx_valid = 1;
1972 }
1973
1974 /*
1975 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification.
1976 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one.
1977 */
1978 static void
iwn_rx_done(struct iwn_softc * sc,struct iwn_rx_desc * desc,struct iwn_rx_data * data)1979 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
1980 struct iwn_rx_data *data)
1981 {
1982 struct iwn_ops *ops = &sc->ops;
1983 struct ieee80211com *ic = &sc->sc_ic;
1984 struct ifnet *ifp = ic->ic_ifp;
1985 struct iwn_rx_ring *ring = &sc->rxq;
1986 struct ieee80211_frame *wh;
1987 struct ieee80211_node *ni;
1988 struct mbuf *m, *m1;
1989 struct iwn_rx_stat *stat;
1990 char *head;
1991 uint32_t flags;
1992 int error, len, rssi;
1993
1994 if (desc->type == IWN_MPDU_RX_DONE) {
1995 /* Check for prior RX_PHY notification. */
1996 if (!sc->last_rx_valid) {
1997 DPRINTF(("missing RX_PHY\n"));
1998 return;
1999 }
2000 sc->last_rx_valid = 0;
2001 stat = &sc->last_rx_stat;
2002 } else
2003 stat = (struct iwn_rx_stat *)(desc + 1);
2004
2005 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE,
2006 BUS_DMASYNC_POSTREAD);
2007
2008 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) {
2009 aprint_error_dev(sc->sc_dev,
2010 "invalid RX statistic header\n");
2011 return;
2012 }
2013 if (desc->type == IWN_MPDU_RX_DONE) {
2014 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1);
2015 head = (char *)(mpdu + 1);
2016 len = le16toh(mpdu->len);
2017 } else {
2018 head = (char *)(stat + 1) + stat->cfg_phy_len;
2019 len = le16toh(stat->len);
2020 }
2021
2022 flags = le32toh(*(uint32_t *)(head + len));
2023
2024 /* Discard frames with a bad FCS early. */
2025 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) {
2026 DPRINTFN(2, ("RX flags error %x\n", flags));
2027 ifp->if_ierrors++;
2028 return;
2029 }
2030 /* Discard frames that are too short. */
2031 if (len < sizeof (*wh)) {
2032 DPRINTF(("frame too short: %d\n", len));
2033 ic->ic_stats.is_rx_tooshort++;
2034 ifp->if_ierrors++;
2035 return;
2036 }
2037
2038 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE);
2039 if (m1 == NULL) {
2040 ic->ic_stats.is_rx_nobuf++;
2041 ifp->if_ierrors++;
2042 return;
2043 }
2044 bus_dmamap_unload(sc->sc_dmat, data->map);
2045
2046 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *),
2047 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ);
2048 if (error != 0) {
2049 m_freem(m1);
2050
2051 /* Try to reload the old mbuf. */
2052 error = bus_dmamap_load(sc->sc_dmat, data->map,
2053 mtod(data->m, void *), IWN_RBUF_SIZE, NULL,
2054 BUS_DMA_NOWAIT | BUS_DMA_READ);
2055 if (error != 0) {
2056 panic("%s: could not load old RX mbuf",
2057 device_xname(sc->sc_dev));
2058 }
2059 /* Physical address may have changed. */
2060 ring->desc[ring->cur] =
2061 htole32(data->map->dm_segs[0].ds_addr >> 8);
2062 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map,
2063 ring->cur * sizeof (uint32_t), sizeof (uint32_t),
2064 BUS_DMASYNC_PREWRITE);
2065 ifp->if_ierrors++;
2066 return;
2067 }
2068
2069 m = data->m;
2070 data->m = m1;
2071 /* Update RX descriptor. */
2072 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8);
2073 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map,
2074 ring->cur * sizeof (uint32_t), sizeof (uint32_t),
2075 BUS_DMASYNC_PREWRITE);
2076
2077 /* Finalize mbuf. */
2078 m_set_rcvif(m, ifp);
2079 m->m_data = head;
2080 m->m_pkthdr.len = m->m_len = len;
2081
2082 /* Grab a reference to the source node. */
2083 wh = mtod(m, struct ieee80211_frame *);
2084 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
2085
2086 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */
2087 /* NetBSD does decryption in ieee80211_input. */
2088
2089 rssi = ops->get_rssi(stat);
2090
2091 /* XXX Added for NetBSD: scans never stop without it */
2092 if (ic->ic_state == IEEE80211_S_SCAN)
2093 iwn_fix_channel(ic, m, stat);
2094
2095 if (sc->sc_drvbpf != NULL) {
2096 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap;
2097
2098 tap->wr_flags = 0;
2099 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE))
2100 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2101 tap->wr_chan_freq =
2102 htole16(ic->ic_channels[stat->chan].ic_freq);
2103 tap->wr_chan_flags =
2104 htole16(ic->ic_channels[stat->chan].ic_flags);
2105 tap->wr_dbm_antsignal = (int8_t)rssi;
2106 tap->wr_dbm_antnoise = (int8_t)sc->noise;
2107 tap->wr_tsft = stat->tstamp;
2108 switch (stat->rate) {
2109 /* CCK rates. */
2110 case 10: tap->wr_rate = 2; break;
2111 case 20: tap->wr_rate = 4; break;
2112 case 55: tap->wr_rate = 11; break;
2113 case 110: tap->wr_rate = 22; break;
2114 /* OFDM rates. */
2115 case 0xd: tap->wr_rate = 12; break;
2116 case 0xf: tap->wr_rate = 18; break;
2117 case 0x5: tap->wr_rate = 24; break;
2118 case 0x7: tap->wr_rate = 36; break;
2119 case 0x9: tap->wr_rate = 48; break;
2120 case 0xb: tap->wr_rate = 72; break;
2121 case 0x1: tap->wr_rate = 96; break;
2122 case 0x3: tap->wr_rate = 108; break;
2123 /* Unknown rate: should not happen. */
2124 default: tap->wr_rate = 0;
2125 }
2126
2127 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m);
2128 }
2129
2130 /* Send the frame to the 802.11 layer. */
2131 ieee80211_input(ic, m, ni, rssi, 0);
2132
2133 /* Node is no longer needed. */
2134 ieee80211_free_node(ni);
2135 }
2136
2137 #ifndef IEEE80211_NO_HT
2138 /* Process an incoming Compressed BlockAck. */
2139 static void
iwn_rx_compressed_ba(struct iwn_softc * sc,struct iwn_rx_desc * desc,struct iwn_rx_data * data)2140 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2141 struct iwn_rx_data *data)
2142 {
2143 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1);
2144 struct iwn_tx_ring *txq;
2145
2146 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba),
2147 BUS_DMASYNC_POSTREAD);
2148
2149 txq = &sc->txq[le16toh(ba->qid)];
2150 /* XXX TBD */
2151 }
2152 #endif
2153
2154 /*
2155 * Process a CALIBRATION_RESULT notification sent by the initialization
2156 * firmware on response to a CMD_CALIB_CONFIG command (5000 only).
2157 */
2158 static void
iwn5000_rx_calib_results(struct iwn_softc * sc,struct iwn_rx_desc * desc,struct iwn_rx_data * data)2159 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2160 struct iwn_rx_data *data)
2161 {
2162 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1);
2163 int len, idx = -1;
2164
2165 /* Runtime firmware should not send such a notification. */
2166 if (sc->sc_flags & IWN_FLAG_CALIB_DONE)
2167 return;
2168
2169 len = (le32toh(desc->len) & 0x3fff) - 4;
2170 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len,
2171 BUS_DMASYNC_POSTREAD);
2172
2173 switch (calib->code) {
2174 case IWN5000_PHY_CALIB_DC:
2175 if (sc->hw_type == IWN_HW_REV_TYPE_5150 ||
2176 sc->hw_type == IWN_HW_REV_TYPE_2030 ||
2177 sc->hw_type == IWN_HW_REV_TYPE_2000 ||
2178 sc->hw_type == IWN_HW_REV_TYPE_135 ||
2179 sc->hw_type == IWN_HW_REV_TYPE_105)
2180 idx = 0;
2181 break;
2182 case IWN5000_PHY_CALIB_LO:
2183 idx = 1;
2184 break;
2185 case IWN5000_PHY_CALIB_TX_IQ:
2186 idx = 2;
2187 break;
2188 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC:
2189 if (sc->hw_type < IWN_HW_REV_TYPE_6000 &&
2190 sc->hw_type != IWN_HW_REV_TYPE_5150)
2191 idx = 3;
2192 break;
2193 case IWN5000_PHY_CALIB_BASE_BAND:
2194 idx = 4;
2195 break;
2196 }
2197 if (idx == -1) /* Ignore other results. */
2198 return;
2199
2200 /* Save calibration result. */
2201 if (sc->calibcmd[idx].buf != NULL)
2202 free(sc->calibcmd[idx].buf, M_DEVBUF);
2203 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT);
2204 if (sc->calibcmd[idx].buf == NULL) {
2205 DPRINTF(("not enough memory for calibration result %d\n",
2206 calib->code));
2207 return;
2208 }
2209 DPRINTF(("saving calibration result code=%d len=%d\n",
2210 calib->code, len));
2211 sc->calibcmd[idx].len = len;
2212 memcpy(sc->calibcmd[idx].buf, calib, len);
2213 }
2214
2215 /*
2216 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification.
2217 * The latter is sent by the firmware after each received beacon.
2218 */
2219 static void
iwn_rx_statistics(struct iwn_softc * sc,struct iwn_rx_desc * desc,struct iwn_rx_data * data)2220 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2221 struct iwn_rx_data *data)
2222 {
2223 struct iwn_ops *ops = &sc->ops;
2224 struct ieee80211com *ic = &sc->sc_ic;
2225 struct iwn_calib_state *calib = &sc->calib;
2226 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1);
2227 int temp;
2228
2229 /* Ignore statistics received during a scan. */
2230 if (ic->ic_state != IEEE80211_S_RUN)
2231 return;
2232
2233 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc),
2234 sizeof (*stats), BUS_DMASYNC_POSTREAD);
2235
2236 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type));
2237 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */
2238
2239 /* Test if temperature has changed. */
2240 if (stats->general.temp != sc->rawtemp) {
2241 /* Convert "raw" temperature to degC. */
2242 sc->rawtemp = stats->general.temp;
2243 temp = ops->get_temperature(sc);
2244 DPRINTFN(2, ("temperature=%dC\n", temp));
2245
2246 /* Update TX power if need be (4965AGN only). */
2247 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
2248 iwn4965_power_calibration(sc, temp);
2249 }
2250
2251 if (desc->type != IWN_BEACON_STATISTICS)
2252 return; /* Reply to a statistics request. */
2253
2254 sc->noise = iwn_get_noise(&stats->rx.general);
2255
2256 /* Test that RSSI and noise are present in stats report. */
2257 if (le32toh(stats->rx.general.flags) != 1) {
2258 DPRINTF(("received statistics without RSSI\n"));
2259 return;
2260 }
2261
2262 /*
2263 * XXX Differential gain calibration makes the 6005 firmware
2264 * crap out, so skip it for now. This effectively disables
2265 * sensitivity tuning as well.
2266 */
2267 if (sc->hw_type == IWN_HW_REV_TYPE_6005)
2268 return;
2269
2270 if (calib->state == IWN_CALIB_STATE_ASSOC)
2271 iwn_collect_noise(sc, &stats->rx.general);
2272 else if (calib->state == IWN_CALIB_STATE_RUN)
2273 iwn_tune_sensitivity(sc, &stats->rx);
2274 }
2275
2276 /*
2277 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN
2278 * and 5000 adapters have different incompatible TX status formats.
2279 */
2280 static void
iwn4965_tx_done(struct iwn_softc * sc,struct iwn_rx_desc * desc,struct iwn_rx_data * data)2281 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2282 struct iwn_rx_data *data)
2283 {
2284 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1);
2285
2286 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc),
2287 sizeof (*stat), BUS_DMASYNC_POSTREAD);
2288 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff);
2289 }
2290
2291 static void
iwn5000_tx_done(struct iwn_softc * sc,struct iwn_rx_desc * desc,struct iwn_rx_data * data)2292 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2293 struct iwn_rx_data *data)
2294 {
2295 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1);
2296
2297 #ifdef notyet
2298 /* Reset TX scheduler slot. */
2299 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx);
2300 #endif
2301
2302 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc),
2303 sizeof (*stat), BUS_DMASYNC_POSTREAD);
2304 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff);
2305 }
2306
2307 /*
2308 * Adapter-independent backend for TX_DONE firmware notifications.
2309 */
2310 static void
iwn_tx_done(struct iwn_softc * sc,struct iwn_rx_desc * desc,int ackfailcnt,uint8_t status)2311 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt,
2312 uint8_t status)
2313 {
2314 struct ieee80211com *ic = &sc->sc_ic;
2315 struct ifnet *ifp = ic->ic_ifp;
2316 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2317 struct iwn_tx_data *data = &ring->data[desc->idx];
2318 struct iwn_node *wn = (struct iwn_node *)data->ni;
2319
2320 /* Update rate control statistics. */
2321 wn->amn.amn_txcnt++;
2322 if (ackfailcnt > 0)
2323 wn->amn.amn_retrycnt++;
2324
2325 if (status != 1 && status != 2)
2326 ifp->if_oerrors++;
2327 else
2328 ifp->if_opackets++;
2329
2330 /* Unmap and free mbuf. */
2331 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize,
2332 BUS_DMASYNC_POSTWRITE);
2333 bus_dmamap_unload(sc->sc_dmat, data->map);
2334 m_freem(data->m);
2335 data->m = NULL;
2336 ieee80211_free_node(data->ni);
2337 data->ni = NULL;
2338
2339 sc->sc_tx_timer = 0;
2340 if (--ring->queued < IWN_TX_RING_LOMARK) {
2341 sc->qfullmsk &= ~(1 << ring->qid);
2342 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) {
2343 ifp->if_flags &= ~IFF_OACTIVE;
2344 (*ifp->if_start)(ifp);
2345 }
2346 }
2347 }
2348
2349 /*
2350 * Process a "command done" firmware notification. This is where we wakeup
2351 * processes waiting for a synchronous command completion.
2352 */
2353 static void
iwn_cmd_done(struct iwn_softc * sc,struct iwn_rx_desc * desc)2354 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc)
2355 {
2356 struct iwn_tx_ring *ring = &sc->txq[4];
2357 struct iwn_tx_data *data;
2358
2359 if ((desc->qid & 0xf) != 4)
2360 return; /* Not a command ack. */
2361
2362 data = &ring->data[desc->idx];
2363
2364 /* If the command was mapped in an mbuf, free it. */
2365 if (data->m != NULL) {
2366 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
2367 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2368 bus_dmamap_unload(sc->sc_dmat, data->map);
2369 m_freem(data->m);
2370 data->m = NULL;
2371 }
2372 wakeup(&ring->desc[desc->idx]);
2373 }
2374
2375 /*
2376 * Process an INT_FH_RX or INT_SW_RX interrupt.
2377 */
2378 static void
iwn_notif_intr(struct iwn_softc * sc)2379 iwn_notif_intr(struct iwn_softc *sc)
2380 {
2381 struct iwn_ops *ops = &sc->ops;
2382 struct ieee80211com *ic = &sc->sc_ic;
2383 struct ifnet *ifp = ic->ic_ifp;
2384 uint16_t hw;
2385
2386 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map,
2387 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD);
2388
2389 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff;
2390 while (sc->rxq.cur != hw) {
2391 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur];
2392 struct iwn_rx_desc *desc;
2393
2394 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc),
2395 BUS_DMASYNC_POSTREAD);
2396 desc = mtod(data->m, struct iwn_rx_desc *);
2397
2398 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n",
2399 desc->qid & 0xf, desc->idx, desc->flags, desc->type));
2400
2401 if (!(desc->qid & 0x80)) /* Reply to a command. */
2402 iwn_cmd_done(sc, desc);
2403
2404 switch (desc->type) {
2405 case IWN_RX_PHY:
2406 iwn_rx_phy(sc, desc, data);
2407 break;
2408
2409 case IWN_RX_DONE: /* 4965AGN only. */
2410 case IWN_MPDU_RX_DONE:
2411 /* An 802.11 frame has been received. */
2412 iwn_rx_done(sc, desc, data);
2413 break;
2414 #ifndef IEEE80211_NO_HT
2415 case IWN_RX_COMPRESSED_BA:
2416 /* A Compressed BlockAck has been received. */
2417 iwn_rx_compressed_ba(sc, desc, data);
2418 break;
2419 #endif
2420 case IWN_TX_DONE:
2421 /* An 802.11 frame has been transmitted. */
2422 ops->tx_done(sc, desc, data);
2423 break;
2424
2425 case IWN_RX_STATISTICS:
2426 case IWN_BEACON_STATISTICS:
2427 iwn_rx_statistics(sc, desc, data);
2428 break;
2429
2430 case IWN_BEACON_MISSED:
2431 {
2432 struct iwn_beacon_missed *miss =
2433 (struct iwn_beacon_missed *)(desc + 1);
2434
2435 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc),
2436 sizeof (*miss), BUS_DMASYNC_POSTREAD);
2437 /*
2438 * If more than 5 consecutive beacons are missed,
2439 * reinitialize the sensitivity state machine.
2440 */
2441 DPRINTF(("beacons missed %d/%d\n",
2442 le32toh(miss->consecutive), le32toh(miss->total)));
2443 if (ic->ic_state == IEEE80211_S_RUN &&
2444 le32toh(miss->consecutive) > 5)
2445 (void)iwn_init_sensitivity(sc);
2446 break;
2447 }
2448 case IWN_UC_READY:
2449 {
2450 struct iwn_ucode_info *uc =
2451 (struct iwn_ucode_info *)(desc + 1);
2452
2453 /* The microcontroller is ready. */
2454 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc),
2455 sizeof (*uc), BUS_DMASYNC_POSTREAD);
2456 DPRINTF(("microcode alive notification version=%d.%d "
2457 "subtype=%x alive=%x\n", uc->major, uc->minor,
2458 uc->subtype, le32toh(uc->valid)));
2459
2460 if (le32toh(uc->valid) != 1) {
2461 aprint_error_dev(sc->sc_dev,
2462 "microcontroller initialization "
2463 "failed\n");
2464 break;
2465 }
2466 if (uc->subtype == IWN_UCODE_INIT) {
2467 /* Save microcontroller report. */
2468 memcpy(&sc->ucode_info, uc, sizeof (*uc));
2469 }
2470 /* Save the address of the error log in SRAM. */
2471 sc->errptr = le32toh(uc->errptr);
2472 break;
2473 }
2474 case IWN_STATE_CHANGED:
2475 {
2476 uint32_t *status = (uint32_t *)(desc + 1);
2477
2478 /* Enabled/disabled notification. */
2479 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc),
2480 sizeof (*status), BUS_DMASYNC_POSTREAD);
2481 DPRINTF(("state changed to %x\n", le32toh(*status)));
2482
2483 if (le32toh(*status) & 1) {
2484 /* The radio button has to be pushed. */
2485 aprint_error_dev(sc->sc_dev,
2486 "Radio transmitter is off\n");
2487 /* Turn the interface down. */
2488 ifp->if_flags &= ~IFF_UP;
2489 iwn_stop(ifp, 1);
2490 return; /* No further processing. */
2491 }
2492 break;
2493 }
2494 case IWN_START_SCAN:
2495 {
2496 struct iwn_start_scan *scan =
2497 (struct iwn_start_scan *)(desc + 1);
2498
2499 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc),
2500 sizeof (*scan), BUS_DMASYNC_POSTREAD);
2501 DPRINTFN(2, ("scanning channel %d status %x\n",
2502 scan->chan, le32toh(scan->status)));
2503
2504 /* Fix current channel. */
2505 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan];
2506 break;
2507 }
2508 case IWN_STOP_SCAN:
2509 {
2510 struct iwn_stop_scan *scan =
2511 (struct iwn_stop_scan *)(desc + 1);
2512
2513 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc),
2514 sizeof (*scan), BUS_DMASYNC_POSTREAD);
2515 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n",
2516 scan->nchan, scan->status, scan->chan));
2517
2518 if (scan->status == 1 && scan->chan <= 14 &&
2519 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) {
2520 /*
2521 * We just finished scanning 2GHz channels,
2522 * start scanning 5GHz ones.
2523 */
2524 sc->sc_flags &= ~IWN_FLAG_SCANNING_2GHZ;
2525 sc->sc_flags |= IWN_FLAG_SCANNING_5GHZ;
2526 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0)
2527 break;
2528 }
2529 sc->sc_flags &= ~IWN_FLAG_SCANNING;
2530 ieee80211_end_scan(ic);
2531 break;
2532 }
2533 case IWN5000_CALIBRATION_RESULT:
2534 iwn5000_rx_calib_results(sc, desc, data);
2535 break;
2536
2537 case IWN5000_CALIBRATION_DONE:
2538 sc->sc_flags |= IWN_FLAG_CALIB_DONE;
2539 wakeup(sc);
2540 break;
2541 }
2542
2543 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT;
2544 }
2545
2546 /* Tell the firmware what we have processed. */
2547 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1;
2548 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7);
2549 }
2550
2551 /*
2552 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up
2553 * from power-down sleep mode.
2554 */
2555 static void
iwn_wakeup_intr(struct iwn_softc * sc)2556 iwn_wakeup_intr(struct iwn_softc *sc)
2557 {
2558 int qid;
2559
2560 DPRINTF(("ucode wakeup from power-down sleep\n"));
2561
2562 /* Wakeup RX and TX rings. */
2563 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7);
2564 for (qid = 0; qid < sc->ntxqs; qid++) {
2565 struct iwn_tx_ring *ring = &sc->txq[qid];
2566 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur);
2567 }
2568 }
2569
2570 /*
2571 * Dump the error log of the firmware when a firmware panic occurs. Although
2572 * we can't debug the firmware because it is neither open source nor free, it
2573 * can help us to identify certain classes of problems.
2574 */
2575 static void
iwn_fatal_intr(struct iwn_softc * sc)2576 iwn_fatal_intr(struct iwn_softc *sc)
2577 {
2578 struct iwn_fw_dump dump;
2579 int i;
2580
2581 /* Force a complete recalibration on next init. */
2582 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE;
2583
2584 /* Check that the error log address is valid. */
2585 if (sc->errptr < IWN_FW_DATA_BASE ||
2586 sc->errptr + sizeof (dump) >
2587 IWN_FW_DATA_BASE + sc->fw_data_maxsz) {
2588 aprint_error_dev(sc->sc_dev,
2589 "bad firmware error log address 0x%08x\n", sc->errptr);
2590 return;
2591 }
2592 if (iwn_nic_lock(sc) != 0) {
2593 aprint_error_dev(sc->sc_dev,
2594 "could not read firmware error log\n");
2595 return;
2596 }
2597 /* Read firmware error log from SRAM. */
2598 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,
2599 sizeof (dump) / sizeof (uint32_t));
2600 iwn_nic_unlock(sc);
2601
2602 if (dump.valid == 0) {
2603 aprint_error_dev(sc->sc_dev,
2604 "firmware error log is empty\n");
2605 return;
2606 }
2607 aprint_error("firmware error log:\n");
2608 aprint_error(" error type = \"%s\" (0x%08X)\n",
2609 (dump.id < __arraycount(iwn_fw_errmsg)) ?
2610 iwn_fw_errmsg[dump.id] : "UNKNOWN",
2611 dump.id);
2612 aprint_error(" program counter = 0x%08X\n", dump.pc);
2613 aprint_error(" source line = 0x%08X\n", dump.src_line);
2614 aprint_error(" error data = 0x%08X%08X\n",
2615 dump.error_data[0], dump.error_data[1]);
2616 aprint_error(" branch link = 0x%08X%08X\n",
2617 dump.branch_link[0], dump.branch_link[1]);
2618 aprint_error(" interrupt link = 0x%08X%08X\n",
2619 dump.interrupt_link[0], dump.interrupt_link[1]);
2620 aprint_error(" time = %u\n", dump.time[0]);
2621
2622 /* Dump driver status (TX and RX rings) while we're here. */
2623 aprint_error("driver status:\n");
2624 for (i = 0; i < sc->ntxqs; i++) {
2625 struct iwn_tx_ring *ring = &sc->txq[i];
2626 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n",
2627 i, ring->qid, ring->cur, ring->queued);
2628 }
2629 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur);
2630 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state);
2631 }
2632
2633 static int
iwn_intr(void * arg)2634 iwn_intr(void *arg)
2635 {
2636 struct iwn_softc *sc = arg;
2637 struct ifnet *ifp = sc->sc_ic.ic_ifp;
2638 uint32_t r1, r2, tmp;
2639
2640 /* Disable interrupts. */
2641 IWN_WRITE(sc, IWN_INT_MASK, 0);
2642
2643 /* Read interrupts from ICT (fast) or from registers (slow). */
2644 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
2645 tmp = 0;
2646 while (sc->ict[sc->ict_cur] != 0) {
2647 tmp |= sc->ict[sc->ict_cur];
2648 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */
2649 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
2650 }
2651 tmp = le32toh(tmp);
2652 if (tmp == 0xffffffff) /* Shouldn't happen. */
2653 tmp = 0;
2654 else if (tmp & 0xc0000) /* Workaround a HW bug. */
2655 tmp |= 0x8000;
2656 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
2657 r2 = 0; /* Unused. */
2658 } else {
2659 r1 = IWN_READ(sc, IWN_INT);
2660 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0)
2661 return 0; /* Hardware gone! */
2662 r2 = IWN_READ(sc, IWN_FH_INT);
2663 }
2664 if (r1 == 0 && r2 == 0) {
2665 if (ifp->if_flags & IFF_UP)
2666 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
2667 return 0; /* Interrupt not for us. */
2668 }
2669
2670 /* Acknowledge interrupts. */
2671 IWN_WRITE(sc, IWN_INT, r1);
2672 if (!(sc->sc_flags & IWN_FLAG_USE_ICT))
2673 IWN_WRITE(sc, IWN_FH_INT, r2);
2674
2675 if (r1 & IWN_INT_RF_TOGGLED) {
2676 tmp = IWN_READ(sc, IWN_GP_CNTRL);
2677 aprint_error_dev(sc->sc_dev,
2678 "RF switch: radio %s\n",
2679 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled");
2680 }
2681 if (r1 & IWN_INT_CT_REACHED) {
2682 aprint_error_dev(sc->sc_dev,
2683 "critical temperature reached!\n");
2684 }
2685 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) {
2686 aprint_error_dev(sc->sc_dev,
2687 "fatal firmware error\n");
2688 /* Dump firmware error log and stop. */
2689 iwn_fatal_intr(sc);
2690 ifp->if_flags &= ~IFF_UP;
2691 iwn_stop(ifp, 1);
2692 return 1;
2693 }
2694 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) ||
2695 (r2 & IWN_FH_INT_RX)) {
2696 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
2697 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX))
2698 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX);
2699 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
2700 IWN_INT_PERIODIC_DIS);
2701 iwn_notif_intr(sc);
2702 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) {
2703 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
2704 IWN_INT_PERIODIC_ENA);
2705 }
2706 } else
2707 iwn_notif_intr(sc);
2708 }
2709
2710 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) {
2711 if (sc->sc_flags & IWN_FLAG_USE_ICT)
2712 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX);
2713 wakeup(sc); /* FH DMA transfer completed. */
2714 }
2715
2716 if (r1 & IWN_INT_ALIVE)
2717 wakeup(sc); /* Firmware is alive. */
2718
2719 if (r1 & IWN_INT_WAKEUP)
2720 iwn_wakeup_intr(sc);
2721
2722 /* Re-enable interrupts. */
2723 if (ifp->if_flags & IFF_UP)
2724 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
2725
2726 return 1;
2727 }
2728
2729 /*
2730 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and
2731 * 5000 adapters use a slightly different format).
2732 */
2733 static void
iwn4965_update_sched(struct iwn_softc * sc,int qid,int idx,uint8_t id,uint16_t len)2734 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
2735 uint16_t len)
2736 {
2737 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx];
2738
2739 *w = htole16(len + 8);
2740 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map,
2741 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr,
2742 sizeof (uint16_t),
2743 BUS_DMASYNC_PREWRITE);
2744 if (idx < IWN_SCHED_WINSZ) {
2745 *(w + IWN_TX_RING_COUNT) = *w;
2746 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map,
2747 (char *)(void *)(w + IWN_TX_RING_COUNT) -
2748 (char *)(void *)sc->sched_dma.vaddr,
2749 sizeof (uint16_t), BUS_DMASYNC_PREWRITE);
2750 }
2751 }
2752
2753 static void
iwn5000_update_sched(struct iwn_softc * sc,int qid,int idx,uint8_t id,uint16_t len)2754 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
2755 uint16_t len)
2756 {
2757 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
2758
2759 *w = htole16(id << 12 | (len + 8));
2760 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map,
2761 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr,
2762 sizeof (uint16_t), BUS_DMASYNC_PREWRITE);
2763 if (idx < IWN_SCHED_WINSZ) {
2764 *(w + IWN_TX_RING_COUNT) = *w;
2765 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map,
2766 (char *)(void *)(w + IWN_TX_RING_COUNT) -
2767 (char *)(void *)sc->sched_dma.vaddr,
2768 sizeof (uint16_t), BUS_DMASYNC_PREWRITE);
2769 }
2770 }
2771
2772 #ifdef notyet
2773 static void
iwn5000_reset_sched(struct iwn_softc * sc,int qid,int idx)2774 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx)
2775 {
2776 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
2777
2778 *w = (*w & htole16(0xf000)) | htole16(1);
2779 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map,
2780 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr,
2781 sizeof (uint16_t), BUS_DMASYNC_PREWRITE);
2782 if (idx < IWN_SCHED_WINSZ) {
2783 *(w + IWN_TX_RING_COUNT) = *w;
2784 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map,
2785 (char *)(void *)(w + IWN_TX_RING_COUNT) -
2786 (char *)(void *)sc->sched_dma.vaddr,
2787 sizeof (uint16_t), BUS_DMASYNC_PREWRITE);
2788 }
2789 }
2790 #endif
2791
2792 static int
iwn_tx(struct iwn_softc * sc,struct mbuf * m,struct ieee80211_node * ni,int ac)2793 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac)
2794 {
2795 struct ieee80211com *ic = &sc->sc_ic;
2796 struct iwn_node *wn = (void *)ni;
2797 struct iwn_tx_ring *ring;
2798 struct iwn_tx_desc *desc;
2799 struct iwn_tx_data *data;
2800 struct iwn_tx_cmd *cmd;
2801 struct iwn_cmd_data *tx;
2802 const struct iwn_rate *rinfo;
2803 struct ieee80211_frame *wh;
2804 struct ieee80211_key *k = NULL;
2805 struct mbuf *m1;
2806 uint32_t flags;
2807 u_int hdrlen;
2808 bus_dma_segment_t *seg;
2809 uint8_t tid, ridx, txant, type;
2810 int i, totlen, error, pad;
2811
2812 const struct chanAccParams *cap;
2813 int noack;
2814 int hdrlen2;
2815
2816 wh = mtod(m, struct ieee80211_frame *);
2817 hdrlen = ieee80211_anyhdrsize(wh);
2818 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2819
2820 hdrlen2 = (ieee80211_has_qos(wh)) ?
2821 sizeof (struct ieee80211_qosframe) :
2822 sizeof (struct ieee80211_frame);
2823
2824 if (hdrlen != hdrlen2)
2825 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n",
2826 hdrlen, hdrlen2);
2827
2828 /* XXX OpenBSD sets a different tid when using QOS */
2829 tid = 0;
2830 if (ieee80211_has_qos(wh)) {
2831 cap = &ic->ic_wme.wme_chanParams;
2832 noack = cap->cap_wmeParams[ac].wmep_noackPolicy;
2833 }
2834 else
2835 noack = 0;
2836
2837 ring = &sc->txq[ac];
2838 desc = &ring->desc[ring->cur];
2839 data = &ring->data[ring->cur];
2840
2841 /* Choose a TX rate index. */
2842 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
2843 type != IEEE80211_FC0_TYPE_DATA) {
2844 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
2845 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1;
2846 } else if (ic->ic_fixed_rate != -1) {
2847 ridx = sc->fixed_ridx;
2848 } else
2849 ridx = wn->ridx[ni->ni_txrate];
2850 rinfo = &iwn_rates[ridx];
2851
2852 /* Encrypt the frame if need be. */
2853 /*
2854 * XXX For now, NetBSD swaps the encryption and bpf sections
2855 * in order to match old code and other drivers. Tests with
2856 * tcpdump indicates that the order is irrelevant, however,
2857 * as bpf produces unencrypted data for both ordering choices.
2858 */
2859 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
2860 k = ieee80211_crypto_encap(ic, ni, m);
2861 if (k == NULL) {
2862 m_freem(m);
2863 return ENOBUFS;
2864 }
2865 /* Packet header may have moved, reset our local pointer. */
2866 wh = mtod(m, struct ieee80211_frame *);
2867 }
2868 totlen = m->m_pkthdr.len;
2869
2870 if (sc->sc_drvbpf != NULL) {
2871 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
2872
2873 tap->wt_flags = 0;
2874 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq);
2875 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags);
2876 tap->wt_rate = rinfo->rate;
2877 tap->wt_hwqueue = ac;
2878 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
2879 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2880
2881 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m);
2882 }
2883
2884 /* Prepare TX firmware command. */
2885 cmd = &ring->cmd[ring->cur];
2886 cmd->code = IWN_CMD_TX_DATA;
2887 cmd->flags = 0;
2888 cmd->qid = ring->qid;
2889 cmd->idx = ring->cur;
2890
2891 tx = (struct iwn_cmd_data *)cmd->data;
2892 /* NB: No need to clear tx, all fields are reinitialized here. */
2893 tx->scratch = 0; /* clear "scratch" area */
2894
2895 flags = 0;
2896 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2897 /* Unicast frame, check if an ACK is expected. */
2898 if (!noack)
2899 flags |= IWN_TX_NEED_ACK;
2900 }
2901
2902 #ifdef notyet
2903 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */
2904 if ((wh->i_fc[0] &
2905 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
2906 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR))
2907 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */
2908 #endif
2909
2910 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
2911 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */
2912
2913 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
2914 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2915 /* NB: Group frames are sent using CCK in 802.11b/g. */
2916 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) {
2917 flags |= IWN_TX_NEED_RTS;
2918 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
2919 ridx >= IWN_RIDX_OFDM6) {
2920 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2921 flags |= IWN_TX_NEED_CTS;
2922 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2923 flags |= IWN_TX_NEED_RTS;
2924 }
2925 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) {
2926 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
2927 /* 5000 autoselects RTS/CTS or CTS-to-self. */
2928 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS);
2929 flags |= IWN_TX_NEED_PROTECTION;
2930 } else
2931 flags |= IWN_TX_FULL_TXOP;
2932 }
2933 }
2934
2935 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
2936 type != IEEE80211_FC0_TYPE_DATA)
2937 tx->id = sc->broadcast_id;
2938 else
2939 tx->id = wn->id;
2940
2941 if (type == IEEE80211_FC0_TYPE_MGT) {
2942 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
2943
2944 #ifndef IEEE80211_STA_ONLY
2945 /* Tell HW to set timestamp in probe responses. */
2946 /* XXX NetBSD rev 1.11 added probe requests here but */
2947 /* probe requests do not take timestamps (from Bergamini). */
2948 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
2949 flags |= IWN_TX_INSERT_TSTAMP;
2950 #endif
2951 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */
2952 /* changes here. These are not needed (from Bergamini). */
2953 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
2954 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
2955 tx->timeout = htole16(3);
2956 else
2957 tx->timeout = htole16(2);
2958 } else
2959 tx->timeout = htole16(0);
2960
2961 if (hdrlen & 3) {
2962 /* First segment length must be a multiple of 4. */
2963 flags |= IWN_TX_NEED_PADDING;
2964 pad = 4 - (hdrlen & 3);
2965 } else
2966 pad = 0;
2967
2968 tx->len = htole16(totlen);
2969 tx->tid = tid;
2970 tx->rts_ntries = 60;
2971 tx->data_ntries = 15;
2972 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
2973 tx->plcp = rinfo->plcp;
2974 tx->rflags = rinfo->flags;
2975 if (tx->id == sc->broadcast_id) {
2976 /* Group or management frame. */
2977 tx->linkq = 0;
2978 /* XXX Alternate between antenna A and B? */
2979 txant = IWN_LSB(sc->txchainmask);
2980 tx->rflags |= IWN_RFLAG_ANT(txant);
2981 } else {
2982 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1;
2983 flags |= IWN_TX_LINKQ; /* enable MRR */
2984 }
2985 /* Set physical address of "scratch area". */
2986 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
2987 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
2988
2989 /* Copy 802.11 header in TX command. */
2990 /* XXX NetBSD changed this in rev 1.20 */
2991 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen);
2992
2993 /* Trim 802.11 header. */
2994 m_adj(m, hdrlen);
2995 tx->security = 0;
2996 tx->flags = htole32(flags);
2997
2998 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m,
2999 BUS_DMA_NOWAIT | BUS_DMA_WRITE);
3000 if (error != 0) {
3001 if (error != EFBIG) {
3002 aprint_error_dev(sc->sc_dev,
3003 "can't map mbuf (error %d)\n", error);
3004 m_freem(m);
3005 return error;
3006 }
3007 /* Too many DMA segments, linearize mbuf. */
3008 MGETHDR(m1, M_DONTWAIT, MT_DATA);
3009 if (m1 == NULL) {
3010 m_freem(m);
3011 return ENOBUFS;
3012 }
3013 if (m->m_pkthdr.len > MHLEN) {
3014 MCLGET(m1, M_DONTWAIT);
3015 if (!(m1->m_flags & M_EXT)) {
3016 m_freem(m);
3017 m_freem(m1);
3018 return ENOBUFS;
3019 }
3020 }
3021 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *));
3022 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len;
3023 m_freem(m);
3024 m = m1;
3025
3026 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m,
3027 BUS_DMA_NOWAIT | BUS_DMA_WRITE);
3028 if (error != 0) {
3029 aprint_error_dev(sc->sc_dev,
3030 "can't map mbuf (error %d)\n", error);
3031 m_freem(m);
3032 return error;
3033 }
3034 }
3035
3036 data->m = m;
3037 data->ni = ni;
3038
3039 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n",
3040 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs));
3041
3042 /* Fill TX descriptor. */
3043 desc->nsegs = 1 + data->map->dm_nsegs;
3044 /* First DMA segment is used by the TX command. */
3045 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3046 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3047 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3048 /* Other DMA segments are for data payload. */
3049 seg = data->map->dm_segs;
3050 for (i = 1; i <= data->map->dm_nsegs; i++) {
3051 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
3052 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
3053 seg->ds_len << 4);
3054 seg++;
3055 }
3056
3057 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize,
3058 BUS_DMASYNC_PREWRITE);
3059 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map,
3060 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr,
3061 sizeof (*cmd), BUS_DMASYNC_PREWRITE);
3062 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map,
3063 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr,
3064 sizeof (*desc), BUS_DMASYNC_PREWRITE);
3065
3066 #ifdef notyet
3067 /* Update TX scheduler. */
3068 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3069 #endif
3070
3071 /* Kick TX ring. */
3072 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3073 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3074
3075 /* Mark TX ring as full if we reach a certain threshold. */
3076 if (++ring->queued > IWN_TX_RING_HIMARK)
3077 sc->qfullmsk |= 1 << ring->qid;
3078
3079 return 0;
3080 }
3081
3082 static void
iwn_start(struct ifnet * ifp)3083 iwn_start(struct ifnet *ifp)
3084 {
3085 struct iwn_softc *sc = ifp->if_softc;
3086 struct ieee80211com *ic = &sc->sc_ic;
3087 struct ieee80211_node *ni;
3088 struct ether_header *eh;
3089 struct mbuf *m;
3090 int ac;
3091
3092 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3093 return;
3094
3095 for (;;) {
3096 if (sc->qfullmsk != 0) {
3097 ifp->if_flags |= IFF_OACTIVE;
3098 break;
3099 }
3100 /* Send pending management frames first. */
3101 IF_DEQUEUE(&ic->ic_mgtq, m);
3102 if (m != NULL) {
3103 ni = M_GETCTX(m, struct ieee80211_node *);
3104 ac = 0;
3105 goto sendit;
3106 }
3107 if (ic->ic_state != IEEE80211_S_RUN)
3108 break;
3109
3110 /* Encapsulate and send data frames. */
3111 IFQ_DEQUEUE(&ifp->if_snd, m);
3112 if (m == NULL)
3113 break;
3114 if (m->m_len < sizeof (*eh) &&
3115 (m = m_pullup(m, sizeof (*eh))) == NULL) {
3116 ifp->if_oerrors++;
3117 continue;
3118 }
3119 eh = mtod(m, struct ether_header *);
3120 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
3121 if (ni == NULL) {
3122 m_freem(m);
3123 ifp->if_oerrors++;
3124 continue;
3125 }
3126 /* classify mbuf so we can find which tx ring to use */
3127 if (ieee80211_classify(ic, m, ni) != 0) {
3128 m_freem(m);
3129 ieee80211_free_node(ni);
3130 ifp->if_oerrors++;
3131 continue;
3132 }
3133
3134 /* No QoS encapsulation for EAPOL frames. */
3135 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ?
3136 M_WME_GETAC(m) : WME_AC_BE;
3137
3138 bpf_mtap(ifp, m);
3139
3140 if ((m = ieee80211_encap(ic, m, ni)) == NULL) {
3141 ieee80211_free_node(ni);
3142 ifp->if_oerrors++;
3143 continue;
3144 }
3145 sendit:
3146 bpf_mtap3(ic->ic_rawbpf, m);
3147
3148 if (iwn_tx(sc, m, ni, ac) != 0) {
3149 ieee80211_free_node(ni);
3150 ifp->if_oerrors++;
3151 continue;
3152 }
3153
3154 sc->sc_tx_timer = 5;
3155 ifp->if_timer = 1;
3156 }
3157 }
3158
3159 static void
iwn_watchdog(struct ifnet * ifp)3160 iwn_watchdog(struct ifnet *ifp)
3161 {
3162 struct iwn_softc *sc = ifp->if_softc;
3163
3164 ifp->if_timer = 0;
3165
3166 if (sc->sc_tx_timer > 0) {
3167 if (--sc->sc_tx_timer == 0) {
3168 aprint_error_dev(sc->sc_dev,
3169 "device timeout\n");
3170 ifp->if_flags &= ~IFF_UP;
3171 iwn_stop(ifp, 1);
3172 ifp->if_oerrors++;
3173 return;
3174 }
3175 ifp->if_timer = 1;
3176 }
3177
3178 ieee80211_watchdog(&sc->sc_ic);
3179 }
3180
3181 static int
iwn_ioctl(struct ifnet * ifp,u_long cmd,void * data)3182 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data)
3183 {
3184 struct iwn_softc *sc = ifp->if_softc;
3185 struct ieee80211com *ic = &sc->sc_ic;
3186 const struct sockaddr *sa;
3187 int s, error = 0;
3188
3189 s = splnet();
3190
3191 switch (cmd) {
3192 case SIOCSIFADDR:
3193 ifp->if_flags |= IFF_UP;
3194 /* FALLTHROUGH */
3195 case SIOCSIFFLAGS:
3196 /* XXX Added as it is in every NetBSD driver */
3197 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
3198 break;
3199 if (ifp->if_flags & IFF_UP) {
3200 if (!(ifp->if_flags & IFF_RUNNING))
3201 error = iwn_init(ifp);
3202 } else {
3203 if (ifp->if_flags & IFF_RUNNING)
3204 iwn_stop(ifp, 1);
3205 }
3206 break;
3207
3208 case SIOCADDMULTI:
3209 case SIOCDELMULTI:
3210 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data);
3211 error = (cmd == SIOCADDMULTI) ?
3212 ether_addmulti(sa, &sc->sc_ec) :
3213 ether_delmulti(sa, &sc->sc_ec);
3214
3215 if (error == ENETRESET)
3216 error = 0;
3217 break;
3218
3219 default:
3220 error = ieee80211_ioctl(ic, cmd, data);
3221 }
3222
3223 if (error == ENETRESET) {
3224 error = 0;
3225 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
3226 (IFF_UP | IFF_RUNNING)) {
3227 iwn_stop(ifp, 0);
3228 error = iwn_init(ifp);
3229 }
3230 }
3231
3232 splx(s);
3233 return error;
3234 }
3235
3236 /*
3237 * Send a command to the firmware.
3238 */
3239 static int
iwn_cmd(struct iwn_softc * sc,int code,const void * buf,int size,int async)3240 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async)
3241 {
3242 struct iwn_tx_ring *ring = &sc->txq[4];
3243 struct iwn_tx_desc *desc;
3244 struct iwn_tx_data *data;
3245 struct iwn_tx_cmd *cmd;
3246 struct mbuf *m;
3247 bus_addr_t paddr;
3248 int totlen, error;
3249
3250 desc = &ring->desc[ring->cur];
3251 data = &ring->data[ring->cur];
3252 totlen = 4 + size;
3253
3254 if (size > sizeof cmd->data) {
3255 /* Command is too large to fit in a descriptor. */
3256 if (totlen > MCLBYTES)
3257 return EINVAL;
3258 MGETHDR(m, M_DONTWAIT, MT_DATA);
3259 if (m == NULL)
3260 return ENOMEM;
3261 if (totlen > MHLEN) {
3262 MCLGET(m, M_DONTWAIT);
3263 if (!(m->m_flags & M_EXT)) {
3264 m_freem(m);
3265 return ENOMEM;
3266 }
3267 }
3268 cmd = mtod(m, struct iwn_tx_cmd *);
3269 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen,
3270 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE);
3271 if (error != 0) {
3272 m_freem(m);
3273 return error;
3274 }
3275 data->m = m;
3276 paddr = data->map->dm_segs[0].ds_addr;
3277 } else {
3278 cmd = &ring->cmd[ring->cur];
3279 paddr = data->cmd_paddr;
3280 }
3281
3282 cmd->code = code;
3283 cmd->flags = 0;
3284 cmd->qid = ring->qid;
3285 cmd->idx = ring->cur;
3286 memcpy(cmd->data, buf, size);
3287
3288 desc->nsegs = 1;
3289 desc->segs[0].addr = htole32(IWN_LOADDR(paddr));
3290 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4);
3291
3292 if (size > sizeof cmd->data) {
3293 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen,
3294 BUS_DMASYNC_PREWRITE);
3295 } else {
3296 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map,
3297 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr,
3298 totlen, BUS_DMASYNC_PREWRITE);
3299 }
3300 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map,
3301 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr,
3302 sizeof (*desc), BUS_DMASYNC_PREWRITE);
3303
3304 #ifdef notyet
3305 /* Update TX scheduler. */
3306 ops->update_sched(sc, ring->qid, ring->cur, 0, 0);
3307 #endif
3308 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : ""));
3309
3310 /* Kick command ring. */
3311 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3312 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3313
3314 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz);
3315 }
3316
3317 static int
iwn4965_add_node(struct iwn_softc * sc,struct iwn_node_info * node,int async)3318 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3319 {
3320 struct iwn4965_node_info hnode;
3321 char *src, *dst;
3322
3323 /*
3324 * We use the node structure for 5000 Series internally (it is
3325 * a superset of the one for 4965AGN). We thus copy the common
3326 * fields before sending the command.
3327 */
3328 src = (char *)node;
3329 dst = (char *)&hnode;
3330 memcpy(dst, src, 48);
3331 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */
3332 memcpy(dst + 48, src + 72, 20);
3333 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async);
3334 }
3335
3336 static int
iwn5000_add_node(struct iwn_softc * sc,struct iwn_node_info * node,int async)3337 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3338 {
3339 /* Direct mapping. */
3340 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async);
3341 }
3342
3343 static int
iwn_set_link_quality(struct iwn_softc * sc,struct ieee80211_node * ni)3344 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni)
3345 {
3346 struct iwn_node *wn = (void *)ni;
3347 struct ieee80211_rateset *rs = &ni->ni_rates;
3348 struct iwn_cmd_link_quality linkq;
3349 const struct iwn_rate *rinfo;
3350 uint8_t txant;
3351 int i, txrate;
3352
3353 /* Use the first valid TX antenna. */
3354 txant = IWN_LSB(sc->txchainmask);
3355
3356 memset(&linkq, 0, sizeof linkq);
3357 linkq.id = wn->id;
3358 linkq.antmsk_1stream = txant;
3359 linkq.antmsk_2stream = IWN_ANT_AB;
3360 linkq.ampdu_max = 31;
3361 linkq.ampdu_threshold = 3;
3362 linkq.ampdu_limit = htole16(4000); /* 4ms */
3363
3364 /* Start at highest available bit-rate. */
3365 txrate = rs->rs_nrates - 1;
3366 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) {
3367 rinfo = &iwn_rates[wn->ridx[txrate]];
3368 linkq.retry[i].plcp = rinfo->plcp;
3369 linkq.retry[i].rflags = rinfo->flags;
3370 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant);
3371 /* Next retry at immediate lower bit-rate. */
3372 if (txrate > 0)
3373 txrate--;
3374 }
3375 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1);
3376 }
3377
3378 /*
3379 * Broadcast node is used to send group-addressed and management frames.
3380 */
3381 static int
iwn_add_broadcast_node(struct iwn_softc * sc,int async)3382 iwn_add_broadcast_node(struct iwn_softc *sc, int async)
3383 {
3384 struct iwn_ops *ops = &sc->ops;
3385 struct iwn_node_info node;
3386 struct iwn_cmd_link_quality linkq;
3387 const struct iwn_rate *rinfo;
3388 uint8_t txant;
3389 int i, error;
3390
3391 memset(&node, 0, sizeof node);
3392 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr);
3393 node.id = sc->broadcast_id;
3394 DPRINTF(("adding broadcast node\n"));
3395 if ((error = ops->add_node(sc, &node, async)) != 0)
3396 return error;
3397
3398 /* Use the first valid TX antenna. */
3399 txant = IWN_LSB(sc->txchainmask);
3400
3401 memset(&linkq, 0, sizeof linkq);
3402 linkq.id = sc->broadcast_id;
3403 linkq.antmsk_1stream = txant;
3404 linkq.antmsk_2stream = IWN_ANT_AB;
3405 linkq.ampdu_max = 64;
3406 linkq.ampdu_threshold = 3;
3407 linkq.ampdu_limit = htole16(4000); /* 4ms */
3408
3409 /* Use lowest mandatory bit-rate. */
3410 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ?
3411 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6];
3412 linkq.retry[0].plcp = rinfo->plcp;
3413 linkq.retry[0].rflags = rinfo->flags;
3414 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant);
3415 /* Use same bit-rate for all TX retries. */
3416 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) {
3417 linkq.retry[i].plcp = linkq.retry[0].plcp;
3418 linkq.retry[i].rflags = linkq.retry[0].rflags;
3419 }
3420 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async);
3421 }
3422
3423 static void
iwn_set_led(struct iwn_softc * sc,uint8_t which,uint8_t off,uint8_t on)3424 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on)
3425 {
3426 struct iwn_cmd_led led;
3427
3428 /* Clear microcode LED ownership. */
3429 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL);
3430
3431 led.which = which;
3432 led.unit = htole32(10000); /* on/off in unit of 100ms */
3433 led.off = off;
3434 led.on = on;
3435 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1);
3436 }
3437
3438 /*
3439 * Set the critical temperature at which the firmware will stop the radio
3440 * and notify us.
3441 */
3442 static int
iwn_set_critical_temp(struct iwn_softc * sc)3443 iwn_set_critical_temp(struct iwn_softc *sc)
3444 {
3445 struct iwn_critical_temp crit;
3446 int32_t temp;
3447
3448 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF);
3449
3450 if (sc->hw_type == IWN_HW_REV_TYPE_5150)
3451 temp = (IWN_CTOK(110) - sc->temp_off) * -5;
3452 else if (sc->hw_type == IWN_HW_REV_TYPE_4965)
3453 temp = IWN_CTOK(110);
3454 else
3455 temp = 110;
3456 memset(&crit, 0, sizeof crit);
3457 crit.tempR = htole32(temp);
3458 DPRINTF(("setting critical temperature to %d\n", temp));
3459 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0);
3460 }
3461
3462 static int
iwn_set_timing(struct iwn_softc * sc,struct ieee80211_node * ni)3463 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni)
3464 {
3465 struct iwn_cmd_timing cmd;
3466 uint64_t val, mod;
3467
3468 memset(&cmd, 0, sizeof cmd);
3469 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
3470 cmd.bintval = htole16(ni->ni_intval);
3471 cmd.lintval = htole16(10);
3472
3473 /* Compute remaining time until next beacon. */
3474 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */
3475 mod = le64toh(cmd.tstamp) % val;
3476 cmd.binitval = htole32((uint32_t)(val - mod));
3477
3478 DPRINTF(("timing bintval=%u, tstamp=%" PRIu64 ", init=%" PRIu32 "\n",
3479 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)));
3480
3481 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1);
3482 }
3483
3484 static void
iwn4965_power_calibration(struct iwn_softc * sc,int temp)3485 iwn4965_power_calibration(struct iwn_softc *sc, int temp)
3486 {
3487 /* Adjust TX power if need be (delta >= 3 degC). */
3488 DPRINTF(("temperature %d->%d\n", sc->temp, temp));
3489 if (abs(temp - sc->temp) >= 3) {
3490 /* Record temperature of last calibration. */
3491 sc->temp = temp;
3492 (void)iwn4965_set_txpower(sc, 1);
3493 }
3494 }
3495
3496 /*
3497 * Set TX power for current channel (each rate has its own power settings).
3498 * This function takes into account the regulatory information from EEPROM,
3499 * the current temperature and the current voltage.
3500 */
3501 static int
iwn4965_set_txpower(struct iwn_softc * sc,int async)3502 iwn4965_set_txpower(struct iwn_softc *sc, int async)
3503 {
3504 /* Fixed-point arithmetic division using a n-bit fractional part. */
3505 #define fdivround(a, b, n) \
3506 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n))
3507 /* Linear interpolation. */
3508 #define interpolate(x, x1, y1, x2, y2, n) \
3509 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n))
3510
3511 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 };
3512 struct ieee80211com *ic = &sc->sc_ic;
3513 struct iwn_ucode_info *uc = &sc->ucode_info;
3514 struct ieee80211_channel *ch;
3515 struct iwn4965_cmd_txpower cmd;
3516 struct iwn4965_eeprom_chan_samples *chans;
3517 const uint8_t *rf_gain, *dsp_gain;
3518 int32_t vdiff, tdiff;
3519 int i, c, grp, maxpwr;
3520 uint8_t chan;
3521
3522 /* Retrieve current channel from last RXON. */
3523 chan = sc->rxon.chan;
3524 DPRINTF(("setting TX power for channel %d\n", chan));
3525 ch = &ic->ic_channels[chan];
3526
3527 memset(&cmd, 0, sizeof cmd);
3528 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1;
3529 cmd.chan = chan;
3530
3531 if (IEEE80211_IS_CHAN_5GHZ(ch)) {
3532 maxpwr = sc->maxpwr5GHz;
3533 rf_gain = iwn4965_rf_gain_5ghz;
3534 dsp_gain = iwn4965_dsp_gain_5ghz;
3535 } else {
3536 maxpwr = sc->maxpwr2GHz;
3537 rf_gain = iwn4965_rf_gain_2ghz;
3538 dsp_gain = iwn4965_dsp_gain_2ghz;
3539 }
3540
3541 /* Compute voltage compensation. */
3542 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7;
3543 if (vdiff > 0)
3544 vdiff *= 2;
3545 if (abs(vdiff) > 2)
3546 vdiff = 0;
3547 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n",
3548 vdiff, le32toh(uc->volt), sc->eeprom_voltage));
3549
3550 /* Get channel attenuation group. */
3551 if (chan <= 20) /* 1-20 */
3552 grp = 4;
3553 else if (chan <= 43) /* 34-43 */
3554 grp = 0;
3555 else if (chan <= 70) /* 44-70 */
3556 grp = 1;
3557 else if (chan <= 124) /* 71-124 */
3558 grp = 2;
3559 else /* 125-200 */
3560 grp = 3;
3561 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp));
3562
3563 /* Get channel sub-band. */
3564 for (i = 0; i < IWN_NBANDS; i++)
3565 if (sc->bands[i].lo != 0 &&
3566 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi)
3567 break;
3568 if (i == IWN_NBANDS) /* Can't happen in real-life. */
3569 return EINVAL;
3570 chans = sc->bands[i].chans;
3571 DPRINTF(("chan %d sub-band=%d\n", chan, i));
3572
3573 for (c = 0; c < 2; c++) {
3574 uint8_t power, gain, temp;
3575 int maxchpwr, pwr, ridx, idx;
3576
3577 power = interpolate(chan,
3578 chans[0].num, chans[0].samples[c][1].power,
3579 chans[1].num, chans[1].samples[c][1].power, 1);
3580 gain = interpolate(chan,
3581 chans[0].num, chans[0].samples[c][1].gain,
3582 chans[1].num, chans[1].samples[c][1].gain, 1);
3583 temp = interpolate(chan,
3584 chans[0].num, chans[0].samples[c][1].temp,
3585 chans[1].num, chans[1].samples[c][1].temp, 1);
3586 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n",
3587 c, power, gain, temp));
3588
3589 /* Compute temperature compensation. */
3590 tdiff = ((sc->temp - temp) * 2) / tdiv[grp];
3591 DPRINTF(("temperature compensation=%d (current=%d, "
3592 "EEPROM=%d)\n", tdiff, sc->temp, temp));
3593
3594 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) {
3595 /* Convert dBm to half-dBm. */
3596 maxchpwr = sc->maxpwr[chan] * 2;
3597 if ((ridx / 8) & 1)
3598 maxchpwr -= 6; /* MIMO 2T: -3dB */
3599
3600 pwr = maxpwr;
3601
3602 /* Adjust TX power based on rate. */
3603 if ((ridx % 8) == 5)
3604 pwr -= 15; /* OFDM48: -7.5dB */
3605 else if ((ridx % 8) == 6)
3606 pwr -= 17; /* OFDM54: -8.5dB */
3607 else if ((ridx % 8) == 7)
3608 pwr -= 20; /* OFDM60: -10dB */
3609 else
3610 pwr -= 10; /* Others: -5dB */
3611
3612 /* Do not exceed channel max TX power. */
3613 if (pwr > maxchpwr)
3614 pwr = maxchpwr;
3615
3616 idx = gain - (pwr - power) - tdiff - vdiff;
3617 if ((ridx / 8) & 1) /* MIMO */
3618 idx += (int32_t)le32toh(uc->atten[grp][c]);
3619
3620 if (cmd.band == 0)
3621 idx += 9; /* 5GHz */
3622 if (ridx == IWN_RIDX_MAX)
3623 idx += 5; /* CCK */
3624
3625 /* Make sure idx stays in a valid range. */
3626 if (idx < 0)
3627 idx = 0;
3628 else if (idx > IWN4965_MAX_PWR_INDEX)
3629 idx = IWN4965_MAX_PWR_INDEX;
3630
3631 DPRINTF(("TX chain %d, rate idx %d: power=%d\n",
3632 c, ridx, idx));
3633 cmd.power[ridx].rf_gain[c] = rf_gain[idx];
3634 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx];
3635 }
3636 }
3637
3638 DPRINTF(("setting TX power for chan %d\n", chan));
3639 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async);
3640
3641 #undef interpolate
3642 #undef fdivround
3643 }
3644
3645 static int
iwn5000_set_txpower(struct iwn_softc * sc,int async)3646 iwn5000_set_txpower(struct iwn_softc *sc, int async)
3647 {
3648 struct iwn5000_cmd_txpower cmd;
3649
3650 /*
3651 * TX power calibration is handled automatically by the firmware
3652 * for 5000 Series.
3653 */
3654 memset(&cmd, 0, sizeof cmd);
3655 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */
3656 cmd.flags = IWN5000_TXPOWER_NO_CLOSED;
3657 cmd.srv_limit = IWN5000_TXPOWER_AUTO;
3658 DPRINTF(("setting TX power\n"));
3659 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async);
3660 }
3661
3662 /*
3663 * Retrieve the maximum RSSI (in dBm) among receivers.
3664 */
3665 static int
iwn4965_get_rssi(const struct iwn_rx_stat * stat)3666 iwn4965_get_rssi(const struct iwn_rx_stat *stat)
3667 {
3668 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf;
3669 uint8_t mask, agc;
3670 int rssi;
3671
3672 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;
3673 agc = (le16toh(phy->agc) >> 7) & 0x7f;
3674
3675 rssi = 0;
3676 if (mask & IWN_ANT_A)
3677 rssi = MAX(rssi, phy->rssi[0]);
3678 if (mask & IWN_ANT_B)
3679 rssi = MAX(rssi, phy->rssi[2]);
3680 if (mask & IWN_ANT_C)
3681 rssi = MAX(rssi, phy->rssi[4]);
3682
3683 return rssi - agc - IWN_RSSI_TO_DBM;
3684 }
3685
3686 static int
iwn5000_get_rssi(const struct iwn_rx_stat * stat)3687 iwn5000_get_rssi(const struct iwn_rx_stat *stat)
3688 {
3689 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf;
3690 uint8_t agc;
3691 int rssi;
3692
3693 agc = (le32toh(phy->agc) >> 9) & 0x7f;
3694
3695 rssi = MAX(le16toh(phy->rssi[0]) & 0xff,
3696 le16toh(phy->rssi[1]) & 0xff);
3697 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);
3698
3699 return rssi - agc - IWN_RSSI_TO_DBM;
3700 }
3701
3702 /*
3703 * Retrieve the average noise (in dBm) among receivers.
3704 */
3705 static int
iwn_get_noise(const struct iwn_rx_general_stats * stats)3706 iwn_get_noise(const struct iwn_rx_general_stats *stats)
3707 {
3708 int i, total, nbant, noise;
3709
3710 total = nbant = 0;
3711 for (i = 0; i < 3; i++) {
3712 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0)
3713 continue;
3714 total += noise;
3715 nbant++;
3716 }
3717 /* There should be at least one antenna but check anyway. */
3718 return (nbant == 0) ? -127 : (total / nbant) - 107;
3719 }
3720
3721 /*
3722 * Compute temperature (in degC) from last received statistics.
3723 */
3724 static int
iwn4965_get_temperature(struct iwn_softc * sc)3725 iwn4965_get_temperature(struct iwn_softc *sc)
3726 {
3727 struct iwn_ucode_info *uc = &sc->ucode_info;
3728 int32_t r1, r2, r3, r4, temp;
3729
3730 r1 = le32toh(uc->temp[0].chan20MHz);
3731 r2 = le32toh(uc->temp[1].chan20MHz);
3732 r3 = le32toh(uc->temp[2].chan20MHz);
3733 r4 = le32toh(sc->rawtemp);
3734
3735 if (r1 == r3) /* Prevents division by 0 (should not happen). */
3736 return 0;
3737
3738 /* Sign-extend 23-bit R4 value to 32-bit. */
3739 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000;
3740 /* Compute temperature in Kelvin. */
3741 temp = (259 * (r4 - r2)) / (r3 - r1);
3742 temp = (temp * 97) / 100 + 8;
3743
3744 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp)));
3745 return IWN_KTOC(temp);
3746 }
3747
3748 static int
iwn5000_get_temperature(struct iwn_softc * sc)3749 iwn5000_get_temperature(struct iwn_softc *sc)
3750 {
3751 int32_t temp;
3752
3753 /*
3754 * Temperature is not used by the driver for 5000 Series because
3755 * TX power calibration is handled by firmware. We export it to
3756 * users through the sensor framework though.
3757 */
3758 temp = le32toh(sc->rawtemp);
3759 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
3760 temp = (temp / -5) + sc->temp_off;
3761 temp = IWN_KTOC(temp);
3762 }
3763 return temp;
3764 }
3765
3766 /*
3767 * Initialize sensitivity calibration state machine.
3768 */
3769 static int
iwn_init_sensitivity(struct iwn_softc * sc)3770 iwn_init_sensitivity(struct iwn_softc *sc)
3771 {
3772 struct iwn_ops *ops = &sc->ops;
3773 struct iwn_calib_state *calib = &sc->calib;
3774 uint32_t flags;
3775 int error;
3776
3777 /* Reset calibration state machine. */
3778 memset(calib, 0, sizeof (*calib));
3779 calib->state = IWN_CALIB_STATE_INIT;
3780 calib->cck_state = IWN_CCK_STATE_HIFA;
3781 /* Set initial correlation values. */
3782 calib->ofdm_x1 = sc->limits->min_ofdm_x1;
3783 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1;
3784 calib->ofdm_x4 = sc->limits->min_ofdm_x4;
3785 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4;
3786 calib->cck_x4 = 125;
3787 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4;
3788 calib->energy_cck = sc->limits->energy_cck;
3789
3790 /* Write initial sensitivity. */
3791 if ((error = iwn_send_sensitivity(sc)) != 0)
3792 return error;
3793
3794 /* Write initial gains. */
3795 if ((error = ops->init_gains(sc)) != 0)
3796 return error;
3797
3798 /* Request statistics at each beacon interval. */
3799 flags = 0;
3800 DPRINTF(("sending request for statistics\n"));
3801 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1);
3802 }
3803
3804 /*
3805 * Collect noise and RSSI statistics for the first 20 beacons received
3806 * after association and use them to determine connected antennas and
3807 * to set differential gains.
3808 */
3809 static void
iwn_collect_noise(struct iwn_softc * sc,const struct iwn_rx_general_stats * stats)3810 iwn_collect_noise(struct iwn_softc *sc,
3811 const struct iwn_rx_general_stats *stats)
3812 {
3813 struct iwn_ops *ops = &sc->ops;
3814 struct iwn_calib_state *calib = &sc->calib;
3815 uint32_t val;
3816 int i;
3817
3818 /* Accumulate RSSI and noise for all 3 antennas. */
3819 for (i = 0; i < 3; i++) {
3820 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff;
3821 calib->noise[i] += le32toh(stats->noise[i]) & 0xff;
3822 }
3823 /* NB: We update differential gains only once after 20 beacons. */
3824 if (++calib->nbeacons < 20)
3825 return;
3826
3827 /* Determine highest average RSSI. */
3828 val = MAX(calib->rssi[0], calib->rssi[1]);
3829 val = MAX(calib->rssi[2], val);
3830
3831 /* Determine which antennas are connected. */
3832 sc->chainmask = sc->rxchainmask;
3833 for (i = 0; i < 3; i++)
3834 if (val - calib->rssi[i] > 15 * 20)
3835 sc->chainmask &= ~(1 << i);
3836 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n",
3837 sc->rxchainmask, sc->chainmask));
3838
3839 /* If none of the TX antennas are connected, keep at least one. */
3840 if ((sc->chainmask & sc->txchainmask) == 0)
3841 sc->chainmask |= IWN_LSB(sc->txchainmask);
3842
3843 (void)ops->set_gains(sc);
3844 calib->state = IWN_CALIB_STATE_RUN;
3845
3846 #ifdef notyet
3847 /* XXX Disable RX chains with no antennas connected. */
3848 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask));
3849 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
3850 #endif
3851
3852 /* Enable power-saving mode if requested by user. */
3853 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON)
3854 (void)iwn_set_pslevel(sc, 0, 3, 1);
3855 }
3856
3857 static int
iwn4965_init_gains(struct iwn_softc * sc)3858 iwn4965_init_gains(struct iwn_softc *sc)
3859 {
3860 struct iwn_phy_calib_gain cmd;
3861
3862 memset(&cmd, 0, sizeof cmd);
3863 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
3864 /* Differential gains initially set to 0 for all 3 antennas. */
3865 DPRINTF(("setting initial differential gains\n"));
3866 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
3867 }
3868
3869 static int
iwn5000_init_gains(struct iwn_softc * sc)3870 iwn5000_init_gains(struct iwn_softc *sc)
3871 {
3872 struct iwn_phy_calib cmd;
3873
3874 memset(&cmd, 0, sizeof cmd);
3875 cmd.code = sc->reset_noise_gain;
3876 cmd.ngroups = 1;
3877 cmd.isvalid = 1;
3878 DPRINTF(("setting initial differential gains\n"));
3879 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
3880 }
3881
3882 static int
iwn4965_set_gains(struct iwn_softc * sc)3883 iwn4965_set_gains(struct iwn_softc *sc)
3884 {
3885 struct iwn_calib_state *calib = &sc->calib;
3886 struct iwn_phy_calib_gain cmd;
3887 int i, delta, noise;
3888
3889 /* Get minimal noise among connected antennas. */
3890 noise = INT_MAX; /* NB: There's at least one antenna. */
3891 for (i = 0; i < 3; i++)
3892 if (sc->chainmask & (1 << i))
3893 noise = MIN(calib->noise[i], noise);
3894
3895 memset(&cmd, 0, sizeof cmd);
3896 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
3897 /* Set differential gains for connected antennas. */
3898 for (i = 0; i < 3; i++) {
3899 if (sc->chainmask & (1 << i)) {
3900 /* Compute attenuation (in unit of 1.5dB). */
3901 delta = (noise - (int32_t)calib->noise[i]) / 30;
3902 /* NB: delta <= 0 */
3903 /* Limit to [-4.5dB,0]. */
3904 cmd.gain[i] = MIN(abs(delta), 3);
3905 if (delta < 0)
3906 cmd.gain[i] |= 1 << 2; /* sign bit */
3907 }
3908 }
3909 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n",
3910 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask));
3911 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
3912 }
3913
3914 static int
iwn5000_set_gains(struct iwn_softc * sc)3915 iwn5000_set_gains(struct iwn_softc *sc)
3916 {
3917 struct iwn_calib_state *calib = &sc->calib;
3918 struct iwn_phy_calib_gain cmd;
3919 int i, ant, div, delta;
3920
3921 /* We collected 20 beacons and !=6050 need a 1.5 factor. */
3922 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
3923
3924 memset(&cmd, 0, sizeof cmd);
3925 cmd.code = sc->noise_gain;
3926 cmd.ngroups = 1;
3927 cmd.isvalid = 1;
3928 /* Get first available RX antenna as referential. */
3929 ant = IWN_LSB(sc->rxchainmask);
3930 /* Set differential gains for other antennas. */
3931 for (i = ant + 1; i < 3; i++) {
3932 if (sc->chainmask & (1 << i)) {
3933 /* The delta is relative to antenna "ant". */
3934 delta = ((int32_t)calib->noise[ant] -
3935 (int32_t)calib->noise[i]) / div;
3936 /* Limit to [-4.5dB,+4.5dB]. */
3937 cmd.gain[i - 1] = MIN(abs(delta), 3);
3938 if (delta < 0)
3939 cmd.gain[i - 1] |= 1 << 2; /* sign bit */
3940 }
3941 }
3942 DPRINTF(("setting differential gains: %x/%x (%x)\n",
3943 cmd.gain[0], cmd.gain[1], sc->chainmask));
3944 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
3945 }
3946
3947 /*
3948 * Tune RF RX sensitivity based on the number of false alarms detected
3949 * during the last beacon period.
3950 */
3951 static void
iwn_tune_sensitivity(struct iwn_softc * sc,const struct iwn_rx_stats * stats)3952 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats)
3953 {
3954 #define inc(val, inc, max) \
3955 if ((val) < (max)) { \
3956 if ((val) < (max) - (inc)) \
3957 (val) += (inc); \
3958 else \
3959 (val) = (max); \
3960 needs_update = 1; \
3961 }
3962 #define dec(val, dec, min) \
3963 if ((val) > (min)) { \
3964 if ((val) > (min) + (dec)) \
3965 (val) -= (dec); \
3966 else \
3967 (val) = (min); \
3968 needs_update = 1; \
3969 }
3970
3971 const struct iwn_sensitivity_limits *limits = sc->limits;
3972 struct iwn_calib_state *calib = &sc->calib;
3973 uint32_t val, rxena, fa;
3974 uint32_t energy[3], energy_min;
3975 uint8_t noise[3], noise_ref;
3976 int i, needs_update = 0;
3977
3978 /* Check that we've been enabled long enough. */
3979 if ((rxena = le32toh(stats->general.load)) == 0)
3980 return;
3981
3982 /* Compute number of false alarms since last call for OFDM. */
3983 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm;
3984 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm;
3985 fa *= 200 * 1024; /* 200TU */
3986
3987 /* Save counters values for next call. */
3988 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp);
3989 calib->fa_ofdm = le32toh(stats->ofdm.fa);
3990
3991 if (fa > 50 * rxena) {
3992 /* High false alarm count, decrease sensitivity. */
3993 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa));
3994 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1);
3995 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1);
3996 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4);
3997 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4);
3998
3999 } else if (fa < 5 * rxena) {
4000 /* Low false alarm count, increase sensitivity. */
4001 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa));
4002 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1);
4003 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1);
4004 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4);
4005 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4);
4006 }
4007
4008 /* Compute maximum noise among 3 receivers. */
4009 for (i = 0; i < 3; i++)
4010 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff;
4011 val = MAX(noise[0], noise[1]);
4012 val = MAX(noise[2], val);
4013 /* Insert it into our samples table. */
4014 calib->noise_samples[calib->cur_noise_sample] = val;
4015 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20;
4016
4017 /* Compute maximum noise among last 20 samples. */
4018 noise_ref = calib->noise_samples[0];
4019 for (i = 1; i < 20; i++)
4020 noise_ref = MAX(noise_ref, calib->noise_samples[i]);
4021
4022 /* Compute maximum energy among 3 receivers. */
4023 for (i = 0; i < 3; i++)
4024 energy[i] = le32toh(stats->general.energy[i]);
4025 val = MIN(energy[0], energy[1]);
4026 val = MIN(energy[2], val);
4027 /* Insert it into our samples table. */
4028 calib->energy_samples[calib->cur_energy_sample] = val;
4029 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10;
4030
4031 /* Compute minimum energy among last 10 samples. */
4032 energy_min = calib->energy_samples[0];
4033 for (i = 1; i < 10; i++)
4034 energy_min = MAX(energy_min, calib->energy_samples[i]);
4035 energy_min += 6;
4036
4037 /* Compute number of false alarms since last call for CCK. */
4038 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck;
4039 fa += le32toh(stats->cck.fa) - calib->fa_cck;
4040 fa *= 200 * 1024; /* 200TU */
4041
4042 /* Save counters values for next call. */
4043 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp);
4044 calib->fa_cck = le32toh(stats->cck.fa);
4045
4046 if (fa > 50 * rxena) {
4047 /* High false alarm count, decrease sensitivity. */
4048 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa));
4049 calib->cck_state = IWN_CCK_STATE_HIFA;
4050 calib->low_fa = 0;
4051
4052 if (calib->cck_x4 > 160) {
4053 calib->noise_ref = noise_ref;
4054 if (calib->energy_cck > 2)
4055 dec(calib->energy_cck, 2, energy_min);
4056 }
4057 if (calib->cck_x4 < 160) {
4058 calib->cck_x4 = 161;
4059 needs_update = 1;
4060 } else
4061 inc(calib->cck_x4, 3, limits->max_cck_x4);
4062
4063 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4);
4064
4065 } else if (fa < 5 * rxena) {
4066 /* Low false alarm count, increase sensitivity. */
4067 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa));
4068 calib->cck_state = IWN_CCK_STATE_LOFA;
4069 calib->low_fa++;
4070
4071 if (calib->cck_state != IWN_CCK_STATE_INIT &&
4072 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 ||
4073 calib->low_fa > 100)) {
4074 inc(calib->energy_cck, 2, limits->min_energy_cck);
4075 dec(calib->cck_x4, 3, limits->min_cck_x4);
4076 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4);
4077 }
4078 } else {
4079 /* Not worth to increase or decrease sensitivity. */
4080 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa));
4081 calib->low_fa = 0;
4082 calib->noise_ref = noise_ref;
4083
4084 if (calib->cck_state == IWN_CCK_STATE_HIFA) {
4085 /* Previous interval had many false alarms. */
4086 dec(calib->energy_cck, 8, energy_min);
4087 }
4088 calib->cck_state = IWN_CCK_STATE_INIT;
4089 }
4090
4091 if (needs_update)
4092 (void)iwn_send_sensitivity(sc);
4093 #undef dec
4094 #undef inc
4095 }
4096
4097 static int
iwn_send_sensitivity(struct iwn_softc * sc)4098 iwn_send_sensitivity(struct iwn_softc *sc)
4099 {
4100 struct iwn_calib_state *calib = &sc->calib;
4101 struct iwn_enhanced_sensitivity_cmd cmd;
4102 int len;
4103
4104 memset(&cmd, 0, sizeof cmd);
4105 len = sizeof (struct iwn_sensitivity_cmd);
4106 cmd.which = IWN_SENSITIVITY_WORKTBL;
4107 /* OFDM modulation. */
4108 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1);
4109 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1);
4110 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4);
4111 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4);
4112 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm);
4113 cmd.energy_ofdm_th = htole16(62);
4114 /* CCK modulation. */
4115 cmd.corr_cck_x4 = htole16(calib->cck_x4);
4116 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4);
4117 cmd.energy_cck = htole16(calib->energy_cck);
4118 /* Barker modulation: use default values. */
4119 cmd.corr_barker = htole16(190);
4120 cmd.corr_barker_mrc = htole16(390);
4121 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS))
4122 goto send;
4123 /* Enhanced sensitivity settings. */
4124 len = sizeof (struct iwn_enhanced_sensitivity_cmd);
4125 cmd.ofdm_det_slope_mrc = htole16(668);
4126 cmd.ofdm_det_icept_mrc = htole16(4);
4127 cmd.ofdm_det_slope = htole16(486);
4128 cmd.ofdm_det_icept = htole16(37);
4129 cmd.cck_det_slope_mrc = htole16(853);
4130 cmd.cck_det_icept_mrc = htole16(4);
4131 cmd.cck_det_slope = htole16(476);
4132 cmd.cck_det_icept = htole16(99);
4133 send:
4134 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n",
4135 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4,
4136 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4,
4137 calib->energy_cck));
4138 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1);
4139 }
4140
4141 /*
4142 * Set STA mode power saving level (between 0 and 5).
4143 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving.
4144 */
4145 static int
iwn_set_pslevel(struct iwn_softc * sc,int dtim,int level,int async)4146 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async)
4147 {
4148 struct iwn_pmgt_cmd cmd;
4149 const struct iwn_pmgt *pmgt;
4150 uint32_t maxp, skip_dtim;
4151 pcireg_t reg;
4152 int i;
4153
4154 /* Select which PS parameters to use. */
4155 if (dtim <= 2)
4156 pmgt = &iwn_pmgt[0][level];
4157 else if (dtim <= 10)
4158 pmgt = &iwn_pmgt[1][level];
4159 else
4160 pmgt = &iwn_pmgt[2][level];
4161
4162 memset(&cmd, 0, sizeof cmd);
4163 if (level != 0) /* not CAM */
4164 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP);
4165 if (level == 5)
4166 cmd.flags |= htole16(IWN_PS_FAST_PD);
4167 /* Retrieve PCIe Active State Power Management (ASPM). */
4168 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
4169 sc->sc_cap_off + PCIE_LCSR);
4170 if (!(reg & PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */
4171 cmd.flags |= htole16(IWN_PS_PCI_PMGT);
4172 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024);
4173 cmd.txtimeout = htole32(pmgt->txtimeout * 1024);
4174
4175 if (dtim == 0) {
4176 dtim = 1;
4177 skip_dtim = 0;
4178 } else
4179 skip_dtim = pmgt->skip_dtim;
4180 if (skip_dtim != 0) {
4181 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM);
4182 maxp = pmgt->intval[4];
4183 if (maxp == (uint32_t)-1)
4184 maxp = dtim * (skip_dtim + 1);
4185 else if (maxp > dtim)
4186 maxp = (maxp / dtim) * dtim;
4187 } else
4188 maxp = dtim;
4189 for (i = 0; i < 5; i++)
4190 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i]));
4191
4192 DPRINTF(("setting power saving level to %d\n", level));
4193 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async);
4194 }
4195
4196 int
iwn5000_runtime_calib(struct iwn_softc * sc)4197 iwn5000_runtime_calib(struct iwn_softc *sc)
4198 {
4199 struct iwn5000_calib_config cmd;
4200
4201 memset(&cmd, 0, sizeof cmd);
4202 cmd.ucode.once.enable = 0xffffffff;
4203 cmd.ucode.once.start = IWN5000_CALIB_DC;
4204 DPRINTF(("configuring runtime calibration\n"));
4205 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0);
4206 }
4207
4208 static int
iwn_config_bt_coex_bluetooth(struct iwn_softc * sc)4209 iwn_config_bt_coex_bluetooth(struct iwn_softc *sc)
4210 {
4211 struct iwn_bluetooth bluetooth;
4212
4213 memset(&bluetooth, 0, sizeof bluetooth);
4214 bluetooth.flags = IWN_BT_COEX_ENABLE;
4215 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF;
4216 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF;
4217
4218 DPRINTF(("configuring bluetooth coexistence\n"));
4219 return iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0);
4220 }
4221
4222 static int
iwn_config_bt_coex_prio_table(struct iwn_softc * sc)4223 iwn_config_bt_coex_prio_table(struct iwn_softc *sc)
4224 {
4225 uint8_t prio_table[16];
4226
4227 memset(&prio_table, 0, sizeof prio_table);
4228 prio_table[ 0] = 6; /* init calibration 1 */
4229 prio_table[ 1] = 7; /* init calibration 2 */
4230 prio_table[ 2] = 2; /* periodic calib low 1 */
4231 prio_table[ 3] = 3; /* periodic calib low 2 */
4232 prio_table[ 4] = 4; /* periodic calib high 1 */
4233 prio_table[ 5] = 5; /* periodic calib high 2 */
4234 prio_table[ 6] = 6; /* dtim */
4235 prio_table[ 7] = 8; /* scan52 */
4236 prio_table[ 8] = 10; /* scan24 */
4237
4238 DPRINTF(("sending priority lookup table\n"));
4239 return iwn_cmd(sc, IWN_CMD_BT_COEX_PRIO_TABLE,
4240 &prio_table, sizeof prio_table, 0);
4241 }
4242
4243 static int
iwn_config_bt_coex_adv_config(struct iwn_softc * sc,struct iwn_bt_basic * basic,size_t len)4244 iwn_config_bt_coex_adv_config(struct iwn_softc *sc, struct iwn_bt_basic *basic,
4245 size_t len)
4246 {
4247 struct iwn_btcoex_prot btprot;
4248 int error;
4249
4250 basic->bt.flags = IWN_BT_COEX_ENABLE;
4251 basic->bt.lead_time = IWN_BT_LEAD_TIME_DEF;
4252 basic->bt.max_kill = IWN_BT_MAX_KILL_DEF;
4253 basic->bt.bt3_timer_t7_value = IWN_BT_BT3_T7_DEF;
4254 basic->bt.kill_ack_mask = IWN_BT_KILL_ACK_MASK_DEF;
4255 basic->bt.kill_cts_mask = IWN_BT_KILL_CTS_MASK_DEF;
4256 basic->bt3_prio_sample_time = IWN_BT_BT3_PRIO_SAMPLE_DEF;
4257 basic->bt3_timer_t2_value = IWN_BT_BT3_T2_DEF;
4258 basic->bt3_lookup_table[ 0] = htole32(0xaaaaaaaa); /* Normal */
4259 basic->bt3_lookup_table[ 1] = htole32(0xaaaaaaaa);
4260 basic->bt3_lookup_table[ 2] = htole32(0xaeaaaaaa);
4261 basic->bt3_lookup_table[ 3] = htole32(0xaaaaaaaa);
4262 basic->bt3_lookup_table[ 4] = htole32(0xcc00ff28);
4263 basic->bt3_lookup_table[ 5] = htole32(0x0000aaaa);
4264 basic->bt3_lookup_table[ 6] = htole32(0xcc00aaaa);
4265 basic->bt3_lookup_table[ 7] = htole32(0x0000aaaa);
4266 basic->bt3_lookup_table[ 8] = htole32(0xc0004000);
4267 basic->bt3_lookup_table[ 9] = htole32(0x00004000);
4268 basic->bt3_lookup_table[10] = htole32(0xf0005000);
4269 basic->bt3_lookup_table[11] = htole32(0xf0005000);
4270 basic->reduce_txpower = 0; /* as not implemented */
4271 basic->valid = IWN_BT_ALL_VALID_MASK;
4272
4273 DPRINTF(("configuring advanced bluetooth coexistence v1\n"));
4274 error = iwn_cmd(sc, IWN_CMD_BT_COEX, basic, len, 0);
4275 if (error != 0) {
4276 aprint_error_dev(sc->sc_dev,
4277 "could not configure advanced bluetooth coexistence\n");
4278 return error;
4279 }
4280
4281 error = iwn_config_bt_coex_prio_table(sc);
4282 if (error != 0) {
4283 aprint_error_dev(sc->sc_dev,
4284 "could not configure send BT priority table\n");
4285 return error;
4286 }
4287
4288 /* Force BT state machine change */
4289 memset(&btprot, 0, sizeof btprot);
4290 btprot.open = 1;
4291 btprot.type = 1;
4292 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1);
4293 if (error != 0) {
4294 aprint_error_dev(sc->sc_dev, "could not open BT protcol\n");
4295 return error;
4296 }
4297
4298 btprot.open = 0;
4299 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1);
4300 if (error != 0) {
4301 aprint_error_dev(sc->sc_dev, "could not close BT protcol\n");
4302 return error;
4303 }
4304 return 0;
4305 }
4306
4307 static int
iwn_config_bt_coex_adv1(struct iwn_softc * sc)4308 iwn_config_bt_coex_adv1(struct iwn_softc *sc)
4309 {
4310 struct iwn_bt_adv1 d;
4311
4312 memset(&d, 0, sizeof d);
4313 d.prio_boost = IWN_BT_PRIO_BOOST_DEF;
4314 d.tx_prio_boost = 0;
4315 d.rx_prio_boost = 0;
4316 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d);
4317 }
4318
4319 static int
iwn_config_bt_coex_adv2(struct iwn_softc * sc)4320 iwn_config_bt_coex_adv2(struct iwn_softc *sc)
4321 {
4322 struct iwn_bt_adv2 d;
4323
4324 memset(&d, 0, sizeof d);
4325 d.prio_boost = IWN_BT_PRIO_BOOST_DEF;
4326 d.tx_prio_boost = 0;
4327 d.rx_prio_boost = 0;
4328 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d);
4329 }
4330
4331 static int
iwn_config(struct iwn_softc * sc)4332 iwn_config(struct iwn_softc *sc)
4333 {
4334 struct iwn_ops *ops = &sc->ops;
4335 struct ieee80211com *ic = &sc->sc_ic;
4336 struct ifnet *ifp = ic->ic_ifp;
4337 uint32_t txmask;
4338 uint16_t rxchain;
4339 int error;
4340
4341 error = ops->config_bt_coex(sc);
4342 if (error != 0) {
4343 aprint_error_dev(sc->sc_dev,
4344 "could not configure bluetooth coexistence\n");
4345 return error;
4346 }
4347
4348 /* Set radio temperature sensor offset. */
4349 if (sc->hw_type == IWN_HW_REV_TYPE_6005) {
4350 error = iwn6000_temp_offset_calib(sc);
4351 if (error != 0) {
4352 aprint_error_dev(sc->sc_dev,
4353 "could not set temperature offset\n");
4354 return error;
4355 }
4356 }
4357
4358 if (sc->hw_type == IWN_HW_REV_TYPE_2030 ||
4359 sc->hw_type == IWN_HW_REV_TYPE_2000 ||
4360 sc->hw_type == IWN_HW_REV_TYPE_135 ||
4361 sc->hw_type == IWN_HW_REV_TYPE_105) {
4362 error = iwn2000_temp_offset_calib(sc);
4363 if (error != 0) {
4364 aprint_error_dev(sc->sc_dev,
4365 "could not set temperature offset\n");
4366 return error;
4367 }
4368 }
4369
4370 if (sc->hw_type == IWN_HW_REV_TYPE_6050 ||
4371 sc->hw_type == IWN_HW_REV_TYPE_6005) {
4372 /* Configure runtime DC calibration. */
4373 error = iwn5000_runtime_calib(sc);
4374 if (error != 0) {
4375 aprint_error_dev(sc->sc_dev,
4376 "could not configure runtime calibration\n");
4377 return error;
4378 }
4379 }
4380
4381 /* Configure valid TX chains for 5000 Series. */
4382 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4383 txmask = htole32(sc->txchainmask);
4384 DPRINTF(("configuring valid TX chains 0x%x\n", txmask));
4385 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask,
4386 sizeof txmask, 0);
4387 if (error != 0) {
4388 aprint_error_dev(sc->sc_dev,
4389 "could not configure valid TX chains\n");
4390 return error;
4391 }
4392 }
4393
4394 /* Set mode, channel, RX filter and enable RX. */
4395 memset(&sc->rxon, 0, sizeof (struct iwn_rxon));
4396 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl));
4397 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr);
4398 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr);
4399 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan);
4400 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
4401 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan))
4402 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
4403 switch (ic->ic_opmode) {
4404 case IEEE80211_M_STA:
4405 sc->rxon.mode = IWN_MODE_STA;
4406 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST);
4407 break;
4408 case IEEE80211_M_MONITOR:
4409 sc->rxon.mode = IWN_MODE_MONITOR;
4410 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST |
4411 IWN_FILTER_CTL | IWN_FILTER_PROMISC);
4412 break;
4413 default:
4414 /* Should not get there. */
4415 break;
4416 }
4417 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */
4418 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */
4419 sc->rxon.ht_single_mask = 0xff;
4420 sc->rxon.ht_dual_mask = 0xff;
4421 sc->rxon.ht_triple_mask = 0xff;
4422 rxchain =
4423 IWN_RXCHAIN_VALID(sc->rxchainmask) |
4424 IWN_RXCHAIN_MIMO_COUNT(2) |
4425 IWN_RXCHAIN_IDLE_COUNT(2);
4426 sc->rxon.rxchain = htole16(rxchain);
4427 DPRINTF(("setting configuration\n"));
4428 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0);
4429 if (error != 0) {
4430 aprint_error_dev(sc->sc_dev,
4431 "RXON command failed\n");
4432 return error;
4433 }
4434
4435 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) {
4436 aprint_error_dev(sc->sc_dev,
4437 "could not add broadcast node\n");
4438 return error;
4439 }
4440
4441 /* Configuration has changed, set TX power accordingly. */
4442 if ((error = ops->set_txpower(sc, 0)) != 0) {
4443 aprint_error_dev(sc->sc_dev,
4444 "could not set TX power\n");
4445 return error;
4446 }
4447
4448 if ((error = iwn_set_critical_temp(sc)) != 0) {
4449 aprint_error_dev(sc->sc_dev,
4450 "could not set critical temperature\n");
4451 return error;
4452 }
4453
4454 /* Set power saving level to CAM during initialization. */
4455 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) {
4456 aprint_error_dev(sc->sc_dev,
4457 "could not set power saving level\n");
4458 return error;
4459 }
4460 return 0;
4461 }
4462
4463 static uint16_t
iwn_get_active_dwell_time(struct iwn_softc * sc,uint16_t flags,uint8_t n_probes)4464 iwn_get_active_dwell_time(struct iwn_softc *sc, uint16_t flags,
4465 uint8_t n_probes)
4466 {
4467 /* No channel? Default to 2GHz settings */
4468 if (flags & IEEE80211_CHAN_2GHZ)
4469 return IWN_ACTIVE_DWELL_TIME_2GHZ +
4470 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1);
4471
4472 /* 5GHz dwell time */
4473 return IWN_ACTIVE_DWELL_TIME_5GHZ +
4474 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1);
4475 }
4476
4477 /*
4478 * Limit the total dwell time to 85% of the beacon interval.
4479 *
4480 * Returns the dwell time in milliseconds.
4481 */
4482 static uint16_t
iwn_limit_dwell(struct iwn_softc * sc,uint16_t dwell_time)4483 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time)
4484 {
4485 struct ieee80211com *ic = &sc->sc_ic;
4486 struct ieee80211_node *ni = ic->ic_bss;
4487 int bintval = 0;
4488
4489 /* bintval is in TU (1.024mS) */
4490 if (ni != NULL)
4491 bintval = ni->ni_intval;
4492
4493 /*
4494 * If it's non-zero, we should calculate the minimum of
4495 * it and the DWELL_BASE.
4496 *
4497 * XXX Yes, the math should take into account that bintval
4498 * is 1.024mS, not 1mS..
4499 */
4500 if (bintval > 0)
4501 return MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100));
4502
4503 /* No association context? Default */
4504 return IWN_PASSIVE_DWELL_BASE;
4505 }
4506
4507 static uint16_t
iwn_get_passive_dwell_time(struct iwn_softc * sc,uint16_t flags)4508 iwn_get_passive_dwell_time(struct iwn_softc *sc, uint16_t flags)
4509 {
4510 uint16_t passive;
4511 if (flags & IEEE80211_CHAN_2GHZ)
4512 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ;
4513 else
4514 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ;
4515
4516 /* Clamp to the beacon interval if we're associated */
4517 return iwn_limit_dwell(sc, passive);
4518 }
4519
4520 static int
iwn_scan(struct iwn_softc * sc,uint16_t flags)4521 iwn_scan(struct iwn_softc *sc, uint16_t flags)
4522 {
4523 struct ieee80211com *ic = &sc->sc_ic;
4524 struct iwn_scan_hdr *hdr;
4525 struct iwn_cmd_data *tx;
4526 struct iwn_scan_essid *essid;
4527 struct iwn_scan_chan *chan;
4528 struct ieee80211_frame *wh;
4529 struct ieee80211_rateset *rs;
4530 struct ieee80211_channel *c;
4531 uint8_t *buf, *frm;
4532 uint16_t rxchain, dwell_active, dwell_passive;
4533 uint8_t txant;
4534 int buflen, error, is_active;
4535
4536 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO);
4537 if (buf == NULL) {
4538 aprint_error_dev(sc->sc_dev,
4539 "could not allocate buffer for scan command\n");
4540 return ENOMEM;
4541 }
4542 hdr = (struct iwn_scan_hdr *)buf;
4543 /*
4544 * Move to the next channel if no frames are received within 10ms
4545 * after sending the probe request.
4546 */
4547 hdr->quiet_time = htole16(10); /* timeout in milliseconds */
4548 hdr->quiet_threshold = htole16(1); /* min # of packets */
4549
4550 /* Select antennas for scanning. */
4551 rxchain =
4552 IWN_RXCHAIN_VALID(sc->rxchainmask) |
4553 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) |
4554 IWN_RXCHAIN_DRIVER_FORCE;
4555 if ((flags & IEEE80211_CHAN_5GHZ) &&
4556 sc->hw_type == IWN_HW_REV_TYPE_4965) {
4557 /* Ant A must be avoided in 5GHz because of an HW bug. */
4558 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC);
4559 } else /* Use all available RX antennas. */
4560 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask);
4561 hdr->rxchain = htole16(rxchain);
4562 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON);
4563
4564 tx = (struct iwn_cmd_data *)(hdr + 1);
4565 tx->flags = htole32(IWN_TX_AUTO_SEQ);
4566 tx->id = sc->broadcast_id;
4567 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
4568
4569 if (flags & IEEE80211_CHAN_5GHZ) {
4570 hdr->crc_threshold = 0xffff;
4571 /* Send probe requests at 6Mbps. */
4572 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp;
4573 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A];
4574 } else {
4575 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO);
4576 /* Send probe requests at 1Mbps. */
4577 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp;
4578 tx->rflags = IWN_RFLAG_CCK;
4579 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G];
4580 }
4581 /* Use the first valid TX antenna. */
4582 txant = IWN_LSB(sc->txchainmask);
4583 tx->rflags |= IWN_RFLAG_ANT(txant);
4584
4585 /*
4586 * Only do active scanning if we're announcing a probe request
4587 * for a given SSID (or more, if we ever add it to the driver.)
4588 */
4589 is_active = 0;
4590
4591 essid = (struct iwn_scan_essid *)(tx + 1);
4592 if (ic->ic_des_esslen != 0) {
4593 essid[0].id = IEEE80211_ELEMID_SSID;
4594 essid[0].len = ic->ic_des_esslen;
4595 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen);
4596
4597 is_active = 1;
4598 }
4599 /*
4600 * Build a probe request frame. Most of the following code is a
4601 * copy & paste of what is done in net80211.
4602 */
4603 wh = (struct ieee80211_frame *)(essid + 20);
4604 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
4605 IEEE80211_FC0_SUBTYPE_PROBE_REQ;
4606 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
4607 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr);
4608 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr);
4609 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr);
4610 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */
4611 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */
4612
4613 frm = (uint8_t *)(wh + 1);
4614 frm = ieee80211_add_ssid(frm, NULL, 0);
4615 frm = ieee80211_add_rates(frm, rs);
4616 #ifndef IEEE80211_NO_HT
4617 if (ic->ic_flags & IEEE80211_F_HTON)
4618 frm = ieee80211_add_htcaps(frm, ic);
4619 #endif
4620 if (rs->rs_nrates > IEEE80211_RATE_SIZE)
4621 frm = ieee80211_add_xrates(frm, rs);
4622
4623 /* Set length of probe request. */
4624 tx->len = htole16(frm - (uint8_t *)wh);
4625
4626
4627 /*
4628 * If active scanning is requested but a certain channel is
4629 * marked passive, we can do active scanning if we detect
4630 * transmissions.
4631 *
4632 * There is an issue with some firmware versions that triggers
4633 * a sysassert on a "good CRC threshold" of zero (== disabled),
4634 * on a radar channel even though this means that we should NOT
4635 * send probes.
4636 *
4637 * The "good CRC threshold" is the number of frames that we
4638 * need to receive during our dwell time on a channel before
4639 * sending out probes -- setting this to a huge value will
4640 * mean we never reach it, but at the same time work around
4641 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER
4642 * here instead of IWN_GOOD_CRC_TH_DISABLED.
4643 *
4644 * This was fixed in later versions along with some other
4645 * scan changes, and the threshold behaves as a flag in those
4646 * versions.
4647 */
4648
4649 /*
4650 * If we're doing active scanning, set the crc_threshold
4651 * to a suitable value. This is different to active veruss
4652 * passive scanning depending upon the channel flags; the
4653 * firmware will obey that particular check for us.
4654 */
4655 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN)
4656 hdr->crc_threshold = is_active ?
4657 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED;
4658 else
4659 hdr->crc_threshold = is_active ?
4660 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER;
4661
4662 chan = (struct iwn_scan_chan *)frm;
4663 for (c = &ic->ic_channels[1];
4664 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) {
4665 if ((c->ic_flags & flags) != flags)
4666 continue;
4667
4668 chan->chan = htole16(ieee80211_chan2ieee(ic, c));
4669 DPRINTFN(2, ("adding channel %d\n", chan->chan));
4670 chan->flags = 0;
4671 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE))
4672 chan->flags |= htole32(IWN_CHAN_ACTIVE);
4673 if (ic->ic_des_esslen != 0)
4674 chan->flags |= htole32(IWN_CHAN_NPBREQS(1));
4675
4676 /*
4677 * Calculate the active/passive dwell times.
4678 */
4679
4680 dwell_active = iwn_get_active_dwell_time(sc, flags, is_active);
4681 dwell_passive = iwn_get_passive_dwell_time(sc, flags);
4682
4683 /* Make sure they're valid */
4684 if (dwell_passive <= dwell_active)
4685 dwell_passive = dwell_active + 1;
4686
4687 chan->active = htole16(dwell_active);
4688 chan->passive = htole16(dwell_passive);
4689
4690 chan->dsp_gain = 0x6e;
4691 if (IEEE80211_IS_CHAN_5GHZ(c)) {
4692 chan->rf_gain = 0x3b;
4693 } else {
4694 chan->rf_gain = 0x28;
4695 }
4696 hdr->nchan++;
4697 chan++;
4698 }
4699
4700 buflen = (uint8_t *)chan - buf;
4701 hdr->len = htole16(buflen);
4702
4703 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan));
4704 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1);
4705 free(buf, M_DEVBUF);
4706 return error;
4707 }
4708
4709 static int
iwn_auth(struct iwn_softc * sc)4710 iwn_auth(struct iwn_softc *sc)
4711 {
4712 struct iwn_ops *ops = &sc->ops;
4713 struct ieee80211com *ic = &sc->sc_ic;
4714 struct ieee80211_node *ni = ic->ic_bss;
4715 int error;
4716
4717 /* Update adapter configuration. */
4718 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
4719 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan);
4720 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
4721 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
4722 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
4723 if (ic->ic_flags & IEEE80211_F_SHSLOT)
4724 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
4725 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4726 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
4727 switch (ic->ic_curmode) {
4728 case IEEE80211_MODE_11A:
4729 sc->rxon.cck_mask = 0;
4730 sc->rxon.ofdm_mask = 0x15;
4731 break;
4732 case IEEE80211_MODE_11B:
4733 sc->rxon.cck_mask = 0x03;
4734 sc->rxon.ofdm_mask = 0;
4735 break;
4736 default: /* Assume 802.11b/g. */
4737 sc->rxon.cck_mask = 0x0f;
4738 sc->rxon.ofdm_mask = 0x15;
4739 }
4740 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan,
4741 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask));
4742 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
4743 if (error != 0) {
4744 aprint_error_dev(sc->sc_dev,
4745 "RXON command failed\n");
4746 return error;
4747 }
4748
4749 /* Configuration has changed, set TX power accordingly. */
4750 if ((error = ops->set_txpower(sc, 1)) != 0) {
4751 aprint_error_dev(sc->sc_dev,
4752 "could not set TX power\n");
4753 return error;
4754 }
4755 /*
4756 * Reconfiguring RXON clears the firmware nodes table so we must
4757 * add the broadcast node again.
4758 */
4759 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) {
4760 aprint_error_dev(sc->sc_dev,
4761 "could not add broadcast node\n");
4762 return error;
4763 }
4764 return 0;
4765 }
4766
4767 static int
iwn_run(struct iwn_softc * sc)4768 iwn_run(struct iwn_softc *sc)
4769 {
4770 struct iwn_ops *ops = &sc->ops;
4771 struct ieee80211com *ic = &sc->sc_ic;
4772 struct ieee80211_node *ni = ic->ic_bss;
4773 struct iwn_node_info node;
4774 int error;
4775
4776 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4777 /* Link LED blinks while monitoring. */
4778 iwn_set_led(sc, IWN_LED_LINK, 5, 5);
4779 return 0;
4780 }
4781 if ((error = iwn_set_timing(sc, ni)) != 0) {
4782 aprint_error_dev(sc->sc_dev,
4783 "could not set timing\n");
4784 return error;
4785 }
4786
4787 /* Update adapter configuration. */
4788 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd));
4789 /* Short preamble and slot time are negotiated when associating. */
4790 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT);
4791 if (ic->ic_flags & IEEE80211_F_SHSLOT)
4792 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
4793 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4794 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
4795 sc->rxon.filter |= htole32(IWN_FILTER_BSS);
4796 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags));
4797 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
4798 if (error != 0) {
4799 aprint_error_dev(sc->sc_dev,
4800 "could not update configuration\n");
4801 return error;
4802 }
4803
4804 /* Configuration has changed, set TX power accordingly. */
4805 if ((error = ops->set_txpower(sc, 1)) != 0) {
4806 aprint_error_dev(sc->sc_dev,
4807 "could not set TX power\n");
4808 return error;
4809 }
4810
4811 /* Fake a join to initialize the TX rate. */
4812 ((struct iwn_node *)ni)->id = IWN_ID_BSS;
4813 iwn_newassoc(ni, 1);
4814
4815 /* Add BSS node. */
4816 memset(&node, 0, sizeof node);
4817 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr);
4818 node.id = IWN_ID_BSS;
4819 #ifdef notyet
4820 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) |
4821 IWN_AMDPU_DENSITY(5)); /* 2us */
4822 #endif
4823 DPRINTF(("adding BSS node\n"));
4824 error = ops->add_node(sc, &node, 1);
4825 if (error != 0) {
4826 aprint_error_dev(sc->sc_dev,
4827 "could not add BSS node\n");
4828 return error;
4829 }
4830 DPRINTF(("setting link quality for node %d\n", node.id));
4831 if ((error = iwn_set_link_quality(sc, ni)) != 0) {
4832 aprint_error_dev(sc->sc_dev,
4833 "could not setup link quality for node %d\n", node.id);
4834 return error;
4835 }
4836
4837 if ((error = iwn_init_sensitivity(sc)) != 0) {
4838 aprint_error_dev(sc->sc_dev,
4839 "could not set sensitivity\n");
4840 return error;
4841 }
4842 /* Start periodic calibration timer. */
4843 sc->calib.state = IWN_CALIB_STATE_ASSOC;
4844 sc->calib_cnt = 0;
4845 callout_schedule(&sc->calib_to, hz/2);
4846
4847 /* Link LED always on while associated. */
4848 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
4849 return 0;
4850 }
4851
4852 #ifdef IWN_HWCRYPTO
4853 /*
4854 * We support CCMP hardware encryption/decryption of unicast frames only.
4855 * HW support for TKIP really sucks. We should let TKIP die anyway.
4856 */
4857 static int
iwn_set_key(struct ieee80211com * ic,struct ieee80211_node * ni,struct ieee80211_key * k)4858 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
4859 struct ieee80211_key *k)
4860 {
4861 struct iwn_softc *sc = ic->ic_softc;
4862 struct iwn_ops *ops = &sc->ops;
4863 struct iwn_node *wn = (void *)ni;
4864 struct iwn_node_info node;
4865 uint16_t kflags;
4866
4867 if ((k->k_flags & IEEE80211_KEY_GROUP) ||
4868 k->k_cipher != IEEE80211_CIPHER_CCMP)
4869 return ieee80211_set_key(ic, ni, k);
4870
4871 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id);
4872 if (k->k_flags & IEEE80211_KEY_GROUP)
4873 kflags |= IWN_KFLAG_GROUP;
4874
4875 memset(&node, 0, sizeof node);
4876 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ?
4877 sc->broadcast_id : wn->id;
4878 node.control = IWN_NODE_UPDATE;
4879 node.flags = IWN_FLAG_SET_KEY;
4880 node.kflags = htole16(kflags);
4881 node.kid = k->k_id;
4882 memcpy(node.key, k->k_key, k->k_len);
4883 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id));
4884 return ops->add_node(sc, &node, 1);
4885 }
4886
4887 static void
iwn_delete_key(struct ieee80211com * ic,struct ieee80211_node * ni,struct ieee80211_key * k)4888 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
4889 struct ieee80211_key *k)
4890 {
4891 struct iwn_softc *sc = ic->ic_softc;
4892 struct iwn_ops *ops = &sc->ops;
4893 struct iwn_node *wn = (void *)ni;
4894 struct iwn_node_info node;
4895
4896 if ((k->k_flags & IEEE80211_KEY_GROUP) ||
4897 k->k_cipher != IEEE80211_CIPHER_CCMP) {
4898 /* See comment about other ciphers above. */
4899 ieee80211_delete_key(ic, ni, k);
4900 return;
4901 }
4902 if (ic->ic_state != IEEE80211_S_RUN)
4903 return; /* Nothing to do. */
4904 memset(&node, 0, sizeof node);
4905 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ?
4906 sc->broadcast_id : wn->id;
4907 node.control = IWN_NODE_UPDATE;
4908 node.flags = IWN_FLAG_SET_KEY;
4909 node.kflags = htole16(IWN_KFLAG_INVALID);
4910 node.kid = 0xff;
4911 DPRINTF(("delete keys for node %d\n", node.id));
4912 (void)ops->add_node(sc, &node, 1);
4913 }
4914 #endif
4915
4916 /* XXX Added for NetBSD (copied from rev 1.39). */
4917
4918 static int
iwn_wme_update(struct ieee80211com * ic)4919 iwn_wme_update(struct ieee80211com *ic)
4920 {
4921 #define IWN_EXP2(v) htole16((1 << (v)) - 1)
4922 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v))
4923 struct iwn_softc *sc = ic->ic_ifp->if_softc;
4924 const struct wmeParams *wmep;
4925 struct iwn_edca_params cmd;
4926 int ac;
4927
4928 /* don't override default WME values if WME is not actually enabled */
4929 if (!(ic->ic_flags & IEEE80211_F_WME))
4930 return 0;
4931 cmd.flags = 0;
4932 for (ac = 0; ac < WME_NUM_AC; ac++) {
4933 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
4934 cmd.ac[ac].aifsn = wmep->wmep_aifsn;
4935 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin);
4936 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax);
4937 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit);
4938
4939 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d "
4940 "txop=%d\n", ac, cmd.ac[ac].aifsn,
4941 cmd.ac[ac].cwmin,
4942 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit));
4943 }
4944 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1);
4945 #undef IWN_USEC
4946 #undef IWN_EXP2
4947 }
4948
4949 #ifndef IEEE80211_NO_HT
4950 /*
4951 * This function is called by upper layer when an ADDBA request is received
4952 * from another STA and before the ADDBA response is sent.
4953 */
4954 static int
iwn_ampdu_rx_start(struct ieee80211com * ic,struct ieee80211_node * ni,uint8_t tid)4955 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
4956 uint8_t tid)
4957 {
4958 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid];
4959 struct iwn_softc *sc = ic->ic_softc;
4960 struct iwn_ops *ops = &sc->ops;
4961 struct iwn_node *wn = (void *)ni;
4962 struct iwn_node_info node;
4963
4964 memset(&node, 0, sizeof node);
4965 node.id = wn->id;
4966 node.control = IWN_NODE_UPDATE;
4967 node.flags = IWN_FLAG_SET_ADDBA;
4968 node.addba_tid = tid;
4969 node.addba_ssn = htole16(ba->ba_winstart);
4970 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid,
4971 ba->ba_winstart));
4972 return ops->add_node(sc, &node, 1);
4973 }
4974
4975 /*
4976 * This function is called by upper layer on teardown of an HT-immediate
4977 * Block Ack agreement (eg. uppon receipt of a DELBA frame).
4978 */
4979 static void
iwn_ampdu_rx_stop(struct ieee80211com * ic,struct ieee80211_node * ni,uint8_t tid)4980 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
4981 uint8_t tid)
4982 {
4983 struct iwn_softc *sc = ic->ic_softc;
4984 struct iwn_ops *ops = &sc->ops;
4985 struct iwn_node *wn = (void *)ni;
4986 struct iwn_node_info node;
4987
4988 memset(&node, 0, sizeof node);
4989 node.id = wn->id;
4990 node.control = IWN_NODE_UPDATE;
4991 node.flags = IWN_FLAG_SET_DELBA;
4992 node.delba_tid = tid;
4993 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid));
4994 (void)ops->add_node(sc, &node, 1);
4995 }
4996
4997 /*
4998 * This function is called by upper layer when an ADDBA response is received
4999 * from another STA.
5000 */
5001 static int
iwn_ampdu_tx_start(struct ieee80211com * ic,struct ieee80211_node * ni,uint8_t tid)5002 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
5003 uint8_t tid)
5004 {
5005 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid];
5006 struct iwn_softc *sc = ic->ic_softc;
5007 struct iwn_ops *ops = &sc->ops;
5008 struct iwn_node *wn = (void *)ni;
5009 struct iwn_node_info node;
5010 int error;
5011
5012 /* Enable TX for the specified RA/TID. */
5013 wn->disable_tid &= ~(1 << tid);
5014 memset(&node, 0, sizeof node);
5015 node.id = wn->id;
5016 node.control = IWN_NODE_UPDATE;
5017 node.flags = IWN_FLAG_SET_DISABLE_TID;
5018 node.disable_tid = htole16(wn->disable_tid);
5019 error = ops->add_node(sc, &node, 1);
5020 if (error != 0)
5021 return error;
5022
5023 if ((error = iwn_nic_lock(sc)) != 0)
5024 return error;
5025 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart);
5026 iwn_nic_unlock(sc);
5027 return 0;
5028 }
5029
5030 static void
iwn_ampdu_tx_stop(struct ieee80211com * ic,struct ieee80211_node * ni,uint8_t tid)5031 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
5032 uint8_t tid)
5033 {
5034 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid];
5035 struct iwn_softc *sc = ic->ic_softc;
5036 struct iwn_ops *ops = &sc->ops;
5037
5038 if (iwn_nic_lock(sc) != 0)
5039 return;
5040 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart);
5041 iwn_nic_unlock(sc);
5042 }
5043
5044 static void
iwn4965_ampdu_tx_start(struct iwn_softc * sc,struct ieee80211_node * ni,uint8_t tid,uint16_t ssn)5045 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5046 uint8_t tid, uint16_t ssn)
5047 {
5048 struct iwn_node *wn = (void *)ni;
5049 int qid = 7 + tid;
5050
5051 /* Stop TX scheduler while we're changing its configuration. */
5052 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5053 IWN4965_TXQ_STATUS_CHGACT);
5054
5055 /* Assign RA/TID translation to the queue. */
5056 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid),
5057 wn->id << 4 | tid);
5058
5059 /* Enable chain-building mode for the queue. */
5060 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid);
5061
5062 /* Set starting sequence number from the ADDBA request. */
5063 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5064 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5065
5066 /* Set scheduler window size. */
5067 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid),
5068 IWN_SCHED_WINSZ);
5069 /* Set scheduler frame limit. */
5070 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5071 IWN_SCHED_LIMIT << 16);
5072
5073 /* Enable interrupts for the queue. */
5074 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5075
5076 /* Mark the queue as active. */
5077 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5078 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA |
5079 iwn_tid2fifo[tid] << 1);
5080 }
5081
5082 static void
iwn4965_ampdu_tx_stop(struct iwn_softc * sc,uint8_t tid,uint16_t ssn)5083 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn)
5084 {
5085 int qid = 7 + tid;
5086
5087 /* Stop TX scheduler while we're changing its configuration. */
5088 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5089 IWN4965_TXQ_STATUS_CHGACT);
5090
5091 /* Set starting sequence number from the ADDBA request. */
5092 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5093 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5094
5095 /* Disable interrupts for the queue. */
5096 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5097
5098 /* Mark the queue as inactive. */
5099 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5100 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1);
5101 }
5102
5103 static void
iwn5000_ampdu_tx_start(struct iwn_softc * sc,struct ieee80211_node * ni,uint8_t tid,uint16_t ssn)5104 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5105 uint8_t tid, uint16_t ssn)
5106 {
5107 struct iwn_node *wn = (void *)ni;
5108 int qid = 10 + tid;
5109
5110 /* Stop TX scheduler while we're changing its configuration. */
5111 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5112 IWN5000_TXQ_STATUS_CHGACT);
5113
5114 /* Assign RA/TID translation to the queue. */
5115 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid),
5116 wn->id << 4 | tid);
5117
5118 /* Enable chain-building mode for the queue. */
5119 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid);
5120
5121 /* Enable aggregation for the queue. */
5122 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5123
5124 /* Set starting sequence number from the ADDBA request. */
5125 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5126 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5127
5128 /* Set scheduler window size and frame limit. */
5129 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5130 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5131
5132 /* Enable interrupts for the queue. */
5133 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5134
5135 /* Mark the queue as active. */
5136 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5137 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]);
5138 }
5139
5140 static void
iwn5000_ampdu_tx_stop(struct iwn_softc * sc,uint8_t tid,uint16_t ssn)5141 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn)
5142 {
5143 int qid = 10 + tid;
5144
5145 /* Stop TX scheduler while we're changing its configuration. */
5146 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5147 IWN5000_TXQ_STATUS_CHGACT);
5148
5149 /* Disable aggregation for the queue. */
5150 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5151
5152 /* Set starting sequence number from the ADDBA request. */
5153 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5154 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5155
5156 /* Disable interrupts for the queue. */
5157 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5158
5159 /* Mark the queue as inactive. */
5160 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5161 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]);
5162 }
5163 #endif /* !IEEE80211_NO_HT */
5164
5165 /*
5166 * Query calibration tables from the initialization firmware. We do this
5167 * only once at first boot. Called from a process context.
5168 */
5169 static int
iwn5000_query_calibration(struct iwn_softc * sc)5170 iwn5000_query_calibration(struct iwn_softc *sc)
5171 {
5172 struct iwn5000_calib_config cmd;
5173 int error;
5174
5175 memset(&cmd, 0, sizeof cmd);
5176 cmd.ucode.once.enable = 0xffffffff;
5177 cmd.ucode.once.start = 0xffffffff;
5178 cmd.ucode.once.send = 0xffffffff;
5179 cmd.ucode.flags = 0xffffffff;
5180 DPRINTF(("sending calibration query\n"));
5181 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0);
5182 if (error != 0)
5183 return error;
5184
5185 /* Wait at most two seconds for calibration to complete. */
5186 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE))
5187 error = tsleep(sc, PCATCH, "iwncal", 2 * hz);
5188 return error;
5189 }
5190
5191 /*
5192 * Send calibration results to the runtime firmware. These results were
5193 * obtained on first boot from the initialization firmware.
5194 */
5195 static int
iwn5000_send_calibration(struct iwn_softc * sc)5196 iwn5000_send_calibration(struct iwn_softc *sc)
5197 {
5198 int idx, error;
5199
5200 for (idx = 0; idx < 5; idx++) {
5201 if (sc->calibcmd[idx].buf == NULL)
5202 continue; /* No results available. */
5203 DPRINTF(("send calibration result idx=%d len=%d\n",
5204 idx, sc->calibcmd[idx].len));
5205 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf,
5206 sc->calibcmd[idx].len, 0);
5207 if (error != 0) {
5208 aprint_error_dev(sc->sc_dev,
5209 "could not send calibration result\n");
5210 return error;
5211 }
5212 }
5213 return 0;
5214 }
5215
5216 static int
iwn5000_send_wimax_coex(struct iwn_softc * sc)5217 iwn5000_send_wimax_coex(struct iwn_softc *sc)
5218 {
5219 struct iwn5000_wimax_coex wimax;
5220
5221 #ifdef notyet
5222 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
5223 /* Enable WiMAX coexistence for combo adapters. */
5224 wimax.flags =
5225 IWN_WIMAX_COEX_ASSOC_WA_UNMASK |
5226 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK |
5227 IWN_WIMAX_COEX_STA_TABLE_VALID |
5228 IWN_WIMAX_COEX_ENABLE;
5229 memcpy(wimax.events, iwn6050_wimax_events,
5230 sizeof iwn6050_wimax_events);
5231 } else
5232 #endif
5233 {
5234 /* Disable WiMAX coexistence. */
5235 wimax.flags = 0;
5236 memset(wimax.events, 0, sizeof wimax.events);
5237 }
5238 DPRINTF(("Configuring WiMAX coexistence\n"));
5239 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0);
5240 }
5241
5242 static int
iwn6000_temp_offset_calib(struct iwn_softc * sc)5243 iwn6000_temp_offset_calib(struct iwn_softc *sc)
5244 {
5245 struct iwn6000_phy_calib_temp_offset cmd;
5246
5247 memset(&cmd, 0, sizeof cmd);
5248 cmd.code = IWN6000_PHY_CALIB_TEMP_OFFSET;
5249 cmd.ngroups = 1;
5250 cmd.isvalid = 1;
5251 if (sc->eeprom_temp != 0)
5252 cmd.offset = htole16(sc->eeprom_temp);
5253 else
5254 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET);
5255 DPRINTF(("setting radio sensor offset to %d\n", le16toh(cmd.offset)));
5256 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5257 }
5258
5259 static int
iwn2000_temp_offset_calib(struct iwn_softc * sc)5260 iwn2000_temp_offset_calib(struct iwn_softc *sc)
5261 {
5262 struct iwn2000_phy_calib_temp_offset cmd;
5263
5264 memset(&cmd, 0, sizeof cmd);
5265 cmd.code = IWN2000_PHY_CALIB_TEMP_OFFSET;
5266 cmd.ngroups = 1;
5267 cmd.isvalid = 1;
5268 if (sc->eeprom_rawtemp != 0) {
5269 cmd.offset_low = htole16(sc->eeprom_rawtemp);
5270 cmd.offset_high = htole16(sc->eeprom_temp);
5271 } else {
5272 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET);
5273 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET);
5274 }
5275 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage);
5276 DPRINTF(("setting radio sensor offset to %d:%d, voltage to %d\n",
5277 le16toh(cmd.offset_low), le16toh(cmd.offset_high),
5278 le16toh(cmd.burnt_voltage_ref)));
5279 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5280 }
5281
5282 /*
5283 * This function is called after the runtime firmware notifies us of its
5284 * readiness (called in a process context).
5285 */
5286 static int
iwn4965_post_alive(struct iwn_softc * sc)5287 iwn4965_post_alive(struct iwn_softc *sc)
5288 {
5289 int error, qid;
5290
5291 if ((error = iwn_nic_lock(sc)) != 0)
5292 return error;
5293
5294 /* Clear TX scheduler state in SRAM. */
5295 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5296 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0,
5297 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t));
5298
5299 /* Set physical address of TX scheduler rings (1KB aligned). */
5300 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5301
5302 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5303
5304 /* Disable chain mode for all our 16 queues. */
5305 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0);
5306
5307 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) {
5308 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0);
5309 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5310
5311 /* Set scheduler window size. */
5312 iwn_mem_write(sc, sc->sched_base +
5313 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ);
5314 /* Set scheduler frame limit. */
5315 iwn_mem_write(sc, sc->sched_base +
5316 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5317 IWN_SCHED_LIMIT << 16);
5318 }
5319
5320 /* Enable interrupts for all our 16 queues. */
5321 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff);
5322 /* Identify TX FIFO rings (0-7). */
5323 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff);
5324
5325 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
5326 for (qid = 0; qid < 7; qid++) {
5327 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
5328 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5329 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1);
5330 }
5331 iwn_nic_unlock(sc);
5332 return 0;
5333 }
5334
5335 /*
5336 * This function is called after the initialization or runtime firmware
5337 * notifies us of its readiness (called in a process context).
5338 */
5339 static int
iwn5000_post_alive(struct iwn_softc * sc)5340 iwn5000_post_alive(struct iwn_softc *sc)
5341 {
5342 int error, qid;
5343
5344 /* Switch to using ICT interrupt mode. */
5345 iwn5000_ict_reset(sc);
5346
5347 if ((error = iwn_nic_lock(sc)) != 0)
5348 return error;
5349
5350 /* Clear TX scheduler state in SRAM. */
5351 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5352 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0,
5353 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t));
5354
5355 /* Set physical address of TX scheduler rings (1KB aligned). */
5356 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5357
5358 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5359
5360 /* Enable chain mode for all queues, except command queue. */
5361 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef);
5362 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0);
5363
5364 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) {
5365 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0);
5366 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5367
5368 iwn_mem_write(sc, sc->sched_base +
5369 IWN5000_SCHED_QUEUE_OFFSET(qid), 0);
5370 /* Set scheduler window size and frame limit. */
5371 iwn_mem_write(sc, sc->sched_base +
5372 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5373 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5374 }
5375
5376 /* Enable interrupts for all our 20 queues. */
5377 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff);
5378 /* Identify TX FIFO rings (0-7). */
5379 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff);
5380
5381 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
5382 for (qid = 0; qid < 7; qid++) {
5383 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
5384 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5385 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]);
5386 }
5387 iwn_nic_unlock(sc);
5388
5389 /* Configure WiMAX coexistence for combo adapters. */
5390 error = iwn5000_send_wimax_coex(sc);
5391 if (error != 0) {
5392 aprint_error_dev(sc->sc_dev,
5393 "could not configure WiMAX coexistence\n");
5394 return error;
5395 }
5396 if (sc->hw_type != IWN_HW_REV_TYPE_5150) {
5397 struct iwn5000_phy_calib_crystal cmd;
5398
5399 /* Perform crystal calibration. */
5400 memset(&cmd, 0, sizeof cmd);
5401 cmd.code = IWN5000_PHY_CALIB_CRYSTAL;
5402 cmd.ngroups = 1;
5403 cmd.isvalid = 1;
5404 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff;
5405 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff;
5406 DPRINTF(("sending crystal calibration %d, %d\n",
5407 cmd.cap_pin[0], cmd.cap_pin[1]));
5408 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5409 if (error != 0) {
5410 aprint_error_dev(sc->sc_dev,
5411 "crystal calibration failed\n");
5412 return error;
5413 }
5414 }
5415 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) {
5416 /* Query calibration from the initialization firmware. */
5417 if ((error = iwn5000_query_calibration(sc)) != 0) {
5418 aprint_error_dev(sc->sc_dev,
5419 "could not query calibration\n");
5420 return error;
5421 }
5422 /*
5423 * We have the calibration results now, reboot with the
5424 * runtime firmware (call ourselves recursively!)
5425 */
5426 iwn_hw_stop(sc);
5427 error = iwn_hw_init(sc);
5428 } else {
5429 /* Send calibration results to runtime firmware. */
5430 error = iwn5000_send_calibration(sc);
5431 }
5432 return error;
5433 }
5434
5435 /*
5436 * The firmware boot code is small and is intended to be copied directly into
5437 * the NIC internal memory (no DMA transfer).
5438 */
5439 static int
iwn4965_load_bootcode(struct iwn_softc * sc,const uint8_t * ucode,int size)5440 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size)
5441 {
5442 int error, ntries;
5443
5444 size /= sizeof (uint32_t);
5445
5446 if ((error = iwn_nic_lock(sc)) != 0)
5447 return error;
5448
5449 /* Copy microcode image into NIC memory. */
5450 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE,
5451 (const uint32_t *)ucode, size);
5452
5453 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0);
5454 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE);
5455 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size);
5456
5457 /* Start boot load now. */
5458 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START);
5459
5460 /* Wait for transfer to complete. */
5461 for (ntries = 0; ntries < 1000; ntries++) {
5462 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) &
5463 IWN_BSM_WR_CTRL_START))
5464 break;
5465 DELAY(10);
5466 }
5467 if (ntries == 1000) {
5468 aprint_error_dev(sc->sc_dev,
5469 "could not load boot firmware\n");
5470 iwn_nic_unlock(sc);
5471 return ETIMEDOUT;
5472 }
5473
5474 /* Enable boot after power up. */
5475 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN);
5476
5477 iwn_nic_unlock(sc);
5478 return 0;
5479 }
5480
5481 static int
iwn4965_load_firmware(struct iwn_softc * sc)5482 iwn4965_load_firmware(struct iwn_softc *sc)
5483 {
5484 struct iwn_fw_info *fw = &sc->fw;
5485 struct iwn_dma_info *dma = &sc->fw_dma;
5486 int error;
5487
5488 /* Copy initialization sections into pre-allocated DMA-safe memory. */
5489 memcpy(dma->vaddr, fw->init.data, fw->init.datasz);
5490 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz,
5491 BUS_DMASYNC_PREWRITE);
5492 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ,
5493 fw->init.text, fw->init.textsz);
5494 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ,
5495 fw->init.textsz, BUS_DMASYNC_PREWRITE);
5496
5497 /* Tell adapter where to find initialization sections. */
5498 if ((error = iwn_nic_lock(sc)) != 0)
5499 return error;
5500 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
5501 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz);
5502 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
5503 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
5504 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz);
5505 iwn_nic_unlock(sc);
5506
5507 /* Load firmware boot code. */
5508 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz);
5509 if (error != 0) {
5510 aprint_error_dev(sc->sc_dev,
5511 "could not load boot firmware\n");
5512 return error;
5513 }
5514 /* Now press "execute". */
5515 IWN_WRITE(sc, IWN_RESET, 0);
5516
5517 /* Wait at most one second for first alive notification. */
5518 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) {
5519 aprint_error_dev(sc->sc_dev,
5520 "timeout waiting for adapter to initialize\n");
5521 return error;
5522 }
5523
5524 /* Retrieve current temperature for initial TX power calibration. */
5525 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz;
5526 sc->temp = iwn4965_get_temperature(sc);
5527
5528 /* Copy runtime sections into pre-allocated DMA-safe memory. */
5529 memcpy(dma->vaddr, fw->main.data, fw->main.datasz);
5530 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz,
5531 BUS_DMASYNC_PREWRITE);
5532 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ,
5533 fw->main.text, fw->main.textsz);
5534 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ,
5535 fw->main.textsz, BUS_DMASYNC_PREWRITE);
5536
5537 /* Tell adapter where to find runtime sections. */
5538 if ((error = iwn_nic_lock(sc)) != 0)
5539 return error;
5540 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
5541 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz);
5542 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
5543 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
5544 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE,
5545 IWN_FW_UPDATED | fw->main.textsz);
5546 iwn_nic_unlock(sc);
5547
5548 return 0;
5549 }
5550
5551 static int
iwn5000_load_firmware_section(struct iwn_softc * sc,uint32_t dst,const uint8_t * section,int size)5552 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst,
5553 const uint8_t *section, int size)
5554 {
5555 struct iwn_dma_info *dma = &sc->fw_dma;
5556 int error;
5557
5558 /* Copy firmware section into pre-allocated DMA-safe memory. */
5559 memcpy(dma->vaddr, section, size);
5560 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE);
5561
5562 if ((error = iwn_nic_lock(sc)) != 0)
5563 return error;
5564
5565 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
5566 IWN_FH_TX_CONFIG_DMA_PAUSE);
5567
5568 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst);
5569 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL),
5570 IWN_LOADDR(dma->paddr));
5571 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL),
5572 IWN_HIADDR(dma->paddr) << 28 | size);
5573 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL),
5574 IWN_FH_TXBUF_STATUS_TBNUM(1) |
5575 IWN_FH_TXBUF_STATUS_TBIDX(1) |
5576 IWN_FH_TXBUF_STATUS_TFBD_VALID);
5577
5578 /* Kick Flow Handler to start DMA transfer. */
5579 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
5580 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD);
5581
5582 iwn_nic_unlock(sc);
5583
5584 /* Wait at most five seconds for FH DMA transfer to complete. */
5585 return tsleep(sc, PCATCH, "iwninit", 5 * hz);
5586 }
5587
5588 static int
iwn5000_load_firmware(struct iwn_softc * sc)5589 iwn5000_load_firmware(struct iwn_softc *sc)
5590 {
5591 struct iwn_fw_part *fw;
5592 int error;
5593
5594 /* Load the initialization firmware on first boot only. */
5595 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ?
5596 &sc->fw.main : &sc->fw.init;
5597
5598 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE,
5599 fw->text, fw->textsz);
5600 if (error != 0) {
5601 aprint_error_dev(sc->sc_dev,
5602 "could not load firmware %s section\n", ".text");
5603 return error;
5604 }
5605 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE,
5606 fw->data, fw->datasz);
5607 if (error != 0) {
5608 aprint_error_dev(sc->sc_dev,
5609 "could not load firmware %s section\n", ".data");
5610 return error;
5611 }
5612
5613 /* Now press "execute". */
5614 IWN_WRITE(sc, IWN_RESET, 0);
5615 return 0;
5616 }
5617
5618 /*
5619 * Extract text and data sections from a legacy firmware image.
5620 */
5621 static int
iwn_read_firmware_leg(struct iwn_softc * sc,struct iwn_fw_info * fw)5622 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw)
5623 {
5624 const uint32_t *ptr;
5625 size_t hdrlen = 24;
5626 uint32_t rev;
5627
5628 ptr = (const uint32_t *)fw->data;
5629 rev = le32toh(*ptr++);
5630
5631 /* Check firmware API version. */
5632 if (IWN_FW_API(rev) <= 1) {
5633 aprint_error_dev(sc->sc_dev,
5634 "bad firmware, need API version >=2\n");
5635 return EINVAL;
5636 }
5637 if (IWN_FW_API(rev) >= 3) {
5638 /* Skip build number (version 2 header). */
5639 hdrlen += 4;
5640 ptr++;
5641 }
5642 if (fw->size < hdrlen) {
5643 aprint_error_dev(sc->sc_dev,
5644 "firmware too short: %zd bytes\n", fw->size);
5645 return EINVAL;
5646 }
5647 fw->main.textsz = le32toh(*ptr++);
5648 fw->main.datasz = le32toh(*ptr++);
5649 fw->init.textsz = le32toh(*ptr++);
5650 fw->init.datasz = le32toh(*ptr++);
5651 fw->boot.textsz = le32toh(*ptr++);
5652
5653 /* Check that all firmware sections fit. */
5654 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz +
5655 fw->init.textsz + fw->init.datasz + fw->boot.textsz) {
5656 aprint_error_dev(sc->sc_dev,
5657 "firmware too short: %zd bytes\n", fw->size);
5658 return EINVAL;
5659 }
5660
5661 /* Get pointers to firmware sections. */
5662 fw->main.text = (const uint8_t *)ptr;
5663 fw->main.data = fw->main.text + fw->main.textsz;
5664 fw->init.text = fw->main.data + fw->main.datasz;
5665 fw->init.data = fw->init.text + fw->init.textsz;
5666 fw->boot.text = fw->init.data + fw->init.datasz;
5667 return 0;
5668 }
5669
5670 /*
5671 * Extract text and data sections from a TLV firmware image.
5672 */
5673 static int
iwn_read_firmware_tlv(struct iwn_softc * sc,struct iwn_fw_info * fw,uint16_t alt)5674 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw,
5675 uint16_t alt)
5676 {
5677 const struct iwn_fw_tlv_hdr *hdr;
5678 const struct iwn_fw_tlv *tlv;
5679 const uint8_t *ptr, *end;
5680 uint64_t altmask;
5681 uint32_t len;
5682
5683 if (fw->size < sizeof (*hdr)) {
5684 aprint_error_dev(sc->sc_dev,
5685 "firmware too short: %zd bytes\n", fw->size);
5686 return EINVAL;
5687 }
5688 hdr = (const struct iwn_fw_tlv_hdr *)fw->data;
5689 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) {
5690 aprint_error_dev(sc->sc_dev,
5691 "bad firmware signature 0x%08x\n", le32toh(hdr->signature));
5692 return EINVAL;
5693 }
5694 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr,
5695 le32toh(hdr->build)));
5696
5697 /*
5698 * Select the closest supported alternative that is less than
5699 * or equal to the specified one.
5700 */
5701 altmask = le64toh(hdr->altmask);
5702 while (alt > 0 && !(altmask & (1ULL << alt)))
5703 alt--; /* Downgrade. */
5704 DPRINTF(("using alternative %d\n", alt));
5705
5706 ptr = (const uint8_t *)(hdr + 1);
5707 end = (const uint8_t *)(fw->data + fw->size);
5708
5709 /* Parse type-length-value fields. */
5710 while (ptr + sizeof (*tlv) <= end) {
5711 tlv = (const struct iwn_fw_tlv *)ptr;
5712 len = le32toh(tlv->len);
5713
5714 ptr += sizeof (*tlv);
5715 if (ptr + len > end) {
5716 aprint_error_dev(sc->sc_dev,
5717 "firmware too short: %zd bytes\n", fw->size);
5718 return EINVAL;
5719 }
5720 /* Skip other alternatives. */
5721 if (tlv->alt != 0 && tlv->alt != htole16(alt))
5722 goto next;
5723
5724 switch (le16toh(tlv->type)) {
5725 case IWN_FW_TLV_MAIN_TEXT:
5726 fw->main.text = ptr;
5727 fw->main.textsz = len;
5728 break;
5729 case IWN_FW_TLV_MAIN_DATA:
5730 fw->main.data = ptr;
5731 fw->main.datasz = len;
5732 break;
5733 case IWN_FW_TLV_INIT_TEXT:
5734 fw->init.text = ptr;
5735 fw->init.textsz = len;
5736 break;
5737 case IWN_FW_TLV_INIT_DATA:
5738 fw->init.data = ptr;
5739 fw->init.datasz = len;
5740 break;
5741 case IWN_FW_TLV_BOOT_TEXT:
5742 fw->boot.text = ptr;
5743 fw->boot.textsz = len;
5744 break;
5745 case IWN_FW_TLV_ENH_SENS:
5746 if (len != 0) {
5747 aprint_error_dev(sc->sc_dev,
5748 "TLV type %d has invalid size %u\n",
5749 le16toh(tlv->type), len);
5750 goto next;
5751 }
5752 sc->sc_flags |= IWN_FLAG_ENH_SENS;
5753 break;
5754 case IWN_FW_TLV_PHY_CALIB:
5755 if (len != sizeof(uint32_t)) {
5756 aprint_error_dev(sc->sc_dev,
5757 "TLV type %d has invalid size %u\n",
5758 le16toh(tlv->type), len);
5759 goto next;
5760 }
5761 if (le32toh(*ptr) <= IWN5000_PHY_CALIB_MAX) {
5762 sc->reset_noise_gain = le32toh(*ptr);
5763 sc->noise_gain = le32toh(*ptr) + 1;
5764 }
5765 break;
5766 case IWN_FW_TLV_FLAGS:
5767 if (len < sizeof(uint32_t))
5768 break;
5769 if (len % sizeof(uint32_t))
5770 break;
5771 sc->tlv_feature_flags = le32toh(*ptr);
5772 DPRINTF(("feature: 0x%08x\n", sc->tlv_feature_flags));
5773 break;
5774 default:
5775 DPRINTF(("TLV type %d not handled\n",
5776 le16toh(tlv->type)));
5777 break;
5778 }
5779 next: /* TLV fields are 32-bit aligned. */
5780 ptr += (len + 3) & ~3;
5781 }
5782 return 0;
5783 }
5784
5785 static int
iwn_read_firmware(struct iwn_softc * sc)5786 iwn_read_firmware(struct iwn_softc *sc)
5787 {
5788 struct iwn_fw_info *fw = &sc->fw;
5789 firmware_handle_t fwh;
5790 int error;
5791
5792 /*
5793 * Some PHY calibration commands are firmware-dependent; these
5794 * are the default values that will be overridden if
5795 * necessary.
5796 */
5797 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN;
5798 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN;
5799
5800 /* Initialize for error returns */
5801 fw->data = NULL;
5802 fw->size = 0;
5803
5804 /* Open firmware image. */
5805 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) {
5806 aprint_error_dev(sc->sc_dev,
5807 "could not get firmware handle %s\n", sc->fwname);
5808 return error;
5809 }
5810 fw->size = firmware_get_size(fwh);
5811 if (fw->size < sizeof (uint32_t)) {
5812 aprint_error_dev(sc->sc_dev,
5813 "firmware too short: %zd bytes\n", fw->size);
5814 firmware_close(fwh);
5815 return EINVAL;
5816 }
5817
5818 /* Read the firmware. */
5819 fw->data = firmware_malloc(fw->size);
5820 if (fw->data == NULL) {
5821 aprint_error_dev(sc->sc_dev,
5822 "not enough memory to stock firmware %s\n", sc->fwname);
5823 firmware_close(fwh);
5824 return ENOMEM;
5825 }
5826 error = firmware_read(fwh, 0, fw->data, fw->size);
5827 firmware_close(fwh);
5828 if (error != 0) {
5829 aprint_error_dev(sc->sc_dev,
5830 "could not read firmware %s\n", sc->fwname);
5831 goto out;
5832 }
5833
5834 /* Retrieve text and data sections. */
5835 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */
5836 error = iwn_read_firmware_leg(sc, fw);
5837 else
5838 error = iwn_read_firmware_tlv(sc, fw, 1);
5839 if (error != 0) {
5840 aprint_error_dev(sc->sc_dev,
5841 "could not read firmware sections\n");
5842 goto out;
5843 }
5844
5845 /* Make sure text and data sections fit in hardware memory. */
5846 if (fw->main.textsz > sc->fw_text_maxsz ||
5847 fw->main.datasz > sc->fw_data_maxsz ||
5848 fw->init.textsz > sc->fw_text_maxsz ||
5849 fw->init.datasz > sc->fw_data_maxsz ||
5850 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ ||
5851 (fw->boot.textsz & 3) != 0) {
5852 aprint_error_dev(sc->sc_dev,
5853 "firmware sections too large\n");
5854 goto out;
5855 }
5856
5857 /* We can proceed with loading the firmware. */
5858 return 0;
5859 out:
5860 firmware_free(fw->data, fw->size);
5861 fw->data = NULL;
5862 fw->size = 0;
5863 return error ? error : EINVAL;
5864 }
5865
5866 static int
iwn_clock_wait(struct iwn_softc * sc)5867 iwn_clock_wait(struct iwn_softc *sc)
5868 {
5869 int ntries;
5870
5871 /* Set "initialization complete" bit. */
5872 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
5873
5874 /* Wait for clock stabilization. */
5875 for (ntries = 0; ntries < 2500; ntries++) {
5876 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY)
5877 return 0;
5878 DELAY(10);
5879 }
5880 aprint_error_dev(sc->sc_dev,
5881 "timeout waiting for clock stabilization\n");
5882 return ETIMEDOUT;
5883 }
5884
5885 static int
iwn_apm_init(struct iwn_softc * sc)5886 iwn_apm_init(struct iwn_softc *sc)
5887 {
5888 pcireg_t reg;
5889 int error;
5890
5891 /* Disable L0s exit timer (NMI bug workaround). */
5892 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER);
5893 /* Don't wait for ICH L0s (ICH bug workaround). */
5894 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX);
5895
5896 /* Set FH wait threshold to max (HW bug under stress workaround). */
5897 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000);
5898
5899 /* Enable HAP INTA to move adapter from L1a to L0s. */
5900 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A);
5901
5902 /* Retrieve PCIe Active State Power Management (ASPM). */
5903 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
5904 sc->sc_cap_off + PCIE_LCSR);
5905 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
5906 if (reg & PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */
5907 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
5908 else
5909 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
5910
5911 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
5912 sc->hw_type <= IWN_HW_REV_TYPE_1000)
5913 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT);
5914
5915 /* Wait for clock stabilization before accessing prph. */
5916 if ((error = iwn_clock_wait(sc)) != 0)
5917 return error;
5918
5919 if ((error = iwn_nic_lock(sc)) != 0)
5920 return error;
5921 if (sc->hw_type == IWN_HW_REV_TYPE_4965) {
5922 /* Enable DMA and BSM (Bootstrap State Machine). */
5923 iwn_prph_write(sc, IWN_APMG_CLK_EN,
5924 IWN_APMG_CLK_CTRL_DMA_CLK_RQT |
5925 IWN_APMG_CLK_CTRL_BSM_CLK_RQT);
5926 } else {
5927 /* Enable DMA. */
5928 iwn_prph_write(sc, IWN_APMG_CLK_EN,
5929 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
5930 }
5931 DELAY(20);
5932 /* Disable L1-Active. */
5933 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS);
5934 iwn_nic_unlock(sc);
5935
5936 return 0;
5937 }
5938
5939 static void
iwn_apm_stop_master(struct iwn_softc * sc)5940 iwn_apm_stop_master(struct iwn_softc *sc)
5941 {
5942 int ntries;
5943
5944 /* Stop busmaster DMA activity. */
5945 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER);
5946 for (ntries = 0; ntries < 100; ntries++) {
5947 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED)
5948 return;
5949 DELAY(10);
5950 }
5951 aprint_error_dev(sc->sc_dev,
5952 "timeout waiting for master\n");
5953 }
5954
5955 static void
iwn_apm_stop(struct iwn_softc * sc)5956 iwn_apm_stop(struct iwn_softc *sc)
5957 {
5958 iwn_apm_stop_master(sc);
5959
5960 /* Reset the entire device. */
5961 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW);
5962 DELAY(10);
5963 /* Clear "initialization complete" bit. */
5964 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
5965 }
5966
5967 static int
iwn4965_nic_config(struct iwn_softc * sc)5968 iwn4965_nic_config(struct iwn_softc *sc)
5969 {
5970 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) {
5971 /*
5972 * I don't believe this to be correct but this is what the
5973 * vendor driver is doing. Probably the bits should not be
5974 * shifted in IWN_RFCFG_*.
5975 */
5976 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5977 IWN_RFCFG_TYPE(sc->rfcfg) |
5978 IWN_RFCFG_STEP(sc->rfcfg) |
5979 IWN_RFCFG_DASH(sc->rfcfg));
5980 }
5981 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5982 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
5983 return 0;
5984 }
5985
5986 static int
iwn5000_nic_config(struct iwn_softc * sc)5987 iwn5000_nic_config(struct iwn_softc *sc)
5988 {
5989 uint32_t tmp;
5990 int error;
5991
5992 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) {
5993 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5994 IWN_RFCFG_TYPE(sc->rfcfg) |
5995 IWN_RFCFG_STEP(sc->rfcfg) |
5996 IWN_RFCFG_DASH(sc->rfcfg));
5997 }
5998 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5999 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
6000
6001 if ((error = iwn_nic_lock(sc)) != 0)
6002 return error;
6003 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS);
6004
6005 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
6006 /*
6007 * Select first Switching Voltage Regulator (1.32V) to
6008 * solve a stability issue related to noisy DC2DC line
6009 * in the silicon of 1000 Series.
6010 */
6011 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR);
6012 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK;
6013 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32;
6014 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp);
6015 }
6016 iwn_nic_unlock(sc);
6017
6018 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) {
6019 /* Use internal power amplifier only. */
6020 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA);
6021 }
6022 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 ||
6023 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) {
6024 /* Indicate that ROM calibration version is >=6. */
6025 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6);
6026 }
6027 if (sc->hw_type == IWN_HW_REV_TYPE_6005)
6028 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2);
6029 if (sc->hw_type == IWN_HW_REV_TYPE_2030 ||
6030 sc->hw_type == IWN_HW_REV_TYPE_2000 ||
6031 sc->hw_type == IWN_HW_REV_TYPE_135 ||
6032 sc->hw_type == IWN_HW_REV_TYPE_105)
6033 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_IQ_INVERT);
6034 return 0;
6035 }
6036
6037 /*
6038 * Take NIC ownership over Intel Active Management Technology (AMT).
6039 */
6040 static int
iwn_hw_prepare(struct iwn_softc * sc)6041 iwn_hw_prepare(struct iwn_softc *sc)
6042 {
6043 int ntries;
6044
6045 /* Check if hardware is ready. */
6046 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
6047 for (ntries = 0; ntries < 5; ntries++) {
6048 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
6049 IWN_HW_IF_CONFIG_NIC_READY)
6050 return 0;
6051 DELAY(10);
6052 }
6053
6054 /* Hardware not ready, force into ready state. */
6055 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE);
6056 for (ntries = 0; ntries < 15000; ntries++) {
6057 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) &
6058 IWN_HW_IF_CONFIG_PREPARE_DONE))
6059 break;
6060 DELAY(10);
6061 }
6062 if (ntries == 15000)
6063 return ETIMEDOUT;
6064
6065 /* Hardware should be ready now. */
6066 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
6067 for (ntries = 0; ntries < 5; ntries++) {
6068 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
6069 IWN_HW_IF_CONFIG_NIC_READY)
6070 return 0;
6071 DELAY(10);
6072 }
6073 return ETIMEDOUT;
6074 }
6075
6076 static int
iwn_hw_init(struct iwn_softc * sc)6077 iwn_hw_init(struct iwn_softc *sc)
6078 {
6079 struct iwn_ops *ops = &sc->ops;
6080 int error, chnl, qid;
6081
6082 /* Clear pending interrupts. */
6083 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6084
6085 if ((error = iwn_apm_init(sc)) != 0) {
6086 aprint_error_dev(sc->sc_dev,
6087 "could not power ON adapter\n");
6088 return error;
6089 }
6090
6091 /* Select VMAIN power source. */
6092 if ((error = iwn_nic_lock(sc)) != 0)
6093 return error;
6094 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK);
6095 iwn_nic_unlock(sc);
6096
6097 /* Perform adapter-specific initialization. */
6098 if ((error = ops->nic_config(sc)) != 0)
6099 return error;
6100
6101 /* Initialize RX ring. */
6102 if ((error = iwn_nic_lock(sc)) != 0)
6103 return error;
6104 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
6105 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0);
6106 /* Set physical address of RX ring (256-byte aligned). */
6107 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8);
6108 /* Set physical address of RX status (16-byte aligned). */
6109 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4);
6110 /* Enable RX. */
6111 IWN_WRITE(sc, IWN_FH_RX_CONFIG,
6112 IWN_FH_RX_CONFIG_ENA |
6113 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */
6114 IWN_FH_RX_CONFIG_IRQ_DST_HOST |
6115 IWN_FH_RX_CONFIG_SINGLE_FRAME |
6116 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) |
6117 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG));
6118 iwn_nic_unlock(sc);
6119 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7);
6120
6121 if ((error = iwn_nic_lock(sc)) != 0)
6122 return error;
6123
6124 /* Initialize TX scheduler. */
6125 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
6126
6127 /* Set physical address of "keep warm" page (16-byte aligned). */
6128 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4);
6129
6130 /* Initialize TX rings. */
6131 for (qid = 0; qid < sc->ntxqs; qid++) {
6132 struct iwn_tx_ring *txq = &sc->txq[qid];
6133
6134 /* Set physical address of TX ring (256-byte aligned). */
6135 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid),
6136 txq->desc_dma.paddr >> 8);
6137 }
6138 iwn_nic_unlock(sc);
6139
6140 /* Enable DMA channels. */
6141 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
6142 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl),
6143 IWN_FH_TX_CONFIG_DMA_ENA |
6144 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA);
6145 }
6146
6147 /* Clear "radio off" and "commands blocked" bits. */
6148 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6149 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED);
6150
6151 /* Clear pending interrupts. */
6152 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6153 /* Enable interrupt coalescing. */
6154 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8);
6155 /* Enable interrupts. */
6156 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6157
6158 /* _Really_ make sure "radio off" bit is cleared! */
6159 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6160 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6161
6162 /* Enable shadow registers. */
6163 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
6164 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff);
6165
6166 if ((error = ops->load_firmware(sc)) != 0) {
6167 aprint_error_dev(sc->sc_dev,
6168 "could not load firmware\n");
6169 return error;
6170 }
6171 /* Wait at most one second for firmware alive notification. */
6172 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) {
6173 aprint_error_dev(sc->sc_dev,
6174 "timeout waiting for adapter to initialize\n");
6175 return error;
6176 }
6177 /* Do post-firmware initialization. */
6178 return ops->post_alive(sc);
6179 }
6180
6181 static void
iwn_hw_stop(struct iwn_softc * sc)6182 iwn_hw_stop(struct iwn_softc *sc)
6183 {
6184 int chnl, qid, ntries;
6185
6186 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO);
6187
6188 /* Disable interrupts. */
6189 IWN_WRITE(sc, IWN_INT_MASK, 0);
6190 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6191 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff);
6192 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6193
6194 /* Make sure we no longer hold the NIC lock. */
6195 iwn_nic_unlock(sc);
6196
6197 /* Stop TX scheduler. */
6198 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
6199
6200 /* Stop all DMA channels. */
6201 if (iwn_nic_lock(sc) == 0) {
6202 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
6203 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0);
6204 for (ntries = 0; ntries < 200; ntries++) {
6205 if (IWN_READ(sc, IWN_FH_TX_STATUS) &
6206 IWN_FH_TX_STATUS_IDLE(chnl))
6207 break;
6208 DELAY(10);
6209 }
6210 }
6211 iwn_nic_unlock(sc);
6212 }
6213
6214 /* Stop RX ring. */
6215 iwn_reset_rx_ring(sc, &sc->rxq);
6216
6217 /* Reset all TX rings. */
6218 for (qid = 0; qid < sc->ntxqs; qid++)
6219 iwn_reset_tx_ring(sc, &sc->txq[qid]);
6220
6221 if (iwn_nic_lock(sc) == 0) {
6222 iwn_prph_write(sc, IWN_APMG_CLK_DIS,
6223 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
6224 iwn_nic_unlock(sc);
6225 }
6226 DELAY(5);
6227 /* Power OFF adapter. */
6228 iwn_apm_stop(sc);
6229 }
6230
6231 static int
iwn_init(struct ifnet * ifp)6232 iwn_init(struct ifnet *ifp)
6233 {
6234 struct iwn_softc *sc = ifp->if_softc;
6235 struct ieee80211com *ic = &sc->sc_ic;
6236 int error;
6237
6238 mutex_enter(&sc->sc_mtx);
6239 if (sc->sc_flags & IWN_FLAG_HW_INITED)
6240 goto out;
6241 if ((error = iwn_hw_prepare(sc)) != 0) {
6242 aprint_error_dev(sc->sc_dev,
6243 "hardware not ready\n");
6244 goto fail;
6245 }
6246
6247 /* Check that the radio is not disabled by hardware switch. */
6248 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) {
6249 aprint_error_dev(sc->sc_dev,
6250 "radio is disabled by hardware switch\n");
6251 error = EPERM; /* :-) */
6252 goto fail;
6253 }
6254
6255 /* Read firmware images from the filesystem. */
6256 if ((error = iwn_read_firmware(sc)) != 0) {
6257 aprint_error_dev(sc->sc_dev,
6258 "could not read firmware\n");
6259 goto fail;
6260 }
6261
6262 /* Initialize interrupt mask to default value. */
6263 sc->int_mask = IWN_INT_MASK_DEF;
6264 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6265
6266 /* Initialize hardware and upload firmware. */
6267 KASSERT(sc->fw.data != NULL && sc->fw.size > 0);
6268 error = iwn_hw_init(sc);
6269 firmware_free(sc->fw.data, sc->fw.size);
6270 sc->fw.data = NULL;
6271 sc->fw.size = 0;
6272 if (error != 0) {
6273 aprint_error_dev(sc->sc_dev,
6274 "could not initialize hardware\n");
6275 goto fail;
6276 }
6277
6278 /* Configure adapter now that it is ready. */
6279 if ((error = iwn_config(sc)) != 0) {
6280 aprint_error_dev(sc->sc_dev,
6281 "could not configure device\n");
6282 goto fail;
6283 }
6284
6285 ifp->if_flags &= ~IFF_OACTIVE;
6286 ifp->if_flags |= IFF_RUNNING;
6287
6288 if (ic->ic_opmode != IEEE80211_M_MONITOR)
6289 ieee80211_begin_scan(ic, 0);
6290 else
6291 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
6292
6293 sc->sc_flags |= IWN_FLAG_HW_INITED;
6294 out:
6295 mutex_exit(&sc->sc_mtx);
6296 return 0;
6297
6298 fail: mutex_exit(&sc->sc_mtx);
6299 iwn_stop(ifp, 1);
6300 return error;
6301 }
6302
6303 static void
iwn_stop(struct ifnet * ifp,int disable)6304 iwn_stop(struct ifnet *ifp, int disable)
6305 {
6306 struct iwn_softc *sc = ifp->if_softc;
6307 struct ieee80211com *ic = &sc->sc_ic;
6308
6309 if (!disable)
6310 mutex_enter(&sc->sc_mtx);
6311 sc->sc_flags &= ~IWN_FLAG_HW_INITED;
6312 ifp->if_timer = sc->sc_tx_timer = 0;
6313 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
6314
6315 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
6316
6317 /* Power OFF hardware. */
6318 iwn_hw_stop(sc);
6319
6320 if (!disable)
6321 mutex_exit(&sc->sc_mtx);
6322 }
6323
6324 /*
6325 * XXX MCLGETI alternative
6326 *
6327 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers
6328 * as long as there are available free buffers then it uses MEXTMALLOC.,
6329 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively.
6330 * The MCLGET4K code is used for testing an alternative mbuf cache.
6331 */
6332
6333 static struct mbuf *
MCLGETIalt(struct iwn_softc * sc,int how,struct ifnet * ifp __unused,u_int size)6334 MCLGETIalt(struct iwn_softc *sc, int how,
6335 struct ifnet *ifp __unused, u_int size)
6336 {
6337 struct mbuf *m;
6338 #ifdef IWN_USE_RBUF
6339 struct iwn_rbuf *rbuf;
6340 #endif
6341
6342 MGETHDR(m, how, MT_DATA);
6343 if (m == NULL)
6344 return NULL;
6345
6346 #ifdef IWN_USE_RBUF
6347 if (sc->rxq.nb_free_entries > 0 &&
6348 (rbuf = iwn_alloc_rbuf(sc)) != NULL) {
6349 /* Attach buffer to mbuf header. */
6350 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf);
6351 m->m_flags |= M_EXT_RW;
6352 }
6353 else {
6354 MEXTMALLOC(m, size, how);
6355 if ((m->m_flags & M_EXT) == 0) {
6356 m_freem(m);
6357 return NULL;
6358 }
6359 }
6360
6361 #else
6362 #ifdef MCLGET4K
6363 if (size == 4096)
6364 MCLGET4K(m, how);
6365 else
6366 panic("size must be 4k");
6367 #else
6368 MEXTMALLOC(m, size, how);
6369 #endif
6370 if ((m->m_flags & M_EXT) == 0) {
6371 m_freem(m);
6372 return NULL;
6373 }
6374 #endif
6375
6376 return m;
6377 }
6378
6379 #ifdef IWN_USE_RBUF
6380 static struct iwn_rbuf *
iwn_alloc_rbuf(struct iwn_softc * sc)6381 iwn_alloc_rbuf(struct iwn_softc *sc)
6382 {
6383 struct iwn_rbuf *rbuf;
6384 mutex_enter(&sc->rxq.freelist_mtx);
6385
6386 rbuf = SLIST_FIRST(&sc->rxq.freelist);
6387 if (rbuf != NULL) {
6388 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next);
6389 sc->rxq.nb_free_entries --;
6390 }
6391 mutex_exit(&sc->rxq.freelist_mtx);
6392 return rbuf;
6393 }
6394
6395 /*
6396 * This is called automatically by the network stack when the mbuf to which
6397 * our RX buffer is attached is freed.
6398 */
6399 static void
iwn_free_rbuf(struct mbuf * m,void * buf,size_t size,void * arg)6400 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg)
6401 {
6402 struct iwn_rbuf *rbuf = arg;
6403 struct iwn_softc *sc = rbuf->sc;
6404
6405 /* Put the RX buffer back in the free list. */
6406 mutex_enter(&sc->rxq.freelist_mtx);
6407 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next);
6408 mutex_exit(&sc->rxq.freelist_mtx);
6409
6410 sc->rxq.nb_free_entries ++;
6411 if (__predict_true(m != NULL))
6412 pool_cache_put(mb_cache, m);
6413 }
6414
6415 static int
iwn_alloc_rpool(struct iwn_softc * sc)6416 iwn_alloc_rpool(struct iwn_softc *sc)
6417 {
6418 struct iwn_rx_ring *ring = &sc->rxq;
6419 struct iwn_rbuf *rbuf;
6420 int i, error;
6421
6422 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET);
6423
6424 /* Allocate a big chunk of DMA'able memory... */
6425 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL,
6426 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE);
6427 if (error != 0) {
6428 aprint_error_dev(sc->sc_dev,
6429 "could not allocate RX buffers DMA memory\n");
6430 return error;
6431 }
6432 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */
6433 SLIST_INIT(&ring->freelist);
6434 for (i = 0; i < IWN_RBUF_COUNT; i++) {
6435 rbuf = &ring->rbuf[i];
6436
6437 rbuf->sc = sc; /* Backpointer for callbacks. */
6438 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE);
6439 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE;
6440
6441 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next);
6442 }
6443 ring->nb_free_entries = IWN_RBUF_COUNT;
6444 return 0;
6445 }
6446
6447 static void
iwn_free_rpool(struct iwn_softc * sc)6448 iwn_free_rpool(struct iwn_softc *sc)
6449 {
6450 iwn_dma_contig_free(&sc->rxq.buf_dma);
6451 }
6452 #endif
6453
6454 /*
6455 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c
6456 * Copyright (c) 2001 Atsushi Onoe
6457 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
6458 * Copyright (c) 2007-2009 Damien Bergamini
6459 * All rights reserved.
6460 */
6461
6462 /*
6463 * Add an SSID element to a frame (see 7.3.2.1).
6464 */
6465 static u_int8_t *
ieee80211_add_ssid(u_int8_t * frm,const u_int8_t * ssid,u_int len)6466 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len)
6467 {
6468 *frm++ = IEEE80211_ELEMID_SSID;
6469 *frm++ = len;
6470 memcpy(frm, ssid, len);
6471 return frm + len;
6472 }
6473
6474 /*
6475 * Add a supported rates element to a frame (see 7.3.2.2).
6476 */
6477 static u_int8_t *
ieee80211_add_rates(u_int8_t * frm,const struct ieee80211_rateset * rs)6478 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs)
6479 {
6480 int nrates;
6481
6482 *frm++ = IEEE80211_ELEMID_RATES;
6483 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE);
6484 *frm++ = nrates;
6485 memcpy(frm, rs->rs_rates, nrates);
6486 return frm + nrates;
6487 }
6488
6489 /*
6490 * Add an extended supported rates element to a frame (see 7.3.2.14).
6491 */
6492 static u_int8_t *
ieee80211_add_xrates(u_int8_t * frm,const struct ieee80211_rateset * rs)6493 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs)
6494 {
6495 int nrates;
6496
6497 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE);
6498
6499 *frm++ = IEEE80211_ELEMID_XRATES;
6500 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE;
6501 *frm++ = nrates;
6502 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates);
6503 return frm + nrates;
6504 }
6505
6506 /*
6507 * XXX: Hack to set the current channel to the value advertised in beacons or
6508 * probe responses. Only used during AP detection.
6509 * XXX: Duplicated from if_iwi.c
6510 */
6511 static void
iwn_fix_channel(struct ieee80211com * ic,struct mbuf * m,struct iwn_rx_stat * stat)6512 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m,
6513 struct iwn_rx_stat *stat)
6514 {
6515 struct iwn_softc *sc = ic->ic_ifp->if_softc;
6516 struct ieee80211_frame *wh;
6517 uint8_t subtype;
6518 uint8_t *frm, *efrm;
6519
6520 wh = mtod(m, struct ieee80211_frame *);
6521
6522 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT)
6523 return;
6524
6525 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
6526
6527 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON &&
6528 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP)
6529 return;
6530
6531 if (sc->sc_flags & IWN_FLAG_SCANNING_5GHZ) {
6532 int chan = le16toh(stat->chan);
6533 if (chan < __arraycount(ic->ic_channels))
6534 ic->ic_curchan = &ic->ic_channels[chan];
6535 return;
6536 }
6537
6538 frm = (uint8_t *)(wh + 1);
6539 efrm = mtod(m, uint8_t *) + m->m_len;
6540
6541 frm += 12; /* skip tstamp, bintval and capinfo fields */
6542 while (frm < efrm) {
6543 if (*frm == IEEE80211_ELEMID_DSPARMS)
6544 #if IEEE80211_CHAN_MAX < 255
6545 if (frm[2] <= IEEE80211_CHAN_MAX)
6546 #endif
6547 ic->ic_curchan = &ic->ic_channels[frm[2]];
6548
6549 frm += frm[1] + 2;
6550 }
6551 }
6552
6553 #ifdef notyetMODULE
6554
6555 MODULE(MODULE_CLASS_DRIVER, if_iwn, "pci");
6556
6557 #ifdef _MODULE
6558 #include "ioconf.c"
6559 #endif
6560
6561 static int
if_iwn_modcmd(modcmd_t cmd,void * data)6562 if_iwn_modcmd(modcmd_t cmd, void *data)
6563 {
6564 int error = 0;
6565
6566 switch (cmd) {
6567 case MODULE_CMD_INIT:
6568 #ifdef _MODULE
6569 error = config_init_component(cfdriver_ioconf_if_iwn,
6570 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn);
6571 #endif
6572 return error;
6573 case MODULE_CMD_FINI:
6574 #ifdef _MODULE
6575 error = config_fini_component(cfdriver_ioconf_if_iwn,
6576 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn);
6577 #endif
6578 return error;
6579 case MODULE_CMD_AUTOUNLOAD:
6580 #ifdef _MODULE
6581 /* XXX This is not optional! */
6582 #endif
6583 return error;
6584 default:
6585 return ENOTTY;
6586 }
6587 }
6588 #endif
6589