1 /* $NetBSD: jmide.c,v 1.21 2016/07/14 10:19:06 msaitoh Exp $ */
2
3 /*
4 * Copyright (c) 2007 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: jmide.c,v 1.21 2016/07/14 10:19:06 msaitoh Exp $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/malloc.h>
33
34 #include <dev/pci/pcivar.h>
35 #include <dev/pci/pcidevs.h>
36 #include <dev/pci/pciidereg.h>
37 #include <dev/pci/pciidevar.h>
38
39 #include <dev/pci/jmide_reg.h>
40
41 #include <dev/ic/ahcisatavar.h>
42
43 #include "jmide.h"
44
45 static const struct jmide_product *jmide_lookup(pcireg_t);
46
47 static int jmide_match(device_t, cfdata_t, void *);
48 static void jmide_attach(device_t, device_t, void *);
49 static int jmide_intr(void *);
50
51 static void jmpata_chip_map(struct pciide_softc*,
52 const struct pci_attach_args*);
53 static void jmpata_setup_channel(struct ata_channel*);
54
55 static int jmahci_print(void *, const char *);
56
57 struct jmide_product {
58 u_int32_t jm_product;
59 int jm_npata;
60 int jm_nsata;
61 };
62
63 static const struct jmide_product jm_products[] = {
64 { PCI_PRODUCT_JMICRON_JMB360,
65 0,
66 1
67 },
68 { PCI_PRODUCT_JMICRON_JMB361,
69 1,
70 1
71 },
72 { PCI_PRODUCT_JMICRON_JMB362,
73 0,
74 2
75 },
76 { PCI_PRODUCT_JMICRON_JMB363,
77 1,
78 2
79 },
80 { PCI_PRODUCT_JMICRON_JMB365,
81 2,
82 1
83 },
84 { PCI_PRODUCT_JMICRON_JMB366,
85 2,
86 2
87 },
88 { PCI_PRODUCT_JMICRON_JMB368,
89 1,
90 0
91 },
92 { 0,
93 0,
94 0
95 }
96 };
97
98 typedef enum {
99 TYPE_INVALID = 0,
100 TYPE_PATA,
101 TYPE_SATA,
102 TYPE_NONE
103 } jmchan_t;
104
105 struct jmide_softc {
106 struct pciide_softc sc_pciide;
107 device_t sc_ahci;
108 int sc_npata;
109 int sc_nsata;
110 jmchan_t sc_chan_type[PCIIDE_NUM_CHANNELS];
111 int sc_chan_swap;
112 };
113
114 struct jmahci_attach_args {
115 const struct pci_attach_args *jma_pa;
116 bus_space_tag_t jma_ahcit;
117 bus_space_handle_t jma_ahcih;
118 };
119
120 #define JM_NAME(sc) (device_xname(sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev))
121
122 CFATTACH_DECL_NEW(jmide, sizeof(struct jmide_softc),
123 jmide_match, jmide_attach, NULL, NULL);
124
125 static const struct jmide_product *
jmide_lookup(pcireg_t id)126 jmide_lookup(pcireg_t id) {
127 const struct jmide_product *jp;
128
129 for (jp = jm_products; jp->jm_product != 0; jp++) {
130 if (jp->jm_product == PCI_PRODUCT(id))
131 return jp;
132 }
133 return NULL;
134 }
135
136 static int
jmide_match(device_t parent,cfdata_t match,void * aux)137 jmide_match(device_t parent, cfdata_t match, void *aux)
138 {
139 struct pci_attach_args *pa = aux;
140
141 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_JMICRON) {
142 if (jmide_lookup(pa->pa_id))
143 return (4); /* higher than ahcisata */
144 }
145 return (0);
146 }
147
148 static void
jmide_attach(device_t parent,device_t self,void * aux)149 jmide_attach(device_t parent, device_t self, void *aux)
150 {
151 struct pci_attach_args *pa = aux;
152 struct jmide_softc *sc = device_private(self);
153 const struct jmide_product *jp;
154 const char *intrstr;
155 pci_intr_handle_t intrhandle;
156 u_int32_t pcictrl0 = pci_conf_read(pa->pa_pc, pa->pa_tag,
157 PCI_JM_CONTROL0);
158 u_int32_t pcictrl1 = pci_conf_read(pa->pa_pc, pa->pa_tag,
159 PCI_JM_CONTROL1);
160 struct pciide_product_desc *pp;
161 int ahci_used = 0;
162 char intrbuf[PCI_INTRSTR_LEN];
163
164 aprint_naive("\n");
165 sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev = self;
166
167 jp = jmide_lookup(pa->pa_id);
168 if (jp == NULL) {
169 aprint_error_dev(self, "jmide_attach: WTF?\n");
170 return;
171 }
172 sc->sc_npata = jp->jm_npata;
173 sc->sc_nsata = jp->jm_nsata;
174
175 pci_aprint_devinfo(pa, "JMICRON PATA/SATA disk controller");
176
177 aprint_normal("%s: ", JM_NAME(sc));
178 if (sc->sc_npata)
179 aprint_normal("%d PATA port%s", sc->sc_npata,
180 (sc->sc_npata > 1) ? "s" : "");
181 if (sc->sc_nsata)
182 aprint_normal("%s%d SATA port%s", sc->sc_npata ? ", " : "",
183 sc->sc_nsata, (sc->sc_nsata > 1) ? "s" : "");
184 aprint_normal("\n");
185
186 if (pci_intr_map(pa, &intrhandle) != 0) {
187 aprint_error("%s: couldn't map interrupt\n", JM_NAME(sc));
188 return;
189 }
190 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf,
191 sizeof(intrbuf));
192 sc->sc_pciide.sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle,
193 IPL_BIO, jmide_intr, sc);
194 if (sc->sc_pciide.sc_pci_ih == NULL) {
195 aprint_error("%s: couldn't establish interrupt", JM_NAME(sc));
196 return;
197 }
198 aprint_normal("%s: interrupting at %s\n", JM_NAME(sc),
199 intrstr ? intrstr : "unknown interrupt");
200
201 if (pcictrl0 & JM_CONTROL0_AHCI_EN) {
202 bus_size_t size;
203 struct jmahci_attach_args jma;
204 u_int32_t saved_pcictrl0;
205 /*
206 * ahci controller enabled; disable sata on pciide and
207 * enable on ahci
208 */
209 saved_pcictrl0 = pcictrl0;
210 pcictrl0 |= JM_CONTROL0_SATA0_AHCI | JM_CONTROL0_SATA1_AHCI;
211 pcictrl0 &= ~(JM_CONTROL0_SATA0_IDE | JM_CONTROL0_SATA1_IDE);
212 pci_conf_write(pa->pa_pc, pa->pa_tag,
213 PCI_JM_CONTROL0, pcictrl0);
214 /* attach ahci controller if on the right function */
215 if ((pa->pa_function == 0 &&
216 (pcictrl0 & JM_CONTROL0_AHCI_F1) == 0) ||
217 (pa->pa_function == 1 &&
218 (pcictrl0 & JM_CONTROL0_AHCI_F1) != 0)) {
219 jma.jma_pa = pa;
220 /* map registers */
221 if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
222 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
223 &jma.jma_ahcit, &jma.jma_ahcih, NULL, &size) != 0) {
224 aprint_error("%s: can't map ahci registers\n",
225 JM_NAME(sc));
226 } else {
227 sc->sc_ahci = config_found_ia(
228 sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev,
229 "jmide_hl", &jma, jmahci_print);
230 }
231 /*
232 * if we couldn't attach an ahci, try to fall back
233 * to pciide. Note that this will not work if IDE
234 * is on function 0 and AHCI on function 1.
235 */
236 if (sc->sc_ahci == NULL) {
237 pcictrl0 = saved_pcictrl0 &
238 ~(JM_CONTROL0_SATA0_AHCI |
239 JM_CONTROL0_SATA1_AHCI |
240 JM_CONTROL0_AHCI_EN);
241 pcictrl0 |= JM_CONTROL0_SATA1_IDE |
242 JM_CONTROL0_SATA0_IDE;
243 pci_conf_write(pa->pa_pc, pa->pa_tag,
244 PCI_JM_CONTROL0, pcictrl0);
245 } else
246 ahci_used = 1;
247 }
248 }
249 sc->sc_chan_swap = ((pcictrl0 & JM_CONTROL0_PCIIDE_CS) != 0);
250 /* compute the type of internal primary channel */
251 if (pcictrl1 & JM_CONTROL1_PATA1_PRI) {
252 if (sc->sc_npata > 1)
253 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_PATA;
254 else
255 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE;
256 } else if (ahci_used == 0 && sc->sc_nsata > 0)
257 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_SATA;
258 else
259 sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE;
260 /* compute the type of internal secondary channel */
261 if (sc->sc_nsata > 1 && ahci_used == 0 &&
262 (pcictrl0 & JM_CONTROL0_PCIIDE0_MS) == 0) {
263 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_SATA;
264 } else {
265 /* only a drive if first PATA enabled */
266 if (sc->sc_npata > 0 && (pcictrl0 & JM_CONTROL0_PATA0_EN)
267 && (pcictrl0 &
268 (sc->sc_chan_swap ? JM_CONTROL0_PATA0_PRI: JM_CONTROL0_PATA0_SEC)))
269 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_PATA;
270 else
271 sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_NONE;
272 }
273
274 if (sc->sc_chan_type[0] == TYPE_NONE &&
275 sc->sc_chan_type[1] == TYPE_NONE)
276 return;
277 if (pa->pa_function == 0 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1))
278 return;
279 if (pa->pa_function == 1 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1) == 0)
280 return;
281 pp = malloc(sizeof(struct pciide_product_desc), M_DEVBUF, M_NOWAIT);
282 if (pp == NULL) {
283 aprint_error("%s: can't malloc sc_pp\n", JM_NAME(sc));
284 return;
285 }
286 aprint_normal("%s: PCI IDE interface used", JM_NAME(sc));
287 pp->ide_product = 0;
288 pp->ide_flags = 0;
289 pp->ide_name = NULL;
290 pp->chip_map = jmpata_chip_map;
291 pciide_common_attach(&sc->sc_pciide, pa, pp);
292 }
293
294 static int
jmide_intr(void * arg)295 jmide_intr(void *arg)
296 {
297 struct jmide_softc *sc = arg;
298 int ret = 0;
299
300 #ifdef NJMAHCI
301 if (sc->sc_ahci)
302 ret |= ahci_intr(device_private(sc->sc_ahci));
303 #endif
304 if (sc->sc_npata)
305 ret |= pciide_pci_intr(&sc->sc_pciide);
306 return ret;
307 }
308
309 static void
jmpata_chip_map(struct pciide_softc * sc,const struct pci_attach_args * pa)310 jmpata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
311 {
312 struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
313 int channel;
314 pcireg_t interface;
315 struct pciide_channel *cp;
316
317 if (pciide_chipen(sc, pa) == 0)
318 return;
319 aprint_verbose("%s: bus-master DMA support present", JM_NAME(jmidesc));
320 pciide_mapreg_dma(sc, pa);
321 aprint_verbose("\n");
322 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
323 if (sc->sc_dma_ok) {
324 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
325 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
326 }
327 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
328 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
329 sc->sc_wdcdev.sc_atac.atac_set_modes = jmpata_setup_channel;
330 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
331 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
332 sc->sc_wdcdev.wdc_maxdrives = 2;
333 wdc_allocate_regs(&sc->sc_wdcdev);
334 /*
335 * can't rely on the PCI_CLASS_REG content if the chip was in raid
336 * mode. We have to fake interface
337 */
338 interface = PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
339 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
340 channel++) {
341 cp = &sc->pciide_channels[channel];
342 if (pciide_chansetup(sc, channel, interface) == 0)
343 continue;
344 aprint_normal("%s: %s channel is ", JM_NAME(jmidesc),
345 PCIIDE_CHANNEL_NAME(channel));
346 switch(jmidesc->sc_chan_type[channel]) {
347 case TYPE_PATA:
348 aprint_normal("PATA");
349 break;
350 case TYPE_SATA:
351 aprint_normal("SATA");
352 break;
353 case TYPE_NONE:
354 aprint_normal("unused");
355 break;
356 default:
357 aprint_normal("impossible");
358 panic("jmide: wrong/uninitialised channel type");
359 }
360 aprint_normal("\n");
361 if (jmidesc->sc_chan_type[channel] == TYPE_NONE) {
362 cp->ata_channel.ch_flags |= ATACH_DISABLED;
363 continue;
364 }
365 pciide_mapchan(pa, cp, interface, pciide_pci_intr);
366 }
367 }
368
369 static void
jmpata_setup_channel(struct ata_channel * chp)370 jmpata_setup_channel(struct ata_channel *chp)
371 {
372 struct ata_drive_datas *drvp;
373 int drive, s;
374 u_int32_t idedma_ctl;
375 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
376 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
377 struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
378 int ide80p;
379
380 /* setup DMA if needed */
381 pciide_channel_dma_setup(cp);
382
383 idedma_ctl = 0;
384
385 /* cable type detect */
386 ide80p = 1;
387 if (chp->ch_channel == (jmidesc->sc_chan_swap ? 1 : 0)) {
388 if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA &&
389 (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL1) &
390 JM_CONTROL1_PATA1_40P))
391 ide80p = 0;
392 } else {
393 if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA &&
394 (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL0) &
395 JM_CONTROL0_PATA0_40P))
396 ide80p = 0;
397 }
398
399 for (drive = 0; drive < 2; drive++) {
400 drvp = &chp->ch_drive[drive];
401 /* If no drive, skip */
402 if (drvp->drive_type == ATA_DRIVET_NONE)
403 continue;
404 if (drvp->drive_flags & ATA_DRIVE_UDMA) {
405 /* use Ultra/DMA */
406 s = splbio();
407 drvp->drive_flags &= ~ATA_DRIVE_DMA;
408 if (drvp->UDMA_mode > 2 && ide80p == 0)
409 drvp->UDMA_mode = 2;
410 splx(s);
411 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
412 } else if (drvp->drive_flags & ATA_DRIVE_DMA) {
413 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
414 }
415 }
416 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */
417 if (idedma_ctl != 0) {
418 /* Add software bits in status register */
419 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL],
420 0, idedma_ctl);
421 }
422 }
423
424 static int
jmahci_print(void * aux,const char * pnp)425 jmahci_print(void *aux, const char *pnp)
426 {
427 if (pnp)
428 aprint_normal("ahcisata at %s", pnp);
429
430 return (UNCONF);
431 }
432
433
434 #ifdef NJMAHCI
435 static int jmahci_match(device_t, cfdata_t, void *);
436 static void jmahci_attach(device_t, device_t, void *);
437 static int jmahci_detach(device_t, int);
438 static bool jmahci_resume(device_t, const pmf_qual_t *);
439
440 CFATTACH_DECL_NEW(jmahci, sizeof(struct ahci_softc),
441 jmahci_match, jmahci_attach, jmahci_detach, NULL);
442
443 static int
jmahci_match(device_t parent,cfdata_t match,void * aux)444 jmahci_match(device_t parent, cfdata_t match, void *aux)
445 {
446 return 1;
447 }
448
449 static void
jmahci_attach(device_t parent,device_t self,void * aux)450 jmahci_attach(device_t parent, device_t self, void *aux)
451 {
452 struct jmahci_attach_args *jma = aux;
453 const struct pci_attach_args *pa = jma->jma_pa;
454 struct ahci_softc *sc = device_private(self);
455 uint32_t ahci_cap;
456
457 aprint_naive(": AHCI disk controller\n");
458 aprint_normal("\n");
459
460 sc->sc_atac.atac_dev = self;
461 sc->sc_ahcit = jma->jma_ahcit;
462 sc->sc_ahcih = jma->jma_ahcih;
463
464 ahci_cap = AHCI_READ(sc, AHCI_CAP);
465
466 if (pci_dma64_available(jma->jma_pa) && (ahci_cap & AHCI_CAP_64BIT))
467 sc->sc_dmat = jma->jma_pa->pa_dmat64;
468 else
469 sc->sc_dmat = jma->jma_pa->pa_dmat;
470
471 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
472 sc->sc_atac_capflags = ATAC_CAP_RAID;
473
474 ahci_attach(sc);
475
476 if (!pmf_device_register(self, NULL, jmahci_resume))
477 aprint_error_dev(self, "couldn't establish power handler\n");
478 }
479
480 static int
jmahci_detach(device_t dv,int flags)481 jmahci_detach(device_t dv, int flags)
482 {
483 struct ahci_softc *sc;
484 sc = device_private(dv);
485
486 int rv;
487
488 if ((rv = ahci_detach(sc, flags)))
489 return rv;
490
491 return 0;
492 }
493
494 static bool
jmahci_resume(device_t dv,const pmf_qual_t * qual)495 jmahci_resume(device_t dv, const pmf_qual_t *qual)
496 {
497 struct ahci_softc *sc;
498 int s;
499
500 sc = device_private(dv);
501
502 s = splbio();
503 ahci_resume(sc);
504 splx(s);
505
506 return true;
507 }
508 #endif
509