1 /* $NetBSD: nouveau_engine_device_nvc0.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $ */
2
3 /*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_device_nvc0.c,v 1.1.1.1 2014/08/06 12:36:24 riastradh Exp $");
29
30 #include <subdev/bios.h>
31 #include <subdev/bus.h>
32 #include <subdev/gpio.h>
33 #include <subdev/i2c.h>
34 #include <subdev/clock.h>
35 #include <subdev/therm.h>
36 #include <subdev/mxm.h>
37 #include <subdev/devinit.h>
38 #include <subdev/mc.h>
39 #include <subdev/timer.h>
40 #include <subdev/fb.h>
41 #include <subdev/ltcg.h>
42 #include <subdev/ibus.h>
43 #include <subdev/instmem.h>
44 #include <subdev/vm.h>
45 #include <subdev/bar.h>
46 #include <subdev/pwr.h>
47 #include <subdev/volt.h>
48
49 #include <engine/device.h>
50 #include <engine/dmaobj.h>
51 #include <engine/fifo.h>
52 #include <engine/software.h>
53 #include <engine/graph.h>
54 #include <engine/vp.h>
55 #include <engine/bsp.h>
56 #include <engine/ppp.h>
57 #include <engine/copy.h>
58 #include <engine/disp.h>
59 #include <engine/perfmon.h>
60
61 int
nvc0_identify(struct nouveau_device * device)62 nvc0_identify(struct nouveau_device *device)
63 {
64 switch (device->chipset) {
65 case 0xc0:
66 device->cname = "GF100";
67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
68 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
69 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
70 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
71 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
72 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
73 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
74 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
75 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
76 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
77 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
78 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
79 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
80 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
81 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
82 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
83 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
84 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
85 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
86 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
87 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
88 device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass;
89 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
90 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
91 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
92 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
93 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
94 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
95 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
96 break;
97 case 0xc4:
98 device->cname = "GF104";
99 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
100 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
101 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
102 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
103 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
104 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
105 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
106 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
107 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
108 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
109 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
110 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
111 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
112 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
113 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
114 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
115 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
116 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
117 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
118 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
119 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
120 device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
121 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
122 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
123 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
124 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
125 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
126 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
127 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
128 break;
129 case 0xc3:
130 device->cname = "GF106";
131 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
132 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
133 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
134 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
135 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
136 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
137 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
138 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
139 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
140 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
141 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
142 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
143 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
144 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
145 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
146 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
147 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
148 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
149 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
150 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
151 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
152 device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
153 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
154 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
155 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
156 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
157 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
158 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
159 break;
160 case 0xce:
161 device->cname = "GF114";
162 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
163 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
164 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
165 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
166 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
167 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
168 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
169 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
170 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
171 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
172 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
173 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
174 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
175 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
176 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
177 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
178 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
179 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
180 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
181 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
182 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
183 device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
184 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
185 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
186 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
187 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
188 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
189 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
190 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
191 break;
192 case 0xcf:
193 device->cname = "GF116";
194 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
195 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
196 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
197 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
198 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
199 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
200 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
201 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
202 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
203 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
204 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
205 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
206 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
207 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
208 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
209 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
210 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
211 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
212 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
213 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
214 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
215 device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
216 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
217 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
218 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
219 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
220 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
221 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
222 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
223 break;
224 case 0xc1:
225 device->cname = "GF108";
226 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
227 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
228 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
229 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
230 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
231 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
232 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
233 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
234 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
235 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
236 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
237 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
238 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
239 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
240 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
241 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
242 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
243 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
244 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
245 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
246 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
247 device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass;
248 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
249 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
250 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
251 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
252 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
253 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
254 break;
255 case 0xc8:
256 device->cname = "GF110";
257 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
258 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
259 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
260 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
261 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
262 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
263 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
264 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
265 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
266 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
267 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
268 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
269 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
270 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
271 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
272 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
273 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
276 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
277 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
278 device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass;
279 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
280 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
281 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
282 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
283 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
284 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
285 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
286 break;
287 case 0xd9:
288 device->cname = "GF119";
289 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
290 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
291 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
292 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
293 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
294 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
295 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
296 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
297 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
298 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
299 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
300 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
301 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
302 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
303 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
304 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
305 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
306 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
307 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
308 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
309 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
310 device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass;
311 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
312 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
313 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
314 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
315 device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
316 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
317 break;
318 case 0xd7:
319 device->cname = "GF117";
320 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
321 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
322 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
323 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
324 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
325 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
326 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
327 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
328 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
329 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
330 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
331 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
332 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
333 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
334 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
335 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
336 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
337 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
338 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
339 device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass;
340 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
341 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
342 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
343 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
344 device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
345 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
346 break;
347 default:
348 nv_fatal(device, "unknown Fermi chipset\n");
349 return -EINVAL;
350 }
351
352 return 0;
353 }
354