1 /* $NetBSD: nouveau_engine_fifo_nv40.c,v 1.2 2016/04/23 14:48:45 riastradh Exp $ */
2
3 /*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: nouveau_engine_fifo_nv40.c,v 1.2 2016/04/23 14:48:45 riastradh Exp $");
29
30 #include <core/os.h>
31 #include <core/class.h>
32 #include <core/engctx.h>
33 #include <core/ramht.h>
34
35 #include <subdev/instmem.h>
36 #include <subdev/instmem/nv04.h>
37 #include <subdev/fb.h>
38
39 #include <engine/fifo.h>
40
41 #include "nv04.h"
42
43 static struct ramfc_desc
44 nv40_ramfc[] = {
45 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
46 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
47 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
48 { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
49 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
50 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_STATE },
51 { 28, 0, 0x18, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
52 { 2, 28, 0x18, 28, 0x002058 },
53 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_ENGINE },
54 { 32, 0, 0x20, 0, NV04_PFIFO_CACHE1_PULL1 },
55 { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
56 { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
57 { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
58 { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_SEMAPHORE },
59 { 32, 0, 0x34, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
60 { 32, 0, 0x38, 0, NV40_PFIFO_GRCTX_INSTANCE },
61 { 17, 0, 0x3c, 0, NV04_PFIFO_DMA_TIMESLICE },
62 { 32, 0, 0x40, 0, 0x0032e4 },
63 { 32, 0, 0x44, 0, 0x0032e8 },
64 { 32, 0, 0x4c, 0, 0x002088 },
65 { 32, 0, 0x50, 0, 0x003300 },
66 { 32, 0, 0x54, 0, 0x00330c },
67 {}
68 };
69
70 /*******************************************************************************
71 * FIFO channel objects
72 ******************************************************************************/
73
74 static int
nv40_fifo_object_attach(struct nouveau_object * parent,struct nouveau_object * object,u32 handle)75 nv40_fifo_object_attach(struct nouveau_object *parent,
76 struct nouveau_object *object, u32 handle)
77 {
78 struct nv04_fifo_priv *priv = (void *)parent->engine;
79 struct nv04_fifo_chan *chan = (void *)parent;
80 u32 context, chid = chan->base.chid;
81 int ret;
82
83 if (nv_iclass(object, NV_GPUOBJ_CLASS))
84 context = nv_gpuobj(object)->addr >> 4;
85 else
86 context = 0x00000004; /* just non-zero */
87
88 switch (nv_engidx(object->engine)) {
89 case NVDEV_ENGINE_DMAOBJ:
90 case NVDEV_ENGINE_SW:
91 context |= 0x00000000;
92 break;
93 case NVDEV_ENGINE_GR:
94 context |= 0x00100000;
95 break;
96 case NVDEV_ENGINE_MPEG:
97 context |= 0x00200000;
98 break;
99 default:
100 return -EINVAL;
101 }
102
103 context |= chid << 23;
104
105 mutex_lock(&nv_subdev(priv)->mutex);
106 ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
107 mutex_unlock(&nv_subdev(priv)->mutex);
108 return ret;
109 }
110
111 static int
nv40_fifo_context_attach(struct nouveau_object * parent,struct nouveau_object * engctx)112 nv40_fifo_context_attach(struct nouveau_object *parent,
113 struct nouveau_object *engctx)
114 {
115 struct nv04_fifo_priv *priv = (void *)parent->engine;
116 struct nv04_fifo_chan *chan = (void *)parent;
117 unsigned long flags;
118 u32 reg, ctx;
119
120 switch (nv_engidx(engctx->engine)) {
121 case NVDEV_ENGINE_SW:
122 return 0;
123 case NVDEV_ENGINE_GR:
124 reg = 0x32e0;
125 ctx = 0x38;
126 break;
127 case NVDEV_ENGINE_MPEG:
128 reg = 0x330c;
129 ctx = 0x54;
130 break;
131 default:
132 return -EINVAL;
133 }
134
135 spin_lock_irqsave(&priv->base.lock, flags);
136 nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4;
137 nv_mask(priv, 0x002500, 0x00000001, 0x00000000);
138
139 if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
140 nv_wr32(priv, reg, nv_engctx(engctx)->addr);
141 nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr);
142
143 nv_mask(priv, 0x002500, 0x00000001, 0x00000001);
144 spin_unlock_irqrestore(&priv->base.lock, flags);
145 return 0;
146 }
147
148 static int
nv40_fifo_context_detach(struct nouveau_object * parent,bool suspend,struct nouveau_object * engctx)149 nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend,
150 struct nouveau_object *engctx)
151 {
152 struct nv04_fifo_priv *priv = (void *)parent->engine;
153 struct nv04_fifo_chan *chan = (void *)parent;
154 unsigned long flags;
155 u32 reg, ctx;
156
157 switch (nv_engidx(engctx->engine)) {
158 case NVDEV_ENGINE_SW:
159 return 0;
160 case NVDEV_ENGINE_GR:
161 reg = 0x32e0;
162 ctx = 0x38;
163 break;
164 case NVDEV_ENGINE_MPEG:
165 reg = 0x330c;
166 ctx = 0x54;
167 break;
168 default:
169 return -EINVAL;
170 }
171
172 spin_lock_irqsave(&priv->base.lock, flags);
173 nv_mask(priv, 0x002500, 0x00000001, 0x00000000);
174
175 if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
176 nv_wr32(priv, reg, 0x00000000);
177 nv_wo32(priv->ramfc, chan->ramfc + ctx, 0x00000000);
178
179 nv_mask(priv, 0x002500, 0x00000001, 0x00000001);
180 spin_unlock_irqrestore(&priv->base.lock, flags);
181 return 0;
182 }
183
184 static int
nv40_fifo_chan_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)185 nv40_fifo_chan_ctor(struct nouveau_object *parent,
186 struct nouveau_object *engine,
187 struct nouveau_oclass *oclass, void *data, u32 size,
188 struct nouveau_object **pobject)
189 {
190 struct nv04_fifo_priv *priv = (void *)engine;
191 struct nv04_fifo_chan *chan;
192 struct nv03_channel_dma_class *args = data;
193 int ret;
194
195 if (size < sizeof(*args))
196 return -EINVAL;
197
198 ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
199 0x1000, args->pushbuf,
200 (1ULL << NVDEV_ENGINE_DMAOBJ) |
201 (1ULL << NVDEV_ENGINE_SW) |
202 (1ULL << NVDEV_ENGINE_GR) |
203 (1ULL << NVDEV_ENGINE_MPEG), &chan);
204 *pobject = nv_object(chan);
205 if (ret)
206 return ret;
207
208 nv_parent(chan)->context_attach = nv40_fifo_context_attach;
209 nv_parent(chan)->context_detach = nv40_fifo_context_detach;
210 nv_parent(chan)->object_attach = nv40_fifo_object_attach;
211 nv_parent(chan)->object_detach = nv04_fifo_object_detach;
212 chan->ramfc = chan->base.chid * 128;
213
214 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);
215 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset);
216 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
217 nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 |
218 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
219 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
220 #ifdef __BIG_ENDIAN
221 NV_PFIFO_CACHE1_BIG_ENDIAN |
222 #endif
223 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
224 nv_wo32(priv->ramfc, chan->ramfc + 0x3c, 0x0001ffff);
225 return 0;
226 }
227
228 static struct nouveau_ofuncs
229 nv40_fifo_ofuncs = {
230 .ctor = nv40_fifo_chan_ctor,
231 .dtor = nv04_fifo_chan_dtor,
232 .init = nv04_fifo_chan_init,
233 .fini = nv04_fifo_chan_fini,
234 .rd32 = _nouveau_fifo_channel_rd32,
235 .wr32 = _nouveau_fifo_channel_wr32,
236 };
237
238 static struct nouveau_oclass
239 nv40_fifo_sclass[] = {
240 { NV40_CHANNEL_DMA_CLASS, &nv40_fifo_ofuncs },
241 {}
242 };
243
244 /*******************************************************************************
245 * FIFO context - basically just the instmem reserved for the channel
246 ******************************************************************************/
247
248 static struct nouveau_oclass
249 nv40_fifo_cclass = {
250 .handle = NV_ENGCTX(FIFO, 0x40),
251 .ofuncs = &(struct nouveau_ofuncs) {
252 .ctor = nv04_fifo_context_ctor,
253 .dtor = _nouveau_fifo_context_dtor,
254 .init = _nouveau_fifo_context_init,
255 .fini = _nouveau_fifo_context_fini,
256 .rd32 = _nouveau_fifo_context_rd32,
257 .wr32 = _nouveau_fifo_context_wr32,
258 },
259 };
260
261 /*******************************************************************************
262 * PFIFO engine
263 ******************************************************************************/
264
265 static int
nv40_fifo_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)266 nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
267 struct nouveau_oclass *oclass, void *data, u32 size,
268 struct nouveau_object **pobject)
269 {
270 struct nv04_instmem_priv *imem = nv04_instmem(parent);
271 struct nv04_fifo_priv *priv;
272 int ret;
273
274 ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
275 *pobject = nv_object(priv);
276 if (ret)
277 return ret;
278
279 nouveau_ramht_ref(imem->ramht, &priv->ramht);
280 nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
281 nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
282
283 nv_subdev(priv)->unit = 0x00000100;
284 nv_subdev(priv)->intr = nv04_fifo_intr;
285 nv_engine(priv)->cclass = &nv40_fifo_cclass;
286 nv_engine(priv)->sclass = nv40_fifo_sclass;
287 priv->base.pause = nv04_fifo_pause;
288 priv->base.start = nv04_fifo_start;
289 priv->ramfc_desc = nv40_ramfc;
290 return 0;
291 }
292
293 static int
nv40_fifo_init(struct nouveau_object * object)294 nv40_fifo_init(struct nouveau_object *object)
295 {
296 struct nv04_fifo_priv *priv = (void *)object;
297 struct nouveau_fb *pfb = nouveau_fb(object);
298 int ret;
299
300 ret = nouveau_fifo_init(&priv->base);
301 if (ret)
302 return ret;
303
304 nv_wr32(priv, 0x002040, 0x000000ff);
305 nv_wr32(priv, 0x002044, 0x2101ffff);
306 nv_wr32(priv, 0x002058, 0x00000001);
307
308 nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
309 ((priv->ramht->bits - 9) << 16) |
310 (priv->ramht->base.addr >> 8));
311 nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
312
313 switch (nv_device(priv)->chipset) {
314 case 0x47:
315 case 0x49:
316 case 0x4b:
317 nv_wr32(priv, 0x002230, 0x00000001);
318 /*FALLTHROUGH*/
319 case 0x40:
320 case 0x41:
321 case 0x42:
322 case 0x43:
323 case 0x45:
324 case 0x48:
325 nv_wr32(priv, 0x002220, 0x00030002);
326 break;
327 default:
328 nv_wr32(priv, 0x002230, 0x00000000);
329 nv_wr32(priv, 0x002220, ((pfb->ram->size - 512 * 1024 +
330 priv->ramfc->addr) >> 16) |
331 0x00030000);
332 break;
333 }
334
335 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
336
337 nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
338 nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);
339
340 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
341 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
342 nv_wr32(priv, NV03_PFIFO_CACHES, 1);
343 return 0;
344 }
345
346 struct nouveau_oclass *
347 nv40_fifo_oclass = &(struct nouveau_oclass) {
348 .handle = NV_ENGINE(FIFO, 0x40),
349 .ofuncs = &(struct nouveau_ofuncs) {
350 .ctor = nv40_fifo_ctor,
351 .dtor = nv04_fifo_dtor,
352 .init = nv40_fifo_init,
353 .fini = _nouveau_fifo_fini,
354 },
355 };
356