1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include <linux/err.h>
34 #include <linux/pm_runtime.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37
38 #include <linux/gcd.h>
39
avivo_crtc_load_lut(struct drm_crtc * crtc)40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
41 {
42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
43 struct drm_device *dev = crtc->dev;
44 struct radeon_device *rdev = dev->dev_private;
45 int i;
46
47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
49
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
53
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
57
58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
59 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
61
62 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
63 for (i = 0; i < 256; i++) {
64 WREG32(AVIVO_DC_LUT_30_COLOR,
65 (radeon_crtc->lut_r[i] << 20) |
66 (radeon_crtc->lut_g[i] << 10) |
67 (radeon_crtc->lut_b[i] << 0));
68 }
69
70 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
71 }
72
dce4_crtc_load_lut(struct drm_crtc * crtc)73 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
74 {
75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
76 struct drm_device *dev = crtc->dev;
77 struct radeon_device *rdev = dev->dev_private;
78 int i;
79
80 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
81 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
82
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
86
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
90
91 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
92 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
93
94 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
95 for (i = 0; i < 256; i++) {
96 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
97 (radeon_crtc->lut_r[i] << 20) |
98 (radeon_crtc->lut_g[i] << 10) |
99 (radeon_crtc->lut_b[i] << 0));
100 }
101 }
102
dce5_crtc_load_lut(struct drm_crtc * crtc)103 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
104 {
105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
106 struct drm_device *dev = crtc->dev;
107 struct radeon_device *rdev = dev->dev_private;
108 int i;
109
110 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
111
112 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
113 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
114 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
115 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
116 NI_GRPH_PRESCALE_BYPASS);
117 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
118 NI_OVL_PRESCALE_BYPASS);
119 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
120 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
121 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
122
123 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
124
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
128
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
132
133 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
134 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
135
136 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
137 for (i = 0; i < 256; i++) {
138 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
139 (radeon_crtc->lut_r[i] << 20) |
140 (radeon_crtc->lut_g[i] << 10) |
141 (radeon_crtc->lut_b[i] << 0));
142 }
143
144 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
145 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
148 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
149 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
150 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
151 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
152 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
153 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
154 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
155 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
156 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
157 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
158 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
159 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
160 if (ASIC_IS_DCE8(rdev)) {
161 /* XXX this only needs to be programmed once per crtc at startup,
162 * not sure where the best place for it is
163 */
164 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
165 CIK_CURSOR_ALPHA_BLND_ENA);
166 }
167 }
168
legacy_crtc_load_lut(struct drm_crtc * crtc)169 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
170 {
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int i;
175 uint32_t dac2_cntl;
176
177 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
178 if (radeon_crtc->crtc_id == 0)
179 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
180 else
181 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
182 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
183
184 /*
185 * At least the RV100 [vendor 1002 product 515e (rev. 0x02)]
186 * has an old style palette
187 */
188 if (rdev->family < CHIP_RV280) {
189 #ifdef notyet
190 /*
191 * Leave CLUT alone for now. The code below gives us a
192 * nice 444 grayscale, but we are not in true color mode
193 * anymore and I don't have any docs how to do this right.
194 */
195 WREG8(RADEON_PALETTE_INDEX, 0);
196 for (i = 0; i < 256; i++) {
197 #define R(x) (radeon_crtc->lut_r[i] >> 2)
198 #define G(x) (radeon_crtc->lut_g[i] >> 2)
199 #define B(x) (radeon_crtc->lut_b[i] >> 2)
200 WREG32(RADEON_PALETTE_DATA, ((R(i) << 16)
201 | (G(i) << 8) | B(i)) << 4);
202 }
203 #else
204 printf("%s: unknown DAC, can't set lookup table\n", __func__);
205 #endif
206 } else {
207 WREG8(RADEON_PALETTE_INDEX, 0);
208 for (i = 0; i < 256; i++) {
209 WREG32(RADEON_PALETTE_30_DATA,
210 (radeon_crtc->lut_r[i] << 20) |
211 (radeon_crtc->lut_g[i] << 10) |
212 (radeon_crtc->lut_b[i] << 0));
213 }
214 }
215 }
216
radeon_crtc_load_lut(struct drm_crtc * crtc)217 void radeon_crtc_load_lut(struct drm_crtc *crtc)
218 {
219 struct drm_device *dev = crtc->dev;
220 struct radeon_device *rdev = dev->dev_private;
221
222 if (!crtc->enabled)
223 return;
224
225 if (ASIC_IS_DCE5(rdev))
226 dce5_crtc_load_lut(crtc);
227 else if (ASIC_IS_DCE4(rdev))
228 dce4_crtc_load_lut(crtc);
229 else if (ASIC_IS_AVIVO(rdev))
230 avivo_crtc_load_lut(crtc);
231 else
232 legacy_crtc_load_lut(crtc);
233 }
234
235 /** Sets the color ramps on behalf of fbcon */
radeon_crtc_fb_gamma_set(struct drm_crtc * crtc,u16 red,u16 green,u16 blue,int regno)236 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
237 u16 blue, int regno)
238 {
239 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
240
241 radeon_crtc->lut_r[regno] = red >> 6;
242 radeon_crtc->lut_g[regno] = green >> 6;
243 radeon_crtc->lut_b[regno] = blue >> 6;
244 }
245
246 /** Gets the color ramps on behalf of fbcon */
radeon_crtc_fb_gamma_get(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,int regno)247 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
248 u16 *blue, int regno)
249 {
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251
252 *red = radeon_crtc->lut_r[regno] << 6;
253 *green = radeon_crtc->lut_g[regno] << 6;
254 *blue = radeon_crtc->lut_b[regno] << 6;
255 }
256
radeon_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t start,uint32_t size)257 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
258 u16 *blue, uint32_t start, uint32_t size)
259 {
260 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
261 int end = (start + size > 256) ? 256 : start + size, i;
262
263 /* userspace palettes are always correct as is */
264 for (i = start; i < end; i++) {
265 radeon_crtc->lut_r[i] = red[i] >> 6;
266 radeon_crtc->lut_g[i] = green[i] >> 6;
267 radeon_crtc->lut_b[i] = blue[i] >> 6;
268 }
269 radeon_crtc_load_lut(crtc);
270 }
271
radeon_crtc_destroy(struct drm_crtc * crtc)272 static void radeon_crtc_destroy(struct drm_crtc *crtc)
273 {
274 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
275
276 drm_crtc_cleanup(crtc);
277 kfree(radeon_crtc);
278 }
279
280 /*
281 * Handle unpin events outside the interrupt handler proper.
282 */
radeon_unpin_work_func(struct work_struct * __work)283 static void radeon_unpin_work_func(struct work_struct *__work)
284 {
285 struct radeon_unpin_work *work =
286 container_of(__work, struct radeon_unpin_work, work);
287 int r;
288
289 /* unpin of the old buffer */
290 r = radeon_bo_reserve(work->old_rbo, false);
291 if (likely(r == 0)) {
292 r = radeon_bo_unpin(work->old_rbo);
293 if (unlikely(r != 0)) {
294 DRM_ERROR("failed to unpin buffer after flip\n");
295 }
296 radeon_bo_unreserve(work->old_rbo);
297 } else
298 DRM_ERROR("failed to reserve buffer after flip\n");
299
300 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
301 kfree(work);
302 }
303
radeon_crtc_handle_flip(struct radeon_device * rdev,int crtc_id)304 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
305 {
306 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
307 struct radeon_unpin_work *work;
308 unsigned long flags;
309 u32 update_pending;
310 int vpos, hpos;
311
312 /* can happen during initialization */
313 if (radeon_crtc == NULL)
314 return;
315
316 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
317 work = radeon_crtc->unpin_work;
318 if (work == NULL ||
319 (work->fence && !radeon_fence_signaled(work->fence))) {
320 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
321 return;
322 }
323 /* New pageflip, or just completion of a previous one? */
324 if (!radeon_crtc->deferred_flip_completion) {
325 /* do the flip (mmio) */
326 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
327 } else {
328 /* This is just a completion of a flip queued in crtc
329 * at last invocation. Make sure we go directly to
330 * completion routine.
331 */
332 update_pending = 0;
333 radeon_crtc->deferred_flip_completion = 0;
334 }
335
336 /* Has the pageflip already completed in crtc, or is it certain
337 * to complete in this vblank?
338 */
339 if (update_pending &&
340 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
341 &vpos, &hpos, NULL, NULL)) &&
342 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
343 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
344 /* crtc didn't flip in this target vblank interval,
345 * but flip is pending in crtc. Based on the current
346 * scanout position we know that the current frame is
347 * (nearly) complete and the flip will (likely)
348 * complete before the start of the next frame.
349 */
350 update_pending = 0;
351 }
352 if (update_pending) {
353 /* crtc didn't flip in this target vblank interval,
354 * but flip is pending in crtc. It will complete it
355 * in next vblank interval, so complete the flip at
356 * next vblank irq.
357 */
358 radeon_crtc->deferred_flip_completion = 1;
359 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
360 return;
361 }
362
363 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
364 radeon_crtc->unpin_work = NULL;
365
366 /* wakeup userspace */
367 if (work->event)
368 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
369
370 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
371
372 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
373 radeon_fence_unref(&work->fence);
374 radeon_post_page_flip(work->rdev, work->crtc_id);
375 schedule_work(&work->work);
376 }
377
radeon_crtc_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags)378 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
379 struct drm_framebuffer *fb,
380 struct drm_pending_vblank_event *event,
381 uint32_t page_flip_flags)
382 {
383 struct drm_device *dev = crtc->dev;
384 struct radeon_device *rdev = dev->dev_private;
385 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
386 struct radeon_framebuffer *old_radeon_fb;
387 struct radeon_framebuffer *new_radeon_fb;
388 struct drm_gem_object *obj;
389 struct radeon_bo *rbo;
390 struct radeon_unpin_work *work;
391 unsigned long flags;
392 u32 tiling_flags, pitch_pixels;
393 u64 base;
394 int r;
395
396 work = kzalloc(sizeof *work, GFP_KERNEL);
397 if (work == NULL)
398 return -ENOMEM;
399
400 work->event = event;
401 work->rdev = rdev;
402 work->crtc_id = radeon_crtc->crtc_id;
403 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
404 new_radeon_fb = to_radeon_framebuffer(fb);
405 /* schedule unpin of the old buffer */
406 obj = old_radeon_fb->obj;
407 /* take a reference to the old object */
408 drm_gem_object_reference(obj);
409 rbo = gem_to_radeon_bo(obj);
410 work->old_rbo = rbo;
411 obj = new_radeon_fb->obj;
412 rbo = gem_to_radeon_bo(obj);
413
414 spin_lock(&rbo->tbo.bdev->fence_lock);
415 if (rbo->tbo.sync_obj)
416 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
417 spin_unlock(&rbo->tbo.bdev->fence_lock);
418
419 INIT_WORK(&work->work, radeon_unpin_work_func);
420
421 /* We borrow the event spin lock for protecting unpin_work */
422 spin_lock_irqsave(&dev->event_lock, flags);
423 if (radeon_crtc->unpin_work) {
424 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
425 r = -EBUSY;
426 goto unlock_free;
427 }
428 radeon_crtc->unpin_work = work;
429 radeon_crtc->deferred_flip_completion = 0;
430 spin_unlock_irqrestore(&dev->event_lock, flags);
431
432 /* pin the new buffer */
433 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
434 work->old_rbo, rbo);
435
436 r = radeon_bo_reserve(rbo, false);
437 if (unlikely(r != 0)) {
438 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
439 goto pflip_cleanup;
440 }
441 /* Only 27 bit offset for legacy CRTC */
442 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
443 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
444 if (unlikely(r != 0)) {
445 radeon_bo_unreserve(rbo);
446 r = -EINVAL;
447 DRM_ERROR("failed to pin new rbo buffer before flip\n");
448 goto pflip_cleanup;
449 }
450 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
451 radeon_bo_unreserve(rbo);
452
453 if (!ASIC_IS_AVIVO(rdev)) {
454 /* crtc offset is from display base addr not FB location */
455 base -= radeon_crtc->legacy_display_base_addr;
456 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
457
458 if (tiling_flags & RADEON_TILING_MACRO) {
459 if (ASIC_IS_R300(rdev)) {
460 base &= ~0x7ff;
461 } else {
462 int byteshift = fb->bits_per_pixel >> 4;
463 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
464 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
465 }
466 } else {
467 int offset = crtc->y * pitch_pixels + crtc->x;
468 switch (fb->bits_per_pixel) {
469 case 8:
470 default:
471 offset *= 1;
472 break;
473 case 15:
474 case 16:
475 offset *= 2;
476 break;
477 case 24:
478 offset *= 3;
479 break;
480 case 32:
481 offset *= 4;
482 break;
483 }
484 base += offset;
485 }
486 base &= ~7;
487 }
488
489 spin_lock_irqsave(&dev->event_lock, flags);
490 work->new_crtc_base = base;
491 spin_unlock_irqrestore(&dev->event_lock, flags);
492
493 /* update crtc fb */
494 crtc->primary->fb = fb;
495
496 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
497 if (r) {
498 DRM_ERROR("failed to get vblank before flip\n");
499 goto pflip_cleanup1;
500 }
501
502 /* set the proper interrupt */
503 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
504
505 return 0;
506
507 pflip_cleanup1:
508 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
509 DRM_ERROR("failed to reserve new rbo in error path\n");
510 goto pflip_cleanup;
511 }
512 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
513 DRM_ERROR("failed to unpin new rbo in error path\n");
514 }
515 radeon_bo_unreserve(rbo);
516
517 pflip_cleanup:
518 spin_lock_irqsave(&dev->event_lock, flags);
519 radeon_crtc->unpin_work = NULL;
520 unlock_free:
521 spin_unlock_irqrestore(&dev->event_lock, flags);
522 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
523 radeon_fence_unref(&work->fence);
524 kfree(work);
525
526 return r;
527 }
528
529 static int
radeon_crtc_set_config(struct drm_mode_set * set)530 radeon_crtc_set_config(struct drm_mode_set *set)
531 {
532 struct drm_device *dev;
533 struct radeon_device *rdev;
534 struct drm_crtc *crtc;
535 bool active = false;
536 int ret;
537
538 if (!set || !set->crtc)
539 return -EINVAL;
540
541 dev = set->crtc->dev;
542
543 ret = pm_runtime_get_sync(dev->dev);
544 if (ret < 0)
545 return ret;
546
547 ret = drm_crtc_helper_set_config(set);
548
549 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
550 if (crtc->enabled)
551 active = true;
552
553 pm_runtime_mark_last_busy(dev->dev);
554
555 rdev = dev->dev_private;
556 /* if we have active crtcs and we don't have a power ref,
557 take the current one */
558 if (active && !rdev->have_disp_power_ref) {
559 rdev->have_disp_power_ref = true;
560 return ret;
561 }
562 /* if we have no active crtcs, then drop the power ref
563 we got before */
564 if (!active && rdev->have_disp_power_ref) {
565 pm_runtime_put_autosuspend(dev->dev);
566 rdev->have_disp_power_ref = false;
567 }
568
569 /* drop the power reference we got coming in here */
570 pm_runtime_put_autosuspend(dev->dev);
571 return ret;
572 }
573 static const struct drm_crtc_funcs radeon_crtc_funcs = {
574 .cursor_set = radeon_crtc_cursor_set,
575 .cursor_move = radeon_crtc_cursor_move,
576 .gamma_set = radeon_crtc_gamma_set,
577 .set_config = radeon_crtc_set_config,
578 .destroy = radeon_crtc_destroy,
579 .page_flip = radeon_crtc_page_flip,
580 };
581
radeon_crtc_init(struct drm_device * dev,int index)582 static void radeon_crtc_init(struct drm_device *dev, int index)
583 {
584 struct radeon_device *rdev = dev->dev_private;
585 struct radeon_crtc *radeon_crtc;
586 int i;
587
588 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
589 if (radeon_crtc == NULL)
590 return;
591
592 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
593
594 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
595 radeon_crtc->crtc_id = index;
596 rdev->mode_info.crtcs[index] = radeon_crtc;
597
598 if (rdev->family >= CHIP_BONAIRE) {
599 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
600 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
601 } else {
602 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
603 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
604 }
605 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
606 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
607
608 #if 0
609 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
610 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
611 radeon_crtc->mode_set.num_connectors = 0;
612 #endif
613
614 for (i = 0; i < 256; i++) {
615 radeon_crtc->lut_r[i] = i << 2;
616 radeon_crtc->lut_g[i] = i << 2;
617 radeon_crtc->lut_b[i] = i << 2;
618 }
619
620 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
621 radeon_atombios_init_crtc(dev, radeon_crtc);
622 else
623 radeon_legacy_init_crtc(dev, radeon_crtc);
624 }
625
626 static const char *encoder_names[38] = {
627 "NONE",
628 "INTERNAL_LVDS",
629 "INTERNAL_TMDS1",
630 "INTERNAL_TMDS2",
631 "INTERNAL_DAC1",
632 "INTERNAL_DAC2",
633 "INTERNAL_SDVOA",
634 "INTERNAL_SDVOB",
635 "SI170B",
636 "CH7303",
637 "CH7301",
638 "INTERNAL_DVO1",
639 "EXTERNAL_SDVOA",
640 "EXTERNAL_SDVOB",
641 "TITFP513",
642 "INTERNAL_LVTM1",
643 "VT1623",
644 "HDMI_SI1930",
645 "HDMI_INTERNAL",
646 "INTERNAL_KLDSCP_TMDS1",
647 "INTERNAL_KLDSCP_DVO1",
648 "INTERNAL_KLDSCP_DAC1",
649 "INTERNAL_KLDSCP_DAC2",
650 "SI178",
651 "MVPU_FPGA",
652 "INTERNAL_DDI",
653 "VT1625",
654 "HDMI_SI1932",
655 "DP_AN9801",
656 "DP_DP501",
657 "INTERNAL_UNIPHY",
658 "INTERNAL_KLDSCP_LVTMA",
659 "INTERNAL_UNIPHY1",
660 "INTERNAL_UNIPHY2",
661 "NUTMEG",
662 "TRAVIS",
663 "INTERNAL_VCE",
664 "INTERNAL_UNIPHY3",
665 };
666
667 static const char *hpd_names[6] = {
668 "HPD1",
669 "HPD2",
670 "HPD3",
671 "HPD4",
672 "HPD5",
673 "HPD6",
674 };
675
radeon_print_display_setup(struct drm_device * dev)676 static void radeon_print_display_setup(struct drm_device *dev)
677 {
678 struct drm_connector *connector;
679 struct radeon_connector *radeon_connector;
680 struct drm_encoder *encoder;
681 struct radeon_encoder *radeon_encoder;
682 uint32_t devices;
683 int i = 0;
684
685 DRM_INFO("Radeon Display Connectors\n");
686 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
687 radeon_connector = to_radeon_connector(connector);
688 DRM_INFO("Connector %d:\n", i);
689 DRM_INFO(" %s\n", drm_get_connector_name(connector));
690 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
691 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
692 if (radeon_connector->ddc_bus) {
693 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
694 radeon_connector->ddc_bus->rec.mask_clk_reg,
695 radeon_connector->ddc_bus->rec.mask_data_reg,
696 radeon_connector->ddc_bus->rec.a_clk_reg,
697 radeon_connector->ddc_bus->rec.a_data_reg,
698 radeon_connector->ddc_bus->rec.en_clk_reg,
699 radeon_connector->ddc_bus->rec.en_data_reg,
700 radeon_connector->ddc_bus->rec.y_clk_reg,
701 radeon_connector->ddc_bus->rec.y_data_reg);
702 if (radeon_connector->router.ddc_valid)
703 DRM_INFO(" DDC Router 0x%x/0x%x\n",
704 radeon_connector->router.ddc_mux_control_pin,
705 radeon_connector->router.ddc_mux_state);
706 if (radeon_connector->router.cd_valid)
707 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
708 radeon_connector->router.cd_mux_control_pin,
709 radeon_connector->router.cd_mux_state);
710 } else {
711 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
712 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
713 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
714 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
715 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
716 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
717 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
718 }
719 DRM_INFO(" Encoders:\n");
720 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
721 radeon_encoder = to_radeon_encoder(encoder);
722 devices = radeon_encoder->devices & radeon_connector->devices;
723 if (devices) {
724 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
725 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
726 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
727 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
728 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
729 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
730 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
731 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
732 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
733 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
734 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
735 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
736 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
737 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
738 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
739 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
740 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
741 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
742 if (devices & ATOM_DEVICE_TV1_SUPPORT)
743 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
744 if (devices & ATOM_DEVICE_CV_SUPPORT)
745 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
746 }
747 }
748 i++;
749 }
750 }
751
radeon_setup_enc_conn(struct drm_device * dev)752 static bool radeon_setup_enc_conn(struct drm_device *dev)
753 {
754 struct radeon_device *rdev = dev->dev_private;
755 bool ret = false;
756
757 if (rdev->bios) {
758 if (rdev->is_atom_bios) {
759 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
760 if (ret == false)
761 ret = radeon_get_atom_connector_info_from_object_table(dev);
762 } else {
763 ret = radeon_get_legacy_connector_info_from_bios(dev);
764 if (ret == false)
765 ret = radeon_get_legacy_connector_info_from_table(dev);
766 }
767 } else {
768 if (!ASIC_IS_AVIVO(rdev))
769 ret = radeon_get_legacy_connector_info_from_table(dev);
770 }
771 if (ret) {
772 radeon_setup_encoder_clones(dev);
773 radeon_print_display_setup(dev);
774 }
775
776 return ret;
777 }
778
radeon_ddc_get_modes(struct radeon_connector * radeon_connector)779 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
780 {
781 struct drm_device *dev = radeon_connector->base.dev;
782 struct radeon_device *rdev = dev->dev_private;
783 int ret = 0;
784
785 /* on hw with routers, select right port */
786 if (radeon_connector->router.ddc_valid)
787 radeon_router_select_ddc_port(radeon_connector);
788
789 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
790 ENCODER_OBJECT_ID_NONE) {
791 if (radeon_connector->ddc_bus->has_aux)
792 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
793 &radeon_connector->ddc_bus->aux.ddc);
794 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
795 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
796 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
797
798 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
799 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
800 radeon_connector->ddc_bus->has_aux)
801 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
802 &radeon_connector->ddc_bus->aux.ddc);
803 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
804 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
805 &radeon_connector->ddc_bus->adapter);
806 } else {
807 if (radeon_connector->ddc_bus && !radeon_connector->edid)
808 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
809 &radeon_connector->ddc_bus->adapter);
810 }
811
812 if (!radeon_connector->edid) {
813 if (rdev->is_atom_bios) {
814 /* some laptops provide a hardcoded edid in rom for LCDs */
815 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
816 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
817 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
818 } else
819 /* some servers provide a hardcoded edid in rom for KVMs */
820 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
821 }
822 if (radeon_connector->edid) {
823 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
824 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
825 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
826 return ret;
827 }
828 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
829 return 0;
830 }
831
832 /* avivo */
833
834 /**
835 * avivo_reduce_ratio - fractional number reduction
836 *
837 * @nom: nominator
838 * @den: denominator
839 * @nom_min: minimum value for nominator
840 * @den_min: minimum value for denominator
841 *
842 * Find the greatest common divisor and apply it on both nominator and
843 * denominator, but make nominator and denominator are at least as large
844 * as their minimum values.
845 */
avivo_reduce_ratio(unsigned * nom,unsigned * den,unsigned nom_min,unsigned den_min)846 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
847 unsigned nom_min, unsigned den_min)
848 {
849 unsigned tmp;
850
851 /* reduce the numbers to a simpler ratio */
852 tmp = gcd(*nom, *den);
853 *nom /= tmp;
854 *den /= tmp;
855
856 /* make sure nominator is large enough */
857 if (*nom < nom_min) {
858 tmp = DIV_ROUND_UP(nom_min, *nom);
859 *nom *= tmp;
860 *den *= tmp;
861 }
862
863 /* make sure the denominator is large enough */
864 if (*den < den_min) {
865 tmp = DIV_ROUND_UP(den_min, *den);
866 *nom *= tmp;
867 *den *= tmp;
868 }
869 }
870
871 /**
872 * avivo_get_fb_ref_div - feedback and ref divider calculation
873 *
874 * @nom: nominator
875 * @den: denominator
876 * @post_div: post divider
877 * @fb_div_max: feedback divider maximum
878 * @ref_div_max: reference divider maximum
879 * @fb_div: resulting feedback divider
880 * @ref_div: resulting reference divider
881 *
882 * Calculate feedback and reference divider for a given post divider. Makes
883 * sure we stay within the limits.
884 */
avivo_get_fb_ref_div(unsigned nom,unsigned den,unsigned post_div,unsigned fb_div_max,unsigned ref_div_max,unsigned * fb_div,unsigned * ref_div)885 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
886 unsigned fb_div_max, unsigned ref_div_max,
887 unsigned *fb_div, unsigned *ref_div)
888 {
889 /* limit reference * post divider to a maximum */
890 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
891
892 /* get matching reference and feedback divider */
893 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
894 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
895
896 /* limit fb divider to its maximum */
897 if (*fb_div > fb_div_max) {
898 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
899 *fb_div = fb_div_max;
900 }
901 }
902
903 /**
904 * radeon_compute_pll_avivo - compute PLL paramaters
905 *
906 * @pll: information about the PLL
907 * @dot_clock_p: resulting pixel clock
908 * fb_div_p: resulting feedback divider
909 * frac_fb_div_p: fractional part of the feedback divider
910 * ref_div_p: resulting reference divider
911 * post_div_p: resulting reference divider
912 *
913 * Try to calculate the PLL parameters to generate the given frequency:
914 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
915 */
radeon_compute_pll_avivo(struct radeon_pll * pll,u32 freq,u32 * dot_clock_p,u32 * fb_div_p,u32 * frac_fb_div_p,u32 * ref_div_p,u32 * post_div_p)916 void radeon_compute_pll_avivo(struct radeon_pll *pll,
917 u32 freq,
918 u32 *dot_clock_p,
919 u32 *fb_div_p,
920 u32 *frac_fb_div_p,
921 u32 *ref_div_p,
922 u32 *post_div_p)
923 {
924 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
925 freq : freq / 10;
926
927 unsigned fb_div_min, fb_div_max, fb_div;
928 unsigned post_div_min, post_div_max, post_div;
929 unsigned ref_div_min, ref_div_max, ref_div;
930 unsigned post_div_best, diff_best;
931 unsigned nom, den;
932
933 /* determine allowed feedback divider range */
934 fb_div_min = pll->min_feedback_div;
935 fb_div_max = pll->max_feedback_div;
936
937 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
938 fb_div_min *= 10;
939 fb_div_max *= 10;
940 }
941
942 /* determine allowed ref divider range */
943 if (pll->flags & RADEON_PLL_USE_REF_DIV)
944 ref_div_min = pll->reference_div;
945 else
946 ref_div_min = pll->min_ref_div;
947
948 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
949 pll->flags & RADEON_PLL_USE_REF_DIV)
950 ref_div_max = pll->reference_div;
951 else
952 ref_div_max = pll->max_ref_div;
953
954 /* determine allowed post divider range */
955 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
956 post_div_min = pll->post_div;
957 post_div_max = pll->post_div;
958 } else {
959 unsigned vco_min, vco_max;
960
961 if (pll->flags & RADEON_PLL_IS_LCD) {
962 vco_min = pll->lcd_pll_out_min;
963 vco_max = pll->lcd_pll_out_max;
964 } else {
965 vco_min = pll->pll_out_min;
966 vco_max = pll->pll_out_max;
967 }
968
969 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
970 vco_min *= 10;
971 vco_max *= 10;
972 }
973
974 post_div_min = vco_min / target_clock;
975 if ((target_clock * post_div_min) < vco_min)
976 ++post_div_min;
977 if (post_div_min < pll->min_post_div)
978 post_div_min = pll->min_post_div;
979
980 post_div_max = vco_max / target_clock;
981 if ((target_clock * post_div_max) > vco_max)
982 --post_div_max;
983 if (post_div_max > pll->max_post_div)
984 post_div_max = pll->max_post_div;
985 }
986
987 /* represent the searched ratio as fractional number */
988 nom = target_clock;
989 den = pll->reference_freq;
990
991 /* reduce the numbers to a simpler ratio */
992 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
993
994 /* now search for a post divider */
995 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
996 post_div_best = post_div_min;
997 else
998 post_div_best = post_div_max;
999 diff_best = ~0;
1000
1001 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1002 unsigned diff;
1003 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1004 ref_div_max, &fb_div, &ref_div);
1005 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1006 (ref_div * post_div));
1007
1008 if (diff < diff_best || (diff == diff_best &&
1009 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1010
1011 post_div_best = post_div;
1012 diff_best = diff;
1013 }
1014 }
1015 post_div = post_div_best;
1016
1017 /* get the feedback and reference divider for the optimal value */
1018 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1019 &fb_div, &ref_div);
1020
1021 /* reduce the numbers to a simpler ratio once more */
1022 /* this also makes sure that the reference divider is large enough */
1023 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1024
1025 /* avoid high jitter with small fractional dividers */
1026 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1027 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1028 if (fb_div < fb_div_min) {
1029 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1030 fb_div *= tmp;
1031 ref_div *= tmp;
1032 }
1033 }
1034
1035 /* and finally save the result */
1036 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1037 *fb_div_p = fb_div / 10;
1038 *frac_fb_div_p = fb_div % 10;
1039 } else {
1040 *fb_div_p = fb_div;
1041 *frac_fb_div_p = 0;
1042 }
1043
1044 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1045 (pll->reference_freq * *frac_fb_div_p)) /
1046 (ref_div * post_div * 10);
1047 *ref_div_p = ref_div;
1048 *post_div_p = post_div;
1049
1050 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1051 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1052 ref_div, post_div);
1053 }
1054
1055 /* pre-avivo */
radeon_div(uint64_t n,uint32_t d)1056 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1057 {
1058 uint64_t mod __unused;
1059
1060 n += d / 2;
1061
1062 mod = do_div(n, d);
1063 return n;
1064 }
1065
radeon_compute_pll_legacy(struct radeon_pll * pll,uint64_t freq,uint32_t * dot_clock_p,uint32_t * fb_div_p,uint32_t * frac_fb_div_p,uint32_t * ref_div_p,uint32_t * post_div_p)1066 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1067 uint64_t freq,
1068 uint32_t *dot_clock_p,
1069 uint32_t *fb_div_p,
1070 uint32_t *frac_fb_div_p,
1071 uint32_t *ref_div_p,
1072 uint32_t *post_div_p)
1073 {
1074 uint32_t min_ref_div = pll->min_ref_div;
1075 uint32_t max_ref_div = pll->max_ref_div;
1076 uint32_t min_post_div = pll->min_post_div;
1077 uint32_t max_post_div = pll->max_post_div;
1078 uint32_t min_fractional_feed_div = 0;
1079 uint32_t max_fractional_feed_div = 0;
1080 uint32_t best_vco = pll->best_vco;
1081 uint32_t best_post_div = 1;
1082 uint32_t best_ref_div = 1;
1083 uint32_t best_feedback_div = 1;
1084 uint32_t best_frac_feedback_div = 0;
1085 uint32_t best_freq = -1;
1086 uint32_t best_error = 0xffffffff;
1087 uint32_t best_vco_diff = 1;
1088 uint32_t post_div;
1089 u32 pll_out_min, pll_out_max;
1090
1091 DRM_DEBUG_KMS("PLL freq %"PRIu64" %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1092 freq = freq * 1000;
1093
1094 if (pll->flags & RADEON_PLL_IS_LCD) {
1095 pll_out_min = pll->lcd_pll_out_min;
1096 pll_out_max = pll->lcd_pll_out_max;
1097 } else {
1098 pll_out_min = pll->pll_out_min;
1099 pll_out_max = pll->pll_out_max;
1100 }
1101
1102 if (pll_out_min > 64800)
1103 pll_out_min = 64800;
1104
1105 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1106 min_ref_div = max_ref_div = pll->reference_div;
1107 else {
1108 while (min_ref_div < max_ref_div-1) {
1109 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1110 uint32_t pll_in = pll->reference_freq / mid;
1111 if (pll_in < pll->pll_in_min)
1112 max_ref_div = mid;
1113 else if (pll_in > pll->pll_in_max)
1114 min_ref_div = mid;
1115 else
1116 break;
1117 }
1118 }
1119
1120 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1121 min_post_div = max_post_div = pll->post_div;
1122
1123 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1124 min_fractional_feed_div = pll->min_frac_feedback_div;
1125 max_fractional_feed_div = pll->max_frac_feedback_div;
1126 }
1127
1128 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1129 uint32_t ref_div;
1130
1131 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1132 continue;
1133
1134 /* legacy radeons only have a few post_divs */
1135 if (pll->flags & RADEON_PLL_LEGACY) {
1136 if ((post_div == 5) ||
1137 (post_div == 7) ||
1138 (post_div == 9) ||
1139 (post_div == 10) ||
1140 (post_div == 11) ||
1141 (post_div == 13) ||
1142 (post_div == 14) ||
1143 (post_div == 15))
1144 continue;
1145 }
1146
1147 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1148 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1149 uint32_t pll_in = pll->reference_freq / ref_div;
1150 uint32_t min_feed_div = pll->min_feedback_div;
1151 uint32_t max_feed_div = pll->max_feedback_div + 1;
1152
1153 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1154 continue;
1155
1156 while (min_feed_div < max_feed_div) {
1157 uint32_t vco;
1158 uint32_t min_frac_feed_div = min_fractional_feed_div;
1159 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1160 uint32_t frac_feedback_div;
1161 uint64_t tmp;
1162
1163 feedback_div = (min_feed_div + max_feed_div) / 2;
1164
1165 tmp = (uint64_t)pll->reference_freq * feedback_div;
1166 vco = radeon_div(tmp, ref_div);
1167
1168 if (vco < pll_out_min) {
1169 min_feed_div = feedback_div + 1;
1170 continue;
1171 } else if (vco > pll_out_max) {
1172 max_feed_div = feedback_div;
1173 continue;
1174 }
1175
1176 while (min_frac_feed_div < max_frac_feed_div) {
1177 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1178 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1179 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1180 current_freq = radeon_div(tmp, ref_div * post_div);
1181
1182 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1183 if (freq < current_freq)
1184 error = 0xffffffff;
1185 else
1186 error = freq - current_freq;
1187 } else
1188 error = abs(current_freq - freq);
1189 vco_diff = abs(vco - best_vco);
1190
1191 if ((best_vco == 0 && error < best_error) ||
1192 (best_vco != 0 &&
1193 ((best_error > 100 && error < best_error - 100) ||
1194 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1195 best_post_div = post_div;
1196 best_ref_div = ref_div;
1197 best_feedback_div = feedback_div;
1198 best_frac_feedback_div = frac_feedback_div;
1199 best_freq = current_freq;
1200 best_error = error;
1201 best_vco_diff = vco_diff;
1202 } else if (current_freq == freq) {
1203 if (best_freq == -1) {
1204 best_post_div = post_div;
1205 best_ref_div = ref_div;
1206 best_feedback_div = feedback_div;
1207 best_frac_feedback_div = frac_feedback_div;
1208 best_freq = current_freq;
1209 best_error = error;
1210 best_vco_diff = vco_diff;
1211 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1212 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1213 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1214 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1215 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1216 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1217 best_post_div = post_div;
1218 best_ref_div = ref_div;
1219 best_feedback_div = feedback_div;
1220 best_frac_feedback_div = frac_feedback_div;
1221 best_freq = current_freq;
1222 best_error = error;
1223 best_vco_diff = vco_diff;
1224 }
1225 }
1226 if (current_freq < freq)
1227 min_frac_feed_div = frac_feedback_div + 1;
1228 else
1229 max_frac_feed_div = frac_feedback_div;
1230 }
1231 if (current_freq < freq)
1232 min_feed_div = feedback_div + 1;
1233 else
1234 max_feed_div = feedback_div;
1235 }
1236 }
1237 }
1238
1239 *dot_clock_p = best_freq / 10000;
1240 *fb_div_p = best_feedback_div;
1241 *frac_fb_div_p = best_frac_feedback_div;
1242 *ref_div_p = best_ref_div;
1243 *post_div_p = best_post_div;
1244 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1245 (long long)freq,
1246 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1247 best_ref_div, best_post_div);
1248
1249 }
1250
radeon_user_framebuffer_destroy(struct drm_framebuffer * fb)1251 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1252 {
1253 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1254
1255 if (radeon_fb->obj) {
1256 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1257 }
1258 drm_framebuffer_cleanup(fb);
1259 kfree(radeon_fb);
1260 }
1261
radeon_user_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file_priv,unsigned int * handle)1262 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1263 struct drm_file *file_priv,
1264 unsigned int *handle)
1265 {
1266 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1267
1268 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1269 }
1270
1271 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1272 .destroy = radeon_user_framebuffer_destroy,
1273 .create_handle = radeon_user_framebuffer_create_handle,
1274 };
1275
1276 int
radeon_framebuffer_init(struct drm_device * dev,struct radeon_framebuffer * rfb,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1277 radeon_framebuffer_init(struct drm_device *dev,
1278 struct radeon_framebuffer *rfb,
1279 struct drm_mode_fb_cmd2 *mode_cmd,
1280 struct drm_gem_object *obj)
1281 {
1282 int ret;
1283 rfb->obj = obj;
1284 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1285 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1286 if (ret) {
1287 rfb->obj = NULL;
1288 return ret;
1289 }
1290 return 0;
1291 }
1292
1293 static struct drm_framebuffer *
radeon_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,struct drm_mode_fb_cmd2 * mode_cmd)1294 radeon_user_framebuffer_create(struct drm_device *dev,
1295 struct drm_file *file_priv,
1296 struct drm_mode_fb_cmd2 *mode_cmd)
1297 {
1298 struct drm_gem_object *obj;
1299 struct radeon_framebuffer *radeon_fb;
1300 int ret;
1301
1302 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1303 if (obj == NULL) {
1304 dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1305 "can't create framebuffer\n", mode_cmd->handles[0]);
1306 return ERR_PTR(-ENOENT);
1307 }
1308
1309 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1310 if (radeon_fb == NULL) {
1311 drm_gem_object_unreference_unlocked(obj);
1312 return ERR_PTR(-ENOMEM);
1313 }
1314
1315 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1316 if (ret) {
1317 kfree(radeon_fb);
1318 drm_gem_object_unreference_unlocked(obj);
1319 return ERR_PTR(ret);
1320 }
1321
1322 return &radeon_fb->base;
1323 }
1324
radeon_output_poll_changed(struct drm_device * dev)1325 static void radeon_output_poll_changed(struct drm_device *dev)
1326 {
1327 struct radeon_device *rdev = dev->dev_private;
1328 radeon_fb_output_poll_changed(rdev);
1329 }
1330
1331 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1332 .fb_create = radeon_user_framebuffer_create,
1333 .output_poll_changed = radeon_output_poll_changed
1334 };
1335
1336 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1337 { { 0, "driver" },
1338 { 1, "bios" },
1339 };
1340
1341 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1342 { { TV_STD_NTSC, "ntsc" },
1343 { TV_STD_PAL, "pal" },
1344 { TV_STD_PAL_M, "pal-m" },
1345 { TV_STD_PAL_60, "pal-60" },
1346 { TV_STD_NTSC_J, "ntsc-j" },
1347 { TV_STD_SCART_PAL, "scart-pal" },
1348 { TV_STD_PAL_CN, "pal-cn" },
1349 { TV_STD_SECAM, "secam" },
1350 };
1351
1352 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1353 { { UNDERSCAN_OFF, "off" },
1354 { UNDERSCAN_ON, "on" },
1355 { UNDERSCAN_AUTO, "auto" },
1356 };
1357
1358 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1359 { { RADEON_AUDIO_DISABLE, "off" },
1360 { RADEON_AUDIO_ENABLE, "on" },
1361 { RADEON_AUDIO_AUTO, "auto" },
1362 };
1363
1364 /* XXX support different dither options? spatial, temporal, both, etc. */
1365 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1366 { { RADEON_FMT_DITHER_DISABLE, "off" },
1367 { RADEON_FMT_DITHER_ENABLE, "on" },
1368 };
1369
radeon_modeset_create_props(struct radeon_device * rdev)1370 static int radeon_modeset_create_props(struct radeon_device *rdev)
1371 {
1372 int sz;
1373
1374 if (rdev->is_atom_bios) {
1375 rdev->mode_info.coherent_mode_property =
1376 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1377 if (!rdev->mode_info.coherent_mode_property)
1378 return -ENOMEM;
1379 }
1380
1381 if (!ASIC_IS_AVIVO(rdev)) {
1382 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1383 rdev->mode_info.tmds_pll_property =
1384 drm_property_create_enum(rdev->ddev, 0,
1385 "tmds_pll",
1386 radeon_tmds_pll_enum_list, sz);
1387 }
1388
1389 rdev->mode_info.load_detect_property =
1390 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1391 if (!rdev->mode_info.load_detect_property)
1392 return -ENOMEM;
1393
1394 drm_mode_create_scaling_mode_property(rdev->ddev);
1395
1396 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1397 rdev->mode_info.tv_std_property =
1398 drm_property_create_enum(rdev->ddev, 0,
1399 "tv standard",
1400 radeon_tv_std_enum_list, sz);
1401
1402 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1403 rdev->mode_info.underscan_property =
1404 drm_property_create_enum(rdev->ddev, 0,
1405 "underscan",
1406 radeon_underscan_enum_list, sz);
1407
1408 rdev->mode_info.underscan_hborder_property =
1409 drm_property_create_range(rdev->ddev, 0,
1410 "underscan hborder", 0, 128);
1411 if (!rdev->mode_info.underscan_hborder_property)
1412 return -ENOMEM;
1413
1414 rdev->mode_info.underscan_vborder_property =
1415 drm_property_create_range(rdev->ddev, 0,
1416 "underscan vborder", 0, 128);
1417 if (!rdev->mode_info.underscan_vborder_property)
1418 return -ENOMEM;
1419
1420 sz = ARRAY_SIZE(radeon_audio_enum_list);
1421 rdev->mode_info.audio_property =
1422 drm_property_create_enum(rdev->ddev, 0,
1423 "audio",
1424 radeon_audio_enum_list, sz);
1425
1426 sz = ARRAY_SIZE(radeon_dither_enum_list);
1427 rdev->mode_info.dither_property =
1428 drm_property_create_enum(rdev->ddev, 0,
1429 "dither",
1430 radeon_dither_enum_list, sz);
1431
1432 return 0;
1433 }
1434
radeon_update_display_priority(struct radeon_device * rdev)1435 void radeon_update_display_priority(struct radeon_device *rdev)
1436 {
1437 /* adjustment options for the display watermarks */
1438 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1439 /* set display priority to high for r3xx, rv515 chips
1440 * this avoids flickering due to underflow to the
1441 * display controllers during heavy acceleration.
1442 * Don't force high on rs4xx igp chips as it seems to
1443 * affect the sound card. See kernel bug 15982.
1444 */
1445 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1446 !(rdev->flags & RADEON_IS_IGP))
1447 rdev->disp_priority = 2;
1448 else
1449 rdev->disp_priority = 0;
1450 } else
1451 rdev->disp_priority = radeon_disp_priority;
1452
1453 }
1454
1455 /*
1456 * Allocate hdmi structs and determine register offsets
1457 */
radeon_afmt_init(struct radeon_device * rdev)1458 static void radeon_afmt_init(struct radeon_device *rdev)
1459 {
1460 int i;
1461
1462 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1463 rdev->mode_info.afmt[i] = NULL;
1464
1465 if (ASIC_IS_NODCE(rdev)) {
1466 /* nothing to do */
1467 } else if (ASIC_IS_DCE4(rdev)) {
1468 static uint32_t eg_offsets[] = {
1469 EVERGREEN_CRTC0_REGISTER_OFFSET,
1470 EVERGREEN_CRTC1_REGISTER_OFFSET,
1471 EVERGREEN_CRTC2_REGISTER_OFFSET,
1472 EVERGREEN_CRTC3_REGISTER_OFFSET,
1473 EVERGREEN_CRTC4_REGISTER_OFFSET,
1474 EVERGREEN_CRTC5_REGISTER_OFFSET,
1475 0x13830 - 0x7030,
1476 };
1477 int num_afmt;
1478
1479 /* DCE8 has 7 audio blocks tied to DIG encoders */
1480 /* DCE6 has 6 audio blocks tied to DIG encoders */
1481 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1482 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1483 if (ASIC_IS_DCE8(rdev))
1484 num_afmt = 7;
1485 else if (ASIC_IS_DCE6(rdev))
1486 num_afmt = 6;
1487 else if (ASIC_IS_DCE5(rdev))
1488 num_afmt = 6;
1489 else if (ASIC_IS_DCE41(rdev))
1490 num_afmt = 2;
1491 else /* DCE4 */
1492 num_afmt = 6;
1493
1494 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1495 for (i = 0; i < num_afmt; i++) {
1496 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1497 if (rdev->mode_info.afmt[i]) {
1498 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1499 rdev->mode_info.afmt[i]->id = i;
1500 }
1501 }
1502 } else if (ASIC_IS_DCE3(rdev)) {
1503 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1504 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1505 if (rdev->mode_info.afmt[0]) {
1506 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1507 rdev->mode_info.afmt[0]->id = 0;
1508 }
1509 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1510 if (rdev->mode_info.afmt[1]) {
1511 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1512 rdev->mode_info.afmt[1]->id = 1;
1513 }
1514 } else if (ASIC_IS_DCE2(rdev)) {
1515 /* DCE2 has at least 1 routable audio block */
1516 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1517 if (rdev->mode_info.afmt[0]) {
1518 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1519 rdev->mode_info.afmt[0]->id = 0;
1520 }
1521 /* r6xx has 2 routable audio blocks */
1522 if (rdev->family >= CHIP_R600) {
1523 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1524 if (rdev->mode_info.afmt[1]) {
1525 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1526 rdev->mode_info.afmt[1]->id = 1;
1527 }
1528 }
1529 }
1530 }
1531
radeon_afmt_fini(struct radeon_device * rdev)1532 static void radeon_afmt_fini(struct radeon_device *rdev)
1533 {
1534 int i;
1535
1536 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1537 kfree(rdev->mode_info.afmt[i]);
1538 rdev->mode_info.afmt[i] = NULL;
1539 }
1540 }
1541
radeon_modeset_init(struct radeon_device * rdev)1542 int radeon_modeset_init(struct radeon_device *rdev)
1543 {
1544 int i;
1545 int ret;
1546
1547 drm_mode_config_init(rdev->ddev);
1548 rdev->mode_info.mode_config_initialized = true;
1549
1550 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1551
1552 if (ASIC_IS_DCE5(rdev)) {
1553 rdev->ddev->mode_config.max_width = 16384;
1554 rdev->ddev->mode_config.max_height = 16384;
1555 } else if (ASIC_IS_AVIVO(rdev)) {
1556 rdev->ddev->mode_config.max_width = 8192;
1557 rdev->ddev->mode_config.max_height = 8192;
1558 } else {
1559 rdev->ddev->mode_config.max_width = 4096;
1560 rdev->ddev->mode_config.max_height = 4096;
1561 }
1562
1563 rdev->ddev->mode_config.preferred_depth = 24;
1564 rdev->ddev->mode_config.prefer_shadow = 1;
1565
1566 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1567
1568 ret = radeon_modeset_create_props(rdev);
1569 if (ret) {
1570 return ret;
1571 }
1572
1573 /* init i2c buses */
1574 radeon_i2c_init(rdev);
1575
1576 /* check combios for a valid hardcoded EDID - Sun servers */
1577 if (!rdev->is_atom_bios) {
1578 /* check for hardcoded EDID in BIOS */
1579 radeon_combios_check_hardcoded_edid(rdev);
1580 }
1581
1582 /* allocate crtcs */
1583 for (i = 0; i < rdev->num_crtc; i++) {
1584 radeon_crtc_init(rdev->ddev, i);
1585 }
1586
1587 /* okay we should have all the bios connectors */
1588 ret = radeon_setup_enc_conn(rdev->ddev);
1589 if (!ret) {
1590 return ret;
1591 }
1592
1593 /* init dig PHYs, disp eng pll */
1594 if (rdev->is_atom_bios) {
1595 radeon_atom_encoder_init(rdev);
1596 radeon_atom_disp_eng_pll_init(rdev);
1597 }
1598
1599 /* initialize hpd */
1600 radeon_hpd_init(rdev);
1601
1602 /* setup afmt */
1603 radeon_afmt_init(rdev);
1604
1605 radeon_fbdev_init(rdev);
1606 drm_kms_helper_poll_init(rdev->ddev);
1607
1608 if (rdev->pm.dpm_enabled) {
1609 /* do dpm late init */
1610 ret = radeon_pm_late_init(rdev);
1611 if (ret) {
1612 rdev->pm.dpm_enabled = false;
1613 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1614 }
1615 /* set the dpm state for PX since there won't be
1616 * a modeset to call this.
1617 */
1618 radeon_pm_compute_clocks(rdev);
1619 }
1620
1621 return 0;
1622 }
1623
radeon_modeset_fini(struct radeon_device * rdev)1624 void radeon_modeset_fini(struct radeon_device *rdev)
1625 {
1626 radeon_fbdev_fini(rdev);
1627 kfree(rdev->mode_info.bios_hardcoded_edid);
1628
1629 if (rdev->mode_info.mode_config_initialized) {
1630 radeon_afmt_fini(rdev);
1631 drm_kms_helper_poll_fini(rdev->ddev);
1632 radeon_hpd_fini(rdev);
1633 drm_mode_config_cleanup(rdev->ddev);
1634 rdev->mode_info.mode_config_initialized = false;
1635 }
1636 /* free i2c buses */
1637 radeon_i2c_fini(rdev);
1638 }
1639
is_hdtv_mode(const struct drm_display_mode * mode)1640 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1641 {
1642 /* try and guess if this is a tv or a monitor */
1643 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1644 (mode->vdisplay == 576) || /* 576p */
1645 (mode->vdisplay == 720) || /* 720p */
1646 (mode->vdisplay == 1080)) /* 1080p */
1647 return true;
1648 else
1649 return false;
1650 }
1651
radeon_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1652 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1653 const struct drm_display_mode *mode,
1654 struct drm_display_mode *adjusted_mode)
1655 {
1656 struct drm_device *dev = crtc->dev;
1657 struct radeon_device *rdev = dev->dev_private;
1658 struct drm_encoder *encoder;
1659 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1660 struct radeon_encoder *radeon_encoder;
1661 struct drm_connector *connector;
1662 struct radeon_connector *radeon_connector;
1663 bool first = true;
1664 u32 src_v = 1, dst_v = 1;
1665 u32 src_h = 1, dst_h = 1;
1666
1667 radeon_crtc->h_border = 0;
1668 radeon_crtc->v_border = 0;
1669
1670 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1671 if (encoder->crtc != crtc)
1672 continue;
1673 radeon_encoder = to_radeon_encoder(encoder);
1674 connector = radeon_get_connector_for_encoder(encoder);
1675 radeon_connector = to_radeon_connector(connector);
1676
1677 if (first) {
1678 /* set scaling */
1679 if (radeon_encoder->rmx_type == RMX_OFF)
1680 radeon_crtc->rmx_type = RMX_OFF;
1681 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1682 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1683 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1684 else
1685 radeon_crtc->rmx_type = RMX_OFF;
1686 /* copy native mode */
1687 memcpy(&radeon_crtc->native_mode,
1688 &radeon_encoder->native_mode,
1689 sizeof(struct drm_display_mode));
1690 src_v = crtc->mode.vdisplay;
1691 dst_v = radeon_crtc->native_mode.vdisplay;
1692 src_h = crtc->mode.hdisplay;
1693 dst_h = radeon_crtc->native_mode.hdisplay;
1694
1695 /* fix up for overscan on hdmi */
1696 if (ASIC_IS_AVIVO(rdev) &&
1697 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1698 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1699 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1700 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1701 is_hdtv_mode(mode)))) {
1702 if (radeon_encoder->underscan_hborder != 0)
1703 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1704 else
1705 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1706 if (radeon_encoder->underscan_vborder != 0)
1707 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1708 else
1709 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1710 radeon_crtc->rmx_type = RMX_FULL;
1711 src_v = crtc->mode.vdisplay;
1712 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1713 src_h = crtc->mode.hdisplay;
1714 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1715 }
1716 first = false;
1717 } else {
1718 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1719 /* WARNING: Right now this can't happen but
1720 * in the future we need to check that scaling
1721 * are consistent across different encoder
1722 * (ie all encoder can work with the same
1723 * scaling).
1724 */
1725 DRM_ERROR("Scaling not consistent across encoder.\n");
1726 return false;
1727 }
1728 }
1729 }
1730 if (radeon_crtc->rmx_type != RMX_OFF) {
1731 fixed20_12 a, b;
1732 a.full = dfixed_const(src_v);
1733 b.full = dfixed_const(dst_v);
1734 radeon_crtc->vsc.full = dfixed_div(a, b);
1735 a.full = dfixed_const(src_h);
1736 b.full = dfixed_const(dst_h);
1737 radeon_crtc->hsc.full = dfixed_div(a, b);
1738 } else {
1739 radeon_crtc->vsc.full = dfixed_const(1);
1740 radeon_crtc->hsc.full = dfixed_const(1);
1741 }
1742 return true;
1743 }
1744
1745 /*
1746 * Retrieve current video scanout position of crtc on a given gpu, and
1747 * an optional accurate timestamp of when query happened.
1748 *
1749 * \param dev Device to query.
1750 * \param crtc Crtc to query.
1751 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1752 * \param *vpos Location where vertical scanout position should be stored.
1753 * \param *hpos Location where horizontal scanout position should go.
1754 * \param *stime Target location for timestamp taken immediately before
1755 * scanout position query. Can be NULL to skip timestamp.
1756 * \param *etime Target location for timestamp taken immediately after
1757 * scanout position query. Can be NULL to skip timestamp.
1758 *
1759 * Returns vpos as a positive number while in active scanout area.
1760 * Returns vpos as a negative number inside vblank, counting the number
1761 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1762 * until start of active scanout / end of vblank."
1763 *
1764 * \return Flags, or'ed together as follows:
1765 *
1766 * DRM_SCANOUTPOS_VALID = Query successful.
1767 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1768 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1769 * this flag means that returned position may be offset by a constant but
1770 * unknown small number of scanlines wrt. real scanout position.
1771 *
1772 */
radeon_get_crtc_scanoutpos(struct drm_device * dev,int crtc,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime)1773 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1774 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1775 {
1776 u32 stat_crtc = 0, vbl = 0, position = 0;
1777 int vbl_start, vbl_end, vtotal, ret = 0;
1778 bool in_vbl = true;
1779
1780 struct radeon_device *rdev = dev->dev_private;
1781
1782 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1783
1784 /* Get optional system timestamp before query. */
1785 if (stime)
1786 *stime = ktime_get();
1787
1788 if (ASIC_IS_DCE4(rdev)) {
1789 if (crtc == 0) {
1790 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1791 EVERGREEN_CRTC0_REGISTER_OFFSET);
1792 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1793 EVERGREEN_CRTC0_REGISTER_OFFSET);
1794 ret |= DRM_SCANOUTPOS_VALID;
1795 }
1796 if (crtc == 1) {
1797 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1798 EVERGREEN_CRTC1_REGISTER_OFFSET);
1799 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1800 EVERGREEN_CRTC1_REGISTER_OFFSET);
1801 ret |= DRM_SCANOUTPOS_VALID;
1802 }
1803 if (crtc == 2) {
1804 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1805 EVERGREEN_CRTC2_REGISTER_OFFSET);
1806 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1807 EVERGREEN_CRTC2_REGISTER_OFFSET);
1808 ret |= DRM_SCANOUTPOS_VALID;
1809 }
1810 if (crtc == 3) {
1811 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1812 EVERGREEN_CRTC3_REGISTER_OFFSET);
1813 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1814 EVERGREEN_CRTC3_REGISTER_OFFSET);
1815 ret |= DRM_SCANOUTPOS_VALID;
1816 }
1817 if (crtc == 4) {
1818 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1819 EVERGREEN_CRTC4_REGISTER_OFFSET);
1820 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1821 EVERGREEN_CRTC4_REGISTER_OFFSET);
1822 ret |= DRM_SCANOUTPOS_VALID;
1823 }
1824 if (crtc == 5) {
1825 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1826 EVERGREEN_CRTC5_REGISTER_OFFSET);
1827 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1828 EVERGREEN_CRTC5_REGISTER_OFFSET);
1829 ret |= DRM_SCANOUTPOS_VALID;
1830 }
1831 } else if (ASIC_IS_AVIVO(rdev)) {
1832 if (crtc == 0) {
1833 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1834 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1835 ret |= DRM_SCANOUTPOS_VALID;
1836 }
1837 if (crtc == 1) {
1838 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1839 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1840 ret |= DRM_SCANOUTPOS_VALID;
1841 }
1842 } else {
1843 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1844 if (crtc == 0) {
1845 /* Assume vbl_end == 0, get vbl_start from
1846 * upper 16 bits.
1847 */
1848 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1849 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1850 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1851 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1852 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1853 if (!(stat_crtc & 1))
1854 in_vbl = false;
1855
1856 ret |= DRM_SCANOUTPOS_VALID;
1857 }
1858 if (crtc == 1) {
1859 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1860 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1861 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1862 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1863 if (!(stat_crtc & 1))
1864 in_vbl = false;
1865
1866 ret |= DRM_SCANOUTPOS_VALID;
1867 }
1868 }
1869
1870 /* Get optional system timestamp after query. */
1871 if (etime)
1872 *etime = ktime_get();
1873
1874 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1875
1876 /* Decode into vertical and horizontal scanout position. */
1877 *vpos = position & 0x1fff;
1878 *hpos = (position >> 16) & 0x1fff;
1879
1880 /* Valid vblank area boundaries from gpu retrieved? */
1881 if (vbl > 0) {
1882 /* Yes: Decode. */
1883 ret |= DRM_SCANOUTPOS_ACCURATE;
1884 vbl_start = vbl & 0x1fff;
1885 vbl_end = (vbl >> 16) & 0x1fff;
1886 }
1887 else {
1888 /* No: Fake something reasonable which gives at least ok results. */
1889 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1890 vbl_end = 0;
1891 }
1892
1893 /* Test scanout position against vblank region. */
1894 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1895 in_vbl = false;
1896
1897 /* Check if inside vblank area and apply corrective offsets:
1898 * vpos will then be >=0 in video scanout area, but negative
1899 * within vblank area, counting down the number of lines until
1900 * start of scanout.
1901 */
1902
1903 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1904 if (in_vbl && (*vpos >= vbl_start)) {
1905 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1906 *vpos = *vpos - vtotal;
1907 }
1908
1909 /* Correct for shifted end of vbl at vbl_end. */
1910 *vpos = *vpos - vbl_end;
1911
1912 /* In vblank? */
1913 if (in_vbl)
1914 ret |= DRM_SCANOUTPOS_INVBL;
1915
1916 /* Is vpos outside nominal vblank area, but less than
1917 * 1/100 of a frame height away from start of vblank?
1918 * If so, assume this isn't a massively delayed vblank
1919 * interrupt, but a vblank interrupt that fired a few
1920 * microseconds before true start of vblank. Compensate
1921 * by adding a full frame duration to the final timestamp.
1922 * Happens, e.g., on ATI R500, R600.
1923 *
1924 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1925 */
1926 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1927 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1928 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1929
1930 if (vbl_start - *vpos < vtotal / 100) {
1931 *vpos -= vtotal;
1932
1933 /* Signal this correction as "applied". */
1934 ret |= 0x8;
1935 }
1936 }
1937
1938 return ret;
1939 }
1940