1 // Standard VGA driver code
2 //
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
5 //
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
7
8 #include "biosvar.h" // GET_GLOBAL
9 #include "farptr.h" // SET_FARVAR
10 #include "stdvga.h" // stdvga_setup
11 #include "string.h" // memset_far
12 #include "vgabios.h" // struct vgamode_s
13 #include "vgautil.h" // stdvga_attr_write
14 #include "x86.h" // outb
15
16
17 /****************************************************************
18 * Attribute control
19 ****************************************************************/
20
21 void
stdvga_set_border_color(u8 color)22 stdvga_set_border_color(u8 color)
23 {
24 u8 v1 = color & 0x0f;
25 if (v1 & 0x08)
26 v1 += 0x08;
27 stdvga_attr_write(0x00, v1);
28
29 int i;
30 for (i = 1; i < 4; i++)
31 stdvga_attr_mask(i, 0x10, color & 0x10);
32 }
33
34 void
stdvga_set_overscan_border_color(u8 color)35 stdvga_set_overscan_border_color(u8 color)
36 {
37 stdvga_attr_write(0x11, color);
38 }
39
40 u8
stdvga_get_overscan_border_color(void)41 stdvga_get_overscan_border_color(void)
42 {
43 return stdvga_attr_read(0x11);
44 }
45
46 void
stdvga_set_palette(u8 palid)47 stdvga_set_palette(u8 palid)
48 {
49 int i;
50 for (i = 1; i < 4; i++)
51 stdvga_attr_mask(i, 0x01, palid & 0x01);
52 }
53
54 void
stdvga_set_all_palette_reg(u16 seg,u8 * data_far)55 stdvga_set_all_palette_reg(u16 seg, u8 *data_far)
56 {
57 int i;
58 for (i = 0; i < 0x10; i++) {
59 stdvga_attr_write(i, GET_FARVAR(seg, *data_far));
60 data_far++;
61 }
62 stdvga_attr_write(0x11, GET_FARVAR(seg, *data_far));
63 }
64
65 void
stdvga_get_all_palette_reg(u16 seg,u8 * data_far)66 stdvga_get_all_palette_reg(u16 seg, u8 *data_far)
67 {
68 int i;
69 for (i = 0; i < 0x10; i++) {
70 SET_FARVAR(seg, *data_far, stdvga_attr_read(i));
71 data_far++;
72 }
73 SET_FARVAR(seg, *data_far, stdvga_attr_read(0x11));
74 }
75
76 void
stdvga_toggle_intensity(u8 flag)77 stdvga_toggle_intensity(u8 flag)
78 {
79 stdvga_attr_mask(0x10, 0x08, (flag & 0x01) << 3);
80 }
81
82 void
stdvga_select_video_dac_color_page(u8 flag,u8 data)83 stdvga_select_video_dac_color_page(u8 flag, u8 data)
84 {
85 if (!(flag & 0x01)) {
86 // select paging mode
87 stdvga_attr_mask(0x10, 0x80, data << 7);
88 return;
89 }
90 // select page
91 u8 val = stdvga_attr_read(0x10);
92 if (!(val & 0x80))
93 data <<= 2;
94 data &= 0x0f;
95 stdvga_attr_write(0x14, data);
96 }
97
98 void
stdvga_read_video_dac_state(u8 * pmode,u8 * curpage)99 stdvga_read_video_dac_state(u8 *pmode, u8 *curpage)
100 {
101 u8 val1 = stdvga_attr_read(0x10) >> 7;
102 u8 val2 = stdvga_attr_read(0x14) & 0x0f;
103 if (!(val1 & 0x01))
104 val2 >>= 2;
105 *pmode = val1;
106 *curpage = val2;
107 }
108
109
110 /****************************************************************
111 * DAC control
112 ****************************************************************/
113
114 void
stdvga_perform_gray_scale_summing(u16 start,u16 count)115 stdvga_perform_gray_scale_summing(u16 start, u16 count)
116 {
117 stdvga_attrindex_write(0x00);
118 int i;
119 for (i = start; i < start+count; i++) {
120 u8 rgb[3];
121 stdvga_dac_read(GET_SEG(SS), rgb, i, 1);
122
123 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
124 u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
125 if (intensity > 0x3f)
126 intensity = 0x3f;
127 rgb[0] = rgb[1] = rgb[2] = intensity;
128
129 stdvga_dac_write(GET_SEG(SS), rgb, i, 1);
130 }
131 stdvga_attrindex_write(0x20);
132 }
133
134
135 /****************************************************************
136 * Memory control
137 ****************************************************************/
138
139 void
stdvga_set_text_block_specifier(u8 spec)140 stdvga_set_text_block_specifier(u8 spec)
141 {
142 stdvga_sequ_write(0x03, spec);
143 }
144
145 // Enable reads and writes to the given "plane" when in planar4 mode.
146 void
stdvga_planar4_plane(int plane)147 stdvga_planar4_plane(int plane)
148 {
149 if (plane < 0) {
150 // Return to default mode (read plane0, write all planes)
151 stdvga_sequ_write(0x02, 0x0f);
152 stdvga_grdc_write(0x04, 0);
153 } else {
154 stdvga_sequ_write(0x02, 1<<plane);
155 stdvga_grdc_write(0x04, plane);
156 }
157 }
158
159
160 /****************************************************************
161 * Font loading
162 ****************************************************************/
163
164 static void
get_font_access(void)165 get_font_access(void)
166 {
167 stdvga_sequ_write(0x00, 0x01);
168 stdvga_sequ_write(0x02, 0x04);
169 stdvga_sequ_write(0x04, 0x07);
170 stdvga_sequ_write(0x00, 0x03);
171 stdvga_grdc_write(0x04, 0x02);
172 stdvga_grdc_write(0x05, 0x00);
173 stdvga_grdc_write(0x06, 0x04);
174 }
175
176 static void
release_font_access(void)177 release_font_access(void)
178 {
179 stdvga_sequ_write(0x00, 0x01);
180 stdvga_sequ_write(0x02, 0x03);
181 stdvga_sequ_write(0x04, 0x03);
182 stdvga_sequ_write(0x00, 0x03);
183 u16 v = (stdvga_misc_read() & 0x01) ? 0x0e : 0x0a;
184 stdvga_grdc_write(0x06, v);
185 stdvga_grdc_write(0x04, 0x00);
186 stdvga_grdc_write(0x05, 0x10);
187 }
188
189 void
stdvga_load_font(u16 seg,void * src_far,u16 count,u16 start,u8 destflags,u8 fontsize)190 stdvga_load_font(u16 seg, void *src_far, u16 count
191 , u16 start, u8 destflags, u8 fontsize)
192 {
193 get_font_access();
194 u16 blockaddr = ((destflags & 0x03) << 14) + ((destflags & 0x04) << 11);
195 void *dest_far = (void*)(blockaddr + start*32);
196 u16 i;
197 for (i = 0; i < count; i++)
198 memcpy_far(SEG_GRAPH, dest_far + i*32
199 , seg, src_far + i*fontsize, fontsize);
200 release_font_access();
201 }
202
203
204 /****************************************************************
205 * CRTC registers
206 ****************************************************************/
207
208 u16
stdvga_get_crtc(void)209 stdvga_get_crtc(void)
210 {
211 if (stdvga_misc_read() & 1)
212 return VGAREG_VGA_CRTC_ADDRESS;
213 return VGAREG_MDA_CRTC_ADDRESS;
214 }
215
216 // Ratio between system visible framebuffer ram and the actual videoram used.
217 int
stdvga_vram_ratio(struct vgamode_s * vmode_g)218 stdvga_vram_ratio(struct vgamode_s *vmode_g)
219 {
220 switch (GET_GLOBAL(vmode_g->memmodel)) {
221 case MM_TEXT:
222 return 2;
223 case MM_CGA:
224 return 4 / GET_GLOBAL(vmode_g->depth);
225 case MM_PLANAR:
226 return 4;
227 default:
228 return 1;
229 }
230 }
231
232 void
stdvga_set_cursor_shape(u16 cursor_type)233 stdvga_set_cursor_shape(u16 cursor_type)
234 {
235 u16 crtc_addr = stdvga_get_crtc();
236 stdvga_crtc_write(crtc_addr, 0x0a, cursor_type >> 8);
237 stdvga_crtc_write(crtc_addr, 0x0b, cursor_type);
238 }
239
240 void
stdvga_set_cursor_pos(int address)241 stdvga_set_cursor_pos(int address)
242 {
243 u16 crtc_addr = stdvga_get_crtc();
244 address /= 2; // Assume we're in text mode.
245 stdvga_crtc_write(crtc_addr, 0x0e, address >> 8);
246 stdvga_crtc_write(crtc_addr, 0x0f, address);
247 }
248
249 void
stdvga_set_scan_lines(u8 lines)250 stdvga_set_scan_lines(u8 lines)
251 {
252 stdvga_crtc_mask(stdvga_get_crtc(), 0x09, 0x1f, lines - 1);
253 }
254
255 // Get vertical display end
256 u16
stdvga_get_vde(void)257 stdvga_get_vde(void)
258 {
259 u16 crtc_addr = stdvga_get_crtc();
260 u16 vde = stdvga_crtc_read(crtc_addr, 0x12);
261 u8 ovl = stdvga_crtc_read(crtc_addr, 0x07);
262 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
263 return vde;
264 }
265
266 int
stdvga_get_window(struct vgamode_s * vmode_g,int window)267 stdvga_get_window(struct vgamode_s *vmode_g, int window)
268 {
269 return -1;
270 }
271
272 int
stdvga_set_window(struct vgamode_s * vmode_g,int window,int val)273 stdvga_set_window(struct vgamode_s *vmode_g, int window, int val)
274 {
275 return -1;
276 }
277
278 int
stdvga_get_linelength(struct vgamode_s * vmode_g)279 stdvga_get_linelength(struct vgamode_s *vmode_g)
280 {
281 u8 val = stdvga_crtc_read(stdvga_get_crtc(), 0x13);
282 return val * 8 / stdvga_vram_ratio(vmode_g);
283 }
284
285 int
stdvga_set_linelength(struct vgamode_s * vmode_g,int val)286 stdvga_set_linelength(struct vgamode_s *vmode_g, int val)
287 {
288 val = DIV_ROUND_UP(val * stdvga_vram_ratio(vmode_g), 8);
289 stdvga_crtc_write(stdvga_get_crtc(), 0x13, val);
290 return 0;
291 }
292
293 int
stdvga_get_displaystart(struct vgamode_s * vmode_g)294 stdvga_get_displaystart(struct vgamode_s *vmode_g)
295 {
296 u16 crtc_addr = stdvga_get_crtc();
297 int addr = (stdvga_crtc_read(crtc_addr, 0x0c) << 8
298 | stdvga_crtc_read(crtc_addr, 0x0d));
299 return addr * 4 / stdvga_vram_ratio(vmode_g);
300 }
301
302 int
stdvga_set_displaystart(struct vgamode_s * vmode_g,int val)303 stdvga_set_displaystart(struct vgamode_s *vmode_g, int val)
304 {
305 u16 crtc_addr = stdvga_get_crtc();
306 val = val * stdvga_vram_ratio(vmode_g) / 4;
307 stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
308 stdvga_crtc_write(crtc_addr, 0x0d, val);
309 return 0;
310 }
311
312 int
stdvga_get_dacformat(struct vgamode_s * vmode_g)313 stdvga_get_dacformat(struct vgamode_s *vmode_g)
314 {
315 return -1;
316 }
317
318 int
stdvga_set_dacformat(struct vgamode_s * vmode_g,int val)319 stdvga_set_dacformat(struct vgamode_s *vmode_g, int val)
320 {
321 return -1;
322 }
323
324 int
stdvga_get_linesize(struct vgamode_s * vmode_g)325 stdvga_get_linesize(struct vgamode_s *vmode_g)
326 {
327 return DIV_ROUND_UP(GET_GLOBAL(vmode_g->width) * vga_bpp(vmode_g), 8);
328 }
329
330 /****************************************************************
331 * Save/Restore state
332 ****************************************************************/
333
334 struct saveVideoHardware {
335 u8 sequ_index;
336 u8 crtc_index;
337 u8 grdc_index;
338 u8 actl_index;
339 u8 feature;
340 u8 sequ_regs[4];
341 u8 sequ0;
342 u8 crtc_regs[25];
343 u8 actl_regs[20];
344 u8 grdc_regs[9];
345 u16 crtc_addr;
346 u8 plane_latch[4];
347 } PACKED;
348
349 static void
stdvga_save_hw_state(u16 seg,struct saveVideoHardware * info)350 stdvga_save_hw_state(u16 seg, struct saveVideoHardware *info)
351 {
352 u16 crtc_addr = stdvga_get_crtc();
353 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
354 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
355 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
356 SET_FARVAR(seg, info->actl_index, stdvga_attrindex_read());
357 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
358
359 int i;
360 for (i=0; i<4; i++)
361 SET_FARVAR(seg, info->sequ_regs[i], stdvga_sequ_read(i+1));
362 SET_FARVAR(seg, info->sequ0, stdvga_sequ_read(0));
363
364 for (i=0; i<25; i++)
365 SET_FARVAR(seg, info->crtc_regs[i], stdvga_crtc_read(crtc_addr, i));
366
367 for (i=0; i<20; i++)
368 SET_FARVAR(seg, info->actl_regs[i], stdvga_attr_read(i));
369
370 for (i=0; i<9; i++)
371 SET_FARVAR(seg, info->grdc_regs[i], stdvga_grdc_read(i));
372
373 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
374
375 /* XXX: read plane latches */
376 for (i=0; i<4; i++)
377 SET_FARVAR(seg, info->plane_latch[i], 0);
378 }
379
380 static void
stdvga_restore_hw_state(u16 seg,struct saveVideoHardware * info)381 stdvga_restore_hw_state(u16 seg, struct saveVideoHardware *info)
382 {
383 int i;
384 for (i=0; i<4; i++)
385 stdvga_sequ_write(i+1, GET_FARVAR(seg, info->sequ_regs[i]));
386 stdvga_sequ_write(0x00, GET_FARVAR(seg, info->sequ0));
387
388 // Disable CRTC write protection
389 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
390 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
391 // Set CRTC regs
392 for (i=0; i<25; i++)
393 if (i != 0x11)
394 stdvga_crtc_write(crtc_addr, i, GET_FARVAR(seg, info->crtc_regs[i]));
395 // select crtc base address
396 stdvga_misc_mask(0x01, crtc_addr == VGAREG_VGA_CRTC_ADDRESS ? 0x01 : 0x00);
397
398 // enable write protection if needed
399 stdvga_crtc_write(crtc_addr, 0x11, GET_FARVAR(seg, info->crtc_regs[0x11]));
400
401 // Set Attribute Ctl
402 for (i=0; i<20; i++)
403 stdvga_attr_write(i, GET_FARVAR(seg, info->actl_regs[i]));
404 stdvga_attrindex_write(GET_FARVAR(seg, info->actl_index));
405
406 for (i=0; i<9; i++)
407 stdvga_grdc_write(i, GET_FARVAR(seg, info->grdc_regs[i]));
408
409 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
410 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
411 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
412 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
413 }
414
415 struct saveDACcolors {
416 u8 rwmode;
417 u8 peladdr;
418 u8 pelmask;
419 u8 dac[768];
420 u8 color_select;
421 } PACKED;
422
423 static void
stdvga_save_dac_state(u16 seg,struct saveDACcolors * info)424 stdvga_save_dac_state(u16 seg, struct saveDACcolors *info)
425 {
426 /* XXX: check this */
427 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
428 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
429 SET_FARVAR(seg, info->pelmask, stdvga_pelmask_read());
430 stdvga_dac_read(seg, info->dac, 0, 256);
431 SET_FARVAR(seg, info->color_select, 0);
432 }
433
434 static void
stdvga_restore_dac_state(u16 seg,struct saveDACcolors * info)435 stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info)
436 {
437 stdvga_pelmask_write(GET_FARVAR(seg, info->pelmask));
438 stdvga_dac_write(seg, info->dac, 0, 256);
439 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
440 }
441
442 int
stdvga_save_restore(int cmd,u16 seg,void * data)443 stdvga_save_restore(int cmd, u16 seg, void *data)
444 {
445 void *pos = data;
446 if (cmd & SR_HARDWARE) {
447 if (cmd & SR_SAVE)
448 stdvga_save_hw_state(seg, pos);
449 if (cmd & SR_RESTORE)
450 stdvga_restore_hw_state(seg, pos);
451 pos += sizeof(struct saveVideoHardware);
452 }
453 pos += bda_save_restore(cmd, seg, pos);
454 if (cmd & SR_DAC) {
455 if (cmd & SR_SAVE)
456 stdvga_save_dac_state(seg, pos);
457 if (cmd & SR_RESTORE)
458 stdvga_restore_dac_state(seg, pos);
459 pos += sizeof(struct saveDACcolors);
460 }
461 return pos - data;
462 }
463
464
465 /****************************************************************
466 * Misc
467 ****************************************************************/
468
469 void
stdvga_enable_video_addressing(u8 disable)470 stdvga_enable_video_addressing(u8 disable)
471 {
472 u8 v = (disable & 1) ? 0x00 : 0x02;
473 stdvga_misc_mask(0x02, v);
474 }
475
476 int
stdvga_setup(void)477 stdvga_setup(void)
478 {
479 // switch to color mode and enable CPU access 480 lines
480 stdvga_misc_write(0xc3);
481 // more than 64k 3C4/04
482 stdvga_sequ_write(0x04, 0x02);
483
484 return 0;
485 }
486