1 /* 2 * Copyright (c) 2018, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_huc_hwcmd_g11_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g11_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 29 // DO NOT EDIT 30 31 #ifndef __MHW_VDBOX_HUC_HWCMD_G11_X_H__ 32 #define __MHW_VDBOX_HUC_HWCMD_G11_X_H__ 33 34 #pragma once 35 #pragma pack(1) 36 37 #include <cstdint> 38 #include <cstddef> 39 40 class mhw_vdbox_huc_g11_X 41 { 42 public: 43 // Internal Macros 44 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 45 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 46 #define __CODEGEN_OP_LENGTH_BIAS 2 47 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 48 GetOpLength(uint32_t uiLength)49 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 50 51 //! 52 //! \brief MEMORYADDRESSATTRIBUTES 53 //! \details 54 //! This field controls the priority of arbitration used in the GAC/GAM 55 //! pipeline for this surface. It defines the attributes for VDBOX addresses 56 //! on BDW+. 57 //! 58 struct MEMORYADDRESSATTRIBUTES_CMD 59 { 60 union 61 { 62 struct 63 { 64 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 65 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Base Address - Index to Memory Object Control State (MOCS) Tables 66 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Base Address - Arbitration Priority Control 67 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Base Address - Memory Compression Enable 68 uint32_t BaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< BASE_ADDRESS_MEMORY_COMPRESSION_MODE 69 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 70 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 71 uint32_t BaseAddressTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BASE_ADDRESS_TILED_RESOURCE_MODE 72 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 73 }; 74 uint32_t Value; 75 } DW0; 76 77 //! \name Local enumerations 78 79 //! \brief BASE_ADDRESS_MEMORY_COMPRESSION_MODE 80 //! \details 81 //! Distinguishes vertical from horizontal compression. Please refer to 82 //! vol1a Memory Data Formats chapter - section media Memory 83 //! Compression for more details. 84 enum BASE_ADDRESS_MEMORY_COMPRESSION_MODE 85 { 86 BASE_ADDRESS_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 87 }; 88 89 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 90 //! \details 91 //! This field controls if the Row Store is going to store inside Media 92 //! Cache (rowstore cache) or to LLC. 93 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 94 { 95 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 96 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 97 }; 98 99 //! \brief BASE_ADDRESS_TILED_RESOURCE_MODE 100 //! \details 101 //! For Media Surfaces: This field specifies the tiled resource mode. 102 enum BASE_ADDRESS_TILED_RESOURCE_MODE 103 { 104 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< TileY resources 105 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 106 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 107 }; 108 109 //! \name Initializations 110 111 //! \brief Explicit member initialization function 112 MEMORYADDRESSATTRIBUTES_CMD(); 113 114 static const size_t dwSize = 1; 115 static const size_t byteSize = 4; 116 }; 117 118 //! 119 //! \brief SPLITBASEADDRESS64BYTEALIGNED 120 //! \details 121 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 122 //! address. 123 //! 124 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 125 { 126 union 127 { 128 struct 129 { 130 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 131 uint64_t Graphicsaddress476 : __CODEGEN_BITFIELD( 6, 47) ; //!< GraphicsAddress47-6 132 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 133 }; 134 uint32_t Value[2]; 135 } DW0_1; 136 137 //! \name Local enumerations 138 139 //! \name Initializations 140 141 //! \brief Explicit member initialization function 142 SPLITBASEADDRESS64BYTEALIGNED_CMD(); 143 144 static const size_t dwSize = 2; 145 static const size_t byteSize = 8; 146 }; 147 148 //! 149 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 150 //! \details 151 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 152 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 153 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 154 //! 155 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 156 { 157 union 158 { 159 struct 160 { 161 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 162 uint64_t Graphicsaddress4712 : __CODEGEN_BITFIELD(12, 47) ; //!< GraphicsAddress47-12 163 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 164 }; 165 uint32_t Value[2]; 166 } DW0_1; 167 168 //! \name Local enumerations 169 170 //! \name Initializations 171 172 //! \brief Explicit member initialization function 173 SPLITBASEADDRESS4KBYTEALIGNED_CMD(); 174 175 static const size_t dwSize = 2; 176 static const size_t byteSize = 8; 177 }; 178 179 //! 180 //! \brief HUC_PIPE_MODE_SELECT 181 //! \details 182 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 183 //! Commands. Each HUC command has assigned a media instruction command as 184 //! defined in DWord 0, BitField 22:16. 185 //! 186 //! The HUC_PIPE_MODE_SELECT command is responsible for general pipeline 187 //! level configuration that would normally be set once for a single stream 188 //! decode and would not be modified on a frame workload basis. 189 //! 190 struct HUC_PIPE_MODE_SELECT_CMD 191 { 192 union 193 { 194 struct 195 { 196 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 197 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 198 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 199 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 200 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 201 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 202 }; 203 uint32_t Value; 204 } DW0; 205 union 206 { 207 struct 208 { 209 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 210 uint32_t IndirectStreamOutEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< INDIRECT_STREAM_OUT_ENABLE 211 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 212 }; 213 uint32_t Value; 214 } DW1; 215 union 216 { 217 struct 218 { 219 uint32_t MediaSoftResetCounterPer1000Clocks ; //!< MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 220 }; 221 uint32_t Value; 222 } DW2; 223 224 //! \name Local enumerations 225 226 enum MEDIA_INSTRUCTION_COMMAND 227 { 228 MEDIA_INSTRUCTION_COMMAND_HUCPIPEMODESELECT = 0, //!< No additional details 229 }; 230 231 //! \brief MEDIA_INSTRUCTION_OPCODE 232 //! \details 233 //! Codec/Engine Name = HUP = Bh 234 enum MEDIA_INSTRUCTION_OPCODE 235 { 236 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 237 }; 238 239 enum PIPELINE_TYPE 240 { 241 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 242 }; 243 244 enum COMMAND_TYPE 245 { 246 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 247 }; 248 249 //! \brief INDIRECT_STREAM_OUT_ENABLE 250 //! \details 251 //! Enables the bitstream to be written out to memory immediately following 252 //! the output of the bit stream. The memory buffer is addressed through 253 //! the HuC Indirect Stream Out ObjectBase Address. 254 enum INDIRECT_STREAM_OUT_ENABLE 255 { 256 INDIRECT_STREAM_OUT_ENABLE_DISABLEINDIRECTSTREAMOUT = 0, //!< No additional details 257 INDIRECT_STREAM_OUT_ENABLE_ENABLEINDIRECTSTREAMOUT = 1, //!< No additional details 258 }; 259 260 //! \brief MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 261 //! \details 262 //! In decoder modes, this counter value specifies the number of clocks (per 263 //! 1000) of GAC inactivity 264 //! before a media soft-reset is applied to the HCP and HuC. If counter 265 //! value is set to 0, the media 266 //! soft-reset feature is disabled and no reset will occur. 267 //! In encoder modes, this counter must be set to 0 to disable media 268 //! soft reset. This feature is not 269 //! supported for the encoder. 270 enum MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 271 { 272 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE = 0, //!< No additional details 273 }; 274 275 //! \name Initializations 276 277 //! \brief Explicit member initialization function 278 HUC_PIPE_MODE_SELECT_CMD(); 279 280 static const size_t dwSize = 3; 281 static const size_t byteSize = 12; 282 }; 283 284 //! 285 //! \brief HUC_IMEM_STATE 286 //! \details 287 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 288 //! Commands. Each HUC command has assigned a media instruction command as 289 //! defined in DWord 0, BitField 22:16. 290 //! 291 //! The HUC_IMEM_STATE command is used to fetch the HUC firmware from the 292 //! WOPCM region and load it into the HUC 96KB L2 storage RAM. The 293 //! HUC_IMEM_STATE specifies the firmware's offset in WOPCM which is a cache 294 //! line aligned 32-bit offset address. The firmware, code and data segment 295 //! size should always be less than 96KB. If its greater than 96KB then the 296 //! firmware should be broken into smaller functions so that there is no 297 //! firmware straddling case. 298 //! When the HUC_IMEM_STATE command is received, the hardware confirms that 299 //! the code has been successfully authenticated by checking the VCR 300 //! provided authentication successful signal. If this signal is asserted, 301 //! the firmware is loaded by the HUC DMA into the 96KB L2 storage RAM. Once 302 //! the firmware is loaded, the VALID IMEM LOADED bit in the HUC_STATUS2 303 //! register is asserted high in the. If the authentication signal is not 304 //! asserted, the DMA aborts the HUC_IMEM_STATE command, the firmware is not 305 //! loaded, and the VALID IMEM LOADED bit remains low. 306 //! 307 struct HUC_IMEM_STATE_CMD 308 { 309 union 310 { 311 struct 312 { 313 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 314 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 315 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 316 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 317 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 318 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 319 }; 320 uint32_t Value; 321 } DW0; 322 union 323 { 324 struct 325 { 326 uint32_t Reserved32 ; //!< Reserved 327 }; 328 uint32_t Value; 329 } DW1; 330 union 331 { 332 struct 333 { 334 uint32_t Reserved64 ; //!< Reserved 335 }; 336 uint32_t Value; 337 } DW2; 338 union 339 { 340 struct 341 { 342 uint32_t Reserved96 ; //!< Reserved 343 }; 344 uint32_t Value; 345 } DW3; 346 union 347 { 348 struct 349 { 350 uint32_t HucFirmwareDescriptor : __CODEGEN_BITFIELD( 0, 7) ; //!< HUC_FIRMWARE_DESCRIPTOR 351 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 352 }; 353 uint32_t Value; 354 } DW4; 355 356 //! \name Local enumerations 357 358 enum MEDIA_INSTRUCTION_COMMAND 359 { 360 MEDIA_INSTRUCTION_COMMAND_HUCIMEMSTATE = 1, //!< No additional details 361 }; 362 363 //! \brief MEDIA_INSTRUCTION_OPCODE 364 //! \details 365 //! Codec/Engine Name = HUC = Bh 366 enum MEDIA_INSTRUCTION_OPCODE 367 { 368 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 369 }; 370 371 enum PIPELINE_TYPE 372 { 373 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 374 }; 375 376 enum COMMAND_TYPE 377 { 378 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 379 }; 380 381 //! \brief HUC_FIRMWARE_DESCRIPTOR 382 //! \details 383 //! This field specifies 1 of 255 firmware descriptors which describe 384 //! which firmware is be loaded in the L2 storage RAM. If the firmware 385 //! descriptor is set to zero, the HUC will not load the firmware. 386 enum HUC_FIRMWARE_DESCRIPTOR 387 { 388 HUC_FIRMWARE_DESCRIPTOR_UNNAMED0 = 0, //!< Illegal 389 }; 390 391 //! \name Initializations 392 393 //! \brief Explicit member initialization function 394 HUC_IMEM_STATE_CMD(); 395 396 static const size_t dwSize = 5; 397 static const size_t byteSize = 20; 398 }; 399 400 //! 401 //! \brief HUC_DMEM_STATE 402 //! \details 403 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 404 //! Commands. Each HUC command has assigned a media instruction command as 405 //! defined in DWord 0, BitField 22:16. 406 //! 407 //! The HUC_DMEM_STATE command is used to fetch the HUC data from the 408 //! graphics memory and load it into the HUC 96KB L2 storage RAM. The 409 //! HUC_DMEM_STATE specifies the data source base address in graphics 410 //! memory. 411 //! 412 //! When the HUC_DMEM_STATE command is received, the data is loaded by the 413 //! HUC DMA into the 96KB L2 storage RAM at the location provided in the 414 //! HUC_DMEM_STATE command. This command also specifies the length of the 415 //! data, which is specified in bytes but must be in increments of 64 byte 416 //! cache lines. 417 //! 418 struct HUC_DMEM_STATE_CMD 419 { 420 union 421 { 422 struct 423 { 424 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 425 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 426 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 427 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 428 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 429 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 430 }; 431 uint32_t Value; 432 } DW0; 433 SPLITBASEADDRESS64BYTEALIGNED_CMD HucDataSourceBaseAddress; //!< DW1..2, HUC Data Source - Base Address 434 MEMORYADDRESSATTRIBUTES_CMD HucDataSourceAttributes; //!< DW3, HUC Data Source - Attributes 435 union 436 { 437 struct 438 { 439 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 440 uint32_t HucDataDestinationBaseAddress : __CODEGEN_BITFIELD( 6, 16) ; //!< HUC Data Destination Base Address 441 uint32_t Reserved145 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 442 }; 443 uint32_t Value; 444 } DW4; 445 union 446 { 447 struct 448 { 449 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 450 uint32_t HucDataLength : __CODEGEN_BITFIELD( 6, 16) ; //!< HUC Data Length 451 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 452 }; 453 uint32_t Value; 454 } DW5; 455 456 //! \name Local enumerations 457 458 enum MEDIA_INSTRUCTION_COMMAND 459 { 460 MEDIA_INSTRUCTION_COMMAND_HUCDMEMSTATE = 2, //!< No additional details 461 }; 462 463 //! \brief MEDIA_INSTRUCTION_OPCODE 464 //! \details 465 //! Codec/Engine Name = HUC = Bh 466 enum MEDIA_INSTRUCTION_OPCODE 467 { 468 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 469 }; 470 471 enum PIPELINE_TYPE 472 { 473 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 474 }; 475 476 enum COMMAND_TYPE 477 { 478 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 479 }; 480 481 //! \name Initializations 482 483 //! \brief Explicit member initialization function 484 HUC_DMEM_STATE_CMD(); 485 486 static const size_t dwSize = 6; 487 static const size_t byteSize = 24; 488 }; 489 490 //! 491 //! \brief HUC_CFG_STATE 492 //! \details 493 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 494 //! Commands. Each HUC command has assigned a media instruction command as 495 //! defined in DWord 0, BitField 22:16. 496 //! 497 //! The HUC_CFG_STATE command is used to force the P24C (MinuteIA) into a 498 //! reset condition as well as forcing it out of a reset condition. This 499 //! command is not normally required since the hardware will handle placing 500 //! the P24C into a reset condition and releasing it from reset, but there 501 //! may be conditions that require a forced reset. 502 //! 503 struct HUC_CFG_STATE_CMD 504 { 505 union 506 { 507 struct 508 { 509 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 510 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 511 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 512 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 513 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 514 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 515 }; 516 uint32_t Value; 517 } DW0; 518 union 519 { 520 struct 521 { 522 uint32_t P24CMinuteia : __CODEGEN_BITFIELD( 0, 0) ; //!< P24C_MINUTEIA 523 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 524 }; 525 uint32_t Value; 526 } DW1; 527 528 //! \name Local enumerations 529 530 enum MEDIA_INSTRUCTION_COMMAND 531 { 532 MEDIA_INSTRUCTION_COMMAND_HUCCFGSTATE = 3, //!< No additional details 533 }; 534 535 //! \brief MEDIA_INSTRUCTION_OPCODE 536 //! \details 537 //! Codec/Engine Name = HUC = Bh 538 enum MEDIA_INSTRUCTION_OPCODE 539 { 540 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 541 }; 542 543 enum PIPELINE_TYPE 544 { 545 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 546 }; 547 548 enum COMMAND_TYPE 549 { 550 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 551 }; 552 553 enum P24C_MINUTEIA 554 { 555 P24C_MINUTEIA_NORMALOPERATION = 0, //!< No reset. 556 P24C_MINUTEIA_FORCERESET = 1, //!< No additional details 557 }; 558 559 //! \name Initializations 560 561 //! \brief Explicit member initialization function 562 HUC_CFG_STATE_CMD(); 563 564 static const size_t dwSize = 2; 565 static const size_t byteSize = 8; 566 }; 567 568 //! 569 //! \brief HUC_VIRTUAL_ADDR_REGION 570 //! \details 571 //! 572 //! 573 struct HUC_VIRTUAL_ADDR_REGION_CMD 574 { 575 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucSurfaceBaseAddressVirtualaddrregion015; //!< DW0..2, HUC Surface Base Address (VirtualAddrRegion[0-15]) 576 MEMORYADDRESSATTRIBUTES_CMD HucSurfaceVirtualaddrregion015; //!< DW0..2, HUC Surface (VirtualAddrRegion[0-15]) 577 578 //! \name Local enumerations 579 580 //! \name Initializations 581 582 //! \brief Explicit member initialization function 583 HUC_VIRTUAL_ADDR_REGION_CMD(); 584 585 static const size_t dwSize = 3; 586 static const size_t byteSize = 12; 587 }; 588 589 //! 590 //! \brief HUC_VIRTUAL_ADDR_STATE 591 //! \details 592 //! HUC is selected with the Media Instruction Opcode "Bh" for all HUC 593 //! Commands. Each HUC command has assigned a media instruction command as 594 //! defined in DWord 0, BitField 22:16. 595 //! 596 //! The HUC_VIRTUAL_ADDR_STATE command is used to define the 48-bit HUC 597 //! Surface Base Address and HUC Surface for each region. 598 //! 599 struct HUC_VIRTUAL_ADDR_STATE_CMD 600 { 601 union 602 { 603 struct 604 { 605 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 606 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 607 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 608 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 609 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 610 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 611 }; 612 uint32_t Value; 613 } DW0; 614 HUC_VIRTUAL_ADDR_REGION_CMD HucVirtualAddressRegion[16]; //!< DW1..48, Huc Virtual Address Region 615 616 //! \name Local enumerations 617 618 enum MEDIA_INSTRUCTION_COMMAND 619 { 620 MEDIA_INSTRUCTION_COMMAND_HUCVIRTUALADDRSTATE = 4, //!< No additional details 621 }; 622 623 //! \brief MEDIA_INSTRUCTION_OPCODE 624 //! \details 625 //! Codec/Engine Name = HUC = Bh 626 enum MEDIA_INSTRUCTION_OPCODE 627 { 628 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 629 }; 630 631 enum PIPELINE_TYPE 632 { 633 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 634 }; 635 636 enum COMMAND_TYPE 637 { 638 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 639 }; 640 641 //! \name Initializations 642 643 //! \brief Explicit member initialization function 644 HUC_VIRTUAL_ADDR_STATE_CMD(); 645 646 static const size_t dwSize = 49; 647 static const size_t byteSize = 196; 648 }; 649 650 //! 651 //! \brief HUC_IND_OBJ_BASE_ADDR_STATE 652 //! \details 653 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 654 //! Commands. Each HUC command has assigned a media instruction command as 655 //! defined in DWord 0, BitField 22:16. 656 //! 657 //! The HUC_IND_OBJ_BASE_ADDR_STATE command is used to define the indirect 658 //! object base address of the stream in graphics memory. This is a frame 659 //! level command. 660 //! 661 struct HUC_IND_OBJ_BASE_ADDR_STATE_CMD 662 { 663 union 664 { 665 struct 666 { 667 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 668 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 669 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 670 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 671 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 672 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 673 }; 674 uint32_t Value; 675 } DW0; 676 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamInObjectbaseAddress; //!< DW1..2, HUC Indirect Stream In ObjectBase Address 677 MEMORYADDRESSATTRIBUTES_CMD HucIndirectStreamInObjectbaseAttributes; //!< DW3, HUC Indirect Stream In ObjectBase Attributes 678 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamInObjectaccessUpperBound; //!< DW4..5, HUC Indirect Stream In ObjectAccess Upper Bound 679 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamOutObjectbaseAddress; //!< DW6..7, HUC Indirect Stream Out ObjectBase Address 680 MEMORYADDRESSATTRIBUTES_CMD HucIndirectStreamOutObjectbaseAttributes; //!< DW8, HUC Indirect Stream Out ObjectBase Attributes 681 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamOutObjectaccessUpperBound; //!< DW9..10, HUC Indirect Stream Out ObjectAccess Upper Bound 682 683 //! \name Local enumerations 684 685 enum MEDIA_INSTRUCTION_COMMAND 686 { 687 MEDIA_INSTRUCTION_COMMAND_HUCINDOBJBASEADDRSTATE = 5, //!< No additional details 688 }; 689 690 //! \brief MEDIA_INSTRUCTION_OPCODE 691 //! \details 692 //! Codec/Engine Name = HUC = Bh 693 enum MEDIA_INSTRUCTION_OPCODE 694 { 695 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 696 }; 697 698 enum PIPELINE_TYPE 699 { 700 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 701 }; 702 703 enum COMMAND_TYPE 704 { 705 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 706 }; 707 708 //! \name Initializations 709 710 //! \brief Explicit member initialization function 711 HUC_IND_OBJ_BASE_ADDR_STATE_CMD(); 712 713 static const size_t dwSize = 11; 714 static const size_t byteSize = 44; 715 }; 716 717 //! 718 //! \brief HUC_STREAM_OBJECT 719 //! \details 720 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 721 //! Commands. Each HUC command has assigned a media instruction command as 722 //! defined in DWord 0, BitField 22:16. 723 //! 724 //! The HUC_STREAM_OBJECT command is used to define the bit stream address 725 //! offset to the Stream Indirect Object base Address and the length of the 726 //! bit stream. The bitstream buffer the HUC operates upon is specified 727 //! through indirect addressing. 728 //! 729 struct HUC_STREAM_OBJECT_CMD 730 { 731 union 732 { 733 struct 734 { 735 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 736 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 737 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 738 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 739 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 740 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 741 }; 742 uint32_t Value; 743 } DW0; 744 union 745 { 746 struct 747 { 748 uint32_t IndirectStreamInDataLength ; //!< Indirect Stream In Data Length 749 }; 750 uint32_t Value; 751 } DW1; 752 union 753 { 754 struct 755 { 756 uint32_t IndirectStreamInStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Stream In Start Address 757 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 30) ; //!< Reserved 758 uint32_t HucProcessing : __CODEGEN_BITFIELD(31, 31) ; //!< HUC_PROCESSING 759 }; 760 uint32_t Value; 761 } DW2; 762 union 763 { 764 struct 765 { 766 uint32_t IndirectStreamOutStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Stream Out Start Address 767 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 768 }; 769 uint32_t Value; 770 } DW3; 771 union 772 { 773 struct 774 { 775 uint32_t StartCodeByte0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Start Code Byte [0] 776 uint32_t StartCodeByte1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Start Code Byte [1] 777 uint32_t StartCodeByte2 : __CODEGEN_BITFIELD(16, 23) ; //!< Start Code Byte [2] 778 uint32_t StartCodeSearchEngine : __CODEGEN_BITFIELD(24, 24) ; //!< START_CODE_SEARCH_ENGINE 779 uint32_t EmulationPreventionByteRemoval : __CODEGEN_BITFIELD(25, 25) ; //!< EMULATION_PREVENTION_BYTE_REMOVAL 780 uint32_t StreamOut : __CODEGEN_BITFIELD(26, 26) ; //!< STREAM_OUT 781 uint32_t Drmlengthmode : __CODEGEN_BITFIELD(27, 28) ; //!< DRMLENGTHMODE 782 uint32_t HucBitstreamEnable : __CODEGEN_BITFIELD(29, 29) ; //!< HUC_BITSTREAM_ENABLE 783 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 784 }; 785 uint32_t Value; 786 } DW4; 787 788 //! \name Local enumerations 789 790 enum MEDIA_INSTRUCTION_COMMAND 791 { 792 MEDIA_INSTRUCTION_COMMAND_HUCSTREAMOBJECT = 32, //!< No additional details 793 }; 794 795 //! \brief MEDIA_INSTRUCTION_OPCODE 796 //! \details 797 //! Codec/Engine Name = HUC = Bh 798 enum MEDIA_INSTRUCTION_OPCODE 799 { 800 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 801 }; 802 803 enum PIPELINE_TYPE 804 { 805 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 806 }; 807 808 enum COMMAND_TYPE 809 { 810 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 811 }; 812 813 //! \brief HUC_PROCESSING 814 //! \details 815 //! Disables the HEVC Decoder CABAC engine to prevent it from starting 816 //! while the HuC is processing. Must be set to "1" for HUC processing so 817 //! that the stream is directed to the HuC and not the CABAC engine. 818 enum HUC_PROCESSING 819 { 820 HUC_PROCESSING_DISABLE = 1, //!< No additional details 821 }; 822 823 enum START_CODE_SEARCH_ENGINE 824 { 825 START_CODE_SEARCH_ENGINE_DISABLE = 0, //!< Bypass Start Code Search Engine 826 START_CODE_SEARCH_ENGINE_ENABLE = 1, //!< Enables the start code search engine to stop on every third byte start code defined by Start Code Byte [2:0] defined in this DWord. 827 }; 828 829 enum EMULATION_PREVENTION_BYTE_REMOVAL 830 { 831 EMULATION_PREVENTION_BYTE_REMOVAL_DISABLE = 0, //!< Bypass Emulation Prevention Byte Removal. 832 EMULATION_PREVENTION_BYTE_REMOVAL_ENABLE = 1, //!< Emulation prevention bytes will be removed after the start code search engine. 833 }; 834 835 //! \brief STREAM_OUT 836 //! \details 837 //! Enables the stream output. 838 enum STREAM_OUT 839 { 840 STREAM_OUT_DISABLE = 0, //!< Disable the stream output. 841 STREAM_OUT_ENABLE = 1, //!< Enable the stream output. 842 }; 843 844 enum DRMLENGTHMODE 845 { 846 DRMLENGTHMODE_STARTCODEMODE = 0, //!< Stops on a start code 847 DRMLENGTHMODE_LENGTHMODE = 1, //!< Stops after a number of bytes are reached in the length counter 848 }; 849 850 //! \brief HUC_BITSTREAM_ENABLE 851 //! \details 852 //! style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; 853 //! line-height: normal;">Enables the bitstream to be sent to the HuC 854 enum HUC_BITSTREAM_ENABLE 855 { 856 HUC_BITSTREAM_ENABLE_DISABLE = 0, //!< No additional details 857 HUC_BITSTREAM_ENABLE_ENABLE = 1, //!< No additional details 858 }; 859 860 //! \name Initializations 861 862 //! \brief Explicit member initialization function 863 HUC_STREAM_OBJECT_CMD(); 864 865 static const size_t dwSize = 5; 866 static const size_t byteSize = 20; 867 }; 868 869 //! 870 //! \brief HUC_START 871 //! \details 872 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 873 //! Commands. Each HUC command has assigned a media instruction command as 874 //! defined in DWord 0, BitField 22:16. 875 //! 876 struct HUC_START_CMD 877 { 878 union 879 { 880 struct 881 { 882 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 883 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 884 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 885 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 886 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 887 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 888 }; 889 uint32_t Value; 890 } DW0; 891 union 892 { 893 struct 894 { 895 uint32_t Laststreamobject : __CODEGEN_BITFIELD( 0, 0) ; //!< LASTSTREAMOBJECT 896 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 897 }; 898 uint32_t Value; 899 } DW1; 900 901 //! \name Local enumerations 902 903 enum MEDIA_INSTRUCTION_COMMAND 904 { 905 MEDIA_INSTRUCTION_COMMAND_HUCSTART = 33, //!< No additional details 906 }; 907 908 //! \brief MEDIA_INSTRUCTION_OPCODE 909 //! \details 910 //! Codec/Engine Name = HUC = Bh 911 enum MEDIA_INSTRUCTION_OPCODE 912 { 913 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 914 }; 915 916 enum PIPELINE_TYPE 917 { 918 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 919 }; 920 921 enum COMMAND_TYPE 922 { 923 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 924 }; 925 926 enum LASTSTREAMOBJECT 927 { 928 LASTSTREAMOBJECT_NOTLASTSTREAMOBJECT = 0, //!< Not the last stream object in the workload. 929 LASTSTREAMOBJECT_LASTSTREAMOBJECT = 1, //!< Last stream object in the workload. 930 }; 931 932 //! \name Initializations 933 934 //! \brief Explicit member initialization function 935 HUC_START_CMD(); 936 937 static const size_t dwSize = 2; 938 static const size_t byteSize = 8; 939 }; 940 941 }; 942 943 #pragma pack() 944 945 #endif // __MHW_VDBOX_HUC_HWCMD_G11_X_H__