1 /*===================== begin_copyright_notice ================================== 2 3 Copyright (c) 2017-2019, Intel Corporation 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included 13 in all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_vdbox_vdenc_hwcmd_g12_X.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of g12_X as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 #ifndef __MHW_VDBOX_VDENC_HWCMD_G12_X_H__ 31 #define __MHW_VDBOX_VDENC_HWCMD_G12_X_H__ 32 33 #pragma once 34 #pragma pack(1) 35 36 #include <cstdint> 37 #include <cstddef> 38 39 class mhw_vdbox_vdenc_g12_X 40 { 41 public: 42 // Internal Macros 43 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 44 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 45 #define __CODEGEN_OP_LENGTH_BIAS 2 46 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 47 GetOpLength(uint32_t uiLength)48 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 49 50 //! 51 //! \brief VDENC_64B_Aligned_Lower_Address 52 //! \details 53 //! 54 //! 55 struct VDENC_64B_Aligned_Lower_Address_CMD 56 { 57 union 58 { 59 //!< DWORD 0 60 struct 61 { 62 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 63 uint32_t Address : __CODEGEN_BITFIELD( 6, 31) ; //!< Address 64 }; 65 uint32_t Value; 66 } DW0; 67 68 //! \name Local enumerations 69 70 //! \name Initializations 71 72 //! \brief Explicit member initialization function 73 VDENC_64B_Aligned_Lower_Address_CMD(); 74 75 static const size_t dwSize = 1; 76 static const size_t byteSize = 4; 77 }; 78 79 //! 80 //! \brief VDENC_64B_Aligned_Upper_Address 81 //! \details 82 //! 83 //! 84 struct VDENC_64B_Aligned_Upper_Address_CMD 85 { 86 union 87 { 88 //!< DWORD 0 89 struct 90 { 91 uint32_t AddressUpperDword : __CODEGEN_BITFIELD( 0, 15) ; //!< Address Upper DWord 92 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 93 }; 94 uint32_t Value; 95 } DW0; 96 97 //! \name Local enumerations 98 99 //! \name Initializations 100 101 //! \brief Explicit member initialization function 102 VDENC_64B_Aligned_Upper_Address_CMD(); 103 104 static const size_t dwSize = 1; 105 static const size_t byteSize = 4; 106 }; 107 108 //! 109 //! \brief VDENC_Surface_Control_Bits 110 //! \details 111 //! 112 //! 113 struct VDENC_Surface_Control_Bits_CMD 114 { 115 union 116 { 117 //!< DWORD 0 118 struct 119 { 120 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Index to Memory Object Control State (MOCS) Tables: 121 uint32_t ArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< ARBITRATION_PRIORITY_CONTROL 122 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MEMORY_COMPRESSION_ENABLE 123 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< Compression Type 124 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 125 uint32_t CacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< CACHE_SELECT 126 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< TILED_RESOURCE_MODE 127 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 128 }; 129 uint32_t Value; 130 } DW0; 131 132 //! \name Local enumerations 133 134 //! \brief ARBITRATION_PRIORITY_CONTROL 135 //! \details 136 //! This field controls the priority of arbitration used in the GAC/GAM 137 //! pipeline for this surface. 138 enum ARBITRATION_PRIORITY_CONTROL 139 { 140 ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 141 ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 142 ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 143 ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 144 }; 145 146 //! \brief MEMORY_COMPRESSION_ENABLE 147 //! \details 148 //! Memory compression will be attempted for this surface. 149 enum MEMORY_COMPRESSION_ENABLE 150 { 151 MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 152 MEMORY_COMPRESSION_ENABLE_ENABLE = 1, //!< No additional details 153 }; 154 155 //! \brief MEMORY_COMPRESSION_MODE 156 //! \details 157 //! Distinguishes Vertical from Horizontal compression. Please refer to 158 //! vol1a <b>Memory Data</b>. 159 enum MEMORY_COMPRESSION_MODE 160 { 161 MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 162 MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 163 }; 164 165 //! \brief CACHE_SELECT 166 //! \details 167 //! This field controls if the Row Store is going to store inside Media 168 //! Cache (rowstore cache) or to LLC. 169 enum CACHE_SELECT 170 { 171 CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 172 CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 173 }; 174 175 //! \brief TILED_RESOURCE_MODE 176 //! \details 177 //! <b>For Media Surfaces</b>: This field specifies the tiled resource mode. 178 enum TILED_RESOURCE_MODE 179 { 180 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource. 181 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 182 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 183 }; 184 185 //! \name Initializations 186 187 //! \brief Explicit member initialization function 188 VDENC_Surface_Control_Bits_CMD(); 189 190 static const size_t dwSize = 1; 191 static const size_t byteSize = 4; 192 }; 193 194 //! 195 //! \brief VDENC_Sub_Mb_Pred_Mode 196 //! \details 197 //! 198 //! 199 struct VDENC_Sub_Mb_Pred_Mode_CMD 200 { 201 union 202 { 203 //!< WORD 0 204 struct 205 { 206 uint8_t Submbpredmode0 : __CODEGEN_BITFIELD( 0, 1) ; //!< SubMbPredMode[0] 207 uint8_t Submbpredmode1 : __CODEGEN_BITFIELD( 2, 3) ; //!< SubMbPredMode[1] 208 uint8_t Submbpredmode2 : __CODEGEN_BITFIELD( 4, 5) ; //!< SubMbPredMode[2] 209 uint8_t Submbpredmode3 : __CODEGEN_BITFIELD( 6, 7) ; //!< SubMbPredMode[3] 210 }; 211 uint8_t Value; 212 } DW0; 213 214 //! \name Local enumerations 215 216 //! \name Initializations 217 218 //! \brief Explicit member initialization function 219 VDENC_Sub_Mb_Pred_Mode_CMD(); 220 221 static const size_t dwSize = 0; 222 static const size_t byteSize = 1; 223 }; 224 225 //! 226 //! \brief VDENC_Block_8x8_4 227 //! \details 228 //! 229 //! 230 struct VDENC_Block_8x8_4_CMD 231 { 232 union 233 { 234 //!< WORD 0 235 struct 236 { 237 uint16_t Block8X80 : __CODEGEN_BITFIELD( 0, 3) ; //!< Block8x8[0] 238 uint16_t Block8X81 : __CODEGEN_BITFIELD( 4, 7) ; //!< Block8x8[1] 239 uint16_t Block8X82 : __CODEGEN_BITFIELD( 8, 11) ; //!< Block8x8[2] 240 uint16_t Block8X83 : __CODEGEN_BITFIELD(12, 15) ; //!< Block8x8[3] 241 }; 242 uint16_t Value; 243 } DW0; 244 245 //! \name Local enumerations 246 247 //! \name Initializations 248 249 //! \brief Explicit member initialization function 250 VDENC_Block_8x8_4_CMD(); 251 252 static const size_t dwSize = 0; 253 static const size_t byteSize = 2; 254 }; 255 256 //! 257 //! \brief VDENC_Delta_MV_XY 258 //! \details 259 //! 260 //! 261 //! Calculates the difference between the actual MV for the Sub Macroblock 262 //! and the predicted MV based on the availability of the neighbors. 263 //! 264 //! This is calculated and populated for Inter frames only. In case of an 265 //! Intra MB in Inter frames, this value should be 0. 266 //! 267 struct VDENC_Delta_MV_XY_CMD 268 { 269 union 270 { 271 //!< DWORD 0 272 struct 273 { 274 uint32_t X0 : __CODEGEN_BITFIELD( 0, 15) ; //!< X0 275 uint32_t Y0 : __CODEGEN_BITFIELD(16, 31) ; //!< Y0 276 }; 277 uint32_t Value; 278 } DW0; 279 union 280 { 281 //!< DWORD 1 282 struct 283 { 284 uint32_t X1 : __CODEGEN_BITFIELD( 0, 15) ; //!< X1 285 uint32_t Y1 : __CODEGEN_BITFIELD(16, 31) ; //!< Y1 286 }; 287 uint32_t Value; 288 } DW1; 289 union 290 { 291 //!< DWORD 2 292 struct 293 { 294 uint32_t X2 : __CODEGEN_BITFIELD( 0, 15) ; //!< X2 295 uint32_t Y2 : __CODEGEN_BITFIELD(16, 31) ; //!< Y2 296 }; 297 uint32_t Value; 298 } DW2; 299 union 300 { 301 //!< DWORD 3 302 struct 303 { 304 uint32_t X3 : __CODEGEN_BITFIELD( 0, 15) ; //!< X3 305 uint32_t Y3 : __CODEGEN_BITFIELD(16, 31) ; //!< Y3 306 }; 307 uint32_t Value; 308 } DW3; 309 310 //! \name Local enumerations 311 312 //! \brief X0 313 //! \details 314 enum X0 315 { 316 X0_UNNAMED0 = 0, //!< No additional details 317 }; 318 319 //! \brief Y0 320 //! \details 321 enum Y0 322 { 323 Y0_UNNAMED0 = 0, //!< No additional details 324 }; 325 326 //! \brief X1 327 //! \details 328 enum X1 329 { 330 X1_UNNAMED0 = 0, //!< No additional details 331 }; 332 333 //! \brief Y1 334 //! \details 335 enum Y1 336 { 337 Y1_UNNAMED0 = 0, //!< No additional details 338 }; 339 340 //! \brief X2 341 //! \details 342 enum X2 343 { 344 X2_UNNAMED0 = 0, //!< No additional details 345 }; 346 347 //! \brief Y2 348 //! \details 349 enum Y2 350 { 351 Y2_UNNAMED0 = 0, //!< No additional details 352 }; 353 354 //! \brief X3 355 //! \details 356 enum X3 357 { 358 X3_UNNAMED0 = 0, //!< No additional details 359 }; 360 361 //! \brief Y3 362 //! \details 363 enum Y3 364 { 365 Y3_UNNAMED0 = 0, //!< No additional details 366 }; 367 368 //! \name Initializations 369 370 //! \brief Explicit member initialization function 371 VDENC_Delta_MV_XY_CMD(); 372 373 static const size_t dwSize = 4; 374 static const size_t byteSize = 16; 375 }; 376 377 //! 378 //! \brief VDENC_Colocated_MV_Picture 379 //! \details 380 //! 381 //! 382 struct VDENC_Colocated_MV_Picture_CMD 383 { 384 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 385 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 386 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 387 388 //! \name Local enumerations 389 390 //! \name Initializations 391 392 //! \brief Explicit member initialization function 393 VDENC_Colocated_MV_Picture_CMD(); 394 395 static const size_t dwSize = 3; 396 static const size_t byteSize = 12; 397 }; 398 399 //! 400 //! \brief VDENC_Down_Scaled_Reference_Picture 401 //! \details 402 //! 403 //! 404 struct VDENC_Down_Scaled_Reference_Picture_CMD 405 { 406 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 407 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 408 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 409 410 //! \name Local enumerations 411 412 //! \name Initializations 413 414 //! \brief Explicit member initialization function 415 VDENC_Down_Scaled_Reference_Picture_CMD(); 416 417 static const size_t dwSize = 3; 418 static const size_t byteSize = 12; 419 }; 420 421 //! 422 //! \brief VDENC_FRAME_BASED_STATISTICS_STREAMOUT 423 //! \details 424 //! 425 //! 426 struct VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD 427 { 428 union 429 { 430 //!< DWORD 0 431 struct 432 { 433 uint32_t SumSadHaarForBestMbChoice ; //!< Sum sad\haar for best MB choice 434 }; 435 uint32_t Value; 436 } DW0; 437 union 438 { 439 //!< DWORD 1 440 struct 441 { 442 uint32_t IntraIso16X16MbCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra iso 16x16 MB count 443 uint32_t IntraMbCount : __CODEGEN_BITFIELD(16, 31) ; //!< Intra MB count 444 }; 445 uint32_t Value; 446 } DW1; 447 union 448 { 449 //!< DWORD 2 450 struct 451 { 452 uint32_t IntraIso4X4MbCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra iso 4x4 MB count 453 uint32_t IntraIso8X8MbCount : __CODEGEN_BITFIELD(16, 31) ; //!< Intra iso 8x8 MB count 454 }; 455 uint32_t Value; 456 } DW2; 457 union 458 { 459 //!< DWORD 3 460 struct 461 { 462 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD( 0, 15) ; //!< segment map count 0 463 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD(16, 31) ; //!< segment map count 1 464 }; 465 uint32_t Value; 466 } DW3; 467 union 468 { 469 //!< DWORD 4 470 struct 471 { 472 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD( 0, 15) ; //!< segment map count 2 473 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD(16, 31) ; //!< segment map count 3 474 }; 475 uint32_t Value; 476 } DW4; 477 478 uint32_t Reserved160[12]; //!< Reserved 479 480 union 481 { 482 //!< DWORD 17 483 struct 484 { 485 uint32_t SumSadHaarForBestMbChoiceBottomHalfPopulation ; //!< Sum sad\haar for best MB choice bottom half population 486 }; 487 uint32_t Value; 488 } DW17; 489 union 490 { 491 //!< DWORD 18 492 struct 493 { 494 uint32_t SumSadHaarForBestMbChoiceTopHalfPopulation ; //!< Sum sad\haar for best MB choice top half population 495 }; 496 uint32_t Value; 497 } DW18; 498 union 499 { 500 //!< DWORD 19 501 struct 502 { 503 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD( 0, 15) ; //!< Sum top half population occurrences 504 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31) ; //!< Sum bottom half population occurrences 505 }; 506 uint32_t Value; 507 } DW19; 508 509 //! \name Local enumerations 510 511 //! \name Initializations 512 513 //! \brief Explicit member initialization function 514 VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD(); 515 516 static const size_t dwSize = 20; 517 static const size_t byteSize = 80; 518 }; 519 520 //! 521 //! \brief VDENC_Mode_StreamOut_Data 522 //! \details 523 //! 524 //! 525 struct VDENC_Mode_StreamOut_Data_CMD 526 { 527 union 528 { 529 //!< DWORD 0 530 struct 531 { 532 uint32_t MbX : __CODEGEN_BITFIELD( 0, 7) ; //!< MB.X 533 uint32_t MbY : __CODEGEN_BITFIELD( 8, 15) ; //!< MB.Y 534 uint32_t MinimalDistortion : __CODEGEN_BITFIELD(16, 31) ; //!< Minimal Distortion 535 }; 536 uint32_t Value; 537 } DW0; 538 union 539 { 540 //!< DWORD 1 541 struct 542 { 543 uint32_t Skiprawdistortion : __CODEGEN_BITFIELD( 0, 15) ; //!< SkipRawDistortion 544 uint32_t Interrawdistortion : __CODEGEN_BITFIELD(16, 31) ; //!< InterRawDistortion 545 }; 546 uint32_t Value; 547 } DW1; 548 union 549 { 550 //!< DWORD 2 551 struct 552 { 553 uint32_t Bestintrarawdistortion : __CODEGEN_BITFIELD( 0, 15) ; //!< BestIntraRawDistortion 554 uint32_t IntermbmodeChromaPredictionMode : __CODEGEN_BITFIELD(16, 17) ; //!< INTERMBMODECHROMA_PREDICTION_MODE 555 uint32_t Intrambmode : __CODEGEN_BITFIELD(18, 19) ; //!< INTRAMBMODE 556 uint32_t Intrambflag : __CODEGEN_BITFIELD(20, 20) ; //!< INTRAMBFLAG 557 uint32_t Lastmbflag : __CODEGEN_BITFIELD(21, 21) ; //!< LASTMBFLAG 558 uint32_t CoefficientClampOccurred : __CODEGEN_BITFIELD(22, 22) ; //!< Coefficient Clamp Occurred 559 uint32_t ConformanceViolation : __CODEGEN_BITFIELD(23, 23) ; //!< Conformance Violation 560 uint32_t Submbpredmode : __CODEGEN_BITFIELD(24, 31) ; //!< SubMbPredMode 561 }; 562 uint32_t Value; 563 } DW2; 564 union 565 { 566 //!< DWORD 3 567 struct 568 { 569 uint32_t Lumaintramode0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LumaIntraMode[0] 570 uint32_t Lumaintramode1 : __CODEGEN_BITFIELD(16, 31) ; //!< LumaIntraMode[1] 571 }; 572 uint32_t Value; 573 } DW3; 574 union 575 { 576 //!< DWORD 4 577 struct 578 { 579 uint32_t Lumaintramode2 : __CODEGEN_BITFIELD( 0, 15) ; //!< LumaIntraMode[2] 580 uint32_t Lumaintramode3 : __CODEGEN_BITFIELD(16, 31) ; //!< LumaIntraMode[3] 581 }; 582 uint32_t Value; 583 } DW4; 584 VDENC_Delta_MV_XY_CMD DeltaMv0 ; //!< Delta MV0 585 VDENC_Delta_MV_XY_CMD DeltaMv1 ; //!< Delta MV1 586 union 587 { 588 //!< DWORD 13 589 struct 590 { 591 uint32_t FwdRefids : __CODEGEN_BITFIELD( 0, 15) ; //!< FWD REFIDs 592 uint32_t BwdRefids : __CODEGEN_BITFIELD(16, 31) ; //!< BWD REFIDs 593 }; 594 uint32_t Value; 595 } DW13; 596 union 597 { 598 //!< DWORD 14 599 struct 600 { 601 uint32_t QpY : __CODEGEN_BITFIELD( 0, 5) ; //!< QP_y 602 uint32_t MbBitCount : __CODEGEN_BITFIELD( 6, 18) ; //!< MB_Bit_Count 603 uint32_t MbHeaderCount : __CODEGEN_BITFIELD(19, 31) ; //!< MB_Header_Count 604 }; 605 uint32_t Value; 606 } DW14; 607 union 608 { 609 //!< DWORD 15 610 struct 611 { 612 uint32_t MbType : __CODEGEN_BITFIELD( 0, 4) ; //!< MB Type 613 uint32_t BlockCbp : __CODEGEN_BITFIELD( 5, 30) ; //!< Block CBP 614 uint32_t Skipmbflag : __CODEGEN_BITFIELD(31, 31) ; //!< SkipMbFlag 615 }; 616 uint32_t Value; 617 } DW15; 618 619 //! \name Local enumerations 620 621 //! \brief INTERMBMODECHROMA_PREDICTION_MODE 622 //! \details 623 //! This field indicates the InterMB Parition type for Inter MB. 624 //! <br>OR</br> 625 //! This field indicates Chroma Prediction Mode for Intra MB. 626 enum INTERMBMODECHROMA_PREDICTION_MODE 627 { 628 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED0 = 0, //!< 16x16 629 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED1 = 1, //!< 16x8 630 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED2 = 2, //!< 8x16 631 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED3 = 3, //!< 8x8 632 }; 633 634 //! \brief INTRAMBMODE 635 //! \details 636 //! This field indicates the Best Intra Partition. 637 enum INTRAMBMODE 638 { 639 INTRAMBMODE_UNNAMED0 = 0, //!< 16x16 640 INTRAMBMODE_UNNAMED1 = 1, //!< 8x8 641 INTRAMBMODE_UNNAMED2 = 2, //!< 4x4 642 }; 643 644 //! \brief INTRAMBFLAG 645 //! \details 646 //! This field specifies whether the current macroblock is an Intra (I) 647 //! macroblock. 648 enum INTRAMBFLAG 649 { 650 INTRAMBFLAG_INTER = 0, //!< inter macroblock 651 INTRAMBFLAG_INTRA = 1, //!< intra macroblock 652 }; 653 654 enum LASTMBFLAG 655 { 656 LASTMBFLAG_NOTLAST = 0, //!< The current MB is not the last MB in the current Slice. 657 LASTMBFLAG_LAST = 1, //!< The current MB is the last MB in the current Slice. 658 }; 659 660 //! \name Initializations 661 662 //! \brief Explicit member initialization function 663 VDENC_Mode_StreamOut_Data_CMD(); 664 665 static const size_t dwSize = 16; 666 static const size_t byteSize = 64; 667 }; 668 669 //! 670 //! \brief VDENC_Original_Uncompressed_Picture 671 //! \details 672 //! 673 //! 674 struct VDENC_Original_Uncompressed_Picture_CMD 675 { 676 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 677 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 678 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 679 680 //! \name Local enumerations 681 682 //! \name Initializations 683 684 //! \brief Explicit member initialization function 685 VDENC_Original_Uncompressed_Picture_CMD(); 686 687 static const size_t dwSize = 3; 688 static const size_t byteSize = 12; 689 }; 690 691 //! 692 //! \brief VDENC_Reference_Picture 693 //! \details 694 //! 695 //! 696 struct VDENC_Reference_Picture_CMD 697 { 698 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 699 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 700 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 701 702 //! \name Local enumerations 703 704 //! \name Initializations 705 706 //! \brief Explicit member initialization function 707 VDENC_Reference_Picture_CMD(); 708 709 static const size_t dwSize = 3; 710 static const size_t byteSize = 12; 711 }; 712 713 //! 714 //! \brief VDENC_Row_Store_Scratch_Buffer_Picture 715 //! \details 716 //! 717 //! 718 struct VDENC_Row_Store_Scratch_Buffer_Picture_CMD 719 { 720 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 721 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 722 VDENC_Surface_Control_Bits_CMD BufferPictureFields ; //!< Buffer Picture Fields 723 724 //! \name Local enumerations 725 726 //! \name Initializations 727 728 //! \brief Explicit member initialization function 729 VDENC_Row_Store_Scratch_Buffer_Picture_CMD(); 730 731 static const size_t dwSize = 3; 732 static const size_t byteSize = 12; 733 }; 734 735 //! 736 //! \brief VDENC_Statistics_Streamout 737 //! \details 738 //! 739 //! 740 struct VDENC_Statistics_Streamout_CMD 741 { 742 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 743 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 744 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 745 746 //! \name Local enumerations 747 748 //! \name Initializations 749 750 //! \brief Explicit member initialization function 751 VDENC_Statistics_Streamout_CMD(); 752 753 static const size_t dwSize = 3; 754 static const size_t byteSize = 12; 755 }; 756 757 //! 758 //! \brief VDENC_Streamin_Data_Picture 759 //! \details 760 //! 761 //! 762 struct VDENC_Streamin_Data_Picture_CMD 763 { 764 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 765 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 766 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 767 768 //! \name Local enumerations 769 770 //! \name Initializations 771 772 //! \brief Explicit member initialization function 773 VDENC_Streamin_Data_Picture_CMD(); 774 775 static const size_t dwSize = 3; 776 static const size_t byteSize = 12; 777 }; 778 779 //! 780 //! \brief VDENC_STREAMIN_STATE 781 //! \details 782 //! 783 //! 784 struct VDENC_STREAMIN_STATE_CMD 785 { 786 union 787 { 788 //!< DWORD 0 789 struct 790 { 791 uint32_t RegionOfInterestRoiSelection : __CODEGEN_BITFIELD( 0, 7) ; //!< Region of Interest (ROI) Selection 792 uint32_t Forceintra : __CODEGEN_BITFIELD( 8, 8) ; //!< FORCEINTRA 793 uint32_t Forceskip : __CODEGEN_BITFIELD( 9, 9) ; //!< FORCESKIP 794 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 795 }; 796 uint32_t Value; 797 } DW0; 798 union 799 { 800 //!< DWORD 1 801 struct 802 { 803 uint32_t Qpprimey : __CODEGEN_BITFIELD( 0, 7) ; //!< QPPRIMEY 804 uint32_t Targetsizeinword : __CODEGEN_BITFIELD( 8, 15) ; //!< TargetSizeInWord 805 uint32_t Maxsizeinword : __CODEGEN_BITFIELD(16, 23) ; //!< MaxSizeInWord 806 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 807 }; 808 uint32_t Value; 809 } DW1; 810 union 811 { 812 //!< DWORD 2 813 struct 814 { 815 uint32_t FwdPredictorX : __CODEGEN_BITFIELD( 0, 15) ; //!< Fwd Predictor.X 816 uint32_t FwdPredictorY : __CODEGEN_BITFIELD(16, 31) ; //!< Fwd Predictor.Y 817 }; 818 uint32_t Value; 819 } DW2; 820 union 821 { 822 //!< DWORD 3 823 struct 824 { 825 uint32_t BwdPredictorX : __CODEGEN_BITFIELD( 0, 15) ; //!< Bwd Predictor.X 826 uint32_t BwdPredictorY : __CODEGEN_BITFIELD(16, 31) ; //!< Bwd Predictor.Y 827 }; 828 uint32_t Value; 829 } DW3; 830 union 831 { 832 //!< DWORD 4 833 struct 834 { 835 uint32_t FwdRefid0 : __CODEGEN_BITFIELD( 0, 3) ; //!< Fwd RefID0 836 uint32_t BwdRefid0 : __CODEGEN_BITFIELD( 4, 7) ; //!< Bwd RefID0 837 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 838 }; 839 uint32_t Value; 840 } DW4; 841 842 uint32_t Reserved160[11]; //!< Reserved 843 844 845 //! \name Local enumerations 846 847 //! \brief FORCEINTRA 848 //! \details 849 //! This field specifies whether current macroblock should be coded as an 850 //! intra macroblock. 851 //! It is illegal to enable both ForceSkip and ForceIntra for 852 //! the same macroblock. 853 //! This should be disabled if Rolling-I is enabled in the 854 //! VDEnc Image State. 855 enum FORCEINTRA 856 { 857 FORCEINTRA_DISABLE = 0, //!< VDEnc determined macroblock type 858 FORCEINTRA_ENABLE = 1, //!< Force to be coded as an intra macroblock 859 }; 860 861 //! \brief FORCESKIP 862 //! \details 863 //! This field specifies whether current macroblock should be coded as a 864 //! skipped macroblock. 865 //! It is illegal to enable both ForceSkip and ForceIntra for 866 //! the same macroblock. 867 //! This should be disabled if Rolling-I is enabled in the 868 //! VDEnc Image State. 869 //! It is illegal to enable ForceSkip for I-Frames. 870 enum FORCESKIP 871 { 872 FORCESKIP_DISABLE = 0, //!< VDEnc determined macroblock type 873 FORCESKIP_ENABLE = 1, //!< Force to be coded as a skipped macroblock 874 }; 875 876 //! \brief QPPRIMEY 877 //! \details 878 //! Quantization parameter for Y. 879 enum QPPRIMEY 880 { 881 QPPRIMEY_UNNAMED0 = 0, //!< No additional details 882 QPPRIMEY_UNNAMED51 = 51, //!< No additional details 883 }; 884 885 //! \name Initializations 886 887 //! \brief Explicit member initialization function 888 VDENC_STREAMIN_STATE_CMD(); 889 890 static const size_t dwSize = 16; 891 static const size_t byteSize = 64; 892 }; 893 894 //! 895 //! \brief VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT 896 //! \details 897 //! 898 //! 899 struct VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD 900 { 901 union 902 { 903 //!< DWORD 0 904 struct 905 { 906 uint32_t SumSadHaarForBestModeDecision ; //!< Sum sad\haar for best mode decision 907 }; 908 uint32_t Value; 909 } DW0; 910 union 911 { 912 //!< DWORD 1 913 struct 914 { 915 uint32_t IntraCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Intra CU count normalized 916 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 917 }; 918 uint32_t Value; 919 } DW1; 920 union 921 { 922 //!< DWORD 2 923 struct 924 { 925 uint32_t NonSkipInterCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Non-skip Inter CU count normalized 926 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 927 }; 928 uint32_t Value; 929 } DW2; 930 union 931 { 932 //!< DWORD 3 933 struct 934 { 935 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 0 936 uint32_t Reserved116 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 937 }; 938 uint32_t Value; 939 } DW3; 940 union 941 { 942 //!< DWORD 4 943 struct 944 { 945 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 1 946 uint32_t Reserved148 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 947 }; 948 uint32_t Value; 949 } DW4; 950 union 951 { 952 //!< DWORD 5 953 struct 954 { 955 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 2 956 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 957 }; 958 uint32_t Value; 959 } DW5; 960 union 961 { 962 //!< DWORD 6 963 struct 964 { 965 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 3 966 uint32_t Reserved212 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 967 }; 968 uint32_t Value; 969 } DW6; 970 union 971 { 972 //!< DWORD 7 973 struct 974 { 975 uint32_t MvXGlobalMeSample025X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 0 (.25x,.25x) 976 uint32_t MvYGlobalMeSample025X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 0 (.25x,.25x) 977 }; 978 uint32_t Value; 979 } DW7; 980 union 981 { 982 //!< DWORD 8 983 struct 984 { 985 uint32_t MvXGlobalMeSample125X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 1 (.25x,.25x) 986 uint32_t MvYGlobalMeSample125X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 1 (.25x,.25x) 987 }; 988 uint32_t Value; 989 } DW8; 990 union 991 { 992 //!< DWORD 9 993 struct 994 { 995 uint32_t MvXGlobalMeSample225X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 2 (.25x,.25x) 996 uint32_t MvYGlobalMeSample225X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 2 (.25x,.25x) 997 }; 998 uint32_t Value; 999 } DW9; 1000 union 1001 { 1002 //!< DWORD 10 1003 struct 1004 { 1005 uint32_t MvXGlobalMeSample325X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 3 (.25x,.25x) 1006 uint32_t MvYGlobalMeSample325X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 3 (.25x,.25x) 1007 }; 1008 uint32_t Value; 1009 } DW10; 1010 union 1011 { 1012 //!< DWORD 11 1013 struct 1014 { 1015 uint32_t MvXGlobalMeSample425X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 4 (.25x,.25x) 1016 uint32_t MvYGlobalMeSample425X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 4 (.25x,.25x) 1017 }; 1018 uint32_t Value; 1019 } DW11; 1020 union 1021 { 1022 //!< DWORD 12 1023 struct 1024 { 1025 uint32_t MvXGlobalMeSample525X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 5 (.25x,.25x) 1026 uint32_t MvYGlobalMeSample525X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 5 (.25x,.25x) 1027 }; 1028 uint32_t Value; 1029 } DW12; 1030 union 1031 { 1032 //!< DWORD 13 1033 struct 1034 { 1035 uint32_t MvXGlobalMeSample625X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 6 (.25x,.25x) 1036 uint32_t MvYGlobalMeSample625X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 6 (.25x,.25x) 1037 }; 1038 uint32_t Value; 1039 } DW13; 1040 union 1041 { 1042 //!< DWORD 14 1043 struct 1044 { 1045 uint32_t MvXGlobalMeSample725X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 7 (.25x,.25x) 1046 uint32_t MvYGlobalMeSample725X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 7 (.25x,.25x) 1047 }; 1048 uint32_t Value; 1049 } DW14; 1050 union 1051 { 1052 //!< DWORD 15 1053 struct 1054 { 1055 uint32_t MvXGlobalMeSample825X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 8 (.25x,.25x) 1056 uint32_t MvYGlobalMeSample825X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 8 (.25x,.25x) 1057 }; 1058 uint32_t Value; 1059 } DW15; 1060 union 1061 { 1062 //!< DWORD 16 1063 struct 1064 { 1065 uint32_t RefidForGlobalmeSample0 : __CODEGEN_BITFIELD( 0, 1) ; //!< RefID for GlobalME sample 0 1066 uint32_t RefidForGlobalmeSample18 : __CODEGEN_BITFIELD( 2, 17) ; //!< RefID for GlobalME sample 1-8 1067 uint32_t Reserved530 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 1068 }; 1069 uint32_t Value; 1070 } DW16; 1071 union 1072 { 1073 //!< DWORD 17 1074 struct 1075 { 1076 uint32_t PaletteCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Palette CU Count Normalized 1077 uint32_t Reserved564 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1078 }; 1079 uint32_t Value; 1080 } DW17; 1081 union 1082 { 1083 //!< DWORD 18 1084 struct 1085 { 1086 uint32_t IbcCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< IBC CU Count Normalized 1087 uint32_t Reserved596 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1088 }; 1089 uint32_t Value; 1090 } DW18; 1091 union 1092 { 1093 //!< DWORD 19 1094 struct 1095 { 1096 uint32_t NumberOfSecondaryColorsChannel1 : __CODEGEN_BITFIELD( 0, 15) ; //!< Number of secondary colors (Channel1) 1097 uint32_t NumberOfPrimaryColorsChannel0 : __CODEGEN_BITFIELD(16, 31) ; //!< Number of primary colors (Channel0) 1098 }; 1099 uint32_t Value; 1100 } DW19; 1101 union 1102 { 1103 //!< DWORD 20 1104 struct 1105 { 1106 uint32_t NumberOfSecondaryColorsChannel2 : __CODEGEN_BITFIELD( 0, 15) ; //!< Number of secondary colors (Channel2) 1107 uint32_t Reserved656 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1108 }; 1109 uint32_t Value; 1110 } DW20; 1111 union 1112 { 1113 //!< DWORD 21 1114 struct 1115 { 1116 uint32_t Reserved672 ; //!< Reserved 1117 }; 1118 uint32_t Value; 1119 } DW21; 1120 union 1121 { 1122 //!< DWORD 22 1123 struct 1124 { 1125 uint32_t PositionOfTimerExpiration : __CODEGEN_BITFIELD( 0, 15) ; //!< Position of Timer expiration 1126 uint32_t TimerExpireStatus : __CODEGEN_BITFIELD(16, 16) ; //!< Timer Expire status 1127 uint32_t Reserved721 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1128 }; 1129 uint32_t Value; 1130 } DW22; 1131 union 1132 { 1133 //!< DWORD 23 1134 struct 1135 { 1136 uint32_t LocationOfPanic : __CODEGEN_BITFIELD( 0, 15) ; //!< Location of panic 1137 uint32_t PanicDetected : __CODEGEN_BITFIELD(16, 16) ; //!< Panic detected 1138 uint32_t Reserved753 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1139 }; 1140 uint32_t Value; 1141 } DW23; 1142 1143 uint32_t Reserved768[5]; //!< Reserved 1144 1145 union 1146 { 1147 //!< DWORD 29 1148 struct 1149 { 1150 uint32_t SumSadHaarForBestModeDecisionBottomHalfPopulation ; //!< Sum sad\haar for best mode decision bottom half population 1151 }; 1152 uint32_t Value; 1153 } DW29; 1154 union 1155 { 1156 //!< DWORD 30 1157 struct 1158 { 1159 uint32_t SumSadHaarForBestModeDecisionTopHalfPopulation ; //!< Sum sad\haar for best mode decision top half population 1160 }; 1161 uint32_t Value; 1162 } DW30; 1163 union 1164 { 1165 //!< DWORD 31 1166 struct 1167 { 1168 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD( 0, 15) ; //!< Sum top half population occurrences 1169 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31) ; //!< Sum bottom half population occurrences 1170 }; 1171 uint32_t Value; 1172 } DW31; 1173 1174 //! \name Local enumerations 1175 1176 //! \name Initializations 1177 1178 //! \brief Explicit member initialization function 1179 VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD(); 1180 1181 static const size_t dwSize = 32; 1182 static const size_t byteSize = 128; 1183 }; 1184 1185 //! 1186 //! \brief VDENC_HEVC_VP9_STREAMIN_STATE 1187 //! \details 1188 //! For the NumMergeCandidate paramaters [64x64/32x32/16x16/8x8], only the 1189 //! following configurations are valid. 1190 //! Normal Mode without force mv or force intra: 4321 [64x64 --> 16x16]. 1191 //! Speed Mode without force mv or force intra: 2220, 2110, 1210, 2200, 1110 1192 //! [64x64 --> 16x16]. 1193 //! 1194 struct VDENC_HEVC_VP9_STREAMIN_STATE_CMD 1195 { 1196 union 1197 { 1198 //!< DWORD 0 1199 struct 1200 { 1201 uint32_t Roi32X32016X1603 : __CODEGEN_BITFIELD( 0, 7) ; //!< ROI 32x32_0 16x16_03 1202 uint32_t Maxtusize : __CODEGEN_BITFIELD( 8, 9) ; //!< MaxTUSize 1203 uint32_t Maxcusize : __CODEGEN_BITFIELD(10, 11) ; //!< MaxCUSize 1204 uint32_t Numimepredictors : __CODEGEN_BITFIELD(12, 15) ; //!< NUMIMEPREDICTORS 1205 uint32_t PuType32X32016X1603 : __CODEGEN_BITFIELD(24, 31) ; //!< PU Type 32x32_0 16x16_03 1206 }; 1207 uint32_t Value; 1208 } DW0; 1209 union 1210 { 1211 //!< DWORD 1 1212 struct 1213 { 1214 uint32_t ForceMvX32X32016X160 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_0 1215 uint32_t ForceMvY32X32016X160 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_0 1216 }; 1217 uint32_t Value; 1218 } DW1; 1219 union 1220 { 1221 //!< DWORD 2 1222 struct 1223 { 1224 uint32_t ForceMvX32X32016X161 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_1 1225 uint32_t ForceMvY32X32016X161 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_1 1226 }; 1227 uint32_t Value; 1228 } DW2; 1229 union 1230 { 1231 //!< DWORD 3 1232 struct 1233 { 1234 uint32_t ForceMvX32X32016X162 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_2 1235 uint32_t ForceMvY32X32016X162 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_2 1236 }; 1237 uint32_t Value; 1238 } DW3; 1239 union 1240 { 1241 //!< DWORD 4 1242 struct 1243 { 1244 uint32_t ForceMvX32X32016X163 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_3 1245 uint32_t ForceMvY32X32016X163 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_3 1246 }; 1247 uint32_t Value; 1248 } DW4; 1249 union 1250 { 1251 //!< DWORD 5 1252 struct 1253 { 1254 uint32_t Reserved160 ; //!< Reserved 1255 }; 1256 uint32_t Value; 1257 } DW5; 1258 union 1259 { 1260 //!< DWORD 6 1261 struct 1262 { 1263 uint32_t ForceMvRefidx32X32016X160 : __CODEGEN_BITFIELD( 0, 3) ; //!< force_mv refidx 32x32_0 16x16_0 1264 uint32_t ForceMvRefidx32X32016X1613 : __CODEGEN_BITFIELD( 4, 15) ; //!< force_mv refidx 32x32_0 16x16_1-3 1265 uint32_t Nummergecandidatecu8X8 : __CODEGEN_BITFIELD(16, 19) ; //!< NumMergeCandidateCU8x8 1266 uint32_t Nummergecandidatecu16X16 : __CODEGEN_BITFIELD(20, 23) ; //!< NumMergeCandidateCU16x16 1267 uint32_t Nummergecandidatecu32X32 : __CODEGEN_BITFIELD(24, 27) ; //!< NumMergeCandidateCU32x32 1268 uint32_t Nummergecandidatecu64X64 : __CODEGEN_BITFIELD(28, 31) ; //!< NumMergeCandidateCU64x64 1269 }; 1270 uint32_t Value; 1271 } DW6; 1272 union 1273 { 1274 //!< DWORD 7 1275 struct 1276 { 1277 uint32_t Segid32X32016X1603Vp9Only : __CODEGEN_BITFIELD( 0, 15) ; //!< SegID 32x32_0 16x16_03 (VP9 only) 1278 uint32_t QpEn32X32016X1603 : __CODEGEN_BITFIELD(16, 19) ; //!< QP_En 32x32_0 16x16_03 1279 uint32_t SegidEnable : __CODEGEN_BITFIELD(20, 20) ; //!< SegID Enable 1280 uint32_t Reserved245 : __CODEGEN_BITFIELD(21, 22) ; //!< Reserved 1281 uint32_t ForceRefidEnable32X320 : __CODEGEN_BITFIELD(23, 23) ; //!< Force Refid Enable (32x32_0) 1282 uint32_t ImePredictorRefidSelect0332X320 : __CODEGEN_BITFIELD(24, 31) ; //!< IME predictor/refid Select0-3 32x32_0 1283 }; 1284 uint32_t Value; 1285 } DW7; 1286 union 1287 { 1288 //!< DWORD 8 1289 struct 1290 { 1291 uint32_t ImePredictor0X32X320 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_0 1292 uint32_t ImePredictor0Y32X320 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_0 1293 }; 1294 uint32_t Value; 1295 } DW8; 1296 union 1297 { 1298 //!< DWORD 9 1299 struct 1300 { 1301 uint32_t ImePredictor0X32X321 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_1 1302 uint32_t ImePredictor0Y32X321 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_1 1303 }; 1304 uint32_t Value; 1305 } DW9; 1306 union 1307 { 1308 //!< DWORD 10 1309 struct 1310 { 1311 uint32_t ImePredictor0X32X322 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_2 1312 uint32_t ImePredictor0Y32X322 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_2 1313 }; 1314 uint32_t Value; 1315 } DW10; 1316 union 1317 { 1318 //!< DWORD 11 1319 struct 1320 { 1321 uint32_t ImePredictor0X32X323 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_3 1322 uint32_t ImePredictor0Y32X323 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_3 1323 }; 1324 uint32_t Value; 1325 } DW11; 1326 union 1327 { 1328 //!< DWORD 12 1329 struct 1330 { 1331 uint32_t ImePredictor0Refidx32X320 : __CODEGEN_BITFIELD( 0, 3) ; //!< ime_predictor0 refidx 32x32_0 1332 uint32_t ImePredictor13Refidx32X3213 : __CODEGEN_BITFIELD( 4, 15) ; //!< ime_predictor1-3 refidx 32x32_1-3 1333 uint32_t Reserved400 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1334 }; 1335 uint32_t Value; 1336 } DW12; 1337 union 1338 { 1339 //!< DWORD 13 1340 struct 1341 { 1342 uint32_t Panicmodelcuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< PanicModeLCUThreshold 1343 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1344 }; 1345 uint32_t Value; 1346 } DW13; 1347 union 1348 { 1349 //!< DWORD 14 1350 struct 1351 { 1352 uint32_t ForceQpValue16X160 : __CODEGEN_BITFIELD( 0, 7) ; //!< Force QP Value 16x16_0 1353 uint32_t ForceQpValue16X161 : __CODEGEN_BITFIELD( 8, 15) ; //!< Force QP Value 16x16_1 1354 uint32_t ForceQpValue16X162 : __CODEGEN_BITFIELD(16, 23) ; //!< Force QP Value 16x16_2 1355 uint32_t ForceQpValue16X163 : __CODEGEN_BITFIELD(24, 31) ; //!< Force QP Value 16x16_3 1356 }; 1357 uint32_t Value; 1358 } DW14; 1359 union 1360 { 1361 //!< DWORD 15 1362 struct 1363 { 1364 uint32_t Reserved480 ; //!< Reserved 1365 }; 1366 uint32_t Value; 1367 } DW15; 1368 1369 //! \name Local enumerations 1370 1371 //! \brief NUMIMEPREDICTORS 1372 //! \details 1373 //! <p>This parameter specifes the number of IME predictors to be processed 1374 //! in stage3 IME.</p> 1375 //! <p></p> 1376 enum NUMIMEPREDICTORS 1377 { 1378 NUMIMEPREDICTORS_UNNAMED0 = 0, //!< No additional details 1379 NUMIMEPREDICTORS_UNNAMED4 = 4, //!< No additional details 1380 NUMIMEPREDICTORS_UNNAMED8 = 8, //!< No additional details 1381 NUMIMEPREDICTORS_UNNAMED12 = 12, //!< No additional details 1382 }; 1383 1384 //! \name Initializations 1385 1386 //! \brief Explicit member initialization function 1387 VDENC_HEVC_VP9_STREAMIN_STATE_CMD(); 1388 1389 static const size_t dwSize = 16; 1390 static const size_t byteSize = 64; 1391 }; 1392 1393 //! 1394 //! \brief VDENC_Surface_State_Fields 1395 //! \details 1396 //! 1397 //! 1398 struct VDENC_Surface_State_Fields_CMD 1399 { 1400 union 1401 { 1402 //!< DWORD 0 1403 struct 1404 { 1405 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< Cr(V)/Cb(U) Pixel Offset V Direction 1406 uint32_t SurfaceFormatByteSwizzle : __CODEGEN_BITFIELD( 2, 2) ; //!< Surface Format Byte Swizzle 1407 uint32_t ColorSpaceSelection : __CODEGEN_BITFIELD( 3, 3) ; //!< Color space selection 1408 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 1409 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 1410 }; 1411 uint32_t Value; 1412 } DW0; 1413 union 1414 { 1415 //!< DWORD 1 1416 struct 1417 { 1418 uint32_t TileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< TILE_WALK 1419 uint32_t TiledSurface : __CODEGEN_BITFIELD( 1, 1) ; //!< TILED_SURFACE 1420 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< HALF_PITCH_FOR_CHROMA 1421 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Surface Pitch 1422 uint32_t ChromaDownsampleFilterControl : __CODEGEN_BITFIELD(20, 22) ; //!< Chroma Downsample Filter Control 1423 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 26) ; //!< Reserved 1424 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 1425 }; 1426 uint32_t Value; 1427 } DW1; 1428 union 1429 { 1430 //!< DWORD 2 1431 struct 1432 { 1433 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) 1434 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1435 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30) ; //!< X Offset for U(Cb) 1436 uint32_t Reserved95 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1437 }; 1438 uint32_t Value; 1439 } DW2; 1440 union 1441 { 1442 //!< DWORD 3 1443 struct 1444 { 1445 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 15) ; //!< Y Offset for V(Cr) 1446 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for V(Cr) 1447 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1448 }; 1449 uint32_t Value; 1450 } DW3; 1451 1452 //! \name Local enumerations 1453 1454 //! \brief TILE_WALK 1455 //! \details 1456 //! (This field must be set to 1: TILEWALK_YMAJOR.) This field specifies the 1457 //! type of memory tiling (XMajor or YMajor) employed to tile this surface. 1458 //! See Memory Interface Functions for details on memory tiling and restrictions. 1459 //! This field is ignored when the surface is linear. Internally H/W always 1460 //! treats this as set to 1 for all VDEnc usage. 1461 enum TILE_WALK 1462 { 1463 TILE_WALK_XMAJOR = 0, //!< TILEWALK_XMAJOR 1464 TILE_WALK_YMAJOR = 1, //!< TILEWALK_YMAJOR 1465 }; 1466 1467 //! \brief TILED_SURFACE 1468 //! \details 1469 //! (This field must be set to TRUE: Tiled.) This field specifies whether 1470 //! the surface is tiled. This field is ignored by VDEnc usage. 1471 enum TILED_SURFACE 1472 { 1473 TILED_SURFACE_FALSE = 0, //!< Linear 1474 TILED_SURFACE_TRUE = 1, //!< Tiled 1475 }; 1476 1477 //! \brief HALF_PITCH_FOR_CHROMA 1478 //! \details 1479 //! (This field must be set to Disable.) This field indicates that the 1480 //! chroma plane(s) will use a pitch equal to half the value specified 1481 //! in the Surface Pitch field. This field is only used for PLANAR 1482 //! surface formats. This field is igored by VDEnc (unless we support YV12). 1483 enum HALF_PITCH_FOR_CHROMA 1484 { 1485 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< No additional details 1486 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< No additional details 1487 }; 1488 1489 //! \brief SURFACE_FORMAT 1490 //! \details 1491 //! Specifies the format of the surface. 1492 enum SURFACE_FORMAT 1493 { 1494 SURFACE_FORMAT_YUV422 = 0, //!< YUYV/YUY2 (8:8:8:8 MSB V0 Y1 U0 Y0) 1495 SURFACE_FORMAT_RGBA4444 = 1, //!< RGBA 32-bit 4:4:4:4 packed (8:8:8:8 MSB-X:B:G:R) 1496 SURFACE_FORMAT_YUV444 = 2, //!< YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-A:Y:U:V) 1497 SURFACE_FORMAT_Y8UNORM = 3, //!< No additional details 1498 SURFACE_FORMAT_PLANAR_420_8 = 4, //!< (NV12, IMC1,2,3,4, YV12) 1499 SURFACE_FORMAT_YCRCB_SWAPY_422 = 5, //!< UYVY (8:8:8:8 MSB Y1 V0 Y0 U0) 1500 SURFACE_FORMAT_YCRCB_SWAPUV_422 = 6, //!< YVYU (8:8:8:8 MSB U0 Y1 V0 Y0) 1501 SURFACE_FORMAT_YCRCB_SWAPUVY_422 = 7, //!< VYUY (8:8:8:8 MSB Y1 U0 Y0 V0) 1502 SURFACE_FORMAT_P010 = 8, //!< 10 - bit planar 420 (Tile - Y / Linear / Tile - X) 1503 SURFACE_FORMAT_RGBA_10_10_10_2 = 9, //!< Need to convert to YUV. 2 bits Alpha, 10 bits R 10 bits G 10 bits B 1504 SURFACE_FORMAT_Y410 = 10, //!< 10 bit 4:4:4 packed 1505 SURFACE_FORMAT_NV21 = 11, //!< 8-bit, same as NV12 but UV interleave is reversed 1506 SURFACE_FORMAT_P010_VARIANT = 12, //!< >8 bit planar 420 with MSB together and LSB at an offset in x direction 1507 }; 1508 1509 //! \name Initializations 1510 1511 //! \brief Explicit member initialization function 1512 VDENC_Surface_State_Fields_CMD(); 1513 1514 static const size_t dwSize = 4; 1515 static const size_t byteSize = 16; 1516 }; 1517 1518 //! 1519 //! \brief VD_PIPELINE_FLUSH 1520 //! \details 1521 //! 1522 //! 1523 struct VD_PIPELINE_FLUSH_CMD 1524 { 1525 union 1526 { 1527 //!< DWORD 0 1528 struct 1529 { 1530 uint32_t DwordCountN : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_COUNT_N 1531 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1532 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1533 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1534 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1535 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1536 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1537 }; 1538 uint32_t Value; 1539 } DW0; 1540 union 1541 { 1542 //!< DWORD 1 1543 struct 1544 { 1545 uint32_t HevcPipelineDone : __CODEGEN_BITFIELD( 0, 0) ; //!< HEVC pipeline Done 1546 uint32_t VdencPipelineDone : __CODEGEN_BITFIELD( 1, 1) ; //!< VD-ENC pipeline Done 1547 uint32_t MflPipelineDone : __CODEGEN_BITFIELD( 2, 2) ; //!< MFL pipeline Done 1548 uint32_t MfxPipelineDone : __CODEGEN_BITFIELD( 3, 3) ; //!< MFX pipeline Done 1549 uint32_t VdCommandMessageParserDone : __CODEGEN_BITFIELD( 4, 4) ; //!< VD command/message parser Done 1550 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 1551 uint32_t HevcPipelineCommandFlush : __CODEGEN_BITFIELD(16, 16) ; //!< HEVC pipeline command flush 1552 uint32_t VdencPipelineCommandFlush : __CODEGEN_BITFIELD(17, 17) ; //!< VD-ENC pipeline command flush 1553 uint32_t MflPipelineCommandFlush : __CODEGEN_BITFIELD(18, 18) ; //!< MFL pipeline command flush 1554 uint32_t MfxPipelineCommandFlush : __CODEGEN_BITFIELD(19, 19) ; //!< MFX pipeline command flush 1555 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1556 }; 1557 uint32_t Value; 1558 } DW1; 1559 1560 //! \name Local enumerations 1561 1562 //! \brief DWORD_COUNT_N 1563 //! \details 1564 //! Total Length - 2 1565 enum DWORD_COUNT_N 1566 { 1567 DWORD_COUNT_N_EXCLUDESDWORD_0 = 0, //!< No additional details 1568 }; 1569 1570 enum SUBOPCODEB 1571 { 1572 SUBOPCODEB_UNNAMED0 = 0, //!< No additional details 1573 }; 1574 1575 enum SUBOPCODEA 1576 { 1577 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 1578 }; 1579 1580 enum MEDIA_COMMAND_OPCODE 1581 { 1582 MEDIA_COMMAND_OPCODE_EXTENDEDCOMMAND = 15, //!< No additional details 1583 }; 1584 1585 enum PIPELINE 1586 { 1587 PIPELINE_MEDIA = 2, //!< No additional details 1588 }; 1589 1590 enum COMMAND_TYPE 1591 { 1592 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1593 }; 1594 1595 //! \name Initializations 1596 1597 //! \brief Explicit member initialization function 1598 VD_PIPELINE_FLUSH_CMD(); 1599 1600 static const size_t dwSize = 2; 1601 static const size_t byteSize = 8; 1602 }; 1603 1604 //! 1605 //! \brief VDENC_WEIGHTSOFFSETS_STATE 1606 //! \details 1607 //! 1608 //! 1609 struct VDENC_WEIGHTSOFFSETS_STATE_CMD 1610 { 1611 union 1612 { 1613 //!< DWORD 0 1614 struct 1615 { 1616 uint32_t DwLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DW_LENGTH 1617 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1618 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1619 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1620 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1621 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1622 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1623 }; 1624 uint32_t Value; 1625 } DW0; 1626 union 1627 { 1628 //!< DWORD 1 1629 struct 1630 { 1631 uint32_t WeightsForwardReference0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Weights Forward Reference0 1632 uint32_t OffsetForwardReference0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Offset Forward Reference0 1633 uint32_t WeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23) ; //!< Weights Forward Reference1 1634 uint32_t OffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31) ; //!< Offset Forward Reference1 1635 }; 1636 uint32_t Value; 1637 } DW1; 1638 union 1639 { 1640 //!< DWORD 2 1641 struct 1642 { 1643 uint32_t WeightsForwardReference2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Weights Forward Reference2 1644 uint32_t OffsetForwardReference2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Offset Forward Reference2 1645 uint32_t HevcVp9WeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23) ; //!< HEVC/VP9 Weights Backward Reference0 1646 uint32_t HevcVp9OffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31) ; //!< HEVC/VP9 Offset Backward Reference0 1647 }; 1648 uint32_t Value; 1649 } DW2; 1650 1651 //! \name Local enumerations 1652 1653 //! \brief DW_LENGTH 1654 //! \details 1655 //! Total Length - 2 1656 enum DW_LENGTH 1657 { 1658 DW_LENGTH_DWORDCOUNTN = 1, //!< Excludes DWord (0,1) 1659 }; 1660 1661 enum SUBOPB 1662 { 1663 SUBOPB_VDENCAVCWEIGHTSOFFSETSTATE = 8, //!< No additional details 1664 }; 1665 1666 enum SUBOPA 1667 { 1668 SUBOPA_UNNAMED0 = 0, //!< No additional details 1669 }; 1670 1671 enum OPCODE 1672 { 1673 OPCODE_VDENCPIPE = 1, //!< No additional details 1674 }; 1675 1676 enum PIPELINE 1677 { 1678 PIPELINE_MFXCOMMON = 2, //!< No additional details 1679 }; 1680 1681 enum COMMAND_TYPE 1682 { 1683 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1684 }; 1685 1686 //! \name Initializations 1687 1688 //! \brief Explicit member initialization function 1689 VDENC_WEIGHTSOFFSETS_STATE_CMD(); 1690 1691 static const size_t dwSize = 3; 1692 static const size_t byteSize = 12; 1693 }; 1694 1695 //! 1696 //! \brief VDENC_CONST_QPT_STATE 1697 //! \details 1698 //! This commands provides the tables for frame constants to the VDEnc HW. 1699 //! The specific parameter value is picked by the VDEnc HW based on the 1700 //! frame level QP. The QP Lambda array for costing (motion-vectors and mode 1701 //! costs) has 42 entires. Skip Threshold tables has 27 entries. 7 FTQ 1702 //! thresholds [0-6] are programmed using 4 sets of tables with 27 entires 1703 //! each. 1704 //! 1705 struct VDENC_CONST_QPT_STATE_CMD 1706 { 1707 union 1708 { 1709 //!< DWORD 0 1710 struct 1711 { 1712 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1713 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1714 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1715 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1716 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1717 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1718 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1719 }; 1720 uint32_t Value; 1721 } DW0; 1722 union { 1723 //!< DWORD 1..10 1724 struct { 1725 uint8_t QpLambdaArrayIndex[40]; //!< QP Lambda Array Index[n] 1726 }; 1727 uint32_t Value[10]; 1728 } DW1_10; 1729 union { 1730 //!< DWORD 11 1731 struct { 1732 uint32_t QpLambdaArrayIndex40 : __CODEGEN_BITFIELD(0, 7); 1733 uint32_t QpLambdaArrayIndex41 : __CODEGEN_BITFIELD(8, 15); 1734 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1735 }; 1736 uint32_t Value; 1737 } DW11; 1738 union { 1739 //!< DWORD 12..24 1740 struct { 1741 uint16_t SkipThresholdArrayIndex[26]; //!< Skip Threshold Array Index[n] 1742 }; 1743 uint32_t Value[13]; 1744 } DW12_24; 1745 union { 1746 //!< DWORD 25 1747 struct { 1748 uint32_t SkipThresholdArrayIndex26 : __CODEGEN_BITFIELD(0, 15); 1749 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1750 }; 1751 uint32_t Value; 1752 } DW25; 1753 union { 1754 //!< DWORD 26..38 1755 struct { 1756 uint16_t SicForwardTransformCoeffThresholdMatrix0ArrayIndex[26]; //!< SIC Forward Transform Coeff Threshold Matrix0 Array Index[n] 1757 }; 1758 uint32_t Value[13]; 1759 } DW26_38; 1760 union { 1761 //!< DWORD 39 1762 struct { 1763 uint32_t SicForwardTransformCoeffThresholdMatrix0ArrayIndex26 : __CODEGEN_BITFIELD(0, 15); 1764 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1765 }; 1766 uint32_t Value; 1767 } DW39; 1768 union { 1769 //!< DWORD 40..45 1770 struct { 1771 uint8_t SicForwardTransformCoeffThresholdMatrix135ArrayIndexN[24]; //!< SIC Forward Transform Coeff Threshold Matrix1/3/5 Array Index[n] 1772 }; 1773 uint32_t Value[6]; 1774 } DW40_45; 1775 union { 1776 //!< DWORD 46 1777 struct { 1778 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1779 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1780 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1781 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1782 }; 1783 uint32_t Value; 1784 } DW46; 1785 union { 1786 //!< DWORD 47..52 1787 struct { 1788 uint8_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex[24]; //!< SIC Forward Transform Coeff Threshold Matrix2 Array Index[n] 1789 }; 1790 uint32_t Value[6]; 1791 } DW47_52; 1792 union { 1793 //!< DWORD 53 1794 struct { 1795 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1796 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1797 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1798 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1799 }; 1800 uint32_t Value; 1801 } DW53; 1802 union { 1803 //!< DWORD 54..59 1804 struct { 1805 uint8_t SicForwardTransformCoeffThresholdMatrix46ArrayIndexN[24]; //!< SIC Forward Transform Coeff Threshold Matrix4/6 Array Index[n] 1806 }; 1807 uint32_t Value[6]; 1808 } DW54_59; 1809 union { 1810 //!< DWORD 60 1811 struct { 1812 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1813 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1814 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1815 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1816 }; 1817 uint32_t Value; 1818 } DW60; 1819 1820 //! \name Local enumerations 1821 1822 enum SUBOPB 1823 { 1824 SUBOPB_VDENCCONSTQPTSTATE = 6, //!< No additional details 1825 }; 1826 1827 enum SUBOPA 1828 { 1829 SUBOPA_UNNAMED0 = 0, //!< No additional details 1830 }; 1831 1832 enum OPCODE 1833 { 1834 OPCODE_VDENCPIPE = 1, //!< No additional details 1835 }; 1836 1837 enum PIPELINE 1838 { 1839 PIPELINE_MFXCOMMON = 2, //!< No additional details 1840 }; 1841 1842 enum COMMAND_TYPE 1843 { 1844 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1845 }; 1846 1847 //! \name Initializations 1848 1849 //! \brief Explicit member initialization function 1850 VDENC_CONST_QPT_STATE_CMD(); 1851 1852 static const size_t dwSize = 61; 1853 static const size_t byteSize = 244; 1854 }; 1855 1856 //! 1857 //! \brief VDENC_DS_REF_SURFACE_STATE 1858 //! \details 1859 //! This command specifies the surface state parameters for the downscaled 1860 //! reference surfaces. 1861 //! 1862 struct VDENC_DS_REF_SURFACE_STATE_CMD 1863 { 1864 union 1865 { 1866 //!< DWORD 0 1867 struct 1868 { 1869 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1870 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1871 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1872 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1873 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1874 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1875 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1876 }; 1877 uint32_t Value; 1878 } DW0; 1879 union 1880 { 1881 //!< DWORD 1 1882 struct 1883 { 1884 uint32_t Reserved32 ; //!< Reserved 1885 }; 1886 uint32_t Value; 1887 } DW1; 1888 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 1889 VDENC_Surface_State_Fields_CMD Dwords69 ; //!< Dwords 6..9 1890 1891 //! \name Local enumerations 1892 1893 enum SUBOPB 1894 { 1895 SUBOPB_VDENCDSREFSURFACESTATE = 3, //!< No additional details 1896 }; 1897 1898 enum SUBOPA 1899 { 1900 SUBOPA_UNNAMED0 = 0, //!< No additional details 1901 }; 1902 1903 enum OPCODE 1904 { 1905 OPCODE_VDENCPIPE = 1, //!< No additional details 1906 }; 1907 1908 enum PIPELINE 1909 { 1910 PIPELINE_MFXCOMMON = 2, //!< No additional details 1911 }; 1912 1913 enum COMMAND_TYPE 1914 { 1915 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1916 }; 1917 1918 //! \name Initializations 1919 1920 //! \brief Explicit member initialization function 1921 VDENC_DS_REF_SURFACE_STATE_CMD(); 1922 1923 static const size_t dwSize = 10; 1924 static const size_t byteSize = 40; 1925 }; 1926 1927 //! 1928 //! \brief VDENC_IMG_STATE 1929 //! \details 1930 //! This command programs the frame level parameters required by the VDEnc 1931 //! pipeline. 1932 //! 1933 struct VDENC_IMG_STATE_CMD 1934 { 1935 union 1936 { 1937 //!< DWORD 0 1938 struct 1939 { 1940 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1941 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1942 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1943 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1944 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1945 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1946 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1947 }; 1948 uint32_t Value; 1949 } DW0; 1950 union 1951 { 1952 //!< DWORD 1 1953 struct 1954 { 1955 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1956 uint32_t BidirectionalMixDisable : __CODEGEN_BITFIELD( 2, 2) ; //!< BIDIRECTIONAL_MIX_DISABLE 1957 uint32_t VdencPerfmode : __CODEGEN_BITFIELD( 3, 3) ; //!< VDENC_PERFMODE 1958 uint32_t TimeBudgetOverflowCheck : __CODEGEN_BITFIELD( 4, 4) ; //!< TIME_BUDGET_OVERFLOW_CHECK 1959 uint32_t VdencUltraMode : __CODEGEN_BITFIELD( 5, 5) ; //!< VDEnc_UltraMode 1960 uint32_t VdencExtendedPakObjCmdEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 1961 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD( 7, 7) ; //!< TRANSFORM_8X8_FLAG 1962 uint32_t VdencL1CachePriority : __CODEGEN_BITFIELD( 8, 9) ; //!< VDENC_L1_CACHE_PRIORITY 1963 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1964 uint32_t LambdaValueForTrellis : __CODEGEN_BITFIELD(16, 31) ; //!< Lambda value for Trellis 1965 }; 1966 uint32_t Value; 1967 } DW1; 1968 union 1969 { 1970 //!< DWORD 2 1971 struct 1972 { 1973 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1974 uint32_t BidirectionalWeight : __CODEGEN_BITFIELD(16, 21) ; //!< BIDIRECTIONAL_WEIGHT 1975 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 27) ; //!< Reserved 1976 uint32_t UnidirectionalMixDisable : __CODEGEN_BITFIELD(28, 28) ; //!< Unidirectional Mix Disable 1977 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1978 }; 1979 uint32_t Value; 1980 } DW2; 1981 union 1982 { 1983 //!< DWORD 3 1984 struct 1985 { 1986 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1987 uint32_t PictureWidth : __CODEGEN_BITFIELD(16, 31) ; //!< Picture Width 1988 }; 1989 uint32_t Value; 1990 } DW3; 1991 union 1992 { 1993 //!< DWORD 4 1994 struct 1995 { 1996 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1997 uint32_t SubPelMode : __CODEGEN_BITFIELD(12, 13) ; //!< SUB_PEL_MODE 1998 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 16) ; //!< Reserved 1999 uint32_t ForwardTransformSkipCheckEnable : __CODEGEN_BITFIELD(17, 17) ; //!< FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2000 uint32_t BmeDisableForFbrMessage : __CODEGEN_BITFIELD(18, 18) ; //!< BME_DISABLE_FOR_FBR_MESSAGE 2001 uint32_t BlockBasedSkipEnabled : __CODEGEN_BITFIELD(19, 19) ; //!< BLOCK_BASED_SKIP_ENABLED 2002 uint32_t InterSadMeasureAdjustment : __CODEGEN_BITFIELD(20, 21) ; //!< INTER_SAD_MEASURE_ADJUSTMENT 2003 uint32_t IntraSadMeasureAdjustment : __CODEGEN_BITFIELD(22, 23) ; //!< INTRA_SAD_MEASURE_ADJUSTMENT 2004 uint32_t SubMacroblockSubPartitionMask : __CODEGEN_BITFIELD(24, 30) ; //!< SUB_MACROBLOCK_SUB_PARTITION_MASK 2005 uint32_t BlockBasedSkipType : __CODEGEN_BITFIELD(31, 31) ; //!< BLOCK_BASED_SKIP_TYPE 2006 }; 2007 uint32_t Value; 2008 } DW4; 2009 union 2010 { 2011 //!< DWORD 5 2012 struct 2013 { 2014 uint32_t PictureHeightMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< Picture Height Minus One 2015 uint32_t CrePrefetchEnable : __CODEGEN_BITFIELD(16, 16) ; //!< CRE_PREFETCH_ENABLE 2016 uint32_t HmeRef1Disable : __CODEGEN_BITFIELD(17, 17) ; //!< HME_REF1_DISABLE 2017 uint32_t MbSliceThresholdValue : __CODEGEN_BITFIELD(18, 21) ; //!< MB Slice Threshold Value 2018 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 25) ; //!< Reserved 2019 uint32_t ConstrainedIntraPredictionFlag : __CODEGEN_BITFIELD(26, 26) ; //!< CONSTRAINED_INTRA_PREDICTION_FLAG 2020 uint32_t Reserved187 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 2021 uint32_t PictureType : __CODEGEN_BITFIELD(29, 30) ; //!< PICTURE_TYPE 2022 uint32_t Reserved191 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2023 }; 2024 uint32_t Value; 2025 } DW5; 2026 union 2027 { 2028 //!< DWORD 6 2029 struct 2030 { 2031 uint32_t SliceMacroblockHeightMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< Slice Macroblock Height Minus One 2032 uint32_t Reserved208 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2033 }; 2034 uint32_t Value; 2035 } DW6; 2036 union 2037 { 2038 //!< DWORD 7 2039 struct 2040 { 2041 uint32_t Hme0XOffset : __CODEGEN_BITFIELD( 0, 7) ; //!< HME0 X Offset 2042 uint32_t Hme0YOffset : __CODEGEN_BITFIELD( 8, 15) ; //!< HME0 Y Offset 2043 uint32_t Hme1XOffset : __CODEGEN_BITFIELD(16, 23) ; //!< HME1 X Offset 2044 uint32_t Hme1YOffset : __CODEGEN_BITFIELD(24, 31) ; //!< HME1 Y Offset 2045 }; 2046 uint32_t Value; 2047 } DW7; 2048 union 2049 { 2050 //!< DWORD 8 2051 struct 2052 { 2053 uint32_t LumaIntraPartitionMask : __CODEGEN_BITFIELD( 0, 4) ; //!< LUMA_INTRA_PARTITION_MASK 2054 uint32_t NonSkipZeroMvCostAdded : __CODEGEN_BITFIELD( 5, 5) ; //!< Non Skip Zero MV Cost Added 2055 uint32_t NonSkipMbModeCostAdded : __CODEGEN_BITFIELD( 6, 6) ; //!< Non Skip MB Mode Cost Added 2056 uint32_t Reserved263 : __CODEGEN_BITFIELD( 7, 15) ; //!< Reserved 2057 uint32_t MvCostScalingFactor : __CODEGEN_BITFIELD(16, 17) ; //!< MV_COST_SCALING_FACTOR 2058 uint32_t BilinearFilterEnable : __CODEGEN_BITFIELD(18, 18) ; //!< BiLinear Filter Enable 2059 uint32_t Reserved275 : __CODEGEN_BITFIELD(19, 21) ; //!< Reserved 2060 uint32_t RefidCostModeSelect : __CODEGEN_BITFIELD(22, 22) ; //!< REFID_COST_MODE_SELECT 2061 uint32_t Reserved279 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 2062 }; 2063 uint32_t Value; 2064 } DW8; 2065 union 2066 { 2067 //!< DWORD 9 2068 struct 2069 { 2070 uint32_t Mode0Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 0 Cost 2071 uint32_t Mode1Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 1 Cost 2072 uint32_t Mode2Cost : __CODEGEN_BITFIELD(16, 23) ; //!< Mode 2 Cost 2073 uint32_t Mode3Cost : __CODEGEN_BITFIELD(24, 31) ; //!< Mode 3 Cost 2074 }; 2075 uint32_t Value; 2076 } DW9; 2077 union 2078 { 2079 //!< DWORD 10 2080 struct 2081 { 2082 uint32_t Mode4Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 4 Cost 2083 uint32_t Mode5Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 5 Cost 2084 uint32_t Mode6Cost : __CODEGEN_BITFIELD(16, 23) ; //!< Mode 6 Cost 2085 uint32_t Mode7Cost : __CODEGEN_BITFIELD(24, 31) ; //!< Mode 7 Cost 2086 }; 2087 uint32_t Value; 2088 } DW10; 2089 union 2090 { 2091 //!< DWORD 11 2092 struct 2093 { 2094 uint32_t Mode8Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 8 Cost 2095 uint32_t Mode9Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 9 Cost 2096 uint32_t RefIdCost : __CODEGEN_BITFIELD(16, 23) ; //!< RefID Cost 2097 uint32_t ChromaIntraModeCost : __CODEGEN_BITFIELD(24, 31) ; //!< Chroma Intra Mode Cost 2098 }; 2099 uint32_t Value; 2100 } DW11; 2101 union 2102 { 2103 //!< DWORD 12 2104 struct 2105 { 2106 uint32_t MvCost0 : __CODEGEN_BITFIELD( 0, 7) ; //!< MvCost 0 2107 uint32_t MvCost1 : __CODEGEN_BITFIELD( 8, 15) ; //!< MvCost 1 2108 uint32_t MvCost2 : __CODEGEN_BITFIELD(16, 23) ; //!< MvCost 2 2109 uint32_t MvCost3 : __CODEGEN_BITFIELD(24, 31) ; //!< MvCost 3 2110 }; 2111 uint32_t Value; 2112 } DW12; 2113 union 2114 { 2115 //!< DWORD 13 2116 struct 2117 { 2118 uint32_t MvCost4 : __CODEGEN_BITFIELD( 0, 7) ; //!< MvCost 4 2119 uint32_t MvCost5 : __CODEGEN_BITFIELD( 8, 15) ; //!< MvCost 5 2120 uint32_t MvCost6 : __CODEGEN_BITFIELD(16, 23) ; //!< MvCost 6 2121 uint32_t MvCost7 : __CODEGEN_BITFIELD(24, 31) ; //!< MvCost 7 2122 }; 2123 uint32_t Value; 2124 } DW13; 2125 union 2126 { 2127 //!< DWORD 14 2128 struct 2129 { 2130 uint32_t QpPrimeY : __CODEGEN_BITFIELD( 0, 7) ; //!< QpPrimeY 2131 uint32_t Reserved456 : __CODEGEN_BITFIELD( 8, 23) ; //!< Reserved 2132 uint32_t TargetSizeInWord : __CODEGEN_BITFIELD(24, 31) ; //!< TargetSizeInWord 2133 }; 2134 uint32_t Value; 2135 } DW14; 2136 union 2137 { 2138 //!< DWORD 15 2139 struct 2140 { 2141 uint32_t Reserved480 ; //!< Reserved 2142 }; 2143 uint32_t Value; 2144 } DW15; 2145 union 2146 { 2147 //!< DWORD 16 2148 struct 2149 { 2150 uint32_t Reserved512 ; //!< Reserved 2151 }; 2152 uint32_t Value; 2153 } DW16; 2154 union 2155 { 2156 //!< DWORD 17 2157 struct 2158 { 2159 uint32_t AvcIntra4X4ModeMask : __CODEGEN_BITFIELD( 0, 8) ; //!< AVC Intra 4x4 Mode Mask 2160 uint32_t Reserved553 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2161 uint32_t AvcIntra8X8ModeMask : __CODEGEN_BITFIELD(16, 24) ; //!< AVC Intra 8x8 Mode Mask 2162 uint32_t Reserved569 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 2163 }; 2164 uint32_t Value; 2165 } DW17; 2166 union 2167 { 2168 //!< DWORD 18 2169 struct 2170 { 2171 uint32_t AvcIntra16X16ModeMask : __CODEGEN_BITFIELD( 0, 3) ; //!< AVC_INTRA_16X16_MODE_MASK 2172 uint32_t AvcIntraChromaModeMask : __CODEGEN_BITFIELD( 4, 7) ; //!< AVC_INTRA_CHROMA_MODE_MASK 2173 uint32_t IntraComputeTypeIntracomputetype : __CODEGEN_BITFIELD( 8, 9) ; //!< INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2174 uint32_t Reserved586 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 2175 }; 2176 uint32_t Value; 2177 } DW18; 2178 union 2179 { 2180 //!< DWORD 19 2181 struct 2182 { 2183 uint32_t Reserved608 ; //!< Reserved 2184 }; 2185 uint32_t Value; 2186 } DW19; 2187 union 2188 { 2189 //!< DWORD 20 2190 struct 2191 { 2192 uint32_t PenaltyForIntra16X16NondcPrediction : __CODEGEN_BITFIELD( 0, 7) ; //!< Penalty for Intra16x16 NonDC Prediction. 2193 uint32_t PenaltyForIntra8X8NondcPrediction : __CODEGEN_BITFIELD( 8, 15) ; //!< Penalty for Intra8x8 NonDC Prediction. 2194 uint32_t PenaltyForIntra4X4NondcPrediction : __CODEGEN_BITFIELD(16, 23) ; //!< Penalty for Intra4x4 NonDC Prediction. 2195 uint32_t Reserved664 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2196 }; 2197 uint32_t Value; 2198 } DW20; 2199 union 2200 { 2201 //!< DWORD 21 2202 struct 2203 { 2204 uint32_t IntraRefreshMBPos : __CODEGEN_BITFIELD( 0, 7) ; //!< IntraRefreshMBPos 2205 uint32_t IntraRefreshMBSizeMinusOne : __CODEGEN_BITFIELD( 8, 15) ; //!< IntraRefreshMBSizeMinusOne 2206 uint32_t IntraRefreshEnableRollingIEnable : __CODEGEN_BITFIELD(16, 16) ; //!< INTRAREFRESHENABLE_ROLLING_I_ENABLE 2207 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(17, 17) ; //!< INTRAREFRESHMODE 2208 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 23) ; //!< Reserved 2209 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(24, 31) ; //!< QP adjustment for Rolling-I 2210 }; 2211 uint32_t Value; 2212 } DW21; 2213 union 2214 { 2215 //!< DWORD 22 2216 struct 2217 { 2218 uint32_t Panicmodembthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< PanicModeMBThreshold 2219 uint32_t Smallmbsizeinword : __CODEGEN_BITFIELD(16, 23) ; //!< SmallMbSizeInWord 2220 uint32_t Largembsizeinword : __CODEGEN_BITFIELD(24, 31) ; //!< LargeMbSizeInWord 2221 }; 2222 uint32_t Value; 2223 } DW22; 2224 union 2225 { 2226 //!< DWORD 23 2227 struct 2228 { 2229 uint32_t L0NumberOfReferencesMinusOne : __CODEGEN_BITFIELD( 0, 7) ; //!< L0 number of references Minus one 2230 uint32_t Reserved744 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 2231 uint32_t L1NumberOfReferencesMinusOne : __CODEGEN_BITFIELD(16, 23) ; //!< L1 number of references Minus One 2232 uint32_t Reserved760 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2233 }; 2234 uint32_t Value; 2235 } DW23; 2236 union 2237 { 2238 //!< DWORD 24 2239 struct 2240 { 2241 uint32_t MacroblockBudget : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock Budget 2242 uint32_t InitialTime : __CODEGEN_BITFIELD(16, 31) ; //!< Initial Time 2243 }; 2244 uint32_t Value; 2245 } DW24; 2246 union 2247 { 2248 //!< DWORD 25 2249 struct 2250 { 2251 uint32_t Reserved800 ; //!< Reserved 2252 }; 2253 uint32_t Value; 2254 } DW25; 2255 union 2256 { 2257 //!< DWORD 26 2258 struct 2259 { 2260 uint32_t Reserved832 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 2261 uint32_t HmeRefWindowsCombiningThreshold : __CODEGEN_BITFIELD( 8, 15) ; //!< HME_REF_WINDOWS_COMBINING_THRESHOLD 2262 uint32_t Reserved848 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2263 }; 2264 uint32_t Value; 2265 } DW26; 2266 union 2267 { 2268 //!< DWORD 27 2269 struct 2270 { 2271 uint32_t MaxHmvR : __CODEGEN_BITFIELD( 0, 15) ; //!< MAXHMVR 2272 uint32_t MaxVmvR : __CODEGEN_BITFIELD(16, 31) ; //!< MAXVMVR 2273 }; 2274 uint32_t Value; 2275 } DW27; 2276 union 2277 { 2278 //!< DWORD 28 2279 struct 2280 { 2281 uint32_t HmeMvCost0 : __CODEGEN_BITFIELD( 0, 7) ; //!< HmeMvCost 0 2282 uint32_t HmeMvCost1 : __CODEGEN_BITFIELD( 8, 15) ; //!< HmeMvCost 1 2283 uint32_t HmeMvCost2 : __CODEGEN_BITFIELD(16, 23) ; //!< HmeMvCost 2 2284 uint32_t HmeMvCost3 : __CODEGEN_BITFIELD(24, 31) ; //!< HmeMvCost 3 2285 }; 2286 uint32_t Value; 2287 } DW28; 2288 union 2289 { 2290 //!< DWORD 29 2291 struct 2292 { 2293 uint32_t HmeMvCost4 : __CODEGEN_BITFIELD( 0, 7) ; //!< HmeMvCost 4 2294 uint32_t HmeMvCost5 : __CODEGEN_BITFIELD( 8, 15) ; //!< HmeMvCost 5 2295 uint32_t HmeMvCost6 : __CODEGEN_BITFIELD(16, 23) ; //!< HmeMvCost 6 2296 uint32_t HmeMvCost7 : __CODEGEN_BITFIELD(24, 31) ; //!< HmeMvCost 7 2297 }; 2298 uint32_t Value; 2299 } DW29; 2300 union 2301 { 2302 //!< DWORD 30 2303 struct 2304 { 2305 uint32_t RoiQpAdjustmentForZone0 : __CODEGEN_BITFIELD( 0, 3) ; //!< ROI QP adjustment for Zone0 2306 uint32_t RoiQpAdjustmentForZone1 : __CODEGEN_BITFIELD( 4, 7) ; //!< ROI QP adjustment for Zone1 2307 uint32_t RoiQpAdjustmentForZone2 : __CODEGEN_BITFIELD( 8, 11) ; //!< ROI QP adjustment for Zone2 2308 uint32_t RoiQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15) ; //!< ROI QP adjustment for Zone3 2309 uint32_t QpAdjustmentForShapeBestIntra4X4Winner : __CODEGEN_BITFIELD(16, 19) ; //!< QP adjustment for shape best intra 4x4 winner 2310 uint32_t QpAdjustmentForShapeBestIntra8X8Winner : __CODEGEN_BITFIELD(20, 23) ; //!< QP adjustment for shape best intra 8x8 winner 2311 uint32_t QpAdjustmentForShapeBestIntra16X16Winner : __CODEGEN_BITFIELD(24, 27) ; //!< QP adjustment for shape best intra 16x16 winner 2312 uint32_t Reserved988 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2313 }; 2314 uint32_t Value; 2315 } DW30; 2316 union 2317 { 2318 //!< DWORD 31 2319 struct 2320 { 2321 uint32_t BestdistortionQpAdjustmentForZone0 : __CODEGEN_BITFIELD( 0, 3) ; //!< BestDistortion QP adjustment for Zone0 2322 uint32_t BestdistortionQpAdjustmentForZone1 : __CODEGEN_BITFIELD( 4, 7) ; //!< BestDistortion QP adjustment for Zone1 2323 uint32_t BestdistortionQpAdjustmentForZone2 : __CODEGEN_BITFIELD( 8, 11) ; //!< BestDistortion QP adjustment for Zone2 2324 uint32_t BestdistortionQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15) ; //!< BestDistortion QP adjustment for Zone3 2325 uint32_t SadHaarThreshold0 : __CODEGEN_BITFIELD(16, 31) ; //!< Sad/Haar_Threshold_0 2326 }; 2327 uint32_t Value; 2328 } DW31; 2329 union 2330 { 2331 //!< DWORD 32 2332 struct 2333 { 2334 uint32_t SadHaarThreshold1 : __CODEGEN_BITFIELD( 0, 15) ; //!< Sad/Haar_Threshold_1 2335 uint32_t SadHaarThreshold2 : __CODEGEN_BITFIELD(16, 31) ; //!< Sad/Haar_Threshold_2 2336 }; 2337 uint32_t Value; 2338 } DW32; 2339 union 2340 { 2341 //!< DWORD 33 2342 struct 2343 { 2344 uint32_t MaxQp : __CODEGEN_BITFIELD( 0, 7) ; //!< MaxQP 2345 uint32_t MinQp : __CODEGEN_BITFIELD( 8, 15) ; //!< MinQP 2346 uint32_t Reserved1072 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 2347 uint32_t Maxdeltaqp : __CODEGEN_BITFIELD(24, 27) ; //!< MaxDeltaQP 2348 uint32_t Reserved1084 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2349 }; 2350 uint32_t Value; 2351 } DW33; 2352 union 2353 { 2354 //!< DWORD 34 2355 struct 2356 { 2357 uint32_t RoiEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< ROI_Enable 2358 uint32_t FwdPredictor0MvEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Fwd/Predictor0 MV Enable 2359 uint32_t BwdPredictor1MvEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< Bwd/Predictor1 MV Enable 2360 uint32_t MbLevelQpEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< MB Level QP Enable 2361 uint32_t TargetsizeinwordsmbMaxsizeinwordsmbEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< TargetSizeinWordsMB/MaxSizeinWordsMB Enable 2362 uint32_t Reserverd : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserverd 2363 uint32_t PpmvDisable : __CODEGEN_BITFIELD( 8, 8) ; //!< PPMV_DISABLE 2364 uint32_t CoefficientClampEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Coefficient Clamp Enable 2365 uint32_t LongtermReferenceFrameBwdRef0Indicator : __CODEGEN_BITFIELD(10, 10) ; //!< LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2366 uint32_t LongtermReferenceFrameFwdRef2Indicator : __CODEGEN_BITFIELD(11, 11) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2367 uint32_t LongtermReferenceFrameFwdRef1Indicator : __CODEGEN_BITFIELD(12, 12) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2368 uint32_t LongtermReferenceFrameFwdRef0Indicator : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2369 uint32_t Reserved1102 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 2370 uint32_t MidpointSadHaar : __CODEGEN_BITFIELD(16, 31) ; //!< Midpoint sad/haar 2371 }; 2372 uint32_t Value; 2373 } DW34; 2374 2375 //! \name Local enumerations 2376 2377 enum SUBOPB 2378 { 2379 SUBOPB_VDENCIMGSTATE = 5, //!< No additional details 2380 }; 2381 2382 enum SUBOPA 2383 { 2384 SUBOPA_UNNAMED0 = 0, //!< No additional details 2385 }; 2386 2387 enum OPCODE 2388 { 2389 OPCODE_VDENCPIPE = 1, //!< No additional details 2390 }; 2391 2392 enum PIPELINE 2393 { 2394 PIPELINE_MFXCOMMON = 2, //!< No additional details 2395 }; 2396 2397 enum COMMAND_TYPE 2398 { 2399 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2400 }; 2401 2402 enum BIDIRECTIONAL_MIX_DISABLE 2403 { 2404 BIDIRECTIONAL_MIX_DISABLE_SUBBLOCKENABLED = 0, //!< Bidirectional decision on subblock level that bidirectional mode is enabled. 2405 BIDIRECTIONAL_MIX_DISABLE_WHOLEMACROBLOCKENABLED = 1, //!< Bidirectional decision on whole macroblock. 2406 }; 2407 2408 //! \brief VDENC_PERFMODE 2409 //! \details 2410 //! This bit indicates if VDEnc is configured for normal or speed mode of 2411 //! operation. 2412 enum VDENC_PERFMODE 2413 { 2414 VDENC_PERFMODE_NORMAL = 0, //!< VDEnc is running in normal mode. IME Search: 3x3 SU per each reference. HME Search: 88x92 search window per HME instance (0 & 1). 2415 VDENC_PERFMODE_SPEED = 1, //!< VDEnc is configured for speed mode. IME Search: 2x2 SU per each reference. HME Search: 48x92 search window per HME instance (0 & 1). 2416 }; 2417 2418 //! \brief TIME_BUDGET_OVERFLOW_CHECK 2419 //! \details 2420 //! <p>This bit enables the frame time budget detection in VDEnc.</p> 2421 //! <p>To detect if a Time Budget Overflow happened in a frame, SW 2422 //! can read "PAK_Stream-Out Report (Errors)" register in MFX. When Time 2423 //! budget overflow condition happens in the frame, this register bits 15:8 2424 //! indicate MB y position and bits 7:0 indicate MB x position where Time 2425 //! budget overflow occured. When there is no time budget overflow in a 2426 //! frame, "<span style="line-height: 20.7999992370605px;">PAK_Stream-Out 2427 //! Report (Errors)" register reads zero.</span></p> 2428 enum TIME_BUDGET_OVERFLOW_CHECK 2429 { 2430 TIME_BUDGET_OVERFLOW_CHECK_DISABLED = 0, //!< No additional details 2431 TIME_BUDGET_OVERFLOW_CHECK_ENABLED = 1, //!< No additional details 2432 }; 2433 2434 //! \brief VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 2435 //! \details 2436 //! This bit enables the distortion data to be populated in the VDenc PAK 2437 //! Obj inline data. 2438 enum VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 2439 { 2440 VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE_DISABLE = 0, //!< The extra two DWS from VDEnc (MDC) to PAK will be Zero. 2441 VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE_ENABLE = 1, //!< The last two DWs from VDEnc (MDC) to PAK will be populated with distortion data. (Defined in the PAK Object command DW 22,23.) 2442 }; 2443 2444 //! \brief TRANSFORM_8X8_FLAG 2445 //! \details 2446 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flag specifies 8x8 IDCT 2447 //! transform may be used in this picture. It is set to the value of the 2448 //! syntax element in the current active PPS. 2449 enum TRANSFORM_8X8_FLAG 2450 { 2451 TRANSFORM_8X8_FLAG_DISABLED = 0, //!< No 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present. 2452 TRANSFORM_8X8_FLAG_ENABLED = 1, //!< 8x8 Transform is allowed. 2453 }; 2454 2455 //! \brief VDENC_L1_CACHE_PRIORITY 2456 //! \details 2457 //! L1 Cache inside VDEnc has 3 clients - IME, CRE and VMC. 2458 //! These bits indicate the priority order for L1 cache to 2459 //! service the client requests. 2460 enum VDENC_L1_CACHE_PRIORITY 2461 { 2462 VDENC_L1_CACHE_PRIORITY_UNNAMED0 = 0, //!< CRE High Priority, VMC and IME round robin. 2463 VDENC_L1_CACHE_PRIORITY_UNNAMED1 = 1, //!< CRE and VMC round robin, IME low priority. 2464 VDENC_L1_CACHE_PRIORITY_UNNAMED2 = 2, //!< CRE High Priority, IME Medium, VMC Low. 2465 VDENC_L1_CACHE_PRIORITY_UNNAMED3 = 3, //!< VMC High Priority, CRE Medium, IME low. 2466 }; 2467 2468 //! \brief BIDIRECTIONAL_WEIGHT 2469 //! \details 2470 //! Default value: Depends on the distance between the B and reference 2471 //! pictures. 2472 enum BIDIRECTIONAL_WEIGHT 2473 { 2474 BIDIRECTIONAL_WEIGHT_UNNAMED16 = 16, //!< No additional details 2475 BIDIRECTIONAL_WEIGHT_UNNAMED21 = 21, //!< No additional details 2476 BIDIRECTIONAL_WEIGHT_UNNAMED32 = 32, //!< No additional details 2477 BIDIRECTIONAL_WEIGHT_UNNAMED43 = 43, //!< No additional details 2478 BIDIRECTIONAL_WEIGHT_UNNAMED48 = 48, //!< No additional details 2479 }; 2480 2481 //! \brief SUB_PEL_MODE 2482 //! \details 2483 //! This field defines the half/quarter pel modes. The mode is inclusive, 2484 //! i.e., higher precision mode samples lower precision locations. 2485 enum SUB_PEL_MODE 2486 { 2487 SUB_PEL_MODE_UNNAMED0 = 0, //!< Integer mode searching. 2488 SUB_PEL_MODE_UNNAMED1 = 1, //!< Half-pel mode searching. 2489 SUB_PEL_MODE_UNNAMED3 = 3, //!< Quarter-pel mode searching. 2490 }; 2491 2492 //! \brief FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2493 //! \details 2494 //! This field enables the forward transform calculation for skip check. 2495 //! It does not override the other skip calculations but it does decrease 2496 //! the performance marginally so don't enable it unless the transform 2497 //! is necessary. 2498 enum FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2499 { 2500 FORWARD_TRANSFORM_SKIP_CHECK_ENABLE_FTDISABLED = 0, //!< No additional details 2501 FORWARD_TRANSFORM_SKIP_CHECK_ENABLE_FTENABLED = 1, //!< No additional details 2502 }; 2503 2504 //! \brief BME_DISABLE_FOR_FBR_MESSAGE 2505 //! \details 2506 //! FBR messages that do not want bidirectional motion estimation 2507 //! performed will set this bit and VME will only perform 2508 //! fractional refinement on the shapes identified by subpredmode. 2509 //! Note: only the LSB of the subpredmode for each shape will be 2510 //! considered in FBR (a shape iseither FWD or BWD as input of FBR, 2511 //! output however could change toBI if BME is enabled). 2512 enum BME_DISABLE_FOR_FBR_MESSAGE 2513 { 2514 BME_DISABLE_FOR_FBR_MESSAGE_BMEENABLED = 0, //!< No additional details 2515 BME_DISABLE_FOR_FBR_MESSAGE_BMEDISABLED = 1, //!< No additional details 2516 }; 2517 2518 //! \brief BLOCK_BASED_SKIP_ENABLED 2519 //! \details 2520 //! When this field is set on the skip thresholding passing criterion will 2521 //! be based on the maximal distortion of individual blocks (8x8's or 4x4's) 2522 //! instead of their sum (i.e. the distortion of 16x16). 2523 enum BLOCK_BASED_SKIP_ENABLED 2524 { 2525 BLOCK_BASED_SKIP_ENABLED_UNNAMED0 = 0, //!< 16x16 Block Based Skip threshold check. 2526 BLOCK_BASED_SKIP_ENABLED_BLOCK_BASEDSKIPTYPE = 1, //!< Parameter indicates 8x8 vs. 4x4 based check. 2527 }; 2528 2529 //! \brief INTER_SAD_MEASURE_ADJUSTMENT 2530 //! \details 2531 //! This field specifies distortion measure adjustments used 2532 //! for the motion search SAD comparison. This field applies 2533 //! to both luma and chroma inter measurement. 2534 enum INTER_SAD_MEASURE_ADJUSTMENT 2535 { 2536 INTER_SAD_MEASURE_ADJUSTMENT_NONE = 0, //!< No additional details 2537 INTER_SAD_MEASURE_ADJUSTMENT_HAARTRANSFORMADJUSTED = 2, //!< No additional details 2538 }; 2539 2540 //! \brief INTRA_SAD_MEASURE_ADJUSTMENT 2541 //! \details 2542 //! This field specifies distortion measure adjustments used for the motion 2543 //! search SAD comparison. This field applies to both luma and chroma 2544 //! intra measurement. 2545 enum INTRA_SAD_MEASURE_ADJUSTMENT 2546 { 2547 INTRA_SAD_MEASURE_ADJUSTMENT_NONE = 0, //!< No additional details 2548 INTRA_SAD_MEASURE_ADJUSTMENT_HAARTRANSFORMADJUSTED = 2, //!< No additional details 2549 }; 2550 2551 //! \brief SUB_MACROBLOCK_SUB_PARTITION_MASK 2552 //! \details 2553 //! This field defines the bit-mask for disabling 2554 //! <ul> 2555 //! <li>sub-partition (minor partition [30:28]) modes</li> 2556 //! <li>sub-macroblock (major partition [27:24]) modes</li> 2557 //! </ul> 2558 enum SUB_MACROBLOCK_SUB_PARTITION_MASK 2559 { 2560 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED113 = 113, //!< 16x16 sub-macroblock disabled 2561 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED114 = 114, //!< 2x(16x8) sub-macroblock within 16x16 disabled 2562 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED116 = 116, //!< 2x(8x16) sub-macroblock within 16x16 disabled 2563 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED120 = 120, //!< 1x(8x8) sub-partition for 4x(8x8) within 16x16 disabled 2564 }; 2565 2566 //! \brief BLOCK_BASED_SKIP_TYPE 2567 //! \details 2568 //! The skip thresholding passing criterion will be based on the maximal 2569 //! distortion of individual blocks (8x8's or 4x4's) instead of 2570 //! their sum (i.e. the distortion of 16x16). This field is only valid 2571 //! when <b>Block-Based Skip Enabled</b> = 1. 2572 enum BLOCK_BASED_SKIP_TYPE 2573 { 2574 BLOCK_BASED_SKIP_TYPE_UNNAMED0 = 0, //!< 4x4 block-based skip threshold check. 2575 BLOCK_BASED_SKIP_TYPE_UNNAMED1 = 1, //!< 8x8 block-based skip threshold check. 2576 }; 2577 2578 //! \brief CRE_PREFETCH_ENABLE 2579 //! \details 2580 //! This field determines if IME will prefetch the fractional CLs that are 2581 //! required by CRE ahead of time while fetching the reference windows around 2582 //! the IME predictors. The recommendation for driver is to always program 2583 //! this bit to 1 unless some usages restrict SubPelMode to be "<i>Integer 2584 //! mode searching</i>". 2585 enum CRE_PREFETCH_ENABLE 2586 { 2587 CRE_PREFETCH_ENABLE_UNNAMED0 = 0, //!< Disable 2588 CRE_PREFETCH_ENABLE_UNNAMED1 = 1, //!< Enable 2589 }; 2590 2591 //! \brief HME_REF1_DISABLE 2592 //! \details 2593 //! This field indicates if HME is disabled for reference 1 (second forward 2594 //! reference). 2595 enum HME_REF1_DISABLE 2596 { 2597 HME_REF1_DISABLE_UNNAMED0 = 0, //!< HME search is performed on forward reference 1. 2598 HME_REF1_DISABLE_UNNAMED1 = 1, //!< HME search is disabled on forward reference 1. 2599 }; 2600 2601 enum CONSTRAINED_INTRA_PREDICTION_FLAG 2602 { 2603 CONSTRAINED_INTRA_PREDICTION_FLAG_UNNAMED0 = 0, //!< Allows both intra and inter neighboring MB to be used in the intra-prediction decoding of the current MB. 2604 CONSTRAINED_INTRA_PREDICTION_FLAG_UNNAMED1 = 1, //!< Allows only to use neighboring Intra MBs in the intra-prediction decoding of the current MB.If the neighbor is an inter MB, it is considered as not available. 2605 }; 2606 2607 //! \brief PICTURE_TYPE 2608 //! \details 2609 //! This field specifies how the current picture is predicted. (It might be 2610 //! redundant from the kernel type.) 2611 enum PICTURE_TYPE 2612 { 2613 PICTURE_TYPE_I = 0, //!< No additional details 2614 PICTURE_TYPE_P = 1, //!< No additional details 2615 }; 2616 2617 //! \brief LUMA_INTRA_PARTITION_MASK 2618 //! \details 2619 //! This field specifies which Luma Intra partition is enabled/disabled for 2620 //! intra mode decision. 2621 enum LUMA_INTRA_PARTITION_MASK 2622 { 2623 LUMA_INTRA_PARTITION_MASK_UNNAMED1 = 1, //!< luma_intra_16x16 disabled 2624 LUMA_INTRA_PARTITION_MASK_UNNAMED2 = 2, //!< luma_intra_8x8 disabled 2625 LUMA_INTRA_PARTITION_MASK_UNNAMED4 = 4, //!< luma_intra_4x4 disabled 2626 }; 2627 2628 enum MV_COST_SCALING_FACTOR 2629 { 2630 MV_COST_SCALING_FACTOR_QPEL = 0, //!< Qpel difference between MV and cost center: eff cost range 0-15pel 2631 MV_COST_SCALING_FACTOR_HPEL = 1, //!< Hpel difference between MV and cost center: eff cost range 0-31pel 2632 MV_COST_SCALING_FACTOR_PEL = 2, //!< Pel difference between MV and cost center: eff cost range 0-63pel 2633 MV_COST_SCALING_FACTOR_2PEL = 3, //!< 2Pel difference between MV and cost center: eff cost range 0-127pel 2634 }; 2635 2636 enum REFID_COST_MODE_SELECT 2637 { 2638 REFID_COST_MODE_SELECT_MODE0 = 0, //!< AVC 2639 REFID_COST_MODE_SELECT_MODE1 = 1, //!< Linear 2640 }; 2641 2642 enum AVC_INTRA_16X16_MODE_MASK 2643 { 2644 AVC_INTRA_16X16_MODE_MASK_VERT = 1, //!< No additional details 2645 AVC_INTRA_16X16_MODE_MASK_HORZ = 2, //!< No additional details 2646 AVC_INTRA_16X16_MODE_MASK_DC = 4, //!< No additional details 2647 AVC_INTRA_16X16_MODE_MASK_PLANAR = 8, //!< No additional details 2648 }; 2649 2650 enum AVC_INTRA_CHROMA_MODE_MASK 2651 { 2652 AVC_INTRA_CHROMA_MODE_MASK_VERT = 1, //!< No additional details 2653 AVC_INTRA_CHROMA_MODE_MASK_HORZ = 2, //!< No additional details 2654 AVC_INTRA_CHROMA_MODE_MASK_DC = 4, //!< No additional details 2655 AVC_INTRA_CHROMA_MODE_MASK_PLANAR = 8, //!< No additional details 2656 }; 2657 2658 //! \brief INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2659 //! \details 2660 //! This field specifies the pixel components measured for Intra prediction. 2661 enum INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2662 { 2663 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED0 = 0, //!< Luma+Chroma enabled. 2664 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED1 = 1, //!< Luma Only. 2665 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED2 = 2, //!< Intra Disabled. 2666 }; 2667 2668 //! \brief INTRAREFRESHENABLE_ROLLING_I_ENABLE 2669 //! \details 2670 //! <p>This parameter indicates if the IntraRefresh is enabled or 2671 //! disabled.</p> 2672 //! 2673 //! <p>This must be disabled on I-Frames.</p> 2674 enum INTRAREFRESHENABLE_ROLLING_I_ENABLE 2675 { 2676 INTRAREFRESHENABLE_ROLLING_I_ENABLE_DISABLE = 0, //!< No additional details 2677 INTRAREFRESHENABLE_ROLLING_I_ENABLE_ENABLE = 1, //!< No additional details 2678 }; 2679 2680 //! \brief INTRAREFRESHMODE 2681 //! \details 2682 //! This parameter indicates if the IntraRefresh is row based or column 2683 //! based. 2684 enum INTRAREFRESHMODE 2685 { 2686 INTRAREFRESHMODE_ROWBASED = 0, //!< No additional details 2687 INTRAREFRESHMODE_COLUMNBASED = 1, //!< No additional details 2688 }; 2689 2690 //! \brief HME_REF_WINDOWS_COMBINING_THRESHOLD 2691 //! \details 2692 //! When the reference windows of the HME refinement VME call and the 2693 //! regular VME call are overlapped and the difference of the locations 2694 //! is within this threshold in quarter pixel unit, the two calls 2695 //! are merged to a single call. 2696 enum HME_REF_WINDOWS_COMBINING_THRESHOLD 2697 { 2698 HME_REF_WINDOWS_COMBINING_THRESHOLD_UNNAMED0 = 0, //!< No additional details 2699 HME_REF_WINDOWS_COMBINING_THRESHOLD_UNNAMED255 = 255, //!< No additional details 2700 }; 2701 2702 //! \brief MAXHMVR 2703 //! \details 2704 //! Horizontal MV component range. The MV range is restricted to 2705 //! [-MaxHmvR+1, MaxHmvR-1] in luma quarter pel unit, 2706 //! which corresponds to [-MaxHmvR/4 + 0.25, MaxHmvR/4-0.25] in luma 2707 //! integer pel unit. 2708 enum MAXHMVR 2709 { 2710 MAXHMVR_UNNAMED256 = 256, //!< No additional details 2711 MAXHMVR_UNNAMED512 = 512, //!< No additional details 2712 MAXHMVR_UNNAMED1024 = 1024, //!< No additional details 2713 MAXHMVR_UNNAMED2048 = 2048, //!< No additional details 2714 MAXHMVR_UNNAMED4096 = 4096, //!< No additional details 2715 MAXHMVR_UNNAMED8192 = 8192, //!< No additional details 2716 }; 2717 2718 //! \brief MAXVMVR 2719 //! \details 2720 //! Vertical MV component range defined in the AVC Spec Annex A. 2721 //! The MV range is restricted to [-MaxVmvR+1, MaxVmvR-1] 2722 //! in luma quarter pel unit, which corresponds to 2723 //! [-MaxVmvR/4 + 0.25, MaxVmvR/4-0.25] in luma integer pel unit. 2724 enum MAXVMVR 2725 { 2726 MAXVMVR_UNNAMED256 = 256, //!< No additional details 2727 MAXVMVR_UNNAMED512 = 512, //!< No additional details 2728 MAXVMVR_UNNAMED1024 = 1024, //!< No additional details 2729 MAXVMVR_UNNAMED2048 = 2048, //!< No additional details 2730 }; 2731 2732 //! \brief PPMV_DISABLE 2733 //! \details 2734 //! This bit forces the IME to use the actual PMV predictor for the IME 2735 //! search. 2736 enum PPMV_DISABLE 2737 { 2738 PPMV_DISABLE_UNNAMED0 = 0, //!< Use PPMV based IME search. 2739 PPMV_DISABLE_UNNAMED1 = 1, //!< Use PMV based IME search. 2740 }; 2741 2742 //! \brief LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2743 //! \details 2744 //! Indicates whether the reference frame is a long or short term reference. 2745 enum LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2746 { 2747 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2748 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2749 }; 2750 2751 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2752 //! \details 2753 //! Indicates whether the reference frame is a long or short term reference. 2754 enum LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2755 { 2756 LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2757 LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2758 }; 2759 2760 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2761 //! \details 2762 //! Indicates whether the reference frame is a long or short term reference. 2763 enum LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2764 { 2765 LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2766 LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2767 }; 2768 2769 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2770 //! \details 2771 //! Indicates whether the reference frame is a long or short term reference. 2772 enum LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2773 { 2774 LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2775 LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2776 }; 2777 2778 //! \name Initializations 2779 2780 //! \brief Explicit member initialization function 2781 VDENC_IMG_STATE_CMD(); 2782 2783 static const size_t dwSize = 35; 2784 static const size_t byteSize = 140; 2785 }; 2786 2787 //! 2788 //! \brief VDENC_PIPE_BUF_ADDR_STATE 2789 //! \details 2790 //! This state command provides the memory base addresses for all row 2791 //! stores, Streamin/StreamOut, DMV buffer along with the uncompressed 2792 //! source, reference pictures and downscaled reference pictures required by 2793 //! the VDENC pipeline. All reference pixel surfaces in the Encoder are 2794 //! programmed with the same surface state (NV12 and TileY format), except 2795 //! each has its own frame buffer base address. Same holds true for the 2796 //! down-scaled reference pictures too. In the tile format, there is no need 2797 //! to provide buffer offset for each slice; since from each MB address, the 2798 //! hardware can calculated the corresponding memory location within the 2799 //! frame buffer directly. VDEnc supports 3 Downscaled reference frames ( 2 2800 //! fwd, 1 bwd) and 4 normal reference frames ( 3 fwd, 1 bwd). The driver 2801 //! will sort out the base address from the DPB table and populate the base 2802 //! addresses that map to the corresponding reference index for both DS 2803 //! references and normal reference frames. Each of the individual DS ref/ 2804 //! Normal ref frames have their own MOCS DW that corresponds to the 2805 //! respective base address. The only thing that is different in the MOCS DW 2806 //! amongst the DS reference frames is the MMCD controls (specified in bits 2807 //! [10:9] of the MOCS DW). Driver needs to ensure that the other bits need 2808 //! to be the same across the different DS ref frames. The same is 2809 //! applicable for the normal reference frames. 2810 //! 2811 struct VDENC_PIPE_BUF_ADDR_STATE_CMD 2812 { 2813 union 2814 { 2815 //!< DWORD 0 2816 struct 2817 { 2818 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2819 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2820 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2821 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2822 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2823 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2824 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2825 }; 2826 uint32_t Value; 2827 } DW0; 2828 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef0 ; //!< DS FWD REF0 2829 union 2830 { 2831 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef1; //!< DS FWD REF1 2832 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef0; //!< DS BWD REF0 2833 }; 2834 VDENC_Down_Scaled_Reference_Picture_CMD Reserved; //!< Reserved 2835 VDENC_Original_Uncompressed_Picture_CMD OriginalUncompressedPicture ; //!< Original Uncompressed Picture 2836 VDENC_Streamin_Data_Picture_CMD StreaminDataPicture ; //!< Streamin Data Picture 2837 VDENC_Row_Store_Scratch_Buffer_Picture_CMD RowStoreScratchBuffer ; //!< Row Store Scratch Buffer 2838 VDENC_Colocated_MV_Picture_CMD ColocatedMv ; //!< Colocated MV 2839 VDENC_Reference_Picture_CMD FwdRef0 ; //!< FWD REF0 2840 VDENC_Reference_Picture_CMD FwdRef1 ; //!< FWD REF1 2841 VDENC_Reference_Picture_CMD FwdRef2 ; //!< FWD REF2 2842 VDENC_Reference_Picture_CMD BwdRef0 ; //!< BWD REF0 2843 VDENC_Statistics_Streamout_CMD VdencStatisticsStreamout ; //!< VDEnc Statistics Streamout 2844 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef04X ; //!< DS FWD REF0 4X 2845 union 2846 { 2847 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef14X ; //!< DS FWD REF1 4X 2848 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef04X ; //!< DS BWD REF1 4X 2849 }; 2850 VDENC_Colocated_MV_Picture_CMD VdencCuRecordStreamOutBuffer ; //!< VDEnc CuRecord stream-out buffer 2851 VDENC_Colocated_MV_Picture_CMD VdencLcuPakObjCmdBuffer ; //!< VDEnc LCU PAK OBJ CMD Buffer 2852 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurface8X ; //!< Scaled Reference Surface 8X 2853 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurface4X ; //!< Scaled Reference Surface 4X 2854 VDENC_Colocated_MV_Picture_CMD Vp9SegmentationMapStreaminBuffer ; //!< VP9 Segmentation Map Streamin Buffer 2855 VDENC_Colocated_MV_Picture_CMD Vp9SegmentationMapStreamoutBuffer ; //!< VP9 Segmentation Map Streamout Buffer 2856 union 2857 { 2858 //!< DWORD 61 2859 struct 2860 { 2861 uint32_t WeightsHistogramStreamoutOffset ; //!< Weights Histogram Streamout offset 2862 }; 2863 uint32_t Value; 2864 } DW61; 2865 VDENC_Row_Store_Scratch_Buffer_Picture_CMD VdencTileRowStoreBuffer ; //!< VDENC Tile Row store Buffer 2866 VDENC_Statistics_Streamout_CMD VdencCumulativeCuCountStreamoutSurface ; //!< VDENC Cumulative CU count streamout surface 2867 VDENC_Statistics_Streamout_CMD VdencPaletteModeStreamoutSurface ; //!< VDENC Palette Mode streamout surface 2868 2869 //! \name Local enumerations 2870 2871 enum SUBOPB 2872 { 2873 SUBOPB_VDENCPIPEBUFADDRSTATE = 4, //!< No additional details 2874 }; 2875 2876 enum SUBOPA 2877 { 2878 SUBOPA_UNNAMED0 = 0, //!< No additional details 2879 }; 2880 2881 enum OPCODE 2882 { 2883 OPCODE_VDENCPIPE = 1, //!< No additional details 2884 }; 2885 2886 enum PIPELINE 2887 { 2888 PIPELINE_MFXCOMMON = 2, //!< No additional details 2889 }; 2890 2891 enum COMMAND_TYPE 2892 { 2893 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2894 }; 2895 2896 //! \name Initializations 2897 2898 //! \brief Explicit member initialization function 2899 VDENC_PIPE_BUF_ADDR_STATE_CMD(); 2900 2901 static const size_t dwSize = 71; 2902 static const size_t byteSize = 284; 2903 }; 2904 2905 //! 2906 //! \brief VDENC_PIPE_MODE_SELECT 2907 //! \details 2908 //! Specifies which codec and hardware module is being used to encode/decode 2909 //! the video data, on a per-frame basis. The VDENC_PIPE_MODE_SELECT command 2910 //! specifies which codec and hardware module is being used to encode/decode 2911 //! the video data, on a per-frame basis. It also configures the hardware 2912 //! pipeline according to the active encoder/decoder operating mode for 2913 //! encoding/decoding the current picture. 2914 //! 2915 struct VDENC_PIPE_MODE_SELECT_CMD 2916 { 2917 union 2918 { 2919 //!< DWORD 0 2920 struct 2921 { 2922 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2923 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2924 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2925 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2926 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2927 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2928 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2929 }; 2930 uint32_t Value; 2931 } DW0; 2932 union 2933 { 2934 //!< DWORD 1 2935 struct 2936 { 2937 uint32_t StandardSelect : __CODEGEN_BITFIELD( 0, 3) ; //!< STANDARD_SELECT 2938 uint32_t ScalabilityMode : __CODEGEN_BITFIELD( 4, 4) ; //!< Scalability Mode 2939 uint32_t FrameStatisticsStreamOutEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< FRAME_STATISTICS_STREAM_OUT_ENABLE 2940 uint32_t VdencPakObjCmdStreamOutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< VDEnc PAK_OBJ_CMD Stream-Out Enable 2941 uint32_t TlbPrefetchEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< TLB_PREFETCH_ENABLE 2942 uint32_t PakThresholdCheckEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< PAK_THRESHOLD_CHECK_ENABLE 2943 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< VDENC_STREAM_IN_ENABLE 2944 uint32_t Downscaled8XWriteDisable : __CODEGEN_BITFIELD(10, 10) ; //!< DownScaled 8x write Disable 2945 uint32_t Downscaled4XWriteDisable : __CODEGEN_BITFIELD(11, 11) ; //!< DownScaled 4x write Disable 2946 uint32_t BitDepth : __CODEGEN_BITFIELD(12, 14) ; //!< BIT_DEPTH 2947 uint32_t PakChromaSubSamplingType : __CODEGEN_BITFIELD(15, 16) ; //!< PAK_CHROMA_SUB_SAMPLING_TYPE 2948 uint32_t OutputRangeControlAfterColorSpaceConversion : __CODEGEN_BITFIELD(17, 17) ; //!< output range control after color space conversion 2949 uint32_t IsRandomAccess : __CODEGEN_BITFIELD(18, 18) ; //!< Is random access B frame or not 2950 uint32_t Reserved50 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 2951 uint32_t RgbEncodingEnable : __CODEGEN_BITFIELD(20, 20) ; //!< RGB encoding enable 2952 uint32_t PrimaryChannelSelectionForRgbEncoding : __CODEGEN_BITFIELD(21, 22) ; //!< PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 2953 uint32_t FirstSecondaryChannelSelectionForRgbEncoding : __CODEGEN_BITFIELD(23, 24) ; //!< FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 2954 uint32_t TileReplayEnable : __CODEGEN_BITFIELD(25, 25) ; //!< Tile replay enable 2955 uint32_t StreamingBufferConfig : __CODEGEN_BITFIELD(26, 27) ; //!< Streaming buffer config 2956 uint32_t Reserved58 : __CODEGEN_BITFIELD(28, 30) ; //!< Reserved 2957 uint32_t DisableSpeedModeFetchOptimization : __CODEGEN_BITFIELD(31, 31) ; //!< Disable Speed Mode fetch optimization 2958 }; 2959 uint32_t Value; 2960 } DW1; 2961 union 2962 { 2963 //!< DWORD 2 2964 struct 2965 { 2966 uint32_t HmeRegionPreFetchenable : __CODEGEN_BITFIELD( 0, 0) ; //!< HME_REGION_PRE_FETCHENABLE 2967 uint32_t Topprefetchenablemode : __CODEGEN_BITFIELD( 1, 2) ; //!< TOPPREFETCHENABLEMODE 2968 uint32_t LeftpreFetchatwraparound : __CODEGEN_BITFIELD( 3, 3) ; //!< LEFTPRE_FETCHATWRAPAROUND 2969 uint32_t Verticalshift32Minus1 : __CODEGEN_BITFIELD( 4, 7) ; //!< VERTICALSHIFT32MINUS1 2970 uint32_t Hzshift32Minus1 : __CODEGEN_BITFIELD( 8, 11) ; //!< HZSHIFT32MINUS1 2971 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2972 uint32_t NumVerticalReqMinus1 : __CODEGEN_BITFIELD(16, 19) ; //!< NUMVERTICALREQMINUS1 2973 uint32_t Numhzreqminus1 : __CODEGEN_BITFIELD(20, 23) ; //!< NUMHZREQMINUS1 2974 uint32_t PreFetchOffsetForReferenceIn16PixelIncrement : __CODEGEN_BITFIELD(24, 27) ; //!< PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT 2975 uint32_t Reserved92 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2976 }; 2977 uint32_t Value; 2978 } DW2; 2979 union 2980 { 2981 //!< DWORD 3 2982 struct 2983 { 2984 uint32_t SourceLumaPackedDataTlbPreFetchenable : __CODEGEN_BITFIELD( 0, 0) ; //!< SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 2985 uint32_t SourceChromaTlbPreFetchenable : __CODEGEN_BITFIELD( 1, 1) ; //!< SOURCE_CHROMA_TLB_PRE_FETCHENABLE 2986 uint32_t Reserved98 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 2987 uint32_t Verticalshift32Minus1Src : __CODEGEN_BITFIELD( 4, 7) ; //!< VERTICALSHIFT32MINUS1SRC 2988 uint32_t Hzshift32Minus1Src : __CODEGEN_BITFIELD( 8, 11) ; //!< HZSHIFT32MINUS1SRC 2989 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2990 uint32_t Numverticalreqminus1Src : __CODEGEN_BITFIELD(16, 19) ; //!< NUMVERTICALREQMINUS1SRC 2991 uint32_t Numhzreqminus1Src : __CODEGEN_BITFIELD(20, 23) ; //!< NUMHZREQMINUS1SRC 2992 uint32_t PreFetchoffsetforsource : __CODEGEN_BITFIELD(24, 27) ; //!< PRE_FETCHOFFSETFORSOURCE 2993 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2994 }; 2995 uint32_t Value; 2996 } DW3; 2997 union 2998 { 2999 struct 3000 { 3001 uint32_t Debugtilepassnum : __CODEGEN_BITFIELD( 0, 3) ; //!< DebugTilePassNum 3002 uint32_t Debugtilenum : __CODEGEN_BITFIELD( 4, 11) ; //!< DebugTileNum 3003 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 3004 }; 3005 uint32_t Value; 3006 } DW4; 3007 union 3008 { 3009 struct 3010 { 3011 uint32_t FrameNumber : __CODEGEN_BITFIELD( 0, 3) ; //!< Frame Number 3012 uint32_t Reserved164 : __CODEGEN_BITFIELD( 4, 9) ; //!< Reserved 3013 uint32_t HeadPointerUpdateAuto : __CODEGEN_BITFIELD(10, 10) ; //!< Head Pointer Update Auto 3014 uint32_t CaptureMode : __CODEGEN_BITFIELD(11, 12) ; //!< CAPTURE_MODE 3015 uint32_t ParallelCaptureAndEncodeSessionId : __CODEGEN_BITFIELD(13, 15) ; //!< PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID 3016 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 3017 uint32_t TailPointerReadFrequency : __CODEGEN_BITFIELD(24, 31) ; //!< Tail pointer read frequency 3018 }; 3019 uint32_t Value; 3020 } DW5; 3021 3022 //! \name Local enumerations 3023 3024 enum SUBOPB 3025 { 3026 SUBOPB_VDENCPIPEMODESELECT = 0, //!< No additional details 3027 }; 3028 3029 enum SUBOPA 3030 { 3031 SUBOPA_UNNAMED0 = 0, //!< No additional details 3032 }; 3033 3034 enum OPCODE 3035 { 3036 OPCODE_VDENCPIPE = 1, //!< No additional details 3037 }; 3038 3039 enum PIPELINE 3040 { 3041 PIPELINE_MFXCOMMON = 2, //!< No additional details 3042 }; 3043 3044 enum COMMAND_TYPE 3045 { 3046 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3047 }; 3048 3049 enum STANDARD_SELECT 3050 { 3051 STANDARD_SELECT_AVC = 2, //!< No additional details 3052 }; 3053 3054 //! \brief FRAME_STATISTICS_STREAM_OUT_ENABLE 3055 //! \details 3056 //! This field controls whether the frame statistics stream-out is enabled. 3057 enum FRAME_STATISTICS_STREAM_OUT_ENABLE 3058 { 3059 FRAME_STATISTICS_STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 3060 FRAME_STATISTICS_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 3061 }; 3062 3063 //! \brief TLB_PREFETCH_ENABLE 3064 //! \details 3065 //! This field controls whether TLB prefetching is enabled. 3066 enum TLB_PREFETCH_ENABLE 3067 { 3068 TLB_PREFETCH_ENABLE_DISABLE = 0, //!< No additional details 3069 TLB_PREFETCH_ENABLE_ENABLE = 1, //!< No additional details 3070 }; 3071 3072 //! \brief PAK_THRESHOLD_CHECK_ENABLE 3073 //! \details 3074 //! For AVC standard: This field controls whether VDEnc will check the 3075 //! PAK indicator for bits overflow and terminates the slice. This mode is 3076 //! called Dynamic Slice Mode. When this field is disabled, VDEnc is in 3077 //! Static Slice Mode. It uses the driver programmed Slice Macroblock Height 3078 //! Minus One to terminate the slice. This feature is also referred to as 3079 //! slice size conformance. 3080 //! For HEVC standard: This bit is used to enable dynamic slice size 3081 //! control. 3082 enum PAK_THRESHOLD_CHECK_ENABLE 3083 { 3084 PAK_THRESHOLD_CHECK_ENABLE_DISABLESTATICSLICEMODE = 0, //!< No additional details 3085 PAK_THRESHOLD_CHECK_ENABLE_ENABLEDYNAMICSLICEMODE = 1, //!< No additional details 3086 }; 3087 3088 //! \brief VDENC_STREAM_IN_ENABLE 3089 //! \details 3090 //! This field controls whether VDEnc will read the stream-in surface 3091 //! that is programmed. Currently the stream-in surface has MB level QP, 3092 //! ROI, predictors and MaxSize/TargetSizeinWordsMB parameters. The 3093 //! individual enables for each of the fields is programmed in the 3094 //! VDENC_IMG_STATE. 3095 //! (ROI_Enable, Fwd/Predictor0 MV Enable, Bwd/Predictor1 MV Enable, MB 3096 //! Level QP Enable, TargetSizeinWordsMB/MaxSizeinWordsMB Enable). 3097 //! This bit is valid only in AVC mode. In HEVC / VP9 mode this bit is 3098 //! reserved and should be set to zero. 3099 enum VDENC_STREAM_IN_ENABLE 3100 { 3101 VDENC_STREAM_IN_ENABLE_DISABLE = 0, //!< No additional details 3102 VDENC_STREAM_IN_ENABLE_ENABLE = 1, //!< No additional details 3103 }; 3104 3105 //! \brief BIT_DEPTH 3106 //! \details 3107 //! This parameter indicates the PAK bit depth. The valid values for this 3108 //! are 0 / 2 in HEVC / VP9 standard. In AVC standard this field should be 3109 //! set to 0. 3110 enum BIT_DEPTH 3111 { 3112 BIT_DEPTH_8BIT = 0, //!< No additional details 3113 BIT_DEPTH_10BIT = 2, //!< No additional details 3114 BIT_DEPTH_12BIT = 3, //!< No additional details 3115 }; 3116 3117 //! \brief PAK_CHROMA_SUB_SAMPLING_TYPE 3118 //! \details 3119 //! This field is applicable only in HEVC and VP9. In AVC, this field is ignored. 3120 enum PAK_CHROMA_SUB_SAMPLING_TYPE 3121 { 3122 PAK_CHROMA_SUB_SAMPLING_TYPE_420 = 1, //!< Used for Main8 and Main10 HEVC, VP9 profile0, AVC. 3123 PAK_CHROMA_SUB_SAMPLING_TYPE_4_4_4 = 3, //!< HEVC RExt 444, VP9 444 profiles. 3124 }; 3125 3126 //! \brief PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3127 //! \details 3128 //! In RGB encoding, any one of the channel could be primary. This field is 3129 //! used for selcting primary channel 3130 enum PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3131 { 3132 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED0 = 0, //!< Channel R is primary channel 3133 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED1 = 1, //!< Channel G is primary channel. 3134 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED2 = 2, //!< Channel B is primary channel 3135 }; 3136 3137 //! \brief FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3138 //! \details 3139 //! In RGB encoding, any one of the channel could be primary. This field is 3140 //! used for selcting primary channel 3141 enum FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3142 { 3143 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED0 = 0, //!< Channel R is first secondary channel 3144 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED1 = 1, //!< Channel G is first secondary channel 3145 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED2 = 2, //!< Channel B is first secondary channel. 3146 }; 3147 3148 //! \brief HME_REGION_PRE_FETCHENABLE 3149 //! \details 3150 //! When this bit is set, for all reference frames HME region pages are pre-fetched. 3151 enum HME_REGION_PRE_FETCHENABLE 3152 { 3153 HME_REGION_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 3154 HME_REGION_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 3155 }; 3156 3157 //! \brief TOPPREFETCHENABLEMODE 3158 //! \details 3159 //! Top Pre-fetch enable Mode 3160 enum TOPPREFETCHENABLEMODE 3161 { 3162 TOPPREFETCHENABLEMODE_UNNAMED1 = 1, //!< No additional details 3163 }; 3164 3165 //! \brief LEFTPRE_FETCHATWRAPAROUND 3166 //! \details 3167 //! Left pre-fetch enabled on wraparound 3168 enum LEFTPRE_FETCHATWRAPAROUND 3169 { 3170 LEFTPRE_FETCHATWRAPAROUND_UNNAMED1 = 1, //!< No additional details 3171 }; 3172 3173 enum VERTICALSHIFT32MINUS1 3174 { 3175 VERTICALSHIFT32MINUS1_UNNAMED0 = 0, //!< No additional details 3176 }; 3177 3178 //! \brief HZSHIFT32MINUS1 3179 //! \details 3180 //! Horizontal_shift >= LCU_size and Horizontal_shift prefetch_offset 3181 enum HZSHIFT32MINUS1 3182 { 3183 HZSHIFT32MINUS1_UNNAMED3 = 3, //!< No additional details 3184 }; 3185 3186 //! \brief NUMHZREQMINUS1 3187 //! \details 3188 //! Number of Vertical requests in each region for a constant horizontal position. 3189 enum NUMVERTICALREQMINUS1 3190 { 3191 NUMVERTICALREQMINUS1_UNNAMED11 = 11, //!< No additional details 3192 }; 3193 3194 //! \brief NUMHZREQMINUS1 3195 //! \details 3196 //! Number of Horizontal Requests minus 1 at row begining. 3197 enum NUMHZREQMINUS1 3198 { 3199 NUMHZREQMINUS1_UNNAMED2 = 2, //!< No additional details 3200 }; 3201 3202 enum PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT 3203 { 3204 PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT_UNNAMED0 = 0, //!< No additional details 3205 }; 3206 3207 //! \brief SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 3208 //! \details 3209 //! When this bit is set, Souce Luma / Packed data TLB pre-fetches are 3210 //! performed. 3211 enum SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 3212 { 3213 SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 3214 SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 3215 }; 3216 3217 //! \brief SOURCE_CHROMA_TLB_PRE_FETCHENABLE 3218 //! \details 3219 //! When this bit is set, Souce Chroma TLB pre-fetches are performed. 3220 enum SOURCE_CHROMA_TLB_PRE_FETCHENABLE 3221 { 3222 SOURCE_CHROMA_TLB_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 3223 SOURCE_CHROMA_TLB_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 3224 }; 3225 3226 enum VERTICALSHIFT32MINUS1SRC 3227 { 3228 VERTICALSHIFT32MINUS1SRC_UNNAMED0 = 0, //!< No additional details 3229 }; 3230 3231 //! \brief HZSHIFT32MINUS1SRC 3232 //! \details 3233 //! Horizontal_shift >= LCU_size and Horizontal_shift prefetch_offset 3234 enum HZSHIFT32MINUS1SRC 3235 { 3236 HZSHIFT32MINUS1SRC_UNNAMED3 = 3, //!< No additional details 3237 }; 3238 3239 //! \brief NUMVERTICALREQMINUS1SRC 3240 //! \details 3241 //! Number of Horizontal requests Minus 1 for source 3242 enum NUMVERTICALREQMINUS1SRC 3243 { 3244 NUMVERTICALREQMINUS1SRC_UNNAMED0 = 0, //!< This is the valid for AVC 3245 NUMVERTICALREQMINUS1SRC_UNNAMED1 = 1, //!< This is the valid value for HEVC 3246 }; 3247 3248 //! \brief NUMHZREQMINUS1SRC 3249 //! \details 3250 //! Number of Horizontal requests Minus 1 for source 3251 enum NUMHZREQMINUS1SRC 3252 { 3253 NUMHZREQMINUS1SRC_UNNAMED0 = 0, //!< No additional details 3254 }; 3255 3256 //! \brief PRE_FETCHOFFSETFORSOURCE 3257 //! \details 3258 //! Pre-fetch offset for Reference in 16 pixel increment. 3259 enum PRE_FETCHOFFSETFORSOURCE 3260 { 3261 PRE_FETCHOFFSETFORSOURCE_UNNAMED_4 = 4, //!< This value is applicable in HEVC mode 3262 PRE_FETCHOFFSETFORSOURCE_UNNAMED7 = 7, //!< This Value is applicable in AVC mode 3263 }; 3264 3265 enum CAPTURE_MODE 3266 { 3267 CAPTURE_MODE_UNNAMED0 = 0, //!< No Parallel capture 3268 CAPTURE_MODE_UNNAMED1 = 1, //!< Parallel encode from Display overlay 3269 CAPTURE_MODE_CAMERA = 2, //!< Parallel encode from Camera Pipe 3270 CAPTURE_MODE_UNNAMED3 = 3, //!< Reserved 3271 }; 3272 3273 enum STREAMING_BUFFER_CONFIG 3274 { 3275 STREAMING_BUFFER_UNSUPPORTED = 0, 3276 STREAMING_BUFFER_64 = 1, 3277 STREAMING_BUFFER_128 = 2, 3278 STREAMING_BUFFER_256 = 3, 3279 }; 3280 3281 enum PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID 3282 { 3283 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED0 = 0, //!< Display tailpointer address location 00ED0h-00ED3h 3284 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED1 = 1, //!< Display tailpointer address location 00ED4h-00ED7h 3285 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED2 = 2, //!< Display tailpointer address location 00ED8h-00EDBh 3286 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED3 = 3, //!< Display tailpointer address location 00EDCh-00EDFh 3287 }; 3288 3289 //! \name Initializations 3290 3291 //! \brief Explicit member initialization function 3292 VDENC_PIPE_MODE_SELECT_CMD(); 3293 3294 static const size_t dwSize = 6; 3295 static const size_t byteSize = 24; 3296 }; 3297 3298 //! 3299 //! \brief VDENC_REF_SURFACE_STATE 3300 //! \details 3301 //! This command specifies the surface state parameters for the normal 3302 //! reference surfaces. 3303 //! 3304 struct VDENC_REF_SURFACE_STATE_CMD 3305 { 3306 union 3307 { 3308 //!< DWORD 0 3309 struct 3310 { 3311 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3312 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3313 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3314 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3315 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3316 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3317 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3318 }; 3319 uint32_t Value; 3320 } DW0; 3321 union 3322 { 3323 //!< DWORD 1 3324 struct 3325 { 3326 uint32_t SurfaceId : __CODEGEN_BITFIELD(0, 2) ; //!< Surface ID 3327 uint32_t Reserved : __CODEGEN_BITFIELD(3, 31) ; //!< Reserved 3328 }; 3329 uint32_t Value; 3330 } DW1; 3331 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 3332 3333 //! \name Local enumerations 3334 3335 enum SUBOPB 3336 { 3337 SUBOPB_VDENCREFSURFACESTATE = 2, //!< No additional details 3338 }; 3339 3340 enum SUBOPA 3341 { 3342 SUBOPA_UNNAMED0 = 0, //!< No additional details 3343 }; 3344 3345 enum OPCODE 3346 { 3347 OPCODE_VDENCPIPE = 1, //!< No additional details 3348 }; 3349 3350 enum PIPELINE 3351 { 3352 PIPELINE_MFXCOMMON = 2, //!< No additional details 3353 }; 3354 3355 enum COMMAND_TYPE 3356 { 3357 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3358 }; 3359 3360 //! \name Initializations 3361 3362 //! \brief Explicit member initialization function 3363 VDENC_REF_SURFACE_STATE_CMD(); 3364 3365 static const size_t dwSize = 6; 3366 static const size_t byteSize = 24; 3367 }; 3368 3369 //! 3370 //! \brief VDENC_SRC_SURFACE_STATE 3371 //! \details 3372 //! This command specifies the uncompressed original input picture to be 3373 //! encoded. The actual base address is defined in the 3374 //! VDENC_PIPE_BUF_ADDR_STATE. Pitch can be wider than the Picture Width in 3375 //! pixels and garbage will be there at the end of each line. The following 3376 //! describes all the different formats that are supported in WLV+ VDEnc: 3377 //! NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V offset is set to 3378 //! 0 (the only format supported for video codec); vertical UV offset is MB 3379 //! aligned; UV xoffsets = 0. 3380 //! This surface state here is identical to the Surface State for 3381 //! deinterlace and sample_8x8 messages described in the Shared Function 3382 //! Volume and Sampler Chapter. For non pixel data, such as row stores, DMV 3383 //! and streamin/out, a linear buffer is employed. For row stores, the H/W 3384 //! is designed to guarantee legal memory accesses (read and write). For the 3385 //! remaining cases, indirect object base address, indirect object address 3386 //! upper bound, object data start address (offset) and object data length 3387 //! are used to fully specified their corresponding buffer. This mechanism 3388 //! is chosen over the pixel surface type because of their variable record 3389 //! sizes. All row store surfaces are linear surface. Their addresses are 3390 //! programmed in VDEnc_Pipe_Buf_Base_State. 3391 //! 3392 struct VDENC_SRC_SURFACE_STATE_CMD 3393 { 3394 union 3395 { 3396 //!< DWORD 0 3397 struct 3398 { 3399 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3400 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3401 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3402 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3403 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3404 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3405 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3406 }; 3407 uint32_t Value; 3408 } DW0; 3409 union 3410 { 3411 //!< DWORD 1 3412 struct 3413 { 3414 uint32_t Reserved32 ; //!< Reserved 3415 }; 3416 uint32_t Value; 3417 } DW1; 3418 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 3419 3420 //! \name Local enumerations 3421 3422 enum SUBOPB 3423 { 3424 SUBOPB_VDENCSRCSURFACESTATE = 1, //!< No additional details 3425 }; 3426 3427 enum SUBOPA 3428 { 3429 SUBOPA_UNNAMED0 = 0, //!< No additional details 3430 }; 3431 3432 enum OPCODE 3433 { 3434 OPCODE_VDENCPIPE = 1, //!< No additional details 3435 }; 3436 3437 enum PIPELINE 3438 { 3439 PIPELINE_MFXCOMMON = 2, //!< No additional details 3440 }; 3441 3442 enum COMMAND_TYPE 3443 { 3444 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3445 }; 3446 3447 //! \name Initializations 3448 3449 //! \brief Explicit member initialization function 3450 VDENC_SRC_SURFACE_STATE_CMD(); 3451 3452 static const size_t dwSize = 6; 3453 static const size_t byteSize = 24; 3454 }; 3455 3456 //! 3457 //! \brief VDENC_WALKER_STATE 3458 //! \details 3459 //! This command provides the macroblock start location for the VDEnc 3460 //! walker. Current programming to always have this command at the frame 3461 //! level, hence the macroblock X,Y location need to be programmed to 0,0 to 3462 //! always start at frame origin. Once the hardware receives this command 3463 //! packet, it internally starts the VDEnc pipeline. This should be the last 3464 //! command that is programmed for the VDEnc pipeline. 3465 //! 3466 //! This command is programmed per super-slice. The X location always needs 3467 //! to be programmed to 0. The Y location needs to be programmed to the 3468 //! starting point of the current super-slice. The programming needs to 3469 //! ensure that all super-slices are contiguous. It is illegal to have gaps 3470 //! between the super-slices. 3471 //! 3472 struct VDENC_WALKER_STATE_CMD 3473 { 3474 union 3475 { 3476 //!< DWORD 0 3477 struct 3478 { 3479 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3480 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3481 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3482 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3483 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3484 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3485 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3486 }; 3487 uint32_t Value; 3488 } DW0; 3489 union 3490 { 3491 //!< DWORD 1 3492 struct 3493 { 3494 uint32_t MbLcuStartYPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< MB/LCU Start Y Position 3495 uint32_t Reserved41 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 3496 uint32_t MbLcuStartXPosition : __CODEGEN_BITFIELD(16, 24) ; //!< MB/LCU Start X Position 3497 uint32_t Reserved57 : __CODEGEN_BITFIELD(25, 27) ; //!< Reserved 3498 uint32_t FirstSuperSlice : __CODEGEN_BITFIELD(28, 28) ; //!< First Super Slice 3499 uint32_t Reserved61 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3500 }; 3501 uint32_t Value; 3502 } DW1; 3503 union 3504 { 3505 //!< DWORD 2 3506 struct 3507 { 3508 uint32_t NextsliceMbStartYPosition : __CODEGEN_BITFIELD( 0, 9) ; //!< NextSlice MB Start Y Position 3509 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 3510 uint32_t NextsliceMbLcuStartXPosition : __CODEGEN_BITFIELD(16, 25) ; //!< NextSlice MB/LCU Start X Position 3511 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 3512 }; 3513 uint32_t Value; 3514 } DW2; 3515 union 3516 { 3517 //!< DWORD 3 3518 struct 3519 { 3520 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD( 0, 2) ; //!< Log 2 Weight Denom Luma 3521 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 3522 uint32_t HevcLog2WeightDemonLuma : __CODEGEN_BITFIELD( 4, 6) ; //!< HevcLog2WeightDemonLuma 3523 uint32_t Reserved78 : __CODEGEN_BITFIELD( 7, 8) ; //!< Reserved 3524 uint32_t NumParEngine : __CODEGEN_BITFIELD( 9, 10) ; //!< NUM_PAR_ENGINE 3525 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 3526 uint32_t TileRowStoreSelect : __CODEGEN_BITFIELD(16, 16) ; //!< TileRowStoreSelect 3527 uint32_t Reserved108 : __CODEGEN_BITFIELD(17, 23) ; //!< Reserved 3528 uint32_t TileNumber : __CODEGEN_BITFIELD(24, 31) ; //!< Tile number 3529 }; 3530 uint32_t Value; 3531 } DW3; 3532 union 3533 { 3534 //!< DWORD 4 3535 struct 3536 { 3537 uint32_t TileStartCtbY : __CODEGEN_BITFIELD( 0, 15) ; //!< Tile Start CTB-Y 3538 uint32_t TileStartCtbX : __CODEGEN_BITFIELD(16, 31) ; //!< Tile Start CTB-X 3539 }; 3540 uint32_t Value; 3541 } DW4; 3542 union 3543 { 3544 //!< DWORD 5 3545 struct 3546 { 3547 uint32_t TileWidth : __CODEGEN_BITFIELD( 0, 15) ; //!< Tile Width 3548 uint32_t TileHeight : __CODEGEN_BITFIELD(16, 31) ; //!< Tile Height 3549 }; 3550 uint32_t Value; 3551 } DW5; 3552 union 3553 { 3554 //!< DWORD 6 3555 struct 3556 { 3557 uint32_t StreaminOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Streamin Offset enable 3558 uint32_t Reserved193 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3559 uint32_t TileStreaminOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Streamin Offset 3560 }; 3561 uint32_t Value; 3562 } DW6; 3563 union 3564 { 3565 //!< DWORD 7 3566 struct 3567 { 3568 uint32_t RowStoreOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Row store Offset enable 3569 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3570 uint32_t TileRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Rowstore Offset 3571 }; 3572 uint32_t Value; 3573 } DW7; 3574 union 3575 { 3576 //!< DWORD 8 3577 struct 3578 { 3579 uint32_t TileStreamoutOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Tile streamout offset enable 3580 uint32_t Reserved257 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3581 uint32_t TileStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile streamout offset 3582 }; 3583 uint32_t Value; 3584 } DW8; 3585 union 3586 { 3587 //!< DWORD 9 3588 struct 3589 { 3590 uint32_t LcuStreamOutOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< LCU stream out offset enable 3591 uint32_t Reserved289 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3592 uint32_t TileLcuStreamOutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile LCU stream out offset 3593 }; 3594 uint32_t Value; 3595 } DW9; 3596 uint32_t DW_Reserved_10_15[6] = {0}; //!< Reserved 3597 union 3598 { 3599 //!< DWORD 16 3600 struct 3601 { 3602 uint32_t Reserved518 : __CODEGEN_BITFIELD( 0, 23) ; //!< Reserved 3603 uint32_t AdaptiveChannelThreshold : __CODEGEN_BITFIELD(24, 28) ; //!< Adaptive Channel Threshold 3604 uint32_t Reserved520 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3605 }; 3606 uint32_t Value; 3607 } DW16; 3608 uint32_t DW_Reserved_17_26[10] = {0}; //!< Reserved 3609 3610 //! \name Local enumerations 3611 3612 enum SUBOPB 3613 { 3614 SUBOPB_VDENCWALKERSTATE = 7, //!< No additional details 3615 }; 3616 3617 enum SUBOPA 3618 { 3619 SUBOPA_UNNAMED0 = 0, //!< No additional details 3620 }; 3621 3622 enum OPCODE 3623 { 3624 OPCODE_VDENCPIPE = 1, //!< No additional details 3625 }; 3626 3627 enum PIPELINE 3628 { 3629 PIPELINE_MFXCOMMON = 2, //!< No additional details 3630 }; 3631 3632 enum COMMAND_TYPE 3633 { 3634 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3635 }; 3636 3637 //! \name Initializations 3638 3639 //! \brief Explicit member initialization function 3640 VDENC_WALKER_STATE_CMD(); 3641 3642 static const size_t dwSize = 27; 3643 static const size_t byteSize = 108; 3644 }; 3645 3646 //! 3647 //! \brief VDENC_CONTROL_STATE 3648 //! \details 3649 //! 3650 //! 3651 struct VDENC_CONTROL_STATE_CMD 3652 { 3653 union 3654 { 3655 //!< DWORD 0 3656 struct 3657 { 3658 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Dword Length 3659 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3660 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< Media Instruction Command 3661 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< Media Instruction Opcode 3662 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< Pipeline Type 3663 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< Command Type 3664 }; 3665 uint32_t Value; 3666 } DW0; 3667 union 3668 { 3669 //!< DWORD 1 3670 struct 3671 { 3672 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3673 uint32_t VdencInitialization : __CODEGEN_BITFIELD( 1, 1) ; //!< VDenc Initialization 3674 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 3675 }; 3676 uint32_t Value; 3677 } DW1; 3678 3679 //! \name Local enumerations 3680 3681 //! \name Initializations 3682 3683 //! \brief Explicit member initialization function 3684 VDENC_CONTROL_STATE_CMD(); 3685 3686 static const size_t dwSize = 2; 3687 static const size_t byteSize = 8; 3688 }; 3689 3690 //! 3691 //! \brief VDENC_CMD1_CMD 3692 //! \details 3693 //! 3694 //! 3695 struct VDENC_CMD1_CMD 3696 { 3697 union 3698 { 3699 //!< DWORD 0 3700 struct 3701 { 3702 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWord Length 3703 uint32_t Reserved13 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3704 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3705 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3706 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3707 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3708 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3709 }; 3710 uint32_t Value; 3711 } DW0; 3712 union 3713 { 3714 //!< DWORD 1 3715 struct 3716 { 3717 uint32_t Reserved30 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3718 }; 3719 uint32_t Value; 3720 } DW1; 3721 union 3722 { 3723 //!< DWORD 2 3724 struct 3725 { 3726 uint32_t Reserved42 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3727 }; 3728 uint32_t Value; 3729 } DW2; 3730 union 3731 { 3732 //!< DWORD 3 3733 struct 3734 { 3735 uint32_t Reserved54 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3736 }; 3737 uint32_t Value; 3738 } DW3; 3739 union 3740 { 3741 //!< DWORD 4 3742 struct 3743 { 3744 uint32_t Reserved66 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3745 }; 3746 uint32_t Value; 3747 } DW4; 3748 union 3749 { 3750 //!< DWORD 5 3751 struct 3752 { 3753 uint32_t Reserved78 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3754 }; 3755 uint32_t Value; 3756 } DW5; 3757 union 3758 { 3759 //!< DWORD 6 3760 struct 3761 { 3762 uint32_t Reserved90 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3763 }; 3764 uint32_t Value; 3765 } DW6; 3766 union 3767 { 3768 //!< DWORD 7 3769 struct 3770 { 3771 uint32_t Reserved102 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3772 }; 3773 uint32_t Value; 3774 } DW7; 3775 union 3776 { 3777 //!< DWORD 8 3778 struct 3779 { 3780 uint32_t Reserved114 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3781 }; 3782 uint32_t Value; 3783 } DW8; 3784 union 3785 { 3786 //!< DWORD 9 3787 struct 3788 { 3789 uint32_t Reserved126 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3790 }; 3791 uint32_t Value; 3792 } DW9; 3793 union 3794 { 3795 //!< DWORD 10 3796 struct 3797 { 3798 uint32_t Reserved138 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3799 }; 3800 uint32_t Value; 3801 } DW10; 3802 union 3803 { 3804 //!< DWORD 11 3805 struct 3806 { 3807 uint32_t Reserved150 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3808 }; 3809 uint32_t Value; 3810 } DW11; 3811 union 3812 { 3813 //!< DWORD 12 3814 struct 3815 { 3816 uint32_t Reserved162 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3817 }; 3818 uint32_t Value; 3819 } DW12; 3820 union 3821 { 3822 //!< DWORD 13 3823 struct 3824 { 3825 uint32_t Reserved174 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3826 }; 3827 uint32_t Value; 3828 } DW13; 3829 union 3830 { 3831 //!< DWORD 14 3832 struct 3833 { 3834 uint32_t Reserved184 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3835 }; 3836 uint32_t Value; 3837 } DW14; 3838 union 3839 { 3840 //!< DWORD 15 3841 struct 3842 { 3843 uint32_t Reserved198 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3844 }; 3845 uint32_t Value; 3846 } DW15; 3847 union 3848 { 3849 //!< DWORD 16 3850 struct 3851 { 3852 uint32_t Reserved210 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3853 }; 3854 uint32_t Value; 3855 } DW16; 3856 union 3857 { 3858 //!< DWORD 17 3859 struct 3860 { 3861 uint32_t Reserved222 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3862 }; 3863 uint32_t Value; 3864 } DW17; 3865 union 3866 { 3867 //!< DWORD 18 3868 struct 3869 { 3870 uint32_t Reserved231 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3871 }; 3872 uint32_t Value; 3873 } DW18; 3874 union 3875 { 3876 //!< DWORD 19 3877 struct 3878 { 3879 uint32_t Reserved246 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3880 }; 3881 uint32_t Value; 3882 } DW19; 3883 union 3884 { 3885 //!< DWORD 20 3886 struct 3887 { 3888 uint32_t Reserved258 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3889 }; 3890 uint32_t Value; 3891 } DW20; 3892 union 3893 { 3894 //!< DWORD 21 3895 struct 3896 { 3897 uint32_t Reserved270 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3898 }; 3899 uint32_t Value; 3900 } DW21; 3901 union 3902 { 3903 //!< DWORD 22 3904 struct 3905 { 3906 uint32_t Reserved282 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3907 }; 3908 uint32_t Value; 3909 } DW22; 3910 union 3911 { 3912 //!< DWORD 23 3913 struct 3914 { 3915 uint32_t Reserved294 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3916 }; 3917 uint32_t Value; 3918 } DW23; 3919 union 3920 { 3921 //!< DWORD 24 3922 struct 3923 { 3924 uint32_t Reserved306 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3925 }; 3926 uint32_t Value; 3927 } DW24; 3928 union 3929 { 3930 //!< DWORD 25 3931 struct 3932 { 3933 uint32_t Reserved318 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3934 }; 3935 uint32_t Value; 3936 } DW25; 3937 union 3938 { 3939 //!< DWORD 26 3940 struct 3941 { 3942 uint32_t Reserved330 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3943 }; 3944 uint32_t Value; 3945 } DW26; 3946 union 3947 { 3948 //!< DWORD 27 3949 struct 3950 { 3951 uint32_t Reserved342 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3952 }; 3953 uint32_t Value; 3954 } DW27; 3955 union 3956 { 3957 //!< DWORD 28 3958 struct 3959 { 3960 uint32_t Reserved354 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3961 }; 3962 uint32_t Value; 3963 } DW28; 3964 union 3965 { 3966 //!< DWORD 29 3967 struct 3968 { 3969 uint32_t Reserved366 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3970 }; 3971 uint32_t Value; 3972 } DW29; 3973 union 3974 { 3975 //!< DWORD 30 3976 struct 3977 { 3978 uint32_t Reserved378 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 3979 }; 3980 uint32_t Value; 3981 } DW30; 3982 3983 //! \name Local enumerations 3984 3985 enum SUBOPB 3986 { 3987 SUBOPB_VDENCCMD1CMD = 10, //!< No additional details 3988 }; 3989 3990 enum SUBOPA 3991 { 3992 SUBOPA_UNNAMED0 = 0, //!< No additional details 3993 }; 3994 3995 enum OPCODE 3996 { 3997 OPCODE_VDENCPIPE = 1, //!< No additional details 3998 }; 3999 4000 enum PIPELINE 4001 { 4002 PIPELINE_MFXCOMMON = 2, //!< No additional details 4003 }; 4004 4005 enum COMMAND_TYPE 4006 { 4007 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4008 }; 4009 4010 //! \name Initializations 4011 4012 //! \brief Explicit member initialization function 4013 VDENC_CMD1_CMD(); 4014 4015 static const size_t dwSize = 31; 4016 static const size_t byteSize = 124; 4017 }; 4018 4019 //! 4020 //! \brief VDENC_CMD2_STATE 4021 //! \details 4022 //! 4023 //! 4024 struct VDENC_CMD2_CMD 4025 { 4026 union 4027 { 4028 //!< DWORD 0 4029 struct 4030 { 4031 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWord Length 4032 uint32_t Reserved13 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4033 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 4034 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 4035 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 4036 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4037 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4038 }; 4039 uint32_t Value; 4040 } DW0; 4041 union 4042 { 4043 //!< DWORD 1 4044 struct 4045 { 4046 uint32_t FrameWidthInPixelsMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< FrameWidthInPixelsMinusOne 4047 uint32_t FrameHeightInPixelsMinusOne : __CODEGEN_BITFIELD(16, 31) ; //!< FrameHeightInPixelsMinusOne 4048 }; 4049 uint32_t Value; 4050 } DW1; 4051 union 4052 { 4053 //!< DWORD 2 4054 struct 4055 { 4056 uint32_t Reserved46 : __CODEGEN_BITFIELD( 0, 19) ; //!< Reserved 4057 uint32_t PictureType : __CODEGEN_BITFIELD(20, 21) ; //!< Picture Type 4058 uint32_t TemporalMvpEnableFlag : __CODEGEN_BITFIELD(22, 22) ; //!< TemporalMvpEnableFlag 4059 uint32_t Reserved49 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 4060 uint32_t LongTermReferenceFlagsL0 : __CODEGEN_BITFIELD(24, 26) ; //!< LongTermReferenceFlags_L0 4061 uint32_t LongTermReferenceFlagsL1 : __CODEGEN_BITFIELD(27, 27) ; //!< LongTermReferenceFlags_L1 4062 uint32_t Reserved53 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 4063 uint32_t TransformSkip : __CODEGEN_BITFIELD(30, 30) ; //!< TransformSkip 4064 uint32_t Reserved55 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 4065 }; 4066 uint32_t Value; 4067 } DW2; 4068 union 4069 { 4070 //!< DWORD 3 4071 struct 4072 { 4073 uint32_t PocNumberForRefid0InL0 : __CODEGEN_BITFIELD( 0, 7) ; //!< FWD_POC_NUMBER_FOR_REFID_0_IN_L0 4074 uint32_t PocNumberForRefid0InL1 : __CODEGEN_BITFIELD( 8, 15) ; //!< BWD_POC_NUMBER_FOR_REFID_0_IN_L1 4075 uint32_t PocNumberForRefid1InL0 : __CODEGEN_BITFIELD(16, 23) ; //!< POC_NUMBER_FOR_REFID_1_IN_L0 4076 uint32_t PocNumberForRefid1InL1 : __CODEGEN_BITFIELD(24, 31) ; //!< POC_NUMBER_FOR_REFID_1_IN_L1 4077 }; 4078 uint32_t Value; 4079 } DW3; 4080 union 4081 { 4082 //!< DWORD 4 4083 struct 4084 { 4085 uint32_t PocNumberForRefid2InL0 : __CODEGEN_BITFIELD( 0, 7) ; //!< FWD_POC_NUMBER_FOR_REFID_2_IN_L0 4086 uint32_t PocNumberForRefid2InL1 : __CODEGEN_BITFIELD( 8, 15) ; //!< BWD_POC_NUMBER_FOR_REFID_2_IN_L1 4087 uint32_t Reserved79 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4088 }; 4089 uint32_t Value; 4090 } DW4; 4091 union 4092 { 4093 //!< DWORD 5 4094 struct 4095 { 4096 uint32_t Reserved89 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 4097 uint32_t StreaminRoiEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< StreamIn ROI Enable 4098 uint32_t Reserved98 : __CODEGEN_BITFIELD( 9, 23) ; //!< Reserved 4099 uint32_t NumRefIdxL0Minus1 : __CODEGEN_BITFIELD(24, 27) ; //!< NumRefIdxL0_minus1 4100 uint32_t NumRefIdxL1Minus1 : __CODEGEN_BITFIELD(28, 31) ; //!< NumRefIdxL1_minus1 4101 }; 4102 uint32_t Value; 4103 } DW5; 4104 union 4105 { 4106 //!< DWORD 6 4107 struct 4108 { 4109 uint32_t Reserved112 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4110 }; 4111 uint32_t Value; 4112 } DW6; 4113 union 4114 { 4115 //!< DWORD 7 4116 struct 4117 { 4118 uint32_t Reserved121 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 4119 uint32_t SegmentationEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< Segmentation Enable 4120 uint32_t SegmentationMapTemporalPredictionEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< Segmentation map temporal prediction enable 4121 uint32_t Reserved124 : __CODEGEN_BITFIELD( 6, 6) ; //!< Reserved 4122 uint32_t TilingEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Tiling enable 4123 uint32_t Reserved126 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 4124 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< VDENC Stream IN 4125 uint32_t Reserved130 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 4126 uint32_t PakOnlyMultiPassEnable : __CODEGEN_BITFIELD(16, 16) ; //!< PAK-Only Multi-Pass Enable 4127 uint32_t Reserved139 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 4128 }; 4129 uint32_t Value; 4130 } DW7; 4131 union 4132 { 4133 //!< DWORD 8 4134 struct 4135 { 4136 uint32_t Reserved155 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4137 }; 4138 uint32_t Value; 4139 } DW8; 4140 union 4141 { 4142 //!< DWORD 9 4143 struct 4144 { 4145 uint32_t Reserved170 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4146 }; 4147 uint32_t Value; 4148 } DW9; 4149 union 4150 { 4151 //!< DWORD 10 4152 struct 4153 { 4154 uint32_t Reserved182 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4155 }; 4156 uint32_t Value; 4157 } DW10; 4158 union 4159 { 4160 //!< DWORD 11 4161 struct 4162 { 4163 uint32_t Reserved199 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4164 }; 4165 uint32_t Value; 4166 } DW11; 4167 union 4168 { 4169 //!< DWORD 12 4170 struct 4171 { 4172 uint32_t Reserved209 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4173 }; 4174 uint32_t Value; 4175 } DW12; 4176 union 4177 { 4178 //!< DWORD 13 4179 struct 4180 { 4181 uint32_t Reserved218 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 4182 uint32_t RoiQpAdjustmentForZone1Stage3 : __CODEGEN_BITFIELD( 4, 7) ; //!< ROI QP adjustment for Zone1 (stage3) 4183 uint32_t RoiQpAdjustmentForZone2Stage3 : __CODEGEN_BITFIELD( 8, 11) ; //!< ROI QP adjustment for Zone2 (stage3) 4184 uint32_t RoiQpAdjustmentForZone3Stage3 : __CODEGEN_BITFIELD(12, 15) ; //!< ROI QP adjustment for Zone3 (stage3) 4185 uint32_t Reserved225 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4186 }; 4187 uint32_t Value; 4188 } DW13; 4189 union 4190 { 4191 //!< DWORD 14 4192 struct 4193 { 4194 uint32_t Reserved238 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4195 }; 4196 uint32_t Value; 4197 } DW14; 4198 union 4199 { 4200 //!< DWORD 15 4201 struct 4202 { 4203 uint32_t Reserved248 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4204 }; 4205 uint32_t Value; 4206 } DW15; 4207 union 4208 { 4209 //!< DWORD 16 4210 struct 4211 { 4212 uint32_t MinQp : __CODEGEN_BITFIELD( 0, 7) ; //!< MINQP 4213 uint32_t MaxQp : __CODEGEN_BITFIELD( 8, 15) ; //!< MAXQP 4214 uint32_t Reserved262 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4215 }; 4216 uint32_t Value; 4217 } DW16; 4218 union 4219 { 4220 //!< DWORD 17 4221 struct 4222 { 4223 uint32_t Reserved271 : __CODEGEN_BITFIELD( 0, 19) ; //!< Reserved 4224 uint32_t TemporalMVEnableForIntegerSearch : __CODEGEN_BITFIELD(20, 20) ; //!< Temporal MV disable for Integer Search 4225 uint32_t Reserved273 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 4226 }; 4227 uint32_t Value; 4228 } DW17; 4229 union 4230 { 4231 //!< DWORD 18 4232 struct 4233 { 4234 uint32_t Reserved286 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4235 }; 4236 uint32_t Value; 4237 } DW18; 4238 union 4239 { 4240 //!< DWORD 19 4241 struct 4242 { 4243 uint32_t Reserved298 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4244 }; 4245 uint32_t Value; 4246 } DW19; 4247 union 4248 { 4249 //!< DWORD 20 4250 struct 4251 { 4252 uint32_t Reserved312 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4253 }; 4254 uint32_t Value; 4255 } DW20; 4256 union 4257 { 4258 //!< DWORD 21 4259 struct 4260 { 4261 uint32_t IntraRefreshPos : __CODEGEN_BITFIELD( 0, 8) ; //!< IntraRefreshPos 4262 uint32_t Reserved322 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 4263 uint32_t IntraRefreshMBSizeMinusOne : __CODEGEN_BITFIELD(16, 23) ; //!< IntraRefreshMBSizeMinusOne 4264 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(24, 24) ; //!< IntraRefreshMode 4265 uint32_t Reserved326 : __CODEGEN_BITFIELD(25, 27) ; //!< Reserved 4266 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(28, 31) ; //!< QP_ADJUSTMENT_FOR_ROLLING_I 4267 }; 4268 uint32_t Value; 4269 } DW21; 4270 union 4271 { 4272 //!< DWORD 22 4273 struct 4274 { 4275 uint32_t Reserved343 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4276 }; 4277 uint32_t Value; 4278 } DW22; 4279 union 4280 { 4281 //!< DWORD 23 4282 struct 4283 { 4284 uint32_t Reserved357 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4285 }; 4286 uint32_t Value; 4287 } DW23; 4288 union 4289 { 4290 //!< DWORD 24 4291 struct 4292 { 4293 uint32_t QpForSeg0 : __CODEGEN_BITFIELD( 0, 7) ; //!< QP for Seg0 4294 uint32_t QpForSeg1 : __CODEGEN_BITFIELD( 8, 15) ; //!< QP for Seg1 4295 uint32_t QpForSeg2 : __CODEGEN_BITFIELD(16, 23) ; //!< QP for Seg2 4296 uint32_t QpForSeg3 : __CODEGEN_BITFIELD(24, 31) ; //!< QP for Seg3 4297 }; 4298 uint32_t Value; 4299 } DW24; 4300 union 4301 { 4302 //!< DWORD 25 4303 struct 4304 { 4305 uint32_t QpForSeg4 : __CODEGEN_BITFIELD( 0, 7) ; //!< QP for Seg4 4306 uint32_t QpForSeg5 : __CODEGEN_BITFIELD( 8, 15) ; //!< QP for Seg5 4307 uint32_t QpForSeg6 : __CODEGEN_BITFIELD(16, 23) ; //!< QP for Seg6 4308 uint32_t QpForSeg7 : __CODEGEN_BITFIELD(24, 31) ; //!< QP for Seg7 4309 }; 4310 uint32_t Value; 4311 } DW25; 4312 union 4313 { 4314 //!< DWORD 26 4315 struct 4316 { 4317 uint32_t RdQpLambda : __CODEGEN_BITFIELD( 0, 15) ; //!< RD QP Lambda 4318 uint32_t SadQpLambda : __CODEGEN_BITFIELD(16, 24) ; //!< SAD QP Lambda 4319 uint32_t Vp9DynamicSliceEnable : __CODEGEN_BITFIELD(25, 25) ; //!< VP9 Dynamic slice enable 4320 uint32_t Reserved394 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 4321 }; 4322 uint32_t Value; 4323 } DW26; 4324 union 4325 { 4326 //!< DWORD 27 4327 struct 4328 { 4329 uint32_t QpPrimeYDc : __CODEGEN_BITFIELD( 0, 7) ; //!< QPPRIMEY_DC 4330 uint32_t QpPrimeYAc : __CODEGEN_BITFIELD( 8, 15) ; //!< QPPRIMEY_AC 4331 uint32_t Reserved405 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4332 }; 4333 uint32_t Value; 4334 } DW27; 4335 union 4336 { 4337 //!< DWORD 28 4338 struct 4339 { 4340 uint32_t Reserved415 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4341 }; 4342 uint32_t Value; 4343 } DW28; 4344 union 4345 { 4346 //!< DWORD 29 4347 struct 4348 { 4349 uint32_t Reserved425 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4350 }; 4351 uint32_t Value; 4352 } DW29; 4353 union 4354 { 4355 //!< DWORD 30 4356 struct 4357 { 4358 uint32_t Reserved435 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4359 }; 4360 uint32_t Value; 4361 } DW30; 4362 union 4363 { 4364 //!< DWORD 31 4365 struct 4366 { 4367 uint32_t Reserved445 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4368 }; 4369 uint32_t Value; 4370 } DW31; 4371 union 4372 { 4373 //!< DWORD 32 4374 struct 4375 { 4376 uint32_t Reserved454 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4377 }; 4378 uint32_t Value; 4379 } DW32; 4380 union 4381 { 4382 //!< DWORD 33 4383 struct 4384 { 4385 uint32_t Reserved474 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4386 }; 4387 uint32_t Value; 4388 } DW33; 4389 union 4390 { 4391 //!< DWORD 34 4392 struct 4393 { 4394 uint32_t Reserved490 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4395 }; 4396 uint32_t Value; 4397 } DW34; 4398 union 4399 { 4400 //!< DWORD 35 4401 struct 4402 { 4403 uint32_t Reserved503 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4404 }; 4405 uint32_t Value; 4406 } DW35; 4407 union 4408 { 4409 //!< DWORD 36 4410 struct 4411 { 4412 uint32_t IntraRefreshBoundaryRef0 : __CODEGEN_BITFIELD( 0, 8) ; //!< IntraRefreshBoundary Ref0 4413 uint32_t Reserved513 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 4414 uint32_t IntraRefreshBoundaryRef1 : __CODEGEN_BITFIELD(10, 18) ; //!< IntraRefreshBoundary Ref1 4415 uint32_t Reserved515 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 4416 uint32_t IntraRefreshBoundaryRef2 : __CODEGEN_BITFIELD(20, 28) ; //!< IntraRefreshBoundary Ref2 4417 uint32_t Reserved517 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 4418 }; 4419 uint32_t Value; 4420 } DW36; 4421 union 4422 { 4423 //!< DWORD 37 4424 struct 4425 { 4426 uint32_t Reserved530 : __CODEGEN_BITFIELD( 0, 22) ; //!< Reserved 4427 uint32_t Reserved533 : __CODEGEN_BITFIELD(23, 26) ; //!< Reserved 4428 uint32_t TileReplayEnable : __CODEGEN_BITFIELD(27, 27) ; //!< Tile Replay enable 4429 uint32_t Reserved536 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 4430 }; 4431 uint32_t Value; 4432 } DW37; 4433 union 4434 { 4435 //!< DWORD 38 4436 struct 4437 { 4438 uint32_t Reserved551 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4439 }; 4440 uint32_t Value; 4441 } DW38; 4442 union 4443 { 4444 //!< DWORD 39 4445 struct 4446 { 4447 uint32_t Reserved561 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4448 }; 4449 uint32_t Value; 4450 } DW39; 4451 union 4452 { 4453 //!< DWORD 40 4454 struct 4455 { 4456 uint32_t Reserved571 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4457 }; 4458 uint32_t Value; 4459 } DW40; 4460 union 4461 { 4462 //!< DWORD 41 4463 struct 4464 { 4465 uint32_t Reserved581 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4466 }; 4467 uint32_t Value; 4468 } DW41; 4469 union 4470 { 4471 //!< DWORD 42 4472 struct 4473 { 4474 uint32_t Reserved591 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4475 }; 4476 uint32_t Value; 4477 } DW42; 4478 union 4479 { 4480 //!< DWORD 43 4481 struct 4482 { 4483 uint32_t Reserved601 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4484 }; 4485 uint32_t Value; 4486 } DW43; 4487 union 4488 { 4489 //!< DWORD 44 4490 struct 4491 { 4492 uint32_t Reserved611 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4493 }; 4494 uint32_t Value; 4495 } DW44; 4496 union 4497 { 4498 //!< DWORD 45 4499 struct 4500 { 4501 uint32_t Reserved621 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4502 }; 4503 uint32_t Value; 4504 } DW45; 4505 union 4506 { 4507 //!< DWORD 46 4508 struct 4509 { 4510 uint32_t Reserved631 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4511 }; 4512 uint32_t Value; 4513 } DW46; 4514 union 4515 { 4516 //!< DWORD 47 4517 struct 4518 { 4519 uint32_t Reserved641 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4520 }; 4521 uint32_t Value; 4522 } DW47; 4523 union 4524 { 4525 //!< DWORD 48 4526 struct 4527 { 4528 uint32_t Reserved651 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4529 }; 4530 uint32_t Value; 4531 } DW48; 4532 union 4533 { 4534 //!< DWORD 49 4535 struct 4536 { 4537 uint32_t Reserved661 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4538 }; 4539 uint32_t Value; 4540 } DW49; 4541 union 4542 { 4543 //!< DWORD 50 4544 struct 4545 { 4546 uint32_t Reserved671 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4547 }; 4548 uint32_t Value; 4549 } DW50; 4550 4551 4552 //! \name Local enumerations 4553 4554 enum SUBOPB 4555 { 4556 SUBOPB_VDENCCMD2CMD = 9, //!< No additional details 4557 }; 4558 4559 enum SUBOPA 4560 { 4561 SUBOPA_UNNAMED0 = 0, //!< No additional details 4562 }; 4563 4564 enum OPCODE 4565 { 4566 OPCODE_VDENCPIPE = 1, //!< No additional details 4567 }; 4568 4569 enum PIPELINE 4570 { 4571 PIPELINE_MFXCOMMON = 2, //!< No additional details 4572 }; 4573 4574 enum COMMAND_TYPE 4575 { 4576 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4577 }; 4578 4579 //! \brief Explicit member initialization function 4580 VDENC_CMD2_CMD(); 4581 4582 static const size_t dwSize = 51; 4583 static const size_t byteSize = 204; 4584 }; 4585 }; 4586 4587 #pragma pack() 4588 4589 #endif // __MHW_VDBOX_VDENC_HWCMD_G12_X_H__ 4590