1 /*
2 * Copyright (c) 2011-2017, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codechal_vdenc_avc_g9_skl.cpp
24 //! \brief This file implements the C++ class/interface for SKL's AVC
25 //! VDEnc encoding to be used CODECHAL components.
26 //!
27
28 #include "codechal_vdenc_avc_g9_skl.h"
29 #if USE_CODECHAL_DEBUG_TOOL
30 #include "mhw_vdbox_mfx_hwcmd_g9_skl.h"
31 #include "mhw_vdbox_vdenc_hwcmd_g9_skl.h"
32 #endif
33
34 typedef struct _CODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_SKL {
35 int nKernelCount;
36
37 // Quality mode for Frame/Field
38 CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_I;
39 CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_P;
40 CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_B;
41 // Normal mode for Frame/Field
42 CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_I;
43 CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_P;
44 CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_B;
45 // Performance modes for Frame/Field
46 CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_I;
47 CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_P;
48 CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_B;
49 // Modes for Frame/Field
50 CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_I;
51 CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_P;
52 CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_B;
53
54 // HME
55 CODECHAL_KERNEL_HEADER AVC_ME_P;
56 CODECHAL_KERNEL_HEADER AVC_ME_B;
57
58 // DownScaling
59 CODECHAL_KERNEL_HEADER PLY_DScale_PLY;
60 CODECHAL_KERNEL_HEADER PLY_DScale_2f_PLY_2f;
61
62 // BRC Init frame
63 CODECHAL_KERNEL_HEADER InitFrameBRC;
64
65 // FrameBRC Update
66 CODECHAL_KERNEL_HEADER FrameENCUpdate;
67
68 // BRC Reset frame
69 CODECHAL_KERNEL_HEADER BRC_ResetFrame;
70
71 // BRC I Frame Distortion
72 CODECHAL_KERNEL_HEADER BRC_IFrame_Dist;
73
74 // BRCBlockCopy
75 CODECHAL_KERNEL_HEADER BRCBlockCopy;
76
77 // MbBRC Update
78 CODECHAL_KERNEL_HEADER MbBRCUpdate;
79
80 // 2x DownScaling
81 CODECHAL_KERNEL_HEADER PLY_2xDScale_PLY;
82 CODECHAL_KERNEL_HEADER PLY_2xDScale_2f_PLY_2f;
83
84 //Motion estimation kernel for the VDENC StreamIN
85 CODECHAL_KERNEL_HEADER AVC_ME_VDENC;
86
87 //Weighted Prediction Kernel
88 CODECHAL_KERNEL_HEADER AVC_WeightedPrediction;
89
90 // Static frame detection Kernel
91 CODECHAL_KERNEL_HEADER AVC_StaticFrameDetection;
92 } CODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_SKL, *PCODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_SKL;
93
94 typedef struct _CODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_SKL
95 {
96 uint8_t BRCFunc_U8; // 0: Init; 2: Reset
97 uint8_t OpenSourceEnable_U8; // 0: disable opensource, 1: enable opensource
98 uint8_t RVSD[2];
99 uint16_t INIT_BRCFlag_U16; // ICQ or CQP with slice size control: 0x00 CBR: 0x10; VBR: 0x20; VCM: 0x40; LOWDELAY: 0x80.
100 uint16_t Reserved;
101 uint16_t INIT_FrameWidth_U16; // Luma width in bytes
102 uint16_t INIT_FrameHeight_U16; // Luma height in bytes
103 uint32_t INIT_TargetBitrate_U32; // target bitrate, set by application
104 uint32_t INIT_MinRate_U32; // 0
105 uint32_t INIT_MaxRate_U32; // Maximum bit rate in bits per second (bps).
106 uint32_t INIT_BufSize_U32; // buffer size
107 uint32_t INIT_InitBufFull_U32; // initial buffer fullness
108 uint32_t INIT_ProfileLevelMaxFrame_U32; // user defined. refer to AVC BRC for conformance check and correction
109 uint32_t INIT_FrameRateM_U32; // FrameRateM is the number of frames in FrameRateD
110 uint32_t INIT_FrameRateD_U32; // If driver gets this FrameRateD from VUI, it is the num_units_in_tick field (32 bits unsigned integer).
111 uint16_t INIT_GopP_U16; // number of P frames in a GOP
112 uint16_t INIT_GopB_U16; // number of B frames in a GOP
113 uint16_t INIT_MinQP_U16; // 10
114 uint16_t INIT_MaxQP_U16; // 51
115 int8_t INIT_DevThreshPB0_S8[8]; // lowdelay ? (-45, -33, -23, -15, -8, 0, 15, 25) : (-46, -38, -30, -23, 23, 30, 40, 46)
116 int8_t INIT_DevThreshVBR0_S8[8]; // lowdelay ? (-45, -35, -25, -15, -8, 0, 20, 40) : (-46, -40, -32, -23, 56, 64, 83, 93)
117 int8_t INIT_DevThreshI0_S8[8]; // lowdelay ? (-40, -30, -17, -10, -5, 0, 10, 20) : (-43, -36, -25, -18, 18, 28, 38, 46)
118 uint8_t INIT_InitQPIP; // Initial QP for I and P
119
120 uint8_t INIT_NotUseRhoDm_U8; // Reserved
121 uint8_t INIT_InitQPB; // Initial QP for B
122 uint8_t INIT_MbQpCtrl_U8; // Enable MB level QP control (global)
123 uint8_t INIT_SliceSizeCtrlEn_U8; // Enable slice size control
124 int8_t INIT_IntraQPDelta_I8[3]; // set to zero for all by default
125 int8_t INIT_SkipQPDelta_I8; // Reserved
126 int8_t INIT_DistQPDelta_I8[4]; // lowdelay ? (-5, -2, 2, 5) : (0, 0, 0, 0)
127 uint8_t INIT_OscillationQpDelta_U8; // BRCFLAG_ISVCM ? 16 : 0
128 uint8_t INIT_HRDConformanceCheckDisable_U8; // BRCFLAG_ISAVBR ? 1 : 0
129 uint8_t INIT_SkipFrameEnableFlag;
130 uint8_t INIT_TopQPDeltaThrForAdapt2Pass_U8; // =1. QP Delta threshold for second pass.
131 uint8_t INIT_TopFrmSzThrForAdapt2Pass_U8; // lowdelay ? 10 : 50. Top frame size threshold for second pass
132 uint8_t INIT_BotFrmSzThrForAdapt2Pass_U8; // lowdelay ? 10 : 200. Bottom frame size threshold for second pass
133 uint8_t INIT_QPSelectForFirstPass_U8; // lowdelay ? 0 : 1. =0 to use previous frame final QP; or =1 to use (targetQP + previousQP) / 2.
134 uint8_t INIT_MBHeaderCompensation_U8; // Reserved
135 uint8_t INIT_OverShootCarryFlag_U8; // set to zero by default
136 uint8_t INIT_OverShootSkipFramePct_U8; // set to zero by default
137 uint8_t INIT_EstRateThreshP0_U8[7]; // 4, 8, 12, 16, 20, 24, 28
138 uint8_t INIT_EstRateThreshB0_U8[7]; // 4, 8, 12, 16, 20, 24, 28
139 uint8_t INIT_EstRateThreshI0_U8[7]; // 4, 8, 12, 16, 20, 24, 28
140 uint8_t INIT_FracQPEnable_U8; // ExtendedRhoDomainEn from par file
141 uint8_t INIT_ScenarioInfo_U8; // 0: UNKNOWN, 1: DISPLAYREMOTING, 2: VIDEOCONFERENCE, 3: ARCHIVE, 4: LIVESTREAMING.
142 uint8_t INIT_StaticRegionStreamIn_U8; // should be programmed from par file
143 uint8_t INIT_DeltaQP_Adaptation_U8; // =1, should be programmed from par file
144 uint8_t INIT_MaxCRFQualityFactor_U8; // =52, should be programmed from par file
145 uint8_t INIT_CRFQualityFactor_U8; // =25, should be programmed from par file
146 uint8_t INIT_BotQPDeltaThrForAdapt2Pass_U8; // =1. QP Delta threshold for second pass.
147 uint8_t INIT_SlidingWindowSize_U8; // =30, the window size (in frames) used to compute bit rate
148 uint8_t INIT_SlidingWidowRCEnable_U8; // =0, sliding window based rate control (SWRC) disabled, 1: enabled
149 uint8_t INIT_SlidingWindowMaxRateRatio_U8; // =120, ratio between the max rate within the window and average target bitrate
150 uint8_t INIT_LowDelayGoldenFrameBoost_U8; // only for lowdelay mode, 0 (default): no boost for I and scene change frames, 1: boost
151 uint8_t RSVD2[61]; // must be zero
152 } CODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_SKL, *PCODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_SKL;
153
154 typedef struct _CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_SKL
155 {
156 uint8_t BRCFunc_U8; // =1 for Update, other values are reserved for future use
157 uint8_t RSVD[3];
158 uint32_t UPD_TARGETSIZE_U32; // refer to AVC BRC for calculation
159 uint32_t UPD_FRAMENUM_U32; // frame number
160 uint32_t UPD_PeakTxBitsPerFrame_U32; // current global target bits - previous global target bits (global target bits += input bits per frame)
161 uint32_t UPD_FrameBudget_U32; // target time counter
162 uint32_t FrameByteCount; // PAK output via MMIO
163 uint32_t TimingBudgetOverflow; // PAK output via MMIO
164 uint32_t ImgStatusCtrl; // PAK output via MMIO
165 uint32_t IPCMNonConformant; // PAK output via MMIO
166
167 uint16_t UPD_startGAdjFrame_U16[4]; // 10, 50, 100, 150
168 uint16_t UPD_MBBudget_U16[52]; // MB bugdet for QP 0 � 51.
169 uint16_t UPD_SLCSZ_TARGETSLCSZ_U16; // target slice size
170 uint16_t UPD_SLCSZ_UPD_THRDELTAI_U16[42]; // slice size threshold delta for I frame
171 uint16_t UPD_SLCSZ_UPD_THRDELTAP_U16[42]; // slice size threshold delta for P frame
172 uint16_t UPD_NumOfFramesSkipped_U16; // Recording how many frames have been skipped.
173 uint16_t UPD_SkipFrameSize_U16; // Recording the skip frame size for one frame. =NumMBs * 1, assuming one bit per mb for skip frame.
174 uint16_t UPD_StaticRegionPct_U16; // One entry, recording the percentage of static region
175 uint8_t UPD_gRateRatioThreshold_U8[7]; // 80,95,99,101,105,125,160
176 uint8_t UPD_CurrFrameType_U8; // I frame: 2; P frame: 0; B frame: 1.
177 uint8_t UPD_startGAdjMult_U8[5]; // 1, 1, 3, 2, 1
178 uint8_t UPD_startGAdjDiv_U8[5]; // 40, 5, 5, 3, 1
179 uint8_t UPD_gRateRatioThresholdQP_U8[8]; // 253,254,255,0,1,1,2,3
180 uint8_t UPD_PAKPassNum_U8; // current pak pass number
181 uint8_t UPD_MaxNumPass_U8; // 2
182 uint8_t UPD_SceneChgWidth_U8[2]; // set both to MIN((NumP + 1) / 5, 6)
183 uint8_t UPD_SceneChgDetectEn_U8; // Enable scene change detection
184 uint8_t UPD_SceneChgPrevIntraPctThreshold_U8; // =96. scene change previous intra percentage threshold
185 uint8_t UPD_SceneChgCurIntraPctThreshold_U8; // =192. scene change current intra percentage threshold
186 uint8_t UPD_IPAverageCoeff_U8; // lowdelay ? 0 : 128
187 uint8_t UPD_MinQpAdjustment_U8; // Minimum QP increase step
188 uint8_t UPD_TimingBudgetCheck_U8; // Flag indicating if kernel will check timing budget.
189 int8_t UPD_ROIQpDelta_I8[4]; // Application specified ROI QP Adjustment for Zone0, Zone1, Zone2 and Zone3.
190 uint8_t UPD_CQP_QpValue_U8; // Application specified target QP in BRC_ICQ mode
191 uint8_t UPD_CQP_FracQp_U8; // Application specified fine position in BRC_ICQ mode
192 uint8_t UPD_HMEDetectionEnable_U8; // 0: default, 1: HuC BRC kernel requires information from HME detection kernel output
193 uint8_t UPD_HMECostEnable_U8; // 0: default, 1: driver provides HME cost table
194 uint8_t UPD_DisablePFrame8x8Transform_U8; // 0: enable, 1: disable
195 uint8_t UPD_SklCabacWAEnable_U8; // 0: disable, 1: enable
196 uint8_t UPD_ROISource_U8; // =0: disable, 1: ROIMap from HME Static Region or from App dirty rectangle, 2: ROIMap from App
197 uint8_t UPD_SLCSZ_ConsertativeThreshold_U8; // =0, 0: do not set conservative threshold (suggested for video conference) 1: set conservative threshold for non-video conference
198 uint16_t UPD_TargetSliceSize_U16; // default: 1498, max target slice size from app DDI
199 uint16_t UPD_MaxNumSliceAllowed_U16; // computed by driver based on level idc
200 uint16_t UPD_SLBB_Size_U16; // second level batch buffer (SLBB) size in bytes, the input buffer will contain two SLBBs A and B, A followed by B, A and B have the same structure.
201 uint16_t UPD_SLBB_B_Offset_U16; // offset in bytes from the beginning of the input buffer, it points to the start of SLBB B, set by driver for skip frame support
202 uint16_t UPD_AvcImgStateOffset_U16; // offset in bytes from the beginning of SLBB A
203
204 /* HME distortion based QP adjustment */
205 uint16_t AveHmeDist_U16;
206 uint8_t HmeDistAvailable_U8; // 0: disabled, 1: enabled
207
208 uint16_t AdditionalFrameSize_U16; // for slice size control improvement
209
210 uint8_t RSVD2[61];
211 } CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_SKL, *PCODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_SKL;
212
213 const uint32_t CodechalVdencAvcStateG9Skl::MV_Cost_SkipBias_QPel[8] =
214 {
215 //PREDSLICE
216 0, 6, 6, 9, 10, 13, 14, 16
217 };
218
219 const uint32_t CodechalVdencAvcStateG9Skl::HmeCost[8][CODEC_AVC_NUM_QP] =
220 {
221 //mv=0
222 {
223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[13 ~25]
225 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26 ~38]
226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[39 ~51]
227 },
228 //mv<=16
229 {
230 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[13 ~25]
232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26 ~38]
233 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[39 ~51]
234 },
235 //mv<=32
236 {
237 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[0 ~12]
238 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[13 ~25]
239 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[26 ~38]
240 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[39 ~51]
241 },
242 //mv<=64
243 {
244 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[0 ~12]
245 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[13 ~25]
246 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[26 ~38]
247 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[39 ~51]
248 },
249 //mv<=128
250 {
251 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[0 ~12]
252 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[13 ~25]
253 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[26 ~38]
254 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[39 ~51]
255 },
256 //mv<=256
257 {
258 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[0 ~12]
259 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[13 ~25]
260 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[26 ~38]
261 10, 10, 10, 10, 20, 30, 40, 50, 50, 50, 50, 50, 50, //QP=[39 ~51]
262 },
263 //mv<=512
264 {
265 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[0 ~12]
266 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[13 ~25]
267 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[26 ~38]
268 20, 20, 20, 40, 60, 80, 100, 100, 100, 100, 100, 100, 100, //QP=[39 ~51]
269 },
270 //mv<=1024
271 {
272 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[0 ~12]
273 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[13 ~25]
274 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[26 ~38]
275 20, 20, 30, 50, 100, 200, 200, 200, 200, 200, 200, 200, 200, //QP=[39 ~51]
276 },
277 };
278
CodechalVdencAvcStateG9Skl(CodechalHwInterface * hwInterface,CodechalDebugInterface * debugInterface,PCODECHAL_STANDARD_INFO standardInfo)279 CodechalVdencAvcStateG9Skl::CodechalVdencAvcStateG9Skl(
280 CodechalHwInterface * hwInterface,
281 CodechalDebugInterface *debugInterface,
282 PCODECHAL_STANDARD_INFO standardInfo) : CodechalVdencAvcStateG9(hwInterface, debugInterface, standardInfo)
283 {
284 CODECHAL_ENCODE_FUNCTION_ENTER;
285
286 this->pfnGetKernelHeaderAndSize = this->EncodeGetKernelHeaderAndSize;
287 m_vdencBrcInitDmemBufferSize = sizeof(CODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_SKL);
288 m_vdencBrcUpdateDmemBufferSize = sizeof(CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_SKL);
289 }
290
~CodechalVdencAvcStateG9Skl()291 CodechalVdencAvcStateG9Skl::~CodechalVdencAvcStateG9Skl()
292 {
293 }
294
EncodeGetKernelHeaderAndSize(void * pvBinary,EncOperation Operation,uint32_t dwKrnStateIdx,void * pvKrnHeader,uint32_t * pdwKrnSize)295 MOS_STATUS CodechalVdencAvcStateG9Skl::EncodeGetKernelHeaderAndSize(void *pvBinary, EncOperation Operation, uint32_t dwKrnStateIdx, void *pvKrnHeader, uint32_t *pdwKrnSize)
296 {
297 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
298
299 CODECHAL_ENCODE_FUNCTION_ENTER;
300
301 CODECHAL_ENCODE_CHK_NULL_RETURN(pvBinary);
302 CODECHAL_ENCODE_CHK_NULL_RETURN(pvKrnHeader);
303 CODECHAL_ENCODE_CHK_NULL_RETURN(pdwKrnSize);
304
305 auto pKernelHeaderTable = (PCODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_SKL)pvBinary;
306 auto pInvalidEntry = &(pKernelHeaderTable->AVC_StaticFrameDetection) + 1;
307 uint32_t dwNextKrnOffset = *pdwKrnSize;
308
309 PCODECHAL_KERNEL_HEADER pCurrKrnHeader;
310 if (Operation == ENC_SCALING4X)
311 {
312 pCurrKrnHeader = &pKernelHeaderTable->PLY_DScale_PLY;
313 }
314 else if (Operation == ENC_SCALING2X)
315 {
316 pCurrKrnHeader = &pKernelHeaderTable->PLY_2xDScale_PLY;
317 }
318 else if (Operation == ENC_ME)
319 {
320 pCurrKrnHeader = &pKernelHeaderTable->AVC_ME_P;
321 }
322 else if (Operation == VDENC_ME)
323 {
324 pCurrKrnHeader = &pKernelHeaderTable->AVC_ME_VDENC;
325 }
326 else if (Operation == ENC_SFD)
327 {
328 pCurrKrnHeader = &pKernelHeaderTable->AVC_StaticFrameDetection;
329 }
330 else
331 {
332 CODECHAL_ENCODE_ASSERTMESSAGE("Unsupported ENC mode requested");
333 eStatus = MOS_STATUS_INVALID_PARAMETER;
334 return eStatus;
335 }
336
337 pCurrKrnHeader += dwKrnStateIdx;
338 *((PCODECHAL_KERNEL_HEADER)pvKrnHeader) = *pCurrKrnHeader;
339
340 PCODECHAL_KERNEL_HEADER pNextKrnHeader = (pCurrKrnHeader + 1);
341 if (pNextKrnHeader < pInvalidEntry)
342 {
343 dwNextKrnOffset = pNextKrnHeader->KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT;
344 }
345 *pdwKrnSize = dwNextKrnOffset - (pCurrKrnHeader->KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
346
347 return eStatus;
348 }
349
GetTrellisQuantization(PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS pParams,PCODECHAL_ENCODE_AVC_TQ_PARAMS pTrellisQuantParams)350 MOS_STATUS CodechalVdencAvcStateG9Skl::GetTrellisQuantization(PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS pParams, PCODECHAL_ENCODE_AVC_TQ_PARAMS pTrellisQuantParams)
351 {
352 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
353
354 CODECHAL_ENCODE_FUNCTION_ENTER;
355
356 CODECHAL_ENCODE_CHK_NULL_RETURN(pParams);
357 CODECHAL_ENCODE_CHK_NULL_RETURN(pTrellisQuantParams);
358
359 pTrellisQuantParams->dwTqEnabled = TrellisQuantizationEnable[pParams->ucTargetUsage];
360 pTrellisQuantParams->dwTqRounding =
361 pTrellisQuantParams->dwTqEnabled ? TrellisQuantizationRounding[pParams->ucTargetUsage] : 0;
362
363 return eStatus;
364 }
365
SetDmemHuCBrcInitReset()366 MOS_STATUS CodechalVdencAvcStateG9Skl::SetDmemHuCBrcInitReset()
367 {
368 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
369
370 CODECHAL_ENCODE_FUNCTION_ENTER;
371
372 // Setup BRC DMEM
373 MOS_LOCK_PARAMS LockFlagsWriteOnly;
374 MOS_ZeroMemory(&LockFlagsWriteOnly, sizeof(LockFlagsWriteOnly));
375 LockFlagsWriteOnly.WriteOnly = 1;
376 auto pHucVDEncBrcInitDmem = (PCODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_SKL)m_osInterface->pfnLockResource(
377 m_osInterface, &m_resVdencBrcInitDmemBuffer[m_currRecycledBufIdx], &LockFlagsWriteOnly);
378 CODECHAL_ENCODE_CHK_NULL_RETURN(pHucVDEncBrcInitDmem);
379 SetDmemHuCBrcInitResetImpl<CODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_SKL>(pHucVDEncBrcInitDmem);
380
381 CODECHAL_DEBUG_TOOL(
382 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateBrcInitParam(
383 pHucVDEncBrcInitDmem));
384 )
385
386 m_osInterface->pfnUnlockResource(m_osInterface, &m_resVdencBrcInitDmemBuffer[m_currRecycledBufIdx]);
387
388 return eStatus;
389 }
390
SetDmemHuCBrcUpdate()391 MOS_STATUS CodechalVdencAvcStateG9Skl::SetDmemHuCBrcUpdate()
392 {
393 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
394
395 CODECHAL_ENCODE_FUNCTION_ENTER;
396
397 // Program update DMEM
398 MOS_LOCK_PARAMS LockFlags;
399 MOS_ZeroMemory(&LockFlags, sizeof(MOS_LOCK_PARAMS));
400 LockFlags.WriteOnly = 1;
401 auto pHucVDEncBrcDmem = (PCODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_SKL)m_osInterface->pfnLockResource(
402 m_osInterface, &m_resVdencBrcUpdateDmemBuffer[m_currRecycledBufIdx][m_currPass], &LockFlags);
403
404 CODECHAL_ENCODE_CHK_NULL_RETURN(pHucVDEncBrcDmem);
405 SetDmemHuCBrcUpdateImpl<CODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_SKL>(pHucVDEncBrcDmem);
406
407 if (m_avcSeqParam->EnableSliceLevelRateCtrl)
408 {
409 pHucVDEncBrcDmem->UPD_SLCSZ_ConsertativeThreshold_U8 = (uint8_t)(m_avcSeqParam->RateControlMethod != RATECONTROL_VCM);
410 }
411 else
412 {
413 pHucVDEncBrcDmem->UPD_SLCSZ_ConsertativeThreshold_U8 = 0;
414 }
415
416 if (m_vdencEnabled && m_16xMeSupported && (m_pictureCodingType == P_TYPE))
417 {
418 pHucVDEncBrcDmem->HmeDistAvailable_U8 = 1;
419 }
420 else
421 {
422 pHucVDEncBrcDmem->HmeDistAvailable_U8 = 0;
423 }
424
425 pHucVDEncBrcDmem->AdditionalFrameSize_U16 = 0; // need to update from DDI
426
427 CODECHAL_DEBUG_TOOL(
428 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateBrcUpdateParam(
429 pHucVDEncBrcDmem));
430 )
431
432 m_osInterface->pfnUnlockResource(m_osInterface, &(m_resVdencBrcUpdateDmemBuffer[m_currRecycledBufIdx][m_currPass]));
433
434 return eStatus;
435 }
436
LoadMvCost(uint8_t QP)437 MOS_STATUS CodechalVdencAvcStateG9Skl::LoadMvCost(uint8_t QP)
438 {
439 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
440
441 CODECHAL_ENCODE_FUNCTION_ENTER;
442
443 m_vdEncMvCost[0] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[0]), 0x6f);
444 m_vdEncMvCost[1] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[1]), 0x6f);
445 m_vdEncMvCost[2] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[2]), 0x6f);
446 m_vdEncMvCost[3] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[3]), 0x6f);
447 m_vdEncMvCost[4] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[4]), 0x6f);
448 m_vdEncMvCost[5] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[5]), 0x6f);
449 m_vdEncMvCost[6] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[6]), 0x6f);
450 m_vdEncMvCost[7] = Map44LutValue((uint32_t)(MV_Cost_SkipBias_QPel[7]), 0x6f);
451
452 return eStatus;
453 }
454
LoadHmeMvCost(uint8_t QP)455 MOS_STATUS CodechalVdencAvcStateG9Skl::LoadHmeMvCost(uint8_t QP)
456 {
457 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
458
459 CODECHAL_ENCODE_FUNCTION_ENTER;
460
461 m_vdEncHmeMvCost[0] = Map44LutValue(*(HmeCost[0] + QP), 0x6f);
462 m_vdEncHmeMvCost[1] = Map44LutValue(*(HmeCost[1] + QP), 0x6f);
463 m_vdEncHmeMvCost[2] = Map44LutValue(*(HmeCost[2] + QP), 0x6f);
464 m_vdEncHmeMvCost[3] = Map44LutValue(*(HmeCost[3] + QP), 0x6f);
465 m_vdEncHmeMvCost[4] = Map44LutValue(*(HmeCost[4] + QP), 0x6f);
466 m_vdEncHmeMvCost[5] = Map44LutValue(*(HmeCost[5] + QP), 0x6f);
467 m_vdEncHmeMvCost[6] = Map44LutValue(*(HmeCost[6] + QP), 0x6f);
468 m_vdEncHmeMvCost[7] = Map44LutValue(*(HmeCost[7] + QP), 0x6f);
469
470 return eStatus;
471 }
472
LoadHmeMvCostTable(PCODEC_AVC_ENCODE_SEQUENCE_PARAMS pSeqParams,uint8_t HMEMVCostTable[8][42])473 MOS_STATUS CodechalVdencAvcStateG9Skl::LoadHmeMvCostTable(PCODEC_AVC_ENCODE_SEQUENCE_PARAMS pSeqParams, uint8_t HMEMVCostTable[8][42])
474 {
475 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
476
477 CODECHAL_ENCODE_FUNCTION_ENTER;
478
479 const uint32_t(*puiVdencHmeCostTable)[CODEC_AVC_NUM_QP];
480 puiVdencHmeCostTable = HmeCost;
481
482 for (int i = 0; i < 8; i++)
483 {
484 for (int j = 0; j < 42; j++)
485 {
486 HMEMVCostTable[i][j] = Map44LutValue(*(puiVdencHmeCostTable[i] + j + 10), 0x6f);
487 }
488 }
489
490 return eStatus;
491 }
492
493 #if USE_CODECHAL_DEBUG_TOOL
PopulateBrcInitParam(void * cmd)494 MOS_STATUS CodechalVdencAvcStateG9Skl::PopulateBrcInitParam(
495 void *cmd)
496 {
497 CODECHAL_DEBUG_FUNCTION_ENTER;
498
499 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
500
501 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
502 {
503 return MOS_STATUS_SUCCESS;
504 }
505
506 PCODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_SKL dmem = (PCODECHAL_VDENC_AVC_BRC_INIT_DMEM_G9_SKL)cmd;
507
508 if (m_pictureCodingType == I_TYPE)
509 {
510 m_avcPar->MBBRCEnable = m_mbBrcEnabled;
511 m_avcPar->MBRC = m_mbBrcEnabled;
512 m_avcPar->BitRate = dmem->INIT_TargetBitrate_U32;
513 m_avcPar->InitVbvFullnessInBit = dmem->INIT_InitBufFull_U32;
514 m_avcPar->MaxBitRate = dmem->INIT_MaxRate_U32;
515 m_avcPar->VbvSzInBit = dmem->INIT_BufSize_U32;
516 m_avcPar->UserMaxFrame = dmem->INIT_ProfileLevelMaxFrame_U32;
517 m_avcPar->SlidingWindowEnable = dmem->INIT_SlidingWidowRCEnable_U8;
518 m_avcPar->SlidingWindowSize = dmem->INIT_SlidingWindowSize_U8;
519 m_avcPar->SlidingWindowMaxRateRatio = dmem->INIT_SlidingWindowMaxRateRatio_U8;
520 m_avcPar->LowDelayGoldenFrameBoost = dmem->INIT_LowDelayGoldenFrameBoost_U8;
521 m_avcPar->TopQPDeltaThrforAdaptive2Pass = dmem->INIT_TopQPDeltaThrForAdapt2Pass_U8;
522 m_avcPar->BotQPDeltaThrforAdaptive2Pass = dmem->INIT_BotQPDeltaThrForAdapt2Pass_U8;
523 m_avcPar->TopFrmSzPctThrforAdaptive2Pass = dmem->INIT_TopFrmSzThrForAdapt2Pass_U8;
524 m_avcPar->BotFrmSzPctThrforAdaptive2Pass = dmem->INIT_BotFrmSzThrForAdapt2Pass_U8;
525 m_avcPar->MBHeaderCompensation = dmem->INIT_MBHeaderCompensation_U8;
526 m_avcPar->QPSelectMethodforFirstPass = dmem->INIT_QPSelectForFirstPass_U8;
527 m_avcPar->MBQpCtrl = (dmem->INIT_MbQpCtrl_U8 > 0) ? true : false;
528 m_avcPar->QPMax = dmem->INIT_MaxQP_U16;
529 m_avcPar->QPMin = dmem->INIT_MinQP_U16;
530 m_avcPar->HrdConformanceCheckDisable = (dmem->INIT_HRDConformanceCheckDisable_U8 > 0) ? true : false;
531 m_avcPar->StreamInStaticRegion = dmem->INIT_StaticRegionStreamIn_U8;
532 ;
533 m_avcPar->ScenarioInfo = dmem->INIT_ScenarioInfo_U8;
534 ;
535 }
536
537 return MOS_STATUS_SUCCESS;
538 }
539
PopulateBrcUpdateParam(void * cmd)540 MOS_STATUS CodechalVdencAvcStateG9Skl::PopulateBrcUpdateParam(
541 void *cmd)
542 {
543 CODECHAL_DEBUG_FUNCTION_ENTER;
544
545 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
546
547 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
548 {
549 return MOS_STATUS_SUCCESS;
550 }
551
552 PCODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_SKL dmem = (PCODECHAL_VDENC_AVC_BRC_UPDATE_DMEM_G9_SKL)cmd;
553
554 if (m_pictureCodingType == I_TYPE)
555 {
556 m_avcPar->EnableMultipass = (dmem->UPD_MaxNumPass_U8 > 0) ? true : false;
557 m_avcPar->MaxNumPakPasses = dmem->UPD_MaxNumPass_U8;
558 m_avcPar->SceneChgDetectEn = (dmem->UPD_SceneChgDetectEn_U8 > 0) ? true : false;
559 m_avcPar->SceneChgPrevIntraPctThresh = dmem->UPD_SceneChgPrevIntraPctThreshold_U8;
560 m_avcPar->SceneChgCurIntraPctThresh = dmem->UPD_SceneChgCurIntraPctThreshold_U8;
561 m_avcPar->SceneChgWidth0 = dmem->UPD_SceneChgWidth_U8[0];
562 m_avcPar->SceneChgWidth1 = dmem->UPD_SceneChgWidth_U8[1];
563 m_avcPar->SliceSizeThr = dmem->UPD_SLCSZ_TARGETSLCSZ_U16;
564 m_avcPar->SliceMaxSize = dmem->UPD_TargetSliceSize_U16;
565 }
566 else if (m_pictureCodingType == P_TYPE)
567 {
568 m_avcPar->Transform8x8PDisable = (dmem->UPD_DisablePFrame8x8Transform_U8 > 0) ? true : false;
569 }
570
571 return MOS_STATUS_SUCCESS;
572 }
573
PopulateEncParam(uint8_t meMethod,void * cmd)574 MOS_STATUS CodechalVdencAvcStateG9Skl::PopulateEncParam(
575 uint8_t meMethod,
576 void *cmd)
577 {
578 CODECHAL_DEBUG_FUNCTION_ENTER;
579
580 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
581
582 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
583 {
584 return MOS_STATUS_SUCCESS;
585 }
586
587 uint8_t *data = nullptr;
588 MOS_LOCK_PARAMS lockFlags;
589 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
590 lockFlags.ReadOnly = 1;
591
592 if (m_vdencBrcEnabled)
593 {
594 // BRC case: VDENC IMG STATE is updated by HuC FW
595 data = (uint8_t *)m_osInterface->pfnLockResource(m_osInterface, &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx], &lockFlags);
596 data = data + mhw_vdbox_mfx_g9_skl::MFX_AVC_IMG_STATE_CMD::byteSize;
597 }
598 else
599 {
600 // CQP case: VDENC IMG STATE is updated by driver or SFD kernel
601 if (!m_staticFrameDetectionInUse)
602 {
603 data = m_batchBufferForVdencImgStat[m_currRecycledBufIdx].pData;
604 data = data + mhw_vdbox_mfx_g9_skl::MFX_AVC_IMG_STATE_CMD::byteSize;
605 }
606 else
607 {
608 data = (uint8_t *)m_osInterface->pfnLockResource(m_osInterface, &m_resVdencSfdImageStateReadBuffer, &lockFlags);
609 }
610 }
611
612 CODECHAL_DEBUG_CHK_NULL(data);
613
614 mhw_vdbox_vdenc_g9_skl::VDENC_IMG_STATE_CMD vdencCmd;
615 vdencCmd = *(mhw_vdbox_vdenc_g9_skl::VDENC_IMG_STATE_CMD *)(data);
616
617 if (m_pictureCodingType == I_TYPE)
618 {
619 m_avcPar->BlockBasedSkip = vdencCmd.DW4.BlockBasedSkipEnabled;
620 }
621 else if (m_pictureCodingType == P_TYPE)
622 {
623 m_avcPar->SubPelMode = vdencCmd.DW4.SubPelMode;
624 m_avcPar->FTQBasedSkip = vdencCmd.DW4.ForwardTransformSkipCheckEnable;
625 m_avcPar->BiMixDisable = vdencCmd.DW1.BidirectionalMixDisable;
626 m_avcPar->SurvivedSkipCost = (vdencCmd.DW8.NonSkipZeroMvCostAdded << 1) + vdencCmd.DW8.NonSkipMbModeCostAdded;
627 m_avcPar->UniMixDisable = vdencCmd.DW2.UnidirectionalMixDisable;
628 m_avcPar->VdencExtPakObjDisable = !vdencCmd.DW1.VdencExtendedPakObjCmdEnable;
629 m_avcPar->PPMVDisable = vdencCmd.DW34.PpmvDisable;
630 }
631
632 if (data)
633 {
634 if (m_vdencBrcEnabled)
635 {
636 m_osInterface->pfnUnlockResource(
637 m_osInterface,
638 &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx]);
639 }
640 else
641 {
642 if (m_staticFrameDetectionInUse)
643 {
644 m_osInterface->pfnUnlockResource(
645 m_osInterface,
646 &m_resVdencSfdImageStateReadBuffer);
647 }
648 }
649 }
650
651 return MOS_STATUS_SUCCESS;
652 }
653
PopulatePakParam(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER secondLevelBatchBuffer)654 MOS_STATUS CodechalVdencAvcStateG9Skl::PopulatePakParam(
655 PMOS_COMMAND_BUFFER cmdBuffer,
656 PMHW_BATCH_BUFFER secondLevelBatchBuffer)
657 {
658 CODECHAL_DEBUG_FUNCTION_ENTER;
659
660 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
661
662 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
663 {
664 return MOS_STATUS_SUCCESS;
665 }
666
667 uint8_t *data = nullptr;
668 MOS_LOCK_PARAMS lockFlags;
669 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
670 lockFlags.ReadOnly = 1;
671
672 if (cmdBuffer != nullptr)
673 {
674 data = (uint8_t*)(cmdBuffer->pCmdPtr - (mhw_vdbox_mfx_g9_skl::MFX_AVC_IMG_STATE_CMD::byteSize / sizeof(uint32_t)));
675 }
676 else if (secondLevelBatchBuffer != nullptr)
677 {
678 data = secondLevelBatchBuffer->pData;
679 }
680 else
681 {
682 data = (uint8_t *)m_osInterface->pfnLockResource(m_osInterface, &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx], &lockFlags);
683 }
684
685 CODECHAL_DEBUG_CHK_NULL(data);
686
687 mhw_vdbox_mfx_g9_skl::MFX_AVC_IMG_STATE_CMD mfxCmd;
688 mfxCmd = *(mhw_vdbox_mfx_g9_skl::MFX_AVC_IMG_STATE_CMD *)(data);
689
690 if (m_pictureCodingType == I_TYPE)
691 {
692 m_avcPar->TrellisQuantizationEnable = mfxCmd.DW5.TrellisQuantizationEnabledTqenb;
693 m_avcPar->EnableAdaptiveTrellisQuantization = mfxCmd.DW5.TrellisQuantizationEnabledTqenb;
694 m_avcPar->TrellisQuantizationRounding = mfxCmd.DW5.TrellisQuantizationRoundingTqr;
695 m_avcPar->TrellisQuantizationChromaDisable = mfxCmd.DW5.TrellisQuantizationChromaDisableTqchromadisable;
696 m_avcPar->ExtendedRhoDomainEn = mfxCmd.DW16_17.ExtendedRhodomainStatisticsEnable;
697 }
698
699 if (data && (cmdBuffer == nullptr) && (secondLevelBatchBuffer == nullptr))
700 {
701 m_osInterface->pfnUnlockResource(
702 m_osInterface,
703 &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx]);
704 }
705
706 return MOS_STATUS_SUCCESS;
707 }
708 #endif
709